Vlsi Front-End Desgin
Vlsi Front-End Desgin
Vlsi Front-End Desgin
BY
venkatesh.n
INTRODUCTION
VERY LARGE SCALE INTERGRATION is the process of creating integrated circuits by combining
thousands of transistors into a single chip.
The Microprocessor is a VLSI device
VLSI Industry in INDIA started in early 80s with Texas Instruments (TI) and ST Microelectronics setting
up their design centers.
The size and cost of circuits is reduced by VLSI by making 1000 of circuits with diodes and resistance
to a single chip
VLSI Field is broadly classified into two Ends
VLSI Design Flow
Design Analysis
Design Specification
Verilog/
Ii Synthesis
VHDL
Library
Simulation
Standad
Cell
Library Timing Analysis
LookUp
Table Place & Route
Extraction
Tech
File for Tech
Layout Files to
Extract
Verification
Steps in Front-End:
Enter the design in one standard format (which EDA tools can understand)
Analyzing the requirements and high level design (identifying various blocks in design)
RTL design evolving the necessary micro architecture for the each block
VHDL, Verilog, other HDLs, Netlist etc.
Developing necessary techbenches for functional verification.
Simulation and model verification using standard simulators
Integration of all the blocks and top level simulation.
Design
Design Analysis Analysis
Design Specification
This is a very crucial step in digital design where
Design Implementation using HDL
the design functionality is stated.
Synthesis
Like if we are making a processor,
Simulation what type of functionality is expected??
Timing Analysis
Extraction
Verification
Design Specification
Design Analysis
Verification
HDL(Hardware Descriptive Language)
Design Analysis
Design Specification
Hardware Description Language is used to run the simulations.
Design Implementation using HDL It is very expensive to build the entire chip and then verify the
performance of the architecture. Imagine if after designing a
Synthesis
chip for a whole year, the chip fabricated, does not come even
Simulation closer to the stated
Timing Analysis specifications.
At this time we can see the design in the form of Source Codes.
Synthesis
If you notice, most of the digital designs are build up of some
basic elements or components like gates, registers, counters,
Simulation
adders, subtractors, comparators, RAM, ROM etc.
Timing Analysis
Verification
Synthesis (Contd.)
Standard Cell Library is the collection of such building blocks which
comprises most of the digital designs.These cell libraries are
fabrication technology specific.
After the RTL simulation, the HDL, code is taken as input by Synthesis
Tool and converted to Gate level.At this stage that the digital design
becomes dependent on the fabrication process.
At the end of this stage, we have the logic circuit I.e. in terms of
gates and memories.
Synthesis ( Contd.)
What synthesis does is , when it encounters a specific construct in HDL it
replaces it with the corresponding Standard Cell Component from the library
to build the entire design.
Extraction
Verification
Timing Analysis
Design Analysis
RTL and Gate Level simulation doesn’t take into account
Design Specification the physical time delay in signal propagation from one
Design Implementation using HDL
device to another and through the device.
Verification Delays are in the form of rise time, fall time and turn off
time delays.
Timing Analysis (Contd.)
Most of the digital designs employ concept of timing by using clocks.This
makes the circuits synchronous.
In timing analysis, using Delay Lookup Tables, all the inputs and outputs of
components are verified with timing introduced.
Verification
Verification is done before Fabrication
Verification is to check whether a block is designed to its functional
specification. Once the functionality is verified, the design can be
sent out to fabrication
SystemVerilog, OpenVera, e, and SystemC are the most commonly
used HVLs
The most commonly used Verification Methodologies are
OVM(Open Verification Methodology)
UVM(Universal Verification Methodology)
Introduction to FPGA Technology:
FPGAs have gone from being simple glue logic chips to actually replacing custom
application-specific integrated circuits (ASICs) and processors for signal processing and
control applications
At the highest level, FPGAs are reprogrammable silicon chips
Partitioning
Floorplanning
Placement
Routing
Fabrication
DESIGN CONSTRAINTS
Main Consideration:
Timing analysis
Power analysis
Area analysis
Tools used:
Synopsys
Cadence
Magma
Tanner
Mentor Graphics.
DSCH&Microwind
TECHNOLOGY
IC Technology
A Sample of Integrated Circuit technologies:
MOS
CMOS
PMOS-only
NMOS-only
Bipolar
Transistor-transistor logic (TTL)
I ntegrated Injection Logic (I 2 L)
Technology generation
Technology Generation is defined by—
Technologies:
250nm (1997)
180nm (1999)
130nm (2002)
100nm (2005)
70nm (2008)
45nm (2012)
FLOORPLANNING
The first step in the physical design flow is Floorplanning.
The floorplanning problem is to plan the positions and shapes of the modules at the
beginning of the design cycle to optimize the circuit performance
PARTITIONING
Partitioning is a process of dividing the chip into small blocks.
Global routing allocates routing resources that are used for connections.
Detailed routing assigns routes to specific metal layers and routing tracks within
the global routing resources
Extraction and Timing Analysis
After global routing and detailed routing, information of the nets can be
extracted and delays can be analyzed.
If some nets fail to meet their timing budget, detailed routing and/or
global
routing needs to be repeated.
Physical Verification
Physical verification checks the correctness of the generated layout design. This includes
Is consistent with the original netlist – Layout vs. Schematic (LVS)
FINAL LAYOUT
At sub-micron level
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Future of VLSI:
In the last five years VLSI industry has grown five times faster than the global average
IC Industry is the second fastest growing industry in India (23%) after the Automation
industry (26%).
There are certain key issues that serve as active areas of research and are constantly
improving as the field continues to mature.
Simply saying,
As long as human exists,
ASIC should exist
PURPOSE OF TRAINING:
The first seats that are to be filled in any engineering college is electronics.
But only 3% of the students are joining in their core side,Remaining are hired
for software and IT jobs.
CAD Engineer
To manage the license and EDA tools
Evaluates EDA solutions and methodologies
Integrates EDA tools and develops flow
Marketing & Sales - Promotes the brand and sells the products.
FrontEnd Companies in India:
BANGALORE HYDERABAD NEW DELHI
OXYS Technologies Pvt.Ltd AIZYC Technologies
KARACHI
GreenMil International Kedhar Solutions
PROCAD Semcon Technologies Pvt.Ltd
PUNE
AECTL MindTree Ltd Thotaka Technologies Pvt.Ltd NOIDA
IPSuper Market TIM Institute of Info Tech & more
COIMBATORE
Kanta Consultancy Services
CHENNAI NAGPUR
Accel IT Academy
ARE-Design
Qmax Systems Pvt.Ltd GUJARAT
K7 Computing
Coreel Technologies MUMBAI
HighTech Park
TIIT Pvt.Ltd
SAS TECH
Cochin
RFIC Technologies
Caravel Info Systems Pvt.Ltd
MINI ATE Systems Pvt.Ltd CHANDIGARH
Kawasaki Microelectronics GURGAON
Park Controls & Communication Ltd
Few Bottlenecks:
Lack of Skilled Professionals in this domain
Conventional Methods of Education in Indian Academy
Lack of good quality faculty in Indian Academy
Industry – Academics gap
Low employability rate
Queries…?
THANK YOU…..