Vlsi Front-End Desgin

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ASIC DESIGN

BY
venkatesh.n
INTRODUCTION
 VERY LARGE SCALE INTERGRATION is the process of creating integrated circuits by combining
thousands of transistors into a single chip.
 The Microprocessor is a VLSI device
 VLSI Industry in INDIA started in early 80s with Texas Instruments (TI) and ST Microelectronics setting
up their design centers.
 The size and cost of circuits is reduced by VLSI by making 1000 of circuits with diodes and resistance
to a single chip
 VLSI Field is broadly classified into two Ends
VLSI Design Flow
Design Analysis

Design Specification

Design Implementation using HDL

Verilog/
Ii Synthesis
VHDL
Library

Simulation
Standad
Cell
Library Timing Analysis

LookUp
Table Place & Route

Extraction
Tech
File for Tech
Layout Files to
Extract
Verification
Steps in Front-End:
 Enter the design in one standard format (which EDA tools can understand)
 Analyzing the requirements and high level design (identifying various blocks in design)
 RTL design evolving the necessary micro architecture for the each block
 VHDL, Verilog, other HDLs, Netlist etc.
 Developing necessary techbenches for functional verification.
 Simulation and model verification using standard simulators
 Integration of all the blocks and top level simulation.
Design
Design Analysis Analysis
Design Specification
This is a very crucial step in digital design where
Design Implementation using HDL
the design functionality is stated.

Synthesis
Like if we are making a processor,
Simulation what type of functionality is expected??
Timing Analysis

Place & Route

Extraction

Verification
Design Specification
Design Analysis

This step involved stating in definite terms the performance


Design Specification
of the chip.
Design Implementation using HDL
Like if we are making a processor, data size, processor speed,
Synthesis special functions, power etc. is clearly stated at this point.
Simulation
Also somewhat it is decided, the way to implement the
design.
Timing Analysis

So, it deals with architectural part of the design at highest


Place & Route
level possible. Based on these foundation , the whole
Extraction design is built

Verification
HDL(Hardware Descriptive Language)
Design Analysis

Design Specification
Hardware Description Language is used to run the simulations.

Design Implementation using HDL It is very expensive to build the entire chip and then verify the
performance of the architecture. Imagine if after designing a
Synthesis
chip for a whole year, the chip fabricated, does not come even
Simulation closer to the stated
Timing Analysis specifications.

Place & Route Hardware description languages provides a way to implement


a design without going into much architecture, simulate and
Extraction
verify the design output and functionality.
Verification
HDL (contd.)
For eg. rather than building a mux design in hardware, we can write verilog
code and verify the output at higher level of abstraction.
Examples of HDL: VHDL, Verilog HDL

At this time we can see the design in the form of Source Codes.

It seems more of the software visualization of the circuit.

The simulated code is taken to Synthesis to generate the Logic Circuit.


Design Analysis
Synthesis
Imagine the use of K-Maps and Truth Tables to make and
Design Specification
implement a digital design.
Design Implementation using HDL

Synthesis
If you notice, most of the digital designs are build up of some
basic elements or components like gates, registers, counters,
Simulation
adders, subtractors, comparators, RAM, ROM etc.
Timing Analysis

Place & Route


It forms the fundamentals of Logic Synthesis using EDA
tools.
Extraction

Verification
Synthesis (Contd.)
Standard Cell Library is the collection of such building blocks which
comprises most of the digital designs.These cell libraries are
fabrication technology specific.

After the RTL simulation, the HDL, code is taken as input by Synthesis
Tool and converted to Gate level.At this stage that the digital design
becomes dependent on the fabrication process.

At the end of this stage, we have the logic circuit I.e. in terms of
gates and memories.
Synthesis ( Contd.)
What synthesis does is , when it encounters a specific construct in HDL it
replaces it with the corresponding Standard Cell Component from the library
to build the entire design.

Like if we use a for loop , it gets converted to counter and a combinational


circuit.

The output of synthesis is a gatelevel netlist.Netlist is an ASCII file which


enlists and indicates the devices and the interconnections between them.
RTL Schematic
 A complete Register Transfer Level Schematic can viewed after
making a Fruitful Front-End Design.
Sample view:
Design Analysis
Simulation
Design Specification After the netlist is generated as part of synthesis,
Design Implementation using HDL
this netlist is simulated to verify the functionality
of this gate level implementation of design.
Synthesis

Simulation Till this level we just dealt with functionality part.


Timing Analysis
Now each step onward deals with performance
part too.
Place & Route

Extraction

Verification
Timing Analysis
Design Analysis
RTL and Gate Level simulation doesn’t take into account
Design Specification the physical time delay in signal propagation from one
Design Implementation using HDL
device to another and through the device.

Synthesis This time delay is dependent on the fabrication process


Simulation adopted.
Timing Analysis
Each component in standard cell library is associated with
Place & Route some specific delay.Delay Lookup Tables list the delays
Extraction
associated with the components.

Verification Delays are in the form of rise time, fall time and turn off
time delays.
Timing Analysis (Contd.)
Most of the digital designs employ concept of timing by using clocks.This
makes the circuits synchronous.

Consider an AND gate with two inputs,x and y.


If at time t = 1 ns, x is available,and y comes 1 ns later, what would be the
output. This mismatch in timing leads to erroneous performance of design.

In timing analysis, using Delay Lookup Tables, all the inputs and outputs of
components are verified with timing introduced.
Verification
 Verification is done before Fabrication
 Verification is to check whether a block is designed to its functional
specification. Once the functionality is verified, the design can be
sent out to fabrication
 SystemVerilog, OpenVera, e, and SystemC are the most commonly
used HVLs
 The most commonly used Verification Methodologies are
 OVM(Open Verification Methodology)
 UVM(Universal Verification Methodology)
Introduction to FPGA Technology:
 FPGAs have gone from being simple glue logic chips to actually replacing custom
application-specific integrated circuits (ASICs) and processors for signal processing and
control applications
 At the highest level, FPGAs are reprogrammable silicon chips

• Xilinx and Altera are the current FPGA market


leaders
• Competitors include
 Lattice Semiconductor
 Achronix
 Actel
 QuickLogic
Back-End Design
Introduction
• Manual (Human) design can occur with small number
of transistors
• As number of transistors increase through SSI and
VLSI, the amount of evaluation and decision making
would become overwhelming (Trade-offs)
 Maintaining performance requirements (Power / Speed /
Area)
 Design and implementation times become impractical

• How does one create a complex electronic design


consisting of millions of transistors?

Automate the Process using Computer-Aided Design (CAD) Tools


Physical Design
Circuit
Design

Partitioning

Floorplanning

Placement

Routing

Fabrication
DESIGN CONSTRAINTS
Main Consideration:
Timing analysis
Power analysis
Area analysis

Tools used:
Synopsys
Cadence
Magma
Tanner
Mentor Graphics.
DSCH&Microwind
TECHNOLOGY
IC Technology
A Sample of Integrated Circuit technologies:
MOS
CMOS
PMOS-only
NMOS-only
 
Bipolar
Transistor-transistor logic (TTL)
I ntegrated Injection Logic (I 2 L)
Technology generation
Technology Generation is defined by—

Feature size: Size of the smallest features on an IC, usually the


length of the transistor channel.
The width of the gate.

Technologies:
250nm (1997)
180nm (1999)
130nm (2002)
100nm (2005)
70nm (2008)
45nm (2012)
FLOORPLANNING
The first step in the physical design flow is Floorplanning.

Floorplanning is the process of identifying structures that should be placed close


together, and allocating space for them.

The floorplanning problem is to plan the positions and shapes of the modules at the
beginning of the design cycle to optimize the circuit performance
PARTITIONING
Partitioning is a process of dividing the chip into small blocks.

Partitioning is mainly to separate different functional blocks and also to


make placement and routing easier.
Routing
There are two types of routing in the physical design process, global routing and
detailed routing.

Global routing allocates routing resources that are used for connections.

Detailed routing assigns routes to specific metal layers and routing tracks within
the global routing resources
Extraction and Timing Analysis
After global routing and detailed routing, information of the nets can be
extracted and delays can be analyzed.

If some nets fail to meet their timing budget, detailed routing and/or
global
routing needs to be repeated.
Physical Verification

Physical verification checks the correctness of the generated layout design. This includes

verifying that the layout.

Complies with all technology requirements – Design Rule Checking (DRC).

Is consistent with the original netlist – Layout vs. Schematic (LVS)
FINAL LAYOUT

This is sent to foundry for fabrication.


Physical Design:
1. FloorPlanning : Architect’s job

2. Placement : Builder’s job

3. Routing : Electrician’s job

At sub-micron level

32
Future of VLSI:
 In the last five years VLSI industry has grown five times faster than the global average
 IC Industry is the second fastest growing industry in India (23%) after the Automation
industry (26%).
 There are certain key issues that serve as active areas of research and are constantly
improving as the field continues to mature.

Simply saying,
As long as human exists,
ASIC should exist
PURPOSE OF TRAINING:
 The first seats that are to be filled in any engineering college is electronics.

 Every year an average of 30K are graduating in electronics.This is because of


the passion towards the electronics.

 But only 3% of the students are joining in their core side,Remaining are hired
for software and IT jobs.

Is this mean that there are no jobs in electronics or low salaries?


Scope of Employment:
 India needs 7.5 Lakh skilled professionals in this industry by 2015
 Anyone who is planning to start his career in the semiconductor industry needs
to have better understanding of the jobs and growth
 Though VLSI is treated as hardware design, VLSI engineers design the chips
using HDL’s,as Software Programmers
 Industries mainly look for your IQ and programming skills but not Domain and
Academic Percentage
 There are plenty of job opportunities in the semiconductor industries. One needs
to have better understanding of the job titles and job profiles,then one can
decide his/her strengths and choose the right job accordingly
Design Engineer  Verification kinds:
Front-end designer - ASIC/FPGA  Front-end verification – simulation
Back-end designer  Acceleration/Emulation – Validation
AMS designer(Analog mixed Signal)
 Hardware Software co-verification
DFT engineer(Design for Test)
 Product validation - Validating the EDA tools
PCB designer - Board design
Library developer  Behavioral Modeling - modeling the design
 Verification IP implementation - TB developers

 CAD Engineer 
 To manage the license and EDA tools
 Evaluates EDA solutions and methodologies
 Integrates EDA tools and develops flow

 Application Engineer - Interface between the R&D and customers,


Promotes EDA solutions
 Field Application Engineer - Pre-sales
 Corporate Application Engineer - Post-sales
 Application Consultants

 Marketing & Sales - Promotes the brand and sells the products.
FrontEnd Companies in India:
 BANGALORE  HYDERABAD  NEW DELHI
 OXYS Technologies Pvt.Ltd  AIZYC Technologies
 KARACHI
 GreenMil International  Kedhar Solutions
 PROCAD  Semcon Technologies Pvt.Ltd
 PUNE
 AECTL MindTree Ltd  Thotaka Technologies Pvt.Ltd  NOIDA
IPSuper Market TIM Institute of Info Tech & more
 
 COIMBATORE
 Kanta Consultancy Services
 CHENNAI  NAGPUR
 Accel IT Academy
 ARE-Design
 Qmax Systems Pvt.Ltd  GUJARAT
 K7 Computing
 Coreel Technologies  MUMBAI
 HighTech Park
 TIIT Pvt.Ltd
 SAS TECH
 Cochin
 RFIC Technologies
 Caravel Info Systems Pvt.Ltd
 MINI ATE Systems Pvt.Ltd  CHANDIGARH
 Kawasaki Microelectronics  GURGAON
 Park Controls & Communication Ltd
Few Bottlenecks:
 Lack of Skilled Professionals in this domain
 Conventional Methods of Education in Indian Academy
 Lack of good quality faculty in Indian Academy
 Industry – Academics gap
 Low employability rate
Queries…?
THANK YOU…..

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