Carry Save Adder VHDL Code
Carry Save Adder VHDL Code
Carry Save Adder VHDL Code
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entity carry_save_adder is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
C : in STD_LOGIC_VECTOR (3 downto 0);
S : OUT STD_LOGIC_VECTOR (4 downto 0);
Cout : OUT STD_LOGIC);
end carry_save_adder;
component full_adder_vhdl_code
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end component;
-- Intermediate signal
signal X,Y: STD_LOGIC_VECTOR(3 downto 0);
signal C1,C2,C3: STD_LOGIC;
begin
-- Carry save adder block
FA1: full_adder_vhdl_code PORT MAP(A(0),B(0),C(0),S(
FA2: full_adder_vhdl_code PORT MAP(A(1),B(1),C(1),Y(
FA3: full_adder_vhdl_code PORT MAP(A(2),B(2),C(2),Y(
FA4: full_adder_vhdl_code PORT MAP(A(3),B(3),C(3),Y(
end Behavioral;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Tb_carry_save IS
END Tb_carry_save;
--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0'
signal B : std_logic_vector(3 downto 0) := (others => '0'
signal C : std_logic_vector(3 downto 0) := (others => '0'
--Outputs
signal S : std_logic_vector(4 downto 0);
signal Cout : std_logic;
BEGIN
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
A <= "1100";
B <= "1101";
C <= "1110";
wait;
end process;
END;
Output Waveform for Carry Save adder
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