Low Noise Amplifier Design

Dr Peter King
info@rfconsult.uk

www.rfconsult.uk :: RF design + consultancy, module build + test and training services

www.researchrf.com :: Low Cost RF Power Amplifier Solutions
www.idealnetworks.net :: IDEAL Networks Data Cable, Network and Telecom Testers
 Author’s Background
• 25 years’ RF system and circuit level R+D experience:
– 11 years’ mobile phone basestations/terminals
– 3 years’ military radios/infrastructure
– 4 years’ aircraft radios
– 3 years’ test equipment
– 4 years’ satcom research project management
• Education:
– PhD (Surrey, 2007) LMS-MIMO Radio Propagation Modelling and Measurement
– MSc (Surrey, 2002) Mobile & Satellite Communications
– BSc (Essex, 1989) Electronic Engineering (Telecommunications)
• Currently designing Cable Certifiers at IDEAL Networks, RF Power Amps at
Research RF and providing RF consultancy at RF Consult. Own RF lab
comprising Keysight RF test equipment and software tools (ADS W2207B,
Matlab/Simulink, SPICE, MathCad, Excel).
 Lecture Outline
• LNA in System: Cascaded NF, IP3
• Example Specification
• Device Selection
• DC biasing
• NF / Gain circles / Stability
• Simultaneous Noise / Conjugate Match
• Distributed Matching
• Linear Performance
• Non-Linear Performance
• Design for Manufacture
 LNA in System
• Cascaded Noise Figure

• Cascaded Intercept Point

 Example LNA Specifications
• Frequency Range (1980-2000MHz)
• Gain (14dB) and Gain Ripple (+/- 2dB)
• Noise Figure (<1dB)
• OIP3 (>20dBm)
• Stability (unconditionally stable)
• Input Match (RL < -14dB)
• Output Match (RL < -14dB)
 Device Selection
• Google search
finds suitable
devices from
Avago
Technologies.
• ATF-58143
looks good
 ADS model of ATF-58143
• First we import the model using File>Unarchive
 Finding DC bias point
• ADS>DesignGuide>Amplifier>FET_IV_Gm_PowerCalcs
Device Characteristics
 Optimum Source/Load Impedance
• ADS>DesignGuide>Amplifier>FET_SP_NF_Match_Circ
V_DC
L
I-V Curve plus L1
SRC1
Vdc=VDS
S-Parameters and L=1.0 mH
Noise Figure versus R=
Bias Voltages
Var
I_Probe Eqn VAR
IDS VAR4
Sind=1.0 {t}

C Term
C1 Term2
C=1.0 uF Num=2
C L
C2 L2 Z=Z0
C=1.0 uF L=1.0 mH ATF58143
Term L L
R= I__22
Term1 L3 L4
Num=1 L=Sind nH L=Sind nH
V_DC
Z=Z0 R= R=
SRC3
Var VAR
Vdc=VGS V Eqn
VAR1
VDS = 0 V
VGS = 0 V

PARAMETER SWEEP PARAMETER SWEEP S-PARAMETERS DC

ParamSweep ParamSweep S_Param DC
Sweep1 Sweep2 SP1 DC1
SweepVar="VGS" SweepVar="VDS" CalcNoise=yes SweepVar="VDS"
SimInstanceName[1]="DC1" SimInstanceName[1]="SP1" Freq=2.0 GHz Start=VDSmin
SimInstanceName[2]="Sweep2" SimInstanceName[2]= Stop=VDSmax
SimInstanceName[3]= SimInstanceName[3]= Set characteristic impedance, Step=VDSstep
SimInstanceName[4]= SimInstanceName[4]= and gate and drain voltage
SimInstanceName[5]= SimInstanceName[5]= sweep limits as needed.
SimInstanceName[6]= SimInstanceName[6]= OPTIONS
Var VAR
Eqn
Start=VGSmin Start=VDSmin VAR3 Options
Stop=VGSmax Stop=VDSmax Z0=50 Options1
Step=VGSstep Step=VDSstep VGSmin=0.3 Temp=16.85
VGSmax=0.7 Tnom=25
VGSstep=0.1
VDSmin=0.25 V
VDSmax=6 V
VDSstep=0.1 V
 Optimum Source Match
• We can add source inductance to make one ZSopt
solution for S11 match and min NF whilst maintaining
high power gain
 Input Matching
• Using Smith Chart utility
 Input Matching
• Find microstrip dimensions using Linecalc
Output Matching
 Test Circuit
MSub

MSUB V_DC
MSub1 SRC1
H=0.8 mm R Vdc=5 V R
Er=4.5 R3 R2
Mur=1 R=6.8 kOhm R=56 Ohm
Cond=1.0E+50
Hu=3.9e+034 mil
T=35 um
TanD=0 MLIN C
Rough=0 mil TL3 C3
Bbase= Subst="MSub1" C=12 pF
Dpeaks= R R W=0.3 mm
R4 R1 L=9 mm
R=100 Ohm R=33 kOhm

C
C2
C=1 pF
C MLIN
C1 TL1
Term C=8.2 pF Subst="MSub1" ATF58143 Term
Term1 W=1.47 mm I__0 Term2
MLOC
Num=1 TL2 L=9 mm L L Num=2
Z=50 Ohm Subst="MSub1" L1 L2 Z=50 Ohm
W=1.47 mm L=1.2 nH L=1.2 nH
L=9 mm R= R=

S-PARAMETERS

S_Param
SP1
Start=1.0 GHz
Stop=3 GHz
Step=10 MHz
Linear Analysis of Test Circuit
Group Delay and Dev_Lin_Phase
 Non-linear Analysis (1)
• Using DesignGuide>Amplifier>HB2TonePswp
Two-Tone Harmonic Balance
Simulation; swept power.
I_Probe
Iload

LNA
I__18 Vload

P_nTone
Term
PORT1
Term1
Num=1
Num=2
Z=Z_s
Z=Z_load
Freq[1]=RFfreq-fspacing/2
Freq[2]=RFfreq+fspacing/2
P[1]=dbmtow(RFpower-3)
P[2]=dbmtow(RFpower-3) Set Load and Source impedances at baseband,
fundamental and harmonic frequencies
Var VAR Var
Eqn
VAR2 Eqn VAR
HARMONIC BALANCE Set these values:
Z0=50 VAR6
Var VAR
HarmonicBalance Eqn ;Load Impedances=
VAR1
HB1 Z_l_bb=Z0+j*0
RFfreq=2000 MHz
MaxOrder=Max_IMD_order Z_l_fund = Z0 + j*0
fspacing=10 kHz
Freq[1]=RFfreq-fspacing/2 Z_l_2 = Z0 + j*0
Max_IMD_order=7
Freq[2]=RFfreq+fspacing/2 Z_l_3 = Z0 + j*0
Order[1]=7 Z_l_4 = Z0 + j*0
Order[2]=7 SWEEP PLAN Z_l_5 = Z0 + j*0
SweepVar="RFpower" ;Source Impedances=
SweepPlan="Sweep1" SweepPlan
Z_s_bb=Z0+j*0
Sweep1
Z_s_fund = Z0 + j*0
Start=-10 Stop=0 Step=2.5 Lin=
Z_s_2 = Z0 + j*0
Start=1 Stop=6 Step=1 Lin=
Z_s_3 = Z0 + j*0
UseSweepPlan=
Z_s_4 = Z0 + j*0
SweepPlan=
Z_s_5 = Z0 + j*0
Reverse=no
IP3, Spectrum, P1dB
 Non-linear Analysis (2)
• We can find 64QAM EVM vs Pin using VTB
LNA
I__3 ENVELOPE

Envelope
VTB2_Env
Freq[1]=vtbFCarrier_Source
Order[1]=5

VTB
Var
Eqn VAR
+ +
Source Sink
VAR1
- -
P_dBm=-20

EVM_ACPR_measurement_Analysis PARAMETER SWEEP

VTB2
Modulation=64-QAM ParamSweep
GainImb=0 Sweep1
PhaseImb=0 SweepVar="P_dBm"
NumSymbols=200 SimInstanceName[1]="VTB2_Env"
NoiseDensity=4.00405e-21 W SimInstanceName[2]=
FCarrier=2 GHz SimInstanceName[3]=
RF_Power=dbmtow(P_dBm) SimInstanceName[4]=
RefR=50 Ohm SimInstanceName[5]=
SymbolRate=1 MHz SimInstanceName[6]=
PortZ[1]=50 Ohm Start=-20
PortZ[2]=50 Ohm Stop=10
Step=5
EVM vs Pin
 Next Steps: Design for Manufacture
• Improve Stability
• Component parasitics
• Microstrip discontinuities / balance stubs
• Supply filtering / regulation / noise
• Real estate
• Layout
• Thermal / MTBF
• Simulated yield optimisation
• Production design centring
• BOM cost
• Transient protection
Thank You