DTEL (Department for Technology Enhanced Learning)

The Centre for Technology enabled Teaching & Learning

Teaching Innovation - Entrepreneurial - Global 1

NAGAR YUWAK SHIKSHAN SANSTHA’S
SHRI DATTA MEGHE POLYTECHNIC

DEPARTMENT OF COMPUTER TECHNOLOGY

Microprocessor and Programming

AUTHORS
MANOJ JETHWA

2
 CONTENT: MICROPROCESSOR AND PROGRAMMING

1 CHAPTER 1: Basics of Microprocessor

.

2 CHAPTER 2: 16 Bit Microprocessor: 8086

3 CHAPTER 3: Instruction Set of 8086 Microprocessor

The Art of Assembly Language

4 CHAPTER 4: Programming

8086 Assembly Language

5 CHAPTER 5: Programming.

Procedure and Macro in Assembly

6 CHAPTER 6: Language Program

DTEL 3
 SYLLABUS GENERAL OBJECTIVE
The student will be able to:

1 Understand What is microprocessor Architecture.

Understand the execution of instructions in

2 pipelining and address generation.

Apply instructions in Assembly Language Program for

3 different problem statements.

Use the procedures and macros in assembly

4 language programming.

DTEL 4
 CHAPTER-1 Basics of Microprocessor

1 .
Topic 1: Evolution of Microprocessor and types

2 Topic 2: 8085 Microprocessor,

3 Topic 3: Salient features of 8085

4 Topic 4: Architecture of 8085 - Functional Block diagram,

5 Topic 5: Pin description,

DTEL 5
 CHAPTER-1 SPECIFIC OBJECTIVE / COURSE OUTCOME

The student will be able to:

Draw the architecture of 8085 and understand the functions of

1 different pins of 8085

Identify status of different flags and understand register

2 organisation of 8085

DTEL 6
 LECTURE 1: BASIC BLOCK OF COMPUTER
CPU OR MICROPROCESSOR

ALU
OUTPUT
INPUT Devices
Devices
Control Unit

DATA PATH CONTROL SIGNALS

MEMORY (Primary) BASIC BLOCK OF COMPUTERS

CONSISTS
ü ALU
MEMORY ü INPUT DEVICE
(Secondary) ü OUTPUT DEVICE
ü MEMORY
ü CONTROL UNIT

DTEL 7
 LECTURE 1:- BASIC BLOCK OF COMPUTER
The typical Computer system consists of:
§ CPU (central processing unit)
ü ALU (arithmetic-logic unit)
ü Control Logic
ü Registers, etc…
§ Memory
§ Input / Output interfaces

Interconnections between these units are through 3 basic buses:

§ Address Bus
§ Data Bus
§ Control Bus

DTEL 8
 LECTURE 1:- CPU
ü The main function of ALU is to perform arithmetic and
logical operations on binary numbers.

ü The Input Device is used to feed data and command for

the CPU.

ü The output device is used for display of result /data

/program etc.

ü The memory is used for storing information.

ü The control unit Synchronizes operation of ALU with IO

and Memory.
DTEL 9
 LECTURE 1:- BUS
The interconnections (known as Interfacing) between the 5 units
of computer system is carried by 3 basic buses i) Address Bus ii)
Data Bus iii) Control Bus. A bus(from the Latin omnibus, meaning
"for all") is essentially a set of wires which is used in computer
system to carry information of the same logical functionality. The
function of the 3 buses is
ü The address bus selects memory location or an I/O device for
the CPU.
ü The data bus transfers information between the
microprocessor and its memory or I/O device. Data transfer
can vary in size, from 8-bits wide to 64 bits wide in various
members of microprocessors.
ü The Control bus generates command signals to synchronise
the CPU operation with IO and Memory devices.

DTEL 10
 LECTURE 1:- Evolution of Microprocessor
Processo Date of Clock Data Bus Adress Bus Addressable Memory Size
r Launch speed Width
4004 1971 740 khz 4 bit 12 4 KB

8-BIT PROCESSOR
8008 1972 800 Khz 8 bit 14 16 Kb

8080 1974 2 Mhz 8 bit 16 64 kb

8085 1976 3 Mhz 8 bit 16 64 kb

16-BIT PROCESSOR
8086 1978 5 Mhz 16 20 1M

80286 1982 16 Mhz 16 24 16 M

DTEL 11
 LECTURE 1:- Evolution of Microprocessor
Processor Date of Clock Data Bus Adress Addressable Memory Size
Launch speed Width Bus
32-BIT PROCESSOR
80386 1985 33 Mhz 32 32 4G
80486 1989 40 Mhz 32 32 4G+ 8k cache
Petium I 1993 100 Mhz 32 32 4G+16k cache
Petium II 1997 233 Mhz 32 32 4G+16k cache + L2 256 Cache
Petium III 1999 1.4 Ghz 32 32 4G+32k cache + L2 256 Cache
Petium IV 2000 2.66 Ghz 32 Internal 32 4G+32k cache + L2 256 Cache
64 External
64-BIT PROCESSOR
2.66 Ghz 64G+Independent L1 64 Kb+
Dual Core 2006 64 36 Common L2 256 kb Cache
Core 2 64G+Independent L1 128 Kb+
Duo 2006 3 Ghz 64 36 Common L2 4 Mb Cache
64G+Independent L1 64 Kb+
Common L2 256 kb Cache + 8 Mb
I7 2008 3.33 Ghz 64 36 L3 Cache

DTEL 12
 LECTURE 2:- 8085 ARCHITECTURE
INTA INTR RST 5.5 RST 6.5 RST 7.5 TRAP SOD SID

INTERRUPT CONTROL SERIAL CONTROL

INTERNAL BUS

ACMULATOR
TEMP
INSTRUCTION B C
.REGISTER
REGISTER (IR) D E
FLAG 8-Bit H L
code
STACK POINTER (SP)
INSTRUCTION
DECODER and
PROGRAM .COUNTER (PC)
ALU MACHINE
CYCLE
ADDRESS
INCREMENTER / DECREMENTER
ENCODING

256-Bit

MULTIPLEXER

X1
TIMMING & CONTROL ADRESS /
Clock WAIT ADRESS
GEN DATA
RESET DMA STATUS CONTROL STATES BUFFER BUFFER
X2

Clock out Reset in HOLD ALE

A15-8 AD7-0
S0 S1 WR READY
Reset out IO / M RD
HLDA

DTEL 13
 LECTURE 2:- Processing Unit

üArithmetic and Logic Unit

üAccumulator
üStatus Flags
üTemporary Register

DTEL 14
 LECTURE 2:- Processing Unit
INTA INTR RST 5.5 RST 6.5 RST 7.5 TRAP SOD SID

Processing INTERRUPT CONTROL SERIAL CONTROL

Unit
INTERNAL BUS
8-Bit
code

ACMULATOR
TEMP
INSTRUCTION B C
.REGISTER
REGISTER (IR) D E
FLAG 8-Bit H L
code
STACK POINTER (SP)
INSTRUCTION
DECODER and
PROGRAM .COUNTER (PC)
ALU MACHINE
CYCLE
ADDRESS
INCREMENTER / DECREMENTER
ENCODING

256-Bit

MULTIPLEXER

X1
TIMMING & CONTROL ADRESS /
Clock WAIT ADRESS
GEN DATA
RESET DMA STATUS CONTROL STATES BUFFER BUFFER
X2

Clock out Reset in HOLD ALE

A15-8 AD7-0
S0 S1 WR READY
Reset out IO / M RD
HLDA

DTEL 15
 LECTURE 2:- Arithmetic & Logic Unit (ALU)

ü It performs Arithmetic and logic operations on binary nos.

ü The result is stored in accumulator in most cases, hence A

is known as accumulator.

ü Arithmetic Operations:

ü Addition, Subtraction, Increment, Decrement .

ü Logic Operations:

ü AND, OR, X-OR, Complement .

DTEL 16
 LECTURE 2:- Arithmetic & Logic Unit (ALU)

ü It the main register of microprocessor directly connected

with the ALU.

ü It is also called register ‘A’.

ü It is an 8-bit register.

ü It is used in the arithmetic and logic operations.

ü It always contains one of the operands on which

arithmetic/logic has to be performed.

ü After the arithmetic/logic operation, the contents of

accumulator are replaced by the result.

DTEL 17
 LECTURE 2:- Arithmetic & Logic Unit (ALU)
Status Flag
F7 F0

SF ZF AF PF CF

The 5 Status Flags are Ø Status

Flags
CF: Carry flag
affected immediately after an
PF: Parity flag
arithmetic or logical operation AF: Auxiliary carry flag
performed by the ALU. The ZF: Zero flag
SF: Sign flag
SET or RESET condition of OF: Overflow flag
each flag is used to indicate
the status of the result
generated by the ALU.

DTEL 18
 LECTURE 2:- Arithmetic & Logic Unit (ALU)
Status Flag
ü Sign Flag: It is used to indicate whether the result is positive or negative. It will
set (SF=1) if the result is –ve and if the result +ve then SF=0.

ü Zero Flag: It is used to indicate whether the result is a Zero or non-zero. It will set
(ZF=1) if the result is zero else ZF=0.

ü Auxiliary carry Flag: It is used to indicate whether or not the ALU has generated a
carry/Borrow from D3 bit position to D4 bit. It will set if there was a carry out
from bit 3 to bit 4 of the result else AF=0. The auxiliary carry flag is used for
binary coded decimal (BCD) operations.

ü Parity Flag: It is used to indicate parity ( Even or Odd) of the result. It will set if the
parity is even else PF =0.

ü Carry Flag: It is used to indicate whether a carry/Borrow has been generated

/occurred during addition/subtraction It will set if there was a carry is generated
from the MS-bit during addition, or borrow during subtraction/comparison else
CF=0.
DTEL 19
 LECTURE 2:- Arithmetic & Logic Unit (ALU)
Program Status Word (PSW)
• The Accumulator and Status Flags clubbed
together is known as Program Status Word (PSW).

• It is a 16-bit word.

Accumulator (8) FLAGs (8)

DTEL 20
 LECTURE 3:- Register sets & pointer
INTA INTR RST 5.5 RST 6.5 RST 7.5 TRAP SOD SID
Storage ,
Pointer and
INTERRUPT CONTROL SERIAL CONTROL
Interface
INTERNAL BUS

ACMULATOR
TEMP
INSTRUCTION B C
.REGISTER
REGISTER (IR) D E
FLAG 8-Bit H L
code
STACK POINTER (SP)
INSTRUCTION
DECODER and
PROGRAM .COUNTER (PC)
ALU MACHINE
CYCLE
ADDRESS
INCREMENTER / DECREMENTER
ENCODING

256.

MULTIPLEXER

X1
TIMMING & CONTROL ADRESS /
Clock WAIT ADRESS
GEN DATA
RESET DMA STATUS CONTROL STATES BUFFER BUFFER
X2

Clock out Reset in HOLD ALE

A15-8 AD7-0
S0 S1 WR READY
Reset out IO / M RD
HLDA

DTEL 21
 LECTURE 3:- Register sets & pointer
ü The 8085 has set of 8 register (of 8-bit) and 2 memory pointers (of
16-bit) . The register A and flag are directly connected with ALU,While
B,C,D,E,H,& L are indirectly connected through internal bus. The
register A is used to store data as well as result of an operation
performed by the ALU.The Flag is used to store status of result. The
register B,C,D,E,H,L are used to store 8-bit data. It can also be paired
to store 16-bit data. The pairing combination can be,
B-C D-E H-L
The register pairs can also be used to generate 16-bit address.

ü The pointers are used to generate 16-bit address for selection of

memory location. The PC generates address during execution of a
program. It contains the memory address (16 bits) of the instruction
that will be executed in the next step.
While SP generates address during stack operation.

DTEL 22
 LECTURE 3:- Timming-Control and IR -Decoder
INTA INTR RST 5.5 RST 6.5 RST 7.5 TRAP SOD SID

INTERRUPT CONTROL SERIAL CONTROL

INTERNAL BUS

ACMULATOR
TEMP
INSTRUCTION B C
.REGISTER
REGISTER (IR) D E
FLAG 8-Bit H L
code
STACK POINTER (SP)
INSTRUCTION
DECODER and
PROGRAM .COUNTER (PC)
ALU MACHINE
CYCLE
ADDRESS
INCREMENTER / DECREMENTER
ENCODING
Instruction
Unit
256-Bit

MULTIPLEXER

X1
TIMMING & CONTROL ADRESS /
Clock WAIT ADRESS
GEN DATA
RESET DMA STATUS CONTROL STATES BUFFER BUFFER
X2

Clock out Reset in HOLD ALE

A15-8 AD7-0
S0 S1 WR READY
Reset out IO / M RD
HLDA

DTEL 23
 LECTURE 3:- IR-DECODER-TIMMING & CONTROL

• Instruction Register : It is used to store the current

instruction code which is fetched from the memory It
is an 8-bit register.

• Instruction Decoder : Instruction is decoded and the

meaning in the form of signal is given to TC.

• Timing and Control Unit : It generates internal and

external signals to execute the code

DTEL 24
PIN DIAGRAM OF 8085

25
 LECTURE 4:- Pin diagram

DTEL 26
 LECTURE 4:- Pin diagram
ü It was introduced in 1977 by Intel.
ü It is 8-bit microprocessor.
ü It is NMOS device consisting of 6200
transistors .
ü Its data bus is 8-bit and address bus is 16-
bit.
ü Its clock speed was 3 MHz. Could
execute 7,69,230 instructions per second.
ü Its data bus is 8-bit and address bus is 16-
bit.
ü It had 6,500 transistors.

ü It is 40 pins Dual-Inline-Package (DIP).

DTEL 27
 LECTURE 4:- X1 & X2 Pin 1 and Pin 2

— It is also called Oscillator

Pins to which crystal of
max 6.14 Mhz should be
connected so that 8085
can generate clock signals
internally.
— The internal Clock pulses
will be ½ times crystal
value i.e, 3.07 Mhz.

DTEL 28
 LECTURE 4:- RESET IN and RESET OUT Pin 36 and Pin 3

◦ RESET IN is used to reset the

microprocessor by making the pin Low.
When the signal on this pin is low for at
least 3 clock cycles, it forces the
microprocessor to reset . Thereby ,
1. Clear the PC and IR.
2. Disable all the interrupts (except
TRAP) and the SOD pin.
3. HIGH output pulse to RESET OUT pin.

◦ Reset OUT is used to reset the external

peripheral devices and ICs on the
circuit. It is active high signal. The
output on this pin goes high whenever
RESET IN pin is made low .

DTEL 29
 LECTURE 4:- SID and SOD Pin 4 and Pin 5
— SID (Serial Input Data): It
receives 1-bit from external
device and Stores the bit at the
MSB of the Accumulator. RIM
(Read Interrupt Mask)
instruction is used to transfer
the bit from SID MS Bit of Acc.

— SOD (Serial Output Data): It

transmits MSB of Accumulator
through this pin. SIM (Set
Interrupt Mask) instruction is
used to transfer the MS bit of
Acc through SOD.

DTEL 30
 LECTURE 4:- Interrupt Pins 6 to 11
— Interrupt: (INTR,RST5.5,RST6.6,RST7.5
and TRAP pins)
• It allows external devices to
interrupt the normal program
execution of the microprocessor.
• When microprocessor receives
interrupt signal, it temporarily
stops current program and starts
executing new program indicated
by the interrupt signal.
• Interrupt signals are generated by
external peripheral devices like
keyboard , sensors, printers etc.
• After execution of the new
program, microprocessor returns
back to the previous program.
DTEL 31
 LECTURE 4:- Interrupt Pins 6 to 11

— The 5 Hardware Interrupt Pins are TRAP , RST 7.5 , RST

6.5 , RST 5.5 and INTR. Interrupts can be classified as,
1. Maskable and Non-Maskable
2. Vectored and Non-Vectored
3. Edge Triggered and Level Triggered
4. Priority Based Interrupts

DTEL 32
 LECTURE 4:- Interrupt Pins 6 to 11
Maskable and Non-Maskable
Maskable interrupts are those interrupts which can be enabled or
disabled. Enabling and Disabling can be done by software
instructions like EI , DI and SIM. The interrupt pins RST7.5, RST6.5
,RST5.5 and INTR are Maskable.

The interrupts which cannot be disabled are called non-maskable

interrupts. These interrupts can never be disabled by any
software instruction. TRAP is a non-maskable interrupt.Such pins
are normally used for emergency cases like fire alarming , fire
extinguisher system ,intruder detector etc.

DTEL 33
 LECTURE 4:- Interrupt Pins 6 to 11
Vectored and Non-Vectored
• Vectored interrupts which have particular memory location where program
control is transferred when interrupt occur. Each vectored interrupt points to the
particular location in memory. RST 7.5 , RST 6.5 ,RST 5.5, TRAP are vectored
Interrupts.
— The addresses to which program control is transferred are :
Name Vectored Address
RST 7.5 003C H (7.5 x 0008 H)
RST 6.5 0034 H (6.5 x 0008 H)
RST 5.5 002C H (5.5 x 0008 H)
TRAP 0024 H (4.5 x 0008 H)
— Absolute address is calculated by multiplying the RST no with 0008 H.

• Non-Vectored interrupts don't have fixed memory location for transfer of

program control. The address of the memory location is given by interrupting
device to the processor along with the interrupt. INTR is a non-vectored
interrupt.

DTEL 34
 LECTURE 4:- Interrupt Pins 6 to 11
Edge Triggered and Level Triggered
The interrupts that are triggered at leading or trailing edge are
called edge triggered interrupts. RST 7.5 is an edge triggered
interrupt. It is triggered during the leading (positive) edge.

The interrupts which are triggered at high or low level are called
level triggered interrupts. RST 6.5,RST 5.5, INTR, are level triggered
…..
interrupt.

The TRAP is edge and level triggered interrupt.

DTEL 35
 LECTURE 4:- Interrupt Pins 6 to 11
Priority Based Interrupts
When there is a simultaneous interrupt request at two or more
interrupt pins then the microprocessor will execute program of
that pin that has higher priority. To avoid confusion in such cases
all microprocessor assigns priority level to each interrupt pins.
Priority is considered by microprocessor only when there are
simultaneous requests. The priority of 8085 pins are:
Interrupt Priority
TRAP 1
RST 7.5 2
RST 6.5 3
RST 5.5 4
INTR 5

DTEL 36
 LECTURE 4:- Address and Data Pins

• Address Bus pins A15–A8 and

AD7–AD0 : The address bus are
used to send address for memory
or IO device. It selects one of the
many locations in memory or a
particular IO port. 8085 has 16-bit
bus.
• Data Bus pins AD7–AD0 : It is
used to transfer data between
microprocessor and memory /IO
Device. 8085 Data bus is of 8-bit.

DTEL 37
 LECTURE 4:- ALE Pin 30

• On this pin 8085 generates a

pulse in the T1 clock of each
Machine cycle to latch lower
byte adress from AD7 – AD0
pins.From mid of T2 to T3 the
bus can transfer data.

• It indicates whether the bus has

address or data .Since the bus
AD7 – AD0 is used for Adress as
well as data therefore it is
known as Multiplexed bus. Due
to multiplexing 8085 has less
no of pins.

DTEL 38
 LECTURE 4:- Status S1 ,So Pin 31 ,29
• S0 and S1 are called Status
Pins.They indicate the
status of current operation
which is in progress by
8085.The 4 status
indicated by 8085 are
S0 S1 Operation
0 0 Halt
0 1 Write
1 0 Read
1 1 Opcode
Fetch

DTEL 39
 LECTURE 4:- IO/M Pin 34

• This pin indicates whether I/O

or memory operation is being
performed by microprocessor.
• If IO/M = 1 then
– I/O operation is being
performed.
• If IO/M = 0 then
– Memory operation is being
performed.

DTEL 40
 LECTURE 4:- RD Pin 32

• It is a control signal used to

perform Read operation
from memory or from
Input device. It is active
low signal. A low signal
indicates that data on the
data bus must be placed by
the selected memory
location or input device.

DTEL 41
 LECTURE 4:- WR Pin 31
• It is a control signal used to
perform Write operation
into memory location or to
output device. It is also
active low signal. A low
signal indicates that data on
the data bus must be
written into selected
memory location or to
output device.

DTEL 42
 LECTURE 4:- READY Pin 35
• This pin is used to
synchronize slower peripheral
devices with high speed of
microprocessor.

• A low pulse in T2 causes the

microprocessor to enter into
wait state.

• The microprocessor remains

in wait state until the input at
this pin goes high.

DTEL 43
 LECTURE 4:- HOLD Pin 38
• HOLD pin is used to request the
microprocessor for DMA
transfer.

• A high signal on this pin is a

request to microprocessor, by
external device, to relinquish
the hold on buses.

• The request is sent by external

device through DMA controller.

DTEL 44
 LECTURE 4:- HLDA Pin 39
• The HLDA signal is send to DMA
Controller as acknowledgement
to DMA controller to indicate
that microprocessor has
relinquished the system bus.

• After data transfer When HOLD

is made low by DMA controller,
HLDA is also made low by 8085
so that the microprocessor
takes control of the buses again.

DTEL 45
 LECTURE 4:- VSS and VCC Pin 20 and Pin 40

• +5V DC power supply

is connected to VCC to
bias internal circuit.
• Ground signal is
connected to VSS.

DTEL 46
 LECTURE 5:- Chapter 1 Question Bank
• What are the technical features of 8085?
• Explain the function of ALU section of 8085.
• Describe the function of the following blocks of 8085
• ALU ii) Timming & control iii) Instruction Decoder
• Explain the function of various registers of 8085.
• Draw the Block (Architecture) of 8085 and explain IR, stack pointer and
programme counter.
• What are the various Flag of 8085?
• What are the pointers of 8085.Explain the function of Pointers of 8085?
• Explain the function of Interrupt section of 8085.
• List Maskable and non-maskable Interrupts of 8085.
• Explain the function of SID & SOD of 8085.
• Describe microprocessor evolution with suitable example?
• Differentiate, any six ,between 8085 & 8086.

DTEL 47
 LECTURE 5:- Summary
1.The typical Computer system consists of:
ü ALU (arithmetic-logic unit)
ü Control Logic
ü Memory
ü Input devices
ü Output devices

2. A bus(from the Latin omnibus, meaning "for all") is essentially a set of

wires which is used in computer system to carry information of the same
logical functionality. The interconnections (known as Interfacing) between the
5 units of computer system is carried by 3 basic buses
i) Address Bus ii) Data Bus iii) Control Bus.

3. 8085 can be divided into sections like i) Processing unit ii) Register &
pointers iii) instruction register-decoder-timming & control.

4.The 8085 has 8-bit flag but 5 are affected by Arithmetic / logical operation.

DTEL 48
 CHAPTER-2 16 Bit Microprocessor: 8086
Topic 1: Salient features of 8086
1 .

Architecture of 8086 - Functional Block

2 Topic 2: diagram,

3 Topic 3: Register organization,

4 Topic 4: Concepts of pipelining, Memory segmentation

5 Topic 5: Operating Modes of 8086

DTEL 49
 CHAPTER-2 SPECIFIC OBJECTIVE / COURSE OUTCOME

The student will be able to:

Draw the architecture of 8086 and understand the functions of

1 different pins of 8086

2 Understand the operating modes of 8086

DTEL 50
Lecture 1: Intel 8086 Microprocessor
Key Features:
üIntroduction date: March 1978
üIt is 16-bit HMOS microprocessor implemented
with 29,000 transistors
üIt can be operated with clock Frequency of 5MHz
üTechnology: HMOS
üNumber of Pins : 40
ü It has 20-bit Address lines and hence it can address 220 = 1 Mbytes
memory location.
üIt can generate 16-bit address for IO devices and can address 216 = 64K IO
ports.
üIt can be operated in two Modes : Maximum and Minimum
üIt has two stage pipeline architecture.
üNumber of instructions: 135 instructions with eight 8-bit registers and eight
16-bit registers
üDC Power Supply +5v

DTEL 51
LECTURE 1 Architecture of 8086
MEMORY

Σ 6 6-Byte Q
5
4
3
CS
2
DS
1
ES
SS
IP
Control
BIU
system
EU

AH AL
BH BL ALU
CH CL
DH DL
SP
BP FLAGS
SI
DI

DTEL 52
LECTURE 2 Architecture of 8086
• The architecture of 8086 provides a number of
improvements over 8085 architecture. It supports a 16-bit
ALU, a set of 16-bit registers and provides segmented
memory addressing capability, a rich instruction set,
powerful interrupt structure, fetched instruction queue
for overlapped fetching and execution.
• The complete architecture of 8086 can be logically
divided into two units a) Bus Interface Unit (BIU) and (b)
Execution Unit (EU). Both units operate asynchronously to
provide the 8086 to overlap instruction fetch and
execution operation , which is called as parallel
processing. This results in efficient use of the system bus
and enhance system performance.

DTEL 53
LECTURE 3 Pipelining and parallel processor
An instruction pipeline is a technique used in the design of
microprocessors to increase the number of instructions that can
be executed in a unit of time. Pipeline technique is used in
advanced microprocessors where the microprocessor begins
operation on next instruction before it has completed operation
on the previous. That is, several instructions are simultaneously
in the pipeline at a different stage of processing. The pipeline is
divided into different Stages and each Stage can perform its
particular operation simultaneously with the other stages.
When a stage completes an operation, it passes the result to
the next stage in the pipeline and fetches the next operation
from the preceding stage. The final results of each instruction
emerge at the end of the pipeline in rapid succession. Since all
units perform operation concurrently on different instructions ,
it is known as parallel processor.
DTEL 54
LECTURE 3 Pipelining and parallel processor
Pipelining of 8086
INSTRUCTION
NO. EXECUTION PHASES
1 Fetch-1 Decode-1 Execute-1
2 Fetch-2 Decode-2 Execute-2
3 Fetch-3 Decode-3 Execute-3
4 Fetch-4 Decode-4 Execute-4
5 Fetch-5 Decode-5 Execute-5
6 Fetch-6 Decode-6 Execute-6

Machine
cycle
1 2 3 4 5 6 7 8
Non-Pipelining Process of 8085
Inst ruction-1 Inst ruction-2 Inst ruction-3
Fetch-1 Decode-1 Execute-1 Fetch-2 Decode-2 Execute-2 Fetch-3 Decode-3 Execute-3
M.
cycle 1 2 3 4 5 6 7 8 9
DTEL 55
LECTURE 4 Register of 8086
8086 has a powerful set of registers that can be grouped as
Ø General Data register
Ø Segment registers
Ø Pointers & Index registers
Ø FLAG
Ø Only GPRs can be accesses as
8/16-bit while others as 16-bit only

AX AH AL CS IP FLAGS /
BH BL DS PSW
BX SI
CX CH CL ES DI
DX DH DL SS SP
General Data Segment BP
registers registers
Pointers and
Index registers

DTEL 56
LECTURE 4 Special Purpose Registers:
• Special Purpose Registers: The special purpose registers are
Ø Segment registers
Ø Pointers and index registers

• Segment Registers : Unlike 8085, the 8086 addresses a

segmented memory of 1MB, which the 8086 is able to address.
The 1 MB is divided into 16 logical segments (16 X 64 KB = 1024
KB = 1 MB). Each segment thus contains 64 Kbytes of memory.
There are four segment registers, viz. Code Segment Register
(CS), Data Segment Register (DS), Extra Segment Register (ES) and
Stack Segment Register (SS).

DTEL 57
LECTURE 4 Special Purpose Registers:
Pointers and Index Registers
The pointers contain offset within the particular
segments. The pointers IP, BP and SP usually contain
offsets within the code, data and stack segments
respectively. The index registers are used as general
purpose registers as well as for offset storage in case of
indexed, based indexed and relative based indexed
addressing modes. The register SI is generally used to
store the offset of source data in DMS while the
register DI is used to store the offset of destination in
DMS or EMS. The index registers are particularly useful
for string manipulations.

DTEL 58
LECTURE 5 Flag Register
• The FLAG is nothing but group of flip-flops which are affected
(SET or RESET) immediately after an arithmetic or logical
operation performed by the ALU.
• The flags of 8086 can be divided into two types: Conditional
Flags and Control Flags
• Conditional Flags are affected immediately after an arithmetic or
logical operation performed by the ALU. The SET or RESET
condition of each flag is used to indicate the status of the result
generated by the ALU.The 8086 has 6 conditional flags, out of
which 5 are similar to the 8085 while Overflow flag is the
additional flag.
• Control Flag are not affected by Arithmetic or logical operation
performed by the ALU but programmer can SET or RESET these
Flags to Control certain operation/Instructions.

DTEL 59
LECTURE 5 Flag Register
Same as 8085
Additional Flags

XX XX XX XX OF DF IF TF SF ZF XX AF XX PF XX CF
F15 F8 F7 F0

Ø Control Flags Ø Status Flags

IF: Interrupt enable flag CF: Carry flag
DF: Direction flag PF: Parity flag
TF: Trap flag AF: Auxiliary carry flag
ZF: Zero flag
SF: Sign flag
XX: Don’t Care OF: Overflow flag

DTEL 60
LECTURE 5 Conditional Flag
The 6 Status or Conditional Flags are affected immediately after an
arithmetic or logical operation performed by the ALU. The SET or
RESET condition of each flag is used to indicate the status of the
result generated by the ALU.

• Sign Flag: It is used to indicate whether the result is positive or

negative. It will set (SF=1) if the result is –ve and if the result +ve then
SF=0.
• Zero Flag: It is used to indicate whether the result is a Zero or non-
zero. It will set (ZF=1) if the result is zero else ZF=0.
•Auxiliary carry Flag: It is used to indicate whether or not the ALU has
generated a carry/Borrow from D3 bit position to D4 bit. It will set if
there was a carry out from bit 3 to bit 4 of the result else AF=0. The
auxiliary carry flag is used for binary coded decimal (BCD) operations.

DTEL 61
LECTURE 5 Conditional Flag
•Parity Flag: It is used to indicate parity ( Even or Odd) of the result.
It will set if the parity is even else PF =0.

•Carry Flag: It is used to indicate whether a carry/Borrow has been

generated /occurred during addition/subtraction It will set if there
was a carry is generated from the MS-bit during addition, or borrow
during subtraction/comparison else CF=0.

•Overflow Flag: The OF indicates a signed arithmetic result

overflow. If result of an operation is too large a positive number or
too small a negative number to fit in the destination then OF will
SET, else it will RESET.

DTEL 62
LECTURE 5 Control Flag
TF (Trap Flag) : It is used for Single step operation .If TF=1 then 8086
executes single instruction at a time and stop momentarily. If TF=0
then 8086 executes the given programme in natural sequence.

IF (Interrupt-enable flag) : When IF=1 then maskable Interrupt INTR

will cause the CPU to transfer control to an interrupt vector location.

DF (Direction flag) : Causes string instructions to auto decrement/

increment the index registers (SI/DI) by 1 ( for byte operation) or 2
by word operation). If DF=1 will decrement and DF=0 will increment
index registers.

DTEL 63
LECTURE 6 20-bit Physical address generation
ü Since the 8086 can generate 20-bit physical address therefore
it can access 2 20= 1048576 locations or 1024 Kbytes location
or 1 Mbytes locations addressed from 00000h TO FFFFFh .
ü For programme flexibility the 1Mbytes location is logically
segmented (divided or organized) into
Ø Code Memory Segment (CMS),

Ø Data Memory Segment (DMS),

Ø Extra Memory Segment (EMS) and

Ø Stack Memory Segment (SMS).

DTEL 64
LECTURE 6 20-bit Physical address generation
ü Each memory segment can be maximum of 64 Kbytes.

ü To access a particular location of memory segment the 20-bit

physical address is generated by the addition of Base Address
(BA) provided by the segment register and 16/8 bit offset
address/displacements (OA) is provided by Pointers/index
registers.

The selection of segment registers and

pointers/index registers is according to the rule
given in the table.

DTEL 65
LECTURE 6 Default combination of seg reg & pointer
Segment Default
Name of register Pointers/ Index Memory
Memory used for register used segment
segment base value for offset used for Segment selection rule
address
CMS Automatic during
(Code memory CS IP Instructions execution of a
Segment) programme to prefetch
code.
DMS During execution of a
(Data memory DS BX/SI/16/8bit Local data string instruction or
Segment) displacement data transfer.
During execution of a
(Data memory ES DI/16/8bit External string instruction or
Segment) displacement data data transfer from IO.
SMS During execution of a
(Data memory SS SP/BP Stack stack instruction.
Segment)

DTEL 66
LECTURE 7 Memory Address generation

4-bit
Inserted
0’s
16-BIT SEGMENT VALUE 0000

+ 16-BIT OFFSET

20-BIT PHYSICAL ADRESS

DTEL 67
LECTURE 7 Memory Address generation Example

Inserted 0’s
Segment
Converted to 20-bit
2500 Base

2 5 0 0 0 Logical Address

Added with
95F3 Offset
9 5 F 3
+
2 E 5 F 3 FFFFF H

20-bit Physical Address to

select Memory location
.
External Memory consisting of
. 1024 K location with address
. range from 0000H to FFFFFH

.
.
00000 H

DTEL 68
LECTURE 8 RANGE OF CMS-DMS-EMS-SMS
FFFFF H
Maximum range of one 16 –BIT NUMBER IN
Memory segment is 64 K SEGMENT REGISTER
Physical Address
range from 00000H
to FFFFFH is Inserted 0’s by ∑ of BIU
1024 KB = 1 MB.
Hence we can create
4 set of 4FFFF H
CMS-DMS-EMS-SMS SMS
40000 H 4000 0
20-bit Base Address
3FFFF H
( for SMS)
EMS
30000 H 3000 0
2FFFF H 20-bit Base Address
( for EMS)
DMS
20000 H 2000 0
1FFFF H 20-bit Base Address
CMS ( for DMS)
Total capacity of 1
set of Memory 10000 H 1000 0
segment will be 64 20-bit Base Address
K + 64 K + 64 K + 64 ( for CMS)
K = 256 K 00000 H + 16-bit Offset (0000 to FFFF )
Hence CMS will range from
10000 h to 1FFFFh

DTEL 69
LECTURE 8 Advantages of memory segmentation

ü Allows the memory capacity to be 1Mb even though the

addresses associated with the individual register / instructions are
only 16 bits wide.

ü Facilitate the use of separate memory areas for the program, its
data and the stack and allows a program and/or its data to be put
into different areas of memory each time the program is
executed. Due to which relocatibility of information becomes
efficient.

DTEL 70
LECTURE 8 Advantages of memory segmentation
üThe greatest advantage of segmented memory is that programs
that reference logical addresses only can be loaded and run
anywhere in memory. This is because the logical addresses always
range from 00000h to 0FFFFh, independent of the code segment
base. Such programs are said to be relocatable, meaning that they
can be executed at any location in memory. The requirements for
writing relocatable programs are
1. No reference should be made to physical addresses, and
2. No changes to the segment registers be allowed once
initialised.
ü Since more than 1 set of CMS-DMS-EMS-SMS can be created
therefore multiprogramming can be implemented easily. Also
sharing of segments by different process is also possible.

DTEL 71
LECTURE 9 MINIMUM & MAXIMUM MODE
8086 works in two modes: GND 1
8086

40 +5V

AD14 2 39 AD15

1) Minimum Mode and 2) Maximum AD13 3 38 A16/S3

Mode AD12

AD11
4

5
37 A17/S4

36 A18/S5

If pin 33 MN/MX is high, it works in

AD10 6 35 A19/S6

AD9 7 34 BHE/ S7

minimum mode and If pin 33 MN/MX AD8 8 33 MN/MX MN/MX =1 MN/MX =0

MINIMUM MAXIMUM

is low, it works in maximum mode. AD7

AD6 10
9 32 RD

31
MODE
SIGNALS
HOLD
MODE
SIGNALS
RG/Gto

AD5 11 30 HLDA RQ/GT1

AD4 12 29 WR LOCK

Pins 24 to 31 generates two different

AD3 13 28 M/IO S2

AD2 14 27 DT / R S1

sets of signals. One set of signals is AD4 15 26 DEN So

generated in minimum mode. Other AD1 16

AD0 17
25

24
ALE

INTA
Qso

QS1

set of signals is generated in maximum NMI 18 23 TEST

mode. CLK 19 22 READY

GND 20 21 RESET

DTEL 72
LECTURE 9 Pin Description for Minimum Mode
• Pin 24 is an interrupt acknowledge. When microprocessor
receives INTR signal, it uses this pin to send acknowledgment by
generating 3 active low signal.
• Pin 25 is an Address Latch Enable signal. It indicates that valid
address is generated on bus AD15 – AD0.It generates a pulse
during T1 state.It is connected to enable external latch .
• Pin 26 is a Data Enable signal. This signal is used to enable the
external transceiver like 8286. Transceiver is used to separate
the data from the address/data bus AD15 – AD0.It is an active low
signal.
• Pin 27 is a Data Transmit/Receive signal. It controls the direction
of data flow through the transceiver. When it is high, data is
transmitted out.When it is low, data is received in.

DTEL 73
LECTURE 9 Pin Description for Minimum Mode
• Pin 28 is issued by the microprocessor to distinguish whether
memory or /O access. When it is high, memory can be
accessed. When it is low, I/O devices can be accessed.
• Pin 29 is a Write signal. It is used to write data in memory or
output device depending on the status of M/IO signal. It is an
active low signal.
• Pin 30 is a Hold Acknowledgement signal.It is issued after
receiving the HOLD signal.It is an active high signal.
• Pin 31 During DMA operation microprocessor receives HOLD
signal from DMA controller.

DTEL 74
LECTURE 9 Pin Description for Maximum Mode
QS1 and QS0
Pin 24 and 25

• These pins provide the status of

internal instruction queue.
QS1 QS0 Status
0 0 No operation
0 1 1st byte of opcode from
queue
1 0 Empty queue
1 1 Subsequent byte from queue

DTEL 75
LECTURE 9 Pin Description for Maximum Mode
S0, S1, S2
Pin 26, 27, 28
• These status signals
S2 S1 S0 Status
indicate the operation
0 0 0 Interrupt
being to be performed Acknowledge
by the microprocessor.
0 0 1 I/O Read
• These information 0 1 0 I/O Write
decoded by the Bus 0 1 1 Halt
Controller 8288 which 1 0 0 Opcode Fetch
generates all memory 1 0 1 Memory Read
and I/O control signals. 1 1 0 Memory Write
1 1 1 Passive

DTEL 76
LECTURE 9 Pin Description for Maximum Mode
LOCK
Pin 29
• This signal indicates that external processors like
8087 should not request CPU to relinquish the
system bus as it is locked with important
operation. This pin is activated by using LOCK
prefix before any instruction.
• When it goes low, all interrupts are masked and
HOLD request is not granted.

DTEL 77
LECTURE 9 Pin Description for Maximum Mode
RQ/GT1 and RQ/GT0
Pin 30 and 31 (Bi-directional)
• These are Request/Grant pins.
• External processors like 8087 can request the CPU
through these lines to release the system bus.
• After receiving the request, CPU sends acknowledge
signal on the same lines.

• RQ/GT0 has higher priority than RQ/GT1.

DTEL 78
LECTURE 10 De-multiplexing Address/Data Pin Description

WR RD A[19:16] FFFFF H
A[19:8]
Buffer

ALE CLK
External memory
8086 A[15:0]
with
AD[15:0] 1024 KB
D Q (i,e. 10,48,576)
locations
D latches
00000 H
DT/ R DEN
Data Bus
D[15:0]
Trans-receiver

DTEL 79
LECTURE 11 Memory Read Timing Diagrams
T1 T2 T3 T4
CLK A[19:6]
ALE Buffer
A[19:0]

A[19:16] A[19:16] S3-S6

8086
AD[15:0]
D latch

AD[15:0] A[15:0] D[15:0]

Memory

IO/M D[15:0]
Trans
DT/R
DT/R -ceiver
DEN
DEN
IO/M
RD WR
RD
WR

DTEL 80
LECTURE 11 Memory Write Timing Diagrams
T1 T2 T3 T4
CLK A[19:6]
ALE Buffer
A[19:0]

A[19:16] A[19:16] S3-S6

8086
AD[15:0]
D latch

AD[15:0] A[15:0] D[15:0]

Memory

IO/M D[15:0]
Trans
DT/R
DT/R -ceiver
DEN
DEN
IO/M
WR WR
RD
RD

DTEL 81
LECTURE 12 Chapter 2 Question Bank
• What is pipeline?
• Explain the function of Q 8086.
• Describe the function EU & BIU.
• Explain the function of various registers of 8086.
• Explain function of segment register & pointer .
• What are the various Flag of 8086?
• How 20-bit address is generated in 8086?
• Explain the Minimum and Maximum mode of 8086.
• Explain the timming diagram of memory read 8086.
• Explain the timming diagram of memory write 8086.

DTEL 82
LECTURE 12 Summary
1.The 8086 logically divided into:
ü BIU &
ü EU
Both units operate asynchronously to give the 8086 an overlapping instruction
fetch and execution mechanism which is called as Pipelining.

2. For programme flexibility the 1Mbytes location is logically segmented (divided or

organized) into Code Memory Segment (CMS), Data Memory Segment (DMS), Extra
Memory Segment (EMS) and Stack Memory Segment (SMS).

3.To access a particular location of memory segment the 20-bit physical address
is generated by the addition of Base Address (BA) provided by the segment
register and 16/8 bit offset address/displacements (OA) is provided by
Pointers/index registers.

4. The flags of 8086 can be divided into two types: Conditional Flags and Control Flags

5. 8086 works in two modes: 1) Minimum Mode 2) Maximum Mode.

DTEL 83
 CHAPTER-3 Instruction Set of 8086 Microprocessor
Topic 1: Machine Language Instruction format,
1 . addressing modes

2 Topic 2: Instruction set,

3 Topic 3: Groups of Instructions,

DTEL 84
 CHAPTER-3 SPECIFIC OBJECTIVE / COURSE OUTCOME

The student will be able to:

1 Understand the different types of instructions

Identify the addressing modes of instruction and the operation of

2 an instructions

DTEL 85
LECTURE 1 INTRODUCTION TO ASSEMBLY PROGRAMMING
A programme is nothing but set of Instructions written sequentially one below
the other and stored in computers memory for execution by microprocessor.

Instruction consists of a mnemonic and one or two operands (data).

ØMachine Language: In this Programs consist of 0s and 1s.

ØAssembly Languages : It uses short form notations , called , mnemonics ,

to write a programme .The Mnemonics are like MOV , ADD , SUB, etc.

Ø High level languages: It uses English like sentences with proper syntax to
write a programme.

ØAssembler translates Assembly language program into machine code.

Ø Compilers like Pascal, Basic, C etc translate the HLL program into
machine code. The programmer does not have to be concerned with internal
details of the CPU.

DTEL 86
LECTURE 1 INTRODUCTION TO ASSEMBLY PROGRAMMING

Conversion from HLL to ML is

Done by Compiler / Interpreter

HIGH LEVEL

ASSEMBLY LEVEL

MACHINE
LEVEL

Conversion from ALL to ML

is Done by Assembler like
MASM

DTEL 87
LECTURE 2 Instruction Format
q General Format of Instructions is
Label: Opcode Operands ; Comment

Ø Label: It provides a symbolic address that can be used in branch instructions

Ø Opcode: It specifies the type of instructions
Ø Operands: Instructions of 8086 family can have one, two, or zero operand
Ø Comments: programmers can use for effective reference

q Machine Code Format

Opcode Mode Operand1 Operand2

MOV AL, BL 1000100011000011

binary code of MOV

DTEL 88
LECTURE 2 What is Addressing Modes?
Ø Addressing modes is define as the way in which data is addressed in the
operand part of the instruction. It indicates the CPU finds from where to get data
and where to store results
Ø When a CPU executes an instruction, it needs to know where to get data
and where to store results. Such information is specified in the operand
fields of the instruction.

1000100011000011 MOV AL, BL

Opcode Mode Operand1 Operand2

Ø An operand can be:

— A datum
— A register
— A memory location

DTEL 89
LECTURE 2 Types of Addressing Modes

Addressing Modes Examples

1] Immediate addressing MOV AL, 1FH

2] Register addressing MOV AL, BH
3] Direct addressing MOV [0200H], AH
4] Register Indirect addressing MOV DX, [SI]
5] Relative Based addressing MOV BX, [SI+4]
6] Relative Indexed addressing MOV [DI+8], BL
7] Based indexed addressing MOV [BP+SI], AL
8] Relative Based indexed with displacement addressing MOV AL, [BX+SI+2]

DTEL 90
LECTURE 2 1] Immediate Addressing Mode
In this AM 8/16-bit Data is specified in the operand part of instruction
immediately

• MOV AL,1Fh

• MOV AX,0FC8h

• MOV AH,4Eh

• MOV DX,1F00h

DTEL 91
LECTURE 2 2] Register Addressing
Ø In this data is specified through register in operand part of instruction

Ø Operands are the names of internal register. The processor gets data
from the register specified by instruction .

For Example: move the value of register BL to register AL

MOV AL, BL AH AL

BH BL

q If AX = 1F00H and BX=8086H, after the execution of MOV AL, BL

what are the new values of AX and BX?

DTEL 92
LECTURE 2 3] Direct Addressing
Ø In this AM 16-bit OFFSET address is specified , with symbol [ ] , in the
operand part of the instruction.

ØThe processor will access memory location by adding this OFFSET with
Base address given by DS.

DS × 10H + OFFSET = Memory location

— Example: If DS = 1000H, then explain the operation

MOV AX, 8085 H

DS: 1 0 0 0 _0
MOV [8000H], AX
+ Disp: 8 0 0 0
AH AL 18000
80 85
85 18000H
80 18001H

DTEL 93
LECTURE 2 3] Direct Addressing example
— Example: If DS = 1000H, then explain the operation

1 MOV AX, F2A5 H

MOV [8000H], AH

2 MOV AX, F2A5 H

MOV [8000H], AL

DTEL 94
LECTURE 2 4] Register Indirect Addressing
Ø In this AM OFFSET address is specified indirectly through one of the
registers BX, SI, DI in the instruction operand.
Ø The index register is specified using symbol [ ].
ØThis value is added with DS to generate 20-bit Physical address

For Example: MOV DL, [SI]

Ø Memory address is calculated as following:

BX
DS × 10H + SI = 20-bit Memory address
DI

DTEL 95
LECTURE 2 4] Register Indirect Addressing example

Ø Example 1: assume DS = 0800H then explain the operation

MOV DL, 12H
MOV SI, 2000H DH DL
MOV DL, [SI] 12

0B000H 12
DS: 0 8 0 0 0_
+ SI: 300 0
memory 0 B000

Ø Example 2: assume DS = 0900H, BX=3000H

MOV DL,E7H
MOV [BX], DL

DTEL 96
LECTURE 2 5] Relative Based Addressing
Ø In this AM OFFSET address is specified indirectly by adding an 8-bit (or 16-bit)
constant (displacement) with one of the registers BX, BP in the instruction operand.
Ø If BX appears in the instruction operand field, segment register DS is used in
address calculation and If BP appears in the instruction operand field, segment
register SS is used in address calculation
Ø Calculation of memory address
DS BX
× 10H + + 8/16-bit Displacement = 20-bit Memory address
SS BP

For Example: If DS = 2000H then explain MOV AX, [ BX+4 ]

DTEL 97
LECTURE 2 5]Relative Based Addressing example
Ø Example 1: assume DS = 0100H, BX=0700H
MOV AX, F4E0H
MOV AX, [ BX+4 ] AH AL
C0 B0

DS: 0 1 0 0 0 01705H C0
+ BX: 070 0 01704H B0
+ Disp.: 0 0 0 4
01704 memory

Ø Example 2: assume SS = 0A00H, BP=0012H, CH = ABH

MOV [BP +7], CH

DTEL 98
LECTURE 2 6] Relative Indexed Addressing
Ø In this AM OFFSET address is specified indirectly by adding an 8-bit (or 16-bit)
constant (displacement) with one of the Index registers SI, DI in the instruction
operand. This value is then added with DS to generate 20-bit Physical address
Ø Calculation for memory address
SI
DS × 10H + + 8 / 16 bit Displacement = Memory address
DI

For Example: MOV BL,17H

MOV DI,0030H
Ø Example: assume DS = 0200H MOV [DI+9],BL

MOV [DI+9], BL BH BL
DS: 0 2 0 0 _0 17
+ DI: 003 0 17 02039H
- Disp.: 0 0 0 9
0 203 9

DTEL 99
LECTURE 2 7] Based Indexed Addressing
Ø In this AM OFFSET address is specified indirectly by adding one of the Index
registers SI /DI with based register BX / BP in the instruction operand. This value is
added with DS to generate 20-bit Physical address.
Ø Calculation for memory address
DS BX SI
× 10H + + = 20-bit Memory address
SS BP DI

For Example: MOV [BX] [SI], AH

or
MOV [BX+SI], AH

q If BX appears in the instruction operand field, then segment register DS is used

in address calculation
q If BP appears in the instruction operand field, segment register SS is used in
address calculation

DTEL 100
LECTURE 2 7] Based Indexed Addressing example
Ø Example 1: assume SS = 2000H explain the operation
MOV AH,07H
MOV SI, 0800H
MOV BP,4000H AH AL
MOV [BP] [SI], AH 07

SS: 2 0 0 0 0_ 24800H 07
+ BP: 4 0 0 0
+ SI.: 080 0
24800 memory

Ø Example 2: assume DS = 0B00H, BX=0112H, DI = 0003H, CH=ABH

MOV [BX+DI], CH

DTEL 101
LECTURE 2 8] Relative Based Indexed Addressing
Ø In this AM OFFSET address is specified indirectly by adding 8/16-bit
displacement with one of the Index registers SI /DI with based register BX / BP in
the instruction operand. This value is added with DS to generate 20-bit Physical
address.
Ø Calculate memory address
DS BX SI 8/16-bit
× 10H + + +
displacement
SS BP DI

For Example: MOV CL, [BX+DI+2080H]

DTEL 102
LECTURE 2 8] Relative Based Indexed Addressing example

Ø Example 1: assume DS = 0300H, BX=1000H, DI=0010H

MOV BX,1000H
MOV DI, 0010H
MOV CL, [BX+DI+2080H] CH CL
20

DS: 0 3 0 0 0_
+ BX: 1 0 0 0 06090H 20
+ DI.: 0010
+ Disp. 2 0 8 0
memory
06090

Ø Example 2: assume SS = 1100H, BP=0110H, SI = 000AH, CH=ABH

MOV [BP+SI+0010H], CH

DTEL 103
LECTURE 2 Instruction Types
1] Data transfer instructions
2] Arithmetic instructions
3] String instructions
4] Bit manipulation instructions
5] Loop and jump instructions
6] Subroutine and interrupt instructions
7] Processor control instructions

DTEL 104
LECTURE 2 1] Data transfer instructions

Various Data transfer Instructions are

a) Memory/Register Transfers
MOV Move byte or word to register or memory
XCHG Exchange byte or word
XLAT Translate byte using look-up table

b) Stack Transfers
PUSH Push data onto stack
PUSHF Push flags onto stack
POP Pop data from stack
POPF Pop flags off stack

c) AH/Flags Transfers
LAHF Load AH from flags
SAHF Store AH into flags

DTEL 105
LECTURE 2 1] Data transfer instructions

d) Address Translation
LEA Load effective address
LDS Load pointer using data segment
LES Load pointer using extra segment

e) Port I/O Instructions

IN Input byte or word from port
OUT Output word to port

DTEL 106
LECTURE 4 2] Arithmetic Instructions
Addition
ADD Add byte or word
ADC Add byte or word with carry
INC Increment byte or word by 1
AAA ASCII adjust for addition
DAA Decimal adjust for addition
Subtraction
SUB Subtract byte or word
SBB Subtract byte or word with borrow
DEC Decrement byte or word by 1
NEG Negate byte or word
AAS ASCII adjust for subtraction
DAS Decimal adjust for subtraction
Multiplication
MUL Multiply byte or word unsigned
IMUL Integer multiply byte or word
AAM ASCII adjust for multiplication
Division
DIV Divide byte or word unsigned
IDIV Integer divide byte or word
AAD ASCII adjust for division
CBW Convert byte to word
CWD Convert word to double word

DTEL 107
LECTURE 4 3] Bit Manipulation Instructions
a) Logical Instructions
q NOT Destination
§ Inverts each bit of the destination
§ Destination can be a register or a memory location
q AND Destination, Source
§ Performs logic AND operation for each bit of the destination with corresponding
source bit and stores result into destination
§ Source can be immediate no while destination can be register or memory
§ Destination and source can not be both memory locations at the same time

q OR Destination, Source
§ Performs logic OR operation for each bit of the destination with source; stores
result into destination
§ Source can be immediate no while destination can be register or memory
§ Destination and source can not be both memory locations at the same time

DTEL 108
LECTURE 4 3] Bit Manipulation Instructions
a) Logical Instructions

q XOR Destination, Source

§ Performs logic XOR operation for each bit of the destination with source; stores
result into destination
§ Source can be immediate no while destination can be register or memory
§ Destination and source can not be both memory locations at the same time

q TEST Destination, Source

§ Performs logic AND operation for each bit of the destination with source
§ Updates Flags depending on the result of AND operation
§ Do not store the result of AND operation anywhere

DTEL 109
LECTURE 4 3] Bit Manipulation Instructions
b) Shift Instruction
q SHL Destination, Count
§ SHift LEFT destination bits; the number of times bits shifted is given by CL
§ During the shift operation, the MSB of the destination is shifted into CF and
zero is shifted into the LSB of the destination
§ Destination can be a register or a memory location

CF Destination 0
MSB LSB

q SHR Destination, Count

§ SHift RIGHT destination bits; the number of times bits shifted is given by CL
§ During the shift operation, the LSB of the destination is shifted into CF and
zero is shifted into the MSB of the destination
§ Destination can be a register or a memory location

0 Destination CF
MSB LSB

DTEL 110
LECTURE 4 3] Bit Manipulation Instructions
b) Shift Instructions
q SAR Destination, Count
§ Shift RIGHT destination bits; the number of times bits shifted is given by CL
§ The LSB of the destination is shifted into CF and the MSB of the destination
is copied in the MSB itself i.e, it remains the same
§ Destination can be a register or a memory location

Destination CF
MSB LSB

DTEL 111
LECTURE 4 3] Bit Manipulation Instructions
c) Rotate Instructions
q ROL Destination, Count
§ Left shift destination bits; the number of times bits shifted is given by CL
§ The MSB of the destination is shifted into CF, it is also rotated into the LSB .
§ Destination can be a register or a memory location
MSB LSB
CF Destination

q ROR Destination, Count

§ Right shift destination bits; the number of times bits shifted is given by CL
§ The LSB of the destination is shifted into CF, it is also rotated into the MSB .
§ Destination can be a register or a memory location

MSB LSB
Destination CF

DTEL 112
LECTURE 4 3] Bit Manipulation Instructions
c) Rotate Instructions
q RCL Destination, Count
§ Left shift destination bits; the number of times bits shifted is given by CL
§ The MSB of the destination is shifted into CF; the old CF value is rotated into the LSB.
§ Destination can be a register or a memory location
MSB LSB
CF Destination

q RCR Destination, Count

§ Right shift destination bits; the number of times bits shifted is given by CL
§ The LSB of the destination is shifted into CF, the old CF value is rotated into the MSB.
§ Destination can be a register or a memory location

MSB LSB
Destination CF

DTEL 113
LECTURE 5 4] String Instructions
q String is a collection of bytes or words stored in successive memory locations of
DMS or EMS that can be up to 64KB in length .
q String instructions can have two operands. One is source string and the second is
destination string .
§ Source string is located in Data Segment and SI register points to the current
element of the source string
§ Destination string is located in Extra Segment and DI register points to the
current element of the destination string
DS : SI ES : DI
0510:0000 5F 02A8:2000 5F
0510:0001 4E 02A8:2001 4E
0510:0002 4A 02A8:2002 4A
0510:0003 5B 02A8:2003 5B
0510:0004 D0 02A8:2004 D0
0510:0005 CA 02A8:2005 CA
0510:0006 55 02A8:2006 55
Source String Destination String

DTEL 114
LECTURE 5 4] String Instructions
Repeat Prefix Instructions
q REP String Instruction
— The prefix instruction repeatedly execute the instruction until CX AUTO-decrements to 0
(During the execution, CX is decremented by one after execution of the string instruction ).

— For Example: MOV CX, 09

REP MOVSB

By the above two instructions, the microprocessor will execute MOVSB 9 times.

— Execution flow of REP MOVSB is as below:

While (CX!=0) Check_CX: If CX!=0 Then

{ CX = CX –1;
CX = CX –1; OR MOVSB;
MOVSB; goto Check_CX;
} next instruction

DTEL 115
LECTURE 5 4] String Instructions
Repeat Prefix Instructions

q REPZ String Instruction

§ Repeatedly execute the string instruction until CX=0 OR zero flag is clear

q REPNZ String Instruction

§ Repeatedly execute the string instruction until CX=0 OR zero flag is set

q REPE String Instruction

§ Repeatedly execute the string instruction until CX=0 OR zero flag is clear

q REPNE String Instruction

§ Repeatedly execute the string instruction until CX=0 OR zero flag is set

DTEL 116
LECTURE 6 4] String Instructions
q MOVSB (MOVSW)
§ Move a byte (word) at source memory location of DMS (DS:SI) to destination
memory location (ES:DI) and update SI and DI according to status of DF.
§ After transfer Increment SI/DI by 1 ( or 2) if DF=0 and Decrement SI/DI if
DF=1.

Example: DS : SI ES : DI
MOV AX, 0510H 0510:0000 5E 0300:0100 5E
MOV DS, AX 0510:0001 48 0300:0101 ?
MOV SI, 0 0510:0002 4F 0300:0102 ?
MOV AX, 0300H 0510:0003 50 0300:0103 ?
MOV ES, AX 0300:0104
0510:0004 50 ?
MOV DI, 100H
0510:0005 45
CLD
MOV CX, 5
0510:0006 52
REP MOVSB Source String Destination String
INT 21

DTEL 117
LECTURE 6 4] String Instructions
q MOVSB (MOVSW)
§ Move a byte (word) at source memory location of DMS (DS:SI) to destination
memory location (ES:DI) and update SI and DI according to status of DF.
§ After transfer Increment SI/DI by 1 ( or 2) if DF=0 and Decrement SI/DI if
DF=1.
§ Example:
DS : SI ES : DI
MOV AX, 0510H 0510:0000 5E 0300:0100 5E
MOV DS, AX 0510:0001 48 0300:0101 48
MOV SI, 0 0510:0002 4F 0300:0102 4F
MOV AX, 0300H 50 0300:0103 50
0510:0003
MOV ES, AX
0510:0004 50 0300:0104 50
MOV DI, 100H
0510:0005 45
CLD
MOV CX, 5 0510:0006 52
REP MOVSB Source String Destination String
INT 21

DTEL 118
LECTURE 6 4] String Instructions
q CMPSB (CMPSW)

§ Compare bytes (words) at memory locations DS:SI and ES:DI;

update SI and DI according to DF and the width of the data being compared
§ Example:
Assume: ES = 02A8H
DI = 2000H
DS = 0510H DS : SI ES : DI
SI = 0000H 0510:0000 4D M 02A8:2000 4D M
0510:0001 4A J 02A8:2001 4A J
0510:0002 45 E 02A8:2002 45 E
CLD 0510:0003 54 54
T 02A8:2003 T
MOV CX, 7 48 H H
0510:0004 02A8:2004 48
REPZ CMPSB 0510:0005 57 W 02A8:2005 57 W
INT 21
0510:0006 41 A 02A8:2006 4E N
What will be the values of CX after Source String Destination String
The execution?

DTEL 119
LECTURE 6 4] String Instructions
q SCASB (SCASW)
§ Compare byte in AL (or word in AX) with data at memory location ES:DI;
It updates DI depending status of DF and the length of the data being compare

q LODSB (LODSW)
§ Load byte (word) at memory location DS:SI to AL (AX);
It updates SI depending status of DF and the length of the data being transferred

q STOSB (STOSW)
§ Store byte (word) at in AL (AX) to memory location ES:DI;
It updates DI depending status of DF and the length of the data being transferred

DTEL 120
LECTURE 7 5] Program Transfer Instructions unconditional

q JMP Label
§ Unconditionally Jump to specified Label or address location.
§ Label can be represented by a word or Alphabet with no.

MOV CX, 0007h

MOV AX,F2FEh
ADD AH,CL
JMP L1 Current
SUB AH,CL instruction
JMP
L1: MOV [0200],AH
INT21
Jump

Next
instruction

DTEL 121
LECTURE 7 5] Program Transfer Instructions conditional

Ø Conditional Jumps
q JZ: Label_1
§ If ZF =1, jump to the target address labeled by Label_1; else do not jump

q JNZ: Label_1
§ If ZF =0, jump to the target address labeled by Label_1; else do not jump

Ø Other Conditional Jumps

JNC JAE JNB JC JB JNAE JNG

JNE JE JNS JS JNO JO JNP
JPO JP JPE JA JBNE JBE JNA
JGE JNL JL JNGE JG JNLE JLE

DTEL 122
LECTURE 8 5] Program Transfer Instructions conditional

Mnemonic Meaning Jump Condition

JA Jump if Above CF = 0 and ZF = 0
JAE Jump if Above or Equal CF = 0
JB Jump if Below CF = 1
JBE Jump if Below or Equal CF = 1 or ZF = 1
JC Jump if Carry CF = 1
JE Jump if Equal ZF = 1
JNC Jump if Not Carry CF = 0
JNE Jump if Not Equal ZF = 0
JNZ Jump if Not Zero ZF = 0
JPE Jump if Parity Even PF = 1
JPO Jump if Parity Odd PF = 0
JZ Jump if Zero ZF = 1

DTEL 123
LECTURE 9 5] Program Transfer Instructions (Looping)

q LOOP Label CX = CX –1
If CX != 0 Then
JMP Label else
Next Instruction

CX = CX –1
q LOOPE/LOOPZ Label If CX != 0 & ZF=1 Then
JMP Label else
Next Instruction

q LOOPNE/LOOPNZ Label
CX = CX –1
If CX != 0 & ZF=0 Then
JMP Label else
Next Instruction

DTEL 124
LECTURE 10 6] Processor Control Instructions
q CLC Clear carry flag
q STC Set carry flag
q CMC Complement carry flag
q CLD Clear direction flag
q STD Set direction flag
q CLI Clear interrupt-enable flag
q STI Set interrupt-enable flag

q HLT Halt microprocessor operation

q NOP No operation
q LOCK Lock Bus During Next Instruction

DTEL 125
LECTURE 10 7] Subroutine Instructions
Ø A subroutine or procedure is a collection of instructions, written
separately from main program, and can be called from a program.
Ø Instruction used is CALL Procedure-Name
Ø RET instruction lets the microprocessor to return from a subroutine to the called
program.
Example
•••
MOV AL, 1
CALL M1
MOV BL, 3 The order of execution will be :
••• MOV AL, 1
MOV CL, 2
MOV BL, 3
M1 PROC
MOV CL, 2
RET
M1 ENDP

DTEL 126
LECTURE 11 Chapter 3 Question Bank
• What Opcode & Operand?
• List various Instructions of 8086.
• Describe the Data transfer Instruction.
• Describe the Arithmetic Instruction.
• Describe the Data Bit manipilation Instruction.
• Explain Various Program control Instruction.
• Describe the Processor Control Instruction.
• What Adressing mode ?
• Explain various Adressing modes of 8086.

DTEL 127
LECTURE 12 Summary
1. Addressing modes is define as the way in which data is addressed in the
operand part of the instruction. It indicates the CPU finds from where to get data
and where to store results.

2. 8086 has 8 Adressing modes a] Immediate addressing b] Register addressing

c] Direct addressing d] Register Indirect addressing e] Relative Based
f] Relative Indexed addressing g] Based indexed addressing h] Relative Based
indexed with displacement addressing

3. 8086 Instructions cab be grouped as ,

1] Data transfer instructions
2] Arithmetic instructions
3] String instructions
4] Bit manipulation instructions
5] Loop and jump instructions
6] Subroutine and interrupt instructions
7] Processor control instructions

DTEL 128
 CHAPTER-4 The Art of Assembly Language Programming

1 .
Topic 1: Program development steps

2 Topic 2: Assembly Language Programming Tools

3 Topic 3: Assembler directives and Operators

DTEL 129
 CHAPTER-4 SPECIFIC OBJECTIVE / COURSE OUTCOME

The student will be able to:

Know the program development steps

1

Use the different program development tools

2

DTEL 130
LECTURE 1 INTRODUCTION TO ASSEMBLY PROGRAMMING

A programme is nothing but set of Instructions written sequentially one

below the other and stored in computers memory for execution by
microprocessor.

Instruction consists of a mnemonic and one or two operands (data).

Ø Machine Language: In this Programs is written in 0s and 1s.

Ø Assembly Languages : It uses short form notations , called ,

mnemonics , to write a programme .The Mnemonics are like MOV , ADD
, SUB, etc.

Ø High level languages: It uses English like sentences with proper

syntax to write a programme.

Ø Assembler translates Assembly language program into machine

code.

DTEL 131
LECTURE 1 INTRODUCTION TO ASSEMBLY PROGRAMMING

Conversion from HLL to ML is

Done by Compiler / Interpreter

HIGH LEVEL

ASSEMBLY LEVEL

MACHINE
LEVEL

Conversion from ALL to ML

is Done by Assembler like
MASM

DTEL 132
LECTURE 2 Assemble, Link and execute Program

Step & Input Software Output

operation
1.Editing / Note pad or Note pad / Filename.asm
writing Word MS-Word
programme
2.Assemble Filename.asm MASM Filename.obj

3.Link Filename.obj LINK Filename.exe

DTEL 133
LECTURE 2 How to Build Executable Programs

Filename.obj
Assembler
checks syntax
Executable
Editor and translate
File
programme like source code Linker filename.exe
note-pad / Word into machine
code (like
MASM)
Other Debug or
OBJ
files & code view
Filename.asm Library if any error

DTEL 134
LECTURE 3 How to Build Executable Programs
Editor
A text editor is required in order to create assembly language
source files, where you’ll be writing your code. You can use
Notepad, DOS editor, or any other editor of your choice that
produces plain ASCII text files.

Debugger
A debugger program allows tracing of program execution and
examination of registers and memory content.
For 16-bit programs, MASM’s debugger named CodeView can be
used to debug .

DTEL 135
LECTURE 3 Assembler

Source files Assembler

Syntax check OBJ
Translate source files
files into
machine code

An assembler is a program that converts source-code programs

written in assembly language into object files in machine
language. Popular assemblers include MASM (Macro Assembler
from Microsoft), TASM (Turbo Assembler from Borland), NASM
(Netwide Assembler for both Windows and Linux), and GNU
assembler distributed by the free software foundation.

DTEL 136
LECTURE 3 Linker

library Executable
Source files Assembler files
Syntax check
Translate source
OBJ
files
Linker
files into
machine code

OBJ
files

A linker program combines your program's object file created by the assembler
with other object files and link libraries, producing a single executable
program. You need a linker utility to produce executable files.
Two linkers: LINK.EXE and LINK32.EXE are provided with the MASM 6.15
distribution to link 16-bit real-address mode and 32-bit protected-address
mode programs respectively.

DTEL 137
LECTURE 3 Assembler Directives

It provides information to assist the assembler in producing

executable code. It creates storage for a variable and initialize it.
Assembler directives (pseudo-instructions) give directions to the
assembler about how it should translate the Assembly language
instructions into machine code, Where as other instructions
discussed in the above section give command to the 8086
microprocessor. Assembler directives are specific for a particular
assembler. However all the popular assemblers like the Intel 8086
macro assembler, the turbo assembler and the IBM macro
assembler use common assembler directives. The basic structure
of a program in ASM will look like this

DTEL 138
Lecture 4 Program format
; Program for addition of two 8-bit nos. Comments / Remark

ASSUME CS: Code DS: Data

Data SEGMENT
N1 DB 2FH
N2 DB 0EH Assembler directives
SUM DB 1 DUP(?)
Data ENDS

Code SEGMENT
MOV AL,N1
MOV BL,N2 Program
ADD AL,BL
MOV SUM,AL

Code ENDS Assembler directives

END

DTEL 139
LECTURE 4 ASSUME

1) The ASSUME directive tells the assembler the name of the

logical segment it should use for a specified segment. It
associates segment names with segment registers. For example
ASSUME CS: Code tells assembler that the
instructions for programme are in the logical segment named
Code.
Similarly for
ASSUME DS: Data tells assembler that for
any program if instruction refers to the data segment then it
should use the logical segment named Data. For example in the
instruction MOV AX, [BX] the memory segment referred to by
[BX] is in logical segment Data.

DTEL 140
LECTURE 4 ASSUME
The 8086 contains a segment register (DS) that is dedicated to a
data memory segment. This register is the default segment register
used for all memory references used for data. The user is
responsible loading the DS register with the appropriate value and
telling the assembler where the DS register points so that it can
calculate the offsets correctly. The standard is to define a segment
to be a data segment. This is a convenient way of keeping data and
code separate. The most common way of doing this is:
Data SEGMENT
...
Data ENDS ;indicates the end of the data segment

Hence the Assume directive is required to inform assembler of

location of DS pointer by : ASSUME DS: Data;

DTEL 141
LECTURE 4 Data directive
2) Data storage directive
Each variable has a data type and is assigned a memory address by
the program. Data directives are used to reserve and provide name
for memory location in data segments. The symbols used for data
types are:
Data type Symbol
Byte B
Word W
Double word D
Quad Word Q
Ten Bytes T

DTEL 142
LECTURE 4 Data directive Example
For byte variable we should use
ü DB for declaration

N1 DB 4 ; initialise variable N1 with value 4 in decimal

N2 DB AFH ; initialise variable N2 with value AF in Hex
Name DB “JETHWA” ; allocates 6 byte with variable Name

J 4A Name
E 45
T 54
H 48
W 57
A 41

DTEL 143
LECTURE 4 DUP Operator
DUP Operator is used to create arrays of elements whose initialize
value is same.

The basic syntax is count DUP ( initial value)

Example :
N1 DB 100 DUP( 0) ; create 100 bytes arrays with value 0 in each

N2 DW 5 DUP (?) ; CREATE 5 arrays of uninitialized words

L1 DB 5, 4, 3 DUP( 2,3 DUP(0),1) is same as

L1 DB 5,4,2,0,0,0,1,2,0,0,0,1,2,0,0,0,1

DTEL 144
LECTURE 5 Chapter 4 Question Bank
• What is Machine language?
• What is Assembly language?
• What is High level language?
• Describe the function of Linker.
• Describe the function of Assembler & debugger.
• What is Assemble directives?
• Explain various Assemble directives.

DTEL 145
LECTURE 5 Summary
1. A programme is nothing but set of Instructions written sequentially one below the other
and stored in computers memory for execution by microprocessor. Program can be written
in 3 levels a) Machine Language b) Assembly Languages c) High level languages
2. Assembler translates Assembly language program into machine code.
3. Compilers like Pascal, Basic, C etc translate the HLL program into machine code.
The programmer does not have to be concerned with internal details of the CPU.
4. A text editor is required in order to create assembly language source files, where you’ll be writing
your code. You can use Notepad, DOS editor, or any other editor of your choice that produces lain
ASCII text files.
5. A debugger program allows tracing of program execution and examination of registers and
memory content.
6. An assembler is a program that converts source-code programs written in assembly
language into object files in machine language.
7. A linker program combines your program's object file created by the assembler with
other object files and link libraries, producing a single executable program. You need
a linker utility to produce executable files.
8. Assembler directives provides information to assist the assembler in producing
executable code. It creates storage for a variable and initialize it. Assembler directives
(pseudo-instructions) give directions to the assembler about how it should translate the
Assembly language instructions into machine code

DTEL 146
 CHAPTER-5 8086 Assembly Language Programming.

Topic 1: Model of 8086 assembly language programs

1 .

Topic 2: Programming using assembler -

2

DTEL 147
 CHAPTER-5 SPECIFIC OBJECTIVE / COURSE OUTCOME

The student will be able to:

Write a appropriate programs using editor

1

Run program using assembler & linker and Debug program

2 using debugger

DTEL 148
Lecture 1 Program for 8-bit addition
; Program for addition of two 8-bit nos. Comments / Remark

ASSUME CS: Code DS: Data

Data SEGMENT
N1 DB 2FH
N2 DB 0EH
SUM DB 1 DUP(?)
Data ENDS

Code SEGMENT
MOV AX, Data
MOV DS,AX
MOV AL,N1
MOV BL,N2
ADD AL,BL
MOV SUM,AL
Code ENDS
END

DTEL 149
Lecture 2 Program for 16-bit addition
; Program for addition of two 16-bit nos. Comments / Remark

ASSUME CS: Code DS: Data

Data SEGMENT
N1 DW 002FH
N2 DW 000EH
SUM DW 1 DUP (?)
Data ENDS

Code SEGMENT
MOV AX, Data
MOV DS,AX
MOV AX,N1
MOV BX,N2
ADD AX,BX
MOV SUM,AX
Code ENDS
END

DTEL 150
Lecture 3 Program for 16-bit Multiplication
; Program for MULTIPLICATION of two 16-bit nos. Comments / Remark

ASSUME CS: Code DS: Data

Data SEGMENT
N1 DW 002FH
N2 DW 000EH
RES DW 2 DUP (?)
Data ENDS
Code SEGMENT
MOV AX, Data
MOV DS,AX
MOV AX,N1
MOV BX,N2
MUL BX
MOV RES,AX
MOV RES+2,BX
Code ENDS
END

DTEL 151
Lecture 4 Program for 16-bit Division
; Program for DIVISION of 16-bit no. Comments / Remark

ASSUME CS: Code DS: Data

Data SEGMENT
N1 DW 0F2FH
N2 DB 0EH
RESQ DB 2 DUP (?)
Data ENDS
Code SEGMENT
MOV AX, Data
MOV DS,AX
MOV AX,N1
MOV BL,N2
DIV BL
MOV RESQ,AL
MOV RESQ+1,AH
Code ENDS
END

DTEL 152
Lecture 5 Program for 32-bit Division
; Program for DIVISION of 32-bit no. Comments / Remark
ASSUME CS: Code DS: Data
Data SEGMENT
N1 DD FE000F2FH
N2 DW E40EH
RESQ DW 2 DUP (?)
Data ENDS
Code SEGMENT
MOV AX, Data
MOV DS,AX
MOV AX,N1
MOV DX,N1+2
MOV BX,N2
DIV BX
MOV RESQ,AX
MOV RESQ+2,DX
Code ENDS
END

DTEL 153
LECTURE 6 Chapter 5 Question Bank
• Write program to transfer a block of 50 bytes B1 to another
block B2.The block B1 begins with offset address 1000h and
block B2 from 2000h?
• Write program to exchange data of block of 10 bytes B1 to with
another block B2.The block B1 begins with offset address
0200h and block B2 from 0300h?
• Write program to arrange a block of 50 bytes in ascending
order. The block begins with offset address 1000h?
• Write program to arrange a block of 50 bytes in descending
order. The block begins with offset address 1000h?

DTEL 154
 CHAPTER-6 Procedure and Macro in Assembly Language Program

1 .
Topic 1: Procedure

2 Topic 2: Defining Macros.

DTEL 155
 CHAPTER-6 SPECIFIC OBJECTIVE / COURSE OUTCOME

The student will be able to:

Understand the purpose of procedure and macros

1

Use procedure and macros

2

DTEL 156
LECTURE 1 Procedures
Procedure is a part of code that can be called from your
program in order to make some specific task. Procedures make
program more structural and easier to understand. Generally
procedure returns to the same point from where it was called.

The syntax for procedure declaration:

name PROC

; here goes the code

; of the procedure ...

RET
name ENDP

DTEL 157
LECTURE 1 Procedures
name - is the procedure name, the same name should be in the top and the
bottom, this is used to check correct closing of procedures.

RET instruction is used from procedure

PROC and ENDP are compiler directives, so they are not assembled into any
real machine code. Compiler just remembers the address of procedure.

CALL instruction is used to call a procedure.

DTEL 158
LECTURE 1 Procedures example
ORG 100h
MOV AL,2FH
MOV BL,F2H
CALL m1
MOV [SI] , AX
RET ; return to operating system.

Procedure for multiplication

m1 PROC
MUL BL
RET ; return to caller.
m1 ENDP
END

DTEL 159
LECTURE 1 Procedures example
There are several ways to pass parameters to procedure, the easiest way to pass
parameters is by using registers, here is another example of a procedure that
receives two parameters in AL and BL registers, multiplies these parameters and
returns the result in AX register:
ORG 100h
MOV AL, 1
MOV BL, 2
CALL m2 In this example value of AL register
CALL m2 is update every time the procedure is
called, BL register stays unchanged,
CALL m2
so this algorithm calculates 2 in
CALL m2 power of 4,
RET ; return to operating
system. so final result in AX register is 16 (or
10h).

m2 PROC
MUL BL ; AX = AL * BL.
RET ; return to caller.
m2 ENDP
END
DTEL 160
LECTURE 1 NEAR CALL & FAR CALL

A near CALL is a call to a procedure which is in the same code

memory segment as that of CALL instruction in this the 8086
decrements Stack pointer by 2 and copies the IP on the
STACK.

A far CALL is a call to a procedure which is in different code

segment as that of CALL instruction. . In this the 8086
decrements Stack pointer by 2 and copies the CS first on the
STACK and then again decrement SP by 2 to copy IP on the
STACK.

DTEL 161
LECTURE 2 Recursive Procedure
Recursive Procedure: A recursive procedure is procedure which calls itself. It is
used to work with complex data structures called trees. If the procedure is called
with N (known as recursion depth) =3 then the n is decremented by 1 after each
procedure CALL and the procedure is called until n=0 as shown in the diagram
below:

Main P Proc Fact Proc Fact Proc Fact

CALL CALL CALL

RET RET RET

With 3! With 2! With 1!

DTEL 162
LECTURE 2 To find out factorial of number
;Program to find out factorial of number Using Recursion
Data SEGMENT
NUMBER DB 03H
FACTORIAL DW 1DUP(?)
ENDS

Stack SEGMENT
DW 128 DUP(0)
ENDS

Code SEGMENT
ASSUME CS:Code, DS:Data, SS:Stack
; INITIALISE SEGMENT REGISTERS:
MOV AX, Data
MOV DS, AX
MOV AX, Stack
MOV SS, AX

MOV CX,NUMBER
CALL FACT
RET

DTEL 163
LECTURE 2 To find out factorial of number

;PROCEDURE FOR FACTORIAL PROGRAM

;CX CONTAINS INPUT NUMBER
;DX CONTAINS RESULT
FACT PROC NEAR
CMP CX, 01H
JNE CONT
MOV DX,01H
RET
CONT: PUSH CX ; FOR BACKUP
DEC CX
CALL FACT
POP AX ; BACKUP OF CX IE N
MUL DX ; N*(N-1)!
MOV DX, AX ; RESULT INTO DX
RET
FACT ENDP
ENDS

DTEL 164
LECTURE 3 Reentrant Procedure
Reentrant Procedure: A program or subroutine is called reentrant
if it can be interrupted in the mid (i.e. the control flow is
transferred outside of the subroutine, either due to an internal
action such as a jump or call, or by an external action such as a
hardware interrupt or signal), and then can then safely be called
again before its previous invocation has been completed, and once
the reentered invocation completes, the previous invocations
should be able to resume execution correctly.
If procedure1 is called from main program and procedure2 is
called from procedure1 and procedure1 again from procedure2
then such is called as reentrant procedure as shown below:

DTEL 165
LECTURE 3 Macros
Macros
Macros are just like procedures, but not really. Macros look
like procedures, but they exist only until your code is
compiled, after compilation all macros are replaced with real
instructions. For Macro assembler generates the code in
program each time where the macro is “called”. If you
declared a macro and never used it in your code, compiler will
simply ignore it.

Macro definition:
name MACRO
[parameters,...]
<instructions>
ENDM

DTEL 166
LECTURE 3 Macros example
MyMacro MACRO p1, p2, p3
MOV AX, p1
MOV BX, p2
MOV CX, p3
ENDM

ORG 100h
MyMacro 1, 2, 3
The code is expanded into:
MyMacro 4, 5, DX
RET MOV AX, 00001h
MOV BX, 00002h
MOV CX, 00003h
MOV AX, 00004h
MOV BX, 00005h
MOV CX, DX

DTEL 167
LECTURE 4 Compare Procedure & Macro
Procedure Macro
Accessed during assembly with
Accessed by CALL & RET
name given during program
instruction
execution to macro when defined
Machine code for
Machine code is generated for
instruction is put only
instruction each time when macro is
once in the memory
called.

With procedures
With macro more memory is
less memory is required
required

Parameters can be passed

Parameters passed as part of
in registers,
statement which calls macro
memory locations or stack

DTEL 168
LECTURE 5 Advantages and Disadvantages of MACRO

Advantages of MACRO
üProgram written with MACRO is more readable
üMACRO can be called by just writing its name along with its
parameters;
hence no extra code is required like CALL & RET.
üExecution time is less as compared to Procedure
üFinding errors is easy

Disadvantages of MACRO
üObject code is generated every time Macro is called, hence
object file
becomes lengthy
üFor large group of instruction macro is not preferred

DTEL 169
LECTURE 5 Chapter 6 Question Bank
• What is Procedures?
• What are the instructions to implement Procedures?
• What is Re-entrant Procedures?
• Describe the function MACROS.
• What are the differences between Procedures & MACROS.
• List various Advantages and disadvantages of MACROS.

DTEL 170
LECTURE 5 Summary
1. Procedure is a part of code that can be called from your program in order to make some specific
task. Procedures make program more structural and easier to understand. Generally procedure
returns to the same point from where it was called. CALL instruction is used to call a procedure.

2. A near CALL is a call to a procedure which is in the same code memory segment as that of CALL
instruction in this the 8086 decrements Stack pointer by 2 and copies the IP on the STACK.

3. A far CALL is a call to a procedure which is in different code segment as that of CALL instruction. . In
this the 8086 decrements Stack pointer by 2 and copies the CS first on the STACK and then again
decrement SP by 2 to copy IP on the STACK.

4. Reentrant Procedure: A program or subroutine is called reentrant if it can be interrupted in the

middle (i.e. the control flow is transferred outside of the subroutine, either due to an internal action
such as a jump or call, or by an external action such as a hardware interrupt or signal), can then
safely be called again before its previous invocations have been completed, and once the reentered
invocation completes, the previous invocations should be able to resume execution correctly.

5. Macros are just like procedures, but not really. Macros look like procedures, but they exist only
until your code is compiled, after compilation all macros are replaced with real instructions. For
Macro assembler generates the code in program each time where the macro is “called”. If you
declared a macro and never used it in your code, compiler will simply ignore it.

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 Recommended Books:
1. Advanced Microprocessor and Peripherals (Architecture, Programming
& Interfacing) by A.K. Roy & K.M. Bhurchandi, Tata Mcgraw Hill
2. Fundamentals of MIcroprocessors by B RAM, Dhanpat Rai Publications
3. Microprocessors by A.P.Godse, Technical Publications
4. 8085 Microprocessor: Programming And Interfacing 1st Edition
Author: N.K.Srinath, PHI Learning Private Limited
5. Microprocessor 8085 And Its Interfacing, Author A.P.Mathur , PHI
Learning Pvt. Ltd.
6. The 8088 and 8086 Microprocessors: , Author: Walter A. Triebel, Avtar
Singh,
7. Microprocessor 8085, 8086 , by Abhishek Yadav
8. Microprocessors: Theory and Applications : Intel and Motorola
by Mohamed Rafiquzzaman
9. “Microcomputer Systems: The 8086/88 Family”, Liu, Gibson, 2nd
Edition, PHI Learning Private Limited

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 References Books:
1. Microprocessor Architecture,Programming and Applications with the 8085
by Ramesh S. Gaonkar , Penram International Publishing (India)
2. Microprocessor & interfacing (programming & hardware) Revised Second
Edition by Douglas V. Hall , Tata McGraw Hill
3. The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386
Barry Bray , Pearson Education; Eighth edition (2011)
4. The 8086/8088 Family: Design, Programming And Interfacing 1st Edition,
John Uffenbeck, Prentice-Hall
5. Microcomputer Systems the 8086/8088 Family : Architecture,
Programming and Design 2nd Edition Author: Gleen A.Gibson , Prentice-
Hall
6. 8085 Microprocessor: Programming And Interfacing 1st Edition
Author: N.K.Srinath, PHI Learning Private Limited
7. The 8086 Microprocessor :Programming & Interfacing the PC with CD
Kenneth Ayala, Publisher: Cengage Learning
8. Assembly programming and the 8086 microprocessor, Douglas Samuel
Jones ,Oxford University Press

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 References Web:

1. www.intel.com
2. www.pcguide.com/ref/CPU
3. www.CPU-World.com /Arch /
4. www.techsource .com / Engineering parts/ microprocessor.html
5. www.slideshare.net
6. www.powershow.com
7. www.authorstream.com
8. www.youtube.com
9. www.scribd.com
10. www.eazynotes.com
11. www.electronicstutorialsblog.com
12. ece.uprm.edu

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