Virtual-Flux Decoupling Hysteresis Control for the

Five-Level ANPC Inverter Connected to the Grid

L. A. Serpa∗, P. K. Steimer† and J. W. Kolar‡
∗ ABBCorporate Research
Power Electronics Applications, Dätwill, Switzerland
Email: leonardo-augusto.serpa@ch.abb.com
† ABB Switzerland Ltd.
Power Electronics and MV Drives, Turgi, Switzerland
‡ Swiss Federal Institute of Technology - ETH

Power Electronics Systems Laboratory, Zürich, Switzerland

Abstract—Interest in multilevel power converters has been their application by the industry. Recently, a new converter
increased in the last decades due to numerous advan- topology has been introduced [3] to overcome some of the
tages.Therefore, new control concepts have to be developed or above mentioned limitations. The five-level active neutral-
existing control techniques must be extended to take advantage
of these benefits.However, although multilevel inverters present point clamped (ANPC) converter combines characteristics of
numerous advantages, some drawbacks are evident. They re- the NPC and FC inverters.
quire a higher number of semiconductors and either multiple However, as new multilevel topologies are proposed, either
isolated dc sources or a bank of series connected capacitors. new control techniques must be developed or existing control
Consequently, the control complexity increases considerably, methods have to be adapted. Among the existing methods the
since more switching devices normally result in a higher number
of possible combinations and the balance of the capacitors has Virtual-Flux Decoupling Hysteresis Control (VF-DHC) has
to be guaranteed. In order to fulfill these requirements, this shown a good performance for the two [4] and the three-level
paper extends the Virtual-Flux Decoupling Hysteresis Control [5] topologies. It combines the simplicity and fast dynamic
(VF-DHC) scheme previously presented for the classical two- response of the classical hysteresis controller to a near con-
level and the industry standard three-level NPC inverters to stant switching frequency operation achieved by employing
operate with the recently introduced five-level Active Neutral-
Point Clamped Inverter (ANPC). a decouple network and modulated hysteresis boundaries.
The decouple network is applied to avoid the interference
I. I NTRODUCTION between phases that is inherent in isolated neutral three-
For low power systems, the classical two-level inverter phases systems.
is typically employed as the interface between dc-supply The VF-DHC to operate with the five-level ANPC inverter
and load. However, modern applications, which range from proposed in this paper is a natural extensions of the two
hundreds of kilowatts up to a few megawatts, demand special and three-level approaches. However, the hysteresis strategies
converter structures. One alternative is to connect switching used in both concepts must be modified in order to further
devices in series to cope with the high voltage stress. extend the ability of the controller to select different voltage
However, this technique requires a precise method to ensure levels. In addition, the five-level ANPC inverter requires
the voltage share between the devices in dynamic and static additional control of the mid-point potential and the voltage
situations. Another method that has been well accepted by across the floating capacitors.
the industry, and is emerging as the standard solution for
II. F IVE -L EVEL ACTIVE N EUTRAL -P OINT C LAMPED
high power medium voltage applications, is the Multilevel
Converter. These structures have the ability to synthesize the The active neutral-point clamped (ANPC) inverter pre-
output waveform from several levels of voltages, improving sented by one-phase leg in Fig. 1 produces five distinct output
the spectrum quality when compared with the classical two- voltage levels by combining the three-level characteristic of
level topology. Furthermore, it permits the use of power the input stage (Cell 1) with the two-level of the output parts
devices with lower voltage rates and reduces electromagnetic
compatibility concerns, due to a smaller dv/dt. The basis of Cell 1
this new branch of topologies is the Neutral-Point Clamped
(NPC) three-level inverter proposed in 1980’s [1]. It utilizes S5 Cell 2 Cell 3
a series connection of dc-sources (generally realized by udc
2
capacitors) and clamping diodes to generated three output S6 S3 udc S1 R
voltage levels. Using the same principle, but with different M 4 C1

clamping elements, the three-level Flying Capacitor (FC) udc

[2] topology makes use of capacitors to limit the volt- 2 S7 S4 S2

age across the non-conducting switches. An extension of

these topologies to higher number of voltages levels may S8
be achieved including extra clamping elements. However,
both topologies reveal technical difficulties which complicate Fig. 1. One phase-leg of a five-level active-neutral point converter.
 TABLE I N
5-L EVEL ANPC INVERTER OUTPUT VOLTAGE LEVELS u g ,i

Lg ,i
Cell 1 Cell 2 Cell 3 Phase Switching 3
S8 S7 S6 S5 S4 S3 S2 S1 Voltage State
1 0 1 0 1 0 1 0 − u2dc u1 i g ,i 1 DHC
1 0 1 0 1 0 0 1 − u4dc u2 sL
i0 u NM uinv ,iM
1 0 1 0 0 1 1 0 − u4dc u3
+ 1
3 ∑
+ i 3
1 0 1 0 0 1 0 1 0 u4 ig' ,i
0 1 0 1 1 0 1 0 0 u5 pref ig ,i ,ref ∆ig' ,i
± hi (uci , u dc )
si
Current -
3
udc
0 1 0 1 1 0 0 1 4
u6 References
+
udc
qref
0 1 0 1 0 1 1 0 4
u7
M

+
udc
0 1 0 1 0 1 0 1 2
u8

ψg ,α β + ψc ,α β Inverter udc
Output
- Voltage

(Cell 2 and Cell 3). Moreover, unlike classical five-level Lg

topologies, the ANPC inverter splits the dc-link into only RS T
αβ
ig ,α β VF
two capacitors and requires only a single floating capacitor
for each phase. Consequently, it reduces costs, volume and Fig. 2. Virtual-Flux Decoupling Hysteresis Control (VF-DHC) scheme.
control complexity.
Five output voltage levels are achieved from eight distinct
switching combinations, indicated by the combination of the The DHC has an additional control loop that generates the
switching functions of S1 , S3 and S5 in Table I. One can current control signal, i0 . By summing the measured line
note that the switches S5 and S7 are operated in the same current, ig,i with i0 , a virtual current i′g,i is formed. With
way and complementarily to S6 and S8 . the correct formation of i0 the switching of the hysteresis
The list of switching combinations also shows the presence controller can occur without any interaction between each of
of redundant states, which generate the same output voltage the phase controllers. The phase interaction is caused because
level referred to the dc-link mid-point M . The voltage level the dc bus mid-point to neutral voltage is not constant, as it
− u4dc is generated either by the switching state u2 or u3 . depends on each of the inverter output voltages.
Nevertheless, they cause an opposite effect on the floating Reducing the phase current interaction results in the
capacitor voltage, due to the different combination of the switching frequency becoming more uniform and allows for
switches. For a positive output phase current for example, a near constant switching frequency if a variable hysteresis
while state u2 discharges, u3 charges de floating capacitor. band is implemented.
A similar behavior is observed on the level u4dc produced
by the states u6 and u7 . Depending on the direction of the IV. VF-DHC FOR F IVE -L EVEL ANPC I NVERTER
output phase current, these states have the ability to charge The Virtual-Flux Decoupling Hysteresis Control operation
or discharge the floating capacitor. with the five-level ANPC inverter is a natural extension of the
Besides that, the redundant combinations have also dif- two-level VF-DHC. The dashed area in the center of Fig. 3
ferent impact on the mid-point potential, depending on the
switching state of the input stage. For building an output
voltage equal to − u4dc , the input stage can be connected N

either to the negative potential − u4dc (u2 ) or directly to M

(u3 ). For the voltage level equal to u4dc , the switching state Lg ,i
u6 results in mid-point current flow, while u7 is connected 3
to the positive potential.
ig ,i 1 DHC
Therefore, this analysis clearly shows a degree of freedom sL
i0 + I 0 u NM uinv ,iM
to balance the floating capacitor of each phase individually + + 1
∑
+ - 3 i 3
by properly selecting the switching states according to the ig' ,i
direction of the output current and the state of the floating iinv ,i ∆uFC
pref ig ,i ,ref ± h (uinv ,i , udc )
capacitor voltage. The influence of each phase on the mid- Current - 3
References modulator
point potential can also be regulated using redundant states qref + ∆ig ,i si
ψ inv,α β ∆u
to create or avoid a link between the output and M . uM ,ct
+

G (s)
-
+ M
udc
III. VF-DHC FOR T WO -L EVEL I NVERTER 2
ψ g ,α β udc
The decoupling hysteresis controller (DHC) [6], as shown +
ψ inv ,α β Inverter 2
Output
by shaded DHC area in Fig. 2, has the same basic outer - Voltage
Lg
structure as the standard current hysteresis controller where
RS T
ig ,α β VF
the phase current is subtracted from a current reference and αβ

the hysteresis controller generates a switching signal from

the current error. Fig. 3. VF Decoupling Hysteresis Control for 5-level ANPC inverters.
 2
marks the blocks which require special attention. h1(t) h2(t)
In order to permit the inverter to switch among five 0 t12(t)
voltage levels, the hysteresis strategy is adapted including

hnorm
two extra hysteresis boundaries. Moreover, the expression -2
which determines the shape of the modulated hysteresis has
to be adjusted. -4
Due to a three-level characteristic of the input cell of 0.8
h (t )
the five-level ANPC topology, the method presented for 0.6
the three-level NPC inverter, which balances the mid-point

hnorm
0.4
potential M by injecting an offset I0 into the phase currents
can also be employed. However, since the ANPC inverter 0.2
demands additional control of the floating capacitors, an
0
extra control block called modulator is included. It balances 0 2 4 6 8 10
Time [ms]
individually the floating capacitors according to the output
currents direction. Fig. 4. Modulated hysteresis.

A. Hysteresis Strategy
Since the shape of the modulated hysteresis band neces- may change. The threshold for changing to another hysteresis
sary to achieve near constant switching frequency is highly shape is the intermediary voltage level u4dc .
influenced by the number of voltage levels, the method The difference between the inverter fundamental voltage
applied for the calculation of the two and three-level sys- and the threshold limit (3) indicates the beginning and end
tem hysteresis boundaries must be reviewed. The five-level of the application of the different shapes
inverter requests a slightly different approach, since during
udc
the positive cycle the inverter output voltage can switch either t12 (t) = uinv,i (t) −
(3)
between u4dc and 0 or u2dc and u4dc according to the operating 4
point. Hence, the analysis shall be performed separately. Fig. 4 illustrates the time behavior of both hysteresis limits
Within the first interval, the inverter switches to u4dc h1 and h2 , considering a sinusoidal fundamental inverter
allowing the current to increase from the lower hysteresis voltage. The transition between the two boundaries to build
limit to the upper limit. When the current reaches the upper the complete hysteresis h is controlled by the function t12 .
hysteresis limit, the controller changes the switching state During the interval where the inverter fundamental voltage
of the switching devices appropriately to generate an output is lower then u4dc (t12 < 0), the controller utilizes h1 , while
voltage equal to 0. As consequence the load current decreases h2 is selected for t12 > 0.
from the upper to the lower hysteresis limit. Combining both Although the modulated hysteresis allows for a near con-
switching times, the hysteresis ensuring a nearly constant stant switching frequency, a dedicated multilevel hysteresis
switching frequency in the interval where the fundamental strategy has to be employed to switch between multiples
inverter output voltage is lower then u4dc can be expressed output voltage levels as shown in Fig. 5. The current error
as is maintained inside of the inner bands, allowing the inverter
to switch only between two consecutive levels. If the state
uinv,i u4dc − uinv,i


selected is not able to correct the current error, the controller
hi,1 = . (1)
2 · Lg · fs · u4dc switches to the next upper (or lower) level when the error
crosses the second hysteresis boundary. This finally forces
From the point where the inverter loses the capability to the current error to operate within the inner bands. Even
regulate the output current by switching only between the two though a double hysteresis band is sufficient to achieve good
lower voltage levels (uinv,i > u4dc ), the controller changes
immediately to the next higher level, selecting appropriately
either u2dc or u4dc .
During this second period, to increase the current from
h, ∆iinv

the lower to the upper hysteresis limit, the inverter generates

an output voltage equal to u2dc . In order to bring the current
back to the lower boundary, and to limit ∆u at the same
time, the controller switches to the next lower level u4dc .
The combination of the on- and off-times provides the
4
Inversor output level

switching period and consequently the modulated hysteresis

expression 3

2
udc
uinv,i − u4dc



2 − uinv,i 1
hi,2 = . (2)
2 · Lg · fs · u4dc 0

0 4 8 12 16 20
Therefore, this analysis shows that depending on the Time [ms]
amplitude of the fundamental inverter voltage, the hysteresis
shape necessary to achieve a constant switching frequency Fig. 5. Hysteresis strategy.
 2
steady-state performance, a four level hysteresis is applied φ = 0ο

Mid-point current [A]

to force the current error back into the inner bands as fast as 1

possible during transients by using extreme dc voltage levels. φ = 40ο

0
φ = 90ο φ = 60ο
B. Mid-Point and Floating Capacitor Balance
-1
The majority of the mid-point voltage balancing schemes
rely on some form of manipulation of redundant vectors -2
-80 -40 0 40 80
available in multilevel topologies. In general the regulation uM,ct [V]

is achieved by adjusting the relative on-time of the redundant

Fig. 7. Transfer characteristic from the controlling signal uM,ct to the
switching state acting in the direction of a reduction of an average iM for different values of mains voltage and current phase-shift.
existing mid-point unbalance [7].
Since in the hysteresis method the control signals are
generated directly from the difference between reference against a reference (5), which is normally half of the total
and actual value of each phase current according to the dc-link voltage, and produces a proportional dc control uM,ct
hysteresis boundaries, the possibility of controlling the mid-
point voltage by influencing the frequency of each redundant
state is limited basically to a modification of the reference ∆u = uCl,ref − uCl (5)
value shape. Therefore, since the amplitude and sinusoidal uM,ct = kp · ∆u. (6)
shape of the currents references are given by the power
requirements, the only remaining degree of freedom is the The influence of the controller output voltage uM,ct on the
addition of a zero-component I0 average mid-point current is shown in Fig. 7. This clearly
shows that if for φ = 0o , e.g. the lower capacitor voltage
i′g,i = ig,i + I0 (4) uCl is below the reference voltage uCl,ref , the resulting
positive controller output voltage uM,ct , produces a negative
where the offset I0 is set to be equal in all three phases and average mid-point current, which charges the lower capacitor,
consequently, its influence on the current shape is canceled balancing the mid-point potential. However, for different
in systems with isolated mains neutral point where the sum values of mains voltage and current phase-shift (φ) the
of the phase currents is forced to 0 (ig,R + ig,S + ig,T = 0). controllability of the mid-point current and consequently of
One can note that I0 has a direct influence on the location the mid-point potential is reduced when φ is approaching
and shape of the tolerance area (Fig. 6), which is defined by 90o .
the intersection of the tolerance bands of each phase. For a Nevertheless, for the five-level ANPC inverter due to
classical operation without offset or I0 = 0, the tolerance existing redundant switching states to generate the levels
area is represented by an equilateral hexagon (Fig. 6(a)), − u4dc and u4dc , there exists an extra degree of freedom
resulting in segments of positive (h+ i ) and negative (hi )
−
to balance the mid-point potential.When the controller of
switching thresholds with equal length. As consequence, the phase i decides to apply an output voltage level of − u4dc ,
resulting average mid-point current is zero. However, when a the inverter has two switching state alternatives, u2 and u3 ,
positive offset I0 is added to the phase currents, the tolerance which affect differently the mid-point potential. While state
bands of each phase are shifted to the positive side according u3 connects the inverter output directly to M to generate
to Fig. 6(b). The intersection of the bands now creates an the voltage level − u4dc (Fig. 8), state u2 establishes a
asymmetric tolerance area, where the the positive (h+ +
R , hS , connection to the negative potential. As consequence, only u3
+ − − −
hT ) and the negative (hR , hS , hT ) switching thresholds are influences the potential of M dependent on the output phase
of unequal lengths, resulting in a positive average mid-point current. The same situation occurs for the voltage level u4dc .
current. While u6 makes use of M , u7 is connected to the positive
In the proposed VF-DHC, the zero sequence current I0 potential. To use the benefits of this extra degree of freedom,
is created by subtracting the signal of the voltage controller the modulator shall select the switching state which either
uM,ct from the input of the integrator (Fig. 3). The voltage corrects the mid-point deviation or does not influence M .
controller compares the voltage across the lower capacitor A strategy to select the proper switching state to balance
the mid-point potential according to the voltage deviation

S ∆ig,β S ∆ig,β

+
hS
hS+ hT−
udc S5 udc S5
hT− + 2 2
hR
− + − R iinv,i
hR hR R hR S6 S3 udc S1 S6 S3 udc S1
∆ig,α ∆ig,α M M
4 4
hS−
hT+ hS− +
hT udc S7 udc
2 iinv,i S4 S2
2
S7 S4 S2

T T S8 S8

(a) I0 = 0 (b) I0 > 0 (a) State u2 (b) State u3

Fig. 6. Tolerance area of a three-phase hysteresis controller (a) without dc Fig. 8. Effect of the redundant switching states u2 and u3 on the mid-point
offset and (b) with positive dc offset. potential and floating capacitors.
 uCl uFC ,i
∆iinv,i h

Balance Control Signal

uCl ,ref ∆uCl u3 uFC ,i ,ref u2
∆uFC,i h

D C si
XOR XOR Mid-Point
suFC ,uC
iinv ,i ii iinv ,i ii Floating
Capacitor
u2 u3
Ts
(a) Mid-Point (b) Floating Capacitors
Fig. 9. Balancing strategy to control the mid-point potential (a) and floating Fig. 10. Switching between floating capacitors and mid-point control.
capacitors (b) for the voltage level − u4dc

V. E XPERIMENTAL V ERIFICATION
of the lower dc-link capacitor ∆uCl and the direction of
current ii , is applied as illustrated in Fig. 9(a). Considering The experimental verification is performed using the 6kW
that the lower dc-link capacitor must be charged, ∆uCl = 1, five-level ANPC prototype presented in Fig. 11. A 10mH
and the inverter is generating a positive phase current, if output filter connects a controlled 400V 3-phase AC power
state u3 is applied, the resulting positive iM would continue source to the inverter, which is operating with a switching
to discharge the lower capacitor. Therefore, a reasonable frequency of 2.5kHz. The 800V dc power is provided by
alternative is to select state u2 that although not correcting two 10kW - 600V dc power supplies connected in series.
the deviation, at least does not contribute negatively as state The controller is implemented fully digitally using an Analog
u3 . This logic is repeated for all different combinations of Devices ADSP21991 16-bit 160M Hz DSP platform.
∆uCl ,i and ii , and is extended to the voltage level u4dc with
Floating
the switching states u6 and u7 . IGBT’s Capacitors

Besides being useful to balance the mid-point potential,

the redundant states can also be used to balance the floating
capacitors. For a positive output phase current iinv,i , state
u2 discharges the floating capacitor (Fig. 8(a)), while state
u3 charges (Fig. 8(b)). For a negative current, the effect on dc-link
Capacitors
the floating capacitor is reversed. Therefore, the modulator
block is in charge to select the proper state to balance the
DSP and
floating capacitor according to the output current direction PLD
Current
Sensors
ii (1 for positive and 0 for negative current), as illustrated
in Fig. 9(b). Additionally, a hysteresis controller provides to
the decision block, an input 1 when the capacitor voltage Fig. 11. Photo of the three-phase five-level ANPC prototype.
deviation ∆uF C,i reaches the upper hysteresis limit and
0 for reaching the negative. If the voltage of the floating Initially, the experimentation is focused on the effective-
capacitor uF C,i is below the reference uF C,i,ref minus the ness of the decoupling method when applied to a five-
limit allowed by the hysteresis controller, i.e. ∆uF C,i = 1, level ANPC inverter. Fig. 12 shows the static performance
assuming a positive output phase current, i.e. ii = 1, the state concerning output phase current ig,R and voltage uinv,R for
u3 shall be selected to charge the capacitor. On the other the classical hysteresis approach (Fig. 12(a)), the decoupling
hand, for the same voltage condition but negative output method (Fig. 12(b)) and the behavior of properly modulating
phase current, ii = 0, u2 is the correct choice to balance the hysteresis boundaries hR (Fig. 12(c)). One can note
the floating capacitor. that the inverter output voltage generated by the classical
The same strategy is applied when the current controller hysteresis controller is very irregular with long intervals
selects the voltage level u4dc . To generate this level the mod- without any action. The performance is more consistent
ulator has two choices, states u6 and u7 . While the first state when the calculated zero sequence current i0 is added to the
discharges the floating capacitor, considering a positive phase measured phase currents, enabling the decoupling strategy.
current, the second state increases the capacitor voltage. In this case, the inverter output voltage turns out to be
A similar decision block and logic strategy as shown in more regular, although there are still some gaps during
Fig. 9 are used to choose among these states, where state transitions between levels. Further improvement is achieved
u6 replaces u2 , while u7 takes the position of u3 . by varying the hysteresis limits hi , where the hysteresis
However, during normal operation the switching state band shows a low width exactly in the moment when the
selected to control the floating capacitor might not be nec- hysteresis controller demands a transition to the next higher
essarily the proper choice to balance the dc-link voltage. (or lower) level. This directly influences in the switching
Therefore, a method to switch between these two controllers frequency which becomes more constant as shown by the
is required. current spectrum analysis of Fig. 12(d)-(f). The inherent
In the proposed approach, each control is selected every wide spread frequency spectrum generated by the classical
switching period successively, as illustrated in Fig. 10. Due to hysteresis approach is presented in Fig. 12(d). It becomes
a nearly constant switching frequency obtained with the five- more centered around the desired switching frequency with
level VF-DHC, both strategies are applied practically over the decoupling method (Fig. 12(e)) and nearly constant when
same interval of a fundamental cycle. the modulated hysteresis is enabled (Fig. 12(f)).
 hR
hR u g, R hR u g, R
u g, R

u inv,R u inv,R u inv,R

ig, R ig, R ig, R

(a) VF-CHC (b) VF-DHC (c) VF-DHC with modulated hysteresis

6.0 6.0 6.0

Amplitude [% of fund.]

Amplitude [% of fund.]

Amplitude [% of fund.]
4.5 4.5 4.5

3.0 3.0 3.0

1.5 1.5 1.5

0 0 0
0 5 10 15 0 5 10 15 0 5 10 15
Frequency [kHz] Frequency [kHz] Frequency [kHz]

(d) VF-CHC (e) VF-DHC (f) VF-DHC with modulated hysteresis

Fig. 12. Hysteresis band hR , grid voltage ug,R (500V/div), inverter output voltage uinv,R (400V/div) and grid current ig,R (10A/div) of five-level (a)
VF-CHC, (b) VF-DHC, and (c) VF-DHC with modulated hysteresis band and respective current spectrum (d),(e) and (f).

uC u uFC,R

uC l
uFC,S
u g, R

uFC,T
ig, R
ig, R

Fig. 13. Experimental results of the voltages uC,u and uC,l across the Fig. 14. Experimental results of the voltage across the floating capacitors.
dc-link capacitors.

state. The static and dynamic performance of both methods

Fig. 13 proves the effectiveness of the strategy applied to have been verified using a 6kW five-level ANPC inverter
balance the mid-point potential. The voltage of the lower dc- prototype connected to a 400V 3-phase AC power source
link capacitor, and consequently of the upper capacitor, are via a first order L filter.
controlled to u2dc or 400V , due to the correct operation of
the modulator selecting a proper redundant switching state. R EFERENCES
Additionally, an offset I0 calculated according to the voltage [1] A. Nabae, I. Takahashi, and H. Akagi, “A new neutral-point clamped
deviation is added to the measured currents to influence the pwm inverter,” IEEE Transactions on Industry Applications, vol. 17,
pp. 518–523, 1981.
resulting mid-point current. [2] T. A. Meynard and H. Foch, “Multi-level conversion: high voltage
Thanks to redundant switching states, the controller is choppers and voltage-source inverters,” in Power Electronics Specialists
able to regulate the voltage of the floating capacitors to u4dc Conference (PESC ’92), vol. 1, 1992, pp. 397–403.
[3] P. Barbosa, P. Steimer, L. Meysenc, M. Winkelnkemper, J. Steinke, and
(Fig. 14). The modulator has the possibility of choosing N. Celanovic, “Active neutral-point-clamped multilevel converters,” in
among two redundant states when the current controller Power Electronics Specialists Conference (PESC ’05), 2005, pp. 2296–
decides to apply a voltage level − u4dc and another two states 2301.
[4] L. A. Serpa, S. D. Round, and J. W. Kolar, “A virtual-flux decoupling
for the level u4dc . hysteresis current controller for mains connected inverter systems,”
IEEE Transactions on Power Electronics, vol. 22, no. 5, pp. 1766–1777,
VI. C ONCLUSION 2007.
[5] L. A. Serpa and J. W. Kolar, “Extended virtual-flux decoupling hystere-
The decoupling current control (VF-DHC) to use for the sis control for mains connected three-level npc inverter systems,” in in
five-level ANPC inverter is an extension of the method Proceedings of the 9th Brazilian Power Electronics Conference.
[6] L. Dalessandro, U. Drofenik, S. D. Round, and J. W. Kolar, “A novel
used for the two-level full-bridge topology. A dedicated hysteresis current control for three-phase three-level pwm rectifiers,” in
modulated hysteresis strategy is used to allow the inverter to Applied Power Electronics Conference and Exposition (APEC’ 2005),
select multiple output voltage levels. Furthermore, in order vol. 1, 2005, pp. 501–507.
[7] C. Newton and M. Sumner, “Neutral point control for multi-level
to balance the mid-point potential and the floating capacitor inverters: Theory, design and operational limitations,” in Industry Ap-
voltages, a modulator is introduced to decode the level plications Conference (IAS’ 1997), vol. 2, 1997, pp. 1336–1343.
selected by the current controller into a correct switching