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    VLSI Design Overview Problems

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    Jorge Ivan Canales Verdial
    This document contains 10 homework problems for an ECE 520 VLSI Design course at the University of New Mexico. The problems cover topics such as logic circuit analysis, transistor sizing, sequential circuit analysis, delay calculations, and ROM circuit analysis. Students are asked to determine logic functions, critical paths, propagation delays, transistor widths and lengths, clock frequencies, and stored values in the circuits depicted in the problems.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    VLSI Design Overview Problems

    Uploaded by

    Jorge Ivan Canales Verdial
    212 views4 pages
    This document contains 10 homework problems for an ECE 520 VLSI Design course at the University of New Mexico. The problems cover topics such as logic circuit analysis, transistor sizing, sequential circuit analysis, delay calculations, and ROM circuit analysis. Students are asked to determine logic functions, critical paths, propagation delays, transistor widths and lengths, clock frequencies, and stored values in the circuits depicted in the problems.

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    VLSI Design Overview Problems

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    This document contains 10 homework problems for an ECE 520 VLSI Design course at the University of New Mexico. The problems cover topics such as logic circuit analysis, transistor sizing, sequential circuit analysis, delay calculations, and ROM circuit analysis. Students are asked to determine logic functions, critical paths, propagation delays, transistor widths and lengths, clock frequencies, and stored values in the circuits depicted in the problems.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    212 views4 pages

    VLSI Design Overview Problems

    Uploaded by

    Jorge Ivan Canales Verdial
    This document contains 10 homework problems for an ECE 520 VLSI Design course at the University of New Mexico. The problems cover topics such as logic circuit analysis, transistor sizing, sequential circuit analysis, delay calculations, and ROM circuit analysis. Students are asked to determine logic functions, critical paths, propagation delays, transistor widths and lengths, clock frequencies, and stored values in the circuits depicted in the problems.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
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    University of New Mexico

    Department of Electrical and Computer Engineering

    ECE 520 - VLSI Design (spring 2019) Homework #7


    Due in class: Thursday May 2, 2019

    1. Consider the following two logic circuits.

    a. Do these two circuits implement the same logic function? If yes, what is that
    logic function? If no, give Boolean expressions for both circuits.
    b. Will these two circuits’ output resistances always be equal to each other?
    c. Will these two circuits’ rise and fall times always be equal to each other? Why
    or why not?

    2. The transistors in the circuits of the preceding problem have been sized to give an
    output resistance of 13 kΩ for the worst-case input pattern. This output resistance
    can vary, however, if other patterns are applied.
    a. What input patterns (A–E) give the lowest output resistance when the output is
    low? What is the value of that resistance?
    b. What input patterns (A–E) give the lowest output resistance when the output is
    high? What is the value of that resistance?
    3. What is the logic function of circuits A and B in the following circuits? Which one is
    a dual network and which one is not? Is the non-dual network still a valid static
    logic gate? Explain. List any advantages of one configuration over the other.

    4. The following figure contains a pass-gate logic network.


    a. Determine the truth table for the circuit. What logic function does it implement?
    b. If the PMOS were removed, would the circuit still function correctly? Does the
    PMOS transistor serve any useful purpose?
    c. Assuming 0 and 2.5 V inputs, size the PMOS transistor to achieve a VOL = 0.3
    V. Assume K’n = 100 µA/V2, K’p = 40 µA/V2 , VTn = 0.4, and VTp = -0.4. Does
    body effect change your result?

    5. Consider the following sequential circuit with 3 edge-triggered registers, a


    multiplier, and an adder.
    (a) Identify all possible paths from the output to the input of any flip -flop in
    this circuit.
    (b) For the delays given in the table below, identify the critical path. Include
    flip -flop and clock buffer delays and the required flip -flop setup time.
    (c) What is the maximum clock frequency at which the circuit can operate
    correctly?
    (d) Does this circuit satisfy the hold time constraint? Why?
    6. We would like to design the following circuit such that the worst case
    propagation delays (tpHL and tpLH) are limited to 2.14 ns. Use Elmore delay
    equation to determine the W/L for PMOS and NMOS used in the 2-input NOR
    gate. Assume that VDD =1.2V, K’n=90uA/V2, Vtn=0.4V, K’p=50 uA/V2, and
    Vtp=-0.5V in the 100nm technology node. Also assume that the transistors
    stay in saturation region for the length of the transition.

    7. Describe the logic function computed by the following circuit. Note that all
    transistors (except for the middle inverters) are NMOS.
    8. Estimate the minimum delay of the path from A to B in Figure below. Choose
    transistor sizes to achieve this delay. The initial NAND2 gate may present a
    load of 8C0 on the input and the output load is equivalent to 45C0, where C0 is
    the input capacitance of a reference (1X) inverter.

    9. A 3-stage logic path is designed so that the effort by each stage (i.e. fi=gibihi)
    is 12, 6, and 9 delay units, respectively. Can this design be improved? Why?
    What is the best number of stages for this path? What changes do you
    recommend to the existing design?

    10. Analyze the CMOS ROM circuit below to determine the stored values.

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