Connecting MATLAB & Simulink with your
SystemVerilog Workflow for Functional
Verification
Corey Mathis
Industry Marketing Manager – Communications, Electronics, and Semiconductors
MathWorks
© 2014 MathWorks, Inc. 1
Who is MathWorks?
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System Design & Simulation in Simulink
Unique advantages
Model continuous-time and
discrete-time components
together
Express analog filters as
Laplace transforms or RLC
circuits
Variable step ODE solvers
Feedback control loops,
VCOs, PLLs
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ASIC/SoC Design Flow
Model-Based Design Integration
RESEARCH REQUIREMENTS
ALGORITHM DESIGN
ALGORITHM TEST & VERIFICATION
Environment Models
ASIC/SoC-LEVEL TEST & VERIFICATION
Digital Models Analog Models RF Models
Timing and Control Logic
Algorithms
MODEL GENERATION ALGORITHM IMPLEMENTATION
RF
C/C++ HDL Analog
SystemC SystemVerilog
MCU DSP FPGA ASIC Transistor
ALGORITHM INTEGRATION
ASIC/SoC-LEVEL INTEGRATION
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Design Gap
How to bridge MathWorks tools and EDA tools?
How do I reuse AMS models from Simulink in an EDA environment?
How can I reuse my testbench for digital ASIC verfication?
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Co-simulation with Simulink
Verify the detailed level design:
– within the context of a full system simulation
– using the visualization and analysis capabilities of Simulink and
MATLAB
– testing each module independently of other modules
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Using Co-simulation for Model Elaboration
Ideal behavioral model
Cosimulation
Refined model
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System Verilog DPI-C Component Generation
Reuse of models in SystemVerilog Testbench
Develop
– System components (IP and test
Data Component
Source Model benches) in Simulink and MATLAB
– Model, Simulate, and Verify
Algorithm
Environment
Model
Export
– Components as C code with
Analysis
Component SystemVerilog wrappers
Model
Algorithmic System-level Testbench Integrate
– DPI-C components in Virtuoso and
Incisive
Verify
DPI-C DPI-C DPI-C DPI-C – Verification of the complete system
design!
SystemVerilog Testbench Environment
Embedded Coder
HDL Verifier 8
Using C Code Generation and the DPI-C Interface
1. Generate C code from your Simulink model
2. Automatically wrap the C code using the DPI-C interface
3. Import, build and simulate an equivalent behavioral
SystemVerilog model in your IC design tool
2. SystemVerilog wrapper
Simulink
3. Cadence
1. C Code 9
Benefits of C Code Generation and DPI-C Export
Fast simulation using the native SystemVerilog API
IC design tool independent
Customizable approach supported by MathWorks
Leverages mature C code generation technology
Most suitable for testbench generation and IC verification
Support discrete and continuous time signals
Simulink
Cadence
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Some Details …
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Mixed-Signal ADC Model
Sine Wave First Order
Signal Source Sigma Delta
Analog Digital
Low Pass Filter Decimator Filter
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Export of Mixed-Signal Models
Continuous time signals
Discrete time solver
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From Variable to Fixed Time Step Solver
Chose a fixed sample time that it is small enough to
give correct results
Tradeoff accuracy and simulation time
Large time step Small time step
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Clocks in SystemVerilog Determine the
Scheduling of the Execution
Simulink handles multi-rate systems automatically
Simulink supports model generation for hierarchical subsystems or individual
components
Need to define multi-rate clocks to schedule the SystemVerilog execution
when different rate components are generated
Fast Rate Slow Rate
Fast Clock Slow Clock
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Model Analog Circuits with Simscape
Model analog electronics with Simscape
Generate a SystemVerilog component for simulation in
the IC Design Tools
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Digital Workflow
HDL Coder
– Used to generate synthesible RTL
HDL for design models
Data Component
Source Model
SystemVerilog DPI-C
Algorithm
Environment – Reuse of golden testbench:
Model Signal sources
Enviorment and channel models
Measurement block and algorithms
Component
Analysis
Model
Algorithmic System-level Testbench Support for
– MATLAB
– Simulink
– Stateflow
DPI-C RTL HDL RTL HDL DPI-C
(VHDL, Verilog) (VHDL, Verilog)
SystemVerilog Testbench Environment
HDL Coder
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Digital Workflow Example
MathWorks can export HDL code for pure digital models
Testbenches need to be exported to Cadence via DPI-C
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Digital Workflow Example
1. Generate synthesizable Verilog or VHDL for design components
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Digital Workflow Example
2. Generate C code with SystemVerilog wrappers for testbench components
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Digital Workflow Example
3. Import HDL and SystemVerilog into Cadence for simulation/verification
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Certified by STARC
http://www.mathworks.com/company/newsletters/articles/a-next-generation-workflow-for-system-level-design-of-mixed-signal-integrated-circuits.html
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SystemVerilog Workflow Summary
MATLAB & Simulink provide a diverse environment for
early stage design exploration
Co-simulation provides a means of elaborating on initial
behavioral models to match detailed level designs
The DPI-C link for SystemVerilog provides a robust way of
exporting behavioral models from MathWorks tools into
Cadence for the purpose of functional verification
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Q/A
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