PWM-FF Ic Tda4916gg

Datasheet, V2.
0, 1 May 1996
PWM-FF IC
TDA4916GG
SMPS IC with MOSFET

Driver Output
Power Management & Supply
N e v e r s t o p t h i n k i n g .
TDA4916GG
Revision History: 1996-05-01 Datasheet

Previous Version:
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Edition 1996-05-01
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SMPS-IC with MOSFET Driver Output TDA 4916 GG
Features
• High clock frequency
• Low current drain
• High reference accuracy
• All monitoring functions
P-DSO-24-1
Type Ordering Code Package

TDA 4916 GG Q67000-A9230 P-DSO-24-1
Functional Description and Application

The general-purpose single-ended switch-mode power supply device for the direct
control of SIPMOS power transistors incorporates both digital and analog functions.
These are required for the construction of high-quality flyback, forward and choke
converters. The device can be likewise used for transformer-less voltage multipliers and
variable-speed motors.
Faults occurring during operation of the switch-mode power supply are detected by
comparators integrated in the device which initiate protective functions.
In addition, pairs of power supplies can be synchronized in antiphase. In-phase or
antiphase synchronization is possible when more than two power supplies are involved.
Version 2.0 3 1 May 1996

TDA 4916 GG
Pin Configuration
(top view)
P-DSO-24-1
Figure 1

TDA 4916 GG
Pin Definitions and Functions
Pin No. Symbol Function

1 0V GND GND
2 VS Supply voltage
3 0V QSIP Ground QSIP
4 Q SIP SIPMOS driver
5 VS QSIP Supply voltage driver
6 SF Series feed
7 – I K5/– I K6 Current sensor negative input
8 + I K5 Current sensor K5
9 + I K6 Current turn-OFF K6
10 Q K6 Output K6
11 PO Pulse omission
12 CSS Soft start
13 I SYN Input synchronization
14 Q SYN Output synchronization
15 RT Frequency generator
16 CT Frequency generator
17 CR Ramp generator
18 I K4 Input undervoltage
19 I K3 Input overvoltage
20 I K1 Input K1
21 Q OP Output operational amplifier
22 – I OP Input operational amplifier
23 + I OP Input operational amplifier
24 VREF Reference voltage

TDA 4916 GG
Figure 2
Block Diagram
TDA 4916 GG
Circuit Description
The individual functional sections of the device and their interactions are described
below.
Power Supply at VS
The device does not enable the output until the turn-ON threshold of VS is exceeded. The
duty factor (active time/period) can then rise from zero to the value set with K1 in the time
determined by the soft start. The turn-OFF threshold lies below the turn-ON threshold.
Below the turn-OFF threshold the output Q SIP is reliably low.
Frequency Generator
The frequency is mainly determined by close-tolerance external components and the
calibrated reference voltage.
The switching frequency at the output can be set by suitable choice of Rt and Ct.
The maximum possible duty factor can be reduced by a defined amount by means of a
resistor from CT to 0V GND. The maximum possible duty factor can be increased by a
defined amount by means of a resistor from CT to VS.
Ramp Generator
The ramp generator is controlled by the frequency generator and operates with the same
frequency. Capacitor Cr on the ramp generator is discharged by an internally-set current
and charged via a current set externally. The duration of the falling edge of the ramp
generator output must be shorter than its rise time. Only then do the upper and lower
switching levels of the ramp generator signal have their nominal values.
In “voltage mode control” operation, the rising edge of the ramp generator signal is
compared with an externally set dc voltage in comparator K1 for pulse-width control at
the output. The slope of the rising edge is set by the current through Rr. The voltage
source connected to Rr can be the SMPS input voltage. This makes it possible to control
the duty factor for a constant volt-second product at the output. This control option
(precontrol) permits equalization of known disturbances (e.g. input voltage ripple).
Superimposed load current control (current mode control) can also be implemented. For
this purpose the actual current at the source of the SIPMOS transistor is sensed and
compared with the specified value in comparator K5.

TDA 4916 GG
Comparator K1 (duty factor setting for voltage mode control)

The two plus inputs of the comparator are so connected that the lower plus level is
always compared with the minus input level. As soon as the voltage of the rising edge of
the sawtooth (minus input) exceeds the lower of the two plus input levels, the output is
inhibited via the turn-OFF Flip-Flop, that is to say the High time of the output can be
continuously varied. Since the frequency remains constant, this corresponds to a duty
factor change.
Comparator K2
The comparator has a switching threshold at 1.5 V. Its output sets the fault Flip-Flop
when the voltage on capacitor Ca lies below 1.5 V. However, the fault Flip-Flop accepts
the setting pulse only if no reset pulse (fault) is applied. This prevents resetting of the
output as long as a fault signal is present.
Comparators K3 (overvoltage), K4 (undervoltage), VS Undervoltage, VREF

Overcurrent
These are fault detectors which cause the output to be inhibited immediately by the fault
Flip-Flop when faults occur. When faults are no longer present, the duty factor is
reestablished via the soft start CSS. In the event of undervoltage, a current is injected at
the input of K4 with the aid of which an adjustable hysteresis or latching is made
possible. The value of the hysteresis is determined by the internal resistance of the
external drive source and the current injected internally at the input of K4. In the event
of undervoltage at K4, the injected current flows into the device.
Comparator K5 (duty factor setting for current mode control)

K5 is used to sense the source current at the switching transistor. The plus input of the
comparator is fed out. Enabling of output Q SIP after cessation of the fault is effected
with an H signal at the turn-OFF Flip-Flop output.
Comparator K6 (overcurrent turn-OFF)

The turn-OFF Flip-Flop is reset when overcurrent is detected by K6. In combination with
the pulse-omission facility, individual pulses can then be omitted. This then results in a
limited rise in the output current with a rising overload at the output.

TDA 4916 GG
Operational Amplifier OP
Opamp OP is a high-quality operational amplifier. It can be used in the control circuit to
transfer the variations in the voltage to be regulated in amplified form to the free plus
input of comparator K1. As a result, a voltage change is converted into a duty factor
change. The output of OP is an open collector. The frequency response of OP is already
corrected. The plus input is connected internally via a capacitor to ground. This gives the
inverting amplifier a more favorable phase response.
Turn-OFF Flip-Flop AFF

A pulse is fed to the set input of the turn-OFF Flip-Flop with the falling edge of the
frequency generator signal. However, it can only really be set if no reset signal is applied.
With a set turn-OFF Flip-Flop, the output is enabled and can be active. The Flip-Flop
inhibits the output in the event of a turn-OFF signal from K1, K5, K6 or K7.
Fault Flip-Flop
Fault signals fed to the reset input of the fault Flip-Flop cause the output to be
immediately disabled (Low), and to be turned on again via the soft start CSS after
removing fault-condition.
Soft Start CSS

The smaller of the two voltages at the plus inputs of K1 - compared with the ramp
generator voltage - is a measure of the duty factor at the output. At the instant the device
is turned-ON, the voltage on capacitor CSS equals zero. Provided no fault exists, the
capacitor is charged up to its maximum value.
CSS is discharged in the event of a fault. However, the fault Flip-Flop inhibits the output
immediately. Below a charging voltage of approx. 1.5 V, a set signal is applied to the fault
Flip-Flop and the output is enabled, provided a reset signal is not applied
simultaneously. However, since the minimum ramp generator voltage is about 1.8 V, the
duty factor at the output is not actually slowly and continuously increased until the
voltage on CSS exceeds a value of 1.8 V.
The Z-diode limits the voltage on capacitor CSS. The voltage at the ramp generator can
reach a higher level than the Zener voltage. With a suitable ramp generator rising edge
slope, the duty factor can be limited to a wanted maximum value.
Pulse Omission PO
In the event of overcurrent in the SIPMOS transistors it is frequently necessary to omit
pulses even with minimum duty factor. Only this measure ensures that the SIPMOS
transistors cannot be overloaded. This wanted function can be achieved with Pulse
Omission PO and Overcurrent Comparator K7 by means of a suitable external circuit.

TDA 4916 GG
Reference Voltage VREF

The reference voltage source makes available a source with a high-stability temperature
characteristic which can be used for external connection to the operational amplifier, the
fault comparators, the frequency generator, or to other external units. The voltage
source is short-circuit-proof to ground.
Synchronization I SYN, Q SYN

The device has an input and an output for synchronization. In the case of a synchronized
device (slave), its output Q SIP is in phase opposition to the output Q SIP of the
synchronizing device (master). In the case of an unconnected input I SYN, or with
connection to VREF, or also when a series capacitor (without switching transitions) is
connected, the device receives its clock from the internal frequency generator in
accordance with the circuit connected to it. As soon as switching transitions appear at
I SYN, switchover to external synchronization and vice versa takes place after a delay.
After a switchover process, a few clock cycles must elapse in addition to the delay before
the frequency and phase achieve their steady states.
Series Feed SF
The Series Feed circuit section is used to turn-OFF the external series-feed transistor
when energy recovery commences. As a result there is minimum power loss in the
supply to the device. With the series-feed transistor turned-OFF, its drive current flows
via VS to VS.
SIPMOS Driver Output Q SIP

The output is High active. The time during which the output is active can be continuously
varied.
The duration of the rising edge of the frequency generator signal is the minimum time
during which the output can be Low.
The duration of the falling edge of the frequency generator signal is the maximum time
during which the output can be High.
The output driver is designed as a push-pull stage. The output current is limited internally
to the specified values.
Output Q SIP is connected via diodes to the supply VS QSIP and 0V QSIP.
A protection circuit SS lies between Q SIP and GND to clamp the output to ground at low
impedance in the event of undervoltage at VS.

TDA 4916 GG
When the supply to the switch-mode power supply is switched on, the capacitive
displacement current from the gate of the SIPMOS transistor is conducted to the
smoothing capacitor at VS QSIP by the diode connected to VS QSIP. The voltage at
VS QSIP may reach about 2.3 V in the process without the SIPMOS transistor being
turned-ON.
The diode connected to ground clamps negative voltages at Q SIP to minus 0.7 V.
Capacitive currents which occur with voltage dips at the drain terminal of the SIPMOS
transistor can then flow away unimpeded.
The output is active Low with supply voltages at VS and VS QSIP from about 4 V on. The
function of the diode connected to VS QSIP and the resistor are then taken over by the
pull-down source.
The two ground terminals 0V SQIP and 0V GND can lie at different levels. This permits
connections to be made to the SIPMOS transistor in such a way that the drive currents
for the gate do not flow to the source via the current-sensing resistor. The maximum
permissible level differences between 0V GND and 0V SQIP are given under Functional
Range. If greater level differences are anticipated, it is better to join the two terminals.

TDA 4916 GG
Absolute Maximum Ratings

TA = – 40 to 85 °C
Parameter Symbol Limit Values Unit Test Condition
min. max.
Supply voltage; VS,VS QSIP VS,VVS QSIP – 0.3 17 V
I OP, I K1, I K3, I K4, I K5, I K6, VI – 0.3 17 V
I SYN VI SYN 0 5 V
II SYN –3 3 mA VI SYN > 5 V or
VI SYN < 0 V
Q SYN VQ SYN – 0.3 5 V
Frequency Generator; CT, RT VCT, RT – 0.3 5 V
ICT, RT 0 3 mA VCT > 5 V
Ramp Generator; CR VCR – 0.3 VCRH V VCRH (see charact.)
ICR 0 3 mA VCR > VCRH
Reference voltage; VREF VREF – 0.3 6 V
IREF – 10 10 mA VREF > 6 V or
VREF < – 0.3 V
Output Opamp; Q OP
Inhibited VQ OP – 0.3 17 V
Conducting IQ OP 0 5 mA
Output Overcurrent Turn-OFF;
Q K6
Inhibited VQ K6 – 0.3 17 V
Conducting IQ K6 0 5 mA
1)
Driver output; Q SIP VQ SIP – 0.3 VS V
Q SIP clamping diodes IQ SIP – 10 10 mA VQ SIP > VS or
VQ SIP < – 0.3 V
Soft start; CSS VCSS – 0.3 VSSH V VSSH (see charact.)
ICSS 0 100 µA VSS > VSSH
Pulse omission; PO VPO – 0.3 VPOH V VPOH (see charact.)
IPO 0 3 mA VPO > VPOH
Series feed; SF VSF – 0.3 17 V
Junction temperature Tj – 65 150 °C
Storage temperature Ts – 65 150 °C
Thermal resistance Rth S/A 60 K/W
system - ambient
The values refer to the two connected ground terminals.
1) Important: observe max. power loss or junction temperature.

TDA 4916 GG
Operating Range
Function Symbol Limit Values Unit
min. max.
Supply voltage VS 0 15 V
VVS QSIP 0 15 V
Frequency generator f 0.05 400 kHz
Ramp generator f 0.05 400 kHz
Ambient temperature TA – 40 + 100 °C
Ground Q SIP V0V QSIP GND – 300 mV GND + 2 V V
Resistor at RT RRT 27 1000 kΩ
Characteristics
VSon < VS < 15 V, – 25 °C < TA < 85 °C; VSon means that VS has exceeded VSH, but has
not gone below VSL.
min. typ. max.
Current in VS IVS 7 mA1) FG at 100 kHz
8 mA1) FG at 300 kHz
Q SYN
unconnected
Q SYN to 0V GND
Current in VS QSIP IVS QSIP 2.5 mA1) FG at 100 kHz
5.5 mA1) FG at 300 kHz
Current in ISum 9 mA1) FG at 100 kHz
VS + VS QSIP 13 mA1) FG at 300 kHz
Q SYN
unconnected
Q SYN to 0 V GND

TDA 4916 GG
Characteristics (cont’d)
not gone below VSL.
min. typ. max.
Current Drain2)
Hysteresis at VS
Turn-ON threshold VSH 8.0 9.1 10 V
for VS rising
Turn-OFF threshold VSL 7.9 9.0 9.9 V
for VS falling
1)
CT; RT (see oscillator nomogram).
2)
The currents as VS and VS QSIP are in each case without loads and without internal discharge to CR, as well
as with active output Q SIP.
Reference Voltage
Voltage VREF 2.460 2.500 2.540 V IREF = 250 µA;
VS = 12 V
Load current – IREF 0 3 mA ∆VREF < 30 mV
Voltage change ∆VREF 5 mV 0 mA < IREF
< 500 µA
Voltage change ∆VREF 3 mV 12 V < VS < 14 V
Temperature ∆VREF/ 0.1 mV/K
response ∆T
Operate threshold – IREFO 3 6 10 mA
VREF overcurrent
Frequency Generator
Nominal frequency ∆fF/fO –4 4 % 20 kHz < fO
spread < 150 kHz;
Q SYN to GND;
VS = 12 V;
TA = 25 °C
Voltage dependence ∆fV/fO –1 1 % 10 V < VS < 14.4 V;
of nominal TA = 25 °C;
frequency relative to
fO at 12 V;
20 kHz < fO
< 150 kHz

TDA 4916 GG
not gone below VSL.
min. typ. max.
Temperature- ∆fτ/fO –3 3 % – 25 °C < TA
dependence of < + 85 °C;
nominal frequency VS = 12 V;
relative to
fO at 25 °C;
20 kHz < fO
< 150 kHz
Nominal frequency f20150 0.92 fO fO 1.08 fO kHz1) 20 kHz to 150 kHz
Nominal frequency f150250 0.88 fO fO 1.12 fO kHz1),2) 150 kHz to 250 kHz
Nominal frequency f250300 0.85 fO fO 1.15 fO kHz1),2) 250 kHz to 300 kHz
Maximum duty cycle ν20150 48 52 %2) 20 kHz to 150 kHz
Ramp Generator
Frequency range f 0.05 300 kHz
Maximum voltage at VCRH 4.8 5.8 6.8 V
CR
Minimum voltage VCRL 1.4 1.8 2.2 V
at CR
Discharge current at Idis 0.75 1.00 1.25 mA internally fixed
CR
Capacitance at CR CR 10 pF
ON-time spread ∆tOt/tOt –9 9 % Cr = 200 pF;
(limited by CSS) VIK1 > VSSH;
IRr = 150 µA;
TA = 25 °C;
relative to
tOt = 4.0 µs
1) CT; RT (see oscillator nomogram).
2)
See diagram: Tolerance of oscillator frequency, duty cycle.

TDA 4916 GG
not gone below VSL.
min. typ. max.
ON-time drift ∆tOt/tOt –2 2 % Cr = 200 pF;
VIK1 > VCAH;
IRr = 150 µA;
relative to
tOt = 25 °C
ON-time spread tOt 3.6 4.0 4.4 µs Cr = 200 pF;
VIK1 > VCAH;
IRr = 150 µA
Operational Amplifier OP
Open-loop gain Go 60 80 100 dB IQ OP = 100 µA
Input offset voltage Vio –5 +5 mV IQ OP = 100 µA
Input current – Ii 1 µA
Input common-mode Vcm – 0.2 4 V
range
Output current IQ OP –3 mA 0.5 < VQ OP < 15 V
Output voltage VQ OP 0.5 15 V 0 mA < IQ OP < 2 mA
Transit frequency ft 2 5 8 MHz
Transit phase φt 90 120 150 Deg.
Temp. coeff. of Vio Tc – 10 + 10 µV/K
Rate of rise of ∆V/∆t 1 ±3 6 V/µs IQ OP = 100 µA
voltage at output
Comparator K1
Input current – IK1 1 µA
Input common-mode Vcm 0 VCAH V
range
Turn-OFF delay tOFF 200 400 ns1) Nominal load 1 nF
at Q SIP
1) Step function ∆V – 100 mV ∆V + 100 mV (for delay from comparator input to Q SIP).

TDA 4916 GG
not gone below VSL.
min. typ. max.
Overvoltage K3
Input current – Ii 0.2 µA
Switching voltage VSW VREF – VREF + V
5 mV 5 mV
Turn-OFF delay tOFF 1 2 4 µs
Undervoltage K4
Input current at K4 – Ii 0.2 µA
Switching voltage VSW VREF – VREF + V
at K4 5 mV 5 mV
Hysteresis current Ihy4H 5 10 15 µA V+ IK4 < Vsw
Ihy4L 0.1 µA V+ IK4 > Vsw
Turn-OFF delay to 1 2 4 µs1)
Current Sensor K5; Overcurrent Turn-OFF K6

Input current – Idyn 1 µA
Input offset voltage Vio –5 +5 mV
Input Vcm 0 4 V
common-mode
range
Turn-OFF delay tOFF 150 300 ns2) Load 1 nF at Q SIP
250 400 ns3)
Output K6 inhibited IQK6 2 µA VQK6 = 5 V
Conducting VQK6 1.2 V IQK6 = 1 mA
1) Step function VREF – 100 mV VREF + 100 mV (for delay from comparator input to Q SIP).
2)
Step function ∆V – 100 mV ∆V + 100 mV (for delay from comparator input to Q SIP).
3) Step function ∆V – 10 mV ∆V + 10 mV (for delay from comparator input to Q SIP).

TDA 4916 GG
not gone below VSL.
min. typ. max.
Soft Start CSS

Charging current – Ich 4 5 8 µA
at CSS
Discharge current at Idis 0.8 1.5 3.0 µA
CSS
Upper clamping VSSH 4.4 4.8 5.2 V
voltage
Difference VDSS 0.1 V VCRH – VSSH
VCRH – VSSH
Switching voltage of VK2 1.1 1.4 1.7 V
K2
Pulse Omission PO
Charging current at – Ich 4 6 9 µA
PO int.
Charging current at Ich 1 mA
PO ext.
Voltage at – K7 V– K7 VS/3 VS/3 VS/3 V
–5% +5%
Upper clamping VPOH V-K7 V-K7 V-K7 V 0 mA < IPO < 1 mA
voltage at + K7 + 0.2 + 0.7 + 1.2
Minimum voltage VPOM 1 V
applied to PO
Synchronization
Input I SYN II SYN – 70 200 µA 0 V< VI SYN < 4.5 V
Switching threshold
at I SYN
Open VI SYNO 1.5 2.7 3.5 V
Rising edge VI SYNR 2.5 3.4 4.0 V
Falling edge VI SYNF 1.0 2.0 3.0 V

TDA 4916 GG
not gone below VSL.
min. typ. max.
Switchover delay int. tdf-s
free-running - 15 35 60 µs
synchronized
synchronized - tds-f 9 18 35 µs
free-running
Limiting diodes – II SYN 0 2 mA VI SYN < 1 V
II SYN 0 2 mA VI SYN > 5 V
Output Q SYN
High VQ SYNH 4.1 V – 500 µA < IQ SYN
< 0 µA
Low VQ SYNL 0.6 V 0 µA< IQ SYN
< 500 µA
Fan-out of Q SYN 2 Q SYN to 0V GND
for control I SYN allowed
Series Feed
Series Feed
Threshold at VS VSFTH 9.0 10.0 10.5 V ISF > 5 µA;
VSF = 13 V
VSH to VSFTH Gap VSFGAP 500 – – mV
Maximum current ISF max 500 – – µA VS = 11.5 V;
VSF = 12.5 V
Voltage at Z1 VZ11 5 – – V IZ1 = 20 µA;
0 ≤ VS ≤ 8 V
Voltage at Z1 VZ12 – – 8 V IZ1 = 500 µA
0 ≤ VS ≤ 8 V
Output Driver Q SIP

Saturation voltage VQ SIPH 1.8 2.0 V IQ SIP = 0 mA
source VQ SIPH 2.2 2.5 V IQ SIP = – 1 mA
VQ SIPH 2.5 3.0 V IQ SIP = – 200 mA
VS = VQ SIP > VSon
Saturation voltage VQ SIPL 0.1 0.5 V IQ SIP = 10 mA
sink VQ SIPL 1.7 2.2 V IQ SIP = 200 mA
VS = VQ SIP > VSon

TDA 4916 GG
not gone below VSL.
min. typ. max.
Saturation voltage VQ SIPP 1.5 V IQ SIP = + 5 mA
sink IC passive
Output current
Falling edge IQ SIP 0.7 1.0 1.5 A1) CQ SIP = 10 nF;
VS = VQ SIP = 12 V
Rising edge – IQ SIP 0.7 1.0 1.5 A1) CQ SIP = 10 nF;
VS = VQ SIP = 12 V
Output voltage
Fall time tQ SIPF 200 ns2) CQ SIP = 10 nF;
VS = VQ SIP = 12 V
Rise time tQ SIPR 200 ns2) CQ SIP = 10 nF;
VS = VQ SIP = 12 V
1)
Maximum dynamic current during rising or falling edge.
2)
Voltage level 10 %/90 %.

TDA 4916 GG
Figure 3
Application Circuit 1: Forward Converter with Output Regulation

TDA 4916 GG
Figure 4
Application Circuit 2: Flyback Converter with EMF Regulation

TDA 4916 GG
Figure 5
Timing Diagram

TDA 4916 GG
Figure 6
Soft Start CSS / Fault/ON - OFF

TDA 4916 GG
Nomogram for FG
fo = 97.5 kHz @ Tj = 25 °C; RT = 40.2 kΩ; CT = 560 pF

TDA 4916 GG
Instructions for the Approximate Calculation of the Maximum Duty Cycle of the FG
when RVS or RGND is Connected to Input CT.
1. General remarks
Duty cycle ν = ON time/period
Time t = CT ∆VCT/ICT
∆VCT = approx. 0.6 V
Current IRGND = 2.2 V/RGND
Current IRT = 2.5 V/RT
Current IRVS = (12 V − 2.2 V)/RVS
Mean value VCT Mean = approx. 2.2 V
To facilitate better general understanding, the equations are not abbreviated in the
following.
The wanted quantity can be isolated using the rules of arithmetic.
2. Calculation for connection of RVS (ν > 0.5)
CT ⋅ 0.6 V
------------------------------
I RT – I RVS
ν max = --------------------------------------------------------------------
CT ⋅ 0.6 V C T ⋅ 0.6 V
------------------------------ + ------------------------------
I RT – I RVS I RT + I RVS
3. Calculation for connection of RGND (ν < 0.5)
CT ⋅ 0.6 V
------------------------------------
I RT + I RGND
ν max = -------------------------------------------------------------------------------
CT ⋅ 0.6 V C T ⋅ 0.6 V
------------------------------------ + ------------------------------------
I RT + I RGND I RT – I RGND

TDA 4916 GG
Duty Cycle Limiting fFG = 100 kHz

Example for νmax = 44 %:
Step ➀ to get 44 % a resistor RGND = 220 kΩ is found
Step ➁ for the same ν we get RT = 39 kΩ to set fFG to 100 kHz

TDA 4916 GG
Tolerance of Osc. Frequency ∆fmax versus Osc. Frequency f
Tolerance of Duty Cycle ∆νmax versus Osc. Frequency f

TDA 4916 GG
Package Outlines
P-DSO-24-1 (SMD)
(Plastic Dual Small Outline Package)
GPS05144
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”
SMD = Surface Mounted Device Dimensions in mm

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Schnelligkeit den entscheidenden Give us the chance to prove the best of
Wettbewerbsvorsprung zu verschaffen. performance through the best of quality
Geben Sie uns die Chance, hohe – you will be convinced.
Leistung durch umfassende Qualität zu
beweisen.
Wir werden Sie überzeugen.
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Published by Infineon Technologies AG

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PWM-FF Ic Tda4916gg

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Datasheet, V2.

SMPS IC with MOSFET

Power Management & Supply

Revision History: 1996-05-01 Datasheet

Type Ordering Code Package

Functional Description and Application

Version 2.0 3 1 May 1996

Version 2.0 4 1 May 1996

Pin Definitions and Functions

Pin No. Symbol Function

Version 2.0 5 1 May 1996

Version 2.0 7 1 May 1996

Comparator K1 (duty factor setting for voltage mode control)

Comparators K3 (overvoltage), K4 (undervoltage), VS Undervoltage, VREF

Comparator K5 (duty factor setting for current mode control)

Comparator K6 (overcurrent turn-OFF)

Version 2.0 8 1 May 1996

Turn-OFF Flip-Flop AFF

Soft Start CSS

Version 2.0 9 1 May 1996

Reference Voltage VREF

Synchronization I SYN, Q SYN

SIPMOS Driver Output Q SIP

Version 2.0 10 1 May 1996

Version 2.0 11 1 May 1996

Absolute Maximum Ratings

Version 2.0 12 1 May 1996

Version 2.0 13 1 May 1996

Version 2.0 14 1 May 1996

Version 2.0 15 1 May 1996

Version 2.0 16 1 May 1996

Current Sensor K5; Overcurrent Turn-OFF K6

Version 2.0 17 1 May 1996

Soft Start CSS

Version 2.0 18 1 May 1996

Output Driver Q SIP

Version 2.0 19 1 May 1996

Version 2.0 20 1 May 1996

Version 2.0 21 1 May 1996

Version 2.0 22 1 May 1996

Version 2.0 23 1 May 1996

Version 2.0 24 1 May 1996

Version 2.0 25 1 May 1996

3. Calculation for connection of RGND (ν < 0.5)

Version 2.0 26 1 May 1996

Duty Cycle Limiting fFG = 100 kHz

Version 2.0 27 1 May 1996

Tolerance of Osc. Frequency ∆fmax versus Osc. Frequency f

Tolerance of Duty Cycle ∆νmax versus Osc. Frequency f

Version 2.0 28 1 May 1996

Version 2.0 29 1 May 1996

Qualität hat für uns eine umfassende Quality takes on an allencompassing

Published by Infineon Technologies AG

Datasheets for electronics components.

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