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    Generic IOMMU APIs

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    Rajesh ravi
    The document discusses dynamic DMA mapping using the generic device API. It describes the basic DMA API and extensions for supporting non-consistent memory machines. The basic API provides functions for allocating consistent DMA-coherent memory buffers and mapping device memory for DMA. It allows drivers to avoid reimplementing interrupt handling by modeling interrupt controllers as irqchips.

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    Generic IOMMU APIs

    Uploaded by

    Rajesh ravi
    83 views2 pages
    The document discusses dynamic DMA mapping using the generic device API. It describes the basic DMA API and extensions for supporting non-consistent memory machines. The basic API provides functions for allocating consistent DMA-coherent memory buffers and mapping device memory for DMA. It allows drivers to avoid reimplementing interrupt handling by modeling interrupt controllers as irqchips.

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    Generic IOMMU APIs

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    The document discusses dynamic DMA mapping using the generic device API. It describes the basic DMA API and extensions for supporting non-consistent memory machines. The basic API provides functions for allocating consistent DMA-coherent memory buffers and mapping device memory for DMA. It allows drivers to avoid reimplementing interrupt handling by modeling interrupt controllers as irqchips.

    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
    Download as txt, pdf, or txt
    83 views2 pages

    Generic IOMMU APIs

    Uploaded by

    Rajesh ravi
    The document discusses dynamic DMA mapping using the generic device API. It describes the basic DMA API and extensions for supporting non-consistent memory machines. The basic API provides functions for allocating consistent DMA-coherent memory buffers and mapping device memory for DMA. It allows drivers to avoid reimplementing interrupt handling by modeling interrupt controllers as irqchips.

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    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
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    The number of interrupt controllers registered as unique irqchips

    show a rising tendency: for example subdrivers of different kinds


    such as GPIO controllers avoid reimplementing identical callback
    mechanisms as the IRQ core system by modelling their interrupt
    handlers as irqchips, i.e. in effect cascading interrupt controllers.

    Here the interrupt number loose all kind of correspondence to


    hardware interrupt numbers: whereas in the past, IRQ numbers could
    be chosen so they matched the hardware IRQ line into the root
    interrupt controller (i.e. the component actually fireing the
    interrupt line to the CPU) nowadays this number is just a number.

    For this reason we need a mechanism to separate controller-local


    interrupt numbers, called hardware irq's, from Linux IRQ numbers.
    ============================================
    Dynamic DMA mapping using the generic device
    ============================================

    :Author: James E.J. Bottomley <James.Bottomley@HansenPartnership.com>

    This document describes the DMA API. For a more gentle introduction
    of the API (and actual examples), see Documentation/DMA-API-HOWTO.txt.

    This API is split into two pieces. Part I describes the basic API.
    Part II describes extensions for supporting non-consistent memory
    machines. Unless you know that your driver absolutely has to support
    non-consistent platforms (this is usually only legacy platforms) you
    should only use the API described in part I.

    Part I - dma_API
    ----------------

    To get the dma_API, you must #include <linux/dma-mapping.h>. This


    provides dma_addr_t and the interfaces described below.

    A dma_addr_t can hold any valid DMA address for the platform. It can be
    given to a device to use as a DMA source or target. A CPU cannot reference
    a dma_addr_t directly because there may be translation between its physical
    address space and the DMA address space.

    Part Ia - Using large DMA-coherent buffers


    ------------------------------------------

    ::

    >-------void *
    >-------dma_alloc_coherent(struct device *dev, size_t size,
    >------->------->------- dma_addr_t *dma_handle, gfp_t flag)

    Consistent memory is memory for which a write by either the device or


    the processor can immediately be read by the processor or device
    without having to worry about caching effects. (You may however need
    to make sure to flush the processor's write buffers before telling
    devices to read that memory.)

    This routine allocates a region of <size> bytes of consistent memory.

    It returns a pointer to the allocated region (in the processor's virtual


    address space) or NULL if the allocation failed.
    It also returns a <dma_handle> which may be cast to an unsigned integer the
    same width as the bus and given to the device as the DMA address base of
    the region.

    Note: consistent memory can be expensive on some platforms, and the


    minimum allocation length may be as big as a page

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