Materials Science in Semiconductor Processing 80 (2018) 24–30

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Materials Science in Semiconductor Processing

journal homepage: www.elsevier.com/locate/mssp

Improved device characteristics obtained in 4H-SiC MOSFET using high-k T

dielectric stack with ultrathin SiO2-AlN as interfacial layers
Vudumula Pavan Kumar Reddy, Siva Kotamraju
⁎

Department of Electronics and Communication Engineering, Indian Institute of Information Technology Sri City, A.P., India

ARTICLE INFO ABSTRACT

Keywords: A novel method of stacking dielectric layers on top of Silicon carbide (SiC) is proposed to address the most
High-k dielectrics common Silicon dioxide (SiO2)-SiC interface issues in SiC based metal oxide semiconductor (MOS) devices.
Specific on resistance Aluminum nitride (AlN) as an interfacial layer, instead of SiO2, between hafnium oxide (HfO2) and SiC showed
Mobility improved device characteristics. However, incorporating SiO2 along with AlN as an interfacial layer is found to
SiC MOSFET
be the best way of stacking dielectric layers. This is concluded, based on the changes observed in the electrical
Sentaurus TCAD
characteristics of the device by intentionally varying lattice temperature (T), interface trap density (Dit) and
junction field effect transistor (JFET) width. All the investigations are done in 4H-SiC half-cell planar n-channel
MOS field effect transistor (MOSFET) using commercially available technology computer aided design (TCAD)
software sentaurus device. Theoretical calculations show good agreement with the simulated results, and are
compared with the published results.

1. Introduction [9]. Low band offsets increases the probability of carriers tunneling
through the dielectric. This issue has been addressed by inserting a thin
SiC based power MOSFETs are regarded as promising devices for layer of SiO2 between HfO2 and SiC [7,9]. The same is the case with
applications which require faster switching and withstand higher tem- AlN, which provides a conduction band offset of about 1.7 eV. Although
peratures without losing device properties [1,2]. The full potential of AlN and HfO2 have been individually investigated as high-k dielectric
SiC devices has not been realized due to low field effect mobility re- [10], no study has been done with AlN as an interfacial layer between
sulting from the high density of traps at the SiO2-SiC interface [3]. It is HfO2 and SiC. AlN provides good lattice matching and thermal expan-
challenging to design a device which has high channel mobility, low sion properties with respect to SiC. Nevertheless, in this study SiO2 is
specific on resistance (Ron,sp), and high blocking voltage simultaneously also being used as an interface layer in combination with AlN as it
as there exists a trade off between these device parameters. The choice provides the highest conduction band offset of about 2.7 eV among the
of gate insulator plays a crucial role in the performance of the device, available dielectrics [11]. While AlN provides good thermo-mechanical
especially on the channel mobility. In addition to coulomb scattering matching with SiC [12], direct deposition of AlN on SiC does introduce
due to interface traps, there could be other scattering mechanisms such interface trap charges causing high leakage currents. Interface trap
as impurity scattering, a phonon scattering, and surface roughness af- density and temperature have been intentionally varied to observe the
fecting the channel mobility [4]. The source of interface traps is pri- magnitude of changes AlN introduces in device characteristics. In this
marily due to dangling bonds, carbon clusters or carbon-related defects paper, we explored sub threshold swing, mobility and Ron,sp char-
from high-temperature oxidation and the near interface traps located acteristics in detail as these are important parameters defining the
1–2 nm in the oxide [5,6]. The gate insulator should ideally minimize switching speed of the device. Moreover, sub threshold characteristics
interface traps and withstand high electric fields during the forward can also be used to understand the gate oxide performance. Two-di-
conduction/ reverse blocking mode with low gate leakage currents. In mensional numerical simulations using sentaurus device from synopsys
order to withstand high electric fields, the focus has been shifted to is utilized in this work to interpret the electrical characteristics of the
other alternative high-k dielectrics. Although HfO2 as a high-k dielectric device.
has been explored earlier, direct deposition on SiC poses a problem
[7,8]. In addition to the high density of surface traps, it leads to high
gate leakage currents due to low conduction band offset of about 0.9 eV

⁎
Corresponding author.
E-mail addresses: siva.k@iiits.in (S. Kotamraju).

https://doi.org/10.1016/j.mssp.2018.02.012
Received 13 December 2017; Received in revised form 3 February 2018; Accepted 12 February 2018
Available online 22 February 2018
1369-8001/ © 2018 Elsevier Ltd. All rights reserved.
V. Pavan Kumar Reddy, S. Kotamraju Materials Science in Semiconductor Processing 80 (2018) 24–30

Table 1
Dielectric parameters used in this work.

Material SiO2 AlN HfO2

Dielectric constant ( ) 3.9 8.5 22

Bandgap Eg (eV) 9.0 6.23 5.9
EC (eV) with respect to SiC [11] 2.7 1.7 0.9
EV (eV) with respect to SiC [11] 3.1 1.3 1.16
EOT (nm) 5 10.9 28

Table 2
Mobility parameters for 4H-SiC.

Parameter Quantity Units

mu1n.caug 40 cm2/V-s
mu2n.caug 950 cm2/V-s
ncritn.caug 1.94 × 1017 cm−3
alphan.caug 0.61 arbitrary
mu1p.caug 15.9 cm2/V-s
mu2p.caug 125 cm2/V-s
ncritp.caug 1.76 × 1019 cm−3
alphap.caug 0.34 arbitrary
betan.caug, betap.caug 2 arbitrary
vsatn, vsatp 2.2 × 1017 cm2/s
Fig. 1. Schematic view of the half-cell 4H-SiC MOSFET along with doping profile and
thickness. V = volt, cm = centimeter, s = second.

OX
2. Device structure and parameters TOX = EOT*
SiO2 (1)

A schematic cross sectional two dimensional (2D) view of 4H-SiC The following equation is used for calculating thickness of dielectric
half-cell MOSFET along with doping profile and thickness is shown in stack with SiO2 as interfacial layer.
Fig. 1.
high k
The device structure is made up of p-base region having thickness Thigh k = (EOT SiO2 )*
(2)
(tP+) of 2 µm, width (WP+/2) of 3 µm, n+ well having thickness 1 µm, SiO2

length of the channel (LCH) is of 2 µm, length of the JFET (WJ/2) is of The mobility parameters used in device simulation are listed in
2 µm, length of the gate (Wg/2) considered slightly above 4 µm in Table 2 and the material parameters in Table 3. Table 2 lists some of the
contact with the source of n+ region. The device contacts source, drain key parameters of temperature, doping and high field dependence
and gate chosen to be Aluminum metal with a work function of 4.26 eV. mobility models. The insulating material is replaced with multiple di-
Half-cell structure of the device is chosen due to its simplified simula- electrics as follows I) HfO2 (18 nm)-SiO2 (2 nm) II) HfO2 (18 nm)-AlN
tion time and mesh grid count. The device is calibrated with fine (2 nm) III) HfO2 (17 nm)-SiO2 (1 nm)-AlN (2 nm). The individual
meshing in the crucial areas like channel of the MOSFET, MOS inter- thickness values mentioned are fairly approximate values adjusted to
face, JFET region and the junction between p-type and n-type semi- EOT of 5 nm with HfO2-AlN slightly lower than 5 nm. The Ron,sp for 4H-
conductor regions with the total number of 32,000 mesh points while SiC MOSFET is given by the summation of Eqs. ((3), (4), (5) and (6))
mesh resolution at the interfaces being 0.3–0.6 nm. Fine meshing en- known for sum of channel resistance (RCH), accumulation resistance
ables to extract the results with a greater degree of accuracy. The cell (RA,SP), JFET resistance (RJFET,SP), drift resistance (RD,SP) i.e.,
pitch of the device (Wcell/2) is 5 µm with a width of 1 µm giving an R on,sp = R CH + RA,SP + RJFET,SP + RD,SP from source to drain. The equa-
active area of 5 µm × 1 µm. Physics based simulation of the device is tions are taken from reference [16], and are used for calculations of
carried out by considering band gap narrowing model, Auger re-
combination model, Shockley-Read-Hall (SRH) recombination, doping- Table 3
electric field-temperature dependent field mobility models and in- Material parameters for 4H-SiC.
complete ionization model [13]. In addition, all the simulations are
Parameter Quantity Value
carried out taking Fermi-Dirac statistics and multidimensional depen-
dent anisotropic effects (Aniso) into consideration. A full description of Eg300 (eV) band gap at 300 K 3.24
the models used can be found in reference [13]. The device structure is dielectric constant 9.66
constructed based on the reference [14], and the basic I-V character- Aniso dielectric constant - aniso 10.03
istics are verified before changes are made to the structure. There are AUGN (cm6/s) Auger-recombination parameter for electron 5 × 10−31
AUGP (cm6/s) Auger-recombination parameter for hole 2 × 10−31
few scattering mechanisms such as phonon scattering, surface rough- Nsrhn SRH concentration dependent lifetime model 1 × 1016
ness scattering, impurity scattering and coulomb scattering that de- for electron
grade the channel mobility. Lombardi model is considered for mobility Nsrhp SRH concentration dependent lifetime model 1 × 1016
degradation in this work. This model has been chosen and verified for for hole
ARICHN (A/K2 cm2) effective richardson constant for electrons 146
SiC MOSFET simulations [15]. Table 1 lists various dielectric properties
ARICHP (A/K2 cm2) effective richardson constant for holes 30
used in the paper. Gvb (eV) degeneracy factor for valence band 4
Since the dielectric constant of AlN and HfO2 is higher than SiO2, Gcb (eV) degeneracy factor for conduction band 2
the physical thickness of high-k dielectric needs to be increased in order LT.TAUN lifetime model parameter for electrons 4
to maintain the same capacitance. The physical thickness of AlN and LT.TAUP lifetime model parameter for holes 4

HfO2 are shown in Table 1 representing an EOT of 5 nm. Eq. (1) is used
1 eV = 1.602 × 10−19 J, eV = electron volt, m = meter, A = ampere, J = joule, K =
for calculating thickness of oxide for a given EOT value. kelvin, nm = nanometer, cm = centimeter, C = centigrade.

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V. Pavan Kumar Reddy, S. Kotamraju Materials Science in Semiconductor Processing 80 (2018) 24–30

Ron,sp in this paper. The specific on resistance due to SiC substrate is

neglected.
LCH Wcell
RCH =
2µinv COX (VG Vth) (3)

WJ Wcell
RA, SP = KA *
4µnA COX (VG Vth) (4)

JFET tp +Wcell
RJFET , SP =
(WJ 2WO ) (5)

D Wcell a + Wp + Wp +
RD, SP = *ln + D tD
2 a 2 (6)
Where width “a” of the JFET region given by a = (WJ-2WO). The
depletion width (WO), built-in potential (Vbi) and resistivity ( JFET) of
the device is calculated by using Eqs. ((7), (8) and (9)).
2 s Vbi
WO =
qNDJ (7) Fig. 2. Transfer characteristics of 4H-SiC MOSFET for multiple dielectric stacks at 300 K.

KT N N
Vbi = *ln A DJ
q n i2 (8)
1
JFET =
qµn NDJ (9)
The leakage current in insulator of the device is modeled using
Fowler-Nordheim (FN) tunneling (Eq. (10)), non-local tunneling at di-
electric-dielectric and dielectric-SiC interface by constructing non local
meshes. JFN is the FN current density and Fins is the field in the in-
sulator, A and B are physical constants.
B
2
JFN = AFins exp Fins (10)
The sub threshold swing for the device is calculated using Eq. (11).
d (Vg )
SS =
d (logId) (11)
It is well known that the interface trap density is highly dependent
on process in SiC. In order to account for the realistic behavior in the
Fig. 3. Output I-V characteristics of the device for multiple dielectric stacks in the linear
interface of dielectric-SiC, trap concentration in the range of 2E12 to
region.
7E12 cm−2 eV−1 is considered. Uniform distribution of trap density is
defined within the band gap in sentaurus device. For all the figures
shown in this paper, a fixed interface trap concentration of high-k dielectric stack with inclusion of AlN as interfacial layer. Fig. 3
2.5E12 cm−2 eV−1 is considered except for Figs. 7 and 8 where the trap shows the plot of Id-Vd curves in the linear region at a fixed value of
concentration value itself is varied. gate voltage (Vg).
An approximate assessment of Ron,sp can be made from the slope of
3. Results and discussion Id-Vd curves in the linear region. The HfO2-SiO2-AlN/HfO2-AlN stack
exhibits much higher drain current (Id) for any given drain voltage (Vd)
3.1. Static characteristics indicating a lower Ron,sp compared to HfO2-SiO2 stack.
The influence of temperature on the sub threshold swing is in-
The value of the threshold voltage (Vth) depends on certain physical vestigated. A plot that has been generated between sub threshold swing
parameters of the SiC MOSFET. Type and thickness of the insulator, and transconductance for three different gate dielectric stacks at
oxide-interface charge density are some of the main parameters. It has varying temperatures from 300 to 600 K is shown in Fig. 4. In general,
been observed earlier that the threshold voltage reduces with increase variation in device temperature affects transconductance, Vth, sub
in dielectric constant for a fixed physical thickness of oxide [11]. threshold swing and Ron,sp which in turn affects the switching behavior
However, when the thickness of SiO2 is reduced to match with the EOT of the device. This is because the temperature has an influence on the
of high-k dielectric, the I-V characteristics should look similar mini- intrinsic carrier concentration (ni), mobility ( µ ) and carrier lifetime.
mizing the variation in threshold voltage. Fig. 2 shows the transfer HfO2-AlN stack shows high transconductance and low sub threshold
characteristics of SiO2 (5 nm) comparing with EOT of all high-k di- swing at any given temperature. On the other hand, HfO2-SiO2 stack
electric stacks. exhibits inferior transconductance and sub threshold swing compared
The Vth using high-k dielectric stack is around 1.7 V, and the same to other two dielectric stacks. Insertion of SiO2 between HfO2 and AlN
can be slightly adjusted to a higher or lower value depending on ap- results in an intermediate value of transconductance and sub threshold
plication. For a given curve, Vth is defined as the gate voltage at which swing. Even though HfO2-AlN stack has exhibited superior character-
the maximum transconductance occurs. The transconductance values istics, a partial compromise on transconductance and sub threshold
have been extracted from Id-Vg curves at a fixed drain voltage. An in- swing is required by inserting SiO2 in order to address the high leakage
crease in transconductance has been observed in structures involving currents that come with high-k dielectrics. The main reason to include

26
V. Pavan Kumar Reddy, S. Kotamraju Materials Science in Semiconductor Processing 80 (2018) 24–30

7
10
HfO2 -SiO2 -AlN
HfO2 -SiO2
HfO2 -AlN

106

E OX (V/cm)
105

4
10
0 5 10 15 20 25 30
Gate voltage (V)

Fig. 6. Comparison of electric fields in the dielectric stack.

Fig. 4. Transconductance versus sub threshold swing at different temperatures from
300 K to 600 K.
complete dielectric stack as in Fig. 6. At higher Vg values, clearly di-
electric stack with SiO2 has an electric field much higher than AlN.
Lower electric fields are preferable as it may reduce the accumulation of
defect density over time due to lower electric field stress. When it comes
to the complete dielectric stack, HfO2-SiO2 has a high electric field at
any gate voltage as shown in the Fig. 6. This could be due to the ef-
fective permittivity of the dielectric stack being much lower as com-
pared to the dielectric stack involving SiO2. The reduction in the elec-
tric field by incorporating SiO2 between HfO2 and AlN is consistent
with lower leakage currents observed in Fig. 5 for dielectric stack with
SiO2-AlN as interfacial layers.

3.2. Mobility and ON resistance

This section focuses on the dielectric-SiC interface with an emphasis

on channel mobility. There have been many studies earlier addressing
high density of traps for SiO2-SiC interface and its influence on channel
Fig. 5. Change in the gate leakage current as a function of gate voltage at below threshold mobility ([17–19]). Post-oxidation treatment such as nitridation is
voltage. found to be one of the promising ways of enhancing channel mobility in
MOSFET with SiO2-SiC interface [20]. This method improves mobility
by reducing interface traps.
SiO2 is to suppress the leakage current. Negligible current flows in the
These traps are usually located in the band gap of SiC and more
oxide for low gate voltages. Large gate currents are not acceptable as it
towards the conduction band edge. The reported channel mobilities are
may lead to premature breakdown of the device. The off state leakage
in the range of 30–40 cm2/V-s, although larger values up to 165 cm2/V-
current has been simulated for Vg value less than Vth as shown in Fig. 5.
s has been reported earlier [21]. In this paper, we explored channel
While AlN only as an interface layer shows noticeably higher leakage
mobility and Ron,sp for SiO2-SiC and AlN-SiC interface by intentionally
current, SiO2-AlN combination reduces the leakage current by five or-
varying the temperature and trap concentration from 2E12 to
ders of magnitude.
7E12 cm−2 eV−1. However, the bulk of the dielectric stack consists of
The improved leakage current of the stacking SiO2-AlN compared to
HfO2 in both the cases. At a fixed Vd = 10 V, channel mobility as a
only AlN is due to the difference in the conduction band offset, and the
function of gate voltage by varying interface trap density from 2E12 to
reduction of electric field in the oxide. Due to less variation in con-
7E12 cm−2 eV−1 is simulated. Fig. 7 shows the mobility values ob-
duction band discontinuity between the dielectric and SiC, increasing
tained for SiO2-SiC interface and Fig. 8 shows the mobility values for
the thickness of SiO2 by a few nanometers further reduces the leakage
AlN-SiC interface. At any given trap concentration, the channel mobi-
current. However, increasing the thickness could marginally affect Vth
lity obtained in case of SiO2-SiC interface is inferior to AlN-SiC inter-
and transconductance.
face.
The amount of electric field in the gate oxide is a critical parameter
AlN as an interfacial layer offers good lattice matching and same
for the device. While SiC can sustain high electric fields up to 3 MV/cm,
coefficient of thermal expansion with SiC up to 1000 °C . The effective
it is important for the insulator to support the same and much higher
mobility is extracted covering the channel region up to 100 nm below
amount of electric fields. The dielectric stack is subjected to a higher
the interface. The mobility value obtained is approximately 55 cm2/V-s
electric field, by applying a positive voltage at the gate terminal.
for SiC-SiO2 interface compared to 80 cm2/V-s for AlN-SiC interface for
Negligible gate current flows in the oxide for low gate voltages. At
the same channel doping concentration of 4.5 × 1017 cm−3 as shown in
higher fields and temperature, the current through the gate can be
Fig. 9. It has been reported earlier that the inversion layer mobility is
described by non local tunneling at dielectric-dielectric interface, di-
influenced more at the first 5 nm from the interface [22]. In our study,
electric-SiC interface and also Fowler-Nordheim (FN) tunneling me-
we extracted the mobility at varying distances (2 nm, 10 nm, and
chanism either from the conduction band or the valence band of SiC.
50 nm) underneath the dielectric-SiC interface. At all locations, the
The electric field is simulated individually for the three combinations of
AlN-SiC interface consistently shows at least 1.5 times better mobility

27
V. Pavan Kumar Reddy, S. Kotamraju Materials Science in Semiconductor Processing 80 (2018) 24–30

sustaining high electric fields. There have been intensive studies for
HfO2 as an alternative to SiO2 in silicon based devices. It is found to be
the most suitable high-k dielectric material with low tunneling current
in silicon technology [25].
Fig. 9 shows channel mobility as a function of gate voltage with
electron density on the other axis. Higher the electron density lower
will be the channel mobility and the reduction in mobility for the SiO2-
SiC interface is more pronounced due to higher inversion charge den-
sity. The improved mobility values for AlN-SiC interface must help in
reducing the overall specific on resistance during the forward conduc-
tion mode. In order to verify, Ron,sp has been calculated for the entire
channel region from source to drain.
The total specific on resistance is around 3.5 m -cm2 for SiO2-SiC
interface against 2.7 m -cm2 for AlN-SiC interface at a fixed trap
concentration of 2.5E12 cm−2 eV−1. The Ron,sp is calculated in the
channel, accumulation, JFET and drift region using the (3) to (6)
mentioned in the device structure section. The mobility values ex-
Fig. 7. Mobility as a function of gate voltage for HfO2-SiO2 by varying different interface tracted from the sentaurus visual are used for the Ron,sp calculations.
trap concentrations ranging from 2E12 cm−2 eV−1 to 7E12 cm−2 eV−1.
Plots have been generated comparing the calculated and simulated
specific on resistance values with respect to the JFET width for all the
three dielectric stacks explored in this paper and shown in Fig. 10.
There has been good agreement between calculated and simulated va-
lues.
Fig. 11 shows the variation of total specific on resistance and total
mobility of the device with respect to temperature comparing SiO2-SiC
and AlN-SiC interface. Ron,sp is supposed to increase, and mobility is
supposed to reduce with an increase in the temperature and the same
trend can be observed in both the plots. SiO2-SiC interface showing
higher specific on resistance and lower mobility at all the temperatures
compared to AlN-SiC interface. Higher Ron,sp can be attributed to the
reduction in the overall mobility of the device with SiO2-SiC interface.
The total mobility and Ron,sp in case of AlN-SiC is found to be better
than that of SiO2-SiC interface with HfO2 as bulk dielectric layer and
the same can be concluded from Fig. 11.
Summing up, it is important to carefully extract effective mobility
values at varying distances from the interface. The mobility values are
lower near to the interface and higher as we move away from the in-
Fig. 8. Mobility as a function of gate voltage for HfO2-SiO2-AlN by varying different in-
terface. In order to make a fair comparison, we ensure that the extracted
terface trap concentrations ranging from 2E12 cm−2 eV−1 to 7E12 cm−2 eV−1.
values are within the same distance from the interface. In this work, we
made a comparison between calculated and simulated results for Ron,sp.
There is a very little discrepancy noticed between simulated and calcu-
lated data. The type of dielectric stack on SiC does play a crucial role on
the device characteristics. Based on our results, we finally come up with
the proposed dielectric structure of SiC MOSFET with the sketch of band
alignment shown in Fig. 12. With this structure, the low conduction band

Fig. 9. Inversion charge density as a function of gate voltage. Higher inversion charge
density is observed in case of SiO2-SiC interface resulting in lower mobility.

than the SiC-SiO2 interface. It is to be noted that for the given settings,
we are doing a relative comparison of mobility. There have been pub-
lished results earlier with channel mobility in the range of 80–170 cm2/
V-s ([23,24]). These papers reported Al2O3 (Aluminum oxide) as their
main layer in the stack with SiO2 as interfacial layer. It is very critical to Fig. 10. Specific on resistance of the device (from source to drain) as a function of JFET
use HfO2 as the thickest layer in the dielectric stack as it will help in width from 2 to 8 μm. There is a very little discrepancy between simulated and calculated
values.

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V. Pavan Kumar Reddy, S. Kotamraju Materials Science in Semiconductor Processing 80 (2018) 24–30

Fig. 11. Variation of total mobility and Ron,sp by varying temperature from T = 300 K to
T = 700 K.

Fig. 14. Schematic of clamped inductive circuit implemented in mixed mode environ-
ment.

4. Clamped inductive switching

Mixed-mode environment has been used for simulating the dynamic

characteristics of the MOSFET where the device is embedded in an
external gate drive circuit. The applied drive circuit shown in Fig. 14
consists of a clamped inductive switching circuit where the drain
terminal is connected to the DC voltage source Vdd of 900 V and a 1 mH
inductor as load. The flywheel diode is a 1.2 kV 4H-SiC PIN diode with
specifications taken from reference [14] connected across the inductor
for discharging of drain current during turn off. The gate is connected to
a time-dependent voltage source with a double-pulse switching input
VPULSE. The switching characteristics of the device are simulated by
applying a double-pulse of voltage raising from 0 V to 15 V, to the gate
approximately for 10 μs. The value of the gate drive resistor is fixed at
Fig. 12. The schematic band alignments of dielectric stack HfO2-SiO2-AlN on SiC.
10 for all the simulations. Simulations were performed to obtain the
switching characteristic of the device with two combinations HfO2-SiO2
and HfO2-SiO2-AlN of gate dielectric stack placed on top of SiC. Turn on
(Eon) and turn off (Eoff) losses are analyzed for the HfO2-SiO2 and HfO2-
SiO2-AlN dielectric stacks in this paper. Fig. 15 shows the switching
waveforms of the device at 300 K for both the cases. It has been in-
dependently verified that Eon is almost same in both cases, while there
is a significant reduction in Eoff when AlN is included in the dielectric
stack. Further work is needed to evaluate the switching characteristics
of the device at different circuit settings.

5. Conclusion

This study shows that using a suitable dielectric stack structure, an

improvement in the mobility and Ron,sp of the device is possible. AlN is
Fig. 13. Proposed structure of dielectric stack (HfO2-SiO2-AlN) for SiC based MOS devices
found to be a better choice instead of SiO2 directly on SiC, owing to
to reduce the influence of interface trap charges on device characteristics.
excellent lattice matching and thermal expansion coefficient. From the
results, AlN shows lesser dependence on interface trap density com-
offset at high-k/SiC interface can be addressed simultaneously improving pared to SiO2. HfO2 is being used as the main high-k dielectric layer on
the device performance. The electrical characteristics of this structure top of SiC with ultra thin SiO2-AlN as intermediate layers. The barrier
comparing with other dielectric stacks has been discussed in detail in this reduction of SiC with HfO2 has been addressed by using SiO2 on top of
paper (Figs. 2 to 11). Fig. 13 shows the mobility variation and direction AlN layer, thus reducing the leakage current in off state. Extracted sub
of current flow for the proposed structure. threshold swing and transconductance are found to be superior for

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V. Pavan Kumar Reddy, S. Kotamraju Materials Science in Semiconductor Processing 80 (2018) 24–30

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