MCF51QE128 Series

Freescale Semiconductor Document Number: MCF51QE128
Data Sheet: Technical Data Rev. 7, 10/2008

An Energy Efficient Solution by Freescale
MCF51QE128 Series MCF51QE128

Covers: MCF51QE128, MCF51QE96, MCF51QE64, 80-LQFP 64-LQFP
MCF51QE32 Case 917A Case 840F
14 mm2 10 mm2
• 32-Bit Version 1 ColdFire® Central Processor Unit (CPU) • Development Support
– Up to 50.33-MHz ColdFire V1 CPU above 2.4V, – Single-wire background debug interface
40-MHz CPU above 2.1V, and 20-MHz CPU above – 4 PC plus 2 address (optional data) breakpoint registers
1.8V, across temperature range with programmable 1- or 2-level trigger response
– Provides 0.94 Dhrystone 2.1 MIPS per MHz – 64-entry processor status and debug data trace buffer
performance when running from internal RAM with programmable start/stop conditions
(0.76 DMIPS/MHz from flash) • ADC — 24-channel, 12-bit resolution; 2.5 μs conversion
– Implements Instruction Set Revision C (ISA_C) time; automatic compare function; 1.7 mV/°C temperature
– Support for up to 30 peripheral interrupt requests and sensor; internal bandgap reference channel; operation in
seven software interrupts stop3; fully functional from 3.6V to 1.8V
• On-Chip Memory • ACMPx — Two analog comparators with selectable
– Flash read/program/erase over full operating voltage interrupt on rising, falling, or either edge of comparator
and temperature output; compare option to fixed internal bandgap reference
– Random-access memory (RAM) voltage; outputs can be optionally routed to TPM module;
– Security circuitry to prevent unauthorized access to operation in stop3
RAM and flash contents • SCIx — Two SCIs with full duplex non-return to zero
• Power-Saving Modes (NRZ); LIN master extended break generation; LIN slave
– Two low power stop modes; reduced power wait mode extended break detection; wake up on active edge
– Peripheral clock enable register can disable clocks to • SPIx— Two serial peripheral interfaces with Full-duplex or
unused modules, reducing currents; allows clocks to single-wire bidirectional; Double-buffered transmit and
remain enabled to specific peripherals in stop3 mode receive; MSB-first or LSB-first shifting
– Very low power external oscillator can be used in stop3 • IICx — Two IICs with; Up to 100 kbps with maximum bus
mode to provide accurate clock to active peripherals loading; Multi-master operation; Programmable slave
– Very low power real time counter for use in run, wait, address; Interrupt driven byte-by-byte data transfer;
and stop modes with internal and external clock sources supports broadcast mode and 10 bit addressing
– 6 μs typical wake up time from stop modes • TPMx — One 6-channel and two 3-channel; Selectable
• Clock Source Options input capture, output compare, or buffered edge- or
– Oscillator (XOSC) — Loop-control Pierce oscillator; center-aligned PWMs on each channel
Crystal or ceramic resonator range of 31.25 kHz to • RTC — 8-bit modulus counter with binary or decimal
38.4 kHz or 1 MHz to 16 MHz based prescaler; External clock source for precise time
– Internal Clock Source (ICS) — FLL controlled by base, time-of-day, calendar or task scheduling functions;
internal or external reference; precision trimming of Free running on-chip low power oscillator (1 kHz) for
internal reference allows 0.2% resolution and 2% cyclic wake-up without external components
deviation; supports CPU freq. from 2 to 50.33 MHz • Input/Output
• System Protection – 70 GPIOs and 1 input-only and 1 output-only pin
– Watchdog computer operating properly (COP) reset – 16 KBI interrupts with selectable polarity
with option to run from dedicated 1-kHz internal clock – Hysteresis and configurable pull-up device on all input
source or bus clock pins; Configurable slew rate and drive strength on all
– Low-voltage detection with reset or interrupt; selectable output pins.
trip points – SET/CLR registers on 16 pins (PTC and PTE)
– Illegal opcode and illegal address detection with – 16 bits of Rapid GPIO connected to the CPU’s
programmable reset or exception response high-speed local bus with set, clear, and toggle
– Flash block protection functionality
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2008. All rights reserved.
Table of Contents
1 MCF51QE128 Series Comparison . . . . . . . . . . . . . . . . . . . . . .4 3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.10.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 21
3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.10.2 TPM Module Timing . . . . . . . . . . . . . . . . . . . . . 23
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.10.3 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . .9 3.11 Analog Comparator (ACMP) Electricals . . . . . . . . . . . 27
3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . .9 3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .10 3.13 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . .11 4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 5 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .15 5.1 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.8 External Oscillator (XOSC) Characteristics . . . . . . . . .18 6 Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.9 Internal Clock Source (ICS) Characteristics . . . . . . . . .19 7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
MCF51QE128 Series Data Sheet, Rev. 7

2 Freescale Semiconductor
PTA7/TPM2CH2/ADP9
TPM1CH2-0 PTA6/TPM1CH2/ADP8
V1 ColdFire CORE
RESET
3-CHANNEL TIMER/PWM PTA5/IRQ/TPM1CLK/RESET
PORT A
TPM1CLK
BKGD/MS
MODULE (TPM1) PTA4/ACMP1O/BKGD/MS

CPU PTA3/KBI1P3/SCL1/ADP3
ACMP1O
ANALOG COMPARATOR PTA2/KBI1P2/SDA1/ADP2
ACMP1+
(ACMP1) PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1-
ACMP1-
BDC / Debug IP Bus Bridge PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+
EXTAL
INTERNAL CLOCK PTB7/SCL1/EXTAL
SOURCE (ICS) XTAL
SYSTEM CONTROL PTB6/SDA1/XTAL
OSCILLATOR (XOSC) PTB5/TPM1CH1/SS1
PORT B
RESETS AND INTERRUPTS
TPM2CH2-0 3 PTB4/TPM2CH1/MISO1
MODES OF OPERATION
POWER MANAGEMENT 3-CHANNEL TIMER/PWM PTB3/KBI1P7/MOSI1/ADP7
MODULE (TPM2) PTB2/KBI1P6/SPSCK1/ADP6
COP LVD TPM2CLK
IRQ
PTB1/KBI1P5/TxD1/ADP5
SCL1 PTB0/KBI1P4/RxD1/ADP4
INTC -
IIC MODULE (IIC1) SDA1
PTC7/RGPIO15/TxD2/ACMP2-
ACMP2+
PTC6/RGPIO14/RxD2/ACMP2+
ANALOG COMPARATOR ACMP2O
PTC5/RGPIO13/TPM3CH5/ACMP2O
PORT C
(ACMP2) ACMP2-
USER FLASH PTC4/RGPIO12/TPM3CH4/RSTO
128K / 64K PTC3/RGPIO11/TPM3CH3
TPM3CH5-0
PTC2/RGPIO10/TPM3CH2
6-CHANNEL TIMER/PWM PTC1/RGPIO9/TPM3CH1
MODULE (TPM3) TPM3CLK PTC0/RGPIO8/TPM3CH0
USER RAM
16 PTD7/KBI2P7
8K / 6K / 4K
PTD6/KBI2P6
SERIAL COMMUNICATIONS TxD1
PTD5/KBI2P5
PORT D
INTERFACE (SCI1) RxD1
Rapid GPIO PTD4/KBI2P4
SS2 PTD3/KBI2P3/SS2
MISO2 PTD2/KBI2P2/MISO2
SERIAL PERIPHERAL
MOSI2 PTD1/KBI2P1/MOSI2
REAL TIME COUNTER (RTC) INTERFACE MODULE (SPI2)
SPSCK2 PTD0/KBI2P0/SPSCK2
VDD
VDD TxD2 PTE7/RGPIO7/TPM3CLK
VOLTAGE SERIAL COMMUNICATIONS RxD2 PTE6/RGPIO6
VSS REGULATOR INTERFACE (SCI2) PTE5/RGPIO5
PORT E
VSS
PTE4/RGPIO4
SS1
PTJ7 PTE3/RGPIO3/SS1
MISO1
PTJ6 SERIAL PERIPHERAL PTE2/RGPIO2/MISO1
MOSI1
INTERFACE MODULE (SPI1) PTE1/RGPIO1/MOSI1
PORT J
PTJ5
SPSCK1
PTJ4 PTE0/RGPIO0/TPM2CLK/SPSCK1
PTJ3
PTF7/ADP17
PTJ2
PTF6/ADP16
PTJ1 24-CHANNEL,12-BIT PTF5/ADP15
PORT F
PTJ0 ANALOG-TO-DIGITAL PTF4/ADP14

VREFH CONVERTER (ADC)
VREFL PTF3/ADP13
VDDA PTF2/ADP12
VSSA PTF1/ADP11
PTF0/ADP10
PTH7/SDA2 SDA2
PTH6/SCL2 SCL2 IIC MODULE (IIC2) PTG7/ADP23
PTG6/ADP22
PORT H
PTH5
PORT G
PTH4 PTG5/ADP21
PTH3 PTG4/ADP20
PTH2 PTG3/ADP19
PTH1 PTG2/ADP18
PTH0 PTG1
PTG0
Figure 1. MCF51QE128 Series Block Diagram

Freescale Semiconductor 3
MCF51QE128 Series Comparison
1 MCF51QE128 Series Comparison

The following table compares the various device derivatives available within the MCF51QE128 series.
Table 1. MCF51QE128 Series Features by MCU and Package
Feature MCF51QE128 MCF51QE96 MCF51QE64 MCF51QE32
Flash size (bytes) 131072 98304 65536 32768
RAM size (bytes) 8192 8192 8192 8192
Pin quantity 80 64 80 64 64 64
Version 1 ColdFire core yes
ACMP1 yes
ACMP2 yes
ADC channels 24 20 24 20 20 20
DBG yes
ICS yes
IIC1 yes
IIC2 yes
KBI 16
Port I/O1, 2 70 54 70 54 54 54
Rapid GPIO yes
RTC yes
SCI1 yes
SCI2 yes
SPI1 yes
SPI2 yes
External IRQ yes
TPM1 channels 3
TPM2 channels 3
TPM3 channels 6
XOSC yes
1 Port I/O count does not include the input-only PTA5/IRQ/TPM1CLK/RESET or the output-only
PTA4/ACMP1O/BKGD/MS.
2 16 bits associated with Ports C and E are shadowed with ColdFire Rapid GPIO module.

Pin Assignments
2 Pin Assignments
This section describes the pin assignments for the available packages. See Table 1 for pin availability by package pin-count.
PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+
PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1-
PTC5/RGPIO13/TPM3CH5/ACMP2O
PTE0/RGPIO0/TPM2CLK/SPSCK1
PTC4/RGPIO12/TPM3CH4/RSTO
PTC6/RGPIO14/RxD2/ACMP2+
PTC7/RGPIO15 /TxD2/ACMP2-
PTA5/IRQ/TPM1CLK/RESET
PTA4/ACMP1O/BKGD/MS
PTE1/RGPIO1/MOSI1
PTE2/RGPIO2/MISO1
PTE3/RGPIO3/SS1
PTG4/ADP20
PTG5/ADP21
PTG6/ADP22
PTG7/ADP23
PTG2/ADP18
PTG3/ADP19
PTG0
PTG1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PTD1/KBI2P1/MOSI2 1 60 PTA2/KBI1P2/SDA1/ADP2
PTD0/KBI2P0/SPSCK2 2 59 PTA3/KBI1P3/SCL1/ADP3
PTH7/SDA2 3 58 PTD2/KBI2P2/MISO2
PTH6/SCL2 4 57 PTD3/KBI2P3/SS2
PTH5 5 56 PTD4/KBI2P4
PTH4 6 55 PTJ0
PTE7/RGPIO7/TPM3CLK 7 54 PTJ1
VDD 8 53 PTF0/ADP10
VDDAD 9 52 PTF1/ADP11
VREFH 10 51 VSS
VREFL 11 50 VDD
VSSAD 12 49 PTE4/RGPIO4
VSS 13 48 PTA6/TPM1CH2/ADP8
PTB7/SCL1/EXTAL 14 47 PTA7/TPM2CH2/ADP9
PTB6/SDA1/XTAL 15 46 PTF2/ADP12
PTH3 45
16 PTF3/ADP13
PTH2
17 44 PTJ2
PTH1 43 PTJ3
18
PTH0 PTB0/KBI1P4/RxD1/ADP4
19 42
PTE6/RGPIO6 PTB1/KBI1P5/TxD1/ADP5
20 41
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PTE5/RGPIO5
PTB4/TPM2CH1/MISO1
PTD7/KBI2P7
PTD6/KBI2P6
PTD5/KBI2P5
PTJ7
PTJ6
PTJ5
PTJ4
PTC1/RGPIO9/TPM3CH1
PTC0/RGPIO8/TPM3CH0
PTF7/ADP17
PTF6/ADP16
PTF5/ADP15
PTF4/ADP14
PTB2/KBI1P6/SPSCK1/ADP6
PTB5/TPM1CH1/SS1
PTB3/KBI1P7/MOSI1/ADP7
Pins in bold are added from the next smaller package.

Figure 2. Pin Assignments in 80-Pin LQFP

6
Pin Assignments
PTE6/RGPIO6
PTB6/SDA1/XTAL
PTB7/SCL1/EXTAL
PTH6/SCL2
PTH7/SDA2
VSSAD
VDD
PTH0
PTH1
VREFH
PTE7/RGPIO7/TPM3CLK
VREFL
PTD0/KBI2P0/SPSCK2
VSS
PTD1/KBI2P1/MOSI2
VDDAD
9
8
7
6
5
4
3
2
1
11
16
15
14
13
12
10
PTE5/RGPIO5 17 64 PTA4/ACMP1O/BKGD/MS
PTB5/TPM1CH1/SS1 18 63 PTA5/IRQ/TPM1CLK/RESET
PTB4/TPM2CH1/MISO1 19 62 PTC4/RGPIO12/TPM3CH4/RSTO
PTC3/RGPIO11/TPM3CH3 20 61 PTC5/RGPIO13/TPM3CH5/ACMP2O
PTC2/RGPIO10/TPM3CH2 21 60 PTE0/RGPIO0/TPM2CLK/SPSCK1
PTD7/KBI2P7 22 59 PTE1/RGPIO1/MOSI1
PTD6/KBI2P6 23 58 PTG0
PTD5/KBI2P5 24 57 PTG1
PTC1/RGPIO9/TPM3CH1 25 56 PTG2/ADP18
PTC0/RGPIO8/TPM3CH0 26 55 PTG3/ADP19
PTF7/ADP17 27 54 PTE2/RGPIO2/MISO1
PTF6/ADP16 28 53 PTE3/RGPIO3/SS1
PTF5/ADP15 29 52 PTC6/RGPIO14/RxD2/ACMP2+
PTF4/ADP14 30 51 PTC7/RGPIO15/TxD2/ACMP2-
PTB3/KBI1P7/MOSI1/ADP7 31 50 PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+
PTB2/KBI1P6/SPSCK1/ADP6 49 PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1-
32

33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
VSS
VDD
Figure 3. Pin Assignments in 64-Pin LQFP Package

PTF3/ADP13
PTF2/ADP12
PTF1/ADP11
PTF0/ADP10
PTD4/KBI2P4
PTE4/RGPIO4
PTD3/KBI2P3/SS2
PTD2/KBI2P2/MISO2
PTA7/TPM2CH2/ADP9
PTA6/TPM1CH2/ADP8
PTB1/KBI1P5/TxD1/ADP5
PTB0/KBI1P4/RxD1/ADP4
PTA3/KBI1P3/SCL1/ADP3
PTA2/KBI1P2/SDA11/ADP2
Freescale Semiconductor
Pin Assignments
Table 2. MCF51QE128 Series Pin Assignment by Package and Pin Sharing Priority
Pin
Lowest ←⎯ Priority ⎯→ Highest
Number
80 64 Port Pin Alt 1 Alt 2 Alt 3 Alt 4

1 1 PTD1 KBI2P1 MOSI2
2 2 PTD0 KBI2P0 SPSCK2
3 3 PTH7 SDA2
4 4 PTH6 SCL2
5 — PTH5
6 — PTH4
7 5 PTE7 RGPIO7 TPM3CLK
8 6 VDD
9 7 VDDAD
10 8 VREFH
11 9 VREFL
12 10 VSSAD
13 11 VSS
14 12 PTB7 SCL1 EXTAL
15 13 PTB6 SDA1 XTAL
16 — PTH3
17 — PTH2
18 14 PTH1
19 15 PTH0
20 16 PTE6 RGPIO6
21 17 PTE5 RGPIO5
22 18 PTB5 TPM1CH1 SS1
23 19 PTB4 TPM2CH1 MISO1
24 20 PTC3 RGPIO11 TPM3CH3
26 22 PTD7 KBI2P7
27 23 PTD6 KBI2P6
28 24 PTD5 KBI2P5
29 — PTJ7
30 — PTJ6
31 — PTJ5
32 — PTJ4
35 27 PTF7 ADP17
36 28 PTF6 ADP16
37 29 PTF5 ADP15
38 30 PTF4 ADP14
39 31 PTB3 KBI1P7 MOSI11 ADP7
40 32 PTB2 KBI1P6 SPSCK1 ADP6

Pin Assignments
Table 2. MCF51QE128 Series Pin Assignment by Package and Pin Sharing Priority (continued)
Pin
Lowest ←⎯ Priority ⎯→ Highest
Number
80 64 Port Pin Alt 1 Alt 2 Alt 3 Alt 4

41 33 PTB1 KBI1P5 TxD1 ADP5
42 34 PTB0 KBI1P4 RxD1 ADP4
43 — PTJ3
44 — PTJ2
45 35 PTF3 ADP13
46 36 PTF2 ADP12
47 37 PTA7 TPM2CH2 ADP9
48 38 PTA6 TPM1CH2 ADP8
49 39 PTE4 RGPIO4
50 40 VDD
51 41 VSS
52 42 PTF1 ADP11
53 43 PTF0 ADP10
54 — PTJ1
55 — PTJ0
56 44 PTD4 KBI2P4
57 45 PTD3 KBI2P3 SS2
58 46 PTD2 KBI2P2 MISO2
59 47 PTA3 KBI1P3 SCL12 ADP3
60 48 PTA2 KBI1P2 SDA1 ADP2
61 49 PTA1 KBI1P1 TPM2CH0 ADP1 ACMP1-
62 50 PTA0 KBI1P0 TPM1CH0 ADP0 ACMP1+
63 51 PTC7 RGPIO15 TxD2 ACMP2-
64 52 PTC6 RGPIO14 RxD2 ACMP2+
65 — PTG7 ADP23
66 — PTG6 ADP22
67 — PTG5 ADP21
68 — PTG4 ADP20
69 53 PTE3 RGPIO3 SS1
70 54 PTE2 RGPIO2 MISO1
71 55 PTG3 ADP19
72 56 PTG2 ADP18
73 57 PTG1
74 58 PTG0
75 59 PTE1 RGPIO1 MOSI1
76 60 PTE0 RGPIO0 TPM2CLK SPSCK1
77 61 PTC5 RGPIO13 TPM3CH5 ACMP2O
78 62 PTC4 RGPIO12 TPM3CH4 RSTO
79 63 PTA5 IRQ TPM1CLK RESET
80 64 PTA43 ACMP1O BKGD MS

Electrical Characteristics
1
SPI1 pins (SS1, MISO1, MOSI1, and SPSCK2) can be repositioned using SPI1PS
in SOPT2. Default locations are PTB5, PTB4, PTB3, and PTB2.
2
IIC1 pins (SCL1 and SDA1) can be repositioned using IIC1PS in SOPT2. Default
locations are PTA3 and PTA2, respectively.
3
The PTA4/ACMP1O/BKGD/MS is limited to output only for the port I/O function.
3 Electrical Characteristics
3.1 Introduction
This section contains electrical and timing specifications for the MCF51QE128 series of microcontrollers available at the time
of publication.
3.2 Parameter Classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
Table 3. Parameter Classifications
P Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically relevant sample
C
size across process variations.
Those parameters are achieved by design characterization on a small sample size from typical devices
T under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
D Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
3.3 Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in Table 4 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised
that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for
instance, either VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled.

Table 4. Absolute Maximum Ratings
Rating Symbol Value Unit
Supply voltage VDD –0.3 to +3.8 V

Maximum current into VDD IDD 120 mA
Digital input voltage VIn –0.3 to VDD + 0.3 V
Instantaneous maximum current ID ± 25 mA
Single pin limit (applies to all port pins)1, 2, 3
Storage temperature range Tstg –55 to 150 °C
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2
All functional non-supply pins are internally clamped to VSS and VDD.
3
Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
3.4 Thermal Characteristics

This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and
it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine
the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of
unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.
Table 5. Thermal Characteristics
Rating Symbol Value Unit
Operating temperature range (packaged):

MCF51QE64, MCF51QE96, and –40 to 85
MCF51QE128:
TA °C
MCF51QE32: 0 to 70
Maximum junction temperature TJM 95 °C

Thermal resistance
Single-layer board
64-pin LQFP 69
θJA °C/W
80-pin LQFP 60
Thermal resistance
Four-layer board
64-pin LQFP 50
θJA °C/W
80-pin LQFP 47

The average chip-junction temperature (TJ) in °C can be obtained from:
TJ = TA + (PD × θJA) Eqn. 1
where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected)
is:
PD = K ÷ (TJ + 273°C) Eqn. 2
Solving Equation 1 and Equation 2 for K gives:
K = PD × (TA + 273°C) + θJA × (PD)2 Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively
for any value of TA.
3.5 ESD Protection and Latch-Up Immunity

Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM) and the
charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
Table 6. ESD and Latch-up Test Conditions
Model Description Symbol Value Unit
Series resistance R1 1500 Ω

Human
Storage capacitance C 100 pF
Body
Number of pulses per pin — 3
Series resistance R1 0 Ω
Machine Storage capacitance C 200 pF
Number of pulses per pin — 3
Minimum input voltage limit – 2.5 V
Latch-up
Maximum input voltage limit 7.5 V

Table 7. ESD and Latch-Up Protection Characteristics
No. Rating1 Symbol Min Max Unit
1 Human body model (HBM) VHBM ± 2000 — V

2 Machine model (MM) VMM ± 200 — V
3 Charge device model (CDM) VCDM ± 500 — V
4 Latch-up current at TA = 85°C ILAT ± 100 — mA
1
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
3.6 DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Table 8. DC Characteristics
Num C Characteristic Symbol Condition Min Typ1 Max Unit
1 Operating Voltage 1.82 3.6 V

Output high All I/O pins,
C 1.8 V, ILoad = –2 mA VDD – 0.5 — —
voltage low-drive strength
2 P All I/O pins, VOH 2.7 V, ILoad = –10 mA VDD – 0.5 — — V

high-drive strength
T 2.3 V, ILoad = –6 mA VDD – 0.5 — —
C 1.8V, ILoad = –3 mA VDD – 0.5 — —
Output high Max total IOH for all
3 D IOHT — — 100 mA
current ports
Output low All I/O pins,
C 1.8 V, ILoad = 2 mA — — 0.5
voltage low-drive strength
4 P All I/O pins, VOL 2.7 V, ILoad = 10 mA — — 0.5 V

high-drive strength
T 2.3 V, ILoad = 6 mA — — 0.5
C 1.8 V, ILoad = 3 mA — — 0.5
Output low Max total IOL for all
5 D IOLT — — 100 mA
current ports
P Input high all digital inputs VDD > 2.7 V 0.70 x VDD — —
6 voltage VIH
C VDD > 1.8 V 0.85 x VDD — —
V
P Input low voltage all digital inputs VDD > 2.7 V — — 0.35 x VDD
7 VIL
C VDD >1.8 V — — 0.30 x VDD
8 C Input hysteresis all digital inputs Vhys 0.06 x VDD — — mV
Input leakage all input only pins
9 P |IIn| VIn = VDD or VSS — — 1 μA
current (Per pin)
Hi-Z (off-state) all input/output
10 P |IOZ| VIn = VDD or VSS — — 1 μA
leakage current (per pin)
Pull-up resistors all digital inputs, when
11 P enabled RPU 17.5 — 52.5 kΩ

Table 8. DC Characteristics (continued)
Num C Characteristic Symbol Condition Min Typ1 Max Unit
DC injection Single pin limit –0.2 — 0.2 mA

3, 4, 5
12 D current Total MCU limit, includes IIC VIN < VSS, VIN > VDD
–5 — 5 mA
sum of all stressed pins
13 C Input Capacitance, all pins CIn — — 8 pF
14 C RAM retention voltage VRAM — 0.6 1.0 V
15 C POR re-arm voltage6 VPOR 0.9 1.4 1.79 V
16 D POR re-arm time tPOR 10 — — μs
Low-voltage detection threshold — VDD falling 2.11 2.16 2.22
17 P VLVDH8 V
high range7 VDD rising 2.16 2.21 2.27
Low-voltage detection threshold — VDD falling 1.80 1.82 1.91
18 P VLVDL V
low range7 VDD rising 1.86 1.90 1.99
Low-voltage warning threshold — VDD falling 2.36 2.46 2.56
19 P VLVWH V
high range7 VDD rising 2.36 2.46 2.56
Low-voltage warning threshold — VDD falling 2.11 2.16 2.22
20 P VLVWL V
low range7 VDD rising 2.16 2.21 2.27
Low-voltage inhibit reset/recover
21 C Vhys — 50 — mV
hysteresis7
22 P Bandgap Voltage Reference9 VBG 1.15 1.17 1.18 V
1 Typical values are measured at 25°C. Characterized, not tested
2
As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above VLVDL.
3
All functional non-supply pins are internally clamped to VSS and VDD.
4 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
5 Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result
in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if
clock rate is very low (which would reduce overall power consumption).
6 Maximum is highest voltage that POR is guaranteed.
7
Low voltage detection and warning limits measured at 1 MHz bus frequency.
8
Run at 1 MHz bus frequency
9 Factory trimmed at VDD = 3.0 V, Temp = 25°C

PULL-UP RESISTOR TYPICALS
PULL-DOWN RESISTANCE (kΩ)

40 PULL-DOWN RESISTOR TYPICALS
85°C 40
PULL-UP RESISTOR (kΩ)
25°C 85°C
–40°C 25°C
35 –40°C
35
30
30
25
25
20
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 20
VDD (V) 1.8 2.3 2.8 3.3 3.6
VDD (V)
Figure 4. Pull-up and Pull-down Typical Resistor Values
TYPICAL VOL VS IOL AT VDD = 3.0 V TYPICAL VOL VS VDD

1.2 0.2
85°C
1 25°C
–40°C 0.15
0.8
VOL (V)
VOL (V)
0.6 0.1
0.4
0.05 85°C, IOL = 2 mA
0.2 25°C, IOL = 2 mA
–40°C, IOL = 2 mA
0 0
0 5 10 15 20 1 2 3 4
IOL (mA) VDD (V)
Figure 5. Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0)
TYPICAL VOL VS IOL AT VDD = 3.0 V TYPICAL VOL VS VDD

1 0.4
85°C 85°C
25°C 25°C
0.8 –40°C –40°C
0.3
0.6
VOL (V)
VOL (V)
0.2 IOL = 10 mA
0.4
IOL = 6 mA
0.2 0.1
IOL = 3 mA
0 0
0 10 20 30 1 2 3 4
VDD (V)
IOL (mA)
Figure 6. Typical Low-Side Driver (Sink) Characteristics — High Drive (PTxDSn = 1)

TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V TYPICAL VDD – VOH VS VDD AT SPEC IOH
1.2 0.25
85°C 85°C, IOH = 2 mA
1 25°C 25°C, IOH = 2 mA
VDD – VOH (V)
VDD – VOH (V)

–40°C 0.2 –40°C, IOH = 2 mA
0.8
0.15
0.6
0.1
0.4
0.2 0.05
0 0
0 –5 –10 –15 –20 1 2 3 4
IOH (mA)) VDD (V)
Figure 7. Typical High-Side (Source) Characteristics — Low Drive (PTxDSn = 0)
TYPICAL VDD – VOH VS VDD AT SPEC IOH

0.4
85°C
25°C
TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V 0.3 –40°C
0.8
VDD – VOH (V)

85°C
VDD – VOH (V)
0.6 25°C
–40°C 0.2 IOH = –10 mA
0.4 IOH = –6 mA
0.1
0.2 IOH = –3 mA
0 0
0 –5 –10 –15 –20 –25 –30
1 2 3 4
IOH (mA) VDD (V)
Figure 8. Typical High-Side (Source) Characteristics — High Drive (PTxDSn = 1)
3.7 Supply Current Characteristics

This section includes information about power supply current in various operating modes.
Table 9. Supply Current Characteristics
Bus VDD Temp

Num C Parameter Symbol Typ1 Max Unit
Freq (V) (°C)
P Run supply current 32 35 –40 to 25

FEI mode, all modules on 25.165 MHz
P 32 35 85
1 T RIDD 20 MHz 3 28.0 — mA
T 8 MHz 13.2 — –40 to 85
T 1 MHz 2.4 —
C Run supply current 25.165 MHz 28.1 29.6
FEI mode, all modules off
T 20 MHz 22.9 —
2 RIDD 3 mA –40 to 85
T 8 MHz 11.3 —
T 1 MHz 2.0 —

Table 9. Supply Current Characteristics (continued)
Bus VDD Temp

Num C Parameter Symbol Typ1 Max Unit
Freq (V) (°C)
Run supply current 16 kHz

T 203 —
LPS=0, all modules off FBILP
3 RIDD 3 μA –40 to 85
16 kHz
T 154 —
FBELP
Run supply current
16 kHz
4 T LPS=1, all modules off, running from RIDD 3 50 — μA –40 to 85
FBELP
Flash
C Wait mode supply current 25.165 MHz 11 13.7
FEI mode, all modules off
T 20 MHz 4.57 —
5 WIDD 3 mA –-40 to 85
T 8 MHz 2 —
T 1 MHz 0.73 —
P Stop2 mode supply current 0.6 0.8 -40 to 25
C 3 3.0 11 70
P 8.0 20 85
6 S2IDD n/a μA
C 0.6 0.8 -40 to 25
C 2 2.5 10 70
C 6.0 12 85
P Stop3 mode supply current 0.8 1.3 -40 to 25
No clocks active
C 3 6.0 18 70
P 18.0 28 85
7 S3IDD n/a μA
C 0.8 1.3 -40 to 25
C 2 5.0 16 70
C 12.0 20 85
1 Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
Table 10. Stop Mode Adders
Temperature (°C)
Num C Parameter Condition Units
-40 25 70 85
1 T LPO 50 75 100 150 nA

2 T ERREFSTEN RANGE = HGO = 0 1000 1000 1100 1500 nA
3 T IREFSTEN1 63 70 77 81 uA
4 T RTC does not include clock source current 50 75 100 150 nA
5 T LVD1 LVDSE = 1 90 100 110 115 uA
1
6 T ACMP not using the bandgap (BGBE = 0) 18 20 22 23 uA
1
7 T ADC ADLPC = ADLSMP = 1 not using the 95 106 114 120 uA
bandgap (BGBE = 0)

1
Not available in stop2 mode.
35
30
25
FEI: 24 MHz
20 FBELP: 24 MHz
IDD (mA)
FEI: 8 MHz
FBELP: 8 MHz
15 FEI: 1 MHz
FBELP: 1 MHz
10
0
1.8 2 2.2 2.4 2.6 2.8 3
VDD (V)
Figure 9. Typical Run IDD for FBE and FEI, IDD vs. VDD
(ADC off, All Other Modules Enabled)

3.8 External Oscillator (XOSC) Characteristics

Reference Figure 10 and Figure 11 for crystal or resonator circuits.
Table 11. XOSC and ICS Specifications (Temperature Range = –40 to 85°C Ambient)
Num C Characteristic Symbol Min Typ1 Max Unit
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)

Low range (RANGE = 0) flo 32 — 38.4 kHz
1 C
High range (RANGE = 1), high gain (HGO = 1) fhi 1 — 16 MHz
High range (RANGE = 1), low power (HGO = 0) fhi 1 — 8 MHz
Load capacitors
See Note2
2 D Low range (RANGE=0), low power (HGO=0) C1,C2
Other oscillator settings See Note3
Feedback resistor
Low range, low power (RANGE=0, HGO=0)2 — — —
3 D RF MΩ
Low range, High Gain (RANGE=0, HGO=1) — 10 —
High range (RANGE=1, HGO=X) — 1 —
Series resistor —
Low range, low power (RANGE = 0, HGO = 0)2 — — —
Low range, high gain (RANGE = 0, HGO = 1) — 0 —
High range, low power (RANGE = 1, HGO = 0) — 100 —
4 D RS kΩ
High range, high gain (RANGE = 1, HGO = 1)
≥ 8 MHz — 0 0
4 MHz — 0 10
1 MHz — 0 20
Crystal start-up time 4
t
Low range, low power CSTL — 200 —
5 C Low range, high power — 400 —
t ms
High range, low power CSTH — 5 —
High range, high power — 15 —
Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)
6 D FEE or FBE mode fextal 0.03125 — 40.0 MHz
FBELP mode 0 — 50.33 MHz
1
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
2 Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE=HGO=0.
3
See crystal or resonator manufacturer’s recommendation.
4 Proper PC board layout procedures must be followed to achieve specifications.

XOSC
EXTAL XTAL
RS
RF
Crystal or Resonator
C1
C2
Figure 10. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain
XOSC
EXTAL XTAL
Crystal or Resonator
Figure 11. Typical Crystal or Resonator Circuit: Low Range/Low Gain
3.9 Internal Clock Source (ICS) Characteristics

Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient)
Average internal reference frequency — factory trimmed

1 P fint_ft — 32.768 — kHz
at VDD = 3.6 V and temperature = 25°C
2 P Internal reference frequency — user trimmed fint_ut 31.25 — 39.06 kHz
3 T Internal reference start-up time tIRST — 60 100 μs

P Low range (DRS=00) 16 — 20
DCO output frequency range —
4 P Mid range (DRS=01) fdco_u 32 — 40 MHz
trimmed 2
P High range (DRS=10) 48 — 60
P DCO output frequency 2 Low range (DRS=00) — 19.92 —
5 P Reference = 32768 Hz Mid range (DRS=01) fdco_DMX32 — 39.85 — MHz
and
P DMX32 = 1 High range (DRS=10) — 59.77 —
Resolution of trimmed DCO output frequency at fixed voltage and
6 C Δfdco_res_t — ± 0.1 ± 0.2 %fdco
temperature (using FTRIM)
Resolution of trimmed DCO output frequency at fixed voltage and
7 C Δfdco_res_t — ± 0.2 ± 0.4 %fdco
temperature (not using FTRIM)

Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient) (continued)
Total deviation of trimmed DCO output frequency over voltage + 0.5

8 C Δfdco_t — ±2 %fdco
and temperature -1.0
Total deviation of trimmed DCO output frequency over fixed
9 C Δfdco_t — ± 0.5 ±1 %fdco
voltage and temperature range of 0°C to 70 °C
10 C FLL acquisition time 3 tAcquire — — 1 ms
Long term jitter of DCO output clock (averaged over 2-ms

11 C CJitter — 0.02 0.2 %fdco
interval) 4
1
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
2
The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.
3
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Bus.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a
given interval.
0.60%
0.40%
0.20%
0.00%
-40 -20 0 20 40 60 80 100 120
% deviation
-0.20%
-0.40%
-0.60%
-0.80%
-1.00%
VDD
Figure 12. Deviation of DCO Output Across Temperature at VDD = 3.0 V

0.50%
0.40%
0.30%
0.20%
0.10%
% deviation
0.00%
2.1V 2.4V 2.7V 3.0V 3.3V 3.6V
-0.10%
-0.20%
-0.30%
-0.40%
-0.50%
VDD
Figure 13. Deviation of DCO Output Across VDD at 25°C
3.10 AC Characteristics
This section describes timing characteristics for each peripheral system.
3.10.1 Control Timing

Table 13. Control Timing
Num C Rating Symbol Min Typ1 Max Unit
Bus frequency (tcyc = 1/fBus)

VDD ≥ 1.8V — 10
1 D fBus dc MHz
VDD > 2.1V — 20
VDD > 2.4V — 25.165
2 D Internal low power oscillator period tLPO 700 — 1300 μs
3 D External reset pulse width2 textrst 100 — — ns
4 D Reset low drive trstdrv 34 x tcyc — — ns
BKGD/MS setup time after issuing background debug
5 D tMSSU 500 — — ns
force reset to enter user or BDM modes
BKGD/MS hold time after issuing background debug
6 D tMSH 100 — — μs
force reset to enter user or BDM modes 3

Table 13. Control Timing (continued)
Num C Rating Symbol Min Typ1 Max Unit
IRQ pulse width

7 D Asynchronous path2 tILIH, tIHIL 100 — —
ns
Synchronous path4 2 x tcyc — —
Keyboard interrupt pulse width
8 D Asynchronous path2 tILIH, tIHIL 100 — —
ns
Synchronous path4 2 x tcyc — —
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)5
tRise, tFall ns
Slew rate control disabled (PTxSE = 0) — 8 —
Slew rate control enabled (PTxSE = 1) — 31 —
9 C
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
tRise, tFall ns
Slew rate control disabled (PTxSE = 0) — 7 —
Slew rate control enabled (PTxSE = 1) — 24 —
10 Voltage regulator recovery time tVRR — 4 — μs
1 Typical values are based on characterization data at VDD = 3.0V, 25°C unless otherwise stated.
2
This is the shortest pulse that is guaranteed to be recognized as a reset or interrupt pin request. Shorter pulses are not
guaranteed to override reset requests from internal sources.
3 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t
MSH after VDD
rises above VLVD.
4 This is the minimum assertion time in which the interrupt may be recognized. The correct protocol is to assert the interrupt
request until it is explicitly negated by the interrupt service routine.

5 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40°C to 85°C.
textrst
RESET PIN
Figure 14. Reset Timing
tIHIL
KBIPx
IRQ/KBIPx
tILIH
Figure 15. IRQ/KBIPx Timing

3.10.2 TPM Module Timing

Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the
optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table 14. TPM Input Timing
No. C Function Symbol Min Max Unit
1 D External clock frequency fTCLK 0 fBus/4 Hz

2 D External clock period tTCLK 4 — tcyc
3 D External clock high time tclkh 1.5 — tcyc
4 D External clock low time tclkl 1.5 — tcyc
5 D Input capture pulse width tICPW 1.5 — tcyc
tTCLK
tclkh
TCLK
tclkl
Figure 16. Timer External Clock
tICPW
TPMCHn
TPMCHn
tICPW
Figure 17. Timer Input Capture Pulse

3.10.3 SPI Timing

Table 15 and Figure 18 through Figure 21 describe the timing requirements for the SPI system.
Table 15. SPI Timing
No. C Function Symbol Min Max Unit
Operating frequency fop

— D Master fBus/2048 fBus/2 Hz
Slave 0 fBus/4 Hz
SPSCK period tSPSCK
1 D Master 2 2048 tcyc
Slave 4 — tcyc
Enable lead time tLead
2 D Master 1/2 — tSPSCK
Slave 1 — tcyc
Enable lag time tLag
3 D Master 1/2 — tSPSCK
Slave 1 — tcyc
Clock (SPSCK) high or low time tWSPSCK
4 D Master tcyc – 30 1024 tcyc ns
Slave tcyc – 30 — ns
Data setup time (inputs) tSU
5 D Master 15 — ns
Slave 15 — ns
Data hold time (inputs) tHI
6 D Master 0 — ns
Slave 25 — ns
7 D Slave access time ta — 1 tcyc
8 D Slave MISO disable time tdis — 1 tcyc
Data valid (after SPSCK edge) tv
9 D Master — 25 ns
Slave — 25 ns
Data hold time (outputs) tHO
10 D Master 0 — ns
Slave 0 — ns
Rise time
11 D Input tRI — tcyc – 25 ns
Output tRO — 25 ns
Fall time
12 D Input tFI — tcyc – 25 ns
Output tFO — 25 ns

SS1
(OUTPUT)
2 1 11 3
SPSCK 4
(CPOL = 0)
(OUTPUT) 4
12
SPSCK
(CPOL = 1)
(OUTPUT)
5 6
MISO
(INPUT) MSB IN2 BIT 6 . . . 1 LSB IN
9 9 10
MOSI
(OUTPUT) MSB OUT2 BIT 6 . . . 1 LSB OUT
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 18. SPI Master Timing (CPHA = 0)
SS(1)
(OUTPUT)
1
2 12 11 3
SPSCK
(CPOL = 0)
(OUTPUT)
4 4 11 12
SPSCK
(CPOL = 1)
(OUTPUT)
5 6
MISO
(INPUT) MSB IN(2) BIT 6 . . . 1 LSB IN
9 10
MOSI
(OUTPUT) PORT DATA MASTER MSB OUT(2) BIT 6 . . . 1 MASTER LSB OUT PORT DATA
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 19. SPI Master Timing (CPHA =1)

SS
(INPUT)
1 12 11 3
SPSCK
(CPOL = 0)
(INPUT)
2 4 4 11 12
SPSCK
(CPOL = 1)
(INPUT) 8
7 9 10 10
MISO SEE
(OUTPUT) SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT NOTE
5 6
MOSI
(INPUT) MSB IN BIT 6 . . . 1 LSB IN
NOTE:
1. Not defined but normally MSB of character just received

Figure 20. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
1 3
2 12 11
SPSCK
(CPOL = 0)
(INPUT)
4 4 11 12
SPSCK
(CPOL = 1)
(INPUT)
9 10 8
MISO SEE
(OUTPUT) NOTE SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT
7 5 6
MOSI
(INPUT) MSB IN BIT 6 . . . 1 LSB IN
NOTE:
1. Not defined but normally LSB of character just received
Figure 21. SPI Slave Timing (CPHA = 1)

3.11 Analog Comparator (ACMP) Electricals

Table 16. Analog Comparator Electrical Specifications
C Characteristic Symbol Min Typical Max Unit
D Supply voltage VDD 1.80 — 3.6 V
C Supply current (active) IDDAC — 20 35 μA
D Analog input voltage VAIN VSS – 0.3 — VDD V

C Analog input offset voltage VAIO 20 40 mV
C Analog comparator hysteresis VH 3.0 9.0 15.0 mV
P Analog input leakage current IALKG — — 1.0 μA

C Analog comparator initialization delay tAINIT — — 1.0 μs
3.12 ADC Characteristics

Table 17. 12-bit ADC Operating Conditions
C Characteristic Conditions Symb Min Typ1 Max Unit Comment
Supply voltage Absolute VDDAD 1.8 — 3.6 V

D
Delta to VDD (VDD-VDDAD)2 ΔVDDAD -100 0 +100 mV
D Ground voltage Delta to VSS (VSS-VSSAD)2 ΔVSSAD -100 0 +100 mV
D Ref Voltage High VREFH 1.8 VDDAD VDDAD V
D Ref Voltage Low VREFL VSSAD VSSAD VSSAD V
D Input Voltage VADIN VREFL — VREFH V
Input CADIN — 4.5 5.5
C pF
Capacitance
C Input Resistance RADIN — 5 7 kΩ
Analog Source 12 bit mode RAS External to MCU
Resistance fADCK > 4MHz — — 2
fADCK < 4MHz — — 5
C 10 bit mode kΩ
fADCK > 4MHz — — 5
fADCK < 4MHz — — 10
8 bit mode (all valid fADCK) — — 10
ADC Conversion High Speed (ADLPC=0) fADCK 0.4 — 8.0
D Clock Freq. MHz
Low Power (ADLPC=1) 0.4 — 4.0
1
Typical values assume VDDAD = 3.0V, Temp = 25°C, fADCK=1.0MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2 DC potential difference.

SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT ZADIN
SIMPLIFIED
Pad
ZAS leakage CHANNEL SELECT
due to CIRCUIT
ADC SAR
input ENGINE
RAS RADIN
protection
+
VADIN
–
CAS
VAS +
–
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN CADIN
Figure 22. ADC Input Impedance Equivalency Diagram
Table 18. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)
Characteristic Conditions C Symb Min Typ1 Max Unit Comment
Supply Current T IDDAD — 120 —

ADLPC=1
μA
ADLSMP=1
ADCO=1
ADLPC=1
μA
ADLSMP=0
ADCO=1
ADLPC=0
μA
ADLSMP=1
ADCO=1
Supply Current D IDDAD — 0.532 1
ADLPC=0
mA
ADLSMP=0
ADCO=1
Supply Current Stop, Reset, Module Off T IDDAD — 0.007 0.8 μA
ADC High Speed (ADLPC=0) P fADACK 2 3.3 5 tADACK = 1/fADACK
Asynchronous MHz
Low Power (ADLPC=1) P 1.25 2 3.3
Clock Source

Table 18. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued)
Characteristic Conditions C Symb Min Typ1 Max Unit Comment
Conversion Time Short Sample (ADLSMP=0) P tADC — 20 — ADCK See the ADC
(Including cycles chapter in the
Long Sample (ADLSMP=1) C — 40 —
sample time) MCF51QE128
Reference Manual
Sample Time Short Sample (ADLSMP=0) P tADS — 3.5 — ADCK
for conversion time
cycles
Long Sample (ADLSMP=1) C — 23.5 — variances
Total Unadjusted 12 bit mode T ETUE — ±3.0 — LSB2 Includes

Error Quantization
10 bit mode P — ±1 ±2.5
8 bit mode T — ±0.5 ±1.0
Differential 12 bit mode T DNL — ±1.75 — LSB2
Non-Linearity
10 bit mode3 P — ±0.5 ±1.0
8 bit mode3 T — ±0.3 ±0.5
Integral 12 bit mode T INL — ±1.5 — LSB2
Non-Linearity
10 bit mode T — ±0.5 ±1.0
8 bit mode T — ±0.3 ±0.5
Zero-Scale Error 12 bit mode T EZS — ±1.5 — LSB2 VADIN = VSSAD
10 bit mode P — ±0.5 ±1.5
8 bit mode T — ±0.5 ±0.5
Full-Scale Error 12 bit mode T EFS — ±1.0 — LSB2 VADIN = VDDAD
10 bit mode P — ±0.5 ±1
8 bit mode T — ±0.5 ±0.5
Quantization 12 bit mode D EQ — -1 to 0 — LSB2
Error
10 bit mode — — ±0.5
8 bit mode — — ±0.5
Input Leakage 12 bit mode D EIL — ±2 — LSB2 Pad leakage4 * RAS
Error
10 bit mode — ±0.2 ±4
8 bit mode — ±0.1 ±1.2
Temp Sensor -40°C to 25°C D m — 1.646 — mV/°C
Slope
25°C to 85°C — 1.769 —
Temp Sensor 25°C D VTEMP25 — 701.2 — mV
Voltage
1 Typical values assume VDDAD = 3.0V, Temp = 25°C, fADCK=1.0MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2 1 LSB = (V N
REFH - VREFL)/2
3
Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes
4 Based on input pad leakage current. Refer to pad electricals.

3.13 Flash Specifications

This section provides details about program/erase times and program-erase endurance for the flash memory.
Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed
information about program/erase operations, see the Memory section of the MCF51QE128 Reference Manual.
Table 19. Flash Characteristics
C Characteristic Symbol Min Typical Max Unit
Supply voltage for program/erase

D
-40°C to 85°C Vprog/erase 1.8 3.6 V
D Supply voltage for read operation VRead 1.8 3.6 V
D Internal FCLK frequency1 fFCLK 150 200 kHz
D Internal FCLK period (1/FCLK) tFcyc 5 6.67 μs
P Longword program time (random location)(2) tprog 9 tFcyc
P Longword program time (burst mode)(2) tBurst 4 tFcyc
P Page erase time2 tPage 4000 tFcyc
P Mass erase time(2) tMass 20,000 tFcyc
Longword program current3 RIDDBP — 9.7 — mA
3
Page erase current RIDDPE — 7.6 — mA
Program/erase endurance4
C TL to TH = –40°C to + 85°C 10,000 — — cycles
T = 25°C — 100,000 —
C Data retention5 tD_ret 15 100 — years
1
The frequency of this clock is controlled by a software setting.
2
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied
for calculating approximate time to program and erase.
3
The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures
with VDD = 3.0 V, bus frequency = 4.0 MHz.
4 Typical endurance for flash was evaluated for this product family on the HC9S12Dx64. For additional information on
how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile
Memory.
5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and
de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention,
please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.

Ordering Information
4 Ordering Information
This section contains ordering information for MCF51QE128MCF51QE96, and MCF51QE64 devices.
Table 20. Ordering Information
Memory
Freescale Part Number1 Temperature range (°C) Package2
Flash RAM
MCF51QE128CLK 128K 8K -40 to +85 80 LQFP
MCF51QE128CLH 128K 8K -40 to +85 64 LQFP
MCF51QE96CLK -40 to +85 80 LQFP
96K 8K
MCF51QE96CLH -40 to +85 64 LQFP
MCF51QE32LH 32K 8K 0 to +70 64 LQFP
1
See the reference manual, MCF51QE128RM, for a complete description of modules included on each device.
2
See Table 21 for package information.
5 Package Information
The below table details the various packages available.
Table 21. Package Descriptions
Pin Count Package Type Abbreviation Designator Case No. Document No.
80 Low Quad Flat Package LQFP LK 917A 98ASS23237W
64 Low Quad Flat Package LQFP LH 840F 98ASS23234W
5.1 Mechanical Drawings

The following pages are mechanical drawings for the packages described in Table 21. For the latest available drawings please
visit our web site (http://www.freescale.com) and enter the package’s document number into the keyword search box.

Package Information
–X–
4X 4X 20 TIPS
X= L, M, N
0.20 (0.008) H L–M N 0.20 (0.008) T L–M N
P
80 61 CL
1 60
AB
AB G
–M–
VIEW Y
B V
PLATING
–L– 3X VIEW Y F BASE
ÇÇÇ
ÍÍÍÍ
V1 J METAL
B1
20
21
–N–
40
41
ÍÍÍÍ
ÇÇÇ D U
A1 0.13 (0.005) M T L–M S N S
S1 SECTION AB–AB
ROTATED 90 CLOCKWISE
A
S NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
C WHERE THE LEAD EXITS THE PLASTIC BODY AT
8X 2 THE BOTTOM OF THE PARTING LINE.
0.10 (0.004) T 4. DATUMS –L–, –M– AND –N– TO BE DETERMINED
–H– AT DATUM PLANE –H–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
–T– SEATING PLANE –T–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
SEATING PROTRUSION. ALLOWABLE PROTRUSION IS
PLANE 0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
VIEW AA DETERMINED AT DATUM PLANE –H–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE LEAD WIDTH TO EXCEED 0.460
(W) (0.018). MINIMUM SPACE BETWEEN
C2 PROTRUSION AND ADJACENT LEAD OR
PROTRUSION 0.07 (0.003).
0.05 (0.002) S
MILLIMETERS INCHES
1 DIM MIN MAX MIN MAX
A 14.00 BSC 0.551 BSC
2X R R1 0.25 (0.010) A1 7.00 BSC 0.276 BSC
B 14.00 BSC 0.551 BSC
GAGE B1 7.00 BSC 0.276 BSC
PLANE C ––– 1.60 ––– 0.063
C1 0.04 0.24 0.002 0.009
(K) C2 1.30 1.50 0.051 0.059
C1 D 0.22 0.38 0.009 0.015
E E 0.40 0.75 0.016 0.030
(Z) F 0.17 0.33 0.007 0.013
G 0.65 BSC 0.026 BSC
VIEW AA J 0.09 0.27 0.004 0.011
K 0.50 REF 0.020 REF
P 0.325 BSC 0.013 REF
R1 0.10 0.20 0.004 0.008
S 16.00 BSC 0.630 BSC
S1 8.00 BSC 0.315 BSC
U 0.09 0.16 0.004 0.006
V 16.00 BSC 0.630 BSC
V1 8.00 BSC 0.315 BSC
W 0.20 REF 0.008 REF
Z 1.00 REF 0.039 REF
DATE 09/21/95 CASE 917A-02 0 0 10 0 10
01 0 ––– 0 –––
ISSUE C 02 9 14 9 14
Figure 23. 80-pin LQFP Package Drawing (Case 917A, Doc #98ASS23237W)

Package Information
Figure 24. 64-pin LQFP Package Drawing (Case 840F, Doc #98ASS23234W), Sheet 1 of 3

Package Information

Package Information

Product Documentation
6 Product Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual (MCF51QE128RM)

Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
7 Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web are the most current. Your
printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://www.freescale.com
The following revision history table summarizes changes contained in this document.
Table 22. Revision History
Revision Date Description of Changes
Table 8: Changed Condition entires in specs #6 (VIH) and #7 (VIL) from VDD ≥ 1.8V to
VDD > 2.7V and VDD ≤ 1.8V to VDD > 1.8V.
3 25 Jun 2007 Table 8: Changed VDD rising and VDD falling min/typ/max specs in row #19 (Low-voltage
warning threshold—high range) from 2.35, 2.40, and 2.50 to 2.36, 2.46, and 2.56
respectively.
Added information about the MCF51QE32 device.
Changed the SRAM size for the MCF51QE64 device (was 4 Kbytes, is 8 Kbytes).
4 17 Sep 2007 Corrected the number of ADC channels for the MCF51QE64 device (was 22, is 20).
Corrected the number of ADC channels for the 64-pin package of the MCF51QE64 device (was
22, is 20).
Changed ACMP electricals, VAIO specification’s test category from P to C.
Updated the tables Thermal Characteristics, DC Characteristics, Supply Current
Characteristics, XOSC and ICS Specifications (Temperature Range = –40 to 85°C
Ambient), ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient),
Control Timing, and Analog Comparator Electrical Specifications, 12-bit ADC
5 28 May 2008
Characteristics (VREFH = VDDAD, VREFL = VSSAD)
Updated the figures Typical Run IDD for FBE and FEI, IDD vs. VDD (ACMP and ADC off,
All Other Modules Enabled), Deviation of DCO Output from Trimmed Frequency (50.33
MHz, 3.0 V), and Deviation of DCO Output from Trimmed Frequency (50.33 MHz, 25°C)
Updated the table Thermal Characteristics
Updated the row corresponding to Num 18 in the table DC Characteristics
Updated the tables MCF51QE128 Series Features by MCU and Package, DC
Characteristics, Supply Current Characteristics, Thermal Characteristics, Control
6 24 Jun 2008
Timing, and Ordering Information
Updated the figures Typical Run IDD for FBE and FEI, IDD vs. VDD
(ADC off, All Other Modules Enabled), Deviation of DCO Output Across Temperature at
VDD = 3.0 V, and Deviation of DCO Output Across VDD at 25×C
Updated the Stop2 and Stop3 mode supply current in the Supply Current Characteristics table.
7 14 Oct 2008 Replaced the stop mode adders section from the Supply Current Characteristics with its own
Stop Mode Adders table with new specifications.

Revision History

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Document Number: MCF51QE128

Rev. 7
10/2008
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Click to View Pricing, Inventory, Delivery & Lifecycle Information:
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Freescale Semiconductor Document Number: MCF51QE128

Data Sheet: Technical Data Rev. 7, 10/2008

MCF51QE128 Series MCF51QE128

MCF51QE128 Series Data Sheet, Rev. 7

MODULE (TPM1) PTA4/ACMP1O/BKGD/MS

PTJ0 ANALOG-TO-DIGITAL PTF4/ADP14

MCF51QE128 Series Data Sheet, Rev. 7

1 MCF51QE128 Series Comparison

Feature MCF51QE128 MCF51QE96 MCF51QE64 MCF51QE32

Flash size (bytes) 131072 98304 65536 32768

RAM size (bytes) 8192 8192 8192 8192

Version 1 ColdFire core yes

Rapid GPIO yes

External IRQ yes

MCF51QE128 Series Data Sheet, Rev. 7

Pins in bold are added from the next smaller package.

MCF51QE128 Series Data Sheet, Rev. 7

MCF51QE128 Series Data Sheet, Rev. 7

Figure 3. Pin Assignments in 64-Pin LQFP Package

80 64 Port Pin Alt 1 Alt 2 Alt 3 Alt 4

MCF51QE128 Series Data Sheet, Rev. 7

80 64 Port Pin Alt 1 Alt 2 Alt 3 Alt 4

MCF51QE128 Series Data Sheet, Rev. 7

3.2 Parameter Classification

3.3 Absolute Maximum Ratings

MCF51QE128 Series Data Sheet, Rev. 7

Table 4. Absolute Maximum Ratings

Rating Symbol Value Unit

Supply voltage VDD –0.3 to +3.8 V

3.4 Thermal Characteristics

Rating Symbol Value Unit

Operating temperature range (packaged):

Maximum junction temperature TJM 95 °C

MCF51QE128 Series Data Sheet, Rev. 7

The average chip-junction temperature (TJ) in °C can be obtained from:

TJ = TA + (PD × θJA) Eqn. 1

PD = K ÷ (TJ + 273°C) Eqn. 2

Solving Equation 1 and Equation 2 for K gives:

K = PD × (TA + 273°C) + θJA × (PD)2 Eqn. 3

3.5 ESD Protection and Latch-Up Immunity

Model Description Symbol Value Unit

Series resistance R1 1500 Ω

MCF51QE128 Series Data Sheet, Rev. 7

Table 7. ESD and Latch-Up Protection Characteristics

No. Rating1 Symbol Min Max Unit

1 Human body model (HBM) VHBM ± 2000 — V

Num C Characteristic Symbol Condition Min Typ1 Max Unit

1 Operating Voltage 1.82 3.6 V

2 P All I/O pins, VOH 2.7 V, ILoad = –10 mA VDD – 0.5 — — V

4 P All I/O pins, VOL 2.7 V, ILoad = 10 mA — — 0.5 V

MCF51QE128 Series Data Sheet, Rev. 7

Table 8. DC Characteristics (continued)

Num C Characteristic Symbol Condition Min Typ1 Max Unit

DC injection Single pin limit –0.2 — 0.2 mA

MCF51QE128 Series Data Sheet, Rev. 7

PULL-UP RESISTOR TYPICALS

PULL-DOWN RESISTANCE (kΩ)

Figure 4. Pull-up and Pull-down Typical Resistor Values

TYPICAL VOL VS IOL AT VDD = 3.0 V TYPICAL VOL VS VDD