MC9S08SE8

Freescale Semiconductor Document Number: MC9S08SE8
Data Sheet: Technical Data Rev. 4, 4/2015
MC9S08SE8
28-Pin SOIC 16-Pin TSSOP
TBD Case 751F Case 948F-01
MC9S08SE8 Series 28-Pin PDIP

Case 710-02
Covers: MC9S08SE8
MC9S08SE4
Features: – SCI — Full duplex non-return to zero (NRZ); LIN
• 8-Bit HCS08 Central Processor Unit (CPU) master extended break generation; LIN slave extended
– 20 MHz HCS08 CPU (central processor unit) break detection; wakeup on active edge
– 10 MHz internal bus frequency – ADC — 10-channel, 10-bit resolution; 2.5 μs
– HC08 instruction set with added BGND conversion time; automatic compare function;
– Support for up to 32 interrupt/reset sources 1.7 mV/°C temperature sensor; internal bandgap
• On-Chip Memory reference channel; runs in stop3
– Up to 8 KB of on-chip in-circuit programmable flash – TPMx — One 2-channel (TPM1) and one 1-channel
memory with block protection and security options (TPM2) 16-bit timer/pulse-width modulator (TPM)
– Up to 512 bytes of on-chip RAM modules; selectable input capture, output compare, and
• Power-Saving Modes edge-aligned PWM capability on each channel; timer
– Wait plus two stops module may be configured for buffered, centered PWM
• Clock Source Options (CPWM) on all channels
– Oscillator (XOSC) — Loop-control Pierce oscillator; – KBI — 8-pin keyboard interrupt module
crystal or ceramic resonator range of 31.25 kHz to – RTC — Real-time counter with binary- or
38.4 kHz or 1 MHz to 16 MHz decimal-based prescaler
– Internal Clock Source (ICS) — Internal clock source • Input/Output
module containing a frequency-locked-loop (FLL) – Software selectable pullups on ports when used as inputs
controlled by internal or external reference; precision – Software selectable slew rate control on ports when used
trimming of internal reference allows 0.2% resolution as outputs
and 2% deviation over temperature and voltage; – Software selectable drive strength on ports when used as
supports bus frequencies from 1 MHz to 10 MHz. outputs
• System Protection – Master reset pin and power-on reset (POR)
– Optional computer operating properly (COP) reset with – Internal pullup on RESET, IRQ, and BKGD/MS pins to
option to run from independent 1 kHz internal clock reduce customer system cost
source or the bus clock • Package Options
– Low voltage detection – 28-pin PDIP
– Illegal opcode detection with reset – 28-pin SOIC
– Illegal address detection with reset – 16-pin TSSOP
• Development Support
– Single-wire background debug interface
– Breakpoint capability to allow single breakpoint setting
during in-circuit debugging
• Peripherals
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2008-2009, 2015. All rights reserved.
Table of Contents
1 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 3.8 Internal Clock Source (ICS) Characteristics . . . . . . . . 20
2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3.9 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . .6 3.10.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . .6 3.10.2 TPM/MTIM Module Timing . . . . . . . . . . . . . . . . 26
3.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .7 3.11 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4 ESD Protection and Latch-Up Immunity . . . . . . . . . . . . .8 4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4.1 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .15 4.2 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.7 External Oscillator (XOSC) Characteristics . . . . . . . . .19
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to: freescale.com
The following revision history table summarizes changes contained in this document.
Revision Date Description of Changes

1 10/8/2008 Initial public released.
2 1/16/2009 In Table 8, added the Max. of S2IDD and S3IDD in 0–105 °C; changed the Max. of S2IDD and
S3IDD in 0–85 °C; changed the typical of S2IDD and S3IDD; changed the S23IDDRTI to P.
3 4/7/2009 Added |IOZTOT| in the Table 7.
Changed VDDAD to VDDA, VSSAD to VSSA.
Updated Table 9, Table 10, Table 11, and Table 12.
Updated Figure 13 and Figure 14.
4 4/10/2015 Updated Table 9.
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual (MC9S08SE8RM)

Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
MC9S08SE8 Series MCU Data Sheet, Rev. 4

2 Freescale Semiconductor
MCU Block Diagram
1 MCU Block Diagram

The block diagram, Figure 1, shows the structure of the MC9S08SE8 series MCUs.
HCS08 CORE
BKGD/MS
DEBUG MODULE (DBG)
CPU BDC
HCS08 SYSTEM CONTROL

REAL-TIME COUNTER (RTC)
RESETS AND INTERRUPTS
MODES OF OPERATION
IRQ POWER MANAGEMENT PTA7/TPM1CH1/ADP5
PTA6/TPM1CH0/ADP4
COP IRQ LVD KBIP7–KBIP0 PTA5/IRQ/TCLK/RESET
KEYBOARD INTERRUPT
PORT A
PTA4/BKGD/MS
MODULE (KBI)
PTA3/KBIP3/ADP3
USER FLASH TCLK PTA2/KBIP2/ADP2
(MC9S08SE8 = 8192 BYTES) 2-CHANNEL TIMER/PWM
MODULE (TPM1) TPM1CH1–TPM1CH0 PTA1/KBIP1/TPM1CH1/ADP1
(MC9S08SE4 = 4096 BYTES)
PTA0/KBIP0/TPM1CH0/ADP0
USER RAM RxD PTB7/EXTAL

SERIAL COMMUNICATIONS
(MC9S08SE8 = 512 BYTES) TxD PTB6/XTAL
(MC9S08SE4 = 256 BYTES) INTERFACE MODULE (SCI)
PTB5
TCLK
PORT B
PTB4/TPM2CH0
1-CHANNEL TIMER/PWM
20 MHz INTERNAL CLOCK MODULE (TPM2) TPM2CH0 PTB3/KBIP7/ADP9
SOURCE (ICS) PTB2/KBIP6/ADP8
EXTAL
PTB1/KBIP5/TxD/ADP7
LOW-POWER OSCILLATOR
31.25 kHz to 38.4 kHz XTAL PTB0/KBIP4/RxD/ADP6
1 MHz to 16 MHz
(XOSC)
PTC7
VSS
PTC6
VOLTAGE REGULATOR
VDD PTC5
PORT C
PTC4
VSSA/VREFL VSSA 10-CHANNEL, 10-BIT PTC3
ADP9–ADP0
VDDA/VREFH VDDA ANALOG-TO-DIGITAL PTC2
VREFL CONVERTER (ADC)
PTC1
VREFH
PTC0
pins not available on 16-pin package
Notes:
When PTA4 is configured as BKGD, pin is bi-directional.
For the 16-pin package: VSSA/VREFL and VDDA/VREFH are double bonded to VSS and VDD respectively.
Figure 1. MC9S08SE8 Series Block Diagram

Freescale Semiconductor 3
Pin Assignments
2 Pin Assignments
This chapter shows the pin assignments in the packages available for the MC9S08SE8 series.
Table 1. Pin Availability by Package Pin-Count
Pin Number
<-- Lowest Priority --> Highest
(Package)
28 16
Port Pin Alt 1 Alt 2 Alt 3
(SOIC/PDIP) (TSSOP)
1 — PTC5
2 — PTC4
3 1 PTA5 IRQ TCLK RESET
4 2 PTA4 BKGD MS
5 3 VDD
6 — VDDA VREFH
7 — VSSA VREFL
8 4 VSS
9 5 PTB7 EXTAL
10 6 PTB6 XTAL
11 7 PTB5
12 8 PTB4 TPM2CH0
13 — PTC3
14 — PTC2
15 — PTC1
16 — PTC0
17 9 PTB3 KBIP7 ADP9
18 10 PTB2 KBIP6 ADP8
19 11 PTB1 KBIP5 TxD ADP7
20 12 PTB0 KBIP4 RxD ADP6
1
21 — PTA7 TPM1CH1 ADP5
22 — PTA6 TPM1CH01 ADP4
23 13 PTA3 KBIP3 ADP3
24 14 PTA2 KBIP2 ADP2
1
25 15 PTA1 KBIP1 TPM1CH1 ADP1
26 16 PTA0 KBIP0 TPM1CH01 ADP0
27 — PTC7
28 — PTC6
1 TPM1 pins can be remapped to PTA7, PTA6 and PTA1,PTA0

Pin Assignments
PTC5 1 28 PTC6
PTC4 2 27 PTC7
PTA5/IRQ/TCLK/RESET 3 26 PTA0/KBIP0/TPM1CH0/ADP0
PTA4/BKGD/MS 4 25 PTA1/KBIP1/TPM1CH1/ADP1
VDD 5 24 PTA2/KBIP2/ADP2
VDDA/VREFH 6 23 PTA3/KBIP3/ADP3
VSSA/VREFL 7 22 PTA6/TPM1CH0/ADP4
VSS 8 21 PTA7/TPM1CH1/ADP5
PTB7/EXTAL 9 20 PTB0/KBIP4/RxD/ADP6
PTB6/XTAL 10 19 PTB1/KBIP5/TxD/ADP7
PTB5 11 18 PTB2/KBIP6/ADP8
PTB4/TPM2CH0 12 17 PTB3/KBIP7/ADP9
PTC3 13 16 PTC0
PTC2 14 15 PTC1
Pins in bold are lost in the next lower pin count package.
Figure 2. MC9S08SE8 Series in 28-Pin PDIP/SOIC Package
PTA5/IRQ/TCLK/RESET 1 16 PTA0/KBIP0/TPM1CH0/ADP0
PTA4/BKGD/MS 2 15 PTA1/KBIP1/TPM1CH1/ADP1
VDD 3 14 PTA2/KBIP2/ADP2
VSS 4 13 PTA3/KBIP3/ADP3
PTB7/EXTAL 5 12 PTB0/KBIP4/RxD/ADP6
PTB6/XTAL 6 11 PTB1/KBIP5/TxD/ADP7
PTB5 7 10 PTB2/KBIP6/ADP8
PTB4/TPM2CH0 8 9 PTB3/KBIP7/ADP9
Figure 3. MC9S08SE8 in 16-Pin TSSOP Package

Electrical Characteristics
3 Electrical Characteristics
This chapter contains electrical and timing specifications.
3.1 Parameter Classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding, the following classification is used and the parameters are tagged
accordingly in the tables where appropriate:
Table 2. Parameter Classifications
P Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically relevant
C
sample size across process variations.
Those parameters are achieved by design characterization on a small sample size from typical devices
T under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
D Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter
tables where appropriate.
3.2 Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the limits specified in Table 3 may affect device reliability or cause permanent
damage to the device. For functional operating conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable
pull-up resistor associated with the pin is enabled.

Table 3. Absolute Maximum Ratings
Rating Symbol Value Unit
Supply voltage VDD –0.3 to 5.8 V

Maximum current into VDD IDD 120 mA
Digital input voltage VIn –0.3 to VDD + 0.3 V
Instantaneous maximum current
ID ±25 mA
Single pin limit (applies to all port pins)1, 2, 3
Storage temperature range Tstg –55 to 150 °C
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2
All functional non-supply pins are internally clamped to VSS and VDD.
3 Power supply must maintain regulation within operating V
DD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
3.3 Thermal Characteristics

This section provides information about operating temperature range, power dissipation, and package
thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in
on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the
MCU design. To take PI/O into account in power calculations, determine the difference between actual pin
voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high
pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.
Table 4. Thermal Characteristics
Rating Symbol Value Unit
Operating temperature range (packaged) TL to TH

C –40 to 85
TA °C
V –40 to 105
M –40 to 125
Maximum junction temperature TJM 135 °C
28-pin SOIC 70
Thermal resistance
28-pin PDIP 68 °C/W
single-layer board
16-pin TSSOP 129
θJA
28-pin SOIC 48
Thermal resistance four-layer
28-pin PDIP 49 °C/W
board
16-pin TSSOP 85

The average chip-junction temperature (TJ) in °C can be obtained from:
TJ = TA + (PD × θJA) Eqn. 1
Where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user-determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ
(if PI/O is neglected) is:
PD = K ÷ (TJ + 273°C) Eqn. 2
Solving Equation 1 and Equation 2 for K gives:
K = PD × (TA + 273°C) + θJA × (PD)2 Eqn. 3
Where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring
PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by
solving Equation 1 and Equation 2 iteratively for any value of TA.
3.4 ESD Protection and Latch-Up Immunity

Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
During the device qualification ESD stresses were performed for the human body model (HBM), the
machine model (MM) and the charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table 5. ESD and Latch-up Test Conditions
Model Description Symbol Value Unit
Series resistance R1 1500 Ω

Human
Storage capacitance C 100 pF
body
Number of pulses per pin — 3 —
Series resistance R1 0 Ω
Machine Storage capacitance C 200 pF
Number of pulses per pin — 3 —

Table 5. ESD and Latch-up Test Conditions (continued)
Model Description Symbol Value Unit
Minimum input voltage limit — –2.5 V

Latch-up
Maximum input voltage limit — 7.5 V
Table 6. ESD and Latch-up Protection Characteristics
No. Rating1 Symbol Min Max Unit
1 Human body model (HBM) VHBM ±2000 — V

2 Machine model (MM) VMM ±200 — V
3 Charge device model (CDM) VCDM ±500 — V
4 Latch-up current at TA = 125 °C ILAT ±100 — mA
1
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
3.5 DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Table 7. DC Characteristics
Num C Parameter Symbol Min Typical1 Max Unit

1 — Operating voltage — 2.7 — 5.5 V
Output high voltage — Low drive (PTxDSn = 0)
5 V, ILoad = –2 mA VDD – 1.5 — —
3 V, ILoad = –0.6 mA VDD – 1.5 — —
5 V, ILoad = –0.4 mA VDD – 0.8 — —
3 V, ILoad = –0.24 mA VDD – 0.8 — —
VOH V
Output high voltage — High drive (PTxDSn = 1)
5 V, ILoad = –10 mA VDD – 1.5 — —
2 P 3 V, ILoad = –3 mA VDD – 1.5 — —
5 V, ILoad = –2 mA VDD – 0.8 — —
3 V, ILoad = –0.4 mA VDD – 0.8 — —
Output low voltage — Low drive (PTxDSn = 0)
5 V, ILoad = 2 mA 1.5 — —
3 V, ILoad = 0.6 mA 1.5 — —
5 V, ILoad = 0.4 mA 0.8 — —
3 V, ILoad = 0.24 mA 0.8 — —
VOL V
Output low voltage — High drive (PTxDSn = 1)
5 V, ILoad = 10 mA 1.5 — —
3 P 3 V, ILoad = 3 mA 1.5 — —
5 V, ILoad = 2 mA 0.8 — —
3 V, ILoad = 0.4 mA 0.8 — —
Output high current — Max total IOH for all ports
4 P 5V IOHT — — 100 mA
3V — — 60

Table 7. DC Characteristics (continued)

Output low current — Max total IOL for all ports
5 P 5V IOLT — — 100 mA
3V — — 60
6 P Input high voltage; all digital inputs VIH 0.65 × VDD — —
V
7 P Input low voltage; all digital inputs VIL — — 0.35 × VDD
8 P Input hysteresis; all digital inputs Vhys 0.06 × VDD — — mV
2
9 C Input leakage current; input only pins |IIn| — 0.1 1 μA
10 P High impedance (off-state) leakage current2 |IOZ| — 0.1 1 μA
Total leakage combined for all inputs and Hi-Z pins
11 C |IOZTOT| — — 2 μA
— All input only and I/O2
12 P Internal pullup resistors3 RPU 20 45 65 kΩ
13 P Internal pulldown resistors4 RPD 20 45 65 kΩ
5, 6, 7
DC injection current
VIN < VSS, VIN > VDD
14 D IIC mA
Single pin limit –0.2 — 0.2
Total MCU limit, includes sum of all stressed pins –5 — 5
15 C Input capacitance; all non-supply pins CIn — — 8 pF
16 C RAM retention voltage VRAM 0.6 1.0 — V
8
17 P POR re-arm voltage VPOR 0.9 1.4 2.0 V
18 D POR re-arm time tPOR 10 — — μs
Low-voltage detection threshold —
high range
19 P VLVD1 V
VDD falling 3.9 4.0 4.1
VDD rising 4.0 4.1 4.2
Low-voltage detection threshold —
low range
20 P VLVD0 V
VDD falling 2.48 2.56 2.64
VDD rising 2.54 2.62 2.70
Low-voltage warning threshold —
high range 1
21 C VLVW3 V
high range 0
22 P VLVW2 V
Low-voltage warning threshold
low range 1
23 P VLVW1 V
VDD falling 2.84 2.92 3.00
VDD rising 2.90 2.98 3.06
low range 0
24 C VLVW0 V
VDD falling 2.66 2.74 2.82
VDD rising 2.72 2.80 2.88

Table 7. DC Characteristics (continued)

Low-voltage inhibit reset/recover hysteresis
25 T 5V Vhys — 100 — mV
3V — 60 —
26 P Bandgap voltage reference9 VBG 1.18 1.20 1.21 V
1
Typical values are measured at 25 °C. Characterized, not tested.
2
Measured with VIn = VDD or VSS.
3
Measured with VIn = VSS.
4
Measured with VIn = VDD.
5
All functional non-supply pins are internally clamped to VSS and VDD.
6
Input must be current-limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.
7
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum
current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of
VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current
greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power.
Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power
consumption).
8 Maximum is highest voltage that POR is guaranteed.
9
Factory trimmed at VDD = 5.0 V, Temp = 25 °C.

VOL vs IOL at VDD = 5.0 V, High Drive
700
-40C
600
0C
500 25C
70C
VDD/mV
400
95C
300 125C
135C
200
100
0
1 1.5 2 2.5 3 9 9.5 10 10.5 11
IOL/mA
Figure 4. Typical VOL vs. IOL for High Drive Enabled Pad (VDD = 5 V)
VOL vs IOL at VDD = 3.0 V, High Drive
350
-40C
300
0C
250
25C
VDD/mV
200 70C
150 95C
100 125C
50 135C
0
0.2 0.3 0.4 0.5 0.6 2 2.5 3 3.5 4
IOL/mA
Figure 5. Typical VOL vs. IOL for High Drive Enabled Pad (VDD = 3 V)

VOL vs IOL at VDD = 5.0 V, Low Drive
600
-40C
500 0C
25C
400
70C
VDD/mV
300 95C
125C
200
135C
100
0
0.2 0.3 0.4 0.5 0.6 1 1.5 2 2.5 3
IOL/mA
Figure 6. Typical VOL vs. IOL for Low Drive Enabled Pad (VDD = 5 V)
VOL vs IOL at VDD = 3.0 V, Low Drive
250
-40C
200 0C
25C
150 70C
VDD/mV
95C
100 125C
135C
50
0
160 200 240 280 320 400 500 600 700 800
IOL/mA
Figure 7. Typical VOL vs. IOL for Low Drive Enabled Pad (VDD = 3 V)

VOH vs IOH at VDD = 5.0 V, High Drive
5.1
-40C
5
0C
4.9
25C
4.8
4.7 70C
VOH/mV
4.6 95C
4.5 125C
4.4 135C
4.3
4.2
4.1
-1 -1.5 -2 -2.5 -3 -9 -9.5 -10 -10.5 -11
IOH/mA
Figure 8. Typical VOH vs. IOH for High Drive Enabled Pad (VDD = 5 V)
VOH vs IOL at VDD = 3.0 V, High Drive
3.05
-40C
3
2.95 0C
2.9 25C
2.85 70C
VOH/mV
2.8 95C
2.75
125C
2.7
135C
2.65
2.6
2.55
2.5
-200 -300 -400 -500 -600 -2 -2.5 -3 -3.5 -4
IOH/mA
Figure 9. Typical VOH vs. IOH for High Drive Enabled Pad (VDD = 3 V)

VOH vs IOH at VDD = 5.0 V, Low Drive
5.2
-40C
5 0C
4.8 25C
70C
VOH/mV
4.6
95C
4.4 125C
4.2 135C
3.8
-200 -300 -400 -500 -600 -1 -1.5 -2 -2.5 -3
IOH/mA
Figure 10. Typical VOH vs. IOH for Low Drive Enabled Pad (VDD = 5 V)
VOH vs IOH at VDD = 3.0 V, Low Drive
3
-40C
2.95
0C
2.9
25C
2.85
70C
VOH/mV
2.8
95C
2.75
125C
2.7
135C
2.65
2.6
2.55
-160 -200 -240 -280 -320 -400 -500 -600 -700 -800
IOH/mA
Figure 11. Typical VOH vs. IOH for Low Drive Enabled Pad (VDD = 3 V)
3.6 Supply Current Characteristics

This section includes information about power supply current in various operating modes.

Table 8. Supply Current Characteristics
VDD Temp
Num C Parameter Symbol Typical1 Max Unit
(V) (°C)
2
Run supply current measured at 5 2.4 2.72
1 C RIDD mA –40 to 125
(CPU clock = 4 MHz, fBus = 2 MHz) 3 2.18 2.26
2
Run supply current measured at 5 6.35 7.29
2 P RIDD mA –40 to 125
(CPU clock = 20 MHz, fBus = 10 MHz) 3 5.79 6.42
2
Wait supply current measured at 5 1.4 1.56
3 P WIDD mA –40 to 125
fBus = 2 MHz 3 1.36 1.53
19 –40 to 85
1.4 28 μA –40 to 105
5
45.8 –40 to 125
4 P Stop2 mode supply current S2IDD
15 –40 to 85
1.3 22 μA –40 to 105
3
37.2 –40 to 125
23 –40 to 85
1.61 43 μA –40 to 105
5
76.1 –40 to 125
5 P Stop3 mode supply current S3IDD
19 –40 to 85
1.44 38 μA –40 to 105
3
66.4 –40 to 125
500 –40 to 85
5 300 nA
500 –40 to 125
6 P RTC adder to stop2 or stop33 S23IDDRTI
500 –40 to 85
3 300 nA
500 –40 to 125
5 122 180 μA –40 to 125
7 C LVD adder to stop3 (LVDE = LVDSE = 1) S3IDDLVD
3 110 160 μA –40 to 125
Adder to stop3 for oscillator enabled4
8 C S3IDDOSC 5,3 5 8 μA –40 to 125
(OSCSTEN =1)
1
Typical values are based on characterization data at 25 °C unless otherwise stated. See Figure 12 through Figure 13 for typical
curves across voltage/temperature.
2
All modules except ADC active, ICS configured for FBE, and does not include any dc loads on port pins.
3 Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait
mode. Wait mode typical is 220 μA at 5 V with fBus = 1 MHz.

4 Values given under the following conditions: low range operation (RANGE = 0) with a 32.768 kHz crystal and low power mode
(HGO = 0).

Run IDD at 10 MHz vs Temp
6
5.5V
5 5.0V
RIDD (mA)
4.5V
4
3.3V
3 3.0V
2.7V
2
0
-40C 0C 25C 70C 95C 125C 135C
Temp (C)
Figure 12. Typical Run IDD Curves
Stop2 IDD vs Temp
20
18
16
14 5.5V
12 5.0V
S2IDD (uA)
4.5V
10
3.3V
8 3.0V
2.7V
6
0
-40C 0C 25C 70C 95C 125C 135C
Temp (C)
Figure 13. Typical Stop2 IDD Curves

Stop3 IDD vs Temp
35
30
25
5.5V
5.0V
S3IDD (uA)
20
4.5V
3.3V
15
3.0V
2.7V
10
0
-40C 0C 25C 70C 95C 125C 135C
Temp (C)
Figure 14. Typical Stop3 IDD Curves
3.7 External Oscillator (XOSC) Characteristics

Table 9. Oscillator electrical specifications (Temperature Range = –40 to 125°C Ambient)
Num C Characteristic Symbol Min. Typical1 Max. Unit
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)

Low range (RANGE = 0) flo 32 — 38.4 kHz
1 C High range (RANGE = 1), high gain (HGO = 1)2 fhi-hgo 1 — 16 MHz
High range (RANGE = 1), low power (HGO = 0)2 fhi-lp 1 — 8 MHz
2 — Load capacitors C1,C2 See crystal or resonator

manufacturer’s recommendation
Feedback resistor
—
3 Low range (32 kHz to 100 kHz) RF — 10 — MΩ
High range (1 MHz to 16 MHz) — 1 —
Series resistor
— Low range, low gain (RANGE = 0, HGO = 0) — 0 —
Low range, high gain (RANGE = 0, HGO = 1) — 100 —
High range, low gain (RANGE = 1, HGO = 0) — 0 —
4 RS kΩ
High range, high gain (RANGE = 1, HGO = 1)
≥ 8 MHz — 0 0
4 MHz — 0 10
1 MHz — 0 20

Table 9. Oscillator electrical specifications (Temperature Range = –40 to 125°C Ambient)
Crystal start-up time3

Low range, low gain (RANGE = 0, HGO = 0) t — 200 —
CSTL-LP
5 T Low range, high gain (RANGE = 0, HGO = 1) t — 400 —
CSTH-HGO ms
High range, low gain (RANGE = 1, HGO = 0)4 t
CSTH-LP — 5 —
High range, high gain (RANGE = 1, HGO = 1)4 t
CSTH-HGO — 15 —
Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)

6 T FEE or FBE mode 2 fextal 0.03125 — 20 MHz
FBELP mode 0 — 20 MHz
1
Typical column was characterized at 5.0 V, 25 °C or is recommended value.
2
The input clock source must be divided using RDIV to within the range of 31.25 kHz to 39.0625 kHz.
3
This parameter is characterized and not tested on each device. Proper PC board layout procedures must be followed to achieve
specifications. This data will vary based upon the crystal manufacturer and board design. The crystal should be characterized
by the crystal manufacturer.
4 4 MHz crystal.
XOSCVLP
EXTAL XTAL
RS
RF
Crystal or Resonator
C1
C2
Figure 15. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain
XOSCVLP
EXTAL XTAL
Crystal or Resonator
Figure 16. Typical Crystal or Resonator Circuit: Low Range/Low Power

3.8 Internal Clock Source (ICS) Characteristics

Table 10. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient)
Average internal reference frequency — factory trimmed

1 P fint_t — 39.0625 — kHz
at VDD = 5 V and temperature = 25 °C
2 P Internal reference frequency — user trimmed fint_ut 31.25 — 39.06 kHz
3 T Internal reference start-up time tIRST — 60 100 μs

DCO output frequency range — Low range
4 D fdco_t 16 — 20 MHz
trimmed2 (DRS = 00)
2
5 D DCO output frequency fdco_DMX32 — 59.77 — MHz
Reference = 32768 Hz and DMX32 = 1
Resolution of trimmed DCO output frequency at fixed
6 C Δfdco_res_t — ±0.1 ±0.2 %fdco
voltage and temperature (using FTRIM)
Resolution of trimmed DCO output frequency at fixed
7 C Δfdco_res_t — ± 0.2 ± 0.4 %fdco
voltage and temperature (not using FTRIM)
Total deviation of DCO output from trimmed frequency3

8 C Over full voltage and temperature range Δfdco_t — –1.0 to 0.5 ±2 %fdco
Over fixed voltage and temperature range of 0 to 70 °C ±0.5 ±1
10 C FLL acquisition time4 tAcquire — — 1 ms
Long term jitter of DCO output clock (averaged over 2-ms

11 C CJitter — 0.02 0.2 %fdco
interval)5
1
Data in Typical column was characterized at 3.0 V, 25 °C or is typical recommended value.
2
The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.
3 This parameter is characterized and not tested on each device.
4 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or
changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used
as the reference, this specification assumes it is already running.
5
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage
for a given interval.

1.00%
0.50%
0.00%
-60 -40 -20 0 20 40 60 80 100 120
Deviation (%)
-0.50%
-1.00% TBD
-1.50%
-2.00%
Temperature
Figure 17. Deviation of DCO Output from Trimmed Frequency (20 MHz, 3.0 V)
3.9 ADC Characteristics

Table 11. 10-Bit ADC Operating Conditions
Characteristic Conditions Symb Min Typ1 Max Unit Comment
Absolute VDDA 2.7 — 5.5 V

Supply voltage
Delta to VDD (VDD – VDDA)2 ΔVDDA –100 0 100 mV
Ground voltage Delta to VSS (VSS – VSSA)2 ΔVSSA –100 0 100 mV
Input voltage VADIN VREFL — VREFH V
Input capacitance CADIN — 4.5 5.5 pF
Input resistance RADIN — 3 5 kΩ
10-bit mode
Analog source fADCK > 4MHz — — 5 External to
fADCK < 4MHz RAS — — 10 kΩ
resistance MCU
8-bit mode (all valid fADCK) — — 10
ADC conversion High speed (ADLPC = 0) 0.4 — 8.0

fADCK MHz
clock frequency Low power (ADLPC = 1) 0.4 — 4.0

1
Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2
DC potential difference.
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT ZADIN
SIMPLIFIED
Pad
ZAS leakage CHANNEL SELECT
due to CIRCUIT
ADC SAR
input ENGINE
RAS RADIN
protection
+
VADIN
–
CAS
VAS +
–
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN CADIN
Figure 18. ADC Input Impedance Equivalency Diagram
Table 12. 10-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA)
Characteristic Conditions C Symb Min Typ1 Max Unit Comment
Supply Current
ADLPC = 1
T IDDA — 133 — μA
ADLSMP = 1
ADCO = 1
Supply Current
ADLPC = 1
ADLSMP = 0
ADCO = 1
Supply Current
ADLPC = 0
ADLSMP = 1
ADCO = 1
Supply Current
ADLPC = 0
D IDDA — 0.582 1 mA
ADLSMP = 0
ADCO = 1
Supply Current Stop, Reset, Module Off D IDDA — 0.011 1 μA

Table 12. 10-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
ADC High Speed (ADLPC = 0) 2 3.3 5

tADACK =
Asynchronous D fADACK MHz
Low Power (ADLPC = 1) 1.25 2 3.3 1/fADACK
Clock Source
Conversion Short Sample (ADLSMP =

— 20 — ADCK
Time (Including 0) D tADC
cycles See SE8
sample time) Long Sample (ADLSMP = 1) — 40 — reference
manual for
Short Sample (ADLSMP = conversion
— 3.5 — ADCK
Sample Time 0) D tADS time variances
cycles
Long Sample (ADLSMP = 1) — 23.5 —
Temp Sensor –40°C– 25°C — 3.266 —

D m mV/°C
Slope 25°C– 125°C — 3.638 —
Temp Sensor
25°C D VTEMP25 — 1.396 — mV
Voltage
Characteristics for 28-pin packages only
Total 10-bit mode P — ±1 ±2.5

Includes
Unadjusted ETUE LSB3
8-bit mode P — ±0.5 ±1.0 quantization
Error
Differential 10-bit mode2 P — ±0.5 ±1.0

DNL LSB3
Non-Linearity 8-bit mode3 P — ±0.3 ±0.5
Integral 10-bit mode T — ±0.5 ±1.0

INL LSB3
Non-Linearity 8-bit mode T — ±0.3 ±0.5
Zero-Scale 10-bit mode P — ±0.5 ±1.5

EZS LSB3 VADIN = VSSA
Error 8-bit mode P — ±0.5 ±0.5
Full-Scale 10-bit mode T — ±0.5 ±1

EFS LSB3 VADIN = VDDA
Error 8-bit mode T — ±0.5 ±0.5
Quantization 10-bit mode — — ±0.5

D EQ LSB3
Error 8-bit mode — — ±0.5
Input Leakage 10-bit mode — ±0.2 ±2.5 Pad leakage4 *

D EIL LSB3
Error 8-bit mode — ±0.1 ±1 RAS
Characteristics for 16-pin package only
Total 10-bit mode P — ±1.5 ±3.5

Includes
Unadjusted ETUE LSB3
8-bit mode P — ±0.7 ±1.5 quantization
Error

Table 12. 10-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Differential 10-bit mode3 P — ±0.5 ±1.0

DNL LSB3
Non-Linearity 8-bit mode3 P — ±0.3 ±0.5
Integral 10-bit mode T — ±0.5 ±1.0

INL LSB3
Non-Linearity 8-bit mode T — ±0.3 ±0.5
Zero-Scale 10-bit mode P — ±1.5 ±2.1

EZS LSB3 VADIN = VSSA
Error 8-bit mode P — ±0.5 ±0.7
Full-Scale 10-bit mode T — ±1 ±1.5

EFS LSB3 VADIN = VDDA
Error 8-bit mode T — ±0.5 ±0.5
Quantization 10-bit mode — — ±0.5

D EQ LSB3
Error 8-bit mode — — ±0.5
Input Leakage 10-bit mode — ±0.2 ±2.5 Pad leakage4 *

D EIL LSB3
Error 8-bit mode — ±0.1 ±1 RAS
1
Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2 Monotonicity and No-Missing-Codes guaranteed in 10-bit and 8-bit modes
3 1 LSB =(V N
REFH – VREFL)/2
4 Based on input pad leakage current. Refer to pad electricals.

3.10 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
3.10.1 Control Timing

Table 13. Control Timing
Num C Rating Symbol Min Typical1 Max Unit
1 D Bus frequency (tcyc = 1/fBus) fBus DC — 10 MHz

2 D Internal low power oscillator period tLPO 700 — 1300 μs
3 D External reset pulse width2 textrst 100 — — ns
4 D Reset low drive3 trstdrv 34 × tcyc — — ns
BKGD/MS setup time after issuing background
5 D tMSSU 500 — — ns
debug force reset to enter user or BDM modes
BKGD/MS hold time after issuing background debug
6 D tMSH 100 — — μs
force reset to enter user or BDM modes4
IRQ pulse width
7 D Asynchronous path2 100 — —
tILIH, tIHIL ns
Synchronous path5 1.5 × tcyc
Pin interrupt pulse width
8 D Asynchronous path2 100 — —
tILIH, tIHIL ns
Synchronous path5 1.5 × tcyc
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)6
tRise, tFall — — ns
Slew rate control disabled (PTxSE = 0) 40
Slew rate control enabled (PTxSE = 1) 75
9 C
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
tRise, tFall — — ns
Slew rate control disabled (PTxSE = 0) 11
Slew rate control enabled (PTxSE = 1) 35
1
Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
2
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
3 When any reset is initiated, internal circuitry drives the reset pin (if enabled, RSTPE = 1) low for about 34 cycles of tcyc.
4
To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD
rises above VLVD.
5
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
6 Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 °C to 125 °C.
textrst
RESET PIN
Figure 19. Reset Timing

tIHIL
IRQ/Pin Interrupts
IRQ/Pin Interrupts
tILIH
Figure 20. IRQ/Pin Interrupt Timing
3.10.2 TPM/MTIM Module Timing

Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
Table 14. TPM Input Timing
Num C Rating Symbol Min Max Unit
1 D External clock frequency fTPMext DC fBus/4 MHz
2 D External clock period tTPMext 4 — tcyc
3 D External clock high time tclkh 1.5 — tcyc
4 D External clock low time tclkl 1.5 — tcyc
5 D Input capture pulse width tICPW 1.5 — tcyc
tTCLK
tclkh
TCLK
tclkl
Figure 21. Timer External Clock
tICPW
TPMCHn
TPMCHn
tICPW
Figure 22. Timer Input Capture Pulse

Ordering Information
3.11 Flash Specifications

This section provides details about program/erase times and program-erase endurance for the flash
memory.
Program and erase operations do not require any special power sources other than the normal VDD supply.
For more detailed information about program/erase operations, see the Memory section in the reference
manual.
Table 15. Flash Characteristics
Num C Characteristic Symbol Min Typical Max Unit
1 D Supply voltage for program/erase Vprog/erase 2.7 — 5.5 V

2 D Supply voltage for read operation VRead 2.7 — 5.5 V
1
3 D Internal FCLK frequency fFCLK 150 — 200 kHz
4 D Internal FCLK period (1/FCLK) tFcyc 5 — 6.67 μs
5 P Byte program time (random location)2 tprog 9 tFcyc
6 P Byte program time (burst mode)2 tBurst 4 tFcyc
7 P Page erase time2 tPage 4000 tFcyc
8 P Mass erase time2 tMass 20,000 tFcyc
Program/erase endurance3
9 C TL to TH = –40 °C to 125 °C nFLPE 10,000 — — cycles
T = 25 °C 100,000
10 C Data retention4 tD_ret 15 100 — years
1
The frequency of this clock is controlled by a software setting.
2 These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for
calculating approximate time to program and erase.
3 Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how
Freescale defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical Endurance for Nonvolatile
Memory.
4 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated
to 25 °C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer
to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory.
4 Ordering Information
This chapter contains ordering information for the device numbering system.
Example of the device numbering system:
MC 9 S08 SE 8 C XX E
Status RoHS compliance indicator (E = yes)
(MC = Fully Qualified) Package designator (see Table 16)
Memory
(9 = Flash-based) Temperature range (C = –40 °C to 85 °C)
Core (V = –40 °C to 105 °C)
(M = –40 °C to 125 °C)
Family Memory Size (in KB)

4.1 Package Information

Table 16. Package Descriptions
Pin Count Package Type Abbreviation Designator Case No. Document No.
28 Plastic Dual In-line Pin PDIP RL 710 98ASB42390B
28 Small Outline Integrated Circuit SOIC WL 751F 98ASB42345B
16 Thin Shrink Small Outline Package TSSOP TG 948F 98ASH70247A
4.2 Mechanical Drawings

The following pages are mechanical drawings for the packages described in Table 16.







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Freescale Semiconductor Document Number: MC9S08SE8

Data Sheet: Technical Data Rev. 4, 4/2015

MC9S08SE8 Series 28-Pin PDIP

Revision Date Description of Changes

Reference Manual (MC9S08SE8RM)

MC9S08SE8 Series MCU Data Sheet, Rev. 4

1 MCU Block Diagram

HCS08 SYSTEM CONTROL

USER RAM RxD PTB7/EXTAL

pins not available on 16-pin package

Figure 1. MC9S08SE8 Series Block Diagram

MC9S08SE8 Series MCU Data Sheet, Rev. 4

MC9S08SE8 Series MCU Data Sheet, Rev. 4

Figure 2. MC9S08SE8 Series in 28-Pin PDIP/SOIC Package

Figure 3. MC9S08SE8 in 16-Pin TSSOP Package

MC9S08SE8 Series MCU Data Sheet, Rev. 4

3.1 Parameter Classification

D Those parameters are derived mainly from simulations.

3.2 Absolute Maximum Ratings

MC9S08SE8 Series MCU Data Sheet, Rev. 4

Table 3. Absolute Maximum Ratings

Rating Symbol Value Unit

Supply voltage VDD –0.3 to 5.8 V

3.3 Thermal Characteristics

Rating Symbol Value Unit

Operating temperature range (packaged) TL to TH

MC9S08SE8 Series MCU Data Sheet, Rev. 4

The average chip-junction temperature (TJ) in °C can be obtained from:

TJ = TA + (PD × θJA) Eqn. 1

PD = K ÷ (TJ + 273°C) Eqn. 2

Solving Equation 1 and Equation 2 for K gives:

K = PD × (TA + 273°C) + θJA × (PD)2 Eqn. 3

3.4 ESD Protection and Latch-Up Immunity

Model Description Symbol Value Unit

Series resistance R1 1500 Ω

MC9S08SE8 Series MCU Data Sheet, Rev. 4

Table 5. ESD and Latch-up Test Conditions (continued)

Model Description Symbol Value Unit

Minimum input voltage limit — –2.5 V

Table 6. ESD and Latch-up Protection Characteristics

No. Rating1 Symbol Min Max Unit

1 Human body model (HBM) VHBM ±2000 — V

Num C Parameter Symbol Min Typical1 Max Unit

MC9S08SE8 Series MCU Data Sheet, Rev. 4

Table 7. DC Characteristics (continued)

Num C Parameter Symbol Min Typical1 Max Unit

MC9S08SE8 Series MCU Data Sheet, Rev. 4

Table 7. DC Characteristics (continued)

Num C Parameter Symbol Min Typical1 Max Unit

MC9S08SE8 Series MCU Data Sheet, Rev. 4

VOL vs IOL at VDD = 5.0 V, High Drive

VOL vs IOL at VDD = 3.0 V, High Drive

MC9S08SE8 Series MCU Data Sheet, Rev. 4

VOL vs IOL at VDD = 5.0 V, Low Drive

VOL vs IOL at VDD = 3.0 V, Low Drive

MC9S08SE8 Series MCU Data Sheet, Rev. 4

VOH vs IOH at VDD = 5.0 V, High Drive

VOH vs IOL at VDD = 3.0 V, High Drive

MC9S08SE8 Series MCU Data Sheet, Rev. 4

VOH vs IOH at VDD = 5.0 V, Low Drive