AN2606

Application note
STM32 microcontroller system memory boot mode

Introduction
The bootloader is stored in the internal boot ROM memory (system memory) of STM32
devices. It is programmed by ST during production. Its main task is to download the
application program to the internal Flash memory through one of the available serial
peripherals (USART, CAN, USB, I2C, SPI, etc.). A communication protocol is defined for
each serial interface, with a compatible command set and sequences. This document
applies to the products listed in Table 1. They are referred as STM32 throughout the
document.

Table 1. Applicable products

Type Part number or product series

STM32F0 Series: STM32F03xxx, STM32F04xxx, STM32F05xxx, STM32F07xxx,

STM32F09xxx
STM32F1 Series.
STM32F2 Series.
STM32F3 Series: STM32F301xx, STM32F302xx, STM32F303xx, STM32F318xx,
STM32F328xx, STM32F334xx, STM32F358xx, STM32F373xx,
STM32F378xx, STM32F398xx
STM32F4 Series: STM32F401xx, STM32F405xx, STM32F407xx, STM32F410xx,
STM32F411xx, STM32F412xx, STM32F413xx, STM32F415xx,
STM32F417xx, STM32F423xx, STM32F427xx, STM32F429xx,
STM32F437xx, STM32F439xx, STM32F446xx, STM32F469xx,
STM32F479xx
STM32F7 Series: STM32F722xx, STM32F723xx, STM32F732xx, STM32F733xx,
Microcontrollers
STM32F745xx, STM32F746xx, STM32F756xx, STM32F765xx,
STM32F767xx, STM32F769xx, STM32F777xx, STM32F779xx
STM32G0 Series: STM32G07xxx, STM32G08xxx
STM32H7 Series: STM32H743xx, STM32H753xx
STM32L0 Series.
STM32L1 Series: STM32L100xx, STM32L151xx, STM32L152xx, STM32L162xx
STM32L4 series: STM32L431xx, STM32L432xx, STM32L433xx, STM32L442xx,
STM32L443xx, STM32L451xx, STM32L452xx, STM32L462xx,
STM32L471xx, STM32L475xx, STM32L476xx, STM32L486xx,
STM32L496xx, STM32L4A6xx, STM32L4R5xx, STM32L4R7xx,
STM32L4R9xx, STM32L4S5xx, STM32L4S7xx, STM32L4S9xx,
STM32L412xx, STM32L422xx
STM32WB series: STM32WB55xx

This application note presents the general concept of the bootloader. It describes the
supported peripherals and hardware requirements to be considered when using the
bootloader of STM32 devices. However the specifications of the low-level communication
protocol for each supported serial peripheral are documented in separate documents as
referred in Section 2: Related documents.

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Contents

1 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2 Related documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4 General bootloader description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1 Bootloader activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2 Bootloader identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3 Hardware connection requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.4 Bootloader memory management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5 STM32F03xx4/6 devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6 STM32F030xC devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7 STM32F05xxx and STM32F030x8 devices bootloader . . . . . . . . . . . . . 36

7.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8 STM32F04xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9 STM32F070x6 devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

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9.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

10 STM32F070xB devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

11 STM32F071xx/072xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . 50

11.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

12 STM32F09xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

12.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
12.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
12.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

13 STM32F10xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

13.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
13.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
13.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

14 STM32F105xx/107xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . 57

14.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
14.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
14.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
14.3.1 How to identify STM32F105xx/107xx bootloader versions . . . . . . . . . . 60
14.3.2 Bootloader unavailability on STM32F105xx/STM32F107xx devices
with a date code below 937 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
14.3.3 USART bootloader Get-Version command returns 0x20
instead of 0x22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
14.3.4 PA9 excessive power consumption when USB cable is plugged
in bootloader V2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

15 STM32F10xxx XL-density devices bootloader . . . . . . . . . . . . . . . . . . . 63

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15.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

15.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
15.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

16 STM32F2xxxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

16.1 Bootloader V2.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
16.1.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
16.1.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
16.1.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
16.2 Bootloader V3.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
16.2.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
16.2.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
16.2.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

17 STM32F301xx/302x4(6/8) devices bootloader . . . . . . . . . . . . . . . . . . . 72

17.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
17.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
17.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

18 STM32F302xB(C)/303xB(C) devices bootloader . . . . . . . . . . . . . . . . . . 75

18.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
18.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
18.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

19 STM32F302xD(E)/303xD(E) devices bootloader . . . . . . . . . . . . . . . . . . 78

19.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
19.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
19.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

20 STM32F303x4(6/8)/334xx/328xx devices bootloader . . . . . . . . . . . . . . 82

20.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
20.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
20.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

21 STM32F318xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

21.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

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21.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

21.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

22 STM32F358xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

22.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
22.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
22.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

23 STM32F373xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

23.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
23.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
23.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

24 STM32F378xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

24.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
24.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
24.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

25 STM32F398xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

25.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
25.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
25.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

26 STM32F40xxx/41xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . 96

26.1 Bootloader V3.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
26.1.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
26.1.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
26.1.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
26.2 Bootloader V9.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
26.2.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
26.2.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
26.2.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

27 STM32F401xB(C) devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . 106

27.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
27.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

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27.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

28 STM32F401xD(E) devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . 112

28.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
28.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
28.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

29 STM32F410xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

29.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
29.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
29.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

30 STM32F411xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

30.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
30.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
30.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

31 STM32F412xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

31.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
31.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
31.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

32 STM32F413xx/423xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 134

32.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
32.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
32.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

33 STM32F42xxx/43xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 140

33.1 Bootloader V7.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
33.1.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
33.1.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
33.1.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
33.2 Bootloader V9.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
33.2.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
33.2.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
33.2.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

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34 STM32F446xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

34.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
34.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
34.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

35 STM32F469xx/479xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 158

35.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
35.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
35.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

36 STM32F72xxx/73xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 165

36.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
36.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
36.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

37 STM32F74xxx/75xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 171

37.1 Bootloader V7.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
37.1.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
37.1.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
37.1.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
37.2 Bootloader V9.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
37.2.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
37.2.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
37.2.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

38 STM32F76xxx/77xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 182

38.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
38.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
38.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

39 STM32G07xxx/08xxx device bootloader . . . . . . . . . . . . . . . . . . . . . . . 189

39.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
39.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
39.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

40 STM32H74xxx/75xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 193

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40.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

40.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
40.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

41 STM32L01xxx/02xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 199

41.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
41.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
41.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

42 STM32L031xx/041xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 203

42.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
42.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
42.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

43 STM32L05xxx/06xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 206

43.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
43.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
43.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

44 STM32L07xxx/08xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 209

44.1 Bootloader V4.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
44.1.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
44.1.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
44.1.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
44.2 Bootloader V11.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
44.2.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
44.2.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
44.2.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

45 STM32L1xxx6(8/B)A devices bootloader . . . . . . . . . . . . . . . . . . . . . . 218

45.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
45.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
45.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

46 STM32L1xxx6(8/B) devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . 220

46.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

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46.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

46.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

47 STM32L1xxxC devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

47.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
47.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
47.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

48 STM32L1xxxD devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

48.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
48.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
48.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

49 STM32L1xxxE devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

49.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
49.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
49.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

50 STM32L412xx/L422xx devices bootloader . . . . . . . . . . . . . . . . . . . . . 233

50.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
50.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
50.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

51 STM32L43xxx/44xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 238

51.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
51.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
51.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

52 STM32L45xxx/46xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 244

52.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
52.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
52.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

53 STM32L47xxx/48xxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 250

53.1 Bootloader V10.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

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53.1.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

53.1.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
53.1.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
53.2 Bootloader V9.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
53.2.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
53.2.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
53.2.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

54 STM32L496xx/4A6xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 262

54.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
54.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
54.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

55 STM32L4Rxxx/4Sxxx devices bootloader . . . . . . . . . . . . . . . . . . . . . . 268

55.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
55.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
55.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

56 STM32WB55xx devices bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

56.1 Bootloader configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
56.2 Bootloader selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
56.3 Bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

57 Device-dependent bootloader parameters . . . . . . . . . . . . . . . . . . . . . 280

58 Bootloader timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

58.1 Bootloader Startup timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
58.2 USART connection timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
58.3 USB connection timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
58.4 I2C connection timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
58.5 SPI connection timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

59 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

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List of tables

Table 1. Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Bootloader activation patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 3. Embedded bootloaders. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 4. STM32 F2, F4 and F7 Voltage Range configuration using bootloader. . . . . . . . . . . . . . . . 31
Table 5. Supported memory area by Write, Read, Erase and Go Commands. . . . . . . . . . . . . . . . . 31
Table 6. STM32F03xx4/6 configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . . . . 32
Table 7. STM32F03xx4/6 bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 8. STM32F030xC configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . . . . . 34
Table 9. STM32F030xC bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 10. STM32F05xxx and STM32F030x8 devices configuration in system memory boot mode . 36
Table 11. STM32F05xxx and STM32F030x8 devices bootloader versions . . . . . . . . . . . . . . . . . . . . 37
Table 12. STM32F04xxx configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 13. STM32F04xxx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 14. STM32F070x6 configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . . . . . 42
Table 15. STM32F070x6 bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 16. STM32F070xB configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . . . . . 46
Table 17. STM32F070xB bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 18. STM32F071xx/072xx configuration in system memory boot mode . . . . . . . . . . . . . . . . . . 50
Table 19. STM32F071xx/072xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 20. STM32F09xxx configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 21. STM32F09xxx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 22. STM32F10xxx configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 23. STM32F10xxx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 24. STM32F105xx/107xx configuration in system memory boot mode . . . . . . . . . . . . . . . . . . 57
Table 25. STM32F105xx/107xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 26. STM32F10xxx XL-density configuration in system memory boot mode . . . . . . . . . . . . . . . 63
Table 27. STM32F10xxx XL-density bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 28. STM32F2xxxx configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 29. STM32F2xxxx bootloader V2.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 30. STM32F2xxxx configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 31. STM32F2xxxx bootloader V3.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 32. STM32F301xx/302x4(6/8) configuration in system memory boot mode. . . . . . . . . . . . . . . 72
Table 33. STM32F301xx/302x4(6/8) bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 34. STM32F302xB(C)/303xB(C) configuration in system memory boot mode . . . . . . . . . . . . . 75
Table 35. STM32F302xB(C)/303xB(C) bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 36. STM32F302xD(E)/303xD(E) configuration in system memory boot mode . . . . . . . . . . . . . 78
Table 37. STM32F302xD(E)/303xD(E) bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 38. STM32F303x4(6/8)/334xx/328xx configuration in system memory boot mode . . . . . . . . . 82
Table 39. STM32F303x4(6/8)/334xx/328xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 40. STM32F318xx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . . . . . 84
Table 41. STM32F318xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 42. STM32F358xx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . . . . . 87
Table 43. STM32F358xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 44. STM32F373xx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . . . . . 89
Table 45. STM32F373xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 46. STM32F378xx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . . . . . 92
Table 47. STM32F378xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 48. STM32F398xx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . . . . . 94

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Table 49. STM32F398xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 50. STM32F40xxx/41xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . 96
Table 51. STM32F40xxx/41xxx bootloader V3.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 52. STM32F40xxx/41xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 100
Table 53. STM32F40xxx/41xxx bootloader V9.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 54. STM32F401xB(C) configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . . 106
Table 55. STM32F401xB(C) bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 56. STM32F401xD(E) configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . . 112
Table 57. STM32F401xD(E) bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 58. STM32F410xx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . . . . 117
Table 59. STM32F410xx bootloader V11.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 60. STM32F411xx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . . . . 122
Table 61. STM32F411xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 62. STM32F412xx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . . . . 128
Table 63. STM32F412xx bootloader V9.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 64. STM32F413xx/423xx configuration in system memory boot mode . . . . . . . . . . . . . . . . . 134
Table 65. STM32F413xx/423xx bootloader V9.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 66. STM32F42xxx/43xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 140
Table 67. STM32F42xxx/43xxx bootloader V7.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 68. STM32F42xxx/43xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 145
Table 69. STM32F42xxx/43xxx bootloader V9.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 70. STM32F446xx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . . . . 152
Table 71. STM32F446xx bootloader V9.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 72. STM32F469xx/479xx configuration in system memory boot mode . . . . . . . . . . . . . . . . . 158
Table 73. STM32F469xx/479xx bootloader V9.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 74. STM32F72xxx/73xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 165
Table 75. STM32F72xxx/73xxx bootloader V9.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 76. STM32F74xxx/75xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 172
Table 77. STM32F74xxx/75xxx bootloader V7.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 78. STM32F74xxx/75xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 176
Table 79. STM32F74xxx/75xxx bootloader V9.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 80. STM32F76xxx/77xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 182
Table 81. STM32F76xxx/77xxx bootloader V9.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 82. STM32G07xxx/8xxx configuration in system memory boot mode . . . . . . . . . . . . . . . . . . 189
Table 83. STM32G07xx/08xxx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 84. STM32H74xxx/75xxx configuration in system memory boot mode . . . . . . . . . . . . . . . . . 193
Table 85. STM32H74xxx/75xxx bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 86. STM32L01xxx/02xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 199
Table 87. STM32L01xxx/02xxx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 88. STM32L031xx/041xx configuration in system memory boot mode . . . . . . . . . . . . . . . . . 203
Table 89. STM32L031xx/041xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 90. STM32L05xxx/06xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 206
Table 91. STM32L05xxx/06xxx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 92. STM32L07xxx/08xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 209
Table 93. STM32L07xxx/08xxx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 94. STM32L07xxx/08xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 213
Table 95. STM32L07xxx/08xxx bootloader V11.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Table 96. STM32L1xxx6(8/B)A configuration in system memory boot mode . . . . . . . . . . . . . . . . . . 218
Table 97. STM32L1xxx6(8/B)A bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 98. STM32L1xxx6(8/B) configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . 220
Table 99. STM32L1xxx6(8/B) bootloader versions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 100. STM32L1xxxC configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . . . . 222

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Table 101. STM32L1xxxC bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Table 102. STM32L1xxxD configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . . . . 225
Table 103. STM32L1xxxD bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 104. STM32L1xxxE configuration in system memory boot mode. . . . . . . . . . . . . . . . . . . . . . . 229
Table 105. STM32L1xxxE bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 106. STM32L412xx/422xx configuration in system memory boot mode . . . . . . . . . . . . . . . . . 233
Table 107. STM32L412xx/422xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Table 108. STM32L43xxx/44xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 238
Table 109. STM32L43xxx/44xxx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Table 110. STM32L45xxx/46xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 244
Table 111. STM32L45xxx/46xxx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Table 112. STM32L47xxx/48xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 250
Table 113. STM32L47xxx/48xxx bootloader V10.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Table 114. STM32L47xxx/48xxx configuration in system memory boot mode. . . . . . . . . . . . . . . . . . 256
Table 115. STM32L47xxx/48xxx bootloader V9.x versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Table 116. STM32L496xx/4A6xx configuration in system memory boot mode . . . . . . . . . . . . . . . . . 262
Table 117. STM32L496xx/4A6xx bootloader version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Table 118. STM32L4Rxxx/4Sxxx configuration in system memory boot mode . . . . . . . . . . . . . . . . . 268
Table 119. STM32L4Rxx/4Sxx bootloader versions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Table 120. STM32WB55xx configuration in system memory boot mode . . . . . . . . . . . . . . . . . . . . . . 275
Table 121. STM32WB55xx bootloader versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Table 122. Bootloader device-dependent parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Table 123. Bootloader startup timings of STM32 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Table 124. USART bootloader minimum timings of STM32 devices . . . . . . . . . . . . . . . . . . . . . . . . . 286
Table 125. USB bootloader minimum timings of STM32 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Table 126. I2C bootloader minimum timings of STM32 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Table 127. SPI bootloader minimum timings of STM32 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Table 128. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

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List of figures AN2606

List of figures

Figure 1. USART Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 2. USB Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 3. I2C Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 4. SPI Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 5. CAN Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 6. Bootloader selection for STM32F03xx4/6 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 7. Bootloader selection for STM32F030xC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 8. Bootloader selection for STM32F05xxx and STM32F030x8 devices . . . . . . . . . . . . . . . . . 37
Figure 9. Bootloader selection for STM32F04xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 10. Bootloader selection for STM32F070x6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 11. Bootloader selection for STM32F070xB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 12. Bootloader selection for STM32F071xx/072xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 13. Bootloader selection for STM32F09xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 14. Bootloader selection for STM32F10xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 15. Bootloader selection for STM32F105xx/107xx devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 16. Bootloader selection for STM32F10xxx XL-density devices. . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 17. Bootloader V2.x selection for STM32F2xxxx devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 18. Bootloader V3.x selection for STM32F2xxxx devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 19. Bootloader selection for STM32F301xx/302x4(6/8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 20. Bootloader selection for STM32F302xB(C)/303xB(C) devices. . . . . . . . . . . . . . . . . . . . . . 77
Figure 21. Bootloader selection for STM32F302xD(E)/303xD(E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 22. Bootloader selection for STM32F303x4(6/8)/334xx/328xx . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 23. Bootloader selection for STM32F318xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 24. Bootloader selection for STM32F358xx devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 25. Bootloader selection for STM32F373xx devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 26. Bootloader selection for STM32F378xx devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 27. Bootloader selection for STM32F398xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 28. Bootloader V3.x selection for STM32F40xxx/41xxx devices . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 29. Bootloader V9.x selection for STM32F40xxx/41xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 30. Bootloader selection for STM32F401xB(C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 31. Bootloader selection for STM32F401xD(E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 32. Bootloader V11.x selection for STM32F410xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 33. Bootloader selection for STM32F411xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 34. Bootloader V9.x selection for STM32F412xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 35. Bootloader V9.x selection for STM32F413xx/423xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 36. Dual Bank Boot Implementation for STM32F42xxx/43xxx Bootloader V7.x . . . . . . . . . . . 142
Figure 37. Bootloader V7.x selection for STM32F42xxx/43xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 38. Dual Bank Boot Implementation for STM32F42xxx/43xxx bootloader V9.x . . . . . . . . . . . 149
Figure 39. Bootloader V9.x selection for STM32F42xxx/43xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 40. Bootloader V9.x selection for STM32F446xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 41. Dual Bank Boot Implementation for STM32F469xx/479xx Bootloader V9.x. . . . . . . . . . . 162
Figure 42. Bootloader V9.x selection for STM32F469xx/479xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 43. Bootloader V9.x selection for STM32F72xxx/73xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 44. Bootloader V7.x selection for STM32F74xxx/75xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 45. Bootloader V9.x selection for STM32F74xxx/75xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 46. Dual Bank Boot Implementation for STM32F76xxx/77xxx Bootloader V9.x . . . . . . . . . . . 186
Figure 47. Bootloader V9.x selection for STM32F76xxx/77xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 48. Access to sticky area from the bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

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Figure 49. Bootloader V11.0 selection for STM32G0xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Figure 50. Bootloader V13.x selection for STM32H74xxx/75xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 51. Bootloader selection for STM32L01xxx/02xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Figure 52. Bootloader selection for STM32L031xx/041xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 53. Bootloader selection for STM32L05xxx/06xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 54. Dual Bank Boot Implementation for STM32L07xxx/08xxx bootloader V4.x . . . . . . . . . . . 211
Figure 55. Bootloader V4.x selection for STM32L07xxx/08xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 56. Dual Bank Boot Implementation for STM32L07xxx/08xxx bootloader V11.x . . . . . . . . . . 215
Figure 57. Bootloader V11.x selection for STM32L07xxx/08xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 58. Bootloader selection for STM32L1xxx6(8/B)A devices. . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Figure 59. Bootloader selection for STM32L1xxx6(8/B) devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 60. Bootloader selection for STM32L1xxxC devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Figure 61. Bootloader selection for STM32L1xxxD devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Figure 62. Bootloader selection for STM32L1xxxE devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 63. Bootloader V9.x selection for STM32L496xx/4A6xx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 64. Bootloader V9.x selection for STM32L43xxx/44xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Figure 65. Bootloader V9.x selection for STM32L45xxx/46xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Figure 66. Dual Bank Boot Implementation for STM32L47xxx/48xxx bootloader V10.x . . . . . . . . . . 253
Figure 67. Bootloader V10.x selection for STM32L47xxx/48xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Figure 68. Dual Bank Boot Implementation for STM32L47xxx/48xxx bootloader V9.x . . . . . . . . . . . 259
Figure 69. Bootloader V9.x selection for STM32L47xxx/48xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Figure 70. Bootloader V9.x selection for STM32L496xx/4A6xx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Figure 71. Dual bank boot implementation for STM32L4Rxxx/STM32L4Sxxx bootloader V9.x . . . . 272
Figure 72. Bootloader V9.x selection for STM32L4Rxx/4Sxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Figure 73. Bootloader V13.0 selection for STM32WB55xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Figure 74. Bootloader Startup timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Figure 75. USART connection timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Figure 76. USB connection timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Figure 77. I2C connection timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Figure 78. SPI connection timing description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

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General information AN2606

1 General information

This document applies to Arm®-based devices.

Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or
elsewhere

2 Related documents

For each supported product (listed in Table 1), please refer to the following documents
available from www.st.com:
• Datasheet or databrief
• Reference manual
• Application Note:
– AN3154: CAN protocol used in the STM32 bootloader
– AN3155: USART protocol used in the STM32 bootloader
– AN3156: USB DFU protocol used in the STM32 bootloader
– AN4221: I2C protocol used in the STM32 bootloader
– AN4286: SPI protocol used in the STM32 bootloader

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AN2606 Glossary

3 Glossary

F0 Series:
STM32F03xxx is used to refer to STM32F030x4, STM32F030x6, STM32F038x6,
STM32F030xC, STM32F031x4 and STM32F031x6 devices.
STM32F04xxx is used to refer to STM32F042x4 and STM32F042x6 devices.
STM32F05xxx and STM32F030x8 devices is used to refer to STM32F051x4,
STM32F051x6, STM32F051x8, STM32F058x8 and STM32F030x8 devices.
STM32F07xxx is used to refer to STM32F070x6, STM32F070xB, STM32F071xB
STM32F072x8 and STM32F072xB devices.
STM32F09xxx is used to refer to STM32F091xx and STM32F098xx devices.
F1 Series:
STM32F10xxx is used to refer to Low-density, Medium-density, High-density, Low-
density value line, Medium-density value line and High-density value line devices:
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and 32
Kbyte.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128
Kbyte.
High-density devices are STM32F101xx and STM32F103xx microcontrollers
where the Flash memory density ranges between 256 and 512 Kbyte.
Low-density value line devices are STM32F100xx microcontrollers where the
Flash memory density ranges between 16 and 32 Kbyte.
Medium-density value line devices are STM32F100xx microcontrollers where
the Flash memory density ranges between 64 and 128 Kbyte.
High-density value line devices are STM32F100xx microcontrollers where the
Flash memory density ranges between 256 and 5128 Kbyte.
STM32F105xx/107xx is used to refer to STM32F105xx and STM32F107xx devices.
STM32F10xxx XL-density is used to refer to STM32F101xx and STM32F103xx
devices where the Flash memory density ranges between 768 Kbyte and 1 Mbyte.
F2 Series:
STM32F2xxxx is used to refer to STM32F215xx, STM32F205xx, STM32F207xx and
SMT32F217xx devices.

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Glossary AN2606

F3 Series:
STM32F301xx/302x4(6/8) is used to refer to STM32F301x4, STM32F301x6,
STM32F301x8, STM32F302x4, STM32F302x6 and STM32F302x8 devices.
STM32F302xB(C)/303xB(C) is used to refer to STM32F302xB, STM32F302xC,
STM32F303xB and STM32F303xC devices.
STM32F302xD(E)/303xD(E) is used to refer to STM32F302xD, STM32F302xE,
STM32F303xD and STM32F303xE devices.
STM32F303x4(6/8)/334xx/328xx is used to refer to STM32F303x4, STM32F303x6,
STM32F303x8, STM32F334x4, STM32F334x6, STM32F334x8, and STM32F328x8
devices.
STM32F318xx is used to refer to STM32F318x8 devices.
STM32F358xx is used to refer to STM32F358xC devices.
STM32F373xx is used to refer to STM32F373x8, STM32F373xB and STM32F373xC
devices.
STM32F378xx is used to refer to STM32F378xC devices.
STM32F398xx is used to refer to STM32F398xE devices.
F4 Series:
STM32F40xxx/41xxx is used to refer to STM32F405xx, STM32F407xx,
STM32F415xx and SMT32F417xx devices.
STM32F401xB(C) is used to refer to STM32F401xB and STM32F401xC devices.
STM32F401xD(E) is used to refer to STM32F401xD and STM32F401xE devices.
STM32F410xx is used to refer to STM32F410x8 and STM32F410xB devices.
STM32F411xx is used to refer to STM32F411xD and STM32F411xE devices.
STM32F412xx is used to refer to STM32F412Cx, STM32F412Rx, STM32F412Vx and
STM32F412Zx devices.
STM32F413xx/423xx is used to refer to STM32F413xG, STM32F413xH and
STM32F423xH devices.
STM32F42xxx/43xxx is used to refer to STM32F427xx, STM32F429xx,
STM32F437xx and STM32F439xx devices
STM32F446xx is used to refer to STM32F446xE and STM32F446xC devices
STM32F469xx/479xx is used to refer to STM32F469xE, STM32F469xG,
STM32F469xI, STM32F479xG and STM32F479xI devices.
F7 Series:
STM32F72xxx/73xxx is used to refer to STM32F722xx, STM32F723xx,
STM32F732xx and STM32F733xx devices.
STM32F74xxx/75xxx is used to refer to STM32F745xx, STM32F746xx and
STM32F756xx devices.
STM32F76xxx/77xxx is used to refer to STM32F765xx, STM32F767xx,
STM32F769xx, STM32F777xx and STM32F779xx devices.
G0Series:
STM32G07xxx/08xxx s used to refer to STM32G07xxx and STM32G08xxx devices.
H7 Series:
STM32H74xxx/75xxx is used to refer to STM32H743xx and STM32H753xx devices.

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L0 Series:
STM32L01xxx/02xxx is used to refer to STM32L011xx and STM32L021xx devices.
STM32L031xx/041xx is used to refer to STM32L031xx and STM32L041xx devices.
STM32L05xxx/06xxx is used to refer to STM32L051xx, STM32L052xx,
STM32L053xx, STM32L062xx and STM32L063xx ultralow power devices.
STM32L07xxx/08xxx is used to refer to STM32L071xx, STM32L072xx,
STM32L073xx, STM32L081xx, STM32L082xx and STM32L083xx devices
L1 Series:
STM32L1xxx6(8/B) is used to refer to STM32L1xxV6T6, STM32L1xxV6H6,
STM32L1xxR6T6, STM32L1xxR6H6, STM32L1xxC6T6, STM32L1xxC6H6,
STM32L1xxV8T6, STM32L1xxV8H6, STM32L1xxR8T6, STM32L1xxR8H6,
STM32L1xxC8T6, STM32L1xxC8H6, STM32L1xxVBT6, STM32L1xxVBH6,
STM32L1xxRBT6, STM32L1xxRBH6, STM32L1xxCBT6 and STM32L1xxCBH6
ultralow power devices.
STM32L1xxx6(8/B)A is used to refer to STM32L1xxV6T6-A, STM32L1xxV6H6-A,
STM32L1xxR6T6-A, STM32L1xxR6H6-A, STM32L1xxC6T6-A, STM32L1xxC6H6-A,
STM32L1xxV8T6-A, STM32L1xxV8H6-A, STM32L1xxR8T6-A, STM32L1xxR8H6-A,
STM32L1xxC8T6-A, STM32L1xxC8H6-A, STM32L1xxVBT6-A, STM32L1xxVBH6-A,
STM32L1xxRBT6-A, STM32L1xxRBH6-A, STM32L1xxCBT6-A and
STM32L1xxCBH6-A ultralow power devices.
STM32L1xxxC is used to refer to STM32L1xxVCT6, STM32L1xxVCH6 ,
STM32L1xxRCT6, STM32L1xxUCY6, STM32L1xxCCT6 and STM32L1xxCCU6
ultralow power devices.
STM32L1xxxD is used to refer to STM32L1xxZDT6, STM32L1xxQDH6,
STM32L1xxVDT6, STM32L1xxRDY6, STM32L1xxRDT6, STM32L1xxZCT6,
STM32L1xxQCH6, STM32L1xxRCY6, STM32L1xxVCT6-A and STM32L1xxRCT6-A
ultralow power devices.
STM32L1xxxE is used to refer to STM32L1xxZET6, STM32L1xxQEH6,
STM32L1xxVET6, STM32L1xxVEY6, and STM32L1xxRET6 ultralow power devices.
L4 Series:
STM32L412xx/422xx is used to refer to STM32L412xB, STM32L412x8,
STM32L422xB devices.
STM32L43xxx/44xxx is used to refer to STM32L431xx, STM32L432xx, STM32L433xx
and STM32L442xx and STM32L443xx devices.
STM32L45xxx/46xxx is used to refer to STM32L451xx, STM32L452xx and
STM32L462xx devices.
STM32L47xxx/48xxx is used to refer to STM32L471xx, STM32L475xx, STM32L476xx
and STM32L486xx devices.
STM32L496xx/4A6xx is used to refer to STM32L496xE, STM32L496xG and
STM32L4A6xG devices.
STM32L4Rxxx/4Sxxx is used to refer to STM32L4R5xx, STM32L4R7xx,
STM32L4R9xx, STM32L4S5xx, STM32L4S7xx and STM32L4S9xx devices.
WB Series:
STM32WB55xx is used to refer to STM32WB55Cx, STM32WB55Rx, STM32WB55Vx
devices.

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Note: BL_USART_Loop refers to the USART bootloader execution loop.

BL_CAN_Loop refers to the CAN bootloader execution loop.
BL_I2C_Loop refers to the I2C bootloader execution loop.
BL_SPI_Loop refers to the SPI bootloader execution loop.

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4 General bootloader description

4.1 Bootloader activation

The bootloader is activated by applying one of the patterns described in Table 2: Bootloader
activation patterns.
If Boot From Bank2 option is activated (for products supporting this feature), bootloader
executes Dual Boot mechanism as described in figures "Dual Bank Boot Implementation for
STM32xxxx" where STM32xxxx is the relative STM32 product.
Otherwise, bootloader selection protocol is executed as described in figures "Bootloader
VY.x selection for STM32xxxx" where STM32xxxx is the relative STM32 product.
When readout protection Level2 is activated, STM32 does not boot on system memory in
any case and bootloader can't be executed (unless jumping to it from Flash user code, all
commands are not accessible except Get, GetID, and GetVersion).

Table 2. Bootloader activation patterns

Patterns Condition

Pattern1 Boot0(pin) = 1 and Boot1(pin) = 0

Pattern2 Boot0(pin) = 1 and nBoot1(bit) = 1
Boot0(pin) = 1, Boot1(pin) = 0 and BFB2(bit) = 1
Boot0(pin) = 0, BFB2(bit) = 0 and both banks don’t contain valid code
Pattern3
Boot0(pin) = 1, Boot1(pin) = 0, BFB2(bit) = 0 and both banks don’t contain valid
code
Boot0(pin) = 1, Boot1(pin) = 0 and BFB2(bit) = 1
Pattern4 Boot0(pin) = 0, BFB2(bit) = 0 and both banks don’t contain valid code
Boot0(pin) = 1, Boot1(pin) = 0 and BFB2(bit) = 0
Boot0(pin) = 1, Boot1(pin) = 0 and BFB2(bit) = 0
Pattern5 Boot0(pin) = 0, BFB2(bit) = 1 and both banks don’t contain valid code
Boot0(pin) = 1, Boot1(pin) = 0 and BFB2 (bit) = 1
Boot0(pin) = 1, nBoot1(bit) = 1 and nBoot0_SW(bit) = 1
Pattern6 nBoot0(bit) = 0, nBoot1(bit) = 1 and nBoot0_SW(bit) = 0
Boot0(pin) = 0, nBoot0_SW(bit) = 1 and main flash empty
Boot0(pin) = 1, nBoot1(bit) = 1 and BFB2(bit) = 0
Pattern7 Boot0(pin) = 0, BFB2(bit) = 1 and both banks don’t contain valid code
Boot0(pin) = 1, nBoot1(bit) = 1 and BFB2(bit) = 1
Boot(pin) = 0 and BOOT_ADD0(optionbyte) = 0x0040
Pattern8
Boot(pin) = 1 and BOOT_ADD1(optionbyte) = 0x0040

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Table 2. Bootloader activation patterns (continued)

Patterns Condition

nDBANK(bit) = 1, Boot(pin) = 0 and BOOT_ADD0(optionbyte) = 0x0040

nDBANK(bit) = 1, Boot(pin) = 1 and BOOT_ADD1(optionbyte) = 0x0040
nDBANK(bit) = 0, nDBOOT(bit) = 1, Boot(pin) = 0 and
BOOT_ADD0(optionbyte) = 0x0040

Pattern9 nDBANK(bit) = 0, nDBOOT(bit) = 1, Boot(pin) = 1 and

BOOT_ADD1(optionbyte) = 0x0040
nDBANK(bit) = 0, nDBOOT(bit) = 0, BOOT_ADDx(optionbyte) out of memory
range or in ICP memory range
nDBANK(bit) = 0, nDBOOT(bit) = 0, BOOT_ADDx(optionbyte) in Flash
memory range and both banks don’t contain valid code
Boot(pin) = 0 and BOOT_ADD0(optionbyte) = 0x1FF0
Pattern10
Boot(pin) = 1 and BOOT_ADD1(optionbyte) = 0x1FF0

In addition to patterns described above, user can execute bootloader by performing a jump
to system memory from user code. Before jumping to bootloader user must:
• Disable all peripheral clocks
• Disable used PLL
• Disable interrupts
• Clear pending interrupts
System memory boot mode can be exited by getting out from bootloader activation
condition and generating hardware reset or using Go command to execute user code.
Note: If you choose to execute the Go command, the peripheral registers used by the bootloader
are not initialized to their default reset values before jumping to the user application. They
should be reconfigured in the user application if they are used. So, if the IWDG is being
used in the application, the IWDG prescaler value has to be adapted to meet the
requirements of the application (since the prescaler was set to its maximum value).
Note: For STM32 devices having the Dual Bank Boot feature, in order to jump to system memory
from user code, the user has first to remap the System Memory bootloader at address
0x00000000 using SYSCFG register (except for STM32F7 series), then jump to bootloader.
For STM32F7 series, the user has to disable nDBOOT and/or nDBANK features (in option
bytes), then jump to bootloader.
Note: For STM32 devices embedding bootloader using the DFU/CAN interface in which the
external clock source (HSE) is required for DFU/CAN operations, the detection of the HSE
value is done dynamically by the bootloader firmware and is based on the internal oscillator
clock (HSI, MSI).
Thus, when due to temperature or other conditions, the internal oscillator precision is altered
above the tolerance band (1% around the theoretical value), the bootloader might calculate
a wrong HSE frequency value.
In this case, the bootloader DFU/CAN interfaces might dysfunction or might not work at all.

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4.2 Bootloader identification

Depending on the STM32 device used, the bootloader may support one or more embedded
serial peripherals used to download the code to the internal Flash memory. The bootloader
identifier (ID) provides information about the supported serial peripherals.
For a given STM32 device, the bootloader is identified by means of the:
1. Bootloader (protocol) version: version of the serial peripheral (USART, CAN, USB,
etc.) communication protocol used in the bootloader. This version can be retrieved
using the bootloader Get Version command.
2. Bootloader identifier (ID): version of the STM32 device bootloader, coded on one
byte in the 0xXY format, where:
– X specifies the embedded serial peripheral(s) used by the device bootloader:
X = 1: one USART is used
X = 2: two USARTs are used
X = 3: USART, CAN and DFU are used
X = 4: USART and DFU are used
X = 5: USART and I2C are used
X = 6: I2C is used
X = 7: USART, CAN, DFU and I2C are used
X = 8: I2C and SPI are used
X = 9: USART, CAN, DFU, I2C and SPI are used
X = 10: USART, DFU and I2C are used
X = 11: USART, I2C and SPI are used
X = 12: USART and SPI are used
X = 13: USART, DFU, I2C and SPI are used
– Y specifies the device bootloader version
Let us take the example of a bootloader ID equal to 0x10. This means that it is the
first version of the device bootloader that uses only one USART.
The bootloader ID is programmed in the last byte address - 1 of the device system
memory and can be read by using the bootloader “Read memory” command or by
direct access to the system memory via JTAG/SWD.
The table below provides identification information about the bootloaders embedded in
STM32 devices.

Table 3. Embedded bootloaders

Bootloader ID Bootloader
STM32 Supported serial
Device (protocol)
series peripherals Memory
ID version
location
STM32F05xxx/STM32F030x8
USART1/USART2 0x21 0x1FFFF7A6 USART (V3.1)
devices
STM32F03xx4/6 USART1 0x10 0x1FFFF7A6 USART (V3.1)
USART (V3.1)
STM32F030xC USART1/I2C1 0x52 0x1FFFF796
I2C1(V1.0)
F0
USART (V3.1)
USART1/USART2/ I2C1/
STM32F04xxx 0xA1 0x1FFFF6A6 DFU (V2.2)
DFU (USB Device FS)
I2C (V1.0)
USART (V3.1)
USART1/USART2/ I2C1/
STM32F071xx/072xx 0xA1 0x1FFFF6A6 DFU (V2.2)
DFU (USB Device FS)
I2C (V1.0)

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Table 3. Embedded bootloaders (continued)

Bootloader ID Bootloader
STM32 Supported serial
Device (protocol)
series peripherals Memory
ID version
location
USART (V3.1)
USART1/USART2/ DFU
STM32F070x6 0xA2 0x1FFFF6A6 DFU (V2.2)
(USB Device FS)/I2C1
I2C (V1.0)
USART (V3.1)
F0 USART1/USART2/ DFU
STM32F070xB 0xA3 0x1FFFF6A6 DFU (V2.2)
(USB Device FS)/I2C1
I2C (V1.0)
USART (V3.1)
STM32F09xxx USART1/USART2/ I2C1 0x50 0x1FFFF796
I2C (V1.0)
Low-density USART1 NA NA USART (V2.2)
Medium-density USART1 NA NA USART (V2.2)
High-density USART1 NA NA USART (V2.2)
STM32F10xxx
Medium-density
USART1 0x10 0x1FFFF7D6 USART (V2.2)
value line
High-density
F1 USART1 0x10 0x1FFFF7D6 USART (V2.2)
value line
USART1 / USART2
USART (V2.2(1))
(remapped) / CAN2
STM32F105xx/107xx NA NA CAN (V2.0)
(remapped) / DFU (USB
DFU(V2.2)
Device)
USART1/USART2
STM32F10xxx XL-density 0x21 0x1FFFF7D6 USART (V3.0)
(remapped)
USART1/USART3 0x20 0x1FFF77DE USART (V3.0)
F2 STM32F2xxxx USART (V3.1)
USART1/USART3/ CAN2/
0x33 0x1FFF77DE CAN (V2.0)
DFU (USB Device FS)
DFU (V2.2)
USART1/USART2/ DFU USART (V3.1)
STM32F373xx 0x41 0x1FFFF7A6
(USB Device FS) DFU (V2.2)
USART (V3.1)
STM32F378xx USART1/USART2/ I2C1 0x50 0x1FFFF7A6
I2C (V1.0)
USART1/USART2/ DFU USART (V3.1)
STM32F302xB(C)/303xB(C) 0x41 0x1FFFF796
(USB Device FS) DFU (V2.2)
USART (V3.1)
STM32F358xx USART1/USART2/ I2C1 0x50 0x1FFFF796
I2C (V1.0)
USART1/USART2/ DFU USART (V3.1)
F3 STM32F301xx/302x4(6/8) 0x40 0x1FFFF796
(USB Device FS) DFU (V2.2)
USART1/USART2/ I2C1/ USART (V3.1)
STM32F318xx 0x50 0x1FFFF796
I2C3 I2C (V1.0)
USART1/USART2/ USART (V3.1)
STM32F302xD(E)/303xD(E) 0x40 0x1FFFF796
DFU (USB Device FS) DFU (V2.2)
USART (V3.1)
STM32F303x4(6/8)/334xx/328xx USART1/USART2/ I2C1 0x50 0x1FFFF796
I2C (V1.0)
USART1/USART2/ USART (V3.1)
STM32F398xx 0x50 0x1FFFF796
I2C1/I2C3 I2C (V1.0)

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Table 3. Embedded bootloaders (continued)

Bootloader ID Bootloader
STM32 Supported serial
Device (protocol)
series peripherals Memory
ID version
location
USART (V3.1)
USART1/USART3/ CAN2/
0x31 0x1FFF77DE CAN (V2.0)
DFU (USB Device FS)
DFU (V2.2)
STM32F40xxx/41xxx USART (V3.1)
USART1/USART3/ CAN2
CAN (V2.0)
/ DFU (USB Device FS)
0x90 0x1FFF77DE DFU (V2.2)
/I2C1/I2C2/I2C3/SPI1/SPI
SPI(V1.1)
2
I2C (V1.0)
USART (V3.1)
USART1/USART3/ CAN2
CAN (V2.0)
/DFU (USB Device FS) / 0x70 0x1FFF76DE
DFU (V2.2)
I2C1
I2C (V1.0)
STM32F42xxx/43xxx USART (V3.1)
USART1/USART3/ CAN2
CAN (V2.0)
/ DFU (USB Device FS) /
0x91 0x1FFF76DE DFU (V2.2)
I2C1/I2C2/I2C3/SPI1/
SPI(V1.1)
SPI2/ SPI4
I2C (V1.0)
USART1/USART2/ DFU USART (V3.1)
(USB Device FS)/ DFU (V2.2)
STM32F401xB(C) 0xD1 0x1FFF76DE
I2C1/I2C2/I2C3/ SPI(V1.1)
SPI1/SPI2/ SPI3 I2C (V1.0)
USART1/USART2/ DFU USART (V3.1)
(USB Device FS)/ DFU (V2.2)
STM32F401xD(E) 0xD1 0x1FFF76DE
I2C1/I2C2/I2C3/ SPI(V1.1)
SPI1/SPI2/ SPI3 I2C (V1.1)
F4
USART1/USART2/ USART (V3.1)
STM32F410xx I2C1/I2C2/I2C4 0xB1 0x1FFF76DE I2C (V1.2)
SPI1/SPI2 SPI (V1.1)
USART1/USART2/ DFU USART (V3.1)
(USB Device FS)/ DFU (V2.2)
STM32F411xx 0xD0 0x1FFF76DE
I2C1/I2C2/I2C3/ SPI(V1.1) I2C
SPI1/SPI2/ SPI3 (V1.1)
USART1/USART2/ USART (V3.1)
USART3/CAN2/ CAN (V2.0)
STM32F412xx DFU (USB Device FS)/ 0x91 0x1FFF76DE DFU (V2.2)
I2C1/I2C2/I2C3/I2C4/ SPI (V1.1)
SPI1/SPI3/SPI4 I2C (V1.2)
USART1/USART2/ USART (V3.1)
USART3/CAN2/ CAN (V2.0)
STM32F413xx/423xx DFU (USB Device FS)/ 0x90 0x1FFF76DE DFU (V2.2)
I2C1/I2C2/I2C3/I2C4/ I2C (V1.2)
SPI1/SPI3/SPI4 SPI (V1.1)
USART (V3.1)
USART1/USART3/ CAN2 CAN (V2.0)
/ DFU (USB Device FS) /
STM32F446xx 0x90 0x1FFF76DE DFU (V2.2)
I2C1/I2C2/I2C3/SPI1/
SPI2/ SPI4 SPI(V1.1)
I2C (V1.2)

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Table 3. Embedded bootloaders (continued)

Bootloader ID Bootloader
STM32 Supported serial
Device (protocol)
series peripherals Memory
ID version
location
USART1/USART3/ USART (V3.1)
I2C1/I2C2/I2C3/ I2C (V1.2)
F4 STM32F469xx/479xx CAN2/ 0x90 0x1FFF76DE CAN (V2.0)
DFU (USB Device FS)/ DFU (V2.2)
SPI1/ SPI2/ SPI4 SPI (V1.1)
USART1/USART3/ USART (V3.1)
CAN1/ CAN (V2.0)
STM32F72xxx/73xxx DFU (USB Device FS)/ 0x90 0x1FF0EDBE DFU (V2.2)
I2C1/I2C2/I2C3/ I2C (V1.2)
SPI1/SPI2/SPI4 SPI (V1.2)
USART1/USART3/ USART (V3.1)
I2C1/I2C2/I2C3/ I2C (V1.2)
0x70 0x1FF0EDBE
CAN2/ CAN (V2.0)
DFU (USB Device FS) DFU (V2.2)
F7 STM32F74xxx/75xxx USART1/USART3/ USART (V3.1)
I2C1/I2C2/I2C3/ I2C (V1.2)
CAN2/ 0x90 0x1FF0EDBE CAN (V2.0)
DFU (USB Device FS)/ DFU (V2.2)
SPI1/SPI2/SPI4 SPI (V1.2)
USART1/USART3/ USART (V3.1)
CAN2/ CAN (V2.0)
STM32F76xxx/77xxx DFU (USB Device FS)/ 0x93 0x1FF0EDBE DFU (V2.2)
I2C1/I2C2/I2C3/ I2C (V1.2)
SPI1/SPI2/SPI4 SPI (V1.2)
USART1/USART2/ USART (V3.1)
G0 STM32G07xxx/08xxx USART3/I2C1/I2C2/ 0xB2 0x1FFF6FFE I2C (V1.2)
SPI1/SPI2 SPI (V1.1)
USART1/USART2/
USART (V3.1)
USART3
I2C (V1.1)
H7 STM32H74xxx/75xxx I2C1/I2C2/I2C3/ 0xD2 0x1FF1E7FE
DFU (V2.2)
DFU (USB Device FS)/
SPI (V1.2)
SPI1/SPI2/SPI3/SPI4
USART (V3.1)
STM32L01xxx/02xxx USART2/SPI1 0xC3 0x1FF00FFE
SPI (V1.1)
USART (V3.1)
STM32L031xx/041xx USART2/SPI1 0xC0 0x1FF00FFE
SPI (V1.1)
USART1/USART2/SPI1/ USART (V3.1)
L0 STM32L05xxx/06xxx 0xC0 0x1FF00FFE
SPI2 SPI (V1.1)
USART1/USART2/ USART (V3.1)
0x41 0x1FF01FFE
DFU (USB Device FS) DFU (V2.2)
STM32L07xxx/08xxx
USART1/USART2/ USART (V3.1)
SPI1/SPI2/ 0xB2 0x1FF01FFE SPI (V1.1)

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Table 3. Embedded bootloaders (continued)

Bootloader ID Bootloader
STM32 Supported serial
Device (protocol)
series peripherals Memory
ID version
location
STM32L1xxx6(8/B) USART1/USART2 0x20 0x1FF00FFE USART (V3.0)
STM32L1xxx6(8/B)A USART1/USART2 0x20 0x1FF00FFE USART (V3.1)
USART1/USART2/ DFU USART (V3.1)
STM32L1xxxC 0x40 0x1FF01FFE
(USB Device FS) DFU (V2.2)
L1
USART1/USART2/ DFU USART (V3.1)
STM32L1xxxD 0x45 0x1FF01FFE
(USB Device FS) DFU (V2.2)
USART1/USART2/ DFU USART (V3.1)
STM32L1xxxE 0x40 0x1FF01FFE
(USB Device FS) DFU (V2.2)
USART1/USART2/ USART (V3.1)
I2C1/I2C2/I2C3/ I2C (V1.2)
STM32L43xxx/44xxx CAN1/ 0x91 0x1FFF6FFE CAN (V2.0)
DFU (USB Device FS)/ DFU (V2.2)
SPI1/SPI2 SPI (V1.1)
USART1/USART2/ USART (V3.1)
I2C1/I2C2/I2C3/ I2C (V1.2)
STM32L45xxx/46xxx CAN1/ 0x92 0x1FFF6FFE CAN (V2.0)
DFU (USB Device FS)/ DFU (V2.2)
SPI1/SPI2 SPI (V1.1)
USART1/USART2/
USART (V3.1)
USART3/
0xA3 0x1FFF6FFE I2C (V1.2)
I2C1/I2C2/I2C3/
DFU (V2.2)
DFU (USB Device FS)
L4 STM32L47xxx/48xxx USART1/USART2/ USART (V3.1)
USART3/ I2C (V1.2)
I2C/I2C2/I2C3/ 0x92 0x1FFF6FFE SPI (V1.1)
SPI1/SPI2/CAN1/ CAN(V2.0)
DFU (USB Device FS) DFU(V2.2)
USART1/USART2/ USART (V3.1)
I2C1/I2C2/I2C3/ I2C (V1.2)
STM32L496xx/4A6xx CAN1/ 0x93 0x1FFF6FFE CAN (V2.0)
DFU (USB Device FS)/ DFU (V2.2)
SPI1/SPI2 SPI (V1.1)
USART1/USART2/ USART (V3.1)
I2C1/I2C2/I2C3/ I2C (V1.2)
STM32L4Rxxx/STM32L4Sxxx CAN1/ 0x92 0x1FFF6FFE CAN (V2.0)
DFU (USB Device FS)/ DFU (V2.2)
SPI1/SPI2 SPI (V1.1)
USART1/ USART (V3.2)
I2C1/I2C3 I2C (V1.2)
WB STM32WB55xx 0xD5 0x1FFF6FFE
SPI1/SPI2 SPI (V1.1)
DFU (USB Device FS) DFU (V2.2)
1. For connectivity line devices, the USART bootloader returns V2.0 instead of V2.2 for the protocol version. For more details
please refer to the “STM32F105xx and STM32F107xx revision Z” errata sheet available from http://www.st.com.

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4.3 Hardware connection requirements

To use the USART bootloader, the host has to be connected to the (RX) and (TX) pins of the
desired USARTx interface via a serial cable.

Figure 1. USART Connection

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1. A Pull-UP resistor should be added, if pull-up resistor are not connected in host side.
2. An RS232 transceiver must be connected to adapt voltage level (3.3V - 12V) between STM32 device and
host.
Note: +V typically 3.3 V and R value typically 100KOhm.This value depend on the application and
the used hardware.
To use the DFU, connect the microcontroller's USB interface to a USB host (i.e. PC).

Figure 2. USB Connection

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1. This additional circuit permits to connect a Pull-Up resistor to (DP) pin using VBus when needed. Refer to
product section (Table which describes STM32 Configuration in system memory boot mode) to know if an
external pull-up resistor must be connected to (DP) pin.
Note: +V typically 3.3 V.This value depends on the application and the used hardware.

28/307 AN2606 Rev 36

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To use the I2C bootloader, connect the host (master) and the desired I2Cx interface (slave)
together via the data (SDA) and clock (SCL) pins. A 1.8 KOhm pull-up resistor has to be
connected to both (SDA) and (SCL) lines.

Figure 3. I2C Connection

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Note: +V typically 3.3 V.This value depends on the application and the used hardware.
To use the SPI bootloader, connect the host (master) and the desired SPIx interface (slave)
together via the (MOSI), (MISO) and (SCK) pins. The (NSS) pin must be connected to
(GND). A pull-down resistor should be connected to the (SCK) line.

Figure 4. SPI Connection

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Note: R value typically 10KOhm. This value depends on the application and the used hardware.
To use the CAN interface, the host has to be connected to the (RX) and (TX) pins of the
desired CANx interface via CAN transceiver and a serial cable. A 120 Ohm resistor should
be added as terminating resistor.

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General bootloader description AN2606

Figure 5. CAN Connection

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Note: When a bootloader firmware supports DFU, it is mandatory that no USB Host is connected
to the USB peripheral during the selection phase of the other interfaces. After selection
phase, the user can plug a USB cable without impacting the selected bootloader execution
except commands which generate a system reset.
It is recommended to keep the RX pins of unused bootloader interfaces (USART_RX,
SPI_MOSI, CAN_RX and USB D+/D- lines if present) at a known (low or high) level at the
startup of the bootloader (detection phase). Leaving these pins floating during the detection
phase might lead to activating unused interface.

4.4 Bootloader memory management

All write operations using bootloader commands must only be Word-aligned (the address
should be a multiple of 4). The number of data to be written must also be a multiple of 4
(non-aligned half page write addresses are accepted).
Some Products embed bootloader that has some specific features:
• Some products don’t support Mass erase operation. To perform a mass erase
operation using bootloader, two options are available:
– Erase all sectors one by one using the Erase command
– Set protection level to Level 1. Then, set it to Level 0 (using the Read protect
command and then the Read Unprotect command). This operation results in a
mass erase of the internal Flash memory.
• Bootloader firmware of STM32 L1 and L0 series supports Data Memory in addition to
standard memories (internal Flash, internal SRAM, option bytes and System memory).
The start address and the size of this area depends on product, please refer to product
reference manual for more information. Data memory can be read and written but
cannot be erased using the Erase Command. When writing in a Data memory location,
the bootloader firmware manages the erase operation of this location before any write.
A write to Data memory must be Word-aligned (address to be written should be a
multiple of 4) and the number of data must also be a multiple of 4. To erase a Data
memory location, you can write zeros at this location.
• Bootloader firmware of STM32 F2, F4, F7 and L4 series supports OTP memory in
addition to standard memories (internal Flash, internal SRAM, option bytes and System
memory). The start address and the size of this area depends on product, please refer
to product reference manual for more information. OTP memory can be read and

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AN2606 General bootloader description

written but cannot be erased using Erase command. When writing in an OTP memory
location, make sure that the relative protection bit is not reset.
• For STM32 F2, F4 and F7 series the internal flash write operation format depends on
voltage Range. By default write operation are allowed by one byte format (Half-Word,
Word and Double-Word operations are not allowed). to increase the speed of write
operation, the user should apply the adequate voltage range that allows write operation
by Half-Word, Word or Double-Word and update this configuration on the fly by the
bootloader software through a virtual memory location. This memory location is not
physical but can be read and written using usual bootloader read/write operations
according to the protocol in use. This memory location contains 4 bytes which are
described in table below. It can be accessed by 1, 2, 3 or 4 bytes. However, reserved
bytes should remain at their default values (0xFF), otherwise the request will be
NACKed.

Table 4. STM32 F2, F4 and F7 Voltage Range configuration using bootloader

Address Size Description

This byte controls the current value of the voltage range.

0x00: voltage range [1.8 V, 2.1 V]
0x01: voltage range [2.1 V, 2.4 V]
0x02: voltage range [2.4 V, 2.7 V]
0xFFFF0000 1 byte 0x03: voltage range [2.7 V, 3.6 V]
0x04: voltage range [2.7 V, 3.6 V] and double word write/erase
operation is used. In this case it is mandatory to supply 9 V
through the VPP pin (refer to the product reference manual for
more details about the double-word write procedure).
Other: all other values are not supported and will be NACKed.
Reserved.
0xFFFF0001 1 byte 0xFF: default value.
Other: all other values are not supported and will be NACKed.
Reserved.
0xFFFF0002 1 byte 0xFF: default value.
Other: all other values are not supported and will be NACKed.
Reserved.
0xFFFF0003 1 byte 0xFF: default value.
Other: all other values are not supported and will be NACKed.

The table below lists the valid memory area depending on the bootloader commands.

Table 5. Supported memory area by Write, Read, Erase and Go Commands

Memory Area Write command Read command Erase command Go command

Flash Supported Supported Supported Supported

RAM Supported Supported Not supported Supported
System Memory Not supported Supported Not supported Not supported
Data Memory Supported Supported Not supported Not supported
OTP Memory Supported Supported Not supported Not supported

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STM32F03xx4/6 devices bootloader AN2606

5 STM32F03xx4/6 devices bootloader

5.1 Bootloader configuration

The STM32F03xx4/6 bootloader is activated by applying pattern2 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 6. STM32F03xx4/6 configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 24 MHz

RCC HSI Enabled (using PLL clocked by HSI).
1 Flash Wait State.
2 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
Common to all
3 Kbyte starting from address 0x1FFFEC00
bootloaders System memory -
contain the bootloader firmware.
The independent watchdog (IWDG)
prescaler is configured to its maximum
IWDG - value. It is periodically refreshed to prevent
watchdog reset in case the hardware IWDG
option was previously enabled by the user.
Once initialized, the USART1 configuration
USART1 USART1 Enabled
is 8 bits, even parity and 1 Stop bit.
bootloader (on
USART1_RX pin Input PA10 pin: USART1 in reception mode.
PA10/PA9)
USART1_TX pin Output PA9 pin: USART1 in transmission mode.
Once initialized, the USART1 configuration
USART1 USART1 Enabled
is 8 bits, even parity and 1 Stop bit.
bootloader (on
USART1_RX pin Input PA15 pin: USART1 in reception mode.
PA14/PA15)
USART1_TX pin Output PA14 pin: USART1 in transmission mode.
USART1 Used to automatically detect the serial baud
SysTick timer Enabled
bootloaders rate from the host.

The system clock is derived from the embedded internal high-speed RC, no external quartz
is required for the bootloader execution.
Note: After the STM32F03xx4/6 devices has booted in bootloader mode, serial wire debug (SWD)
communication is no longer possible until the system is reset. This is because the SWD
uses the PA14 pin (SWCLK) which is already used by the bootloader (USART1_TX).

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5.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 6. Bootloader selection for STM32F03xx4/6 devices

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5.3 Bootloader version

The following table lists the STM32F03xx4/6 devices bootloader versions.

Table 7. STM32F03xx4/6 bootloader versions

Bootloader
version Description Known limitations
number

For the USART interface, two consecutive

NACKs instead of 1 NACK are sent when a
V1.0 Initial bootloader version
Read Memory or Write Memory command is
sent and the RDP level is active.

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6 STM32F030xC devices bootloader

6.1 Bootloader configuration

The STM32F030xC bootloader is activated by applying pattern2 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 8.STM32F030xC configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 48 MHz with

RCC HSI enabled
HSI 8 MHz as clock source.
6 Kbyte starting from address 0x20000000
Common to all RAM -
are used by the bootloader firmware
bootloaders
8 Kbyte starting from address
System memory - 0x1FFFD800, contain the bootloader
firmware.
Once initialized the USART1 configuration
USART1 Enabled
is: 8-bits, even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration
USART2 Enabled
is: 8-bits, even parity and 1 Stop bit
USART2
bootloader USART2_RX pin Input PA15 pin: USART2 in reception mode
USART2_TX pin Output PA14 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
The I2C1 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1000001x
(where x = 0 for write and x = 1 for read)
I2C1 bootloader
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.

Note: After the STM32F030xC devices have booted in bootloader mode using USART2, the serial
wire debug (SWD) communication is no more possible until the system is reset, because
SWD uses PA14 pin (SWCLK) which is already used by the bootloader (USART2_RX).
The system clock is derived from the embedded internal high-speed RC, no external quartz
is required for the bootloader execution.

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6.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 7.Bootloader selection for STM32F030xC

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6.3 Bootloader version

The following table lists the STM32F030xC devices bootloader versions.

Table 9.STM32F030xC bootloader versions

Bootloader
version Description Known limitations
number

V5.2 Initial bootloader version None

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7 STM32F05xxx and STM32F030x8 devices bootloader

7.1 Bootloader configuration

The STM32F05xxx and STM32F030x8 devices bootloader is activated by applying pattern2
(described in Table 2: Bootloader activation patterns). The following table shows the
hardware resources used by this bootloader.

Table 10. STM32F05xxx and STM32F030x8 devices configuration in system memory boot mode
Bootloader Feature/Peripheral State Comment

The system clock frequency is 24 MHz

RCC HSI Enabled (using PLL clocked by HSI).
1 Flash Wait State.
2 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
Common to all 3 Kbyte starting from address
bootloaders System memory - 0x1FFFEC00, contain the bootloader
firmware.
The independent watchdog (IWDG)
prescaler is configured to its maximum
IWDG - value. It is periodically refreshed to prevent
watchdog reset in case the hardware IWDG
option was previously enabled by the user.
Once initialized, the USART1 configuration
USART1 Enabled
is 8 bits, even parity and 1 Stop bit.
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode.
USART1_TX pin Output PA9 pin: USART1 in transmission mode.
Once initialized, the USART2 configuration
USART2 Enabled
is 8 bits, even parity and 1 Stop bit.
USART2
bootloader USART2_RX pin Input PA15 pin: USART2 in reception mode.
USART2_TX pin Output PA14 pin: USART2 in transmission mode.
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host.

The system clock is derived from the embedded internal high-speed RC, no external quartz
is required for the bootloader execution.
Note: After the STM32F05xxx and STM32F030x8 devices have booted in bootloader mode, the
serial wire debug (SWD) communication is no more possible until the system is reset,
because SWD uses PA14 pin (SWCLK) which is already used by the bootloader
(USART2_TX).

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7.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 8. Bootloader selection for STM32F05xxx and STM32F030x8 devices

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7.3 Bootloader version

The following table lists the STM32F05xxx and STM32F030x8 devices bootloader versions.

Table 11. STM32F05xxx and STM32F030x8 devices bootloader versions

Bootloader
version Description Known limitations
number

– At bootloader startup, the HSITRIM value is

set to (0) (in HSITRIM bits on RCC_CR
register) instead of default value (16), as
consequence a deviation is generated in
crystal measurement. For better results,
V2.1 Initial bootloader version please use the smallest supported crystal
value (ie. 4 MHz).
– For the USART interface, two consecutive
NACKs instead of 1 NACK are sent when a
Read Memory or Write Memory command is
sent and the RDP level is active.

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STM32F04xxx devices bootloader AN2606

8 STM32F04xxx devices bootloader

8.1 Bootloader configuration

The STM32F04xxx bootloader is activated by applying pattern6 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 12. STM32F04xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 48 MHz with

HSI enabled
HSI48 48 MHz as clock source.
RCC The clock recovery system (CRS) is
- enabled for the DFU bootloader to allow
USB to be clocked by HSI48 48 MHz.
6 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware
Common to all
13 Kbyte starting from address
bootloaders
System memory - 0x1FFFC400, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
Once initialized the USART1 configuration
USART1 Enabled
is: 8-bits, even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration
USART2 Enabled
is: 8-bits, even parity and 1 Stop bit
USART2
bootloader USART2_RX pin Input PA15 pin: USART2 in reception mode
USART2_TX pin Output PA14 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
The I2C1configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111110x (where x = 0 for write
and x = 1 for read).
I2C1 bootloader
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.

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Table 12. STM32F04xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

USB Enabled USB used in FS mode

USB_DM pin PA11: USB DM line.
DFU bootloader
Input/Output PA12: USB DP line
USB_DP pin
No external pull-up resistor is required.

Note: After the STM32F04xxx devices have booted in bootloader mode using USART2, the serial
wire debug (SWD) communication is no more possible until the system is reset, because
SWD uses PA14 pin (SWCLK) which is already used by the bootloader (USART2_RX).
The system clock is derived from the embedded internal high-speed RC, no external quartz
is required for the bootloader execution.
Note: Due to empty check mechanism present on this product, it is not possible to jump from user
code to system bootloader.
Such jump will result in a jump back to user flash space.
But if the first 4 bytes of User Flash (at 0x0800 0000) are empty at the moment of jump (ie.
erase first sector before jump or execute code from SRAM while Flash is empty), then
system bootloader will be executed when jumped to.

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8.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 9. Bootloader selection for STM32F04xxx

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40/307 AN2606 Rev 36

AN2606 STM32F04xxx devices bootloader

8.3 Bootloader version

The following table lists the STM32F04xxx devices bootloader versions:

Table 13. STM32F04xxx bootloader versions

Bootloader
version Description Known limitations
number

V10.0 Initial bootloader version At bootloader startup, the HSITRIM value is set to (0)
(in HSITRIM bits on RCC_CR register) instead of
Add dynamic support of default value (16), as consequence a deviation is
USART/USB interfaces on generated in crystal measurement.
V10.1
PA11/12 IOs for small For better results, please use the smallest supported
packages. crystal value (ie. 4 MHz).

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STM32F070x6 devices bootloader AN2606

9 STM32F070x6 devices bootloader

9.1 Bootloader configuration

The STM32F070x6 bootloader is activated by applying pattern6 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 14. STM32F070x6 configuration in system memory boot mode

Feature/Periphe
Bootloader State Comment
ral
At startup, the system clock frequency is configured
HSI enabled to 48 MHz using the HSI. If an external clock (HSE) is
not present, the system is kept clocked from the HSI.
The external clock can be used for all bootloader
interfaces and should have one of the following
RCC HSE enabled
values [24, 18, 16, 12, 8, 6, 4] MHz. The PLL is used
Common to all to generate 48 MHz for USB and system clock.
bootloaders The Clock Security System (CSS) interrupt is enabled
- for HSE. Any failure (or removal) of the external clock
generates system reset.
6 Kbyte starting from address 0x20000000 are used
RAM -
by the bootloader firmware
13 Kbyte starting from address 0x1FFFC400, contain
System memory -
the bootloader firmware.
Once initialized the USART1 configuration is: 8-bits,
USART1 Enabled
USART1 even parity and 1 Stop bit
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration is: 8-bits,
USART2 Enabled
USART2 even parity and 1 Stop bit
bootloader USART2_RX pin Input PA15 pin: USART2 in reception mode
USART2_TX pin Output PA14 pin: USART2 in transmission mode
Used to automatically detect the serial baud rate from
USARTx bootloaders SysTick timer Enabled
the host for USARTx bootloaders.
The I2C1 configuration is:
I2C speed: up to 400 KHz, 7-bit address, slave mode,
I2C1 Enabled analog filter ON.
I2C1 bootloader Slave 7-bit address: 0b0111110x where x = 0 for write
and x = 1 for read)
I2C1_SCL pin Input/Output PB6 pin: clock line is used in open-drain mode.
I2C1_SDA pin Input/Output PB7 pin: data line is used in open-drain mode.

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Table 14. STM32F070x6 configuration in system memory boot mode (continued)

Feature/Periphe
Bootloader State Comment
ral
USB FS configured in forced device mode. USB FS
USB Enabled interrupt vector is enabled and used for USB DFU
communications.
DFU bootloader
USB_DM pin PA11 pin: USB FS DM line
Input/Output PA12 pin: USB FS DP line.
USB_DP pin
No external Pull-up resistor is required.

Note: If HSI deviation exceeds 1% , the bootloader might not function correctly.
Note: After the STM32F070x6 devices have booted in bootloader mode using USART2, the serial
wire debug (SWD) communication is no more possible until the system is reset, because
SWD uses PA14 pin (SWCLK) which is already used by the bootloader (USART2_RX).
The bootloader has two cases of operation depending on the presence of the external clock
(HSE) at bootloader startup:
• If HSE is present and has a value of 24, 18, 16, 12, 8, 6, 4 MHz, the system clock is
configured to 48 MHz with HSE as clock source. The DFU interface, USART1,
USART2 and I2C1 are functional and can be used to communicate with the bootloader
device.
• If HSE is not present, the HSI is kept as default clock source and only USART1,
USART2 and I2C1 are functional.
The external clock (HSE) must be kept if it’s connected at bootloader startup because it will
be used as system clock source.
Note: Due to empty check mechanism present on this product, it is not possible to jump from user
code to system bootloader.
Such jump will result in a jump back to user flash space.
But if the first 4 bytes of User Flash (at 0x0800 0000) are empty at the moment of jump (ie.
erase first sector before jump or execute code from SRAM while Flash is empty), then
system bootloader will be executed when jumped to.

AN2606 Rev 36 43/307

306
STM32F070x6 devices bootloader AN2606

9.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 10.Bootloader selection for STM32F070x6

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44/307 AN2606 Rev 36

AN2606 STM32F070x6 devices bootloader

9.3 Bootloader version

The following table lists the STM32F070x6 devices bootloader versions.

Table 15.STM32F070x6 bootloader versions

Bootloader
version Description Known limitations
number

V10.2 Initial bootloader version At bootloader startup, the HSITRIM value is set to
(0) (in HSITRIM bits on RCC_CR register) instead
of default value (16), as consequence a deviation
Clock configuration fixed is generated in crystal measurement. For better
V10.3
to HSI 8 MHz results, please use the smallest supported crystal
value (ie. 4 MHz).

AN2606 Rev 36 45/307

306
STM32F070xB devices bootloader AN2606

10 STM32F070xB devices bootloader

10.1 Bootloader configuration

The STM32F070xB bootloader is activated by applying pattern2 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 16. STM32F070xB configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment
At startup, the system clock frequency is
configured to 48 MHz using the HSI. If an
HSI enabled
external clock (HSE) is not present, the
system is kept clocked from the HSI.
The external clock can be used for all
bootloader interfaces and should have one
RCC HSE enabled of the following values [24, 18, 16, 12, 8, 6,
4] MHz. The PLL is used to generate 48
Common to all MHz for USB and system clock.
bootloaders The Clock Security System (CSS) interrupt
is enabled for HSE. Any failure (or removal)
-
of the external clock generates system
reset.
6 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware
12 Kbyte starting from address
System memory - 0x1FFFC800, contain the bootloader
firmware.
Once initialized the USART1 configuration
USART1 Enabled
USART1 is: 8-bits, even parity and 1 Stop bit
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration
USART2 Enabled
USART2 is: 8-bits, even parity and 1 Stop bit
bootloader USART2_RX pin Input PA15 pin: USART2 in reception mode
USART2_TX pin Output PA14 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
The I2C1 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b0111011x
I2C1 bootloader (where x = 0 for write and x = 1 for read)
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.

46/307 AN2606 Rev 36

AN2606 STM32F070xB devices bootloader

Table 16. STM32F070xB configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment
USB FS configured in forced device mode.
USB Enabled USB FS interrupt vector is enabled and
used for USB DFU communications.
DFU bootloader USB_DM pin PA11 pin: USB FS DM line
Input/Output PA12 pin: USB FS DP line.
USB_DP pin
No external Pull-up resistor is required.

Note: If HSI deviation exceeds 1% , the bootloader might not function correctly.
Note: After the STM32F070xB devices have booted in bootloader mode using USART2, the serial
wire debug (SWD) communication is no more possible until the system is reset, because
SWD uses PA14 pin (SWCLK) which is already used by the bootloader (USART2_RX).
The bootloader has two cases of operation depending on the presence of the external clock
(HSE) at bootloader startup:
• If HSE is present and has a value of 24, 18, 16, 12, 8, 6, 4 MHz, the system clock is
configured to 48 MHz with HSE as clock source. The DFU interface, USART1,
USART2 and I2C1 are functional and can be used to communicate with the bootloader
device.
• If HSE is not present, the HSI is kept as default clock source and only USART1,
USART2 and I2C1 are functional.
The external clock (HSE) must be kept if it’s connected at bootloader startup because it will
be used as system clock source.

AN2606 Rev 36 47/307

306
STM32F070xB devices bootloader AN2606

10.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 11.Bootloader selection for STM32F070xB

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48/307 AN2606 Rev 36

AN2606 STM32F070xB devices bootloader

10.3 Bootloader version

The following table lists the STM32F070xB devices bootloader versions.

Table 17.STM32F070xB bootloader versions

Bootloader
version Description Known limitations
number

V10.2 Initial bootloader version At bootloader startup, the HSITRIM value is set to
(0) (in HSITRIM bits on RCC_CR register) instead
of default value (16), as consequence a deviation
Clock configuration fixed is generated in crystal measurement. For better
V10.3
to HSI 8 MHz results, please use the smallest supported crystal
value (ie. 4 MHz).

AN2606 Rev 36 49/307

306
STM32F071xx/072xx devices bootloader AN2606

11 STM32F071xx/072xx devices bootloader

11.1 Bootloader configuration

The STM32F071xx/072xx bootloader is activated by applying pattern2 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 18. STM32F071xx/072xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 48 MHz with

HSI enabled
HSI48 48 MHz as clock source.
RCC The clock recovery system (CRS) is
- enabled for the DFU bootloader to allow
USB to be clocked by HSI48 48 MHz.
6 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware
Common to all
12 Kbyte starting from address
bootloaders
System memory - 0x1FFFC800, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
Once initialized the USART1 configuration
USART1 Enabled
is: 8-bits, even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration
USART2 Enabled
is: 8-bits, even parity and 1 Stop bit
USART2
bootloader USART2_RX pin Input PA15 pin: USART2 in reception mode
USART2_TX pin Output PA14 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
The I2C1 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111011x (where x = 0 for write
and x = 1 for read)
I2C1 bootloader
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.

50/307 AN2606 Rev 36

AN2606 STM32F071xx/072xx devices bootloader

Table 18. STM32F071xx/072xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

USB Enabled USB used in FS mode

USB_DM pin PA11: USB DM line.
DFU bootloader
Input/Output PA12: USB DP line
USB_DP pin
No external pull-up resistor is required.

Note: After the STM32F071xx/072xx devices have booted in bootloader mode using USART2, the
serial wire debug (SWD) communication is no more possible until the system is reset,
because SWD uses PA14 pin (SWCLK) which is already used by the bootloader
(USART2_RX).
The system clock is derived from the embedded internal high-speed RC, no external quartz
is required for the bootloader execution.

AN2606 Rev 36 51/307

306
STM32F071xx/072xx devices bootloader AN2606

11.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 12. Bootloader selection for STM32F071xx/072xx

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11.3 Bootloader version

The following table lists the STM32F071xx/072xx devices bootloader versions:

Table 19. STM32F071xx/072xx bootloader versions

Bootloader
version Description Known limitations
number

At bootloader startup, the HSITRIM value is set to

(0) (in HSITRIM bits on RCC_CR register) instead
of default value (16), as consequence a deviation
V10.1 Initial bootloader version
is generated in crystal measurement. For better
results, please use the smallest supported crystal
value (ie. 4 MHz).

52/307 AN2606 Rev 36

AN2606 STM32F09xxx devices bootloader

12 STM32F09xxx devices bootloader

12.1 Bootloader configuration

The STM32F09xxx bootloader is activated by applying pattern6 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 20.STM32F09xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 48 MHz with

RCC HSI enabled
HSI48 48 MHz as clock source.
6 Kbyte starting from address 0x20000000
Common to all RAM -
are used by the bootloader firmware
bootloaders
8 Kbyte starting from address
System memory - 0x1FFFD800, contain the bootloader
firmware.
Once initialized the USART1 configuration
USART1 Enabled
is: 8-bits, even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration
USART2 Enabled
is: 8-bits, even parity and 1 Stop bit
PA3 pin: USART2 in reception mode
USART2 USART2_RX pin Input
bootloader PA15 pin: USART2 in reception mode
PA2 pin: USART2 in transmission mode
USART2_TX pin Output
PA14 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
The I2C1 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1000001x
(where x = 0 for write and x = 1 for read)
I2C1 bootloader
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.

Note: After the STM32F09xxx devices have booted in bootloader mode using USART2, the serial
wire debug (SWD) communication is no more possible until the system is reset, because
SWD uses PA14 pin (SWCLK) which is already used by the bootloader (USART2_RX).
The system clock is derived from the embedded internal high-speed RC, no external quartz
is required for the bootloader execution.

AN2606 Rev 36 53/307

306
STM32F09xxx devices bootloader AN2606

12.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 13. Bootloader selection for STM32F09xxx

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12.3 Bootloader version

The following table lists the STM32F09xxx devices bootloader versions.

Table 21.STM32F09xxx bootloader versions

Bootloader
version Description Known limitations
number

At bootloader startup, the HSITRIM value is set to

(0) (in HSITRIM bits on RCC_CR register) instead
of default value (16), as consequence a deviation
V5.0 Initial bootloader version
is generated in crystal measurement. For better
results, please use the smallest supported crystal
value (ie. 4 MHz).

54/307 AN2606 Rev 36

AN2606 STM32F10xxx devices bootloader

13 STM32F10xxx devices bootloader

13.1 Bootloader configuration

The STM32F10xxx bootloader is activated by applying pattern1 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 22. STM32F10xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 24 MHz

RCC HSI enabled
using the PLL.
512 byte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
2 Kbyte starting from address 0x1FFFF000
System memory -
contain the bootloader firmware.
The independent watchdog (IWDG)
prescaler is configured to its maximum
USART1 value and is periodically refreshed to
IWDG -
bootloader prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
Once initialized, the USART1 configuration
USART1 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output push-pull PA9 pin: USART1 in transmission mode
Used to automatically detect the serial baud
SysTick timer Enabled
rate from the host.

The system clock is derived from the embedded internal high-speed RC, no external quartz
is required for the bootloader execution.

AN2606 Rev 36 55/307

306
STM32F10xxx devices bootloader AN2606

13.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 14. Bootloader selection for STM32F10xxx

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13.3 Bootloader version

The following table lists the STM32F10xxx devices bootloader versions:

Table 23. STM32F10xxx bootloader versions

Bootloader version number Description

V2.0 Initial bootloader version

– Updated Go Command to initialize the main stack pointer
– Updated Go command to return NACK when jump address is in
V2.1 the Option byte area or System memory area
– Updated Get ID command to return the device ID on two bytes
– Update the bootloader version to V2.1
– Updated Read Memory, Write Memory and Go commands to
deny access with a NACK response to the first 0x200 bytes of
V2.2 RAM memory used by the bootloader
– Updated Readout Unprotect command to initialize the whole
RAM content to 0x0 before ROP disable operation

56/307 AN2606 Rev 36

AN2606 STM32F105xx/107xx devices bootloader

14 STM32F105xx/107xx devices bootloader

14.1 Bootloader configuration

The STM32F105xx/107xx bootloader is activated by applying pattern1 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 24. STM32F105xx/107xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 24 MHz

using the PLL. This is used only for
USARTx bootloaders and during CAN2,
HSI enabled USB detection for CAN and DFU
bootloaders (once CAN or DFU bootloader
is selected, the clock source will be derived
from the external crystal).
The external clock is mandatory only for
DFU and CAN bootloaders and it must
provide one of the following frequencies: 8
RCC MHz, 14.7456 MHz or 25 MHz.
For CAN bootloader, the PLL is used only
HSE enabled
to generate 48 MHz when 14.7456 MHz is
used as HSE.
For DFU bootloader, the PLL is used to
generate a 48 MHz system clock from all
Common to all supported external clock frequencies.
bootloaders
The Clock Security System (CSS) interrupt
is enabled for the CAN and DFU
-
bootloaders. Any failure (or removal) of the
external clock will generate system reset.
4 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
18 Kbyte starting from address
System memory - 0x1FFFB000 contain the bootloader
firmware.
The independent watchdog (IWDG)
prescaler is configured to its maximum
value and is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
Once initialized, the USART1 configuration
USART1 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output push-pull PA9 pin: USART1 in transmission mode

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STM32F105xx/107xx devices bootloader AN2606

Table 24. STM32F105xx/107xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized, the USART2 configuration

USART2 Enabled is: 8 bits, even parity and 1 Stop bit. The
USART2 uses its remapped pins.
USART2 bootloader
USART2_RX pin Input PD6 pin: USART2 receive (remapped pin)
USART2_TX pin Output push-pull PD5 pin: USART2 transmit (remapped pin)
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloader.
Once initialized, the CAN2 configuration is:
Baudrate 125 kbps, 11-bit identifier.
Note: CAN1 is clocked during the CAN
CAN2 Enabled
bootloader execution because CAN1
CAN2 bootloader manages the communication between
CAN2 and SRAM.
CAN2_RX pin Input PB5 pin: CAN2 receives (remapped pin).
CAN2_TX pin Output push-pull PB6 pin: CAN2 transmits (remapped pin).
USB OTG FS configured in forced device
USB Enabled
mode
USB_VBUS pin Input PA9: Power supply voltage line
DFU bootloader
USB_DM pin PA11 pin: USB_DM line
Input/Output PA12 pin: USB_DP line.
USB_DP pin
No external Pull-up resistor is required

The system clock is derived from the embedded internal high-speed RC for USARTx
bootloader. This internal clock is used also for DFU and CAN bootloaders but only for the
selection phase. An external clock (8 MHz, 14.7456 MHz or 25 MHz.) is required for DFU
and CAN bootloader execution after the selection phase.

58/307 AN2606 Rev 36

AN2606 STM32F105xx/107xx devices bootloader

14.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 15. Bootloader selection for STM32F105xx/107xx devices

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AN2606 Rev 36 59/307

306
STM32F105xx/107xx devices bootloader AN2606

14.3 Bootloader version

The following table lists the STM32F105xx/107xx devices bootloader versions:

Table 25. STM32F105xx/107xx bootloader versions

Bootloader version
Description
number

V1.0 Initial bootloader version

– Bootloader detection mechanism updated to fix the issue when GPIOs of
unused peripherals in this bootloader are connected to low level or left
floating during the detection phase.
For more details please refer to Section 14.3.2.
– Vector table set to 0x1FFFB000 instead of 0x00000000
– Go command updated (for all bootloaders): USART1, USART2, CAN2,
V2.0
GPIOA, GPIOB, GPIOD and SysTick peripheral registers are set to their
default reset values
– DFU bootloader: USB pending interrupt cleared before executing the Leave
DFU command
– DFU subprotocol version changed from V1.0 to V1.2
– Bootloader version updated to V2.0
– Fixed PA9 excessive consumption described in Section 14.3.4.
– Get-Version command (defined in AN3155) corrected. It returns 0x22
V2.1
instead of 0x20 in bootloader V2.0. Refer to Section 14.3.3 for more details.
– Bootloader version updated to V2.1
– Fixed DFU option bytes descriptor (set to ‘e’ instead of ‘g’ because it is
read/write and not erasable).
V2.2 – Fixed DFU polling timings for Flash Read/Write/Erase operations.
– Robustness enhancements for DFU bootloader interface.
– Updated bootloader version to V2.2.

14.3.1 How to identify STM32F105xx/107xx bootloader versions

Bootloader V1.0 is implemented on devices which date code is below 937 (refer to
STM32F105xx and STM32F107xx datasheet for where to find the date code on the device
marking).
Bootloader V2.0 and V2.1 are implemented on devices with a date code higher or equal to
937.
Bootloader V2.2 is implemented on devices with a date code higher or equal to 227 and
lower to 937.
There are two ways to distinguish between bootloader versions:
• When using the USART bootloader, the Get-Version command defined in AN2606 and
AN3155 has been corrected in V2.1 version. It returns 0x22 instead of 0x20 as in
bootloader V2.0.

60/307 AN2606 Rev 36

AN2606 STM32F105xx/107xx devices bootloader

• The values of the vector table at the beginning of the bootloader code are different. The
user software (or via JTAG/SWD) reads 0x1FFFE945 at address 0x1FFFB004 for
bootloader V2.0 0x1FFFE9A1 for bootloader V2.1, and 0x1FFFE9C1 for bootloader
V2.2.
• The DFU version is the following:
– V2.1 in bootloader V2.1
– V2.2 in bootloader V2.2.
It can be read through the bcdDevice field of the DFU Device Descriptor.

14.3.2 Bootloader unavailability on STM32F105xx/STM32F107xx devices

with a date code below 937
Description
The bootloader cannot be used if the USART1_RX (PA10), USART2_RX (PD6, remapped),
CAN2_Rx (PB5, remapped), OTG_FS_DM (PA11), and/or OTG_FS_DP (PA12) pin(s) are
held low or left floating during the bootloader activation phase.
The bootloader cannot be connected through CAN2 (remapped), DFU (OTG FS in Device
mode), USART1 or USART2 (remapped).
On 64-pin packages, the USART2_RX signal remapped PD6 pin is not available and it is
internally grounded. In this case, the bootloader cannot be used at all.

Workaround
• For 64-pin packages
None. The bootloader cannot be used.
• For 100-pin packages
Depending on the used peripheral, the pins for the unused peripherals have to be kept
at a high level during the bootloader activation phase as described below:
– If USART1 is used to connect to the bootloader, PD6 and PB5 have to be kept at a
high level.
– If USART2 is used to connect to the bootloader, PA10, PB5, PA11 and PA12 have
to be kept at a high level.
– If CAN2 is used to connect to the bootloader, PA10, PD6, PA11 and PA12 have to
be kept at a high level.
– If DFU is used to connect to the bootloader, PA10, PB5 and PD6 have to be kept
at a high level.
Note: This limitation applies only to STM32F105xx and STM32F107xx devices with a date code
below 937. STM32F105xx and STM32F107xx devices with a date code higher or equal to
937 are not impacted. See STM32F105xx and STM32F107xx datasheets for where to find
the date code on the device marking.

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306
STM32F105xx/107xx devices bootloader AN2606

14.3.3 USART bootloader Get-Version command returns 0x20

instead of 0x22
Description
In USART mode, the Get-Version command (defined in AN3155) returns 0x20 instead of
0x22.
This limitation is present on bootloader versions V1.0 and V2.0, while it is fixed in bootloader
version 2.1.

Workaround
None.

14.3.4 PA9 excessive power consumption when USB cable is plugged

in bootloader V2.0
Description
When connecting a USB cable after booting from System-Memory mode, PA9 pin
(connected to VBUS=5 V) is also shared with USART TX pin which is configured as alternate
push-pull and forced to 0 since the USART peripheral is not yet clocked. As a consequence,
a current higher than 25 mA is drained by PA9 I/O and may affect the I/O pad reliability.
This limitation is fixed in bootloader version 2.1 by configuring PA9 as alternate function
push-pull when a correct 0x7F is received on RX pin and the USART is clocked. Otherwise,
PA9 is configured as alternate input floating.

Workaround
None.

62/307 AN2606 Rev 36

AN2606 STM32F10xxx XL-density devices bootloader

15 STM32F10xxx XL-density devices bootloader

15.1 Bootloader configuration

The STM32F10xxx XL-density bootloader is activated by applying pattern3 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader:

Table 26. STM32F10xxx XL-density configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 24 MHz

RCC HSI enabled
using the PLL.
2 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
6 Kbyte starting from address 0x1FFFE000
Common to all System memory -
contain the bootloader firmware.
bootloaders
The independent watchdog (IWDG)
prescaler is configured to its maximum
value and is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
Once initialized, the USART1 configuration
USART1 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output push-pull PA9 pin: USART1 in transmission mode
Once initialized, the USART2 configuration
USART2 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART2 PD6 pin: USART2 receives (remapped
USART2_RX pin Input
bootloader pins).
PD5 pin: USART2 transmits (remapped
USART2_TX pin Output push-pull
pins).
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host.

The system clock is derived from the embedded internal high-speed RC, no external quartz
is required for the bootloader execution.

AN2606 Rev 36 63/307

306
STM32F10xxx XL-density devices bootloader AN2606

15.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 16. Bootloader selection for STM32F10xxx XL-density devices

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15.3 Bootloader version

The following table lists the STM32F10xxx XL-density devices bootloader versions:

Table 27. STM32F10xxx XL-density bootloader versions

Bootloader version
Description
number

V2.1 Initial bootloader version

64/307 AN2606 Rev 36

AN2606 STM32F2xxxx devices bootloader

16 STM32F2xxxx devices bootloader

Two bootloader versions are available on STM32F2xxxx devices:

• V2.x supporting USART1 and USART3
This version is embedded in STM32F2xxxx devices revision B.
• V3.x supporting USART1, USART3, CAN2 and DFU (USB FS Device)
This version is embedded in STM32F2xxxx devices revision X and Y.

16.1 Bootloader V2.x

16.1.1 Bootloader configuration

The STM32F2xxxx bootloader is activated by applying pattern1 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 28. STM32F2xxxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

RCC HSI enabled The system clock frequency is 24 MHz.

RAM - 8 Kbyte starting from address 0x20000000.
29 Kbyte starting from address
System memory - 0x1FFF0000, contain the bootloader
firmware.
The independent watchdog (IWDG)
prescaler is configured to its maximum
Common to all value and is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
bootloaders
hardware IWDG option was previously
enabled by the user).
Voltage range is set to [1.62 V, 2.1 V]. In
this range internal Flash write operations
are allowed only in byte format (Half-Word,
Power - Word and Double-Word operations are not
allowed). The voltage range can be
configured in run time using bootloader
commands.
Once initialized, the USART1 configuration
USART1 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized, the USART3 configuration
USART3 USART3 Enabled
is: 8 bits, even parity and 1 Stop bit.
bootloader (on
USART3_RX pin Input PC11 pin: USART3 in reception mode
PC10/PC11)
USART3_TX pin Output PC10 pin: USART3 in transmission mode

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STM32F2xxxx devices bootloader AN2606

Table 28. STM32F2xxxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized, the USART3 configuration

USART3 USART3 Enabled
is: 8 bits, even parity and 1 Stop bit
bootloader (on
USART3_RX pin Input PB11 pin: USART3 in reception mode
PB10/PB11)
USART3_TX pin Output PB10 pin: USART3 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host.

The system clock is derived from the embedded internal high-speed RC. No external quartz
is required for the bootloader code.

16.1.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 17. Bootloader V2.x selection for STM32F2xxxx devices

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66/307 AN2606 Rev 36

AN2606 STM32F2xxxx devices bootloader

16.1.3 Bootloader version

This following table lists the STM32F2xxxx devices V2.x bootloader versions:

Table 29. STM32F2xxxx bootloader V2.x versions

Bootloader
version Description Known limitations
number

When a Read Memory command or Write Memory

command is issued with an unsupported memory
address and a correct address checksum (ie.
address 0x6000 0000), the command is aborted by
the bootloader device, but the NACK (0x1F) is not
sent to the host. As a result, the next 2 bytes (which
are the number of bytes to be read/written and its
V2.0 Initial bootloader version
checksum) are considered as a new command and
its checksum.
For the CAN interface, the Write Unprotect
command is not functional. Instead you can use
Write Memory command and write directly to the
option bytes in order to disable the write
protection.(1)
1. If the “number of data - 1” (N-1) to be read/written is not equal to a valid command code (0x00, 0x01, 0x02,
0x11, 0x21, 0x31, 0x43, 0x44, 0x63, 0x73, 0x82 or 0x92), then the limitation is not perceived from the host
since the command is NACKed anyway (as an unsupported new command).

AN2606 Rev 36 67/307

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STM32F2xxxx devices bootloader AN2606

16.2 Bootloader V3.x

16.2.1 Bootloader configuration

The STM32F2xxxx bootloader is activated by applying pattern1 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 30. STM32F2xxxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 24 MHz

using the PLL.
The HSI clock source is used at startup
HSI enabled (interface detection phase) and when
USARTx interfaces are selected (once CAN
or DFU bootloader is selected, the clock
source will be derived from the external
crystal).
The system clock frequency is 60 MHz.
RCC The HSE clock source is used only when
the CAN or the DFU (USB FS Device)
HSE enabled interfaces are selected.
The external clock must provide a
frequency multiple of 1 MHz and ranging
from 4 MHz to 26 MHz.
The Clock Security System (CSS) interrupt
is enabled for the CAN and DFU
-
bootloaders. Any failure (or removal) of the
Common to all external clock generates system reset.
bootloaders
8 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
29 Kbyte starting from address
System memory - 0x1FF00000 contain the bootloader
firmware.
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
Voltage range is set to [1.62 V, 2.1 V]. In
this range internal Flash write operations
are allowed only in byte format (Half-Word,
Power - Word and Double-Word operations are not
allowed). The voltage range can be
configured in run time using bootloader
commands.

68/307 AN2606 Rev 36

AN2606 STM32F2xxxx devices bootloader

Table 30. STM32F2xxxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized, the USART1 configuration

USART1 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized, the USART3 configuration
USART3 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART3 bootloader
(on PB10/PB11) USART3_RX pin Input PB11 pin: USART3 in reception mode
USART3_TX pin Output PB10 pin: USART3 in transmission mode
Once initialized, the USART3 configuration
USART3 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART3 bootloader
(on PC10/PC11) USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
Once initialized, the CAN2 configuration is:
Baudrate 125 kbps, 11-bit identifier.
Note: CAN1 is clocked during CAN2
CAN2 Enabled
bootloader execution because CAN1
CAN2 bootloader manages the communication between
CAN2 and SRAM.
CAN2_RX pin Input PB5 pin: CAN2 in reception mode
CAN2_TX pin Output PB13 pin: CAN2 in transmission mode
USB OTG FS configured in forced device
USB Enabled
mode
DFU bootloader USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
USB_DP pin
No external Pull-up resistor is required
This timer is used to determine the value of
CAN2 and DFU the HSE. Once the HSE frequency is
TIM11 Enabled
bootloaders determined, the system clock is configured
to 60 MHz using PLL and HSE.

The system clock is derived from the embedded internal high-speed RC for USARTx
bootloaders. This internal clock is also used for CAN and DFU (USB FS Device) but only for
the selection phase. An external clock multiple of 1 MHz (between 4 and 26 MHz) is
required for CAN and DFU bootloader execution after the selection phase.

AN2606 Rev 36 69/307

306
STM32F2xxxx devices bootloader AN2606

16.2.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 18. Bootloader V3.x selection for STM32F2xxxx devices

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70/307 AN2606 Rev 36

AN2606 STM32F2xxxx devices bootloader

16.2.3 Bootloader version

The following table lists the STM32F2xxxx devices V3.x bootloader versions:

Table 31. STM32F2xxxx bootloader V3.x versions

Bootloader
version Description Known limitations
number

– When a Read Memory command or Write

Memory command is issued with an unsupported
memory address and a correct address
checksum (ie. address 0x6000 0000), the
command is aborted by the bootloader device,
but the NACK (0x1F) is not sent to the host. As a
V3.2 Initial bootloader version. result, the next 2 bytes (which are the number of
bytes to be read/written and its checksum) are
considered as a new command and its
checksum(1).
– Option bytes, OTP and Device Feature
descriptors (in DFU interface) are set to “g”
instead of “e” (not erasable memory areas).
– For the USART interface, two consecutive
NACKs (instead of 1 NACK) are sent when a
Read Memory or Write Memory command is sent
Fix V3.2 limitations. DFU and the RDP level is active.
V3.3 interface robustness – For the CAN interface, the Write Unprotect
enhancement. command is not functional. Instead you can use
Write Memory command and write directly to the
option bytes in order to disable the write
protection.
1. If the “number of data - 1” (N-1) to be read/written is not equal to a valid command code (0x00, 0x01, 0x02,
0x11, 0x21, 0x31, 0x43, 0x44, 0x63, 0x73, 0x82 or 0x92), then the limitation is not perceived from the host
since the command is NACKed anyway (as an unsupported new command).

AN2606 Rev 36 71/307

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STM32F301xx/302x4(6/8) devices bootloader AN2606

17 STM32F301xx/302x4(6/8) devices bootloader

17.1 Bootloader configuration

The STM32F301xx/302x4(6/8) bootloader is activated by applying pattern2 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.
Table 32. STM32F301xx/302x4(6/8) configuration in system memory boot mode
Bootloader Feature/Peripheral State Comment

The system clock frequency is 48 MHz with

HSI enabled
HSI48 48 MHz as clock source.
The external clock can be used for all
bootloader interfaces and should have one
the following values [24,18,16,12,9,8,6,4,3]
HSE enabled MHz.
RCC The PLL is used to generate the USB48
MHz clock and the 48 MHz clock for the
system clock.
The Clock Security System (CSS) interrupt
is enabled for the DFU bootloader. Any
-
Common to all failure (or removal) of the external clock
bootloaders generates system reset.
6 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware
8 Kbyte starting from address
System memory - 0x1FFFD800, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
Once initialized the USART1 configuration
USART1 Enabled
is: 8-bits, even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration
USART2 Enabled
is: 8-bits, even parity and 1 Stop bit
USART2
bootloader USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.

72/307 AN2606 Rev 36

AN2606 STM32F301xx/302x4(6/8) devices bootloader

Table 32. STM32F301xx/302x4(6/8) configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

USB Enabled USB used in FS mode

USB_DM pin PA11: USB DM line.
DFU bootloader
Input/Output PA12: USB DP line
USB_DP pin An external pull-up resistor 1.5 KOhm must
be connected to USB_DP pin.

The bootloader has two case of operation depending on the presence of the external clock
(HSE) at bootloader startup:
• If HSE is present and has a value of 24, 18, 16, 12, 9, 8, 6, 4 or 3 MHz, the system
clock is configured to 48 MHz with HSE as clock source. The DFU interface, USART1
and USART2 are functional and can be used to communicate with the bootloader
device.
• If HSE is not present, the HSI is kept as default clock source and only USART1 and
USART2 are functional.
The external clock (HSE) must be kept if it’s connected at bootloader startup because it will
be used as system clock source.

AN2606 Rev 36 73/307

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STM32F301xx/302x4(6/8) devices bootloader AN2606

17.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 19. Bootloader selection for STM32F301xx/302x4(6/8)

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17.3 Bootloader version

The following table lists the STM32F301xx/302x4(6/8) devices bootloader versions:

Table 33. STM32F301xx/302x4(6/8) bootloader versions

Bootloader
version Description Known limitations
number

V4.0 Initial bootloader version None

74/307 AN2606 Rev 36

AN2606 STM32F302xB(C)/303xB(C) devices bootloader

18 STM32F302xB(C)/303xB(C) devices bootloader

18.1 Bootloader configuration

The STM32F302xB(C)/303xB(C) bootloader is activated by applying pattern2 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 34. STM32F302xB(C)/303xB(C) configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

At startup, the system clock frequency is

configured to 48 MHz using the HSI. If an
HSI enabled
external clock (HSE) is not present, the
system is kept clocked from the HSI.
The external clock can be used for all
bootloader interfaces and should have one
the following values [24, 18,16, 12, 9, 8, 6,
RCC HSE enabled 4, 3] MHz.
The PLL is used to generate the USB
48 MHz clock and the 48 MHz clock for the
system clock.
The Clock Security System (CSS) interrupt
Common to all is enabled for the DFU bootloader. Any
-
bootloaders failure (or removal) of the external clock
generates system reset.
5 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
8 Kbyte starting from address
System memory - 0x1FFFD800, contains the bootloader
firmware.
The independent watchdog (IWDG)
prescaler is configured to its maximum
value and is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
Once initialized, the USART1 configuration
USART1 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized, the USART2 configuration
USART2 Enabled is: 8 bits, even parity and 1 Stop bit. The
USART2 uses its remapped pins.
USART2 bootloader
USART2_RX pin Input PD6 pin: USART2 in reception mode
USART2_TX pin Output PD5 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloader.

AN2606 Rev 36 75/307

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STM32F302xB(C)/303xB(C) devices bootloader AN2606

Table 34. STM32F302xB(C)/303xB(C) configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

USB Enabled USB used in FS mode

USB_DM pin PA11: USB DM line.
DFU bootloader
Input/Output PA12: USB DP line
USB_DP pin An external pull-up resistor 1.5 KOhm must
be connected to USB_DP pin.

The bootloader has two case of operation depending on the presence of the external clock
(HSE) at bootloader startup:
• If HSE is present and has a value of 24, 18, 16, 12, 9, 8, 6, 4 or 3 MHz, the system
clock is configured to 48 MHz with HSE as clock source. The DFU interface, USART1
and USART2 are functional and can be used to communicate with the bootloader
device.
• If HSE is not present, the HSI is kept as default clock source and only USART1 and
USART2 are functional.
The external clock (HSE) must be kept if it’s connected at bootloader startup because it will
be used as system clock source.

76/307 AN2606 Rev 36

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18.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 20. Bootloader selection for STM32F302xB(C)/303xB(C) devices

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18.3 Bootloader version

The following table lists the STM32F302xB(C)/303xB(C) devices bootloader versions.

Table 35. STM32F302xB(C)/303xB(C) bootloader versions

Bootloader version number Description Known limitations

V4.1 Initial bootloader version None

AN2606 Rev 36 77/307

306
STM32F302xD(E)/303xD(E) devices bootloader AN2606

19 STM32F302xD(E)/303xD(E) devices bootloader

19.1 Bootloader configuration

The STM32F302xD(E)/303xD(E) bootloader is activated by applying pattern2 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 36.STM32F302xD(E)/303xD(E) configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment
The system clock frequency is 48 MHz with HSI48 48 MHz
HSI enabled
as clock source.
The external clock can be used for all bootloader
interfaces and should have one the following values
HSE enabled [24,18,16, 12, 9, 8, 6, 4, 3] MHz.
RCC
The PLL is used to generate the USB 48 MHz clock and
the 48 MHz clock for the system clock.
The Clock Security System (CSS) interrupt is enabled for
Common to all - the DFU bootloader. Any failure (or removal) of the
bootloaders external clock generates system reset.
6 Kbyte starting from address 0x20000000 are used by the
RAM -
bootloader firmware
8 Kbyte starting from address 0x1FFFD800, contain the
System memory -
bootloader firmware
The independent watchdog (IWDG) prescaler is
configured to its maximum value. It is periodically
IWDG -
refreshed to prevent watchdog reset (in case the hardware
IWDG option was previously enabled by the user).
Once initialized the USART1 configuration is: 8-bits, even
USART1 Enabled
USART1 parity and 1 Stop bit
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration is: 8-bits, even
USART2 Enabled
USART2 parity and 1 Stop bit
bootloader USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
USARTx Used to automatically detect the serial baud rate from the
SysTick timer Enabled
bootloaders host for USARTx bootloaders.
USB FS configured in forced device mode. USB FS
USB Enabled interrupt vector is enabled and used for USB DFU
communications.
DFU bootloader
USB_DM pin PA11 pin: USB FS DM line.
Input/Output PA12 pin: USB FS DP line. An external pull-up resistor 1.5
USB_DP pin
KOhm must be connected to USB_DP pin.

78/307 AN2606 Rev 36

AN2606 STM32F302xD(E)/303xD(E) devices bootloader

The bootloader has two cases of operation depending on the presence of the external clock
(HSE) at bootloader startup:
• If HSE is present and has a value of 24, 18, 16, 12, 9, 8, 6, 4 or 3 MHz, the system
clock is configured to 48 MHz with HSE as clock source. The DFU interface, USART1
and USART2 are functional and can be used to communicate with the bootloader
device.
• If HSE is not present, the HSI is kept as default clock source and only USART1 and
USART2 are functional.
The external clock (HSE) must be kept if it’s connected at bootloader startup because it will
be used as system clock source.

AN2606 Rev 36 79/307

306
STM32F302xD(E)/303xD(E) devices bootloader AN2606

19.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 21. Bootloader selection for STM32F302xD(E)/303xD(E)

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80/307 AN2606 Rev 36

AN2606 STM32F302xD(E)/303xD(E) devices bootloader

19.3 Bootloader version

The following table lists the STM32F302xD(E)/303xD(E) devices bootloader versions.

Table 37.STM32F302xD(E)/303xD(E) bootloader versions

Bootloader
version Description Known limitations
number

V4.0 Initial bootloader version None

AN2606 Rev 36 81/307

306
STM32F303x4(6/8)/334xx/328xx devices bootloader AN2606

20 STM32F303x4(6/8)/334xx/328xx devices bootloader

20.1 Bootloader configuration

The STM32F303x4(6/8)/334xx/328xx bootloader is activated by applying pattern2
(described in Table 2: Bootloader activation patterns). The following table shows the
hardware resources used by this bootloader.

Table 38. STM32F303x4(6/8)/334xx/328xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 60 MHz with

RCC HSI enabled
HSI 8 MHz as clock source.
6 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware
8 Kbyte starting from address
Common to all System memory - 0x1FFFD800, contain the bootloader
bootloaders firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
Once initialized the USART1 configuration
USART1 Enabled
is: 8-bits, even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration
USART2 Enabled
is: 8-bits, even parity and 1 Stop bit
USART2
bootloader USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
The I2C1 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111111x (where x = 0 for write
and x = 1 for read)
I2C1 bootloader
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.

The system clock is derived from the embedded internal high-speed RC, no external quartz
is required for the bootloader execution.

82/307 AN2606 Rev 36

AN2606 STM32F303x4(6/8)/334xx/328xx devices bootloader

20.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 22. Bootloader selection for STM32F303x4(6/8)/334xx/328xx

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20.3 Bootloader version

The following table lists the STM32F303x4(6/8)/334xx/328xx devices bootloader versions:

Table 39. STM32F303x4(6/8)/334xx/328xx bootloader versions

Bootloader
version Description Known limitations
number

V5.0 Initial bootloader version None

AN2606 Rev 36 83/307

306
STM32F318xx devices bootloader AN2606

21 STM32F318xx devices bootloader

21.1 Bootloader configuration

The STM32F318xx bootloader is activated by applying pattern2 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 40. STM32F318xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 60 MHz with

RCC HSI enabled
HSI 8 MHz as clock source.
6 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware
8 Kbyte starting from address
Common to all System memory - 0x1FFFD800, contain the bootloader
bootloaders firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
Once initialized the USART1 configuration
USART1 Enabled
is: 8-bits, even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration
USART2 Enabled
is: 8-bits, even parity and 1 Stop bit
USART2
bootloader USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
The I2C1 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111101x (where x = 0 for write
and x = 1 for read)
I2C1 bootloader
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.

84/307 AN2606 Rev 36

AN2606 STM32F318xx devices bootloader

Table 40. STM32F318xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C3 configuration is:

I2C speed: up to 400 KHz, 7-bit address,
I2C3 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111101x (where x = 0 for write
and x = 1 for read) and digital filter disabled.
I2C3 bootloader
PA8 pin: clock line is used in open-drain
I2C3_SCL pin Input/Output
mode.
PB5 pin: data line is used in open-drain
I2C3_SDA pin Input/Output
mode.

The system clock is derived from the embedded internal high-speed RC, no external quartz
is required for the bootloader execution.

21.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 23. Bootloader selection for STM32F318xx

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AN2606 Rev 36 85/307

306
STM32F318xx devices bootloader AN2606

21.3 Bootloader version

The following table lists the STM32F318xx devices bootloader versions:

Table 41. STM32F318xx bootloader versions

Bootloader
version Description Known limitations
number

V5.0 Initial bootloader version None

86/307 AN2606 Rev 36

AN2606 STM32F358xx devices bootloader

22 STM32F358xx devices bootloader

22.1 Bootloader configuration

The STM32F358xx bootloader is activated by applying pattern2 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 42. STM32F358xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 8 MHz using

RCC HSI enabled
the HSI.
5 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
8 Kbyte starting from address
System memory - 0x1FFFD800, contains the bootloader
Common to all firmware.
bootloaders
The independent watchdog (IWDG)
prescaler is configured to its maximum
value and is periodically refreshed to
IWDG - prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user). Window feature is
disabled.
Once initialized, the USART1 configuration
USART1 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode.
USART1_TX pin Output PA9 pin: USART1 in transmission mode.
Once initialized, the USART2 configuration
USART2 Enabled is: 8 bits, even parity and 1 Stop bit. The
USART2 USART2 uses its remapped pins.
bootloader USART2_RX pin Input PD6 pin: USART2 in reception mode.
USART2_TX pin Output PD5 pin: USART2 in transmission mode.
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloader.
The I2C1 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0110111x (where x = 0 for write
I2C1 and x = 1 for read)
bootloader
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.

AN2606 Rev 36 87/307

306
STM32F358xx devices bootloader AN2606

The system clock is derived from the embedded internal high-speed RC, no external quartz
is required for the bootloader execution.

22.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 24. Bootloader selection for STM32F358xx devices

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22.3 Bootloader version

The following table lists the STM32F358xx devices bootloader versions.
Table 43. STM32F358xx bootloader versions
Bootloader version
Description Known limitations
number

For USART1 and USART2 interfaces,

V5.0 Initial bootloader version the maximum baudrate supported by
the bootloader is 57600 baud.

88/307 AN2606 Rev 36

AN2606 STM32F373xx devices bootloader

23 STM32F373xx devices bootloader

23.1 Bootloader configuration

The STM32F373xx bootloader is activated by applying pattern2 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 44. STM32F373xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

At startup, the system clock frequency is

configured to 48 MHz using the HSI. If an
HSI enabled
external clock (HSE) is not present, the
system is kept clocked from the HSI.
The external clock can be used for all
bootloader interfaces and should have one
the following values [24,18,16,12,9,8,6,4,3]
RCC HSE enabled MHz.
The PLL is used to generate the USB
48 MHz clock and the 48 MHz clock for the
system clock.
The Clock Security System (CSS) interrupt
Common to all is enabled for the DFU bootloader. Any
-
bootloaders failure (or removal) of the external clock
generates system reset.
5 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
8 Kbyte starting from address
System memory - 0x1FFFD800, contains the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value and is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
Once initialized, the USART1 configuration
USART1 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized, the USART2 configuration
USART2 Enabled is: 8 bits, even parity and 1 Stop bit. The
USART2 uses its remapped pins.
USART2 bootloader
USART2_RX pin Input PD6 pin: USART2 in reception mode
USART2_TX pin Output PD5 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloader.

AN2606 Rev 36 89/307

306
STM32F373xx devices bootloader AN2606

Table 44. STM32F373xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

USB Enabled USB used in FS mode

USB_DM pin PA11: USB DM line.
DFU bootloader
Input/Output PA12: USB DP line
USB_DP pin An external pull-up resistor 1.5 KOhm must
be connected to USB_DP pin.

The bootloader has two case of operation depending on the presence of the external clock
(HSE) at bootloader startup:
• If HSE is present and has a value of 24, 18, 16, 12, 9, 8, 6, 4 or 3 MHz, the system
clock is configured to 48 MHz with HSE as clock source. The DFU interface, USART1
and USART2 are functional and can be used to communicate with the bootloader
device.
• If HSE is not present, the HSI is kept as default clock source and only USART1 and
USART2 are functional.
Note: The external clock (HSE) must be kept if it’s connected at bootloader startup because it will
be used as system clock source.

90/307 AN2606 Rev 36

AN2606 STM32F373xx devices bootloader

23.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 25. Bootloader selection for STM32F373xx devices

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23.3 Bootloader version

The following table lists the STM32F373xx devices bootloader versions.

Table 45. STM32F373xx bootloader versions

Bootloader version number Description Known limitations

V4.1 Initial bootloader version None

AN2606 Rev 36 91/307

306
STM32F378xx devices bootloader AN2606

24 STM32F378xx devices bootloader

24.1 Bootloader configuration

The STM32F378xx bootloader is activated by applying pattern2 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 46. STM32F378xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 8 MHz using

RCC HSI enabled
the HSI.
4 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
8 Kbyte starting from address
System memory - 0x1FFFD800, contains the bootloader
Common to all firmware
bootloaders
The independent watchdog (IWDG)
prescaler is configured to its maximum
value and is periodically refreshed to
IWDG - prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user). Window feature is
disabled.
Once initialized, the USART1 configuration
USART1 Enabled
is: 8 bits, even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode.
USART1_TX pin Output PA9 pin: USART1 in transmission mode.
Once initialized, the USART2 configuration
USART2 Enabled is: 8 bits, even parity and 1 Stop bit. The
USART2 USART2 uses its remapped pins.
bootloader USART2_RX pin Input PD6 pin: USART2 in reception mode.
USART2_TX pin Output PD5 pin: USART2 in transmission mode.
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloader.
The I2C1 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0110111x (where x = 0 for write
I2C1 and x = 1 for read).
bootloader
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.

92/307 AN2606 Rev 36

AN2606 STM32F378xx devices bootloader

The system clock is derived from the embedded internal high-speed RC, no external quartz
is required for the bootloader execution.

24.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 26. Bootloader selection for STM32F378xx devices

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24.3 Bootloader version

The following table lists the STM32F378xx devices bootloader versions.
Table 47. STM32F378xx bootloader versions
Bootloader version
Description Known limitations
number

For USART1 and USART2 interfaces, the

V5.0 Initial bootloader version maximum baudrate supported by the
bootloader is 57600 baud.

AN2606 Rev 36 93/307

306
STM32F398xx devices bootloader AN2606

25 STM32F398xx devices bootloader

25.1 Bootloader configuration

The STM32F398xx bootloader is activated by applying pattern2 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 48.STM32F398xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment
The system clock frequency is 60 MHz with HSI 8
RCC HSI enabled
MHz as clock source.
6 Kbyte starting from address 0x20000000 are
RAM -
used by the bootloader firmware
Common to all 7 Kbyte starting from address 0x1FFFD800,
System memory -
bootloaders contain the bootloader firmware
The independent watchdog (IWDG) prescaler is
configured to its maximum value. It is periodically
IWDG - refreshed to prevent watchdog reset (in case the
hardware IWDG option was previously enabled by
the user).
Once initialized the USART1 configuration is: 8-
USART1 Enabled
USART1 bits, even parity and 1 Stop bit
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration is: 8-
USART2 Enabled
USART2 bits, even parity and 1 Stop bit
bootloader USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
USARTx Used to automatically detect the serial baud rate
SysTick timer Enabled
bootloaders from the host for USARTx bootloaders.
The I2C1 configuration is:
I2C speed: up to 400 KHz, 7-bit address, slave
I2C1 Enabled mode, analog filter ON. Slave 7-bit address:
I2C1 bootloader 0b1000000x (where x = 0 for write and x = 1 for
read).
I2C1_SCL pin Input/Output PB6 pin: clock line is used in open-drain mode.
I2C1_SDA pin Input/Output PB7 pin: data line is used in open-drain mode.
The I2C3 configuration is:
I2C speed: up to 400 KHz, 7-bit address, slave
I2C3 Enabled mode, analog filter ON. Slave 7-bit address:
I2C3 bootloader 0b1000000x (where x = 0 for write and x = 1 for
read).
I2C3_SCL pin Input/Output PA8 pin: clock line is used in open-drain mode.
I2C3_SDA pin Input/Output PB5 pin: data line is used in open-drain mode.

The system clock is derived from the embedded internal high-speed RC for all bootloader
interfaces. No external quartz is required for bootloader operations.

94/307 AN2606 Rev 36

AN2606 STM32F398xx devices bootloader

25.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 27.Bootloader selection for STM32F398xx

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25.3 Bootloader version

The following table lists the STM32F398xx devices bootloader versions.

Table 49.STM32F398xx bootloader versions

Bootloader
version Description Known limitations
number

V5.0 Initial bootloader version None

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26 STM32F40xxx/41xxx devices bootloader

26.1 Bootloader V3.x

26.1.1 Bootloader configuration

The STM32F40xxx/41xxx bootloader is activated by applying pattern1 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 50. STM32F40xxx/41xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 24 MHz

using the PLL.
The HSI clock source is used at startup
HSI enabled (interface detection phase) and when
USARTx interfaces are selected (once CAN
or DFU bootloader is selected, the clock
source will be derived from the external
crystal).
The system clock frequency is 60 MHz.
RCC The HSE clock source is used only when
the CAN or the DFU (USB FS Device)
HSE enabled interfaces are selected.
The external clock must provide a
frequency multiple of 1 MHz and ranging
from 4 MHz to 26 MHz.
The Clock Security System (CSS) interrupt
is enabled for the CAN and DFU
-
Common to all bootloaders. Any failure (or removal) of the
bootloaders external clock generates system reset.
8 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
29 Kbyte starting from address 0x1FFF
System memory -
0000 contain the bootloader firmware.
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
Voltage range is set to [1.62 V, 2.1 V]. In
this range internal Flash write operations
are allowed only in byte format (Half-Word,
Power - Word and Double-Word operations are not
allowed). The voltage range can be
configured in run time using bootloader
commands.

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Table 50. STM32F40xxx/41xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized, the USART1 configuration

USART1 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized, the USART3 configuration
USART3 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART3 bootloader
(on PB10/PB11) USART3_RX pin Input PB11 pin: USART3 in reception mode
USART3_TX pin Output PB10 pin: USART3 in transmission mode
Once initialized, the USART3 configuration
USART3 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART3 bootloader
(on PC10/PC11) USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
Once initialized, the CAN2 configuration is:
Baudrate 125 kbps, 11-bit identifier.
Note: CAN1 is clocked during CAN2
CAN2 Enabled
bootloader execution because CAN1
CAN2 bootloader manages the communication between
CAN2 and SRAM.
CAN2_RX pin Input PB5 pin: CAN2 in reception mode
CAN2_TX pin Output PB13 pin: CAN2 in transmission mode
USB OTG FS configured in forced device
USB Enabled
mode
DFU bootloader USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
USB_DP pin
No external Pull-up resistor is required
This timer is used to determine the value of
CAN2 and DFU the HSE. Once the HSE frequency is
TIM11 Enabled
bootloaders determined, the system clock is configured
to 60 MHz using PLL and HSE.

The system clock is derived from the embedded internal high-speed RC for USARTx
bootloaders. This internal clock is also used for CAN and DFU (USB FS Device) but only for
the selection phase. An external clock multiple of 1 MHz (between 4 and 26 MHz) is
required for CAN and DFU bootloader execution after the selection phase.

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26.1.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 28. Bootloader V3.x selection for STM32F40xxx/41xxx devices

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98/307 AN2606 Rev 36

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26.1.3 Bootloader version

The following table lists the STM32F40xxx/41xxx devices V3.x bootloader versions:

Table 51. STM32F40xxx/41xxx bootloader V3.x versions

Bootloader
version Description Known limitations
number

– When a Read Memory command or Write

Memory command is issued with an unsupported
memory address and a correct address
checksum (ie. address 0x6000 0000), the
command is aborted by the bootloader device,
but the NACK (0x1F) is not sent to the host. As a
result, the next 2 bytes (which are the number of
bytes to be read/written and its checksum) are
V3.0 Initial bootloader version considered as a new command and its
checksum(1).
– Option bytes, OTP and Device Feature
descriptors (in DFU interface) are set to “g”
instead of “e” (not erasable memory areas).
After executing Go command (jump to user code)
the bootloader resets AHB1ENR value to 0x0000
0000 and thus CCM RAM, when present, is not
active (shall be re-enabled by user code at startup)
– For the USART interface, two consecutive
NACKs (instead of 1 NACK) are sent when a
Read Memory or Write Memory command is sent
and the RDP level is active.
– For the CAN interface, the Write Unprotect
Fix V3.0 limitations. DFU command is not functional. Instead you can use
V3.1 interface robustness Write Memory command and write directly to the
enhancement. option bytes in order to disable the write
protection.
After executing Go command (jump to user code)
the bootloader resets AHB1ENR value to 0x0000
0000 and thus CCM RAM, when present, is not
active (shall be re-enabled by user code at startup)
1. If the “number of data - 1” (N-1) to be read/written is not equal to a valid command code (0x00, 0x01, 0x02,
0x11, 0x21, 0x31, 0x43, 0x44, 0x63, 0x73, 0x82 or 0x92), then the limitation is not perceived from the host
since the command is NACKed anyway (as an unsupported new command).

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26.2 Bootloader V9.x

26.2.1 Bootloader configuration

The STM32F40xxx/41xxx bootloader is activated by applying pattern1 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.
Note: The bootloader version V9.x is only embedded in STM32F405xx/415xx WCSP90 package
devices.

Table 52. STM32F40xxx/41xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 60 MHz

using the PLL.
The HSI clock source is used at startup
HSI enabled (interface detection phase) and when
USART or SPI or I2C interfaces are
selected (once CAN or DFU bootloader is
selected, the clock source will be derived
from the external crystal).
The system clock frequency is 60 MHz.
RCC The HSE clock source is used only when
the CAN or the DFU (USB FS Device)
HSE enabled interfaces are selected.
The external clock must provide a
frequency multiple of 1 MHz and ranging
from 4 MHz to 26 MHz.
The Clock Security System (CSS) interrupt
is enabled for the CAN and DFU
-
bootloaders. Any failure (or removal) of the
Common to all external clock generates system reset.
bootloaders 12 Kbyte starting from address
RAM - 0x20000000 are used by the bootloader
firmware
29 Kbyte starting from address
System memory - 0x1FFF0000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
Voltage range is set to [1.62 V, 2.1 V]. In
this range internal Flash write operations
are allowed only in byte format (Half-Word,
Power - Word and Double-Word operations are not
allowed). The voltage range can be
configured in run time using bootloader
commands.

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Table 52. STM32F40xxx/41xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART1 configuration

USART1 Enabled
is: 8-bits, even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART3 configuration
USART3 USART3 Enabled
is: 8-bits, even parity and 1 Stop bit
bootloader (on
USART3_RX pin Input PB11 pin: USART3 in reception mode
PB10/PB11)
USART3_TX pin Output PB10 pin: USART3 in transmission mode
Once initialized the USART3 configuration
USART3 USART3 Enabled
is: 8-bits, even parity and 1 Stop bit
bootloader (on
USART3_RX pin Input PC11 pin: USART3 in reception mode
PC10/PC11)
USART3_TX pin Output PC10 pin: USART3 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
Once initialized the CAN2 configuration is:
Baudrate 125 kbps, 11-bit identifier.
CAN2 Enabled Note: CAN1 is clocked during CAN2
bootloader execution because CAN1
CAN2 bootloader manages the communication between
CAN2 and SRAM.
CAN2_RX pin Input PB5 pin: CAN2 in reception mode
CAN2_TX pin Output PB13 pin: CAN2 in transmission mode
The I2C1 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111010x (where x = 0 for write
and x = 1 for read).
I2C1 bootloader
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.
The I2C2 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C2 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111010x (where x = 0 for write
and x = 1 for read).
I2C2 bootloader
PF1 pin: clock line is used in open-drain
I2C2_SCL pin Input/Output
mode.
PF0 pin: data line is used in open-drain
I2C2_SDA pin Input/Output
mode.

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Table 52. STM32F40xxx/41xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C3 configuration is:

I2C speed: up to 400 KHz, 7-bit address,
I2C3 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111010x (where x = 0 for write
and x = 1 for read).
I2C3 bootloader
PA8 pin: clock line is used in open-drain
I2C3_SCL pin Input/Output
mode.
PC9 pin: data line is used in open-drain
I2C3_SDA pin Input/Output
mode.
The SPI1 configuration is:
slave mode, Full Duplex, 8-bit MSB, Speed
SPI1 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PA7 pin: Slave data Input line, used in
SPI1_MOSI pin Input
Push-pull pull-down mode
SPI1 bootloader
PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
Push-pull pull-down mode
PA5 pin: Slave clock line, used in Push-pull
SPI1_SCK pin Input
pull-down mode
PA4 pin: slave chip select pin used in Push-
SPI1_NSS pin Input
pull pull-down mode.
The SPI2 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI2 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PI3 pin: Slave data Input line, used in Push-
SPI2_MOSI pin Input
pull pull-down mode
SPI2 bootloader
PI2 pin: Slave data output line, used in
SPI2_MISO pin Output
Push-pull pull-down mode
PI1 pin: Slave clock line, used in Push-pull
SPI2_SCK pin Input
pull-down mode
PI0 pin: slave chip select pin used in Push-
SPI2_NSS pin Input
pull pull-down mode.
USB OTG FS configured in forced device
USB Enabled
mode
DFU bootloader USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
USB_DP pin
No external Pull-up resistor is required
This timer is used to determine the value of
CAN2 and DFU the HSE. Once the HSE frequency is
TIM11 Enabled
bootloaders determined, the system clock is configured
to 60 MHz using PLL and HSE.

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The system clock is derived from the embedded internal high-speed RC for USARTx, I2Cx
and SPIx bootloaders. This internal clock is also used for CAN and DFU (USB FS Device)
but only for the selection phase. An external clock multiple of 1 MHz (between 4 and
26 MHz) is required for CAN and DFU bootloader execution after the selection phase.

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26.2.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 29. Bootloader V9.x selection for STM32F40xxx/41xxx

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104/307 AN2606 Rev 36

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26.2.3 Bootloader version

The following table lists the STM32F40xxx/41xxx devices V9.x bootloader versions.

Table 53. STM32F40xxx/41xxx bootloader V9.x versions

Bootloader
version Description Known limitations
number

– For the USART interface, two consecutive

NACKs (instead of 1 NACK) are sent when a
This bootloader is an updated Read Memory or Write Memory command is sent
version of bootloader v3.1. and the RDP level is active.
This new version of bootloader – For the CAN interface, the Write Unprotect
supports I2C1, I2C2, I2C3, SPI1 command is not functional. Instead you can use
V9.0 and SPI2 interfaces. Write Memory command and write directly to the
The RAM used by this bootloader option bytes in order to disable the write
is increased from 8Kb to 12Kb. protection.
The ID of this bootloader is 0x90. After executing Go command (jump to user code)
The connection time is increased. the bootloader resets AHB1ENR value to 0x0000
0000 and thus CCM RAM, when present, is not
active (shall be re-enabled by user code at startup)

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27 STM32F401xB(C) devices bootloader

27.1 Bootloader configuration

The STM32F401xB(C) bootloader is activated by applying pattern1 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 54. STM32F401xB(C) configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 60 MHz

using the PLL.
The HSI clock source is used at startup
HSI enabled (interface detection phase) and when
USART or SPI or I2C interface is selected
(once DFU bootloader is selected, the clock
source will be derived from the external
crystal).
The system clock frequency is 60 MHz.
RCC The HSE clock source is used only when
the DFU (USB FS Device) interface is
HSE enabled selected.
The external clock must provide a
frequency multiple of 1 MHz and ranging
from 4 MHz to 26 MHz.
The Clock Security System (CSS) interrupt
is enabled for the CAN and DFU
-
bootloaders. Any failure (or removal) of the
Common to all external clock generates system reset.
bootloaders
12 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware
29 Kbyte starting from address
System memory - 0x1FFF0000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
Voltage range is set to [1.62 V, 2.1 V]. In
this range internal Flash write operations
are allowed only in byte format (Half-Word,
Power - Word and Double-Word operations are not
allowed). The voltage range can be
configured in run time using bootloader
commands.

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Table 54. STM32F401xB(C) configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART1 configuration

USART1 Enabled
is: 8-bits, even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration
USART2 Enabled
is: 8-bits, even parity and 1 Stop bit
USART2
bootloader USART2_RX pin Input PD6 pin: USART2 in reception mode
USART2_TX pin Output PD5 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
The I2C1 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111001x (where x = 0 for write
and x = 1 for read)
I2C1 bootloader
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.
The I2C2 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C2 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111001x (where x = 0 for write
and x = 1 for read)
I2C2 bootloader
PB10 pin: clock line is used in open-drain
I2C2_SCL pin Input/Output
mode.
PB3 pin: data line is used in open-drain
I2C2_SDA pin Input/Output
mode.
The I2C3 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C3 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111001x (where x = 0 for write
and x = 1 for read)
I2C3 bootloader
PA8 pin: clock line is used in open-drain
I2C3_SCL pin Input/Output
mode.
PB4 pin: data line is used in open-drain
I2C3_SDA pin Input/Output
mode.

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Table 54. STM32F401xB(C) configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI1 configuration is:

Slave mode, Full Duplex, 8-bit MSB, Speed
SPI1 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PA7 pin: Slave data Input line, used in
SPI1_MOSI pin Input
SPI1 bootloader Push-pull pull-down mode
PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
Push-pull pull-down mode
PA5 pin: Slave clock line, used in Push-pull
SPI1_SCK pin Input
pull-down mode
PA4 pin: slave chip select pin used in Push-
SPI1_NSS pin Input
pull pull-down mode.
The SPI2 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI2 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PB15 pin: Slave data Input line, used in
SPI2_MOSI pin Input
SPI2 bootloader Push-pull pull-down mode
PB14 pin: Slave data output line, used in
SPI2_MISO pin Output
Push-pull pull-down mode
PB13 pin: Slave clock line, used in Push-
SPI2_SCK pin Input
pull pull-down mode
PB12 pin: slave chip select pin used in
SPI2_NSS pin Input
Push-pull pull-down mode.
The SPI3 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI3 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PC12 pin: Slave data Input line, used in
SPI3_MOSI pin Input
SPI3 bootloader Push-pull pull-down mode
PC11 pin: Slave data output line, used in
SPI3_MISO pin Output
Push-pull pull-down mode
PC10 pin: Slave clock line, used in Push-
SPI3_SCK pin Input
pull pull-down mode
PA15 pin: slave chip select pin used in
SPI3_NSS pin Input
Push-pull pull-down mode.

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Table 54. STM32F401xB(C) configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

USB OTG FS configured in forced device

USB Enabled
mode
USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
DFU bootloader USB_DP pin
No external Pull-up resistor is required
This timer is used to determine the value of
the HSE. Once the HSE frequency is
TIM11 Enabled
determined, the system clock is configured
to 60 MHz using PLL and HSE.

The system clock is derived from the embedded internal high-speed RC for USARTx, I2Cx
and SPIx bootloaders. This internal clock is also used for CAN and DFU (USB FS Device)
but only for the selection phase. An external clock multiple of 1 MHz (between 4 and
26 MHz) is required for CAN and DFU bootloader execution after the selection phase.

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27.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 30. Bootloader selection for STM32F401xB(C)

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110/307 AN2606 Rev 36

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27.3 Bootloader version

The following table lists the STM32F401xB(C) devices bootloader version.

Table 55. STM32F401xB(C) bootloader versions

Bootloader
version Description Known limitations
number

After executing Go command (jump to user code)

the bootloader resets AHB1ENR value to 0x0000
V13.0 Initial bootloader version
0000 and thus CCM RAM, when present, is not
active (shall be re-enabled by user code at startup)

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28 STM32F401xD(E) devices bootloader

28.1 Bootloader configuration

The STM32F401xD(E) bootloader is activated by applying pattern1 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 56. STM32F401xD(E) configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment
The system clock frequency is 60 MHz
using the PLL.
The HSI clock source is used at startup
(interface detection phase) and when
HSI enabled
USART or SPI or I2C interface is selected
(once DFU bootloader is selected, the clock
source will be derived from the external
crystal).
The system clock frequency is 60 MHz.
RCC The HSE clock source is used only when
the DFU (USB FS Device) interface is
HSE enabled selected.
The external clock must provide a
frequency multiple of 1 MHz and ranging
from 4 MHz to 26 MHz.
The Clock Security System (CSS) interrupt
is enabled for the DFU bootloader. Any
-
failure (or removal) of the external clock
Common to all
generates system reset.
bootloaders
12 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware
29 Kbyte starting from address
System memory - 0x1FFF0000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
Voltage range is set to [1.62 V, 2.1 V]. In
this range internal Flash write operations
are allowed only in byte format (Half-Word,
Power - Word and Double-Word operations are not
allowed). The voltage range can be
configured in run time using bootloader
commands.

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Table 56. STM32F401xD(E) configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment
Once initialized the USART1 configuration
USART1 Enabled
USART1 is: 8-bits, even parity and 1 Stop bit
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration
USART2 Enabled
USART2 is: 8-bits, even parity and 1 Stop bit
bootloader USART2_RX pin Input PD6 pin: USART2 in reception mode
USART2_TX pin Output PD5 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
The I2C1 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111001x (where x = 0 for write
I2C1 bootloader and x = 1 for read)
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.
The I2C2 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C2 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111001x (where x = 0 for write
I2C2 bootloader and x = 1 for read)
PB10 pin: clock line is used in open-drain
I2C2_SCL pin Input/Output
mode.
PB3 pin: data line is used in open-drain
I2C2_SDA pin Input/Output
mode.
The I2C3 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C3 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111001x (where x = 0 for write
I2C3 bootloader and x = 1 for read)
PA8 pin: clock line is used in open-drain
I2C3_SCL pin Input/Output
mode.
PB4 pin: data line is used in open-drain
I2C3_SDA pin Input/Output
mode.

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Table 56. STM32F401xD(E) configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment
The SPI1 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI1 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PA7 pin: Slave data Input line, used in
SPI1_MOSI pin Input
SPI1 bootloader Push-pull pull-down mode
PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
Push-pull pull-down mode
PA5 pin: Slave clock line, used in Push-pull
SPI1_SCK pin Input
pull-down mode
PA4 pin: slave chip select pin used in Push-
SPI1_NSS pin Input
pull pull-down mode.
The SPI2 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI2 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PB15 pin: Slave data Input line, used in
SPI2_MOSI pin Input
SPI2 bootloader Push-pull pull-down mode
PB14 pin: Slave data output line, used in
SPI2_MISO pin Output
Push-pull pull-down mode
PB13 pin: Slave clock line, used in Push-
SPI2_SCK pin Input
pull pull-down mode
PB12 pin: slave chip select pin used in
SPI2_NSS pin Input
Push-pull pull-down mode.
The SPI3 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI3 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PC12 pin: Slave data Input line, used in
SPI3_MOSI pin Input
SPI3 bootloader Push-pull pull-down mode
PC11 pin: Slave data output line, used in
SPI3_MISO pin Output
Push-pull pull-down mode
PC10 pin: Slave clock line, used in Push-
SPI3_SCK pin Input
pull pull-down mode
PA15 pin: slave chip select pin used in
SPI3_NSS pin Input
Push-pull pull-down mode.
USB OTG FS configured in forced device
USB Enabled
mode
USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
DFU bootloader USB_DP pin
No external Pull-up resistor is required
This timer is used to determine the value of
the HSE. Once the HSE frequency is
TIM11 Enabled
determined, the system clock is configured
to 60 MHz using PLL and HSE.

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The system clock is derived from the embedded internal high-speed RC for USARTx, I2Cx
and SPIx bootloaders. This internal clock is also used for DFU (USB FS Device) but only for
the selection phase. An external clock multiple of 1 MHz (between 4 and 26 MHz) is
required for DFU bootloader execution after the selection phase.

28.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 31. Bootloader selection for STM32F401xD(E)

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28.3 Bootloader version

The following table lists the STM32F401xD(E) devices bootloader version.

Table 57. STM32F401xD(E) bootloader versions

Bootloader
version Description Known limitations
number

After executing Go command (jump to user code)

the bootloader resets AHB1ENR value to 0x0000
V13.1 Initial bootloader version
0000 and thus CCM RAM, when present, is not
active (shall be re-enabled by user code at startup)

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AN2606 STM32F410xx devices bootloader

29 STM32F410xx devices bootloader

29.1 Bootloader configuration

The STM32F410xx bootloader is activated by applying pattern1 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 58. STM32F410xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The HSI is used at startup as clock source

RCC HSI enabled for system clock configured to 60 MHz and
for USART and I2C bootloader operation.
5 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware
29 Kbyte starting from address
System memory - 0x1FFF0000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
Common to all value. It is periodically refreshed to
IWDG -
bootloaders prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
The voltage range is [1.8V, 3.6V]
In this range:
- Flash wait states 3.
Power - - System clock Frequency 60 MHz.
- ART Accelerator enabled.
- Flash write operation by byte (refer to
bootloader memory management section
for more information).
Once initialized the USART1 configuration
USART1 Enabled
is: 8-bits, even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration
USART2 Enabled
is: 8-bits, even parity and 1 Stop bit
USART2
bootloader USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Used to automatically detect the serial
USARTx
SysTick timer Enabled baud rate from the host for USARTx
bootloaders bootloaders.

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Table 58. STM32F410xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C1 configuration is:

I2C speed: up to 400 KHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b1000111x (where x = 0 for
write and x = 1 for read)
I2C1 bootloader
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.
The I2C2 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C2 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b1000111x (where x = 0 for
write and x = 1 for read)
I2C2 bootloader
PB10 pin: clock line is used in open-drain
I2C2_SCL pin Input/Output
mode.
PB11 pin: data line is used in open-drain
I2C2_SDA pin Input/Output
mode.
The I2C4 configuration is:
I2C speed: up to 1 MHz, 7-bit address,
I2C4 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b1000111x (where x = 0 for
write and x = 1 for read)
PB15 pin: clock line is used in open-drain
I2C4 bootloader mode for STM32F410Cx/Rx devices.
I2C4_SCL pin Input/Output
PB10 pin: clock line is used in open-drain
mode for STM32F410Tx devices.
PB14 pin: data line is used in open-drain
mode for STM32F410Cx/Rx devices.
I2C4_SDA pin Input/Output
PB3 pin: data line is used in open-drain
mode for STM32F410Tx devices.

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Table 58. STM32F410xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI1 configuration is:

SPI1 Enabled Slave mode, Full Duplex, 8-bit MSB,
Speed up to 8MHz, Polarity: CPOL Low,
CPHA Low, NSS hardware.
PA7 pin: Slave data Input line, used in
Push-pull pull-down mode for
STM32F410Cx/Rx devices.
SPI1_MOSI pin Input
PB5 pin: Slave data Input line, used in
Push-pull pull-down mode for
STM32F410Tx devices.
PA6 pin: Slave data output line, used in
Push-pull pull-down mode for
SPI1 bootloader
STM32F410Cx/Rx devices.
SPI1_MISO pin Output
PB4 pin: Slave data output line, used in
Push-pull pull-down mode for
STM32F410Tx devices.
PA5 pin: Slave clock line, used in Push-
SPI1_SCK pin Input
pull pull-down mode.
PA4 pin: slave chip select pin used in
Push-pull pull-up mode for
STM32F410Cx/Rx devices.
SPI1_NSS pin Input
PA15 pin: slave chip select pin used in
Push-pull pull-up mode for STM32F410Tx
devices.
The SPI2 configuration is:
Slave mode, Full Duplex, 8-bit MSB,
SPI2 Enabled
Speed up to 8MHz, Polarity: CPOL Low,
CPHA Low, NSS hardware.
PC3 pin: Slave data Input line, used in
SPI2_MOSI pin Input
Push-pull pull-down mode
SPI2 bootloader
PC2 pin: Slave data output line, used in
SPI2_MISO pin Output
Push-pull pull-down mode
PB13 pin: Slave clock line, used in Push-
SPI2_SCK pin Input
pull pull-down mode
PB12 pin: slave chip select pin used in
SPI2_NSS pin Input
Push-pull pull-up mode.

The system clock is derived from the embedded internal high-speed RC for all bootloader
interfaces. No external quartz is required for bootloader operations.

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29.2 Bootloader selection

The Figure 32 shows the bootloader selection mechanism.

Figure 32.Bootloader V11.x selection for STM32F410xx

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29.3 Bootloader version

The following table lists the STM32F410xx devices bootloader V11.x versions.

Table 59.STM32F410xx bootloader V11.x versions

Bootloader
version Description Known limitations
number

After executing Go command (jump to user code)

the bootloader resets AHB1ENR value to 0x0000
V11.0 Initial bootloader version 0000 and thus CCM RAM, when present, is not
active (shall be re-enabled by user code at
startup)
After executing Go command (jump to user code)
the bootloader resets AHB1ENR value to 0x0000
Support I2C4 and SPI1 for
V11.1 0000 and thus CCM RAM, when present, is not
STM32F410Tx devices.
active (shall be re-enabled by user code at
startup)

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30 STM32F411xx devices bootloader

30.1 Bootloader configuration

The STM32F411xx bootloader is activated by applying pattern1 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 60. STM32F411xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 60 MHz

using the PLL.
The HSI clock source is used at startup
HSI enabled (interface detection phase) and when
USART or SPI or I2C interface is selected
(once DFU bootloader is selected, the clock
source will be derived from the external
crystal).
The system clock frequency is 60 MHz.
RCC The HSE clock source is used only when
the DFU (USB FS Device) interface is
HSE enabled selected.
The external clock must provide a fre-
quency multiple of 1 MHz and ranging from
4 MHz to 26 MHz.
The Clock Security System (CSS) interrupt
is enabled for the DFU bootloader. Any fail-
-
Common to all ure (or removal) of the external clock gener-
bootloaders ates system reset.
12 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware
29 Kbyte starting from address
System memory - 0x1FFF0000, contain the bootloader firm-
ware
The independent watchdog (IWDG) pres-
caler is configured to its maximum value. It
IWDG - is periodically refreshed to prevent watch-
dog reset (in case the hardware IWDG
option was previously enabled by the user).
Voltage range is set to [1.62 V, 2.1 V]. In
this range internal Flash write operations
are allowed only in byte format (Half-Word,
Power - Word and Double-Word operations are not
allowed). The voltage range can be config-
ured in run time using bootloader com-
mands.

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Table 60. STM32F411xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART1 configuration

USART1 Enabled
is: 8-bits, even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration
USART2 Enabled
is: 8-bits, even parity and 1 Stop bit
USART2
bootloader USART2_RX pin Input PD6 pin: USART2 in reception mode
USART2_TX pin Output PD5 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
The I2C1 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111001x (where x = 0 for write
and x = 1 for read)
I2C1 bootloader
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.
The I2C2 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C2 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111001x (where x = 0 for write
and x = 1 for read)
I2C2 bootloader
PB10 pin: clock line is used in open-drain
I2C2_SCL pin Input/Output
mode.
PB3 pin: data line is used in open-drain
I2C2_SDA pin Input/Output
mode.
The I2C3 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C3 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111001x (where x = 0 for write
and x = 1 for read)
I2C3 bootloader
PA8 pin: clock line is used in open-drain
I2C3_SCL pin Input/Output
mode.
PB4 pin: data line is used in open-drain
I2C3_SDA pin Input/Output
mode.

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Table 60. STM32F411xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI1 configuration is:

Slave mode, Full Duplex, 8-bit MSB, Speed
SPI1 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PA7 pin: Slave data Input line, used in
SPI1_MOSI pin Input
Push-pull pull-down mode
SPI1 bootloader
PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
Push-pull pull-down mode
PA5 pin: Slave clock line, used in Push-pull
SPI1_SCK pin Input
pull-down mode
PA4 pin: slave chip select pin used in Push-
SPI1_NSS pin Input
pull pull-down mode.
The SPI2 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI2 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PB15 pin: Slave data Input line, used in
SPI2_MOSI pin Input
Push-pull pull-down mode
SPI2 bootloader
PB14 pin: Slave data output line, used in
SPI2_MISO pin Output
Push-pull pull-down mode
PB13 pin: Slave clock line, used in Push-
SPI2_SCK pin Input
pull pull-down mode
PB12 pin: slave chip select pin used in
SPI2_NSS pin Input
Push-pull pull-down mode.
The SPI3 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI3 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PC12 pin: Slave data Input line, used in
SPI3_MOSI pin Input
Push-pull pull-down mode
SPI3 bootloader
PC11 pin: Slave data output line, used in
SPI3_MISO pin Output
Push-pull pull-down mode
PC10 pin: Slave clock line, used in Push-
SPI3_SCK pin Input
pull pull-down mode
PA15 pin: slave chip select pin used in
SPI3_NSS pin Input
Push-pull pull-down mode.

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Table 60. STM32F411xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

USB OTG FS configured in forced device

USB Enabled
mode
USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
DFU bootloader USB_DP pin
No external Pull-up resistor is required
This timer is used to determine the value of
the HSE. Once the HSE frequency is
TIM11 Enabled
determined, the system clock is configured
to 60 MHz using PLL and HSE.

The system clock is derived from the embedded internal high-speed RC for USARTx, I2Cx
and SPIx bootloaders. This internal clock is also used for DFU (USB FS Device) but only for
the selection phase. An external clock multiple of 1 MHz (between 4 and 26 MHz) is
required for DFU bootloader execution after the selection phase.

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30.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 33. Bootloader selection for STM32F411xx

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126/307 AN2606 Rev 36

AN2606 STM32F411xx devices bootloader

30.3 Bootloader version

The following table lists the STM32F411xx devices bootloader version.

Table 61. STM32F411xx bootloader versions

Bootloader
version num- Description Known limitations
ber

After executing Go command (jump to user code) the

bootloader resets AHB1ENR value to 0x0000 0000
V13.0 Initial bootloader version
and thus CCM RAM, when present, is not active
(shall be re-enabled by user code at startup)

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31 STM32F412xx devices bootloader

31.1 Bootloader configuration

The STM32F412xx bootloader is activated by applying pattern1 (described in Table 2:
Bootloader activation patterns). The table shows the hardware resources used by this
bootloader.

Table 62.STM32F412xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The HSI is used at startup as clock source

HSI enabled for system clock configured to 60 MHz and
for USART and I2C bootloader operation.
The HSE is used only when the CAN or the
DFU (USB FS Device) interfaces are
selected. In this case the system clock
HSE enabled configured to 60 MHz with HSE as clock
RCC
source.
The HSE frequency must be multiple of 1
MHz and ranging from 4 MHz to 26 MHz.
The Clock Security System (CSS) interrupt
is enabled for the CAN and DFU
-
bootloaders. Any failure (or removal) of the
external clock generates system reset.
16 Kbyte starting from address
RAM - 0x20000000 are used by the bootloader
Common to all firmware
bootloaders 29 Kbyte starting from address
System memory - 0x1FFF0000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
The voltage range is [1.8V, 3.6V]
In this range:
- Flash wait states 3.
- System clock Frequency 60 MHz.
Power -
- ART Accelerator enabled.
- Flash write operation by byte (refer to
bootloader memory management section
for more information).

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Table 62.STM32F412xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART1 configuration

USART1 Enabled
is: 8-bits, even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration
USART2 Enabled
is: 8-bits, even parity and 1 Stop bit
USART2
bootloader USART2_RX pin Input PD6 pin: USART2 in reception mode
USART2_TX pin Output PD5 pin: USART2 in transmission mode
Once initialized the USART3 configuration
USART3 Enabled
is: 8-bits, even parity and 1 Stop bit
USART3
bootloader USART3_RX pin Input PB11 pin: USART3 in reception mode
USART3_TX pin Output PB10 pin: USART3 in transmission mode
USARTx Used to automatically detect the serial baud
SysTick timer Enabled
bootloaders rate from the host for USARTx bootloaders.
Once initialized the CAN2 configuration is:
Baudrate 125 kbps, 11-bit identifier.
Note: CAN1 is clocked during CAN2
CAN2 Enabled
bootloader execution because CAN1
CAN2 bootloader manages the communication between
CAN2 and SRAM.
CAN2_RX pin Input PB5 pin: CAN2 in reception mode
CAN2_TX pin Output PB13 pin: CAN2 in transmission mode
The I2C1 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1000110x (where x
I2C1 bootloader = 0 for write and x = 1 for read)
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.
The I2C2 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C2 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1000110x (where x
I2C2 bootloader = 0 for write and x = 1 for read)
PF1 pin: clock line is used in open-drain
I2C2_SCL pin Input/Output
mode.
PF0 pin: data line is used in open-drain
I2C2_SDA pin Input/Output
mode.

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Table 62.STM32F412xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C3 configuration is:

I2C speed: up to 400 KHz, 7-bit address,
I2C3 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1000110x (where x
I2C3 bootloader = 0 for write and x = 1 for read)
PA8 pin: clock line is used in open-drain
I2C3_SCL pin Input/Output
mode.
PB4 pin: data line is used in open-drain
I2C3_SDA pin Input/Output
mode.
The I2C4 configuration is:
I2C speed: up to 1 MHz, 7-bit address,
I2C4 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1000110x (where x
I2C4 bootloader = 0 for write and x = 1 for read)
PB15 pin: clock line is used in open-drain
I2C4_SCL pin Input/Output
mode.
PB14 pin: data line is used in open-drain
I2C4_SDA pin Input/Output
mode.
The SPI1 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI1 Enabled
up to 8MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PA7 pin: Slave data Input line, used in
SPI1_MOSI pin Input
Push-pull pull-down mode
SPI1 bootloader
PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
Push-pull pull-down mode
PA5 pin: Slave clock line, used in Push-pull
SPI1_SCK pin Input
pull-down mode
PA4 pin: slave chip select pin used in Push-
SPI1_NSS pin Input
pull pull-up mode.
The SPI3 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI3 Enabled
up to 8MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PC12 pin: Slave data Input line, used in
SPI3_MOSI pin Input
Push-pull pull-down mode
SPI3 bootloader
PC11 pin: Slave data output line, used in
SPI3_MISO pin Output
Push-pull pull-down mode
PC10 pin: Slave clock line, used in Push-
SPI3_SCK pin Input
pull pull-down mode
PA15 pin: slave chip select pin used in
SPI3_NSS pin Input
Push-pull pull-up mode.

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Table 62.STM32F412xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI4 configuration is:

Slave mode, Full Duplex, 8-bit MSB, Speed
SPI4 Enabled
up to 8MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PE14 pin: Slave data Input line, used in
SPI4_MOSI pin Input
Push-pull pull-down mode
SPI4 bootloader
PE13 pin: Slave data output line, used in
SPI4_MISO pin Output
Push-pull pull-down mode
PE12 pin: Slave clock line, used in Push-
SP4_SCK pin Input
pull pull-down mode
PE11 pin: slave chip select pin used in
SPI4_NSS pin Input
Push-pull pull-up mode.
USB OTG FS configured in forced device
USB Enabled
mode

DFU bootloader USB_DM pin PA11 pin: USB DM line.

Input/Output PA12 pin: USB DP line
USB_DP pin
No external Pull-Up resistor is required.
This timer is used to determine the value of
CAN2 and DFU the HSE. Once HSE frequency is
TIM11 Enabled
bootloaders determined, the system clock is configured
to 60 MHz using PLL and HSE.

The system clock is derived from the embedded internal high-speed RC for USARTx and
I2Cx bootloaders. This internal clock is also used for CAN and DFU (USB FS Device) but
only for the selection phase. An external clock multiple of 1 MHz (between 4 and 26 MHz) is
required for CAN and DFU bootloader execution after the selection phase.

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31.2 Bootloader selection

The Figure 34 shows the bootloader selection mechanism.

Figure 34.Bootloader V9.x selection for STM32F412xx

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31.3 Bootloader version

The following table lists the STM32F412xx devices bootloader V9.x versions.

Table 63.STM32F412xx bootloader V9.x versions

Bootloader
version Description Known limitations
number

After executing Go command (jump to user code)

the bootloader resets AHB1ENR value to 0x0000
V9.0 Initial bootloader version 0000 and thus CCM RAM, when present, is not
active (shall be re-enabled by user code at
startup)
After executing Go command (jump to user code)
the bootloader resets AHB1ENR value to 0x0000
V9.1 Fix USART3 interface pinout 0000 and thus CCM RAM, when present, is not
active (shall be re-enabled by user code at
startup)

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32 STM32F413xx/423xx devices bootloader

32.1 Bootloader configuration

The STM32F413xx/423xx bootloader is activated by applying pattern1 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 64. STM32F413xx/423xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The HSI is used at startup as clock

source for system clock configured to
HSI enabled
60 MHz and for USART and I2C
bootloader operation.
The HSE is used only when the CAN
or the DFU (USB FS Device)
interfaces are selected. In this case
the system clock configured to 60 MHz
HSE enabled
RCC with HSE as clock source.
The HSE frequency must be multiple
of 1 MHz and ranging from 4 MHz to
26 MHz.
The Clock Security System (CSS)
interrupt is enabled for the CAN and
- DFU bootloaders. Any failure (or
removal) of the external clock
generates system reset.
16 Kbyte starting from address
Common to all RAM - 0x20000000 are used by the
bootloaders bootloader firmware
60 Kbyte starting from address
System memory - 0x1FF00000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
The voltage range is [1.8V, 3.6V]
In this range:
– Flash wait states 4.
Power - – System clock Frequency 60 MHz.
– ART Accelerator enabled.
– Flash write operation by byte (refer
to Bootloader memory management
for more information).

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Table 64. STM32F413xx/423xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART1

USART1 Enabled configuration is: 8-bits, even parity and
USART1 1 Stop bit
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
PA9 pin: USART1 in transmission
USART1_TX pin Output
mode
Once initialized the USART2
USART2 Enabled configuration is: 8-bits, even parity and
USART2 1 Stop bit
bootloader USART2_RX pin Input PD6 pin: USART2 in reception mode
PD5 pin: USART2 in transmission
USART2_TX pin Output
mode
Once initialized the USART3
USART3 Enabled configuration is: 8-bits, even parity and
USART3 1 Stop bit
bootloader USART3_RX pin Input PB11 pin: USART3 in reception mode
PB10 pin: USART3 in transmission
USART3_TX pin Output
mode
Used to automatically detect the serial
USARTx
SysTick timer Enabled baud rate from the host for USARTx
bootloaders bootloaders.
Once initialized the CAN2
configuration is: Baudrate 125 kbps,
11-bit identifier.
CAN2 Enabled Note: CAN1 is clocked during CAN2
CAN2 bootloader bootloader execution because CAN1
manages the communication between
CAN2 and SRAM.
CAN2_RX pin Input PB5 pin: CAN2 in reception mode
CAN2_TX pin Output PB13 pin: CAN2 in transmission mode
The I2C1 configuration is:
I2C speed: up to 400 KHz, 7-bit
address, slave mode, analog filter ON.
I2C1 Enabled
Slave 7-bit address: 0b1001010x
(where x = 0 for write and x = 1 for
I2C1 bootloader read)
PB6 pin: clock line is used in open-
I2C1_SCL pin Input/Output
drain mode.
PB7 pin: data line is used in open-
I2C1_SDA pin Input/Output
drain mode.

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Table 64. STM32F413xx/423xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C2 configuration is:

I2C speed: up to 400 KHz, 7-bit
address, slave mode, analog filter ON.
I2C2 Enabled
Slave 7-bit address: 0b1001010x
(where x = 0 for write and x = 1 for
I2C2 bootloader read)
PF1 pin: clock line is used in open-
I2C2_SCL pin Input/Output
drain mode.
PF0 pin: data line is used in open-
I2C2_SDA pin Input/Output
drain mode.
The I2C3 configuration is:
I2C speed: up to 400 KHz, 7-bit
address, slave mode, analog filter ON.
I2C3 Enabled
Slave 7-bit address: 0b1001010x
(where x = 0 for write and x = 1 for
I2C3 bootloader read)
PA8 pin: clock line is used in open-
I2C3_SCL pin Input/Output
drain mode.
PB4 pin: data line is used in open-
I2C3_SDA pin Input/Output
drain mode.
The I2C4 configuration is:
I2C speed: up to 1 MHz, 7-bit address,
slave mode, analog filter ON.
I2C4 Enabled
Slave 7-bit address: 0b1001010x
(where x = 0 for write and x = 1 for
I2C4 bootloader read)
PB15 pin: clock line is used in open-
I2C4_SCL pin Input/Output
drain mode.
PB14 pin: data line is used in open-
I2C4_SDA pin Input/Output
drain mode.
The SPI1 configuration is:
– Slave mode
– Full Duplex
SPI1 Enabled
– 8-bit MSB, speed up to 8MHz
– Polarity: CPOL Low, CPHA Low,
NSS hardware.
PA7 pin: Slave data Input line, used in
SPI1 bootloader SPI1_MOSI pin Input
Push-pull pull-down mode
PA6 pin: Slave data output line, used
SPI1_MISO pin Output
in Push-pull pull-down mode
PA5 pin: Slave clock line, used in
SPI1_SCK pin Input
Push-pull pull-down mode
PA4 pin: slave chip select pin used in
SPI1_NSS pin Input
Push-pull pull-up mode.

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Table 64. STM32F413xx/423xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI3 configuration is:

– Slave mode
– Full Duplex
SPI3 Enabled
– 8-bit MSB, speed up to 8MHz
– Polarity: CPOL Low, CPHA Low,
NSS hardware.
PC12 pin: Slave data Input line, used
SPI3 bootloader SPI3_MOSI pin Input
in Push-pull pull-down mode
PC11 pin: Slave data output line, used
SPI3_MISO pin Output
in Push-pull pull-down mode
PC10 pin: Slave clock line, used in
SPI3_SCK pin Input
Push-pull pull-down mode
PA15 pin: slave chip select pin used in
SPI3_NSS pin Input
Push-pull pull-up mode.
The SPI4 configuration is:
– Slave mode
– Full Duplex
SPI4 Enabled
– 8-bit MSB, speed up to 8MHz
– Polarity: CPOL Low, CPHA Low,
NSS hardware.
PE14 pin: Slave data Input line, used
SPI4 bootloader SPI4_MOSI pin Input
in Push-pull pull-down mode
PE13 pin: Slave data output line, used
SPI4_MISO pin Output
in Push-pull pull-down mode
PE12 pin: Slave clock line, used in
SP4_SCK pin Input
Push-pull pull-down mode
PE11 pin: slave chip select pin used in
SPI4_NSS pin Input
Push-pull pull-up mode.
USB OTG FS configured in forced
USB Enabled
device mode
USB_DM pin PA11 pin: USB DM line.
DFU bootloader
Input/Output PA12 pin: USB DP line
USB_DP pin No external Pull-Up resistor is
required.
This timer is used to determine the
value of the HSE. Once HSE
CAN2 and DFU
TIM11 Enabled frequency is determined, the system
bootloaders
clock is configured to 60 MHz using
PLL and HSE.

The system clock is derived from the embedded internal high-speed RC for USARTx and
I2Cx bootloaders. This internal clock is also used for CAN and DFU (USB FS Device) but
only for the selection phase. An external clock multiple of 1 MHz (between 4 and 26 MHz) is
required for CAN and DFU bootloader execution after the selection phase.

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32.2 Bootloader selection

The Figure 35 shows the bootloader selection mechanism.

Figure 35.Bootloader V9.x selection for STM32F413xx/423xx

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138/307 AN2606 Rev 36

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32.3 Bootloader version

The following table lists the STM32F413xx/423xx devices bootloader V9.x versions.

Table 65.STM32F413xx/423xx bootloader V9.x versions

Bootloader
version Description Known limitations
number

After executing Go command (jump to user code)

the bootloader resets AHB1ENR value to 0x0000
V9.0 Initial bootloader version 0000 and thus CCM RAM, when present, is not
active (shall be re-enabled by user code at
startup)

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33 STM32F42xxx/43xxx devices bootloader

33.1 Bootloader V7.x

33.1.1 Bootloader configuration

The STM32F42xxx/43xxx bootloader is activated by applying pattern5 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 66. STM32F42xxx/43xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 24 MHz

using the PLL.
The HSI clock source is used at startup
(interface detection phase) and when
HSI enabled
USART or I2C interfaces are selected
(once CAN or DFU bootloader is selected,
the clock source will be derived from the
external crystal).
The system clock frequency is 60 MHz.
RCC The HSE clock source is used only when
the CAN or the DFU (USB FS Device)
HSE enabled interfaces are selected.
The external clock must provide a
frequency multiple of 1 MHz and ranging
from 4 MHz to 26 MHz.
The Clock Security System (CSS) interrupt
is enabled for the CAN and DFU
-
bootloaders. Any failure (or removal) of the
Common to all external clock generates system reset.
bootloaders
8 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware
29 Kbyte starting from address
System memory - 0x1FFF0000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
Voltage range is set to [1.62 V, 2.1 V]. In
this range internal Flash write operations
are allowed only in byte format (Half-Word,
Power - Word and Double-Word operations are not
allowed). The voltage range can be
configured in run time using bootloader
commands.

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Table 66. STM32F42xxx/43xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART1 configuration

USART1 Enabled
is: 8 bits, even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART3 configuration
USART3 Enabled
USART3 is: 8 bits, even parity and 1 Stop bit
bootloader
USART3_RX pin Input PB11 pin: USART3 in reception mode
(on PB10/PB11)
USART3_TX pin Output PB10 pin: USART3 in transmission mode
Once initialized the USART3 configuration
USART3 Enabled
USART3 is: 8 bits, even parity and 1 Stop bit
bootloader
USART3_RX pin Input PC11 pin: USART3 in reception mode
(on PC10/PC11)
USART3_TX pin Output PC10 pin: USART3 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
Once initialized the CAN2 configuration is:
Baudrate 125 kbps, 11-bit identifier.
CAN2 Enabled Note: CAN1 is clocked during CAN2
bootloader execution because CAN1
CAN2 bootloader manages the communication between
CAN2 and SRAM.
CAN2_RX pin Input PB5 pin: CAN2 in reception mode
CAN2_TX pin Output PB13 pin: CAN2 in transmission mode
The I2C1 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b0111000x (where x = 0 for write
and x = 1 for read).
I2C1 bootloader
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB9 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.
USB OTG FS configured in forced device
USB Enabled
mode
DFU bootloader USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
USB_DP pin
No external Pull-up resistor is required
This timer is used to determine the value of
CAN2 and DFU the HSE. Once the HSE frequency is
TIM11 Enabled
bootloaders determined, the system clock is configured
to 60 MHz using PLL and HSE.

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The system clock is derived from the embedded internal high-speed RC for USARTx and
I2Cx bootloaders. This internal clock is also used for CAN and DFU (USB FS Device) but
only for the selection phase. An external clock multiple of 1 MHz (between 4 and 26 MHz) is
required for CAN and DFU bootloader execution after the selection phase.

33.1.2 Bootloader selection

The Figure 36 and Figure 37 show the bootloader selection mechanism.

Figure 36. Dual Bank Boot Implementation for STM32F42xxx/43xxx Bootloader V7.x

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Figure 37. Bootloader V7.x selection for STM32F42xxx/43xxx

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33.1.3 Bootloader version

The following table lists the STM32F42xxx/43xxx devices bootloader V7.x versions.

Table 67. STM32F42xxx/43xxx bootloader V7.x versions

Bootloader
version Description Known limitations
number

For the CAN interface, the Write Unprotect

command is not functional. Instead you can use
Write Memory command and write directly to the
option bytes in order to disable the write protection.
For the USB DFU interface, in Dual Bank mode,
the Erase operation is not functional for the second
V7.0 Initial bootloader version bank. Instead you can return to Single Bank mode,
erase desired sector(s) and then reactivate the
Dual Bank mode.
After executing Go command (jump to user code)
the bootloader resets AHB1ENR value to 0x0000
0000 and thus CCM RAM, when present, is not
active (shall be re-enabled by user code at startup)

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33.2 Bootloader V9.x

33.2.1 Bootloader configuration

The STM32F42xxx/43xxx bootloader is activated by applying pattern5 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 68. STM32F42xxx/43xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 60 MHz using the PLL.

The HSI clock source is used at startup (interface
detection phase) and when USART or SPI or I2C
HSI enabled
interfaces are selected (once CAN or DFU bootloader
is selected, the clock source will be derived from the
external crystal).
The system clock frequency is 60 MHz.
RCC The HSE clock source is used only when the CAN or
HSE enabled the DFU (USB FS Device) interfaces are selected.
The external clock must provide a frequency multiple
of 1 MHz and ranging from 4 MHz to 26 MHz.
The Clock Security System (CSS) interrupt is enabled
for the CAN and DFU bootloaders. Any failure (or
-
removal) of the external clock generates system
Common to all reset.
bootloaders 12 Kbyte starting from address 0x20000000 are used
RAM -
by the bootloader firmware
29 Kbyte starting from address 0x1FFF0000, contain
System memory -
the bootloader firmware
The independent watchdog (IWDG) prescaler is
configured to its maximum value. It is periodically
IWDG - refreshed to prevent watchdog reset (in case the
hardware IWDG option was previously enabled by
the user).
Voltage range is set to [1.62 V, 2.1 V]. In this range
internal Flash write operations are allowed only in
byte format (Half-Word, Word and Double-Word
Power -
operations are not allowed). The voltage range can
be configured in run time using bootloader
commands.
Once initialized the USART1 configuration is: 8-bits,
USART1 Enabled
even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode

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Table 68. STM32F42xxx/43xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART3 configuration is: 8-bits,

USART3 USART3 Enabled
even parity and 1 Stop bit
bootloader (on
USART3_RX pin Input PB11 pin: USART3 in reception mode
PB10/PB11)
USART3_TX pin Output PB10 pin: USART3 in transmission mode
Once initialized the USART3 configuration is: 8-bits,
USART3 USART3 Enabled
even parity and 1 Stop bit
bootloader (on
USART3_RX pin Input PC11 pin: USART3 in reception mode
PC10/PC11)
USART3_TX pin Output PC10 pin: USART3 in transmission mode
USARTx Used to automatically detect the serial baud rate from
SysTick timer Enabled
bootloaders the host for USARTx bootloaders.
Once initialized the CAN2 configuration is: Baudrate
125 kbps, 11-bit identifier.
CAN2 Enabled Note: CAN1 is clocked during CAN2 bootloader
execution because CAN1 manages the
CAN2 bootloader
communication between CAN2 and SRAM.
CAN2_RX pin Input PB5 pin: CAN2 in reception mode
CAN2_TX pin Output PB13 pin: CAN2 in transmission mode
The I2C1 configuration is:
I2C speed: up to 400 KHz, 7-bit address, slave mode,
I2C1 Enabled
analog filter ON. Slave 7-bit address: 0b0111000x
I2C1 bootloader (where x = 0 for write and x = 1 for read).
I2C1_SCL pin Input/Output PB6 pin: clock line is used in open-drain mode.
I2C1_SDA pin Input/Output PB9 pin: data line is used in open-drain mode.
The I2C2 configuration is:
I2C speed: up to 400 KHz, 7-bit address, slave mode,
I2C2 Enabled
analog filter ON. Slave 7-bit address: 0b0111000x
I2C2 bootloader (where x = 0 for write and x = 1 for read).
I2C2_SCL pin Input/Output PF1 pin: clock line is used in open-drain mode.
I2C2_SDA pin Input/Output PF0 pin: data line is used in open-drain mode.
The I2C3 configuration is:
I2C speed: up to 400 KHz, 7-bit address, slave mode,
I2C3 Enabled
analog filter ON. Slave 7-bit address: 0b0111000x
I2C3 bootloader (where x = 0 for write and x = 1 for read).
I2C3_SCL pin Input/Output PA8 pin: clock line is used in open-drain mode.
I2C3_SDA pin Input/Output PC9 pin: data line is used in open-drain mode.

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Table 68. STM32F42xxx/43xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI1 configuration is:

Slave mode, Full Duplex, -bit MSB, Speed up to 8
SPI1 Enabled
MHz, Polarity: CPOL Low, CPHA Low, NSS
hardware.
PA7 pin: Slave data Input line, used in Push-pull pull-
SPI1_MOSI pin Input
down mode
SPI1 bootloader
PA6 pin: Slave data output line, used in Push-pull
SPI1_MISO pin Output
pull-down mode
PA5 pin: Slave clock line, used in Push-pull pull-down
SPI1_SCK pin Input
mode
PA4 pin: slave chip select pin used in Push-pull pull-
SPI1_NSS pin Input
down mode.
The SPI2 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed up to 8
SPI2 Enabled
MHz, Polarity: CPOL Low, CPHA Low, NSS
hardware.
PI3 pin: Slave data Input line, used in Push-pull pull-
SPI2_MOSI pin Input
down mode
SPI2 bootloader
PI2 pin: Slave data output line, used in Push-pull pull-
SPI2_MISO pin Output
down mode
PI1 pin: Slave clock line, used in Push-pull pull-down
SPI2_SCK pin Input
mode
PI0 pin: slave chip select pin used in Push-pull pull-
SPI2_NSS pin Input
down mode.
The SPI4 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed up to 8
SPI4 Enabled
MHz, Polarity: CPOL Low, CPHA Low, NSS
hardware.
PE14 pin: Slave data Input line, used in Push-pull
SPI4_MOSI pin Input
pull-down mode
SPI4 bootloader
PE13 pin: Slave data output line, used in Push-pull
SPI4_MISO pin Output
pull-down mode
PE12 pin: Slave clock line, used in Push-pull pull-
SP4_SCK pin Input
down mode
PE11 pin: slave chip select pin used in Push-pull pull-
SPI4_NSS pin Input
down mode.
USB Enabled USB OTG FS configured in forced device mode
USB_DM pin PA11: USB DM line.
DFU bootloader
Input/Output PA12: USB DP line
USB_DP pin
No external Pull-up resistor is required
This timer is used to determine the value of the HSE.
CAN2 and DFU
TIM11 Enabled Once the HSE frequency is determined, the system
bootloaders
clock is configured to 60 MHz using PLL and HSE.

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The system clock is derived from the embedded internal high-speed RC for USARTx, I2Cx
and SPIx bootloaders. This internal clock is also used for CAN and DFU (USB FS Device)
but only for the selection phase. An external clock multiple of 1 MHz (between 4 and
26 MHz) is required for CAN and DFU bootloader execution after the selection phase.

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33.2.2 Bootloader selection

The Figure 38 and Figure 39 show the bootloader selection mechanism.

Figure 38. Dual Bank Boot Implementation for STM32F42xxx/43xxx bootloader V9.x

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Figure 39. Bootloader V9.x selection for STM32F42xxx/43xxx

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33.2.3 Bootloader version

The following table lists the STM32F42xxx/43xxx devices bootloader V9.x versions.

Table 69. STM32F42xxx/43xxx bootloader V9.x versions

Bootloader
version Description Known limitations
number

For the USB DFU interface, in Dual Bank mode,

This bootloader is an updated
the Erase operation is not functional for the
version of bootloader v7.0.
second bank. Instead you can return to Single
This new version of bootloader
Bank mode, erase desired sector(s) and then
supports I2C2, I2C3, SPI1, SPI2
reactivate the Dual Bank mode.
V9.0 and SPI4 interfaces.
The RAM used by this bootloader After executing Go command (jump to user code)
is increased from 8Kb to 12Kb. the bootloader resets AHB1ENR value to 0x0000
The ID of this bootloader is 0x90 0000 and thus CCM RAM, when present, is not
The connection time is increased. active (shall be re-enabled by user code at
startup)
For the CAN interface, the Write Unprotect
command is not functional. Instead you can use
This bootloader is an updated Write Memory command and write directly to the
version of bootloader v9.0. This option bytes in order to disable the write
new version implements the new protection.
I2C No-stretch commands (I2C For the USB DFU interface, in Dual Bank mode,
protocol v1.1) and the capability the Erase operation is not functional for the
V9.1 of disabling PcROP when RDP1 second bank. Instead you can return to Single
is enabled with Bank mode, erase desired sector(s) and then
ReadOutUnprotect command for reactivate the Dual Bank mode.
all protocols(USB, USART, CAN, After executing Go command (jump to user code)
I2C and SPI). The ID of this the bootloader resets AHB1ENR value to 0x0000
bootloader is 0x91 0000 and thus CCM RAM, when present, is not
active (shall be re-enabled by user code at
startup)

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34 STM32F446xx devices bootloader

34.1 Bootloader configuration

The STM32F446xx bootloader is activated by applying pattern1 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 70.STM32F446xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The HSI is used at startup as clock source

for system clock configured to 60 MHz and
HSI enabled
for USART, I2C and SPI bootloader
operation.
The HSE is used only when the CAN or the
DFU (USB FS Device) interfaces are
selected. In this case the system clock
RCC HSE enabled configured to 60 MHz with HSE as clock
source.
The HSE frequency must be multiple of
1 MHz and ranging from 4 MHz to 26 MHz.
The Clock Security System (CSS) interrupt
is enabled for the CAN and DFU
-
bootloaders. Any failure (or removal) of the
external clock generates system reset.
12 Kbyte starting from address
RAM - 0x20000000 are used by the bootloader
Common to all firmware
bootloaders
29 Kbyte starting from address
System memory - 0x1FFF0000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
The voltage range is [1.71 V, 3.6 V].
In this range:
- Flash wait states 3.
- System Clock 60 MHz.
Power -
- Prefetch disabled.
- Flash write operation by byte (refer to
section bootloader memory management
for more information).

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Table 70.STM32F446xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART1 configuration

USART1 Enabled
is: 8-bits, even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART3 configuration
USART3 USART3 Enabled
is: 8-bits, even parity and 1 Stop bit
bootloader (on
USART3_RX pin Input PB11 pin: USART3 in reception mode
PB10/PB11)
USART3_TX pin Output PB10 pin: USART3 in transmission mode
Once initialized the USART3 configuration
USART3 USART3 Enabled
is: 8-bits, even parity and 1 Stop bit
bootloader (on
USART3_RX pin Input PC11 pin: USART3 in reception mode
PC10/PC11)
USART3_TX pin Output PC10 pin: USART3 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
Once initialized the CAN2 configuration is:
Baudrate 125 kbps, 11-bit identifier.
CAN2 Enabled Note: CAN1 is clocked during CAN2
bootloader execution because in CAN1
CAN2 bootloader manages the communication between
CAN2 and SRAM.
CAN2_RX pin Input PB5 pin: CAN2 in reception mode
CAN2_TX pin Output PB13 pin: CAN2 in transmission mode
The I2C1 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b0111100x
I2C1 bootloader (where x = 0 for write and x = 1 for read)
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB9 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.
The I2C2 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C2 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b0111100x
I2C2 bootloader (where x = 0 for write and x = 1 for read)
PF1 pin: clock line is used in open-drain
I2C2_SCL pin Input/Output
mode.
PF0 pin: data line is used in open-drain
I2C2_SDA pin Input/Output
mode.

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Table 70.STM32F446xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C3 configuration is:

I2C speed: up to 400 KHz, 7-bit address,
I2C3 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b0111100x
I2C3 bootloader (where x = 0 for write and x = 1 for read)
PA8 pin: clock line is used in open-drain
I2C3_SCL pin Input/Output
mode.
PC9 pin: data line is used in open-drain
I2C3_SDA pin Input/Output
mode.
The SPI1 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI1 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PA7 pin: Slave data Input line, used in
SPI1_MOSI pin Input
Push-pull pull-down mode
SPI1 bootloader
PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
Push-pull pull-down mode
PA5 pin: Slave clock line, used in Push-pull
SPI1_SCK pin Input
pull-down mode
PA4 pin: slave chip select pin used in Push-
SPI1_NSS pin Input
pull pull-up mode.
The SPI2 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI2 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PB15 pin: Slave data Input line, used in
SPI2_MOSI pin Input
Push-pull pull-down mode
SPI2 bootloader
PB14 pin: Slave data output line, used in
SPI2_MISO pin Output
Push-pull pull-down mode
PC7 pin: Slave clock line, used in Push-pull
SPI2_SCK pin Input
pull-down mode
PB12 pin: slave chip select pin used in
SPI2_NSS pin Input
Push-pull pull-up mode.

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Table 70.STM32F446xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI4 configuration is:

Slave mode, Full Duplex, 8-bit MSB, Speed
SPI4 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PE14 pin: Slave data Input line, used in
SPI4_MOSI pin Input
Push-pull pull-down mode
SPI4 bootloader
PE13 pin: Slave data output line, used in
SPI4_MISO pin Output
Push-pull pull-down mode
PE12 pin: Slave clock line, used in Push-
SPI4_SCK pin Input
pull pull-down mode
PE11 pin: slave chip select pin used in
SPI4_NSS pin Input
Push-pull pull-up mode.
USB OTG FS configured in forced device
USB Enabled
mode

DFU bootloader USB_DM pin PA11: USB DM line.

Input/Output PA12: USB DP line
USB_DP pin
No external Pull-up resistor is required
This timer is used to determine the value of
CAN2 and DFU the HSE. Once the HSE frequency is
TIM17 Enabled
bootloaders determinated, the system clock is
configured to 60 MHz using PLL and HSE.

The system clock is derived from the embedded internal high-speed RC for USARTx and
I2Cx bootloaders. This internal clock is also used for CAN and DFU (USB FS Device) but
only for the selection phase. An external clock multiple of 1 MHz (between 4 and 26 MHz) is
required for CAN and DFU bootloader execution after the selection phase.

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34.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 40.Bootloader V9.x selection for STM32F446xx

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34.3 Bootloader version

The following table lists the STM32F446xx devices bootloader V9.x versions:

Table 71. STM32F446xx bootloader V9.x versions

Bootloader
version Description Known limitations
number

After executing Go command (jump to user code)

the bootloader resets AHB1ENR value to 0x0000
V9.0 Initial bootloader version 0000 and thus CCM RAM, when present, is not
active (shall be re-enabled by user code at
startup)

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35 STM32F469xx/479xx devices bootloader

35.1 Bootloader configuration

The STM32F469xx/479xx bootloader is activated by applying pattern5 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 72. STM32F469xx/479xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 60 MHz

using the PLL.
The HSI clock source is used at startup
HSI enabled (interface detection phase) and when
USART or SPI or I2C interfaces are
selected (once CAN or DFU bootloader is
selected, the clock source will be derived
from external crystal).
The system clock frequency is 60 MHz.
RCC The HSE clock source is used only when
the CAN or the DFU (USB FS Device)
HSE enabled interfaces are selected.
The external clock must provide a
frequency multiple of 1 MHz and ranging
from 4 MHz to 26 MHz.
The Clock Security System (CSS)
interrupt is enabled for the CAN and DFU
-
bootloaders. Any failure (or removal) of
Common to all the external clock generates system reset.
bootloaders 12 Kbyte starting from address
RAM - 0x20000000 are used by the bootloader
firmware
29 Kbyte starting from address
System memory - 0x1FFF0000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
Voltage range is set to [1.62 V, 2.1 V]. In
this range internal Flash write operations
are allowed only in byte format (Half-
Power - Word, Word and Double-Word operations
are not allowed). The voltage range can
be configured in run time using bootloader
commands.

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Table 72. STM32F469xx/479xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART1 configuration

USART1 Enabled
is: 8-bits, even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART3 configuration
USART3 USART3 Enabled
is: 8-bits, even parity and 1 Stop bit
bootloader (on
USART3_RX pin Input PB11 pin: USART3 in reception mode
PB10/PB11)
USART3_TX pin Output PB10 pin: USART3 in transmission mode
Once initialized the USART3 configuration
USART3 USART3 Enabled
is: 8-bits, even parity and 1 Stop bit
bootloader (on
USART3_RX pin Input PC11 pin: USART3 in reception mode
PC10/PC11)
USART3_TX pin Output PC10 pin: USART3 in transmission mode
Used to automatically detect the serial
USARTx bootloaders SysTick timer Enabled baud rate from the host for USARTx
bootloaders.
Once initialized the CAN2 configuration is:
Baudrate 125 kbps, 11-bit identifier.
Note: CAN1 is clocked during CAN2
CAN2 Enabled
bootloader execution because CAN1
CAN2 bootloader manages the communication between
CAN2 and SRAM.
CAN2_RX pin Input PB05 pin: CAN2 in reception mode
CAN2_TX pin Output PB13 pin: CAN2 in transmission mode
The I2C1 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b1000100x (where x = 0 for
write and x = 1 for read).
I2C1 bootloader
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB9 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.
The I2C2 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C2 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b1000100x (where x = 0 for
write and x = 1 for read).
I2C2 bootloader
PF0 pin: clock line is used in open-drain
I2C2_SCL pin Input/Output
mode.
PF1 pin: data line is used in open-drain
I2C2_SDA pin Input/Output
mode.

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Table 72. STM32F469xx/479xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C3 configuration is:

I2C speed: up to 400 KHz, 7-bit address,
I2C3 Enabled slave mode, analog filter ON. Slave 7-bit
address: 0b1000100x (where x = 0 for
write and x = 1 for read).
I2C3 bootloader
PA8 pin: clock line is used in open-drain
I2C3_SCL pin Input/Output
mode.
PC9 pin: data line is used in open-drain
I2C3_SDA pin Input/Output
mode.
The SPI1 configuration is:
Slave mode, Full Duplex, 8-bit MSB,
SPI1 Enabled
Speed up to 8 MHz, Polarity: CPOL Low,
CPHA Low, NSS hardware.
PA7 pin: Slave data Input line, used in
SPI1_MOSI pin Input
Push-pull pull-down mode
SPI1 bootloader
PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
Push-pull pull-down mode
PA5 pin: Slave clock line, used in Push-
SPI1_SCK pin Input
pull pull-down mode
PA4 pin: slave chip select pin used in
SPI1_NSS pin Input
Push-pull pull-up mode.
The SPI2 configuration is:
Slave mode, Full Duplex, 8-bit MSB,
SPI2 Enabled
Speed up to 8 MHz, Polarity: CPOL Low,
CPHA Low, NSS hardware.
PI3 pin: Slave data Input line, used in
SPI2_MOSI pin Input
Push-pull pull-down mode
SPI2 bootloader
PI2 pin: Slave data output line, used in
SPI2_MISO pin Output
Push-pull pull-down mode
PI1pin: Slave clock line, used in Push-pull
SPI2_SCK pin Input
pull-down mode
PI0 pin: slave chip select pin used in
SPI2_NSS pin Input
Push-pull pull-up mode.

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Table 72. STM32F469xx/479xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI4 configuration is:

Slave mode, Full Duplex, 8-bit MSB,
SPI4 Enabled
Speed up to 8 MHz, Polarity: CPOL Low,
CPHA Low, NSS hardware.
PE14 pin: Slave data Input line, used in
SPI4_MOSI pin Input
Push-pull pull-down mode
SPI4 bootloader
PE13 pin: Slave data output line, used in
SPI4_MISO pin Output
Push-pull pull-down mode
PE12 pin: Slave clock line, used in Push-
SP4_SCK pin Input
pull pull-down mode
PE11 pin: slave chip select pin used in
SPI4_NSS pin Input
Push-pull pull-up mode.
USB OTG FS configured in forced device
mode. USB_OTG_FS interrupt vector is
USB Enabled
enabled and used for USB DFU
communications.
DFU bootloader
USB_DM pin PA11 pin: USB DM line.
Input/Output PA12 pin: USB DP line.
USB_DP pin
No external Pull-Up resistor is required.

The system clock is derived from the embedded internal high-speed RC for USARTx and
I2Cx bootloaders. This internal clock is also used for CAN and DFU (USB FS Device) but
only for the selection phase. An external clock multiple of 1 MHz (between 4 and 48 MHz) is
required for CAN and DFU bootloaders execution after the selection phase.

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35.2 Bootloader selection

The Figure 41 and Figure 42 show the bootloader selection mechanism.

Figure 41. Dual Bank Boot Implementation for STM32F469xx/479xx Bootloader V9.x

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162/307 AN2606 Rev 36

AN2606 STM32F469xx/479xx devices bootloader

Figure 42.Bootloader V9.x selection for STM32F469xx/479xx

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35.3 Bootloader version

The following table lists the STM32F469xx/479xx devices V9.x bootloader versions:

Table 73.STM32F469xx/479xx bootloader V9.x versions

Bootloader
version Description Known limitations
number

After executing Go command (jump to user code)

the bootloader resets AHB1ENR value to 0x0000
V9.0 Initial bootloader version 0000 and thus CCM RAM, when present, is not
active (shall be re-enabled by user code at
startup)

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36 STM32F72xxx/73xxx devices bootloader

36.1 Bootloader configuration

The STM32F72xxx/73xxx bootloader is activated by applying pattern8 (described in Table 2:
Bootloader activation patterns). The Table 74 shows the hardware resources used by this
bootloader.

Table 74. STM32F72xxx/73xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The HSI is used at startup as clock

source for system clock configured to
HSI enabled
60 MHz and for USART and I2C
bootloader operation.
The HSE is used only when the CAN
or the DFU (USB FS Device)
interfaces are selected. In this case
the system clock configured to 60 MHz
HSE enabled
RCC with HSE as clock source.
The HSE frequency must be multiple
of 1 MHz and ranging from 4 MHz to
26 MHz.
The Clock Security System (CSS)
interrupt is enabled for the CAN and
- DFU bootloaders. Any failure (or
removal) of the external clock
generates system reset.
16 Kbyte starting from address
Common to all RAM - 0x20000000 are used by the
bootloaders bootloader firmware
59 Kbyte starting from address
System memory - 0x1FF00000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
The voltage range is [1.8V, 3.6V]
In this range:
- Flash wait states 3.
Power - - System clock Frequency 60 MHz.
- ART Accelerator enabled.
- Flash write operation by byte (refer to
bootloader memory management
section for more information).

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Table 74. STM32F72xxx/73xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART1

USART1 Enabled configuration is: 8-bits, even parity and
1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
PA9 pin: USART1 in transmission
USART1_TX pin Output
mode
Once initialized the USART3
USART3 Enabled configuration is: 8-bits, even parity and
USART3 1 Stop bit
bootloader (on
USART3_RX pin Input PB11 pin: USART3 in reception mode
PB11/PB10)
PB10 pin: USART3 in transmission
USART3_TX pin Output
mode
Once initialized the USART3
USART3 Enabled configuration is: 8-bits, even parity and
USART3 1 Stop bit
bootloader (on USART3_RX pin Input PC11 pin: USART3 in reception mode
PC11/PC10)
PC10 pin: USART3 in transmission
USART3_TX pin Output
mode
Used to automatically detect the serial
USARTx
SysTick timer Enabled baud rate from the host for USARTx
bootloaders bootloaders.
Once initialized the CAN1
CAN1 Enabled configuration is: Baudrate 125 kbps,
11-bit identifier.
CAN1 bootloader
CAN1_RX pin Input PD0 pin: CAN1 in reception mode
CAN1_TX pin Output PD1 pin: CAN1 in transmission mode
The I2C1 configuration is:
I2C speed: up to 400 KHz, 7-bit
address, slave mode, analog filter ON.
I2C1 Enabled
Slave 7-bit address: 0b1001001x
(where x = 0 for write and x = 1 for
I2C1 bootloader read)
PB6 pin: clock line is used in open-
I2C1_SCL pin Input/Output
drain mode.
PB9 pin: data line is used in open-
I2C1_SDA pin Input/Output
drain mode.

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Table 74. STM32F72xxx/73xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C2 configuration is:

I2C speed: up to 400 KHz, 7-bit
address, slave mode, analog filter ON.
I2C2 Enabled
Slave 7-bit address: 0b1001101x
(where x = 0 for write and x = 1 for
I2C2 bootloader read)
PF1 pin: clock line is used in open-
I2C2_SCL pin Input/Output
drain mode.
PF0 pin: data line is used in open-
I2C2_SDA pin Input/Output
drain mode.
The I2C3 configuration is:
I2C speed: up to 400 KHz, 7-bit
address, slave mode, analog filter ON.
I2C3 Enabled
Slave 7-bit address: 0b1001001x
(where x = 0 for write and x = 1 for
I2C3 bootloader read)
PA8 pin: clock line is used in open-
I2C3_SCL pin Input/Output
drain mode.
PC9 pin: data line is used in open-
I2C3_SDA pin Input/Output
drain mode.
The SPI1 configuration is:
Slave mode, Full Duplex, 8-bit MSB,
SPI1 Enabled
Speed up to 8MHz, Polarity: CPOL
Low, CPHA Low, NSS hardware.
PA7 pin: Slave data Input line, used in
SPI1_MOSI pin Input
Push-pull pull-down mode
SPI1 bootloader
PA6 pin: Slave data output line, used
SPI1_MISO pin Output
in Push-pull pull-down mode
PA5 pin: Slave clock line, used in
SPI1_SCK pin Input
Push-pull pull-down mode
PA4 pin: slave chip select pin used in
SPI1_NSS pin Input
Push-pull pull-up mode.
The SPI2 configuration is:
Slave mode, Full Duplex, 8-bit MSB,
SPI2 Enabled
Speed up to 8MHz, Polarity: CPOL
Low, CPHA Low, NSS hardware.
PI3 pin: Slave data Input line, used in
SPI2_MOSI pin Input
Push-pull pull-down mode
SPI2 bootloader
PI2 pin: Slave data output line, used in
SPI2_MISO pin Output
Push-pull pull-down mode
PI1 pin: Slave clock line, used in Push-
SPI2_SCK pin Input
pull pull-down mode
PI0 pin: slave chip select pin used in
SPI2_NSS pin Input
Push-pull pull-up mode.

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Table 74. STM32F72xxx/73xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI4 configuration is:

Slave mode, Full Duplex, 8-bit MSB,
SPI4 Enabled
Speed up to 8MHz, Polarity: CPOL
Low, CPHA Low, NSS hardware.
PE14 pin: Slave data Input line, used
SPI4_MOSI pin Input
in Push-pull pull-down mode
SPI4 bootloader
PE13 pin: Slave data output line, used
SPI4_MISO pin Output
in Push-pull pull-down mode
PE12 pin: Slave clock line, used in
SP4_SCK pin Input
Push-pull pull-down mode
PE11 pin: slave chip select pin used in
SPI4_NSS pin Input
Push-pull pull-up mode.
USB OTG FS configured in forced
USB Enabled
device mode
USB_DM pin PA11 pin: USB DM line.
DFU bootloader
Input/Output PA12 pin: USB DP line
USB_DP pin No external Pull-Up resistor is
required.
This timer is used to determine the
value of the HSE. Once HSE
CAN1 and DFU
TIM11 Enabled frequency is determined, the system
bootloaders
clock is configured to 60 MHz using
PLL and HSE.

The system clock is derived from the embedded internal high-speed RC for USARTx and
I2Cx bootloaders. This internal clock is also used for CAN and DFU (USB FS Device) but
only for the selection phase. An external clock multiple of 1 MHz (between 4 and 26 MHz) is
required for CAN and DFU bootloader execution after the selection phase.

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36.2 Bootloader selection

The Figure 43 below show the bootloader selection mechanism:

Figure 43. Bootloader V9.x selection for STM32F72xxx/73xxx

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36.3 Bootloader version

The Table 75 lists the STM32F72xxx/73xxx devices bootloader V9.x versions.

Table 75.STM32F72xxx/73xxx bootloader V9.x versions

Bootloader
version Description Known limitations
number

V9.0 Initial bootloader version None

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AN2606 STM32F74xxx/75xxx devices bootloader

37 STM32F74xxx/75xxx devices bootloader

Two bootloader versions are available on STM32F74xxx/75xxx:

• V7.x supporting USART1, USART3, CAN2, I2C1, I2C2, I2C3 and DFU (USB FS
Device). This version is embedded in STM32F74xxx/75xxx rev. A devices.
• V9.x supporting USART1, USART3, CAN2, I2C1, I2C2, I2C3, SPI1, SPI2, SPI4 and
DFU (USB FS Device). This version is embedded in STM32F74xxx/75xxx rev. Z
devices.
Note: When readout protection Level2 is activated, STM32F74xxx/75xxx devices can boot also on
system memory and all commands are not accessible except Get, GetID, and GetVersion.

37.1 Bootloader V7.x

37.1.1 Bootloader configuration

The STM32F74xxx/75xxx bootloader is activated by applying pattern8 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

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Table 76. STM32F74xxx/75xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment
The HSI is used at startup as clock source for system
HSI enabled clock configured to 60 MHz and for USART and I2C
bootloader operation.
The HSE is used only when the CAN or the DFU (USB
FS Device) interfaces are selected. In this case the
system clock configured to 60 MHz with HSE as clock
HSE enabled source.
RCC
The HSE frequency must be multiple of 1 MHz and
ranging from 4 MHz to 26 MHz.
The Clock Security System (CSS) interrupt
is enabled for the CAN and DFU
-
bootloaders. Any failure (or removal) of the
external clock generates system reset.
Common to all 16 Kbyte starting from address 0x20000000 are used
RAM -
bootloaders by the bootloader firmware
60 Kbyte starting from address 0x1FF00000, contain
System memory -
the bootloader firmware
The independent watchdog (IWDG) prescaler is
configured to its maximum value. It is periodically
IWDG - refreshed to prevent watchdog reset (in case the
hardware IWDG option was previously enabled by the
user).
The voltage range is [1.8V, 3.6V]. In this range:
- Flash wait states 3.
- System clock Frequency 60 MHz.
Power -
- ART Accelerator enabled.
- Flash write operation by byte (refer to bootloader
memory management section for more information).
Once initialized the USART1 configuration is: 8-bits,
USART1 Enabled
USART1 even parity and 1 Stop bit
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART3 configuration is: 8-bits,
USART3 USART3 Enabled
even parity and 1 Stop bit
bootloader (on
USART3_RX pin Input PB11 pin: USART3 in reception mode
PB10/PB11)
USART3_TX pin Output PB10 pin: USART3 in transmission mode
Once initialized the USART3 configuration is: 8-bits,
USART3 USART3 Enabled
even parity and 1 Stop bit
bootloader (on
USART3_RX pin Input PC11 pin: USART3 in reception mode
PC10/PC11)
USART3_TX pin Output PC10 pin: USART3 in transmission mode
USARTx Used to automatically detect the serial baud rate from
SysTick timer Enabled
bootloaders the host for USARTx bootloaders.

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Table 76. STM32F74xxx/75xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment
Once initialized the CAN2 configuration is: Baudrate
125 kbps, 11-bit identifier.
CAN2 Enabled Note: CAN1 is clocked during CAN2 bootloader
CAN2 execution because CAN1 manages the
bootloader communication between CAN2 and SRAM.
CAN2_RX pin Input PB5 pin: CAN2 in reception mode
CAN2_TX pin Output PB13 pin: CAN2 in transmission mode
The I2C1 configuration is:
I2C speed: up to 400 KHz, 7-bit address, slave mode,
I2C1 Enabled analog filter ON.
I2C1 bootloader Slave 7-bit address: 0b1000101x
(where x = 0 for write and x = 1 for read)
I2C1_SCL pin Input/Output PB6 pin: clock line is used in open-drain mode.
I2C1_SDA pin Input/Output PB9 pin: data line is used in open-drain mode.
The I2C2 configuration is:
I2C speed: up to 400 KHz, 7-bit address, slave mode,
I2C2 Enabled analog filter ON.
I2C2 bootloader Slave 7-bit address: 0b1000101x
(where x = 0 for write and x = 1 for read)
I2C2_SCL pin Input/Output PF1 pin: clock line is used in open-drain mode.
I2C2_SDA pin Input/Output PF0 pin: data line is used in open-drain mode.
The I2C3 configuration is:
I2C speed: up to 400 KHz, 7-bit address, slave mode,
I2C3 Enabled analog filter ON.
I2C3 bootloader Slave 7-bit address: 0b1000101x
(where x = 0 for write and x = 1 for read)
I2C3_SCL pin Input/Output PA8 pin: clock line is used in open-drain mode.
I2C3_SDA pin Input/Output PC9 pin: data line is used in open-drain mode.
USB Enabled USB OTG FS configured in forced device mode.
USB_DM pin PA11 pin: USB DM line.
DFU bootloader
Input/Output PA12 pin: USB DP line
USB_DP pin
No external Pull-Up resistor is required.
This timer is used to determine the value of the HSE.
CAN2 and DFU
TIM11 Enabled Once HSE frequency is determined, the system clock
bootloaders
is configured to 60 MHz using PLL and HSE.

The system clock is derived from the embedded internal high-speed RC for USARTx and
I2Cx bootloaders. This internal clock is also used for CAN and DFU (USB FS Device) but
only for the selection phase. An external clock multiple of 1 MHz (between 4 and 26 MHz) is
required for CAN and DFU bootloader execution after the selection phase.

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37.1.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 44.Bootloader V7.x selection for STM32F74xxx/75xxx

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37.1.3 Bootloader version

The following table lists the STM32F74xxx/75xxx devices bootloader V7.x versions:

Table 77.STM32F74xxx/75xxx bootloader V7.x versions

Bootloader
version Description Known limitations
number

V7.0 Initial bootloader version None

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37.2 Bootloader V9.x

37.2.1 Bootloader configuration

The STM32F74xxx/75xxx bootloader is activated by applying pattern8 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 78. STM32F74xxx/75xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The HSI is used at startup as clock source

for system clock configured to 60 MHz and
HSI enabled
for USART, I2C and SPI bootloader
operation.
The HSE is used only when the CAN or the
DFU (USB FS Device) interfaces are
selected. In this case the system clock
RCC HSE enabled configured to 60 MHz with HSE as clock
source.
The HSE frequency must be multiple of 1
MHz and ranging from 4 MHz to 26 MHz.
The Clock Security System (CSS) interrupt
is enabled for the CAN and DFU
-
bootloaders. Any failure (or removal) of the
external clock generates system reset.
16 Kbyte starting from address
RAM - 0x20000000 are used by the bootloader
Common to all
firmware
bootloaders
60 Kbyte starting from address
System memory - 0x1FF00000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
The voltage range is [1.8V, 3.6V]
In this range:
- Flash wait states 3.
Power - - System clock Frequency 60 MHz.
- ART Accelerator enabled.
- Flash write operation by byte (refer to
bootloader memory management section
for more information).

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Table 78. STM32F74xxx/75xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART1 configuration

USART1 Enabled
is: 8-bits, even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART3 configuration
USART3 USART3 Enabled
is: 8-bits, even parity and 1 Stop bit
bootloader (on
USART3_RX pin Input PB11 pin: USART3 in reception mode
PB10/PB11)
USART3_TX pin Output PB10 pin: USART3 in transmission mode
Once initialized the USART3 configuration
USART3 USART3 Enabled
is: 8-bits, even parity and 1 Stop bit
bootloader (on
USART3_RX pin Input PC11 pin: USART3 in reception mode
PC10/PC11)
USART3_TX pin Output PC10 pin: USART3 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.
Once initialized the CAN2 configuration is:
Baudrate 125 kbps, 11-bit identifier.
CAN2 Enabled Note: CAN1 is clocked during CAN2
bootloader execution because CAN1
CAN2 bootloader manages the communication between
CAN2 and SRAM.
CAN2_RX pin Input PB5 pin: CAN2 in reception mode
CAN2_TX pin Output PB13 pin: CAN2 in transmission mode
The I2C1 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1000101x
I2C1 bootloader (where x = 0 for write and x = 1 for read)
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/output
mode.
PB9 pin: data line is used in open-drain
I2C1_SDA pin Input/output
mode.
The I2C2 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C2 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1000101x
I2C2 bootloader (where x = 0 for write and x = 1 for read)
PF1 pin: clock line is used in open-drain
I2C2_SCL pin Input/output
mode.
PF0 pin: data line is used in open-drain
I2C2_SDA pin Input/output
mode.

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Table 78. STM32F74xxx/75xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C3 configuration is:

I2C speed: up to 400 KHz, 7-bit address,
I2C3 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1000101x
I2C3 bootloader (where x = 0 for write and x = 1 for read)
PA8 pin: clock line is used in open-drain
I2C3_SCL pin Input/output
mode.
PC9 pin: data line is used in open-drain
I2C3_SDA pin Input/output
mode.
The SPI1 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI1 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PA7 pin: Slave data Input line, used in
SPI1_MOSI pin Input
Push-pull pull-down mode
SPI1 bootloader
PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
Push-pull pull-down mode
PA5 pin: Slave clock line, used in Push-pull
SPI1_SCK pin Input
pull-down mode
PA4 pin: slave chip select pin used in Push-
SPI1_NSS pin Input
pull pull-up mode.
The SPI2 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI2 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PI3 pin: Slave data Input line, used in Push-
SPI2_MOSI pin Input
pull pull-down mode
SPI2 bootloader
PI2 pin: Slave data output line, used in
SPI2_MISO pin Output
Push-pull pull-down mode
PI1 pin: Slave clock line, used in Push-pull
SPI2_SCK pin Input
pull-down mode
PI0 pin: slave chip select pin used in Push-
SPI2_NSS pin Input
pull pull-up mode.

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AN2606 STM32F74xxx/75xxx devices bootloader

Table 78. STM32F74xxx/75xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI4 configuration is:

Slave mode, Full Duplex, 8-bit MSB, Speed
SPI4 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PE14 pin: Slave data Input line, used in
SPI4_MOSI pin Input
Push-pull pull-down mode
SPI4 bootloader
PE13 pin: Slave data output line, used in
SPI4_MISO pin Output
Push-pull pull-down mode
PE12 pin: Slave clock line, used in Push-
SP4_SCK pin Input
pull pull-down mode
PE11 pin: slave chip select pin used in
SPI4_NSS pin Input
Push-pull pull-up mode.
USB OTG FS configured in forced device
USB Enabled
mode.

DFU bootloader USB_DM pin PA11 pin: USB DM line.

Input/Output PA12 pin: USB DP line
USB_DP pin
No external Pull-Up resistor is required.
This timer is used to determine the value of
CAN2 and DFU the HSE. Once HSE frequency is
TIM11 Enabled
bootloaders determined, the system clock is configured
to 60 MHz using PLL and HSE.

The system clock is derived from the embedded internal high-speed RC for USARTx, I2Cx
and SPIx bootloaders. This internal clock is also used for CAN and DFU (USB FS Device)
but only for the selection phase. An external clock multiple of 1 MHz (between 4 and
26 MHz) is required for CAN and DFU bootloader execution after the selection phase.

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37.2.2 Bootloader selection

The Figure 45 shows the bootloader selection mechanism.

Figure 45.Bootloader V9.x selection for STM32F74xxx/75xxx

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180/307 AN2606 Rev 36

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37.2.3 Bootloader version

The following table lists the STM32F74xxx/75xxx bootloader V9.x versions:

Table 79.STM32F74xxx/75xxx bootloader V9.x versions

Bootloader
version Description Known limitations
number

V9.0 Initial bootloader version None

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38 STM32F76xxx/77xxx devices bootloader

38.1 Bootloader configuration

The STM32F76xxx/77xxx bootloader is activated by applying pattern9 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 80. STM32F76xxx/77xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The HSI is used at startup as clock source

HSI enabled for system clock configured to 60 MHz and
for USART and I2C bootloader operation.
The HSE is used only when the CAN or the
DFU (USB FS Device) interfaces are
selected. In this case the system clock
HSE enabled configured to 60 MHz with HSE as clock
RCC source.
The HSE frequency must be multiple of 1
MHz and ranging from 4 MHz to 26 MHz.
The Clock Security System (CSS) interrupt
is enabled for the CAN and DFU
-
bootloaders. Any failure (or removal) of the
external clock generates system reset.
16 Kbyte starting from address
RAM - 0x20000000 are used by the bootloader
Common to all firmware
bootloaders 59 Kbyte starting from address
System memory - 0x1FF00000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
The voltage range is [1.8V, 3.6V]
In this range:
- Flash wait states 3.
Power - - System clock Frequency 60 MHz.
- ART Accelerator enabled.
- Flash write operation by byte (refer to
bootloader memory management section
for more information).

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Table 80. STM32F76xxx/77xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART1 configuration

USART1 Enabled
is: 8-bits, even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART3 configuration
USART3 Enabled
USART3 is: 8-bits, even parity and 1 Stop bit
bootloader (on USART3_RX pin Input PB11 pin: USART3 in reception mode
PB11/PB10)
USART3_TX pin Output PB10 pin: USART3 in transmission mode
Once initialized the USART3 configuration
USART3 Enabled
USART3 is: 8-bits, even parity and 1 Stop bit
bootloader (on USART3_RX pin Input PC11 pin: USART3 in reception mode
PC11/PC10)
USART3_TX pin Output PC10 pin: USART3 in transmission mode
USARTx Used to automatically detect the serial baud
SysTick timer Enabled
bootloaders rate from the host for USARTx bootloaders.
Once initialized the CAN2 configuration is:
Baudrate 125 kbps, 11-bit identifier.
Note: CAN1 is clocked during CAN2
CAN2 Enabled
bootloader execution because CAN1
CAN2 bootloader manages the communication between
CAN2 and SRAM.
CAN2_RX pin Input PB5 pin: CAN2 in reception mode
CAN2_TX pin Output PB13 pin: CAN2 in transmission mode
The I2C1 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1001001x (where x
I2C1 bootloader = 0 for write and x = 1 for read)
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB9 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.
The I2C2 configuration is:
I2C speed: up to 400 KHz, 7-bit address,
I2C2 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1001001x (where x
I2C2 bootloader = 0 for write and x = 1 for read)
PF1 pin: clock line is used in open-drain
I2C2_SCL pin Input/Output
mode.
PF0 pin: data line is used in open-drain
I2C2_SDA pin Input/Output
mode.

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Table 80. STM32F76xxx/77xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C3 configuration is:

I2C speed: up to 400 KHz, 7-bit address,
I2C3 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1001001x (where x
I2C3 bootloader = 0 for write and x = 1 for read)
PA8 pin: clock line is used in open-drain
I2C3_SCL pin Input/Output
mode.
PC9 pin: data line is used in open-drain
I2C3_SDA pin Input/Output
mode.
The SPI1 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI1 Enabled
up to 8MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PA7 pin: Slave data Input line, used in
SPI1_MOSI pin Input
Push-pull pull-down mode
SPI1 bootloader
PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
Push-pull pull-down mode
PA5 pin: Slave clock line, used in Push-pull
SPI1_SCK pin Input
pull-down mode
PA4 pin: slave chip select pin used in Push-
SPI1_NSS pin Input
pull pull-up mode.
The SPI2 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI2 Enabled
up to 8MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PI3 pin: Slave data Input line, used in Push-
SPI2_MOSI pin Input
pull pull-down mode
SPI2 bootloader
PI2 pin: Slave data output line, used in
SPI2_MISO pin Output
Push-pull pull-down mode
PI1 pin: Slave clock line, used in Push-pull
SPI2_SCK pin Input
pull-down mode
PI0 pin: slave chip select pin used in Push-
SPI2_NSS pin Input
pull pull-up mode.

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Table 80. STM32F76xxx/77xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI4 configuration is:

Slave mode, Full Duplex, 8-bit MSB, Speed
SPI4 Enabled
up to 8MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PE14 pin: Slave data Input line, used in
SPI4_MOSI pin Input
Push-pull pull-down mode
SPI4 bootloader
PE13 pin: Slave data output line, used in
SPI4_MISO pin Output
Push-pull pull-down mode
PE12 pin: Slave clock line, used in Push-
SP4_SCK pin Input
pull pull-down mode
PE11 pin: slave chip select pin used in
SPI4_NSS pin Input
Push-pull pull-up mode.
USB OTG FS configured in forced device
USB Enabled
mode

DFU bootloader USB_DM pin PA11 pin: USB DM line.

Input/Output PA12 pin: USB DP line
USB_DP pin
No external Pull-Up resistor is required.
This timer is used to determine the value of
CAN2 and DFU the HSE. Once HSE frequency is
TIM11 Enabled
bootloaders determined, the system clock is configured
to 60 MHz using PLL and HSE.

The system clock is derived from the embedded internal high-speed RC for USARTx and
I2Cx bootloaders. This internal clock is also used for CAN and DFU (USB FS Device) but
only for the selection phase. An external clock multiple of 1 MHz (between 4 and 26 MHz) is
required for CAN and DFU bootloader execution after the selection phase.

38.2 Bootloader selection

The Figure 46 and Figure 47 show the bootloader selection mechanism.

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STM32F76xxx/77xxx devices bootloader AN2606

Figure 46. Dual Bank Boot Implementation for STM32F76xxx/77xxx Bootloader V9.x

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1. Only BOOT_ADD0 value is considered whatever the BOOT0 pin state, as described in Known limitation under Table 81.
2. ITCM RAM is not considered valid as stack pointer address for the dual bank boot mechanism.

186/307 AN2606 Rev 36

AN2606 STM32F76xxx/77xxx devices bootloader

Figure 47. Bootloader V9.x selection for STM32F76xxx/77xxx

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38.3 Bootloader version

The following table lists the STM32F76xxx/77xxx devices bootloader V9.x versions.

Table 81.STM32F76xxx/77xxx bootloader V9.x versions

Bootloader
version Description Known limitations
number

When the Flash memory is configured to the dual

bank boot mode (nDBANK=nDBOOT=0),
whatever the BOOT0 Pin state only
BOOT_ADD0 value is considered (when BOOT0
Pin=1, BOOT_ADD0 value is considered not the
V9.3 Initial bootloader version
BOOT_ADD1).
Workaround: in order to manage dual bank boot
with BOOT_ADD0 only, please refer to the
AN4826: "STM32F7 Series Flash memory dual
bank mode”

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AN2606 STM32G07xxx/08xxx device bootloader

39 STM32G07xxx/08xxx device bootloader

39.1 Bootloader configuration

The STM32G0xxx bootloader is activated by applying pattern10 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 82. STM32G07xxx/8xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 24 MHz (using PLL

RCC HSI enabled
clocked by HSI).
12 Kbytes starting from address 0x20000000 are
RAM -
used by the bootloader firmware

Common to all 28 Kbytes starting from address 0x1FFF0000,

System memory -
bootloaders contain the bootloader firmware
The independent watchdog (IWDG) prescaler is
configured to its maximum value. It is periodically
IWDG - refreshed to prevent watchdog reset (in case the
hardware IWDG option was previously enabled by
the user).
The Address to jump to for the sticky area:
Sticky area - -
@0x1FFF6800
Once initialized the USART1 configuration is: 8-bits,
USART1 Enabled
even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration is: 8-bits,
USART2 Enabled
even parity and 1 Stop bit
USART2
bootloader USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Once initialized the USART3 configuration is: 8-bits,
USART3 Enabled
even parity and 1 Stop bit
USART3
bootloader USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode
The I2C1 configuration is:
I2C speed: up to 1 MHz, 7-bit address, slave mode,
I2C1 Enabled analog filter ON.
Slave 7-bit address: 0b1010001x
I2C1 bootloader
(where x = 0 for write and x = 1 for read)
I2C1_SCL pin Input/Output PB6 pin: clock line is used in open-drain mode.
I2C1_SDA pin Input/Output PB7 pin: data line is used in open-drain mode.

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Table 82. STM32G07xxx/8xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C2 configuration is:

I2C speed: up to 1 MHz, 7-bit address, slave mode,
I2C2 Enabled analog filter ON.
Slave 7-bit address: 0b1010001x
I2C2 bootloader
(where x = 0 for write and x = 1 for read)
I2C2_SCL pin Input/Output PB10 pin: clock line is used in open-drain mode.
I2C2_SDA pin Input/Output PB11 pin: data line is used in open-drain mode.
The SPI1 configuration is:
– Slave mode
– Full Duplex
SPI1 Enabled
– 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS hardware.
PA7 pin: Slave data Input line, used in Push-pull,
SPI1_MOSI pin Input
SPI1 bootloader pull-down mode.
PA6 pin: Slave data output line, used in Push-pull,
SPI1_MISO pin Output
pull-down mode.
PA5 pin: Slave clock line, used in Push-pull, pull-
SPI1_SCK pin Input
down mode.
PA4 pin: slave chip select pin used in Push-pull,
SPI1_NSS pin Input pull-up mode. Note: This IO can be tied to Gnd if the
SPI Master does not use it.
The SPI2 configuration is:
– Slave mode
– Full Duplex
SPI2 Enabled
– 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS hardware.
PB15 pin: Slave data Input line, used in Push-pull,
SPI2_MOSI pin Input
pull-down mode.
SPI2 bootloader
PB14 pin: Slave data output line, used in Push-pull,
SPI2_MISO pin Output
pull-down mode.
PB13 pin: Slave clock line, used in Push-pull, pull-
SPI2_SCK pin Input
down mode.
PB12 pin: slave chip select pin used in Push-pull,
pull-up.
SPI2_NSS pin Input
Note: This IO can be tied to GND if the SPI master
does not use it.

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AN2606 STM32G07xxx/08xxx device bootloader

The sticky area is used to isolate boot code/data which manipulate sensitive information
(secrets) from application code:
• Access is controlled by a sticky bit STICKY_PROT (write once), in the flash CR
register;
• Executed once at boot then locked by writing the sticky bit;
• Width (number of FLASH pages) is defined through an OB, STICKY_SIZE, in the flash
STICKYR register;
The chain of trust is seeded by a unique boot entry via an additional option byte, the
BOOT_EP option byte in the flash STICKYR register.
The BOOT_EP forces boot from user flash, regardless from boot configuration and RDP
level.
Note: For more information regarding the STM32G0xxxx option bytes configuration, refer to the
STM32G0 reference manual
Figure 48 shows the flow to access to sticky area from the bootloader.

Figure 48. Access to sticky area from the bootloader

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of the address to jump to.

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39.2 Bootloader selection

Figure 49 shows the bootloader selection mechanism.

Figure 49. Bootloader V11.0 selection for STM32G0xxx

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39.3 Bootloader version

Table 83 lists the STM32G07xxx/8xxx devices bootloader versions.

Table 83. STM32G07xx/08xxx bootloader versions

Bootloader version number Description Known limitations

Not supporting packages

V11.0 Initial bootloader version
smaller then LQFP64
V11.1 Supporting all packages None
V11.2 Add sticky area feature None

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AN2606 STM32H74xxx/75xxx devices bootloader

40 STM32H74xxx/75xxx devices bootloader

40.1 Bootloader configuration

The STM32H74xxx/75xxx bootloader is activated by applying pattern10 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 84. STM32H74xxx/75xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 64 MHz

using the HSI.
HSI enabled The HSI clock source is used at startup
(interface detection phase) and when
USART or SPI or I2C interface is selected.
RCC
The HSE clock source is used only when
the DFU (USB FS Device) interface is
HSE enabled selected. In this case the system clock is configured
to 64 MHz with HSE as clock source. The HSE
fequency must have one of the following values [25,
Common to all 20, 16,12, 10, 8, 4] MHz.
bootloaders 16 Kbyte starting from address 0x20000000, and
RAM - 208 Kbyte starting from address 0x24000000 are
used by the bootloader firmware
122 Kbyte starting from address 0x1FFF0000,
System memory -
contain the bootloader firmware
The independent watchdog (IWDG) prescaler is
configured to its maximum value. It is periodically
IWDG - refreshed to prevent watchdog reset (in case the
hardware IWDG option was previously enabled by
the user).
Power - Voltage range is set to Voltage Range 3.
Once initialized the USART1 configuration is: 8-bits,
USART1 Enabled
USART1 even parity and 1 Stop bit
bootloader (on USART1_RX pin Input PA10 pin: USART1 in reception mode
PA9/PA10)
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART1 configuration is: 8-bits,
USART1 Enabled
USART1 even parity and 1 Stop bit
bootloader (on
USART1_RX pin Input PB15 pin: USART1 in reception mode
PB14/PB15)
USART1_TX pin Output PB14 pin: USART1 in transmission mode
Once initialized the USART2 configuration is: 8-bits,
USART2 Enabled
even parity and 1 Stop bit
USART2
bootloader USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode

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306
STM32H74xxx/75xxx devices bootloader AN2606

Table 84. STM32H74xxx/75xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART3 configuration is: 8-bits,

USART3 Enabled
even parity and 1 Stop bit
USART3
bootloader USART3_RX pin Input PB11 pin: USART3 in reception mode
USART3_TX pin Output PB10 pin: USART3 in transmission mode
The I2C1 configuration is:
I2C speed: up to 400 KHz, 7-bit address, slave
I2C1 Enabled mode, analog filter ON.
Slave 7-bit address: 0b1001110x
I2C1 bootloader
(where x = 0 for write and x = 1 for read)
I2C1_SCL pin Input/Output PB6 pin: clock line is used in open-drain mode.
I2C1_SDA pin Input/Output PB9 pin: data line is used in open-drain mode.
The I2C2 configuration is:
I2C speed: up to 400 KHz, 7-bit address, slave
I2C2 Enabled mode, analog filter ON.
Slave 7-bit address: 0b1001110x
I2C2 bootloader
(where x = 0 for write and x = 1 for read)
I2C2_SCL pin Input/Output PF1 pin: clock line is used in open-drain mode.
I2C2_SDA pin Input/Output PF0 pin: data line is used in open-drain mode.
The I2C3 configuration is:
I2C speed: up to 400 KHz, 7-bit address, slave
I2C3 Enabled mode, analog filter ON.
Slave 7-bit address: 0b1001110x
I2C3 bootloader
(where x = 0 for write and x = 1 for read)
I2C3_SCL pin Input/Output PA8 pin: clock line is used in open-drain mode.
I2C3_SDA pin Input/Output PC9 pin: data line is used in open-drain mode.
The SPI1 configuration is:
– Slave mode
– Full Duplex
SPI1 Enabled
– 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS hardware.
SPI1 bootloader PA7 pin: Slave data Input line, used in Push-pull, no
SPI1_MOSI pin Input
pull-up no pull-down mode.
PA6 pin: Slave data output line, used in Push-pull,
SPI1_MISO pin Output
no pull-up no pull-down mode.
PA5 pin: Slave clock line, used in Push-pull no pull-
SPI1_SCK pin Input
up, no pull-up no pull-down mode.
PA4 pin: slave chip select pin used in Push-pull, no
SPI1_NSS pin Input
pull-up no pull-down mode.

194/307 AN2606 Rev 36

AN2606 STM32H74xxx/75xxx devices bootloader

Table 84. STM32H74xxx/75xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI2 configuration is:

– Slave mode
– Full Duplex
SPI2 Enabled
– 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS hardware.
SPI2 bootloader PI3 pin: Slave data Input line, used in Push-pull, no
SPI2_MOSI pin Input
pull-up no pull-down mode.
PI2 pin: Slave data output line, used in Push-pull, no
SPI2_MISO pin Output
pull-up no pull-down mode.
PI1 pin: Slave clock line, used in Push-pull, no pull-
SPI2_SCK pin Input
up no pull-down mode.
PI0 pin: slave chip select pin used in Push-pull, no
SPI2_NSS pin Input
pull-up no pull-down mode.
The SPI3 configuration is:
– Slave mode
– Full Duplex
SPI3 Enabled
– 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS hardware.
SPI3 bootloader PC12 pin: Slave data Input line, used in Push-pull,
SPI3_MOSI pin Input
no pull-up no-pull down mode
PC11 pin: Slave data output line, used in Push-pull,
SPI3_MISO pin Output
no pull-up no-pull down mode.
PC10 pin: Slave clock line, used in Push-pull, no
SPI3_SCK pin Input
pull-up no-pull down mode.
PA15 pin: slave chip select pin used in Push-pull, no
SPI3_NSS pin Input
pull-up no pull-down mode.
The SPI4 configuration is:
– Slave mode
– Full Duplex
SPI4 Enabled
– 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS hardware.
SPI4 bootloader PE14 pin: Slave data Input line, used in Push-pull,
SPI4_MOSI pin Input
no pull-up no pull-down mode.
PE13 pin: Slave data output line, used in Push-pull,
SPI4_MISO pin Output
no pull-up no pull-down mode.
PE12 pin: Slave clock line, used in Push-pull, no
SPI4_SCK pin Input
pull-up no pull-down mode.
PE11 pin: slave chip select pin used in Push-pull, no
SPI4_NSS pin Input
pull-up no pull-down mode.

AN2606 Rev 36 195/307

306
STM32H74xxx/75xxx devices bootloader AN2606

Table 84. STM32H74xxx/75xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

USB FS configured in forced device mode.

USB Enabled USB FS interrupt vector is enabled and used for
USB DFU communications.
USB_DM pin PA11: USB DM line.

DFU bootloader Input/Output PA12: USB DP line

USB_DP pin
No external Pull-up resistor is required
This timer is used to determine the value of the
HSE. Once the HSE frequency is determined, the
TIM17 Enabled
system clock is configured to 64 MHz using PLL and
HSE.

196/307 AN2606 Rev 36

AN2606 STM32H74xxx/75xxx devices bootloader

40.2 Bootloader selection

The Figure 50 shows the bootloader selection mechanism.

Figure 50. Bootloader V13.x selection for STM32H74xxx/75xxx

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AN2606 Rev 36 197/307

306
STM32H74xxx/75xxx devices bootloader AN2606

40.3 Bootloader version

Table 85 lists the STM32H74xxx/75xxx devices bootloader versions.

Table 85.STM32H74xxx/75xxx bootloader version

Bootloader
version Description Known limitations
number

V13.2 Initial bootloader version None

198/307 AN2606 Rev 36

AN2606 STM32L01xxx/02xxx devices bootloader

41 STM32L01xxx/02xxx devices bootloader

41.1 Bootloader configuration

The STM32L01xxx/02xxx bootloader is activated by applying pattern6 (described in Table 2:
Bootloader activation patterns). The following Table 86 shows the hardware resources used
by this bootloader.

Table 86. STM32L01xxx/02xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 32 MHz with HSI 16

RCC HSI enabled
MHz as clock source.
2 Kbyte starting from address 0x20000000 are
RAM -
used by the bootloader firmware

Common to all 4 Kbyte starting from address 0x1FF00000, contain

System memory -
bootloaders the bootloader firmware
The independent watchdog (IWDG) prescaler is
configured to its maximum value. It is periodically
IWDG - refreshed to prevent watchdog reset (in case the
hardware IWDG option was previously enabled by
the user).
Once initialized the USART2 configuration is: 8-bits,
USART2 Enabled
USART2 even parity and 1 Stop bit
bootloader (on
USART2_RX pin Input PA10 pin: USART2 in reception mode
PA9/PA10)
USART2_TX pin Output PA9 pin: USART2 in transmission mode
Once initialized the USART2 configuration is: 8-bits,
USART2 Enabled
USART2 even parity and 1 Stop bit
bootloader (on USART2_RX pin Input PA3 pin: USART2 in reception mode
PA2/PA3)
USART2_TX pin Output PA2 pin: USART2 in transmission mode
USART2 Used to automatically detect the serial baud rate
SysTick timer Enabled
bootloader from the host for USARTx bootloaders.

The SPI1 configuration is:

Slave mode, Full Duplex, 8-bit MSB, Speed up to 8
SPI1 Enabled
MHz, Polarity: CPOL Low, CPHA Low, NSS
hardware.
PA7 pin: Slave data Input line, used in Push-pull
SPI1_MOSI pin Input
pull-down mode
SPI1 bootloader
(for all device PA6 pin: Slave data output line, used in Push-pull
SPI1_MISO pin Output
packages except pull-down mode
TSSOP14)
PA5 pin: Slave clock line, used in Push-pull pull-
SPI1_SCK pin Input
down mode
PA4 pin: slave chip select pin used in Push-pull pull-
up mode.
SPI1_NSS pin Input
Note:This IO can be tied to GND if the SPI Master
does not use it.

AN2606 Rev 36 199/307

306
STM32L01xxx/02xxx devices bootloader AN2606

Table 86. STM32L01xxx/02xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI1 configuration is:

Slave mode, Full Duplex, 8-bit MSB, Speed up to 8
SPI1 Enabled
MHz, Polarity: CPOL Low, CPHA Low, NSS
hardware.
PA7 pin: Slave data Input line, used in Push-pull
SPI1_MOSI pin Input
pull-down mode
PA14 pin: Slave data output line, used in Push-pull
pull-down mode.
SPI1 bootloader Note: This IO is also used as SWCLK for debug
SPI1_MISO pin Output
(only for devices on interface, as consequence debugger can not
TSSOP14 package) connect to the device in "on-the-fly" mode when the
bootloader is running.
PA13 pin: Slave clock line, used in Push-pull pull-
SPI1_SCK pin Input
down mode
PA4 pin: slave chip select pin used in Push-pull pull-
up mode.
SPI1_NSS pin Input Note: NSS pin synchronization is required on
bootloader with SPI1 interface for devices on
TSSOP14 package.

The system clock is derived from the embedded internal high-speed RC for all bootloader
interfaces. No external quartz is required for bootloader operations.

200/307 AN2606 Rev 36

AN2606 STM32L01xxx/02xxx devices bootloader

41.2 Bootloader selection

The Table 51 shows the bootloader selection mechanism.

Figure 51. Bootloader selection for STM32L01xxx/02xxx

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AN2606 Rev 36 201/307

306
STM32L01xxx/02xxx devices bootloader AN2606

41.3 Bootloader version

The following table lists the STM32L01xxx/02xxx devices bootloader versions.

Table 87.STM32L01xxx/02xxx bootloader versions

Bootloader
version Description Known limitations
number

Bootloader not functional with SPI1 interface for

V12.2 Initial bootloader version
devices on TSSOP14 package.
For the SPI1 interface for devices in TSSOP14, a
This bootloader is an updated falling edge on NSS pin is required before staring
version of bootloader V12.2. communication, to properly synchronize the SPI
V12.3 This new version add support interface. If the NSS pin is grounded (all time from
of SPI interface for devices on device reset) the SPI communication is not
TSSOP14 package. synchronized and bootloader does not work
properly with the SPI interface.

202/307 AN2606 Rev 36

AN2606 STM32L031xx/041xx devices bootloader

42 STM32L031xx/041xx devices bootloader

42.1 Bootloader configuration

The STM32L031xx/041xx bootloader is activated by applying pattern2 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 88. STM32L031xx/041xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 32 MHz with HSI 16

RCC HSI enabled
MHz as clock source.
4 Kbyte starting from address 0x20000000 are
RAM -
used by the bootloader firmware

Common to all 4 Kbyte starting from address 0x1FF00000, contain

System memory -
bootloaders the bootloader firmware
The independent watchdog (IWDG) prescaler is
configured to its maximum value. It is periodically
IWDG - refreshed to prevent watchdog reset (in case the
hardware IWDG option was previously enabled by
the user).
Once initialized the USART2 configuration is: 8-bits,
USART2 USART2 Enabled
even parity and 1 Stop bit
bootloader
USART2_RX pin Input PA10 pin: USART2 in reception mode
(on PA9/PA10)
USART2_TX pin Output PA9 pin: USART2 in transmission mode
Once initialized the USART2 configuration is: 8-bits,
USART2 USART2 Enabled
even parity and 1 Stop bit
bootloader
USART2_RX pin Input PA3 pin: USART2 in reception mode
(on PA2/PA3)
USART2_TX pin Output PA2 pin: USART2 in transmission mode
USART2
Used to automatically detect the serial baud rate
bootloader SysTick timer Enabled
from the host for USARTx bootloaders.

AN2606 Rev 36 203/307

306
STM32L031xx/041xx devices bootloader AN2606

Table 88. STM32L031xx/041xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI1 configuration is:

Slave mode, Full Duplex, 8-bit MSB, Speed up to 8
SPI1 Enabled
MHz, Polarity: CPOL Low, CPHA Low, NSS
hardware.
PA7 pin: Slave data Input line, used in Push-pull
SPI1_MOSI pin Input
pull-down mode
SPI1 bootloader PA6 pin: Slave data output line, used in Push-pull
SPI1_MISO pin Output
pull-down mode
PA5 pin: Slave clock line, used in Push-pull pull-
SPI1_SCK pin Input
down mode
PA4 pin: slave chip select pin used in Push-pull pull-
up mode.
SPI1_NSS pin Input
Note:This IO can be tied to GND if the SPI Master
does not use it.

The system clock is derived from the embedded internal high-speed RC for all bootloader
interfaces. No external quartz is required for bootloader operations.
The bootloader Read/Write commands don’t support SRAM memory space for this product.

204/307 AN2606 Rev 36

AN2606 STM32L031xx/041xx devices bootloader

42.2 Bootloader selection

The Figure 52 shows the bootloader selection mechanism.

Figure 52. Bootloader selection for STM32L031xx/041xx

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42.3 Bootloader version

The Table 89 lists the STM32L031xx/041xx devices bootloader versions:

Table 89. STM32L031xx/041xx bootloader versions

Bootloader version number Description Known limitations

V12.0 Initial bootloader version None

AN2606 Rev 36 205/307

306
STM32L05xxx/06xxx devices bootloader AN2606

43 STM32L05xxx/06xxx devices bootloader

43.1 Bootloader configuration

The STM32L05xxx/06xxx bootloader is activated by applying pattern1 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 90. STM32L05xxx/06xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 32 MHz with

RCC HSI enabled
HSI 16 MHz as clock source.
Power - Voltage range is set to Voltage Range 1.
4 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware
Common to all 4 Kbyte starting from address 0x1FF00000,
System memory -
bootloaders contain the bootloader firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
Once initialized the USART1 configuration
USART1 Enabled
is: 8-bits, even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration
USART2 Enabled
is: 8-bits, even parity and 1 Stop bit
USART2
bootloader USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloaders.

206/307 AN2606 Rev 36

AN2606 STM32L05xxx/06xxx devices bootloader

Table 90. STM32L05xxx/06xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI1 configuration is:

Slave mode, Full Duplex, 8-bit MSB, Speed
SPI1 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PA7 pin: Slave data Input line, used in
SPI1_MOSI pin Input
Push-pull pull-down mode
SPI1 bootloader
PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
Push-pull pull-down mode
PA5 pin: Slave clock line, used in Push-pull
SPI1_SCK pin Input
pull-down mode
PA4 pin: slave chip select pin used in Push-
SPI1_NSS pin Input
pull pull-down mode.
The SPI2 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed
SPI2 Enabled
up to 8 MHz, Polarity: CPOL Low, CPHA
Low, NSS hardware.
PB15 pin: Slave data Input line, used in
SPI2_MOSI pin Input
Push-pull pull-down mode
SPI2 bootloader
PB14 pin: Slave data output line, used in
SPI2_MISO pin Output
Push-pull pull-down mode
PB13 pin: Slave clock line, used in Push-
SPI2_SCK pin Input
pull pull-down mode
PB12 pin: slave chip select pin used in
SPI2_NSS pin Input
Push-pull pull-down mode.

The system clock is derived from the embedded internal high-speed RC for all bootloader
interfaces. No external quartz is required for bootloader operations.

AN2606 Rev 36 207/307

306
STM32L05xxx/06xxx devices bootloader AN2606

43.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 53. Bootloader selection for STM32L05xxx/06xxx

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43.3 Bootloader version

The following table lists the STM32L05xxx/06xxx devices bootloader versions:

Table 91. STM32L05xxx/06xxx bootloader versions

Bootloader
version Description Known limitations
number

V12.0 Initial bootloader version None

208/307 AN2606 Rev 36

AN2606 STM32L07xxx/08xxx devices bootloader

44 STM32L07xxx/08xxx devices bootloader

Two bootloader versions are available on STM32L07xxx/08xxx devices:

• V4.x supporting USART1, USART2 and DFU (USB FS Device).
This version is embedded in STM32L072xx/73xx and STM32L082xx/83xx devices.
• V11.x supporting USART1, USART2, I2C1, I2C2, SPI1 and SPI2.
This version is embedded in other STM32L071xx/081xx devices.

44.1 Bootloader V4.x

44.1.1 Bootloader configuration

The STM32L07xxx/08xxx bootloader is activated by applying pattern2 or pattern7 when
dual bank boot feature is available (described in Table 2: Bootloader activation patterns).
The Table 92 shows the hardware resources used by this bootloader.

Table 92. STM32L07xxx/08xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 32 MHz with

RCC HSI enabled
HSI 16 MHz as clock source.
4 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
8 Kbyte starting from address 0x1FF00000,
Common to all System memory -
contain the bootloader firmware.
bootloaders
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware
IWDG option was previously enabled by the
user).
Once initialized the USART1 configuration
USART1 Enabled
is: 8-bits, even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART2 in reception mode
USART1_TX pin Output PA9 pin: USART2 in transmission mode
Once initialized the USART2 configuration
USART2 Enabled
is: 8-bits, even parity and 1 Stop bit
USART2
bootloader USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
USARTx Used to automatically detect the serial baud
SysTick timer Enabled
bootloaders rate from the host for USARTx bootloaders.

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306
STM32L07xxx/08xxx devices bootloader AN2606

Table 92. STM32L07xxx/08xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

USB FS configured in forced device mode.

USB Enabled USB FS interrupt vector is enabled and
used for USB DFU communications.
DFU bootloader
USB_DM pin PA11 pin: USB FS DM line
Input/Output PA12 pin: USB FS DP line.
USB_DP pin
No external Pull-up resistor is required.

The system clock is derived from the embedded internal high-speed RC for all bootloader
interfaces. No external quartz is required for bootloader operations.

210/307 AN2606 Rev 36

AN2606 STM32L07xxx/08xxx devices bootloader

44.1.2 Bootloader selection

The Figure 54 and Figure 55 show the bootloader selection mechanism.

Figure 54. Dual Bank Boot Implementation for STM32L07xxx/08xxx bootloader V4.x

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AN2606 Rev 36 211/307

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STM32L07xxx/08xxx devices bootloader AN2606

Figure 55. Bootloader V4.x selection for STM32L07xxx/08xxx

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44.1.3 Bootloader version

The Table 93 lists the STM32L07xxx/08xxx devices bootloader versions:

Table 93. STM32L07xxx/08xxx bootloader versions

Bootloader version number Description Known limitations

V4.0 Initial bootloader version None

This bootloader is an updated
version of bootloader V4.0. This
V4.1 None
new version implements the
Dual Bank Boot feature.

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AN2606 STM32L07xxx/08xxx devices bootloader

44.2 Bootloader V11.x

44.2.1 Bootloader configuration

The STM32L07xxx/08xxx bootloader is activated by applying pattern2 or pattern7 when
dual bank boot feature is available (described in Table 2: Bootloader activation patterns).
The Table 94 shows the hardware resources used by this bootloader.

Table 94. STM32L07xxx/08xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 32 MHz

RCC HSI enabled
with HSI 16 MHz as clock source.
5 Kbyte starting from address
RAM - 0x20000000 are used by the bootloader
firmware
8 Kbyte starting from address
Common to all System memory - 0x1FF00000, contain the bootloader
bootloaders firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
Once initialized the USART1
USART1 Enabled configuration is: 8-bits, even parity and
USART1 1 Stop bit
bootloader USART1_RX pin Input PA10 pin: USART2 in reception mode
USART1_TX pin Output PA9 pin: USART2 in transmission mode
Once initialized the USART2
USART2 Enabled configuration is: 8-bits, even parity and
USART2 1 Stop bit
bootloader USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
USARTx Used to automatically detect the serial
bootloaders SysTick timer Enabled baud rate from the host for USARTx
bootloaders.

The I2C1 configuration is:

I2C speed: up to 400 KHz, 7-bit
I2C1 Enabled address, slave mode, analog filter ON.
Slave 7-bit address: 0b1000010x
I2C1 bootloader (where x = 0 for write and x = 1 for read)
PB6 pin: I2C1 clock line is used in
I2C1_SCL pin Input/Output
open-drain mode.
PB7 pin: I2C1 data line is used in open-
I2C1_SDA pin Input/Output
drain mode.

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Table 94. STM32L07xxx/08xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C2 configuration is:

I2C speed: up to 400 KHz, 7-bit
I2C2 Enabled address, slave mode, analog filter ON.
Slave 7-bit address: 0b1000010x
I2C2 bootloader (where x = 0 for write and x = 1 for read)
PB10 pin: I2C2 clock line is used in
I2C2_SCL pin Input/Output
open-drain mode.
PB11 pin: I2C2 data line is used in
I2C2_SDA pin Input/Output
open-drain mode.
The SPI1 configuration is:
Slave mode, Full Duplex, 8-bit MSB,
SPI1 Enabled
Speed up to 8 MHz, Polarity: CPOL
Low, CPHA Low, NSS hardware.
PA7 pin: Slave data Input line, used in
SPI1_MOSI pin Input
Push-pull pull-down mode
SPI1 bootloader PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
Push-pull pull-down mode
PA5 pin: Slave clock line, used in Push-
SPI1_SCK pin Input
pull pull-down mode
PA4 pin: slave chip select pin used in
Push-pull pull-up mode.
SPI1_NSS pin Input
Note: This IO can be tied to Gnd if the
SPI Master does not use it.
The SPI2 configuration is:
Slave mode, Full Duplex, 8-bit MSB,
SPI2 Enabled
Speed up to 8 MHz, Polarity: CPOL
Low, CPHA Low, NSS hardware.
PB15 pin: Slave data Input line, used in
SPI2_MOSI pin Input
Push-pull pull-down mode
SPI2 bootloader PB14 pin: Slave data output line, used
SPI2_MISO pin Output
in Push-pull pull-down mode
PB13 pin: Slave clock line, used in
SPI2_SCK pin Input
Push-pull pull-down mode
PB12 pin: slave chip select pin used in
Push-pull pull-up mode.
SPI2_NSS pin Input
Note: This IO can be tied to GND if the
SPI Master does not use it.

The system clock is derived from the embedded internal high-speed RC for all bootloader
interfaces. No external quartz is required for bootloader operations.

214/307 AN2606 Rev 36

AN2606 STM32L07xxx/08xxx devices bootloader

44.2.2 Bootloader selection

The Figure 56 and Figure 57 show the bootloader selection mechanism.

Figure 56. Dual Bank Boot Implementation for STM32L07xxx/08xxx bootloader V11.x

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STM32L07xxx/08xxx devices bootloader AN2606

Figure 57. Bootloader V11.x selection for STM32L07xxx/08xxx

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216/307 AN2606 Rev 36

AN2606 STM32L07xxx/08xxx devices bootloader

44.2.3 Bootloader version

The following table lists the STM32L07xxx/08xxx devices bootloader versions:

Table 95. STM32L07xxx/08xxx bootloader V11.x versions

Bootloader version number Description Known limitations

V11.1 Initial bootloader version None

This bootloader is an updated
version of bootloader V11.1.
V11.2 None
This new version implements
the Dual Bank Boot feature.

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STM32L1xxx6(8/B)A devices bootloader AN2606

45 STM32L1xxx6(8/B)A devices bootloader

45.1 Bootloader configuration

The STM32L1xxx6(8/B)A bootloader is activated by applying pattern1 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 96. STM32L1xxx6(8/B)A configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

RCC HSI enabled The system clock frequency is 16 MHz.

2 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
4 Kbyte starting from address 0x1FF00000
System memory -
contain the bootloader firmware.
Common to all
The independent watchdog (IWDG)
bootloaders
prescaler is configured to its maximum
value and is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
Power - Voltage range is set to Voltage Range 1.
Once initialized, the USART1 configuration
USART1 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized, the USART2 configuration
USART2 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART2
bootloader USART2_RX pin Input PD6 pin: USART2 in reception mode
USART2_TX pin Output PD5 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host.

The system clock is derived from the embedded internal high-speed RC, no external quartz
is required for the bootloader execution.

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AN2606 STM32L1xxx6(8/B)A devices bootloader

45.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 58. Bootloader selection for STM32L1xxx6(8/B)A devices

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45.3 Bootloader version

The following table lists the STM32L1xxx6(8/B)A devices bootloader versions:

Table 97. STM32L1xxx6(8/B)A bootloader versions

Bootloader
version Description Known limitations
number

When a Read Memory command or Write Memory

command is issued with an unsupported memory
address and a correct address checksum (ie. address
0x6000 0000), the command is aborted by the bootloader
V2.0 Initial bootloader version
device, but the NACK (0x1F) is not sent to the host. As a
result, the next 2 bytes (which are the number of bytes to
be read/written and its checksum) are considered as a
new command and its checksum.(1)
1. If the “number of data - 1” (N-1) to be read/written is not equal to a valid command code, then the limitation
is not perceived from the host since the command is NACKed anyway (as an unsupported new command).

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STM32L1xxx6(8/B) devices bootloader AN2606

46 STM32L1xxx6(8/B) devices bootloader

46.1 Bootloader configuration

The STM32L1xxx6(8/B) bootloader is activated by applying pattern1 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 98. STM32L1xxx6(8/B) configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

RCC HSI enabled The system clock frequency is 16 MHz.

2 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
4 Kbyte starting from address 0x1FF00000
System memory -
contain the bootloader firmware.
Common to all
The independent watchdog (IWDG)
bootloaders
prescaler is configured to its maximum
value and is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
Power - Voltage range is set to Voltage Range 1.
Once initialized, the USART1 configuration
USART1 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized, the USART2 configuration
USART2 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART2
bootloader USART2_RX pin Input PD6 pin: USART2 in reception mode
USART2_TX pin Output PD5 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host.

The system clock is derived from the embedded internal high-speed RC, no external quartz
is required for the bootloader execution.

220/307 AN2606 Rev 36

AN2606 STM32L1xxx6(8/B) devices bootloader

46.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 59. Bootloader selection for STM32L1xxx6(8/B) devices

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46.3 Bootloader version

The following table lists the STM32L1xxx6(8/B) devices bootloader versions:

Table 99. STM32L1xxx6(8/B) bootloader versions

Bootloader
version Description Known limitations
number

When a Read Memory command or Write Memory

command is issued with an unsupported memory
address and a correct address checksum (ie. address
0x6000 0000), the command is aborted by the bootloader
V2.0 Initial bootloader version
device, but the NACK (0x1F) is not sent to the host. As a
result, the next 2 bytes (which are the number of bytes to
be read/written and its checksum) are considered as a
new command and its checksum.(1)
1. If the “number of data - 1” (N-1) to be read/written is not equal to a valid command code, then the limitation
is not perceived from the host since the command is NACKed anyway (as an unsupported new command).

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STM32L1xxxC devices bootloader AN2606

47 STM32L1xxxC devices bootloader

47.1 Bootloader configuration

The STM32L1xxxC bootloader is activated by applying pattern1 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 100. STM32L1xxxC configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 16 MHz

using the HSI. This is used only for
USARTx bootloaders and during USB
HSI enabled
detection for DFU bootloader (once the
DFU bootloader is selected, the clock
source is derived from the external crystal).
The external clock is mandatory only for the
DFU bootloader and must be in the
RCC following range:
HSE enabled [24, 16, 12, 8, 6, 4, 3, 2] MHz.
The PLL is used to generate the USB
48 MHz clock and the 32 MHz clock for the
system clock.
The Clock Security System (CSS) interrupt
Common to all
is enabled for the DFU bootloader. Any
bootloaders -
failure (or removal) of the external clock
generates a system reset.
4 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
8 Kbyte starting from address 0x1FF00000
System memory -
contains the bootloader firmware.
The independent watchdog (IWDG)
prescaler is configured to its maximum
value and is periodically refreshed to
IWDG -
prevent watchdog resets (in case the
hardware IWDG option was previously
enabled by the user).
Power - Voltage range is set to Voltage Range 1.
Once initialized, the USART1 configuration
USART1 Enabled
is 8 bits, even parity and 1 stop bit.
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized, the USART2 configuration
USART2 Enabled is 8 bits, even parity and 1 stop bit. The
USART2 uses its remapped pins.
USART2 bootloader
USART2_RX pin Input PD6 pin: USART2 in reception mode
USART2_TX pin Output PD5 pin: USART2 in transmission mode

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AN2606 STM32L1xxxC devices bootloader

Table 100. STM32L1xxxC configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Used to automatically detect the serial baud

USARTx bootloaders SysTick timer Enabled rate from the host for the USARTx
bootloader.
USB Enabled USB used in FS mode
USB_DM pin PA11: USB DM line.
DFU bootloader
Input/Output PA12: USB DP line
USB_DP pin An external pull-up resistor 1.5 KOhm must
be connected to USB_DP pin.

The system clock is derived from the embedded internal high-speed RC for the USARTx
bootloader. This internal clock is also used the for DFU bootloader but only for the selection
phase. An external clock in the range of [24, 16, 12, 8, 6, 4, 3, 2] MHz is required for the
execution of the DFU bootloader after the selection phase.

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47.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 60. Bootloader selection for STM32L1xxxC devices

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47.3 Bootloader version

The following table lists the STM32L1xxxC devices bootloader versions:
Table 101. STM32L1xxxC bootloader versions
Bootloader version
Description Known limitations
number

For the USART interface, two consecutive NACKs

Initial bootloader instead of 1 NACK are sent when a Read Memory
V4.0
version or Write Memory command is sent and the RDP
level is active.

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AN2606 STM32L1xxxD devices bootloader

48 STM32L1xxxD devices bootloader

48.1 Bootloader configuration

The STM32L1xxxD bootloader is activated by applying pattern4 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 102. STM32L1xxxD configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 16 MHz

using the HSI. This is used only for
USARTx bootloaders and during USB
HSI enabled detection for DFU bootloader (once the
DFU bootloader is selected, the clock
source will be derived from the external
crystal).
The external clock is mandatory only for
DFU bootloader and it must be in the
RCC
following range: [24, 16, 12, 8, 6, 4, 3, 2]
HSE enabled MHz.
The PLL is used to generate the USB
48 MHz clock and the 32 MHz clock for the
system clock.
Common to all The Clock Security System (CSS) interrupt
bootloaders is enabled for the DFU bootloader. Any
-
failure (or removal) of the external clock
generates system reset.
4 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
8 Kbyte starting from address 0x1FF00000
System memory -
contains the bootloader firmware.
The independent watchdog (IWDG)
prescaler is configured to its maximum
value and is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
Power - Voltage range is set to Voltage Range 1.
Once initialized, the USART1 configuration
USART1 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode

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Table 102. STM32L1xxxD configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized, the USART2 configuration

USART2 Enabled is: 8 bits, even parity and 1 Stop bit. The
USART2 uses its remapped pins.
USART2 bootloader
USART2_RX pin Input PD6 pin: USART2 in reception mode
USART2_TX pin Output PD5 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloader.
USB Enabled USB used in FS mode
USB_DM pin PA11: USB DM line.
DFU bootloader
Input/Output PA12: USB DP line
USB_DP pin An external pull-up resistor 1.5 KOhm must
be connected to USB_DP pin.

The system clock is derived from the embedded internal high-speed RC for USARTx
bootloader. This internal clock is used also for DFU bootloader but only for the selection
phase. An external clock in the range of [24, 16, 12, 8, 6, 4, 3, 2] MHz is required for DFU
bootloader execution after the selection phase.

226/307 AN2606 Rev 36

AN2606 STM32L1xxxD devices bootloader

48.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 61. Bootloader selection for STM32L1xxxD devices

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306
STM32L1xxxD devices bootloader AN2606

48.3 Bootloader version

The following table lists the STM32L1xxxD devices bootloader versions:

Table 103. STM32L1xxxD bootloader versions

Bootloader version
Description Known limitations
number

– In the bootloader code the PA13

(JTMS/SWDIO) I/O output speed
is configured to 400 KHz, as
consequence some debugger can
not connect to the device in Serial
Wire mode when the bootloader is
running.
V4.1 Initial bootloader version – When the DFU bootloader is
selected, the RTC is reset and thus
all RTC information (calendar,
alarm, ...) will be lost including
backup registers. Note: When the
USART bootloader is selected
there is no change on the RTC
configuration (including backup
registers).
– Stack overflow by 8 bytes when
jumping to Bank1/Bank2 if BFB2=0
or when Read Protection level is
set to 2.
Workaround: the user code should
force in the startup file the top of
stack address before to jump to the
main program. This can be done in
the “Reset_Handler” routine.
Fix V4.1 limitations (available on – When the Stack of the user code is
V4.2
Rev.Z devices only.) placed outside the SRAM (ie. @
0x2000C000) the bootloader
cannot jump to that user code
which is considered invalid. This
might happen when using
compilers which place the stack at
a non-physical address at the top
of the SRAM (ie. @ 0x2000C000).
Workaround: place manually the
stack at a physical address.
– For the USART interface, two
Fix V4.2 limitations. consecutive NACKs (instead of 1
DFU interface robustness NACK) are sent when a Read
V4.5
enhancements (available on Rev.Y Memory or Write Memory
devices only). command is sent and the RDP
level is active.

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49 STM32L1xxxE devices bootloader

49.1 Bootloader configuration

The STM32L1xxxE bootloader is activated by applying pattern4 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 104. STM32L1xxxE configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 16 MHz

using the HSI. This is used only for
USARTx bootloaders and during USB
HSI enabled detection for DFU bootloader (once the
DFU bootloader is selected, the clock
source will be derived from the external
crystal).
The external clock is mandatory only for
DFU bootloader and it must be in the
RCC
following range: [24, 16, 12, 8, 6, 4, 3, 2]
HSE enabled MHz.
The PLL is used to generate the USB
48 MHz clock and the 32 MHz clock for the
system clock.
Common to all The Clock Security System (CSS) interrupt
bootloaders is enabled for the DFU bootloader. Any
-
failure (or removal) of the external clock
generates system reset.
4 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware.
8 Kbyte starting from address 0x1FF00000
System memory -
contains the bootloader firmware.
The independent watchdog (IWDG)
prescaler is configured to its maximum
value and is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
Power - Voltage range is set to Voltage Range 1.
Once initialized, the USART1 configuration
USART1 Enabled
is: 8 bits, even parity and 1 Stop bit.
USART1 bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode

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Table 104. STM32L1xxxE configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized, the USART2 configuration

USART2 Enabled is: 8 bits, even parity and 1 Stop bit. The
USART2 uses its remapped pins.
USART2 bootloader
USART2_RX pin Input PD6 pin: USART2 in reception mode
USART2_TX pin Output PD5 pin: USART2 in transmission mode
Used to automatically detect the serial baud
USARTx bootloaders SysTick timer Enabled
rate from the host for USARTx bootloader.
USB Enabled USB used in FS mode
USB_DM pin PA11: USB DM line.
DFU bootloader
Input/Output PA12: USB DP line
USB_DP pin An external pull-up resistor 1.5 KOhm must
be connected to USB_DP pin.

The system clock is derived from the embedded internal high-speed RC for USARTx
bootloader. This internal clock is used also for DFU bootloader but only for the selection
phase. An external clock in the range of [24, 16, 12, 8, 6, 4, 3, 2] MHz is required for DFU
bootloader execution after the selection phase.

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49.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 62. Bootloader selection for STM32L1xxxE devices

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49.3 Bootloader version

The following table lists the STM32L1xxxE devices bootloader versions:

Table 105. STM32L1xxxE bootloader versions

Bootloader version
Description Known limitations
number

For the USART interface, two

consecutive NACKs (instead of 1
V4.0 Initial bootloader version NACK) are sent when a Read
Memory or Write Memory command
is sent and the RDP level is active.

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50 STM32L412xx/L422xx devices bootloader

50.1 Bootloader configuration

The STM32L412xx/L422xx bootloader is activated by applying pattern6 (described in
Table 2: Bootloader activation patterns). The following table shows the hardware resources
used by this bootloader.

Table 106. STM32L412xx/422xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The HSI is used at startup as clock source for

HSI enabled system clock configured to 72 MHz and for USART,
I2C, SPI and USB bootloader operation.
RCC
The clock recovery system (CRS) is enabled for the
- DFU bootloader to allow USB to be clocked by
HSI48 48 MHz.
12 Kbyte starting from address 0x20000000 are
RAM -
used by the bootloader firmware

Common to all 28 Kbyte starting from address 0x1FFF0000, contain

System memory -
bootloaders the bootloader firmware
The independent watchdog (IWDG) prescaler is
configured to its maximum value. It is periodically
IWDG - refreshed to prevent watchdog reset (in case the
hardware IWDG option was previously enabled by
the user).
The DFU can’t be used to communicate with
bootloader if the voltage scaling range 2 is selected.
Power -
Bootloader firmware doesn’t configure voltage
scaling range value in PWR_CR1 register.
Once initialized the USART1 configuration is: 8-bits,
USART1 Enabled
even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration is: 8-bits,
USART2 Enabled
even parity and 1 Stop bit
USART2
bootloader USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Once initialized the USART3 configuration is: 8-bits,
USART3 Enabled
even parity and 1 Stop bit
USART3
bootloader USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode
USARTx Used to automatically detect the serial baud rate
SysTick timer Enabled
bootloaders from the host for USARTx bootloaders.

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Table 106. STM32L412xx/422xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C1 configuration is:

I2C speed: up to 1 MHz, 7-bit address, slave mode,
I2C1 Enabled analog filter ON.
Slave 7-bit address: 0b1010010x
I2C1 bootloader
(where x = 0 for write and x = 1 for read)
I2C1_SCL pin Input/Output PB6 pin: clock line is used in open-drain mode.
I2C1_SDA pin Input/Output PB7 pin: data line is used in open-drain mode.
The I2C2 configuration is:
I2C speed: up to 1 MHz, 7-bit address, slave mode,
I2C2 Enabled analog filter ON.
Slave 7-bit address: 0b1010010x
I2C2 bootloader
(where x = 0 for write and x = 1 for read)
I2C2_SCL pin Input/Output PB10 pin: clock line is used in open-drain mode.
I2C2_SDA pin Input/Output PB11 pin: data line is used in open-drain mode.
The I2C3 configuration is:
I2C speed: up to 1 MHz, 7-bit address, slave mode,
I2C3 Enabled analog filter ON.
Slave 7-bit address: 0b1010010x
I2C3 bootloader
(where x = 0 for write and x = 1 for read)
I2C3_SCL pin Input/Output PC0 pin: clock line is used in open-drain mode.
I2C3_SDA pin Input/Output PC1 pin: data line is used in open-drain mode.
The SPI1 configuration is:
– Slave mode
– Full Duplex
SPI1 Enabled
– 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS hardware.
PA7 pin: Slave data Input line, used in Push-pull pull-
SPI1_MOSI pin Input
down mode
SPI1 bootloader
PA6 pin: Slave data output line, used in Push-pull
SPI1_MISO pin Output
pull-down mode
PA5 pin: Slave clock line, used in Push-pull pull-
SPI1_SCK pin Input
down mode
PA4 pin: slave chip select pin used in Push-pull pull-
up mode.
SPI1_NSS pin Input
Note:This IO can be tied to Gnd if the SPI Master
does not use it.

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Table 106. STM32L412xx/422xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI2 configuration is:

– Slave mode
– Full Duplex
SPI2 Enabled
– 8-bit MSB
– Speed up to 8 MHz
Polarity: CPOL Low, CPHA Low, NSS hardware
PB15 pin: Slave data Input line, used in Push-pull
SPI2_MOSI pin Input
SPI2 bootloader pull-down mode
PB14 pin: Slave data output line, used in Push-pull
SPI2_MISO pin Output
pull-down mode
PB13 pin: Slave clock line, used in Push-pull pull-
SPI2_SCK pin Input
down mode
PB12 pin: slave chip select pin used in Push-pull
pull-up mode.
SPI2_NSS pin Input
Note:This IO can be tied to Gnd if the SPI Master
does not use it.
USB FS configured in forced device mode.
USB FS interrupt vector is enabled and used for
USB Enabled USB DFU communications.
Note: VDDUSB IO must be connected to
DFU bootloader 3.3V for USB to be operational.
USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
USB_DP pin
No external Pull-up resistor is required

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50.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 63.Bootloader V9.x selection for STM32L496xx/4A6xx

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50.3 Bootloader version

The Table 107 lists the STM32L412xx/422xx devices bootloader version.

Table 107.STM32L412xx/422xx bootloader versions

Bootloader
version Description Known limitations
number

On connection phase, USART responds with two

V13.1 Initial bootloader version
ACK bytes (0x79) instead of only one.

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51 STM32L43xxx/44xxx devices bootloader

51.1 Bootloader configuration

The bootloader V9.1 version is updated to fix known limitations relative to USB-DFU
interface, and is implemented on devices with version information ID equal to 0x10 (refer to
Table 109 for more details).
The STM32L43xxx/44xxx bootloader is activated by applying pattern6 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 108. STM32L43xxx/44xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The HSI is used at startup as clock source for

HSI enabled system clock configured to 60 MHz and for USART,
I2C, SPI and USB bootloader operation.
The clock recovery system (CRS) is enabled for the
- DFU bootloader to allow USB to be clocked by
HSI48 48 MHz.
RCC The HSE is used only when the CAN interface is
HSE enabled selected. The HSE must have one of the following
values [24,20,18,16,12,9,8,6,4] MHz.
The Clock Security System (CSS) interrupt is
enabled when HSE is enabled. Any failure (or
-
removal) of the external clock generates system
Common to all reset
bootloaders 12 Kbyte starting from address 0x20000000 are
RAM -
used by the bootloader firmware
28 Kbyte starting from address 0x1FFF0000, contain
System memory -
the bootloader firmware
The independent watchdog (IWDG) prescaler is
configured to its maximum value. It is periodically
IWDG - refreshed to prevent watchdog reset (in case the
hardware IWDG option was previously enabled by
the user).
The DFU can’t be used to communicate with
bootloader if the voltage scaling range 2 is selected.
Power -
Bootloader firmware doesn’t configure voltage
scaling range value in PWR_CR1 register.
Once initialized the USART1 configuration is: 8-bits,
USART1 Enabled
even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode

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Table 108. STM32L43xxx/44xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART2 configuration is: 8-bits,

USART2 Enabled
even parity and 1 Stop bit
USART2
bootloader USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Once initialized the USART3 configuration is: 8-bits,
USART3 Enabled
even parity and 1 Stop bit
USART3
bootloader USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode
USARTx
Used to automatically detect the serial baud rate
bootloaders SysTick timer Enabled
from the host for USARTx bootloaders.

The I2C1 configuration is:

I2C speed: up to 1 MHz, 7-bit address, slave mode,
I2C1 Enabled analog filter ON.
Slave 7-bit address: 0b1001000x
I2C1 bootloader
(where x = 0 for write and x = 1 for read)
I2C1_SCL pin Input/Output PB6 pin: clock line is used in open-drain mode.
I2C1_SDA pin Input/Output PB7 pin: data line is used in open-drain mode.
The I2C2 configuration is:
I2C speed: up to 1 MHz, 7-bit address, slave mode,
I2C2 Enabled analog filter ON.
Slave 7-bit address: 0b1001000x
I2C2 bootloader
(where x = 0 for write and x = 1 for read)
I2C2_SCL pin Input/Output PB10 pin: clock line is used in open-drain mode.
I2C2_SDA pin Input/Output PB11 pin: data line is used in open-drain mode.
The I2C3 configuration is:
I2C speed: up to 1 MHz, 7-bit address, slave mode,
I2C3 Enabled analog filter ON.
Slave 7-bit address: 0b1001000x
I2C3 bootloader
(where x = 0 for write and x = 1 for read)
I2C3_SCL pin Input/Output PC0 pin: clock line is used in open-drain mode.
I2C3_SDA pin Input/Output PC1 pin: data line is used in open-drain mode.

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Table 108. STM32L43xxx/44xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI1 configuration is:

– Slave mode
– Full Duplex
SPI1 Enabled
– 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS hardware.
PA7 pin: Slave data Input line, used in Push-pull pull-
SPI1_MOSI pin Input
down mode
SPI1 bootloader
PA6 pin: Slave data output line, used in Push-pull
SPI1_MISO pin Output
pull-down mode
PA5 pin: Slave clock line, used in Push-pull pull-
SPI1_SCK pin Input
down mode
PA4 pin: slave chip select pin used in Push-pull pull-
up mode.
SPI1_NSS pin Input
Note:This IO can be tied to Gnd if the SPI Master
does not use it.
The SPI2 configuration is:
– Slave mode
– Full Duplex
SPI2 Enabled
– 8-bit MSB
– Speed up to 8 MHz
Polarity: CPOL Low, CPHA Low, NSS hardware
PB15 pin: Slave data Input line, used in Push-pull
SPI2_MOSI pin Input
SPI2 bootloader pull-down mode
PB14 pin: Slave data output line, used in Push-pull
SPI2_MISO pin Output
pull-down mode
PB13 pin: Slave clock line, used in Push-pull pull-
SPI2_SCK pin Input
down mode
PB12 pin: slave chip select pin used in Push-pull
pull-up mode.
SPI2_NSS pin Input
Note:This IO can be tied to Gnd if the SPI Master
does not use it.
Once initialized the CAN1 configuration is:
CAN1 Enabled
Baudrate 125 kbps, 11 -bit identifier.
CAN1_RX pin Input PB8 pin: CAN1 in reception mode
CAN1 bootloader CAN1_TX pin Output PB9 pin: CAN1 in transmission mode
This timer is used to determine the value of the HSE.
TIM16 Enabled Once the HSE frequency is determined, the system
clock is configured to 60 MHz using PLL and HSE.

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Table 108. STM32L43xxx/44xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

USB FS configured in forced device mode.

USB FS interrupt vector is enabled and used for
USB Enabled USB DFU communications.
Note: VDDUSB IO must be connected to
DFU bootloader 3.3V for USB to be operational.
USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
USB_DP pin
No external Pull-up resistor is required

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51.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 64. Bootloader V9.x selection for STM32L43xxx/44xxx

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51.3 Bootloader version

The Table 109 lists the STM32L43xxx/44xxx devices bootloader versions.

Table 109.STM32L43xxx/44xxx bootloader versions

Bootloader
version Description Known limitations
number

Check the Version Information ID of your

STM32L43xxx/44xxx device, which can be read
at 0x1FFF6FF2 address.
Version Information ID equal to 0xFF:
– For memory write operations using DFU
interface: If the buffer size is larger than 256
bytes and not multiple of 8 bytes, the write
memory operation result is corrupted.
Workaround: if the file size is larger than 256
V9.1 Initial bootloader version bytes, add byte padding to align it on 8-bytes
multiple size.
– For the USB-DFU interface, the CRS (clock
recovery system) is not correctly configured
and this may lead to random USB
communication errors (depending on
temperature and voltage). In most case
communication error will manifest by a "Stall"
response to setup packets.
Version Information ID equal to 0x10: None

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STM32L45xxx/46xxx devices bootloader AN2606

52 STM32L45xxx/46xxx devices bootloader

52.1 Bootloader configuration

The STM32L45xxx/46xxx bootloader is activated by applying pattern6 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 110. STM32L45xxx/46xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The HSI is used at startup as clock source for

system clock configured to 72 MHz and for
HSI enabled
USART, I2C, SPI and USB bootloader
operation.
The clock recovery system (CRS) is
- enabled for the DFU bootloader to allow
USB to be clocked by HSI48 48 MHz.
RCC The system clock frequency is 60 MHz.
The HSE is used only when the CAN interface is
HSE enabled
selected . The HSE must have one of the
following values [24,20,18,16,12,9,8,6,4] MHz.
The Clock Security System (CSS) interrupt is
enabled when HSE is enabled. Any failure (or
-
Common to all removal) of the external clock generates system
reset
bootloaders
12 Kbyte starting from address 0x20000000 are
RAM -
used by the bootloader firmware
28 Kbyte starting from address 0x1FFF0000,
System memory -
contain the bootloader firmware
The independent watchdog (IWDG) prescaler is
configured to its maximum value. It is
IWDG - periodically refreshed to prevent watchdog reset
(in case the hardware IWDG option was
previously enabled by the user).
The DFU can’t be used to communicate with
bootloader if the voltage scaling range 2 is
Power - selected. Bootloader firmware doesn’t configure
voltage scaling range value in PWR_CR1
register.
Once initialized the USART1 configuration is: 8-
USART1 Enabled
bits, even parity and 1 Stop bit
USART1
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode

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Table 110. STM32L45xxx/46xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART2 configuration is: 8-

USART2 Enabled
bits, even parity and 1 Stop bit
USART2
bootloader USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Once initialized the USART3 configuration is: 8-
USART3 Enabled
bits, even parity and 1 Stop bit
USART3
bootloader USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode
USARTx Used to automatically detect the serial baud rate
SysTick timer Enabled
bootloaders from the host for USARTx bootloaders.

The I2C1 configuration is:

I2C speed: up to 1 MHz, 7-bit address, slave
I2C1 Enabled mode, analog filter ON.
Slave 7-bit address: 0b1001010x
I2C1 bootloader
(where x = 0 for write and x = 1 for read)
I2C1_SCL pin Input/Output PB6 pin: clock line is used in open-drain mode.
I2C1_SDA pin Input/Output PB7 pin: data line is used in open-drain mode.
The I2C2 configuration is:
I2C speed: up to 1 MHz, 7-bit address, slave
I2C2 Enabled mode, analog filter ON.
Slave 7-bit address: 0b1001010x
I2C2 bootloader
(where x = 0 for write and x = 1 for read)
I2C2_SCL pin Input/Output PB10 pin: clock line is used in open-drain mode.
I2C2_SDA pin Input/Output PB11 pin: data line is used in open-drain mode.
The I2C3 configuration is:
I2C speed: up to 1 MHz, 7-bit address, slave
I2C3 Enabled mode, analog filter ON.
Slave 7-bit address: 0b1001010x
I2C3 bootloader
(where x = 0 for write and x = 1 for read)
I2C3_SCL pin Input/Output PC0 pin: clock line is used in open-drain mode.
I2C3_SDA pin Input/Output PC1 pin: data line is used in open-drain mode.

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Table 110. STM32L45xxx/46xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI1 configuration is:

– Slave mode
– Full Duplex
SPI1 Enabled – 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS
hardware.
PA7 pin: Slave data Input line, used in Push-pull
SPI1 bootloader SPI1_MOSI pin Input
pull-down mode
PA6 pin: Slave data output line, used in Push-
SPI1_MISO pin Output
pull pull-down mode
PA5 pin: Slave clock line, used in Push-pull pull-
SPI1_SCK pin Input
down mode
PA4 pin: slave chip select pin used in Push-pull
pull-up mode.
SPI1_NSS pin Input
Note: This IO can be tied to Gnd if the SPI
Master does not use it.
The SPI2 configuration is:
– Slave mode
– Full Duplex
SPI2 Enabled – 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS
hardware.
PB15 pin: Slave data Input line, used in Push-
SPI2 bootloader SPI2_MOSI pin Input
pull pull-down mode
PB14 pin: Slave data output line, used in Push-
SPI2_MISO pin Output
pull pull-down mode
PB13 pin: Slave clock line, used in Push-pull
SPI2_SCK pin Input
pull-down mode
PB12 pin: slave chip select pin used in Push-
pull pull-up mode.
SPI2_NSS pin Input
Note: This IO can be tied to Gnd if the SPI
Master does not use it.
Once initialized the CAN1 configuration is:
CAN1 Enabled
Baudrate 125 kbps, 11 -bit identifier.
CAN1_RX pin Input PB8 pin: CAN1 in reception mode

CAN1 bootloader CAN1_TX pin Output PB9 pin: CAN1 in transmission mode
This timer is used to determine the value of the
HSE. Once the HSE frequency is determined,
TIM16 Enabled
the system clock is configured to 60 MHz using
PLL and HSE.

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Table 110. STM32L45xxx/46xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

USB FS configured in forced device mode.

USB FS interrupt vector is enabled and used for
USB Enabled USB DFU communications.
Note: VDDUSB IO must be connected to
DFU bootloader 3.3V for USB to be operational.
USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
USB_DP pin
No external Pull-up resistor is required

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52.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 65.Bootloader V9.x selection for STM32L45xxx/46xxx

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248/307 AN2606 Rev 36

AN2606 STM32L45xxx/46xxx devices bootloader

52.3 Bootloader version

Table 111 lists the STM32L45xxx/46xxx devices bootloader versions.

Table 111. STM32L45xxx/46xxx bootloader versions

Bootloader version number Description Known limitations

V9.2 Initial bootloader version None

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STM32L47xxx/48xxx devices bootloader AN2606

53 STM32L47xxx/48xxx devices bootloader

Two bootloader versions are available on STM32L47xxx/48xxx:

• V10.x supporting USART, I2C and DFU (USB FS Device).
This version is embedded in STM32L47xxx/48xxx rev. 2 and rev. 3 devices.
• V9.x supporting USART, I2C, SPI, CAN and DFU (USB FS Device).
This version is embedded in STM32L47xxx/48xxx rev. 4 devices.

53.1 Bootloader V10.x

53.1.1 Bootloader configuration

The STM32L47xxx/48xxx bootloader is activated by applying pattern7 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 112. STM32L47xxx/48xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment
The HSI is used at startup as clock source for system clock
HSI enabled configured to 24 MHz and for USART and I2C bootloader
operation.
The HSE is used only when the USB interface is selected
HSE enabled and the LSE is not present. The HSE must have one of the
following values [24,20,18,16,12,9,8,6,4] MHz.
The LSE is used to trim the MSI which is configured to 48
MHz as USB clock source. The LSE must be equal to
RCC LSE enabled
32,768 KHz. If the LSE is not detected, the HSE will be
used instead if USB is connected.
The MSI is configured to 48 MHz and will be used as USB
MSI enabled clock source. The MSI is used only if LSE is detected,
otherwise, HSE will be used if USB is connected.
Common to all The Clock Security System (CSS) interrupt is enabled
bootloaders - when LSE or HSE is enabled. Any failure (or removal) of
the external clock generates system reset.
12 Kbyte starting from address 0x20000000 are used by
RAM -
the bootloader firmware
28 Kbyte starting from address 0x1FFF0000, contain the
System memory -
bootloader firmware
The independent watchdog (IWDG) prescaler is configured
to its maximum value. It is periodically refreshed to prevent
IWDG -
watchdog reset (in case the hardware IWDG option was
previously enabled by the user).
The DFU can’t be used to communicate with bootloader if
the voltage scaling range 2 is selected. Bootloader
Power -
firmware doesn’t configure voltage scaling range value in
PWR_CR1 register.

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Table 112. STM32L47xxx/48xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment
Once initialized the USART1 configuration is: 8-bits, even
USART1 Enabled
USART1 parity and 1 Stop bit
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2 configuration is: 8-bits, even
USART2 Enabled
USART2 parity and 1 Stop bit
bootloader USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Once initialized the USART3 configuration is: 8-bits, even
USART3 Enabled
USART3 parity and 1 Stop bit
bootloader USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode
USARTx Used to automatically detect the serial baud rate from the
SysTick timer Enabled
bootloaders host for USARTx bootloaders.
The I2C1 configuration is:
I2C speed: up to 400 KHz, 7-bit address, slave mode,
I2C1 Enabled analog filter ON.
I2C1 bootloader Slave 7-bit address: 0b1000011x
(where x = 0 for write and x = 1 for read)
I2C1_SCL pin Input/Output PB6 pin: clock line is used in open-drain mode.
I2C1_SDA pin Input/Output PB7 pin: data line is used in open-drain mode.
The I2C2 configuration is:
I2C speed: up to 400 KHz, 7-bit address, slave mode,
I2C2 Enabled analog filter ON.
I2C2 bootloader Slave 7-bit address: 0b1000011x
(where x = 0 for write and x = 1 for read)
I2C2_SCL pin Input/Output PB10 pin: clock line is used in open-drain mode.
I2C2_SDA pin Input/Output PB11 pin: data line is used in open-drain mode.
The I2C3 configuration is:
I2C speed: up to 400 KHz, 7-bit address, slave mode,
I2C3 Enabled analog filter ON.
I2C3 bootloader Slave 7-bit address is 0b1000011x
(where x = 0 for write and x = 1 for read)
I2C3_SCL pin Input/Output PC0 pin: clock line is used in open-drain mode.
I2C3_SDA pin Input/Output PC1 pin: data line is used in open-drain mode.
USB Enabled USB OTG FS configured in forced device mode
USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
DFU bootloader USB_DP pin No external Pull-up resistor is required
This timer is used to determine the value of the HSE. Once
TIM17 Enabled the HSE frequency is determined, the system clock is
configured to 24 MHz using PLL and HSE.

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For USARTx and I2Cx bootloaders no external clock is required.

USB bootloader (DFU) requires either an LSE (low-speed external clock) or a HSE (high-
speed external clock) :
• In case, the LSE is present regardless the HSE presence, the MSI will be configured
and trimmed by the LSE to provide an accurate clock equal to 48 MHz which is the
clock source of the USB. The system clock is kept clocked to 24 MHz by the HSI.
• In case, the HSE is present, the system clock and USB clock will be configured
respectively to 24 MHz and 48 MHz with HSE as clock source.

252/307 AN2606 Rev 36

AN2606 STM32L47xxx/48xxx devices bootloader

53.1.2 Bootloader selection

The Figure 66 and Figure 67 show the bootloader selection mechanism.

Figure 66. Dual Bank Boot Implementation for STM32L47xxx/48xxx bootloader V10.x

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STM32L47xxx/48xxx devices bootloader AN2606

Figure 67.Bootloader V10.x selection for STM32L47xxx/48xxx

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254/307 AN2606 Rev 36

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53.1.3 Bootloader version

The following table lists the STM32L47xxx/48xxx devices bootloader V10.x versions:

Table 113. STM32L47xxx/48xxx bootloader V10.x versions

Bootloader
version Description Known limitations
number

For memory write operations using DFU interface:

If the buffer size is larger than 256 bytes and not
multiple of 8 bytes, the write memory operation
result is corrupted.
V10.1 Initial bootloader version Workaround: if the file size is larger than 256
bytes, add byte padding to align it on 8-bytes
multiple size.
Write in SRAM is corrupted.
For memory write operations using DFU interface:
If the buffer size is larger than 256 bytes and not
multiple of 8 bytes, the write memory operation
V10.2 Fix write in SRAM issue result is corrupted.
Workaround: if the file size is larger than 256
bytes, add byte padding to align it on 8-bytes
multiple size.
For memory write operations using DFU interface:
Add support of MSI as USB clock If the buffer size is larger than 256 bytes and not
source (MSI is trimmed by LSE). multiple of 8 bytes, the write memory operation
V10.3 Update dual bank boot feature to result is corrupted.
support the case when user stack Workaround: if the file size is larger than 256
is mapped in SRAM2. bytes, add byte padding to align it on 8-bytes
multiple size.

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53.2 Bootloader V9.x

53.2.1 Bootloader configuration

The STM32L47xxx/48xxx bootloader is activated by applying pattern7 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 114. STM32L47xxx/48xxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment
The HSI is used at startup as clock source for
HSI enabled system clock configured to 72 MHz and for
USART and I2C bootloader operation.
The HSE is used only when the USB interface
is selected and the LSE is not present. The
HSE must have one of the following values
HSE enabled
[24,20,18,16,12,8,6,4] MHz.
System is clocked at 72 MHz if USB is used or
60 MHz if CAN is used.
The LSE is used to trim the MSI which is
configured to 48 MHz as USB clock source.
RCC
LSE enabled The LSE must be equal to 32,768 KHz. If the
LSE is not detected, the HSE will be used
instead if USB is connected.
The MSI is configured to 48 MHz and will be
used as USB clock source. The MSI is used
MSI enabled
only if LSE is detected, otherwise, HSE will be
Common to all used if USB is connected.
bootloaders The Clock Security System (CSS) interrupt is
enabled when LSE or HSE is enabled. Any
CSS
failure (or removal) of the external clock
generates system reset.
13 Kbyte starting from address 0x20000000
RAM -
are used by the bootloader firmware
28 Kbyte starting from address 0x1FFF0000,
System memory -
contain the bootloader firmware
The independent watchdog (IWDG) prescaler
is configured to its maximum value. It is
IWDG - periodically refreshed to prevent watchdog
reset (in case the hardware IWDG option was
previously enabled by the user).
The DFU can’t be used to communicate with
bootloader if the voltage scaling range 2 is
Power - selected. Bootloader firmware doesn’t
configure voltage scaling range value in
PWR_CR1 register.
Once initialized the USART1 configuration is:
USART1 Enabled
USART1 8-bits, even parity and 1 Stop bit
bootloader USART1_RX pin Input PA10 pin: USART2 in reception mode
USART1_TX pin Output PA9 pin: USART2 in transmission mode

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Table 114. STM32L47xxx/48xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment
Once initialized the USART2 configuration is:
USART2 Enabled
USART2 8-bits, even parity and 1 Stop bit
bootloader USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Once initialized the USART3 configuration is:
USART3 Enabled
USART3 8-bits, even parity and 1 Stop bit
bootloader USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode
USARTx Used to automatically detect the serial baud
SysTick timer Enabled
bootloaders rate from the host for USARTx bootloaders.
The I2C1 configuration is:
I2C speed: up to 400 KHz, 7-bit address, slave
I2C1 Enabled mode, analog filter ON. Slave 7-bit address:
I2C1 bootloader 0b1000011x (where x = 0 for write and x = 1 for
read)
I2C1_SCL pin Input/Output PB6 pin: clock line is used in open-drain mode.
I2C1_SDA pin Input/Output PB7 pin: data line is used in open-drain mode.
The I2C2 configuration is:
I2C speed: up to 400 KHz, 7-bit address, slave
I2C2 Enabled mode, analog filter ON. Slave 7-bit address:
0b1000011x (where x = 0 for write and x = 1 for
I2C2 bootloader read)
PB10 pin: clock line is used in open-drain
I2C2_SCL pin Input/Output
mode.
PB11 pin: data line is used in open-drain
I2C2_SDA pin Input/Output
mode.
The I2C3 configuration is:
I2C speed: up to 400 KHz, 7-bit address, slave
I2C3 Enabled mode, analog filter ON. Slave 7-bit address:
I2C3 bootloader 0b1000011x (where x = 0 for write and x = 1 for
read)
I2C3_SCL pin Input/Output PC0 pin: clock line is used in open-drain mode.
I2C3_SDA pin Input/Output PC1 pin: data line is used in open-drain mode.
The SPI1 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed up
SPI1 Enabled
to 8 MHz, Polarity: CPOL Low, CPHA Low,
NSS hardware.
PA7 pin: Slave data Input line, used in Push-
SPI1_MOSI pin Input
pull pull-down mode
SPI1 bootloader
PA6 pin: Slave data output line, used in Push-
SPI1_MISO pin Output
pull pull-down mode
PA5 pin: Slave clock line, used in Push-pull
SPI1_SCK pin Input
pull-down mode
PA4 pin: slave chip select pin used in Push-
SPI1_NSS pin Input
pull pull-down mode.

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Table 114. STM32L47xxx/48xxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment
The SPI2 configuration is:
Slave mode, Full Duplex, 8-bit MSB, Speed up
SPI2 Enabled
to 8 MHz, Polarity: CPOL Low, CPHA Low,
NSS hardware
PB15 pin: Slave data Input line, used in Push-
SPI2_MOSI pin Input
pull pull-down mode
SPI2 bootloader
PB14 pin: Slave data output line, used in Push-
SPI2_MISO pin Output
pull pull-down mode
PB13 pin: Slave clock line, used in Push-pull
SPI2_SCK pin Input
pull-down mode
PB12 pin: slave chip select pin used in Push-
SPI2_NSS pin Input
pull pull-down mode.
Once initialized the CAN1 configuration is:
CAN1 Enabled
Baudrate 125 kbps, 11-bit identifier.
CAN1 bootloader
CAN1_RX pin Input PB8 pin: CAN1 in reception mode
CAN1_TX pin Output PB9 pin: CAN1 in transmission mode
USB FS configured in forced device mode.
USB FS interrupt vector is enabled and used
USB Enabled for USB DFU communications.
Note: VDDUSB IO must be connected to 3.3V
DFU bootloader for USB to be operational.
USB_DM pin PA11 pin: USB FS DM line
Input/Output PA12 pin: USB FS DP line.
USB_DP pin
No external Pull-up resistor is required.

In case, the HSE is present, the system clock and USB clock will be configured respectively
to 72 MHz and 48 MHz with PLL (clocked by HSE) as a clock source.

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AN2606 STM32L47xxx/48xxx devices bootloader

53.2.2 Bootloader selection

The Figure 68 and Figure 69 show the bootloader selection mechanism.

Figure 68. Dual Bank Boot Implementation for STM32L47xxx/48xxx bootloader V9.x

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STM32L47xxx/48xxx devices bootloader AN2606

Figure 69.Bootloader V9.x selection for STM32L47xxx/48xxx

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260/307 AN2606 Rev 36

AN2606 STM32L47xxx/48xxx devices bootloader

53.2.3 Bootloader version

The following table lists the STM32L47xxx/48xxx devices bootloader V9.x versions:

Table 115. STM32L47xxx/48xxx bootloader V9.x versions

Bootloader
version Description Known limitations
number

For memory write operations using DFU interface:

If the buffer size is larger than 256 bytes and not
multiple of 8 bytes, the write memory operation
result is corrupted.
V9.0 Initial bootloader version Workaround: if the file size is larger than 256
bytes, add byte padding to align it on 8-bytes
multiple size.
Write in SRAM is corrupted
V9.1 Deprecated version (not used) None
For memory write operations using DFU interface:
If the buffer size is larger than 256 bytes and not
multiple of 8 bytes, the write memory operation
V9.2 Fix write in SRAM issue result is corrupted.
Workaround: if the file size is larger than 256
bytes, add byte padding to align it on 8-bytes
multiple size.

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STM32L496xx/4A6xx devices bootloader AN2606

54 STM32L496xx/4A6xx devices bootloader

54.1 Bootloader configuration

The STM32L496xx/4A6xx bootloader is activated by applying pattern6 (described in
Table 2: Bootloader activation patterns). The Table 116 shows the hardware resources used
by this bootloader.

Table 116. STM32L496xx/4A6xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The HSI is used at startup as clock

source for system clock configured to 72
HSI enabled
MHz and for USART, I2C and SPI
bootloader operation.
The clock recovery system (CRS) is
- enabled for the DFU bootloader to allow
USB to be clocked by HSI 48 MHz.
RCC The HSE is used only when the CAN
interface is selected . The HSE must
HSE enabled
have one of the following value
[24,20,18,16,12,9,8,6,4] MHz.
The Clock Security System (CSS)
interrupt is enabled when HSE is
-
enabled. Any failure (or removal) of the
external clock generates system reset
Common to all 12 Kbyte starting from address
bootloaders RAM - 0x20000000 are used by the bootloader
firmware
28 Kbyte starting from address
System memory - 0x1FFF0000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
The DFU can’t be used to communicate
with bootloader if the voltage scaling
Power - range 2 is selected. Bootloader firmware
doesn’t configure voltage scaling range
value in PWR_CR1 register.
Once initialized the USART1
USART1 Enabled configuration is: 8-bits, even parity and 1
USART1 Stop bit
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode

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AN2606 STM32L496xx/4A6xx devices bootloader

Table 116. STM32L496xx/4A6xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART2

USART2 Enabled configuration is: 8-bits, even parity and 1
USART2 Stop bit
bootloader USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Once initialized the USART3
USART3 Enabled configuration is: 8-bits, even parity and 1
USART3 Stop bit
bootloader
USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode
USARTx Used to automatically detect the serial
bootloaders SysTick timer Enabled baud rate from the host for USARTx
bootloaders.

The I2C1 configuration is:

I2C speed: up to 1 MHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1001100x (where
I2C1 bootloader x = 0 for write and x = 1 for read)
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.
The I2C2 configuration is:
I2C speed: up to 1 MHz, 7-bit address,
I2C2 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1001100x (where
I2C2 bootloader x = 0 for write and x = 1 for read)
PB10 pin: clock line is used in open-drain
I2C2_SCL pin Input/Output
mode.
PB11 pin: data line is used in open-drain
I2C2_SDA pin Input/Output
mode.
The I2C3 configuration is:
I2C speed: up to 1 MHz, 7-bit address,
I2C3 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1001100x (where
I2C3 bootloader x = 0 for write and x = 1 for read)
PC0 pin: clock line is used in open-drain
I2C3_SCL pin Input/Output
mode.
PC1 pin: data line is used in open-drain
I2C3_SDA pin Input/Output
mode.

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STM32L496xx/4A6xx devices bootloader AN2606

Table 116. STM32L496xx/4A6xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The SPI1 configuration is:

– Slave mode
– Full Duplex
SPI1 Enabled – 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS
hardware.
PA7 pin: Slave data Input line, used in
SPI1 bootloader SPI1_MOSI pin Input
Push-pull pull-down mode
PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
Push-pull pull-down mode
PA5 pin: Slave clock line, used in Push-
SPI1_SCK pin Input
pull pull-down mode
PA4 pin: slave chip select pin used in
Push-pull pull-down mode.
SPI1_NSS pin Input
Note: This IO can be tied to Gnd if the
SPI Master does not use it.
The SPI2 configuration is:
– Slave mode
– Full Duplex
SPI2 Enabled – 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS
hardware.
PB15 pin: Slave data Input line, used in
SPI2 bootloader SPI2_MOSI pin Input
Push-pull pull-down mode
PB14 pin: Slave data output line, used in
SPI2_MISO pin Output
Push-pull pull-down mode
PB13 pin: Slave clock line, used in Push-
SPI2_SCK pin Input
pull pull-down mode
PB12 pin: slave chip select pin used in
Push-pull pull-down mode.
SPI2_NSS pin Input
Note: This IO can be tied to GND if the
SPI Master does not use it.
Once initialized the CAN1 configuration
CAN1 Enabled is:
Baudrate 125 kbps, 11 -bit identifier.
CAN1_RX pin Input PB8 pin: CAN1 in reception mode

CAN1 bootloader CAN1_TX pin Output PB9 pin: CAN1 in transmission mode
This timer is used to determine the value
of the HSE. Once the HSE frequency is
TIM16 Enabled determined, the system clock is
configured to 60 MHz using PLL and
HSE.

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AN2606 STM32L496xx/4A6xx devices bootloader

Table 116. STM32L496xx/4A6xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

USB OTG FS configured in forced device

mode.
USB OTG FS interrupt vector is enabled
USB Enabled
and used for USB DFU communications.
Note: VDDUSB IO must be connected to
DFU bootloader
3.3V for USB to be operational.
USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
USB_DP pin
No external Pull-up resistor is required

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STM32L496xx/4A6xx devices bootloader AN2606

54.2 Bootloader selection

The Figure 70 shows the bootloader selection mechanism.

Figure 70.Bootloader V9.x selection for STM32L496xx/4A6xx

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266/307 AN2606 Rev 36

AN2606 STM32L496xx/4A6xx devices bootloader

54.3 Bootloader version

The Table 117 lists the STM32L496xx/4A6xx devices bootloader versions.

Table 117.STM32L496xx/4A6xx bootloader version

Bootloader
version Description Known limitations
number

The Bank Erase command is aborted by the

bootloader device, and the NACK (0x1F) is sent
V9.3 Initial bootloader version to the host. Workaround: Perform Bank erase
operation through page erase using the Erase
command (0x44).

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STM32L4Rxxx/4Sxxx devices bootloader AN2606

55 STM32L4Rxxx/4Sxxx devices bootloader

55.1 Bootloader configuration

The STM32L4Rxx/4Sxx bootloader is activated by applying pattern6 (described in Table 2:
Bootloader activation patterns). The Table 118 shows the hardware resources used by this
bootloader.

Table 118. STM32L4Rxxx/4Sxxx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The HSI is used at startup as clock

source for system clock configured to 60
HSI enabled
MHz and for USART, I2C, SPI and USB
bootloader operation.
The clock recovery system (CRS) is
- enabled for the DFU bootloader to allow
USB to be clocked by HSI 48 MHz.
RCC
The HSE is used only when the CAN
interface is selected . The HSE must
HSE enabled
have one of the following value
[24,20,18,16,12,9,8,6,4] MHz.
The Clock Security System (CSS)
interrupt is enabled when HSE is
-
enabled. Any failure (or removal) of the
external clock generates system reset
Common to all 12 Kbytes starting from address
bootloaders RAM - 0x20000000 are used by the bootloader
firmware
28672 bytes starting from address
System memory - 0x1FFF0000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
The DFU can’t be used to communicate
with bootloader if the voltage scaling
range 2 is selected. Bootloader firmware
Power - doesn’t configure voltage scaling range
value in
PWR_CR1 register.

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AN2606 STM32L4Rxxx/4Sxxx devices bootloader

Table 118. STM32L4Rxxx/4Sxxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the USART1

USART1 Enabled configuration is: 8-bits, even parity and 1
USART1 Stop bit
bootloader USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
Once initialized the USART2
USART2 Enabled configuration is: 8-bits, even parity and 1
USART2 Stop bit
bootloader
USART2_RX pin Input PA3 pin: USART2 in reception mode
USART2_TX pin Output PA2 pin: USART2 in transmission mode
Once initialized the USART3
USART3 Enabled configuration is: 8-bits, even parity and 1
USART3 Stop bit
bootloader USART3_RX pin Input PC11 pin: USART3 in reception mode
USART3_TX pin Output PC10 pin: USART3 in transmission mode
USARTx Used to automatically detect the serial
bootloaders SysTick timer Enabled baud rate from the host for USARTx
bootloaders.

The I2C1 configuration is:

I2C speed: up to 1 MHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1010000x
I2C1 bootloader (where x = 0 for write and x = 1 for read)
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.
The I2C2 configuration is:
I2C speed: up to 1 MHz, 7-bit address,
I2C2 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1010000x
I2C2 bootloader (where x = 0 for write and x = 1 for read)
PB10 pin: clock line is used in open-drain
I2C2_SCL pin Input/Output
mode.
PB11 pin: data line is used in open-drain
I2C2_SDA pin Input/Output
mode.

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STM32L4Rxxx/4Sxxx devices bootloader AN2606

Table 118. STM32L4Rxxx/4Sxxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C3 configuration is:

I2C speed: up to 1 MHz, 7-bit address,
I2C3 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1010000x
I2C3 bootloader (where x = 0 for write and x = 1 for read)
PC0 pin: clock line is used in open-drain
I2C3_SCL pin Input/Output
mode.
PC1 pin: data line is used in open-drain
I2C3_SDA pin Input/Output
mode.
The SPI1 configuration is:
– Slave mode
– Full Duplex
SPI1 Enabled – 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS
hardware.
PA7 pin: Slave data Input line, used in
SPI1 bootloader SPI1_MOSI pin Input
Push-pull pull-down mode
PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
Push-pull pull-down mode
PA5 pin: Slave clock line, used in Push-
SPI1_SCK pin Input
pull pull-down mode
PA4 pin: slave chip select pin used in
Push-pull pull-up mode.
SPI1_NSS pin Input
Note:This IO can be tied to Gnd if the SPI
Master does not use it.
The SPI2 configuration is:
– Slave mode
– Full Duplex
SPI2 Enabled – 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS
hardware.
PB15 pin: Slave data Input line, used in
SPI2 bootloader SPI2_MOSI pin Input
Push-pull pull-down mode
PB14 pin: Slave data output line, used in
SPI2_MISO pin Output
Push-pull pull-down mode
PB13 pin: Slave clock line, used in Push-
SPI2_SCK pin Input
pull pull-down mode
PB12 pin: slave chip select pin used in
Push-pull pull-up mode.
SPI2_NSS pin Input
Note:This IO can be tied to Gnd if the SPI
Master does not use it.

270/307 AN2606 Rev 36

AN2606 STM32L4Rxxx/4Sxxx devices bootloader

Table 118. STM32L4Rxxx/4Sxxx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

Once initialized the CAN1 configuration

CAN1 Enabled is:
Baudrate 125 kbps, 11 -bit identifier.
CAN1_RX pin Input PB8 pin: CAN1 in reception mode

CAN1 bootloader CAN1_TX pin Output PB9 pin: CAN1 in transmission mode
This timer is used to determine the value
of the HSE. Once the HSE frequency is
TIM16 Enabled determined, the system clock is
configured to 60 MHz using PLL and
HSE.
USB FS configured in forced device
mode.
USB FS interrupt vector is enabled and
USB Enabled
used for USB DFU communications.
Note: VDDUSB IO must be connected to
DFU bootloader
3.3V for USB to be operational.
USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
USB_DP pin
No external Pull-up resistor is required

AN2606 Rev 36 271/307

306
STM32L4Rxxx/4Sxxx devices bootloader AN2606

55.2 Bootloader selection

The Figure 71 and Figure 72 show the bootloader selection mechanisms.

Figure 71. Dual bank boot implementation for STM32L4Rxxx/STM32L4Sxxx bootloader V9.x

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272/307 AN2606 Rev 36

AN2606 STM32L4Rxxx/4Sxxx devices bootloader

Figure 72.Bootloader V9.x selection for STM32L4Rxx/4Sxx

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AN2606 Rev 36 273/307

306
STM32L4Rxxx/4Sxxx devices bootloader AN2606

55.3 Bootloader version

The Table 119 lists the STM32L4Rxx/4Sxx devices bootloader versions.

Table 119.STM32L4Rxx/4Sxx bootloader versions

Bootloader
version Description Known limitations
number

V9.0 Initial bootloader version None

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AN2606 STM32WB55xx devices bootloader

56 STM32WB55xx devices bootloader

56.1 Bootloader configuration

The STM32WBxxx bootloader is activated by applying pattern6 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.

Table 120. STM32WB55xx configuration in system memory boot mode

Bootloader Feature/Peripheral State Comment

The system clock frequency is 64 MHz

MSI enabled
(using PLL clocked by MSI).
RCC The clock recovery system (CRS) is
- enabled for the DFU bootloader to allow
USB to be clocked by HSI 48 MHz.
20 Kbytes starting from address
RAM - 0x20000000 are used by the bootloader
Common to all firmware
bootloaders 28 Kbytes starting from address
System memory - 0x1FFF0000, contain the bootloader
firmware
The independent watchdog (IWDG)
prescaler is configured to its maximum
value. It is periodically refreshed to
IWDG -
prevent watchdog reset (in case the
hardware IWDG option was previously
enabled by the user).
Once initialized the USART1
USART1 Enabled configuration is: 8-bits, even parity and 1
USART1 Stop bit
bootloader
USART1_RX pin Input PA10 pin: USART1 in reception mode
USART1_TX pin Output PA9 pin: USART1 in transmission mode
The I2C1 configuration is:
I2C speed: up to 1 MHz, 7-bit address,
I2C1 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1010000x
I2C1 bootloader (where x = 0 for write and x = 1 for read)
PB6 pin: clock line is used in open-drain
I2C1_SCL pin Input/Output
mode.
PB7 pin: data line is used in open-drain
I2C1_SDA pin Input/Output
mode.

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STM32WB55xx devices bootloader AN2606

Table 120. STM32WB55xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

The I2C3 configuration is:

I2C speed: up to 1 MHz, 7-bit address,
I2C3 Enabled slave mode, analog filter ON.
Slave 7-bit address: 0b1010000x (where
I2C3 bootloader x = 0 for write and x = 1 for read)
PC0 pin: clock line is used in open-drain
I2C3_SCL pin Input/Output
mode.
PC1 pin: data line is used in open-drain
I2C3_SDA pin Input/Output
mode.
The SPI1 configuration is:
– Slave mode
– Full Duplex
SPI1 Enabled – 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS
hardware.
PA7 pin: Slave data Input line, used in
SPI1_MOSI pin Input
SPI1 bootloader Push-pull pull-down mode
PA6 pin: Slave data output line, used in
SPI1_MISO pin Output
Push-pull pull-down mode
PA5 pin: Slave clock line, used in Push-
SPI1_SCK pin Input
pull pull-down mode
PA4 pin: slave chip select pin used in
Push-pull pull-up mode.
SPI1_NSS pin Input
Note:This IO can be tied to Gnd if the SPI
Master does not use it.
The SPI2 configuration is:
– Slave mode
– Full Duplex
SPI2 Enabled – 8-bit MSB
– Speed up to 8 MHz
– Polarity: CPOL Low, CPHA Low, NSS
hardware.
PB15 pin: Slave data Input line, used in
SPI2 bootloader SPI2_MOSI pin Input
Push-pull pull-down mode
PB14 pin: Slave data output line, used in
SPI2_MISO pin Output
Push-pull pull-down mode
PB13 pin: Slave clock line, used in Push-
SPI2_SCK pin Input
pull pull-down mode
PB12 pin: slave chip select pin used in
Push-pull pull-up mode.
SPI2_NSS pin Input
Note:This IO can be tied to Gnd if the SPI
Master does not use it.

276/307 AN2606 Rev 36

AN2606 STM32WB55xx devices bootloader

Table 120. STM32WB55xx configuration in system memory boot mode (continued)

Bootloader Feature/Peripheral State Comment

USB FS configured in forced device

mode.
USB FS interrupt vector is enabled and
USB Enabled
used for USB DFU communications.
Note: VDDUSB IO must be connected to
DFU bootloader
3.3V for USB to be operational.
USB_DM pin PA11: USB DM line.
Input/Output PA12: USB DP line
USB_DP pin
No external Pull-up resistor is required

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STM32WB55xx devices bootloader AN2606

56.2 Bootloader selection

The figure below shows the bootloader selection mechanism.

Figure 73. Bootloader V13.0 selection for STM32WB55xx

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56.3 Bootloader version

Table 121.STM32WB55xx bootloader versions
Bootloader
version Description Known limitations
number

V13.5 Initial bootloader version None

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57 Device-dependent bootloader parameters

The bootloader protocol’s command set and sequences for each serial peripheral are the
same for all STM32 devices. However, some parameters depend on device and bootloader
version:
• PID (Product ID)
• Valid RAM memory addresses (RAM area used during bootloader execution is not
accessible) accepted by the bootloader when the Read Memory, Go and Write Memory
commands are requested.
• System Memory area.
The table below shows the values of these parameters for each STM32 device bootloader in
production.

Table 122. Bootloader device-dependent parameters

STM32 BL System
Device PID RAM memory
series ID memory

STM32F05xxx and
0x440 0x21 0x20000800 - 0x20001FFF
STM32F030x8 devices 0x1FFFEC00 - 0x1FFFF7FF
STM32F03xx4/6 0x444 0x10 0x20000800 - 0x20000FFF
STM32F030xC 0x442 0x52 0x20001800 - 0x20007FFF 0x1FFFD800 - 0x1FFFF7FF

F0 STM32F04xxx 0x445 0xA1 NA 0x1FFFC400 - 0x1FFFF7FF

STM32F070x6 0x445 0xA2 NA 0x1FFFC400 - 0x1FFFF7FF
STM32F070xB 0x448 0xA2 NA 0x1FFFC800 - 0x1FFFF7FF
STM32F071xx/072xx 0x448 0xA1 0x20001800 - 0x20003FFF 0x1FFFC800 - 0x1FFFF7FF
STM32F09xxx 0x442 0x50 NA 0x1FFFD800 - 0x1FFFF7FF
Low-density 0x412 NA 0x20000200 - 0x200027FF
Medium-
0x410 NA 0x20000200 - 0x20004FFF
density
High-density 0x414 NA 0x20000200 - 0x2000FFFF
STM32F10x
0x1FFFF000 - 0x1FFFF7FF
xx Medium-
F1 density value 0x420 0x10 0x20000200 - 0x20001FFF
line
High-density
0x428 0x10 0x20000200 - 0x20007FFF
value line
STM32F105xx/107xx 0x418 NA 0x20001000 - 0x2000FFFF 0x1FFFB000 - 0x1FFFF7FF
STM32F10xxx XL-density 0x430 0x21 0x20000800 - 0x20017FFF 0x1FFFE000 - 0x1FFFF7FF
0x20
F2 STM32F2xxxx 0x411 0x20002000 - 0x2001FFFF 0x1FFF0000 - 0x1FFF77FF
0x33

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Table 122. Bootloader device-dependent parameters (continued)

STM32 BL System
Device PID RAM memory
series ID memory

STM32F373xx 0x41 0x20001400 - 0x20007FFF

0x432
STM32F378xx 0x50 0x20001000 - 0x20007FFF
STM32F302xB(C)/303xB(C) 0x41
0x422 0x20001400 - 0x20009FFF
STM32F358xx 0x50
STM32F301xx/302x4(6/8) 0x40
F3 0x439 0x20001800 - 0x20003FFF 0x1FFFD800 - 0x1FFFF7FF
STM32F318xx 0x50
STM32F303x4(6/8)/
0x438 0x50 0x20001800 - 0x20002FFF
334xx/328xx
STM32F302xD(E)/303xD(E) 0x446 0x40 0x20001800 - 0x2000FFFF
STM32F398xx 0x446 0x50 0x20001800 - 0x2000FFFF
0x31 0x20002000 - 0x2001FFFF
STM32F40xxx/41xxx 0x413
0x90 0x20003000 - 0x2001FFFF
0x70
STM32F42xxx/43xxx 0x419 0x20003000 - 0x2002FFFF
0x91
STM32F401xB(C) 0x423 0xD1 0x20003000 - 0x2000FFFF
STM32F401xD(E) 0x433 0xD1 0x20003000 - 0x20017FFF
F4 0x1FFF0000 - 0x1FFF77FF
STM32F410xx 0x458 0xB1 0x20003000 - 0x20007FFF
STM32F411xx 0x431 0xD0 0x20003000 - 0x2001FFFF
STM32F412xx 0x441 0x90 0x20003000 - 0x2003FFFF
STM32F446xx 0x421 0x90 0x20003000 - 0x2001FFFF
STM32F469xx/479xx 0x434 0x90 0x20003000 - 0x2005FFFF
STM32F413xx/423xx 0x463 0x90 0x20003000 - 0x2004FFFF
STM32F72xxx/73xxx 0x452 0x90 0x20004000 - 0x2003FFFF 0x1FF00000 - 0x1FF0EDBF
0x70 0x20004000 - 0x2004FFFF 0x1FF00000 - 0x1FF0EDBF
F7 STM32F74xxx/75xxx 0x449
0x90 0x20004000 - 0x2004FFFF 0x1FF00000 - 0x1FF0EDBF
STM32F76xxx/77xxx 0x451 0x93 0x20004000 - 0x2007FFFF 0x1FF00000 - 0x1FF0EDBF
G0 STM32G07xxx/08xxx 0x460 0xB2 0x20000000 - 0x200026FF 0x1FFF0000 - 0x1FFF6FFF
0x20004100 - 0x2001FFFF
H7 STM32H74xxx/75xxx 0x450 0xD2 0x1FF00000 - 0x1FF1E7FF
0x24034000 - 0x2407FFFF
STM32L01xxx/02xxx 0x457 0xC3 NA 0x1FF00000 - 0x1FF00FFF
STM32L031xx/041xx 0x425 0xC0 0x20001000 - 0x20001FFF 0x1FF00000 - 0x1FF00FFF
L0 STM32L05xxx/06xxx 0x417 0xC0 0x20001000 - 0x20001FFF 0x1FF00000 - 0x1FF00FFF
0x41 0x20001000 - 0x20004FFF
STM32L07xxx/08xxx 0x447 0x1FF00000 - 0x1FF01FFF
0xB2 0x20001400 - 0x20004FFF

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Table 122. Bootloader device-dependent parameters (continued)

STM32 BL System
Device PID RAM memory
series ID memory

STM32L1xxx6(8/B) 0x416 0x20 0x20000800 - 0x20003FFF

STM32L1xxx6(8/B)A 0x429 0x20
0x20001000 - 0x20007FFF
L1 STM32L1xxxC 0x427 0x40 0x1FF00000 - 0x1FF01FFF
STM32L1xxxD 0x436 0x45 0x20001000 - 0x2000BFFF
STM32L1xxxE 0x437 0x40 0x20001000 - 0x20013FFF
STM32L43xxx/44xxx 0x435 0x91 0x20003100 - 0x2000BFFF 0x1FFF0000 - 0x1FFF6FFF
STM32L45xxx/46xxx 0x462 0x92 0x20003100 - 0x2001FFFF 0x1FFF0000 - 0x1FFF6FFF
0xA3 0x20003000 - 0x20017FFF
L4 STM32L47xxx/48xxx 0x415 0x1FFF0000 - 0x1FFF6FFF
0x92 0x20003100 - 0x20017FFF
STM32L496xx/4A6xx 0x461 0x93 0x20003100 - 0x2003FFFF 0x1FFF0000 - 0x1FFF6FFF
STM32L4Rxx/4Sxx 0x470 0x92 0x20003200 - 0x2009FFFF 0x1FFF0000 - 0x1FFF6FFF
WB STM32WB55xx 0x485 0xD5 0x20000000 – 0x20005000 0x1FFF0000 - 0x1FFF7000

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58 Bootloader timing

This section presents the typical timings of the bootloader firmware that should be used to
ensure correct synchronization between host and STM32 device.
Two types of timings will be described herein:
• STM32 device bootloader resources initialization duration.
• Communication interface selection duration.
After these timings the bootloader is ready to receive and execute host commands.

58.1 Bootloader Startup timing

After bootloader reset, the host should wait until the STM32 bootloader is ready to start
detection phase with a specific interface communication. This time corresponds to
bootloader startup timing, during which resources used by bootloader are initialized.

Figure 74. Bootloader Startup timing description

The table below contains the minimum startup timing for each STM32 product:

Table 123. Bootloader startup timings of STM32 devices

Minimum
Device bootloader Startup HSE Timeout (ms)
(ms)

STM32F03xx4/6 1.612 NA
STM32F05xxx and STM32F030x8 devices 1.612 NA
STM32F04xxx 0.058 NA
STM32F071xx/072xx 0.058 NA
HSE connected 3
STM32F070x6 200
HSE not connected 230

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Table 123. Bootloader startup timings of STM32 devices (continued)

Minimum
Device bootloader Startup HSE Timeout (ms)
(ms)

HSE connected 6
STM32F070xB 200
HSE not connected 230
STM32F09xxx 2 NA
STM32F10xxx 1.227 NA
PA9 pin low 1.396
STM32F105xx/107xx NA
PA9 pin high 524.376
STM32F10xxx XL-density 1.227 NA
V2.x 134 NA
STM32F2xxxx
V3.x 84.59 0.790
HSE connected 45
STM32F301xx/302x4(6/8) 560.5
HSE not connected 560.8
HSE connected 43.4
STM32F302xB(C)/303xB(C) 2.236
HSE not connected 2.36
HSE connected 7.53 NA
STM32F302xD(E)/303xD
HSE not connected 146.71 NA
STM32F303x4(6/8)/334xx/328xx 0.155 NA
STM32F318xx 0.182 NA
STM32F358xx 1.542 NA
HSE connected 43.4
STM32F373xx 2.236
HSE not connected 2.36
STM32F378xx 1.542 NA
STM32F398xx 1.72 NA
V3.x 84.59 0.790
STM32F40xxx/41xxx
V9.x 74 96
STM32F401xB(C) 74.5 85
STM32F401xD(E) 74.5 85
STM32F410xx 0.614 NA
STM32F411xx 74.5 85
STM32F412xx 0.614 180
STM32F413xx/423xx 0.642 165
V7.x 82 97
STM32F429xx/439xx
V9.x 74 97
STM32F446xx 73.61 96

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Table 123. Bootloader startup timings of STM32 devices (continued)

Minimum
Device bootloader Startup HSE Timeout (ms)
(ms)

STM32F469xx/479xx 73.68 230

STM32F72xxx/73xxx 17.93 50
STM32F74xxx/75xxx 16.63 50
STM32G07xxx/08xxx 0.390 NA
STM32H74xxx/75xxx 53.975 2
STM32L01xxx/02xxx 0.63 NA
STM32L031xx/041xx 0.62 NA
STM32L05xxx/06xxx 0.22 NA
V4.x 0.61 NA
STM32L07xxx/08xxx
V11.x 0.71 NA
STM32L1xxx6(8/B)A 0.542 NA
STM32L1xxx6(8/B) 0.542 NA
STM32L1xxxC 0.708 80
STM32L1xxxD 0.708 80
STM32L1xxxE 0.708 200
STM32L43xxx/44xxx 0.3335 100
STM32L45xxx/46xxx 50.93 NA
LSE connected 55
V10.x 100
LSE not connected 2560
STM32L47xxx/48xxx
LSE connected 55.40
V9.x 100
LSE not connected 2560.51
STM32L412xx/L422xx 0.12 NA
STM32L496xx/4A6xx 76.93 100
STM32L4Rxx/4Sxx NA NA
STM32WB55xx 0.390 NA

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58.2 USART connection timing

USART connection timing is the time that the host should wait for between sending the
synchronization data (0x7F) and receiving the first acknowledge response (0x79).

Figure 75. USART connection timing description

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1. Receiving any other character different from 0x7F (or line glitches) will cause bootloader to start
communication using a wrong baudrate. Bootloader measures the signal length between rising edge of first
1 bit in 0x7F to the falling edge of the last 1 bit in 0x7F to deduce the baudrate value
2. Bootloader does not re-align the calculated baudrate to standard baudrate values (ie. 1200, 9600, 115200,
...).

Note: For STM32F105xx/107xx line devices, PA9 pin (USB_VBUS) is used to detect the USB host
connection. The initialization of USB peripheral is performed only if PA9 is high at detection
phase which means that a host is connected to the port and delivering 5 V on the USB bus.
When PA9 level is high at detection phase, more time is required to initialize and shutdown
the USB peripheral. To minimize bootloader detection time when PA9 pin is not used, keep
PA9 state low during USART detection phase from the moment the device is reset till a
device ACK is sent.

Table 124. USART bootloader minimum timings of STM32 devices

USART
One USART byte USART
Device configuration
sending (ms) connection (ms)
(ms)

STM32F03xx4/6 0.078125 0.0064 0.16265

STM32F05xxx and STM32F030x8 devices 0.078125 0.0095 0.16575
STM32F04xxx 0.078125 0.007 0.16325
STM32F071xx/072xx 0.078125 0.007 0.16325
STM32F070x6 0.078125 0.014 0.17
STM32F070xB 0.078125 0.08 0.23

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Table 124. USART bootloader minimum timings of STM32 devices (continued)

USART
One USART byte USART
Device configuration
sending (ms) connection (ms)
(ms)

STM32F09xxx 0.078125 0.07 0.22

STM32F10xxx 0.078125 0.002 0.15825
PA9 pin low 0.007 0.16325
STM32F105xx/107xx 0.078125
PA9 pin High 105 105.15625
STM32F10xxx XL-density 0.078125 0.006 0.16225
V2.x
STM32F2xxxx 0.078125 0.009 0.16525
V3.x
HSE connected
STM32F301xx/302x4(6/8) 0.078125 0.002 0.15825
HSE not connected
HSE connected
STM32F302xB(C)/303xB(C) 0.078125 0.002 0.15825
HSE not connected
STM32F302xD(E)/303xD 0.078125 0.002 0.15885
STM32F303x4(6/8)/334xx/328xx 0.078125 0.002 0.15825
STM32F318xx 0.078125 0.002 0.15825
STM32F358xx 0.15625 0.001 0.3135
HSE connected
STM32F373xx 0.078125 0.002 0.15825
HSE not connected
STM32F378xx 0.15625 0.001 0.3135
STM32F398xx 0.078125 0.002 0.15885
V3.x 0.009 0.16525
STM32F40xxx/41xxx 0.078125
V9.x 0.0035 0.15975
STM32F401xB(C) 0.078125 0.00326 0.15951
STM32F401xD(E) 0.078125 0.00326 0.15951
STM32F410xx 0.078125 0.002 0.158
STM32F411xx 0.078125 0.00326 0.15951
STM32F412xx 0.078125 0.002 0.158
STM32F413xx/423xx 0.078125 0.002 0.158
V7.x 0.007 0.16325
STM32F429xx/439xx 0.078125
V9.x 0.00326 0.15951
STM32F446xx 0.078125 0.004 0.16
STM32F469xx/479xx 0.078125 0.003 0.159
STM32F72xxx/73xxx 0.078125 0.070 0.22
STM32F74xxx/75xxx 0.078125 0.065 0.22

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Table 124. USART bootloader minimum timings of STM32 devices (continued)

USART
One USART byte USART
Device configuration
sending (ms) connection (ms)
(ms)

STM32G07xxx/08xxx 0.078125 0.01 0.11

STM32H74xxx/75xxx 0.078125 0.072 0.22825
STM32L01xxx/02xxx 0.078125 0.016 0.17
STM32L031xx/041xx 0.078125 0.018 0.174
STM32L05xxx/06xxx 0.078125 0.018 0.17425
V4.x 0.078125 0.017 0.173
STM32L07xxx/08xxx
V11.x 0.078125 0.017 0.158
STM32L1xxx6(8/B)A 0.078125 0.008 0.16425
STM32L1xxx6(8/B) 0.078125 0.008 0.16425
STM32L1xxxC 0.078125 0.008 0.16425
STM32L1xxxD 0.078125 0.008 0.16425
STM32L1xxxE 0.078125 0.008 0.16425
STM32L412xx/L422xx 0.078125 0.005 0.2
STM32L43xxx/44xxx 0.078125 0.003 0.159
STM32L45xxx/46xxx 0.078125 0.07 0.22
V10.x 0.078125 0.003 0.159
STM32L47xxx/48xxx
V9.x 0.078125 0.003 0.159
STM32L496xx/4A6xx 0.078125 0.003 0.159
STM32L4Rxx/4Sxx NA NA NA
STM32WB55xx 0.078125 0.003 0.159

58.3 USB connection timing

USB connection timing is the time that the host should wait for between plugging the USB
cable and establishing a correct connection with the device. This timing includes
enumeration and DFU components configuration. USB connection depends on the host.

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Figure 76. USB connection timing description

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Note: For STM32F105xx/107xx devices, if the external HSE crystal frequency is different from
25 MHz (14.7456 MHz or 8 MHz), the device performs several unsuccessful enumerations
(with connect – disconnect sequences) before being able to establish a correct connection
with the host. This is due to the HSE automatic detection mechanism based on Start Of
Frame (SOF) detection.

Table 125. USB bootloader minimum timings of STM32 devices

Device USB connection (ms)

STM32F04xxx 350
STM32F070x6 TBD
STM32F070xB 320
HSE = 25 MHz 460
STM32F105xx/107xx HSE = 14.7465 MHz 4500
HSE = 8 MHz 13700
STM32F2xxxx 270
STM32F301xx/302x4(6/8) 300
STM32F302xB(C)/303xB(C) 300
STM32F302xD(E)/303xD 100
STM32F373xx 300
V3.x 270
STM32F40xxx/41xxx
V9.x 250
STM32F401xB(C) 250
STM32F401xD(E) 250
STM32F411xx 250
STM32F412xx 380
STM32F413xx/423xx 350

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Table 125. USB bootloader minimum timings of STM32 devices (continued)

Device USB connection (ms)

V7.x
STM32F429xx/439xx 250
V9.x
STM32F446xx 200
STM32F469xx/479xx 270
STM32F72xxx/73xxx 320
STM32F74xxx/75xxx 230
STM32H74xxx/75xxx 53.9764
STM32L07xxx/08xxx 140
STM32L1xxxC 849
STM32L1xxxD 849
STM32L412xx/L422xx 820
STM32L43xxx/44xxx 820
STM32L45xxx/46xxx 330
V10.x
STM32L47xxx/48xxx 300
V9.x
STM32L496xx/4A6xx 430
STM32L4Rxx/4Sxx NA
STM32WB55xx 300

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58.4 I2C connection timing

I2C connection timing is the time that the host should wait for between sending I2C device
address and sending command code. This timing includes I2C line stretching duration.

Figure 77. I2C connection timing description

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Note: For I2C communication, a timeout mechanism is implemented and it must be respected to
execute bootloader commands correctly. This timeout is implemented between two I2C
frames in the same command (eg: for Write memory command a timeout is inserted
between command sending frame and address memory sending frame). Also the same
timeout period is inserted between two successive data reception or transmission in the
same I2C frame. If the timeout period is elapsed a system reset is generated to avoid
bootloader crash.
In erase memory command and read-out unprotect command, the duration of flash
operation should be taken into consideration when implementing the host side. After
sending the code of pages to be erased, the host should wait until the bootloader device
performs page erasing to complete the remaining steps of erase command.

Table 126. I2C bootloader minimum timings of STM32 devices

Start condition
I2C line I2C connection I2C Timeout
Device + one I2C byte
stretching (ms) (ms) (ms)
sending (ms)

STM32F04xxx 0.0225 0.0025 0.0250 1000

STM32F070x6 0.0225 0.0025 0.0245 1000
STM32F070xB 0.0225 0.0025 0.0245 1000
STM32F071xx/072xx 0.0225 0.0025 0.0250 1000
STM32F09xxx 0.0225 0.0025 0.0245 1000
STM32F303x4(6/8)/334xx/328xx 0.0225 0.0027 0.0252 1000

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Table 126. I2C bootloader minimum timings of STM32 devices (continued)

Start condition
I2C line I2C connection I2C Timeout
Device + one I2C byte
stretching (ms) (ms) (ms)
sending (ms)

STM32F318xx 0.0225 0.0027 0.0252 1000

STM32F358xx 0.0225 0.0055 0.0280 10
STM32F378xx 0.0225 0.0055 0.0280 10
STM32F398xx 0.0225 0.0020 0.0245 1500
STM32F40xxx/41xxx 0.0225 0.0022 0.0247 1000
STM32F401xB(C) 0.0225 0.0022 0.0247 1000
STM32F401xD(E) 0.0225 0.0022 0.0247 1000
STM32F410xx 0.0225 0.0020 0.0245 1000
STM32F411xx 0.0225 0.0022 0.0247 1000
STM32F412xx 0.0225 0.0020 0.0245 1000
STM32F413xx/423xx 0.0225 0.0020 0.0245 1000
V7.x 0.0225 0.0033 0.0258 1000
STM32F42xxx/43xxx
V9.x 0.0225 0.0022 0.0247 1000
STM32F446xx 0.0225 0.0020 0.0245 1000
STM32F469xx/479xx 0.0225 0.0020 0.0245 1000
STM32F72xxx/73xxx 0.0225 0.0020 0.0245 1000
STM32F74xxx/75xxx 0.0225 0.0020 0.0245 500
STM32G07xxx/08xxx 0.0225 0.0020 0.0245 1000
STM32H74xxx/75xxx 0.0225 0.05 0.0725 1000
STM32L07xxx/08xxx 0.0225 0.0020 0.0245 1000
STM32L412xx/L422xx 0.0225 0.0020 0.o245 1000
STM32L43xxx/44xxx 0.0225 0.0020 0.0245 1000
STM32L45xxx/46xxx 0.0225 0.0020 0.0245 1000
V10.x 0.0225 0.0020 0.0245 1000
STM32L47xxx/48xxx
V9.x 0.0225 0.0020 0.0245 1000
STM32L496xx/4A6xx 0.0225 0.0020 0.0245 1000
STM32L4Rxx/4Sxx NA NA NA NA
STM32WB55xx 0.0225 0.0020 0.0245 1000

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AN2606 Bootloader timing

58.5 SPI connection timing

SPI connection timing is the time that the host should wait for between sending the
synchronization data (0xA5) and receiving the first acknowledge response (0x79).

Figure 78. SPI connection timing description

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Table 127. SPI bootloader minimum timings of STM32 devices

One SPI byte Delay between two SPI connection
Device
sending (ms) bytes(ms) (ms)

All products 0.001 0.008 0.01

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59 Revision history

Table 128. Document revision history

Date Revision Changes

22-Oct-2007 1 Initial release.

All STM32 in production (rev. B and rev. Z) include the bootloader described in
this application note.
Modified: Section 3.1: Bootloader activation and Section 1.4: Bootloader code
sequence.
Added: Section 1.3: Hardware requirements, Section 1.5: Choosing the
22-Jan-2008 2 USART baud rate, Section 1.6: Using the bootloader and Section:
Note 2 linked to Get, Get Version & Read Protection Status and Get ID
commands in Table 3: Bootloader commands, Note 3 added.
Notion of “permanent” (Permanent Write Unprotect/Readout
Protect/Unprotect) removed from document. Small text changes.
Bootloader version upgraded to 2.0.
Small text changes. RAM and System memory added to Table : The system
clock is derived from the embedded internal high-speed RC, no external quartz
is required for the bootloader execution.
Section 1.6: Using the bootloader on page 8 removed.
Erase modified, Note 3 modified and Note 1 added in Table 3: Bootloader
commands on page 9.
Byte 3: on page 11 modified.
Byte 2: on page 13 modified.
Byte 2:, Bytes 3-4: and Byte 5: on page 15 modified, Note 3 modified.
Byte 8: on page 18 modified.
Notes added to Section 2.5: Go command on page 18.
26-May-2008 3 Figure 11: Go command: device side on page 20 modified.
Note added in Section 2.6: Write Memory command on page 21.
Byte 8: on page 24 modified.
Figure 14: Erase Memory command: host side and Figure 15: Erase Memory
command: device side modified.
Byte 3: on page 26 modified.
Table 3: Bootloader commands on page 9.
Note modified and note added in Section 2.8: Write Protect command on
page 27.
Figure 16: Write Protect command: host side, Figure 17: Write Protect
command: device side, Figure 19: Write Unprotect command: device side,
Figure 21: Readout Protect command: device side and Figure 23: Readout
Unprotect command: device side modified.
This application note also applies to the STM32F102xx microcontrollers.
29-Jan-2009 4
Bootloader version updated to V2.2 (see Table 4: Bootloader versions).

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Table 128. Document revision history (continued)

Date Revision Changes

IWDG added to Table : The system clock is derived from the embedded
internal high-speed RC, no external quartz is required for the bootloader
execution.. Note added.
BL changed bootloader in the entire document.
Go command description modified in Table : The system clock is derived from
the embedded internal high-speed RC, no external quartz is required for the
bootloader execution.
Number of bytes awaited by the bootloader corrected in Section 2.4: Read
Memory command.
19-Nov-2009 5 Note modified below Figure 10: Go command: host side.
Note removed in Section 2.5: Go command and note added.
Start RAM address specified and note added in Section 2.6: Write Memory
command. All options are erased when a Write Memory command is issued to
the Option byte area.
Figure 11: Go command: device side modified.
Figure 13: Write Memory command: device side modified.
Note added and bytes 3 and 4 sent by the host modified in Section 2.7: Erase
Memory command.
Note added to Section 2.8: Write Protect command.
Application note restructured. Value line and connectivity line device
09-Mar-2010 6 bootloader added (Replaces AN2662).
Introduction changed. Glossary added.
Related documents: added XL-density line datasheets and programming
manual.
Glossary: added XL-density line devices.
Table 3: added information for XL-density line devices.
20-Apr-2010 7
Section 4.1: Bootloader configuration: updated first sentence.
Section 5.1: Bootloader configuration: updated first sentence.
Added Section 6: STM32F10xxx XL-density devices bootloader.
Table 65: added information for XL-density line devices.
08-Oct-2010 8 Added information for high-density value line devices in Table 3 and Table 65.
14-Oct-2010 9 Removed references to obsolete devices.
26-Nov-2010 10 Added information on ultralow power devices.
Added information related to STM32F205/215xx and STM32F207/217xx
13-Apr-2011 11 devices.
Added Section 32: Bootloader timing
Updated:
– Table 12: STM32L1xxx6(8/B) bootloader versions
06-Jun-2011 12 – Table 17: STM32F2xxxx configuration in System memory boot mode
– Table 18: STM32F2xxxx bootloader V2.x versions
– Table 20: STM32F2xxxx bootloader V3.x versions
Added information related to STM32F405/415xx and STM32F407/417xx
bootloader, and STM32F105xx/107xx bootloader V2.1.
28-Nov-2011 13
Added value line devices in Section 4: STM32F10xxx devices bootloader title
and overview.

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Table 128. Document revision history (continued)

Date Revision Changes

Added information related to STM32F051x6/STM32F051x8 and to High-

density ultralow power STM32L151xx, STM32L152xx bootloader.
Added case of BOOT1 bit in Section 3.1: Bootloader activation.
Updated Connectivity line, High-density ultralow power line, STM32F2xx and
STM32F4xx in Table 3: Embedded bootloaders.
Added bootloader version V2.2 in Table 8: STM32F105xx/107xx bootloader
versions.
Added bootloader V2.2 in Section 5.3.1: How to identify STM32F105xx/107xx
bootloader versions.
Added note related to DFU interface below Table 15: STM32L1xxxx high-
density configuration in System memory boot mode. Added V4.2 bootloader
know limitations and updated description, and added V4.5 bootloader in
Table 16: STM32L1xxxx high-density bootloader versions.
Added note related to DFU interface below Table 19: STM32F2xxxx
configuration in System memory boot mode. Added V3.2 bootloader know
30-Jul-2012 14 limitations, and added V3.3 bootloader in Table 20: STM32F2xxxx bootloader
V3.x versions. Updated STM32F2xx and STM32F4xx system memory end
address in Table 21: STM32F40xxx/41xxx configuration in System memory
boot mode.
Added note related to DFU interface below Table 21: STM32F40xxx/41xxx
configuration in System memory boot mode. Added V3.0 bootloader know
limitations, and added V3.1 bootloader in Table 22: STM32F40xxx/41xxx
bootloader V3.x version.
Added bootloader V2.1 know limitations in Table 26: STM32F051xx bootloader
versions.
Updated STM32F051x6/x8 system memory end address in Table 65:
Bootloader device-dependent parameters.
Added Table 75: USART bootloader timings for high-density ultralow power
devices, and Table 78: USART bootloader timings for STM32F051xx devices.
Added Table 88: USB minimum timings for high-density ultralow power
devices.

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Table 128. Document revision history (continued)

Date Revision Changes

Updated generic product names throughout the document (see Glossary).

Added the following new sections:
– Section 8: STM32L1xxxC devices bootloader.
– Section 13: STM32F031xx devices bootloader.
– Section 14: STM32F373xx devices bootloader.
– Section 15: STM32F302xB(C)/303xB(C) devices bootloader.
– Section 16: STM32F378xx devices bootloader.
– Section 17: STM32F358xx devices bootloader.
– Section 18: STM32F427xx/437xx devices bootloader.
– Section 34.3: I2C bootloader timing characteristics.
24-Jan-2013 15 Updated Section 1: Related documents and Section 2: Glossary.
Added Table 79 to Table 85 (USART bootloader timings).
Replaced Figure 6 to Figure 16, and Figures 18, 19 and 42.
Modified Tables 3, 5, 9, 11, 17, 20, 21, 22 to 13, 27, 29, 31, 33, 35, 37 and 65.
Removed “X = 6: one USART is used” in Section 3.3: Hardware connection
requirement.
Replaced address 0x1FFFF 8002 with address 0x1FFF F802 in Section 12.1:
Bootloader configuration.
Modified procedure related to execution of the bootloader code in Note: on
page 28, in Section 6.2: Bootloader selection and in Section 9.2: Bootloader
selection.
Added information related to I2C throughout the document.
Streamlined Table 1: Applicable products and Section 1: Related documents.
Modified Table 3: Embedded bootloaders as follows:
– Replaced "V6.0" with "V1.0"
– Replaced "0x1FFFF7A6" with "0x1FFFF796" in row STM32F31xx
– Replaced "0x1FFF7FA6" with "0x1FFFF7A6" in row STM32F051xx
Updated figures 6, 9 and 11.
Added Note: in Glossary and Note: in Section 3.1: Bootloader activation.
Replaced:
– "1.62 V" with "1.8 V" in tables17, 19, 19, 22, 21, 27, 37 and 59
06-Feb-2013 16
– "5 Kbyte" with "4 Kbyte" in row RAM of Table 33
– "127 pages (2 KB each)" with "4 KB (2 pages of 2 KB each)" in rows F3 of
Table 65
– "The bootloader ID is programmed in the last two bytes of the device system
memory" with "The bootloader ID is programmed in the last byte address - 1
of the device system memory" in Section 3.3: Hardware connection
requirement.
– "STM32F2xxxx devices revision Y" by "STM32F2xxxx devices revision X
and Y" in Section 10: STM32F2xxxx devices bootloader
– “Voltage Range 2” with “Voltage Range 1” in tables 11, 15 and 26.

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Table 128. Document revision history (continued)

Date Revision Changes

Updated:
– Introduction
– Section 2: Glossary
– Section 3.3: Hardware connection requirement
– Section 7: STM32L1xxx6(8/B) devices bootloader to include STM32L100
value line
– Section 32.2: USART connection timing
– Section 34.2: USB bootloader timing characteristics
21-May-2013 17
– Section 34.3: I2C bootloader timing characteristics
– Table 1: Applicable products
– Table 3: Embedded bootloaders
– Table 25: STM32F051xx configuration in System memory boot mode
– Table 27: STM32F031xx configuration in System memory boot mode
– Table 65: Bootloader device-dependent parameters
– Figure 17: Bootloader selection for STM32F031xx devices
Added Section 19: STM32F429xx/439xx devices bootloader.
Add:
– Figure 1 to Figure 5, Figure 62, Figure 6, Figure 25, Figure 26, Figure 24,
from Figure 38 to Figure 74, Figure 78
– Table 4, Table 104, Table 105, from Table 6 to Table 45, from Table 46 to
Table 43, from Table 68 to Table 69, from Table to Table 127
– Section 38.4, Section 33.2, Section 58.1, Section 58.5
– Section 5 ,Section 23, Section 24, Section 22, from Section 17 to Section 53
– note under Figure 1, Figure 2, Figure 3 and Figure 4
Updated:
19-May-2014 18 – Updated starting from Section 4 to Section 7 and Section 18, Section 33 and
Section 33 the chapter structure organized in three subsection: Bootloader
configuration, Bootloader selection and Bootloader version.
Updated Section 53 and Section 58
– Updated block diagram of Figure 25 and Figure 20.
– Fixed I2C address for STM32F429xx/439xx devices in Table 66
– Table 1, Table 2, Table 3, Table 24, Table 98, Table 100, Table 102,
Table 28, Table 30, Table 50, Table 122
– from Figure 14, to Figure 28, Figure 8, from Figure 74 to Figure 78
– note on Table 99

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Table 128. Document revision history (continued)

Date Revision Changes

Updated:
– notes under Table 2
– Figure 61 and Figure 62
– Section 3: Glossary
– replaced any reference to STM32F427xx/437xx with STM32F42xxx/43xxx
on Section 33: STM32F42xxx/43xxx devices bootloader
– replace any occurrence of ‘STM32F072xx’ with ‘STM32F07xxx’
– replace any occurrence of ‘STM32F051xx’ with ‘STM32F051xx and
STM32F030x8 devices’.
– comment field related to OTG_FS_DP and OTG_FS_DM on Table 24,
Table 30, Table 50, Table 104, Table 66, Table 68, Table 12, Table 18,
Table 54, Table 56 and Table 60
29-Jul-2014 19
– comment field related to USB_DM on Table 104.
– replace reference to "STM32F429xx/439xx" by "STM32F42xxx/43xxx” on
Table 3
– comment field related to SPI2_MOSI, SPI2_MISO, SPI2_SCK and
SPI2_NSS pins on Table 68
Added:
– note under Table 2
– reference to STM32F411 on Table 1, Section 3: Glossary, Table 123,
Table 124, Table 125, Table 126
– Section 30: STM32F411xx devices bootloader
Removed reference to STM32F427xx/437xx on Table 3, Section 3: Glossary,
Table 122, Table 123, Table 124, Table 125
Updated:
– comment in “SPI1_NSS pin" and "SPI2_NSS pin" rows on Table 104 and
Table 90
24-Nov-2014 20
– comment in "SPI1_NSS pin", "SPI2_NSS pin" and "SPI3_NSS pin" rows on
Table 54, Table 56 and Table 60
– Figure 1
Updated:
– Table 1, Table 3, Table 22, Table 26, Table 98, Table 28, Table 30, Table 31,
Table 50, Table 104, Table 10, Table 11, Table 6, Table 34, Table 66,
Table 68, Table 12, Table 13, Table 18, Table 19,Table 32, Table 96,
Table 112, Table 122, Table 123, Table 124, Table 125 and Table 126
11-Mar-2015 21 – Figure 67
– Chapter 3: Glossary
– Section 4.1 and Section 4.4
Added:
– Section 53: STM32L47xxx/48xxx devices bootloader and Section 34:
STM32F446xx devices bootloader

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Table 128. Document revision history (continued)

Date Revision Changes

Added:
– Section 9: STM32F070x6 devices bootloader
– Section 10: STM32F070xB devices bootloader
– Section 12: STM32F09xxx devices bootloader
– Section 19: STM32F302xD(E)/303xD(E) devices bootloaderSection 25:
STM32F398xx devices bootloader
– Section 36: STM32F72xxx/73xxx devices bootloader
– Section 53.2: Bootloader V9.x
09-Jun-2015 22
– Notes 1 and 2 on Figure 75
Updated:
– Table 1
– Section 3: Glossary
– Table 2
– Table 3
– Section 4.4: Bootloader memory management
– Table 122, Table 123, Table 124, Table 125 and Table 126
Added:
– Section 29: STM32F410xx devices bootloader
– Section 35: STM32F469xx/479xx devices bootloader
– Section 42: STM32L031xx/041xx devices bootloader
– Section 44: STM32L07xxx/08xxx devices bootloader
29-Sep-2015 23
Updated:
– Table 1
– Section 3: Glossary
– Table 3
– Figure 67, Table 114, Table 123, Table 124, Table 125, Table 126
Updated:
– Table 1, Table 3, Table 122, Table 123, Table 124, Table 125, Table 126
– Section 35
02-Nov-2015 24
Added:
– Note on Section 26.2.1
– Section 31
Updated:
01-Dec-2015 25 – Section 4.1, Section 44
– Table 122
Updated:
– Table 1, Table 3, Table 63, Table 93, Table 95, Table 122
– Section 3, Section 44.1.1, Section 44.2.1, Section 53
03-Mar-2016 26
Added:
– Section 41: STM32L01xxx/02xxx devices bootloader
– Figure 54, Figure 56

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Table 128. Document revision history (continued)

Date Revision Changes

Added:
– Section 38: STM32F76xxx/77xxx devices bootloader, Section 51:
STM32L43xxx/44xxx devices bootloader.
– Note on: Section 4.1: Bootloader activation, Section 8.1: Bootloader
configuration, Section 9.1: Bootloader configuration, Figure 36: Dual Bank
Boot Implementation for STM32F42xxx/43xxx Bootloader V7.x, Figure 38:
Dual Bank Boot Implementation for STM32F42xxx/43xxx bootloader V9.x
Updated:
– Table 1: Applicable products, Table 2: Bootloader activation patterns,
Table 8: STM32F030xC configuration in system memory boot mode,
Table 14: STM32F070x6 configuration in system memory boot mode,
21-Apr-2016 27 Table 16: STM32F070xB configuration in system memory boot mode,
Table 20: STM32F09xxx configuration in system memory boot mode,
Table 32: STM32F301xx/302x4(6/8) configuration in system memory boot
mode, Table 34: STM32F302xB(C)/303xB(C) configuration in system
memory boot mode, Table 36: STM32F302xD(E)/303xD(E) configuration in
system memory boot mode, Table 44: STM32F373xx configuration in
system memory boot mode, Table 54: STM32F401xB(C) configuration in
system memory boot mode, Table 56: STM32F401xD(E) configuration in
system memory boot mode, Table 60: STM32F411xx configuration in system
memory boot mode, Table 113: STM32L47xxx/48xxx bootloader V10.x
versions, Table 115: STM32L47xxx/48xxx bootloader V9.x versions,
Table 122: Bootloader device-dependent parameters
– Section 3: Glossary,

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Table 128. Document revision history (continued)

Date Revision Changes

Updated:
– Table 1: Applicable products, Table 8: STM32F030xC configuration in
system memory boot mode, Table 10: STM32F05xxx and STM32F030x8
devices configuration in system memory boot mode, Table 12:
STM32F04xxx configuration in system memory boot mode, Table 14:
STM32F070x6 configuration in system memory boot mode, Table 16:
STM32F070xB configuration in system memory boot mode, Table 18:
STM32F071xx/072xx configuration in system memory boot mode, Table 20:
STM32F09xxx configuration in system memory boot mode, Table 24:
STM32F105xx/107xx configuration in system memory boot mode, Table 26:
STM32F10xxx XL-density configuration in system memory boot mode,
Table 28: STM32F2xxxx configuration in system memory boot mode,
Table 30: STM32F2xxxx configuration in system memory boot mode,
Table 32: STM32F301xx/302x4(6/8) configuration in system memory boot
mode, Table 34: STM32F302xB(C)/303xB(C) configuration in system
memory boot mode, Table 36: STM32F302xD(E)/303xD(E) configuration in
system memory boot mode, Table 38: STM32F303x4(6/8)/334xx/328xx
configuration in system memory boot mode, Table 40: STM32F318xx
configuration in system memory boot mode, Table 42: STM32F358xx
configuration in system memory boot mode, Table 44: STM32F373xx
configuration in system memory boot mode, Table 46: STM32F378xx
configuration in system memory boot mode, Table 48: STM32F398xx
05-Sep-2016 28
configuration in system memory boot mode, Table 50: STM32F40xxx/41xxx
configuration in system memory boot mode, Table 52: STM32F40xxx/41xxx
configuration in system memory boot mode, Table 54: STM32F401xB(C)
configuration in system memory boot mode, Table 56: STM32F401xD(E)
configuration in system memory boot mode, Table 60: STM32F411xx
configuration in system memory boot mode, Table 66: STM32F42xxx/43xxx
configuration in system memory boot mode, Table 68: STM32F42xxx/43xxx
configuration in system memory boot modeTable 70: STM32F446xx
configuration in system memory boot mode, Table 72: STM32F469xx/479xx
configuration in system memory boot mode, Table 76: STM32F74xxx/75xxx
configuration in system memory boot mode, Table 78: STM32F74xxx/75xxx
configuration in system memory boot mode, Table 90: STM32L05xxx/06xxx
configuration in system memory boot mode, Table 96: STM32L1xxx6(8/B)A
configuration in system memory boot mode, Table 98: STM32L1xxx6(8/B)
configuration in system memory boot mode, Table 100: STM32L1xxxC
configuration in system memory boot mode, Table 102: STM32L1xxxD
configuration in system memory boot mode, Table 104: STM32L1xxxE
configuration in system memory boot mode, Table 109: STM32L43xxx/44xxx
bootloader versions, Table 112: STM32L47xxx/48xxx configuration in
system memory boot mode, Table 122: Bootloader device-dependent
parameters
– Section 51.1: Bootloader configuration

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Table 128. Document revision history (continued)

Date Revision Changes

– Figure 22: Bootloader selection for STM32F303x4(6/8)/334xx/328xx,

Figure 23: Bootloader selection for STM32F318xx, Figure 25: Bootloader
selection for STM32F373xx devices, Figure 26: Bootloader selection for
STM32F378xx devices, Figure 29: Bootloader V9.x selection for
28 STM32F40xxx/41xxx, Figure 32: Bootloader V11.x selection for
05-Sep-2016
(continued) STM32F410xx, Figure 34: Bootloader V9.x selection for STM32F412xx,
Figure 42: Bootloader V9.x selection for STM32F469xx/479xx, Figure 47:
Bootloader V9.x selection for STM32F76xxx/77xxx, Figure 57: Bootloader
V11.x selection for STM32L07xxx/08xxx, Figure 67: Bootloader V10.x
selection for STM32L47xxx/48xxx
Updated:
– Table 1: Applicable products, Section 3: Glossary, Section 4.1: Bootloader
activation, Table 3: Embedded bootloaders, Table 12: STM32F09xxx
devices bootloader, Table 14: STM32F105xx/107xx devices bootloader,
Table 15: STM32F10xxx XL-density devices bootloader, Table 16:
STM32F2xxxx devices bootloader, Table 17: STM32F301xx/302x4(6/8)
devices bootloader, Table 18: STM32F302xB(C)/303xB(C) devices
bootloader, Table 20: STM32F303x4(6/8)/334xx/328xx devices bootloader,
Table 22: STM32F358xx devices bootloader, Table 25: STM32F398xx
devices bootloader, Table 29: STM32F410xx devices bootloader, Table 32:
STM32F413xx/423xx devices bootloader, Table 56: STM32F401xD(E)
configuration in system memory boot mode, Section 14.3.1: How to identify
STM32F105xx/107xx bootloader versions, Section 28.1: Bootloader
configuration, Table 58: STM32F410xx configuration in system memory boot
mode, Table 60: STM32F411xx configuration in system memory boot mode,
07-Dec-2016 29 Table 62: STM32F412xx configuration in system memory boot mode,
Section 30.1: Bootloader configuration, Table 67: STM32F42xxx/43xxx
bootloader V7.x versions, Table 69: STM32F42xxx/43xxx bootloader V9.x
versions, Table 80: STM32F76xxx/77xxx configuration in system memory
boot mode, Table 81: STM32F76xxx/77xxx bootloader V9.x versions,
Table 87: STM32L01xxx/02xxx bootloader versions, Table 95:
STM32L07xxx/08xxx bootloader V11.x versions, Table 108:
STM32L43xxx/44xxx configuration in system memory boot mode, Table 109:
STM32L43xxx/44xxx bootloader versions, Table 113: STM32L47xxx/48xxx
bootloader V10.x versions, Table 122: Bootloader device-dependent
parameters, Table 123: Bootloader startup timings of STM32 devices,
Table 125: USB bootloader minimum timings of STM32 devices, Table 125:
USB bootloader minimum timings of STM32 devices, Table 126: I2C
bootloader minimum timings of STM32 devices
Added:
– Section 32: STM32F413xx/423xx devices bootloader

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Table 128. Document revision history (continued)

Date Revision Changes

Updated:
– Table 1: Applicable products, Table 3: Embedded bootloaders, Table 11:
STM32F05xxx and STM32F030x8 devices bootloader versions, Table 12:
STM32F04xxx configuration in system memory boot mode, Table 13:
STM32F04xxx bootloader versions, Table 15: STM32F070x6 bootloader
versions, Table 17: STM32F070xB bootloader versions, Table 18:
STM32F071xx/072xx configuration in system memory boot mode, Table 19:
STM32F071xx/072xx bootloader versions, Table 20: STM32F09xxx
configuration in system memory boot mode, Table 21: STM32F09xxx
bootloader versions, Table 32: STM32F301xx/302x4(6/8) configuration in
system memory boot mode, Table 35: STM32F302xB(C)/303xB(C)
bootloader versions, Table 81: STM32F76xxx/77xxx bootloader V9.x
versions, Table 86: STM32L01xxx/02xxx configuration in system memory
13-Mar-2017 30
boot mode, Table 109: STM32L43xxx/44xxx bootloader versions, Table 122:
Bootloader device-dependent parameters, Table 114: STM32L47xxx/48xxx
configuration in system memory boot mode, Table 123: Bootloader startup
timings of STM32 devices, Table 124: USART bootloader minimum timings
of STM32 devices, Table 125: USB bootloader minimum timings of STM32
devices, Table 126: I2C bootloader minimum timings of STM32 devices,
Table 127: SPI bootloader minimum timings of STM32 devices
– Section 3: Glossary, Section 6.1: Bootloader configuration, Section 14.3.3:
USART bootloader Get-Version command returns 0x20 instead of 0x22,
RPN reference in Section 51: STM32L43xxx/44xxx devices bootloader and
in Section 53: STM32L47xxx/48xxx devices bootloader
Added Section 36: STM32F72xxx/73xxx devices bootloader and Section 54:
STM32L496xx/4A6xx devices bootloader

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Table 128. Document revision history (continued)

Date Revision Changes

Updated:
– Table 1: Applicable products, Table 2: Bootloader activation patterns,
Table 3: Embedded bootloaders, Table 25: STM32F105xx/107xx bootloader
versions, Table 30: STM32F2xxxx configuration in system memory boot
mode, Table 34: STM32F302xB(C)/303xB(C) configuration in system
memory boot mode, Table 42: STM32F358xx configuration in system
memory boot mode, Table 44: STM32F373xx configuration in system
memory boot mode, Table 46: STM32F378xx configuration in system
memory boot mode, Table 52: STM32F40xxx/41xxx configuration in system
memory boot mode, Table 54: STM32F401xB(C) configuration in system
memory boot mode, Table 56: STM32F401xD(E) configuration in system
memory boot mode, Table 60: STM32F411xx configuration in system
memory boot mode, Table 66: STM32F42xxx/43xxx configuration in system
memory boot mode, Table 70: STM32F446xx configuration in system
memory boot mode, Table 72: STM32F469xx/479xx configuration in system
memory boot mode, Table 74: STM32F72xxx/73xxx configuration in system
04-Jul-2017 31 memory boot mode, Table 76: STM32F74xxx/75xxx configuration in system
memory boot mode, Table 78: STM32F74xxx/75xxx configuration in system
memory boot mode, Table 84: STM32H74xxx/75xxx configuration in system
memory boot mode, Table 100: STM32L1xxxC configuration in system
memory boot mode, Table 102: STM32L1xxxD configuration in system
memory boot mode, Table 104: STM32L1xxxE configuration in system
memory boot mode, Table 110: STM32L45xxx/46xxx configuration in system
memory boot mode, Table 122: Bootloader device-dependent parameters,
Table 123: Bootloader startup timings of STM32 devices, Table 124: USART
bootloader minimum timings of STM32 devices, Table 125: USB bootloader
minimum timings of STM32 devices, Table 126: I2C bootloader minimum
timings of STM32 devices
– Introduction, Section 3: Glossary
– Figure 64: Bootloader V9.x selection for STM32L43xxx/44xxx
Added:
– Section 40: STM32H74xxx/75xxx devices bootloader, Section 52:
STM32L45xxx/46xxx devices bootloader
Updated Table 3: Embedded bootloaders, Table 85: STM32H74xxx/75xxx
bootloader version, Table 116: STM32L496xx/4A6xx configuration in system
memory boot mode, Table 117: STM32L496xx/4A6xx bootloader version,
Table 122: Bootloader device-dependent parameters, Table 123: Bootloader
16-Feb-2018 32 startup timings of STM32 devices, Table 124: USART bootloader minimum
timings of STM32 devices, Table 125: USB bootloader minimum timings of
STM32 devices, Table 126: I2C bootloader minimum timings of STM32
devices.
Added Section 55: STM32L4Rxxx/4Sxxx devices bootloader
Updated Note: in Section 8.1: Bootloader configuration, Note: in Section 9.1:
07-Aug-2018 33
Bootloader configuration

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Revision history AN2606

Table 128. Document revision history (continued)

Date Revision Changes

Updated Table 1: Applicable products, Table 51: STM32F40xxx/41xxx

bootloader V3.x versions, Table 53: STM32F40xxx/41xxx bootloader V9.x
versions, Table 55: STM32F401xB(C) bootloader versions, Table 57:
STM32F401xD(E) bootloader versions, Table 59: STM32F410xx bootloader
V11.x versions, Table 61: STM32F411xx bootloader versions, Table 63:
STM32F412xx bootloader V9.x versions, Table 65: STM32F413xx/423xx
bootloader V9.x versions, Table 67: STM32F42xxx/43xxx bootloader V7.x
versions, Table 69: STM32F42xxx/43xxx bootloader V9.x versions, Table 71:
05-Nov-2018 34 STM32F446xx bootloader V9.x versions, Table 73: STM32F469xx/479xx
bootloader V9.x versions, Table 75: STM32F72xxx/73xxx bootloader V9.x
versions, Table 77: STM32F74xxx/75xxx bootloader V7.x versions, Table 79:
STM32F74xxx/75xxx bootloader V9.x versions, Table 81:
STM32F76xxx/77xxx bootloader V9.x versions, Table 122: Bootloader device-
dependent parameters, Table 123: Bootloader startup timings of STM32
devices, Table 124: USART bootloader minimum timings of STM32 devices,
Table 125: USB bootloader minimum timings of STM32 devices.
Added Section 50: STM32L412xx/L422xx devices bootloader
Updated Table 1: Applicable products, Section 3: Glossary, Table 123:
Bootloader startup timings of STM32 devices, Table 124: USART bootloader
06-Dec-2018 35 minimum timings of STM32 devices, Table 126: I2C bootloader minimum
timings of STM32 devices.
Added Section 39: STM32G07xxx/08xxx device bootloader
Updated Table 1: Applicable products, Section 3: Glossary, Table 3:
Embedded bootloaders, Table 122: Bootloader device-dependent parameters,
Table 123: Bootloader startup timings of STM32 devices, Table 124: USART
21-Feb-2019 36 bootloader minimum timings of STM32 devices, Table 125: USB bootloader
minimum timings of STM32 devices, Table 126: I2C bootloader minimum
timings of STM32 devices.
Added Section 56: STM32WB55xx devices bootloader

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