DESIGN OF RF MIXER WITH HIGH LINEARITY

AND LOW POWER FOR 5G APPLICATIONS

A thesis submitted in partial fulfilment of the requirements for

the award of the degree of

B.Tech

in
Electronics and Communication Engineering

By
M. Sowmya Lakshmi (108115055)
Vijayalakshmi S. (108115104)

ELECTRONICS AND COMMUNICATION ENGINNERING

NATIONAL INSTITUTE OF TECHNOLOGY
TIRUCHIRAPALLI – 620015

MAY 2019
 BONAFIDE CERTIFICATE

This is to certify that the project titled DESIGN OF RF MIXER WITH HIGH
LINEARITY AND LOW POWER FOR 5G APPLICATIONS is a bonafide
record of the work done by

M. Sowmya Lakshmi (108115055)

Vijayalakshmi .S (108115104)

in partial fulfilment of the requirements for the award of the degree of Bachelor of
Technology in Electronics and Communication Engineering of the NATIONAL
INSTITUTE OF TECHNOLOGY, TIRUCHIRAPPALLI, during the year 2018-
2019.

Dr. BHASKAR Dr. G LAKSHMI NARAYANAN

Guide Head of the department,
Department of Electronics and Department of Electronics and
Communication Engineering, Communication Engineering,
National Institute of technology, National Institute of technology,
Tiruchirappalli – 620015, India. Tiruchirappalli – 620015, India.

Project Viva-voce held on _______________________

Internal Examiner External Examiner

 ABSTRACT

5G is the term used to describe the next-generation of mobile networks beyond Long
Term Evolution (LTE) mobile networks. 5G network speeds should have a peak data
rate of 20 Gbps for the downlink and 10 Gbps for the uplink. 5G will use the spectrum
in the existing frequency range (600 MHz - 6 GHz), called the sub-6 GHz band group
and also in millimetre wave bands (24 GHz- 86 GHz). The bulk of future 5G networks
will likely consist of the sub 6 GHz mid-band group. 5G has been driven by the need
to provide ubiquitous connectivity for applications as diverse as automotive
communications, remote control with haptic style feedback, huge video downloads, as
well as the very low data rate applications like remote sensors and the IoT, Internet of
Things.

In the scope of sub-6 GHz 5G technology, besides massive communication demands,

5G sensing applications play another vital role. Sensing techniques featuring compact
system size, high reliability, reduced cost, and low power consumption are immensely
needed. As a part of any application, which incorporates reception of data, a receiver is
required. Every receiver consists of a low noise amplifier and a mixer apart from the
receiving antenna. The proposed double linearization topology, designed using UMC
180 nm technology, aims to develop a low power mixer at the frequency of 5 GHz. One
of the major applications of the 5 GHz frequency band is the Wi-Fi. 5 GHz band can
help mitigate the effects of interference and significantly improve performance. The
mixer is designed to produce a high linearity which helps in overcoming the
intermodulation products due to the non- linear characteristics of the mixer. The given
mixer topology has a desirable conversion gain and noise figure at 5 GHz.

i
 ACKNOWLEDGEMENTS

We would like to extend our heartfelt gratitude to the following people for their support
and guidance without which the completion of this project in fruition would not be
possible.

Dr. M. Bhaskar, our project guide for helping and guiding us in the course of this
project.

Dr. G. Lakshmi Narayanan, the Head of the Department, Department of Electronics

and Communication Engineering for his kind words of motivation.

Mr. S. Chrisben Gladson, for his unrelenting support and encouragement.

A special thanks to the Department of Electronics and Communication Engineering

for giving us unlimited access to the facilities at the RFIC Design Lab.

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 TABLE OF CONTENTS

Title Page No
ABSTRACT i
ACKNOWLEDGEMENTS ii
TABLE OF CONTENTS iii
LIST OF TABLES v
LIST OF FIGURES vi
CHAPTER 1 INTRODUCTION
1.1 Wireless Transmitter Architecture 1
1.2 Wireless Receiver Architecture 2
CHAPTER 2 LITERATURE REVIEW
2.1 Low power balun LNA using noise cancellation 10
2.2 RF down-conversion Gilbert cell 11
2.3 Balun LNA using current-bleeding technique 12
2.4 Down-conversion mixer using NRC technique 13
2.5 Active mixer using derivative superposition 14
2.6 Wideband Gilbert SHM using regulated cascade stage 15
and Inductive connections
CHAPTER 3 PROPOSED TOPOLOGY
3.1 Amplification Stage 18
3.2 Linearization Stage 18
3.3 Feedback Stage 19
3.4 Mixing Stage 19
CHAPTER 4 ANALYSIS
4.1 Gain Analysis 20
4.2 Noise Analysis 23
4.3 Linearity 24
4.4 Input Impedance Analysis 25

CHAPTER 5 RESULTS AND DISCUSSIONS 28

iii
CHAPTER 6 SUMMARY AND CONCLUSIONS
6.1 Summary 35
6.2 Scope for Future Work 35
CHAPTER 7 PUBLICATIONS 36
REFERENCES 37

iv
 LIST OF TABLES

Table No. Title Page No.

Table 5.1 Component Values used in Proposed Mixer 29
Table 5.2 Voltage Bias used in Proposed Mixer 29
Table 5.3 Passive Component Values in Proposed Mixer 29
Table 5.4 IIP3 Performance of Proposed Mixer with PVT 32
Variations
Table 5.5 Performance Comparison of Proposed Mixer with Recent 33
Literature

v
 LIST OF FIGURES

Figure No. Title Page No.

Fig. 1.1 Fixed IF Transmitter 1
Fig. 1.2 Superheterodyne Transmitter 2
Fig. 1.3 RF Receiver Block Diagram 3
Fig. 1.4 Simple circuit to demonstrate Conversion Gain in Mixers 4
Fig. 1.5 Depiction of effect of Noise in RF Mixers 4
Fig. 1.6 Illustration of SSB noise in RF Mixers 6
Fig. 1.7 Illustration of DSB noise in RF Mixers 6
Fig. 1.8 Illustration of 1dB-Compression Point 8
Fig. 1.9 Third-order intermodulation products 9
Fig. 2.1 Proposed Ultra wideband LNA using noise cancellation 10
and current re-use technique (Topology 1)
Fig. 2.2 Gilbert cell architecture (Topology 2) 11
Fig. 2.3 Proposed RL degeneration circuit (Topology 2) 12
Fig. 2.4 Existing resistance degeneration circuit (Topology 2) 12
Fig. 2.5 A conventional CBLD circuit (Topology 3) 12
Fig. 2.6 Modified CBLD circuit (Topology 3) 12
Fig. 2.7 Schematic diagram of 90-96 GHz CMOS down- 13
conversion mixer (Topology 4)
Fig. 2.8 Complete schematic of the proposed CMOS active mixer 14
(Topology 5)
Fig. 2.9 Schematic of the Proposed SHM (Topology 6) 16
Fig. 3.1 Proposed topology: Double linearization with feedback 17
Fig. 4.1 Simplified equivalent circuit for gain analysis 20
Fig. 4.2 Calculation of impedances 21
Fig. 4.3 Simplified equivalent circuit for gain analysis 22
Fig. 4.4 Simplified equivalent circuit for linearity analysis 24
Fig. 4.5 Simplified equivalent circuit for impedance matching 25
Fig. 4.6 Calculation of impedance 26
Fig. 5.1 Conversion gain versus LO Power 30
Fig. 5.2 DSB-NF versus frequency 30
Fig. 5.3 IIP3 before linearization 30

vi
Fig. 5.4 IIP3 after linearization 30
Fig. 5.5 Corner analysis of Conversion Gain 30
Fig. 5.6 Corner analysis of DSB-NF 30
Fig. 5.7 Variation of Conversion Gain with voltage 31
Fig. 5.8 Variation of DSB-NF with voltage 31
Fig. 5.9 Variation of Conversion Gain with temperature 31
Fig. 5.10 Variation of DSB-NF with temperature 31
Fig. 5.11 Monte-Carlo simulation of IIP2 31
Fig. 5.12 Monte-Carlo simulation of IIP3 31
Fig. 5.13 Monte-Carlo simulation of Conversion Gain 32
Fig. 5.14 Monte-Carlo simulation of DSB-NF 32
Fig. 5.15 Physical chip layout of proposed Mixer 33
Fig. 5.16 Layout 34

vii
 CHAPTER 1

INTRODUCTION

1.1. WIRELESS TRANSMITTER ARCHITECTURE

Radio frequency transceiver plays a significant role in the wireless communication

system, turns the analog signals into the digital baseband signals, and eventually
determines the reliability of the transmitted signal and the performance of the
communication system. Generally, RF transmitter includes zero-intermediate
frequency (IF) architecture, and super-heterodyne architecture. Zero-IF architecture
transmitters only use conversion once to obtain the analog baseband, however, local
oscillator leakage (LOL), DC offset lead to deterioration of the performance. A
superheterodyne receiver, often shortened to superhet, is a type of radio receiver that
uses frequency mixing to convert a received signal to a fixed intermediate frequency
(IF) which can be more conveniently processed than the original carrier frequency.
Superheterodyne is a traditional structure to implement the transceiver system, but the
complexity of RF circuits brings quantities of work, and simultaneously increases the
cost and size of the whole system.

Fig. 1.1. Fixed IF transmitter

1
 Fig. 1.2. Superheterodyne Transmitter

The major design considerations of a transmitter are frequency of operation, the type of
modulation, the stability and purity of the resulting signal, the efficiency of power use,
and the power level required to meet the system design objectives. High-power
transmitters may have additional constraints with respect to radiation safety, generation
of X-rays, and protection from high voltages.

1.1.1 Friis Transmission Equation

Since it was introduced in 1946. The Friis transmission equation has become extremely
popular amongst wireless communication engineers. The Friis transmission equation
relates the received power (PR) in watts to the transmitter power (PT) in watts, the gain
of the transmitting antenna (GT) and the receiving antenna (GR), distance between the
two (R) and the frequency of the transmission (f).

𝑃𝑇 𝐺𝑇 𝐺𝑅 𝑐 2 (1.1)
𝑃𝑅 =
(4𝜋𝑅𝑓)2

1.2 WIRELESS RECEIVER ARCHITECTURE

With the development of wireless communication, RF integrated circuit is playing a

growing and ever-more critical part of our daily life, and attracts the researchers’
attention. Low power consumption, low hardware cost, and low noise for a RF receiver

2
front-end composed of low noise amplifier (LNA) and mixer is required in the wireless
senor network applications.

LNA

Fig. 1.3. RF receiver block diagram.

The input signal is obtained with the help of the receiving antenna with the input power
at -85 dBm (accounting for the noise and distortions prior to reception). A low noise
amplifier is present to add minimal noise at the input and amplify the input RF signal.
It does not degrade the signal to noise ratio of the signal. A band pass filter removes the
spectral noise before the signal is further processed. The power at the output of the filter
is 65 dBm. The mixer down converts the input frequency to an intermediate frequency.
Conversion to intermediate frequency is required as high frequency processing is
difficult and is bound to be corrupted easily.

This project deals with the design of an RF receiver front-end consisting of a high
linearity mixer. The major focus in the design of the mixer is on minimizing the noise
figure, while maximizing conversion gain as well as linearity performance (IIP3). One
of the major issues in a mixer is the image problem if the input frequencies have
adjacent bands that come within the bandwidth of the band pass filter of the receiver.

Some of the important parameters to be analyzed are the conversion gain, noise figure,
signal to noise ratio and the linearity of the receiver. The fundamental concepts behind
these parameters will be discussed in this section.

3
1.2.1 Conversion Gain

It is generally expressed as voltage gain or as transducer power gain. Measured in dB,

conversion gain measures the signal gain in an active mixer. It is defined as the ratio
between IF output power and RF input power.

Fig. 1.4. Simplified circuit to demonstrate conversion gain of mixers

𝑂𝑢𝑡𝑝𝑢𝑡 𝑃𝑜𝑤𝑒𝑟 𝑎𝑡 𝐼𝑛𝑡𝑒𝑟𝑚𝑒𝑑𝑖𝑎𝑡𝑒 𝐹𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 (1.2)

𝐶𝑜𝑛𝑣𝑒𝑟𝑠𝑖𝑜𝑛 𝐺𝑎𝑖𝑛 =
𝐴𝑣𝑎𝑖𝑙𝑎𝑏𝑙𝑒 𝑖𝑛𝑝𝑢𝑡 𝑅𝐹 𝑃𝑜𝑤𝑒𝑟

1.2.2 Noise Figure

The noise figure of an LNA or a Mixer gives the added noise generated by that
component and present at its output node. The noise figure is the second most important
parameter to be considered while designing RF circuits.

Fig. 1.5. Depiction of effect of noise in an RF Mixer

Input noise power due to the source can be modelled as 𝑘𝑇𝐵, where 𝐵 is the bandwidth
of the input signal, 𝑘 is the Boltzmann constant and 𝑇 is the temperature of the source.
Input signal has the power 𝑃𝑆 at either the lower or upper sideband (or both for direct
conversion).

𝑃𝑆 (1.3)
𝑆𝑁𝑅𝑖 =
𝑘𝑇𝐵

4
At the IF frequency, we have the down-converted signal 𝐺 𝑥 𝑃𝑆 and down-converted
noise from the two sidebands, 𝐿𝑂 − 𝐼𝐹 and𝐿𝑂 + 𝐼𝐹.

𝐺 𝑥 𝑃𝑆 (1.4)
𝑆𝑁𝑅𝑜 =
(𝐺 ′ + 𝐺 ′′ )𝑘𝑇𝐵

Where, 𝐺 is the gain of the mixer for the signal, and 𝐺′ and 𝐺′′ are the gains of the mixer
for the two sidebands respectively. The noise figure is defined as the logarithm of the
ratio of the input SNR to the output SNR.

For an ideal mixer 𝐺 = 𝐺 ′ = 𝐺′′.

𝑆𝑁𝑅𝑖 (1.5)
𝐹=
𝑆𝑁𝑅𝑜
𝑃𝑆 𝑥 2𝑘𝑇𝐵 (1.6)
𝐹= =2
𝑘𝑇𝐵 𝑥 𝑃𝑠

𝑁𝑜𝑖𝑠𝑒 𝑓𝑖𝑔𝑢𝑟𝑒 (𝑁𝐹) = 3 𝑑𝐵 (1.7)

For a real mixer, noise from multiple sidebands can fold into IF frequency and degrade
NF.

Because of the image problem, a receive mixer down converts both desired and the
image bands to IF frequency. This means folding the noise at the image frequency on
top of the desired band at IF. Therefore, the total noise at IF is as follows:

 The noise at the desired RF band down-converted to IF.

 The noise at image RF band down-converted to IF.
 The noise added by the noisy mixer circuit itself.

1.2.2.1 Single Sideband Noise Figure (SSB-NF)

The single-side band NF definition assumes that there is no signal at the image
frequency except the source noise. This definition is useful in finite IF architectures,
where the image signal is suppressed by an image filter before reaching the mixer. The
NF is the degradation of S/N at mixer output. Therefore, one can write:
𝑆𝑜𝑢𝑡 = 𝑆𝑑 𝐺𝑚𝑖𝑥_𝑑 (1.8)

5
 𝑁𝑜𝑢𝑡 = 𝑁𝑑 𝐺𝑚𝑖𝑥_𝑑 + 𝑁𝑖𝑚 𝐺𝑚𝑖𝑥_𝑖𝑚 + 𝑁𝑚𝑖𝑥_𝑑 𝐺𝑚𝑖𝑥_𝑑 + 𝑁𝑚𝑖𝑥_𝑖𝑚 𝐺𝑚𝑖𝑥_𝑖𝑚 (1.9)

where 𝑆𝑑 is the desired signal, 𝑁𝑑 is the noise in the desired band, 𝑁𝑖𝑚 is the noise in
the image band, 𝐺𝑚𝑖𝑥_𝑑 and 𝐺𝑚𝑖𝑥_𝑖𝑚 are the mixer gains at both the desired and image
frequencies respectively. 𝑁𝑚𝑖𝑥_𝑑 And 𝑁𝑚𝑖𝑥_𝑖𝑚 are the desired and image band noise due
to the mixer circuit itself referred to its input.
To simplify the analysis, we will assume 𝑁𝑑 = 𝑁𝑖𝑚 , 𝑁𝑚𝑖𝑥_𝑑 = 𝑁𝑚𝑖𝑥_𝑖𝑚 and 𝐺𝑚𝑖𝑥_𝑑 =
𝐺𝑚𝑖𝑥_𝑖𝑚 .

(1.10)
𝑆𝑜𝑢𝑡 𝑆𝑑 𝑆𝑑 1
= = ( )
𝑁𝑜𝑢𝑡 2𝑁𝑑 + 2𝑁𝑚𝑖𝑥 𝑁𝑑 2𝑁𝑚𝑖𝑥 + 2
𝑁𝑑
2𝑁𝑚𝑖𝑥 (1.11)
𝐹𝑆𝑆𝐵 = 2 +
𝑁𝑑

Fig. 1.6. Illustration of SSB noise in RF Mixers

1.2.2.2 Double Sideband Noise Figure (DSB-NF)

Fig. 1.7. Illustration of DSB noise in RF Mixers

6
The double-side band NF definition assumes that the image band contains both noise
and an image signal identical to the desired band signal. This definition is useful in
direct-conversion receiver where the image is the signal itself. Therefore, one can write:
𝑆𝑜𝑢𝑡 = 𝑆𝑑 𝐺𝑚𝑖𝑥_𝑑 + 𝑆𝑖𝑚 𝐺𝑚𝑖𝑥_𝑖𝑚 (1.12)
𝑁𝑜𝑢𝑡 = 𝑁𝑑 𝐺𝑚𝑖𝑥_𝑑 + 𝑁𝑖𝑚 𝐺𝑚𝑖𝑥_𝑖𝑚 + 𝑁𝑚𝑖𝑥_𝑑 𝐺𝑚𝑖𝑥_𝑑 + 𝑁𝑚𝑖𝑥_𝑖𝑚 𝐺𝑚𝑖𝑥_𝑖𝑚 (1.13)
Where, 𝑆𝑖𝑚 is the image signal.
To simplify analysis, we will assume 𝑆𝑑 = 𝑆𝑖𝑚 , 𝑁𝑑 = 𝑁𝑖𝑚 , 𝑁𝑚𝑖𝑥_𝑑 = 𝑁𝑚𝑖𝑥_𝑖𝑚 and
𝐺𝑚𝑖𝑥_𝑑 = 𝐺𝑚𝑖𝑥_𝑖𝑚 .

(1.14)
𝑆𝑜𝑢𝑡 2𝑆𝑑 𝑆𝑑 1
= = ( )
𝑁𝑜𝑢𝑡 2𝑁𝑑 + 2𝑁𝑚𝑖𝑥 𝑁𝑑 𝑁𝑚𝑖𝑥
+ 1
𝑁𝑑
𝑁𝑚𝑖𝑥 (1.15)
𝐹𝐷𝑆𝐵 = 1 +
𝑁𝑑

Therefore, 𝑁𝑜𝑢𝑡 = 2𝑁𝑑 𝐺𝑚𝑖𝑥_𝑑 = 2𝑁𝑚𝑖𝑥 𝐺𝑚𝑖𝑥_𝑑

It can be seen that the difference between the SSB NF and DSB NF is exactly 3dB.
1.5.2.3 Noise Figure for Cascaded Stages

For cascaded stages, the noise figure is given by the Friis noise equation:

𝑁𝐹2 − 1 𝑁𝐹𝑘 − 1 (1.16)

𝑁𝐹𝑡𝑜𝑡 = 1 + 𝑁𝐹1 + + ⋯+
𝐺1 𝐺1 𝐺2 … 𝐺𝑘−1

1.2.3 Linearity

Linearity is critical for systems transmitting carrier signals. Because RF/microwave

amplifiers are based on semiconductors, which are inherently nonlinear devices, they
fall prey to nonlinear behavior under certain operating conditions. One of these is when
boosting the multiple-tone signals commonly used in wireless communications
systems. Nonlinear behavior can result in signals mixing and generating unwanted
levels of intermodulation distortion (IMD).

The nonlinear behavior tends to worsen as an amplifier approaches saturation, when

operating with the highest possible input signals. However, an amplifier operating at
saturation is also functioning at its highest efficiency.

7
Several standard performance parameters help expose an amplifier’s potential
nonlinearity: 1-dB compression (P1dB) point, second-order intercept (IP2) point, and
third-order intercept point (TOI or IP3) point. An amplifier’s compression point refers
to an operating condition at which the output signal level no longer increases by the
same amount as the input signal level (with the input signal increased as a function of
the amplifier’s gain). Amplifiers are usually operated 1 dB below the compression point
to preserve linearity and achieve acceptable efficiency.

An amplifier’s IP2 and IP3 points are meant to express either input or output power
levels beyond which linearity can be expected. Due to nonlinear behavior, an amplifier
will generate a certain amount of IMD as a function of input power. When the IMD
increases by 2 dB for every 1-dB increase in input power, it is said to be second-order
distortion. When the IMD increases by 3 dB for every 1-dB increase in input power, it
is referred to as third-order IMD.

1.2.3.1 1dB-Compression Point

Fig. 1.8. Illustration of 1dB-Compresion point

Most linear amplifiers have a fixed gain for a specific frequency range. The slope of
the line is the gain. As the input power continues to increase, at some point the gain
begins to decrease. The amplifier goes into compression where no further output
increases occur for an input increase. Its response becomes non-linear and produces

8
signal distortion, harmonics, and potentially intermodulation products. The 1-dB
decrease may be specified as the input level that produces it or the output power where
the 1-dB drop occurs.

1.2.3.2 Third order Input referred Intercept Point

If the input signals are close together in frequency, some of the sum and difference
frequencies called intermodulation products produced can occur within the bandwidth
of the amplifier. These cannot be filtered out, so they will ultimately become interfering
signals to the main signals to be amplified.

Fig. 1.9.Third order intermodulation products

The two input signals with frequencies f1 and f2 occur within the amplifier bandwidth.
With distortion, new signals f1 – f2 and f1 + f2 are produced. They can usually be filtered
out. However, these signals will also mix with the second, third, and higher harmonics
to produce a wide range of potentially interfering signals with the amplifier pass band.
The most troublesome are the third-order products, which are 2f1 ± f2 and 2f2 ± f1. Those
possibly occurring in the amplifier frequency range are 2f1 – f2 and 2f2 – f1.

Assume two input signals of frequencies f1 and f2.

The ultimate and penultimate third order frequencies fall into the bandwidth of the band
pass filter of the receiver and cause intermodulation.

9
 CHAPTER 2
LITERATURE SURVEY

The battery-powered IoT devices are expected to run at least a day without the need for
recharging. For RF signal reception, the circuits in the IoT device consumes power
constantly in the ON state. The RF signal processing circuits such as the LNA and
Mixer requires sufficient power for providing proper performances in terms of linearity,
conversion gain, and noise figure. Thus, the current challenge in the wireless industry
is to develop circuit techniques that consume low power and low silicon area without
compromising the system’s linearity performance. Some other techniques to improve
the performance of the mixer are discussed below.

2.1 LOW POWER BALUN LNA USING NOISE CANCELLATION:

The author of [1] has described a low power, single to differential (balun) low noise
amplifier (LNA) using noise cancellation and current re-use techniques is presented for
ultra wide-band applications. An upsurge balun LNA is designed using UMC 0.18-μm
RF CMOS technology with an emphasis on the covenant between gain, bandwidth and
power dissipation.

Fig.2.1. Proposed UWB-LNA using noise cancellation and current re-use techniques.

10
The proposed balun exerts a differential stage on top of common gate-common source
(CG-CS) stage. A CG-CS stage exploits amalgamation of CG stage (for wide-band
impedance matching) and CS to curtail gain and phase imbalance, while simultaneously
negating the noise and distortion of input matching transistor. The escalation of
bandwidth has been accomplished using staggered tuning on CG-CS and differential
stages. The stacked differential amplifier does cancellation of self noise as well as
supply noise.

The proposed UWB balun LNA achieves 14 dB voltage gain with agreeable input
reverse isolation (S11) of <−8 dB over the frequency range of 3.19–8.8 GHz. The
minimum noise figure of 3.9 dB and P1dB of −10.5 dBm while exhausting 3.8 mW
from 1.2 V supply. The superlative performance of balun LNA is accomplished
between 3.19 and 8.8 GHz with gain and phase errors below 0.2 dB and 0. 40
respectively. The layout occupying 0.77 sq.mm area.

2.2. RF DOWN-CONVERSION GILBERT CELL:

The author of [2] has proposed a design of RF down-conversion Gilbert-Cell, with 65

nm CMOS technology, at a supply voltage of 1.8 V, with a new degenerating structure
to improve linearity. This architecture opens the way to more integrated CMOS RF
circuits and to achieve a good characteristics in terms of evaluating parameters of RF
mixers with a very low power consumption (2.17 mW).

Fig.2.2. Gilbert cell architecture.

11
 Fig.2.3. Proposed RL degeneration circuit. Fig.2.4. Existing resistance degeneration
circuit.

At 1.9 GHz RF frequency; obtained results show a third order input intercept point
(IIP3) equal to 11.6 dBm, Noise Figure (NF) is 4.12 dB, when conversion gain is 8.75
dB.

2.3. BALUN LNA USING CURRENT BLEEDING TECHNIQUE:

The author of [3] has proposed a new noise-cancelling method that employs a modified
current-bleeding (CBLD) technique and balanced loads is presented by developing a
design for a low-noise and high linearity balun-low-noise amplifier (LNA) for
broadband applications.

Fig.2.5. a conventional CBLD circuit. Fig.2.6.Modified CBLD circuit.

12
The basic common-gate (CG)–common-source (CS) balun topology cannot achieve a
noise figure (NF) of less than 3 dB. Thus, a practical topology containing a CS transistor
of which the transconductance is N times larger than that of the CG transistor and a CS
resistor of which the resistance is N times smaller than that of the CG resistor is often
used to decrease the NF.

The proposed modified CBLD technique enables the balun-LNA to achieve differential
balanced output, low noise, and low-second-order distortion characteristics. The
proposed balun-LNA is implemented in 65-nm CMOS technology and covers the
frequency range of 50 MHz–1 GHz. It achieves a voltage gain of 30 dB, an S11 of less
than −10 dB, an OIP3 of 25.9 dBm, and an OIP2 of 50.6 dBm. The minimum NF is 2.3
dB whereas the average NF is 2.63 dB across the whole band. It operates at a nominal
supply voltage of 2.2 V with bias currents of 9 mA. The active die area is 0.0448 sq.mm.

2.4. DOWN-CONVERSION MIXER USING NRC TECHNIQUE:

The author of [4] has proposed a 90-96 GHz down-conversion mixer for 94 GHz image
radar sensors using standard 90 nm CMOS technology. RF negative resistance
compensation (NRC) technique, i.e. NMOS LC-oscillator-based RF transconductance
(GM) stage load, is used to increase the output impedance and suppress the feedback
capacitance Cgd of RF GM stage. By doing so, conversion gain (CG), noise figure (NF)
and LO-RF isolation of the mixer can be enhanced.

Fig.2.7. Schematic diagram of the 90~96 GHz CMOS down-conversion mixer.

13
The mixer consumes 15 mW and achieves excellent RF-port input reflection coefficient
of 10~ 36.4 dB for frequencies of 85~105 GHz. The corresponding 10 dB input
matching bandwidth is 20 GHz. In addition to this, for 90~96 GHz frequencies, the
mixer achieves CG of 6.3~9 dB (the corresponding 3-dB CG bandwidth is greater than
6 GHz) and LO-RF isolation of 40~45.1 dB. The mixer also achieves an excellent input
third-order intercept point (IIP3) of 1 dBm at 94 GHz.

2.5. ACTIVE MIXER USING DERIVATIVE SUPERPOSITION:

The author of [5] a high linearity, enhanced conversion gain, and low noise figure (NF)
CMOS active mixer is presented for wideband applications using the derivative
superposition and noise cancellation techniques.

Fig.2.8. Complete schematic of the proposed CMOS active mixer.

The third-order input intercept point (IIP3) of the proposed mixer is improved by
cancelling the intrinsic second-order derivative trans conductance (gm) of the main

14
transistor. This is achieved by using an auxiliary transistor which is biased in the weak
inversion region to create gm with the same amplitude and opposite sign relative to the
main transistor. A linear path consisting of two parallel transistors is utilized to cancel
the thermal noise of the input transistors and a constant trans conductance (Gm) bias
circuit is employed to achieve robust performance against process, voltage and
temperature variations.

The simulated mixer operates from 500 MHz to 3.1 GHz RF input frequency. Post-
layout circuit-level simulation results using a 90-nm RF CMOS process with Spectre-
RF reveal that the IIP3 and conversion gain of the proposed mixer are improved about
6.1 dB and 6.2 dB. Also, the NF of the proposed mixer is decreased about 2 dB. The
simulated S11 is less than − 12 dB in whole RF range. It consumes 13.9 mW from a
single 1.1 V power supply.

2.6. WIDEBAND GILBERT SHM USING REGULATED CASCODE STAGE

AND INDUCTIVE CONNECTION:

The author of [6] has proposed a design for a wideband Gilbert sub harmonic mixer
(SHM) that partly overcomes the fundamental trade-off between radio frequency (RF)
and intermediate frequency (IF) currents. Compared to the conventional SHM, the
proposed SHM features large gain, low noise figure (NF) and moderate linearity over
a wide bandwidth by concurrent usage of regulated-cascode RF-stage and inductive
connection between RF and LO stages.

15
 Fig.2.9. Schematic of proposed SHM.

Simulations using a 0.18 Micro metre RF-CMOS process demonstrate that the proposed
mixer, at a fixed IF of 100 MHz, exhibits more than 5 dB and 2 dB improvements in
conversion gain (CG) and NF, respectively.

16
 CHAPTER 3
PROPOSED TOPOLOGY

Fig. 3.1. Proposed Topology: Double Linearization with Feedback

One of the major issues faced in a mixer is low linearity and high power consumption.
The linearity of the circuit is determined by the ability of the mixer to reject the
intermodulation products and thus reproduce only a scaled version of the input radio
frequency signal. The circuit is designed to consume low power at a 5GHz.

The input transistors of the circuit are M1 and M2. M1 is a common gate transistor
NMOS which takes the input RF signal (VRF). The M2 which is also NMOS transistor
works in the common source topology. The outputs of these two transistors are
amplified. They move through the inductors L1 and L2 which are used as tuning circuits
with the capacitors C1 and C2. The signals enter the transistors M5 (NMOS) and M6
(NMOS), which also act in the common gate topology. The resistors R1 and R2 along

17
with M7 (NMOS) and M8 (NMOS), which are diode connected transistors act as the
load for the circuit. Resistors R3 and R4 are used for biasing M5 and M8. The
differential outputs from the drains of M5 and M6 are given to the sources of M9
(NMOS) and M10 (NMOS). Transistors M3 (NMOS) and M4 (NMOS) are attached to
the drains of M1 and M2. The outputs taken from the drains of M5 (VOUT+) and M6
(VOUT-) are also given a Gilbert cell. They are given to the sources of M12 (PMOS)
and M13 (PMOS). The differential outputs from the local oscillator (VLO+, VLO-) are
given to the gates of M11 (PMOS), M12, M13 and M14 (PMOS). Loads M15 (NMOS)
and M16 (NMOS) are used current sources. The differential outputs of intermediate
frequencies are taken from the drains of M11 (VIF+) and M12 (VIF-).

The proposed RF mixer consists of an amplification stage, linearization stage, feedback

stage and a mixing stage. A detailed description of the effect of each stage on the
incoming RF signal is given in this section.

3.1 AMPLIFICATION STAGE

The amplification consists of a CG-CS stage with a differential pair stacked on top of
them. A CG-CS stage helps in amalgamation of two main factors- impedance matching
property of the CG stage to the antenna and the CS stage helps in reducing the
imbalance in gain and the phase of the input. It also helps in negating the noise and
distortion introduced by the input matching transistor. The stacked differential stage
cancels the self and supply noise and also adds substantial gain to input. The cascode
connection helps in reducing the distortion effects due to temperature and fluctuations
of the supply voltages.

3.2 LINEARIZATION STAGE

Transistors M3 and M4 are the linearization transistors for M1 and M2 respectively,

which help in the increasing the IIP3 of the circuit. The non-linear dependence of the
current on the bias voltage of M3 and M4 helps in cancelling the second-order
transconductance of M1 and M2 respectively. Thus it helps in increasing the linearity
of the circuit.

18
3.3 FEEDBACK STAGE

M9 and M10 are the feedback transistors. Cross coupling of the outputs taken at the
drains of M5 and M6 helps in giving a negative feedback topology which reduces the
noise figure of the circuit. The feedback stage also contributes in helping the linearity
of the circuit by reducing the magnitude of the intermodulation products.

3.4 MIXING STAGE

It produces output signals that are proportional to the product of two input signals.
Such circuits are widely used for frequency conversion in radio systems. The advantage
of this circuit is the output current is an accurate multiplication of the (differential) base
currents of both inputs. As a mixer, its balanced operation cancels out many unwanted
mixing products, resulting in a "cleaner" output.

19
 CHAPTER 4

ANALYSIS

The following parameters were considered for the analysis during the design of the
circuit- gain, noise figure, linearity and input impedance.

𝑔𝑚 denotes the trans conductance of the MOSFET. 𝑟𝑜 denotes the resistance of the
MOS device when it is operating in saturation between the source and drain.
𝑉𝑔𝑠 denotes the voltage between the source and gate of a transistor. 𝑋𝐿 and 𝑋𝑐 denote
the reactances of inductors and capacitors respectively. 𝑍 denotes the impedance of
the circuit. The subscripts denote the transistors to which the entities belong.

4.1 GAIN ANALYSIS

For the input transistor M1 the input RF signal is given to its source denoted by𝑉𝑖𝑛 .

Fig.4.1. Simplified equivalent circuit for gain analysis

20
 𝑍 + 𝑍𝑜

𝑍𝑜 + 𝑍

𝑍𝑠

Fig.4.2.Calculation of impedances. On the left- 𝑍𝑜 + 𝑍. On the right- 𝑍𝑠

Node 1:

Let the voltage at the node be𝑉1′ .

(𝑉1 ′ − 𝑉𝑖𝑛 )⁄ 𝑉𝑖𝑛

𝑔𝑚1 𝑉𝑔𝑠 + 𝑟𝑜1 = ⁄𝑍
𝑠
(4.1)

Node 2:

𝑍𝑜
𝑉𝑜𝑢𝑡 = 𝑉1 ′
𝑍𝑜 + 𝑍
(4.2)

21
Thus the gain for 𝑉𝑜𝑢𝑡+ is given by -

𝑟 𝑟
𝑍𝑜 { 𝑜1⁄𝑍 + 1 + 𝑜1⁄𝑔𝑚1 }
𝑉 𝑠
𝐴𝑣 = 𝑜𝑢𝑡⁄𝑉 = (4.3)
𝑖𝑛 𝑍𝑜 + 𝑍
𝑍 = 𝑋𝐿1 + 1⁄𝑔𝑚5 (4.4)

𝑍𝑜 = 𝑅1 // 1⁄𝑔𝑚7 (4.5)

𝑍𝑠 = 𝑋𝐿3 + 𝑟𝑜9 (4.6)

Equation (4.3) gives the gain of the half circuit with the common gate as the input
topology.

For the input transistor M2, the input RF signal is given to its source denoted by𝑉𝑖𝑛 .

Fig.4.3.Simplified equivalent circuit for gain analysis

Node 1:

Let the voltage at the node be 𝑉1′ .

𝑉𝑠 𝑉1 ′ − 𝑉𝑠
= 𝑔𝑚2 (𝑉𝑖𝑛 − 𝑉𝑠 ) +
𝑍𝑠 𝑟𝑜2 (4.7)

𝑉1 ′ 𝑉1 ′𝑍𝑠 𝑉1 ′ − 𝑉𝑠
= 𝑔𝑚2 (𝑉𝑖𝑛 − )+
𝑍 + 𝑍𝑜 𝑍 + 𝑍𝑜 𝑟𝑜2 (4.8)

22
 𝑉1 ′ (4.9)
𝑉𝑜𝑢𝑡 =
𝑍 + 𝑍𝑜

Upon solving equations (4.8), (4.9), (4.10), the gain

𝑉𝑜𝑢𝑡 𝑔𝑚2 𝑍 2 𝑜 𝑟𝑜2

𝐴𝑣 = =
𝑉𝑖𝑛 (1 + 𝑔𝑚2 𝑍𝑠 + 𝑍𝑠 𝑟𝑜2 )𝑍𝑜 𝑟𝑜2 − 𝑍𝑜 (𝑍 + 𝑍𝑜 ) (4.10)
𝑍𝑠 = 𝑟10 (4.11)

Equation (4.10) gives the gain of the half circuit with the common source as the input
topology.

4.2 NOISE FIGURE

The noise components of the circuit are MOSFETS and the resistors. The input
referred noise of the transistor can be calculated as the ratio of the power spectral
density of the output noise and the square of the gain of the transistor. The input stage
offers minimal noise to the circuit compared to the mixer stage.

The noise offered by the mixer stage is given by –

2 2𝛾𝑅𝐿 𝐼
𝑣 𝑜,𝑛 = 8𝑘𝑇𝑅𝐿 ( 1 + + 𝛾𝑔𝑚 𝑅𝐿 )
𝜋𝐴𝑙𝑜
(4.12)

Where 𝑘 is the Boltzmann Constant, 𝑇 is the temperature in Kelvin, 𝑅𝐿 is the load

resistance, 𝐼 is the bias current, 𝐴𝑙𝑜 is the amplitude of the local oscillator signal, 𝑔𝑚 is
the trans conductance of the mixer and 𝛾 is the process dependent parameter with
value between 2-3 for 180nm process.

4.3 LINEARITY

23
The circuit aims to improve the linearity of the mixer. The linearization transistors M3
and M4 are used for the linearization.

The figure depicts the effect of linearization transistor M3 on M1.

𝑉𝑏𝑖𝑎𝑠

Fig.4.4.Simplified circuit for analysis of linearity

𝑖𝑜 = 𝑖1 + 𝑖3 (4.13)

𝑖1 = 𝐺𝑚,𝑚1 𝑉𝑔𝑠1 + 𝐺′𝑚,𝑚1 𝑉𝑔𝑠1 2 + 𝐺′′𝑚,𝑚1 𝑉𝑔𝑠1 3 + ⋯ (4.14)

𝑔𝑚1 (4.15)
Where 𝐺𝑚,𝑚1 = ⁄1 + 𝑔 𝑍
𝑚1 𝑠

𝑖3 = 𝑔𝑚,𝑚3 𝑉𝑔𝑠1 + 𝑔′𝑚,𝑚3 𝑉𝑔𝑠1 2 + 𝑔′′𝑚,𝑚3 𝑉𝑔𝑠1 3 + ⋯ (4.16)

Substituting in (4.13) and (4.15) in (4.12) –

24
 𝑖𝑜 = 𝑉𝑔𝑠1 (𝐺𝑚,𝑚1 + 𝑔𝑚,𝑚3 ) + 𝑉𝑔𝑠1 2 (𝐺′𝑚,𝑚1 + 𝑔′𝑚,𝑚3 ) (4.17)

+ 𝑉𝑔𝑠1 3 (𝐺′′𝑚,𝑚1 + 𝑔′′𝑚,𝑚3 ) + ⋯

Here (.)’ and (.)’’ denote the differentiation and double differentiation of the
respective entities. Similarly the effect current of M4 on current of M2 can be shown
to be the same.

By making (𝐺 ′′ 𝑚,𝑚1 + 𝑔′′ 𝑚,𝑚3 ) of the circuit zero, the magnitude of third order input

referred intercept point can be increased.

4.4 INPUT IMPEDANCE ANALYSIS

To calculate the input impedance, a voltage source 𝑉𝑥 from which a current of 𝑖𝑥

flows in the circuit is placed at the source of M1.

Fig.4.5.Simplified equivalent circuit for impedance matching

25
 𝑍𝑖𝑛

Fig.4.6. Calculation of impedance 𝑍𝑖𝑛

At node 1:

For the input transistor M1 the gate to source voltage 𝑉𝑔𝑠 . Let the voltage at the node
1 be 𝑉1’

𝑔𝑚1 𝑉𝑔𝑠 + (𝑉1 ′ − 𝑉𝑥 ) + 𝑖𝑥 = 0

(4.18)
𝑉1 ′ = −𝑉𝑥
(4.19)

At node 2:

1
[𝑉𝑥 (𝑟 + 𝑔𝑚1 ) − 𝑖𝑥 ]𝑟𝑜1
𝑜1
= 𝑖𝑥 (4.20)
1
𝑋𝐿1 + 𝑔
𝑚5

26
Solving equation (4.3) we get,

1
𝑉𝑥 𝑋𝐿1 + 𝑔 + 𝑟𝑜1⁄
𝑍= = 𝑚5
𝑖𝑥 1 + 𝑔𝑚1 𝑟𝑜1 (4.21)

Hence the total input impedance is given by –

𝑍(𝑗𝜔𝐿3 + 𝑟𝑜9 )
𝑍𝑖𝑛 = 1⁄𝑗𝜔𝐶 +
5 𝑍 + 𝑗𝜔𝐿3 + 𝑟𝑜9
(4.22)

27
 CHAPTER 5
RESULTS AND DISCUSSION

The proposed Mixer is designed and implemented in UMC 180nm deep n-well CMOS
process for wideband operation. The post-layout characterization of the Mixer is
completed using SpectreRF circuit simulator from Cadence. The gain and noise figure
plot for the LNA is shown in Fig. 5.1 and 5.2 respectively. The Mixer provides a
maximum conversion gain of 15.33 dB at LO Power value of -4 dBm, and also stays
within acceptable limits within a frequency range of 4GHz to 6GHz. Within this range,
the noise figure also stays below 5dB. The Mixer has a minimum noise figure of 12.51
dB at 5GHz. The linearity performance is measured by means of 1dB-compression
point (1dB-CP), IIP2 and IIP3. The 1dB-CP and IIP3 values are measured from the
harmonic balance analysis with two-tone inputs. The tones were selected to be closely
spaced at 5GHz and 5.01GHz respectively. The IIP3 is measured at 11.04 dBm. The
IIP3 values before and after linearization are shown in Fig. 5.3 and 5.4 respectively.

The device sizing of the proposed structure is listed in Table 5.1. The bias voltages
applied to the transistors are described in Table 5.2. Table 5.3 gives the characteristics
of the passive components in the circuit. The gain and noise performance of the
proposed Mixer at the limiting process corners such as Fast-Fast (FF), Fast NMOS-
Slow PMOS (FNSP), Slow NMOS-Fast PMOS (SNFP), and Slow-Slow (SS) is
analyzed in figures 5.5 and 5.6 respectively. The gain and NF performance with voltage
and temperature variation is illustrated in figures 5.7 to 5.10 respectively. The voltage
variation is ±100𝑚𝑉 from the nominal supply voltage of 1V. For temperature variation
analysis, the circuit was characterized at different temperatures of -40C, 0C, 27C and
125C respectively. The IIP3 and Noise Figure performance of the Mixer at different
corners, voltages and temperatures is listed in Tables 5.4 and 5.5. During silicon
fabrication, process and device mismatch occurs. The designed RF circuit must be able
to withstand such parasitic changes that occur during fabrication. Hence, the effect of
the process and device mismatch on circuit performance is analyzed using Monte-Carlo
simulations and the results are shown in figures 5.11 to 5.14. MC analyses show the
mean (µ), standard deviation (σ) of the circuit parameters. MC simulation was run for
100 random samples of the circuit’s device and process parameters.

28
 TABLE 5.1: COMPONENT VALUES USED IN PROPOSED DESIGN

Component Width
M1,M2 100u
M3,M4 6u
M5, M6 100u
M 7 , M8 80u
M9, M10 90u
M11, M12, M13, M14 80u
M15, M16 10 x 50u

TABLE 5.2: VOLTAGE BIAS USED IN PROPOSED DESIGN

Voltage Source Bias Value

V1 700mV
V2 600mV
Vtail 300mV
Vdd 1V
Vbias 1V

TABLE 5.3: PASSIVE COMPONENT VALUES

INDUCTOR Values
Inductance 5.342nH
Diameter 208.72um
Width 6um
Turn Number 3.5

29
Fig. 5.1. Conversion gain versus LO Fig. 5.2. DSB-NF versus frequency
Power

Fig. 5.3. IIP3 before linearization Fig. 5.4. IIP3 after linearization

Fig 5.5. Corner analysis of Conversion Fig. 5.6. Corner analysis of DSB-NF
Gain

30
Fig. 5.7. Variation of Conversion gain Fig. 5.8. Variation of Conversion gain
with voltage with temperature

Fig. 5.9. Variation of DSB-NF with Fig. 5.10. Variation of DSB-NF with
voltage temperature

𝜇 = 81.31

𝜎 = 798

N= 100

Fig. 5.11. Monte-Carlo simulations of Fig. 5.12. Monte-Carlo simulations of

IIP2 values IIP3 values

31
 𝜇 = 19.10

𝜎 = 4.83

N = 100

Fig. 5.13. Monte-Carlo simulations of Fig. 5.14. Monte-Carlo simulations of

Conversion Gain values DSB-NF values

TABLE 5.4: IIP3 PERFORMANCE OF MIXER WITH PVT VARIATIONS

Corners Temperature Voltage

Parameters FF FNSP SNFP SS -40C 0C 125C 0.99V 1.01V
IIP3 (dBm) -4.52 -11 -1.135 -2.83 -4.87 -0.78 -1.68 8.216 9.187
IIP2 (dBm) 75.96 63 82.73 79.33 75.26 83.44 81.64 101.4 103.4

The proposed RF mixer is compared with the recently proposed mixer circuits [1, 2, 3,
4, 5, 6] in Table 5.5. The performance of the RF circuits are quantified by the figure-
of-merit (FoM) given as:

10𝐺𝑎𝑖𝑛⁄20 . 10𝐼𝐼𝑃3⁄20 (5.1)

𝐹𝑜𝑀 = 10. log10
10𝑁𝐹⁄10 . 𝑃

32
 TABLE 5.5: PERFORMANCE COMPARISON OF PROPOSED MIXER
WITH RECENT LITERATURE.

This [1] [2] [3] [4] [5] [6]

Work
Year 2019 2017 2014 2018 2017 2018 2017
Technology (nm) 180 180 65 65 90 90 180
Bandwidth (GHz) 4-6 5-10.6 1.2-2.8 0.05-1 90-95 0.5-3.1 5-10
Gain (dB) 15.33 10 8.75 30 7.65 15 18.5
NF (dB) 12.51 3.9 4.12 2.63 16.9 6.7 8.8
IIP3 (dBm) 11.04 -10.5 11.6 25.9 1.0 9.5 -4
Power (mW) 1.539 3.8 2.02 19.8 15 13.9 12
FoM1 20.441 7.60 10.43 19.44 0.038 12.57 14.8
FoM2 28.81 18.5 17.35 16.67 0.022 14.37 13.65

Fig. 5.15 illustrates the physical chip layout of the proposed mixer. The layout is
designed using the UMC 180nm CMOS process. The Design Rule Check (DRC) and
Layout versus Schematic (LVS) analysis were done using the Assura tool. The core
area of the proposed structure is 10385.66 sq.um.

Fig. 5.15: Physical chip layout of proposed mixer.

33
Fig. 5.16: Layout of active region of proposed mixer

34
 CHAPTER 6

SUMMARY AND CONCLUSIONS

6.1 SUMMARY

In this project, a novel high linear and ultra-low power RF mixer circuit, is designed
and implemented in UMC 180 nm process technology, and post-layout characterization
is performed using industry standard Cadence SpectreRF. The Mixer provides a gain
of 15.33 dB and a minimum noise figure of 12.51 dB at 5 GHz. The proposed double
linearizatin with feedback based RF Mixer achieves an IIP3 of 11.04 dBm. The high
linearity performance of the Mixer combined with low power consumption of 1.539
mW makes the proposed Mixer a suitable choice for wireless applications like WLAN,
Zigbee, Bluetooth, MobileFi, WiMAX. The proposed Mixer offers the best in class
performance for Mixers in the 5 GHz range.The core circuit is implemented in a chip
area of 10385.6627 sq.um. Thus, the proposed RF mixer accomplishes the challenge of
low cost, low power, high linearity and high-performance required by the wireless
industry for IEEE 802.15.4 wireless personal area network applications.

6.2 SCOPE FOR FUTURE WORK

The project does leave a considerable amount of scope for future work, in terms of
extending the robustness of the mixer module by incorporating it into an RF front end.

35
 CHAPTER 7
PUBLICATIONS

S.Chrisben Gladson, Vijayalakshmi.S, M. Sowmya Lakshmi, M.Bhaskar. A high linear

balanced RF mixer using Double Linearization for 5 GHz applications. (Research
paper in progress)

36
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