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    Sync and Asyc FIFO

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    vshokin
    A synchronous FIFO uses a single clock for writing and reading, while an asynchronous FIFO transfers data between different clock domains using synchronized write and read pointers. Synchronization is achieved using a binary to gray code and gray to binary code converters to resolve metastability issues. While a single flip-flop chain is insufficient, adding delay is not a problem. The asynchronous FIFO is implemented in VHDL and tested to verify functionality at different clock frequencies.

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    Sync and Asyc FIFO

    Uploaded by

    vshokin
    514 views3 pages
    A synchronous FIFO uses a single clock for writing and reading, while an asynchronous FIFO transfers data between different clock domains using synchronized write and read pointers. Synchronization is achieved using a binary to gray code and gray to binary code converters to resolve metastability issues. While a single flip-flop chain is insufficient, adding delay is not a problem. The asynchronous FIFO is implemented in VHDL and tested to verify functionality at different clock frequencies.

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    A synchronous FIFO uses a single clock for writing and reading, while an asynchronous FIFO transfers data between different clock domains using synchronized write and read pointers. Synchronization is achieved using a binary to gray code and gray to binary code converters to resolve metastability issues. While a single flip-flop chain is insufficient, adding delay is not a problem. The asynchronous FIFO is implemented in VHDL and tested to verify functionality at different clock frequencies.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    514 views3 pages

    Sync and Asyc FIFO

    Uploaded by

    vshokin
    A synchronous FIFO uses a single clock for writing and reading, while an asynchronous FIFO transfers data between different clock domains using synchronized write and read pointers. Synchronization is achieved using a binary to gray code and gray to binary code converters to resolve metastability issues. While a single flip-flop chain is insufficient, adding delay is not a problem. The asynchronous FIFO is implemented in VHDL and tested to verify functionality at different clock frequencies.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 3
    At a glance
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    The key takeaways are that synchronous and asynchronous FIFOs are discussed. Synchronous FIFOs use one clock for writing and reading while asynchronous FIFOs transfer data between two clock domains using synchronization circuits.

    The purpose of designing an asynchronous FIFO is to allow communication between different clock domains by transferring data between a write clock domain and a read clock domain.

    Synchronization is needed between the read and write pointers in an asynchronous FIFO to determine the full/empty flags and FIFO size. The read pointer must be synchronized to the write domain and the write pointer must be synchronized to the read domain.

    EXERCISE 2 (Asynchronous FIFO)

    The purpose of this exercise is to design an asynchronous FIFO for communication between different clock
    domains. First, synchronous FIFO design is reviewed followed by an introduction to asynchronous FIFO
    design.

    Synchronous FIFO
    A Block diagram of a synchronous FIFO is shown below. It is synchronous because only one clock signal
    exists, and this clock signal is used for both writing and reading.
    write_data_in read_data_out

    Dual port memory


    waddr

    raddr
    wen

    ren
    clk

    reset

    write_enable FIFO Control read_enable

    fifo_occupancy

    full empty

    We assume that the Dual port memory has 2^n locations, i.e. the write and read addresses have n bits:
    waddr[n-1:0],raddr[n-1:0]. Internally in the FIFO control module, pointers are used to determine memory
    addresses, full status, empty status and FIFO occupancy. As we will see in the following, it is convenient to
    have (n+1) pointer bits. Thus, the write and read addresses are determined from the n least significant
    pointerbits:
    waddr[n-1:0] = wptr[n-1:0],
    raddr[n-1:0] = rptr[n-1:0].

    Full/empty flags.
    The write pointer is incremented for each write operation. The most significant bit (wptr[n]) indicates if the
    write address has wrapped around an even or uneven number of times. Ditto for the read pointer.
    If (waddr=raddr) the FIFO is either full or empty. The additional pointer bit can be utilized to distinguish
    between the two situations: if (wptr[n]=rptr[n]) the FIFO is empty, and if (wptr[n]!=rptr[n]) the FIFO is
    full.

    FIFO occupancy.
    The FIFO occupancy can be calculated from the pointer values. Also in this case, the most significant
    pointer bits are utilized to perform the calculation:
    (wptr[n]=rptr[n]) : fifo_size = wptr[n-1:0] - rptr[n-1:0],
    (wptr[n]!=rptr[n]) : fifo_size = 2^n – (rptr[n-1:0] - wptr[n-1:0])

    The relationship between FIFO pointers and occupancy is illustrated below with three examples.
    wptr=000 rptr=000 wptr=010 rptr=000 wptr=100 rptr=000

    11 11 11

    10 10 10

    01 01 01

    00 00 00

    occupancy = 0 occupancy = 4
    occupancy = 2
    FIFO is empty FIFO is full

    Asynchronous FIFO
    Asynchronous FIFOs are commonly used to transfer data between two clock domains. A block diagram is
    shown below. In order to determine full/empty flags and FIFO size, the read pointer (rptr) must be syn-
    chronized to the write domain, and the write pointer (wptr) must be synchronized to the read-domain.

    write_data_in read_data_out

    Dual port memory


    waddr

    raddr
    wen

    ren
    rclk

    wclk wptr rclk


    SYNC

    reset reset

    write_enable FIFO Write FIFO Read read_enable


    Control Control
    fifo_occu_in rptr fifo_occu_out
    SYNC

    full empty
    wclk

    TASK 1

    Typically, synchronization is achieved by a chain of flip-flops to resolve metastability, as shown below:

    rclk

    wptr wptr_sync

    Explain why this circuit is insufficient for use in the asynchronous fifo design. Would it be beneficial to
    add more flip-flops in the chain?
    TASK 2

    Correct synchronization is obtained with the circuit below. Explain why. Specify logical equations for the
    binary to gray code converter and for the gray to binary code converter.
    rclk

    Binary code Gray code


    wptr to to wptr_sync
    gray code binary code
    converter converter

    The synchronization circuit introduces a delay. Is this a problem?

    TASK 3

    Implement the Asynchronous FIFO. The entity declaration is given below. The Xilinx LogiCORE tool can
    generate the dual-port memory.

    entity async_fifo is
    port (
    reset : in std_logic;
    wclk : in std_logic;
    rclk : in std_logic;
    write_enable : in std_logic;
    read_enable : in std_logic;
    fifo_occu_in : out std_logic_vector(4 downto 0);
    fifo_occu_out : out std_logic_vector(4 downto 0);
    write_data_in : in std_logic_vector(7 downto 0);
    read_data_out : out std_logic_vector(7 downto 0)
    );
    end async_fifo;

    Synthesize and place & route the code and note the clock frequency (device: Xilinx XCV 812E – 8C).
    Verify the design in a testbench.

    Report
    The report must contain:
    • Answers to questions in task 1 & task 2
    • VHDL code
    • Test results
    • Synthesis report, Place & route report

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