APB

APB Protocol v 1.
Introduction
Transfers
Operating States
Signal Descriptions
Conventions
This section describes the conventions that this specification uses:
Typographical
Timing diagrams
Signals
Typographical
This specification uses the following typographical conventions:
Italic - Highlights important notes, introduces special

terminology,denotes internal cross-references, and citations.
Bold - Highlights interface elements, such as menu names. Denotes
ARM processor signal names. Also used for terms in descriptive lists,
where appropriate.
Monospace - Denotes text that you can enter at the keyboard, such as
commands, file and program names, and source code.
Monospace - Denotes a permitted abbreviation for a command or option.

You can enter the underlined text instead of the full command or option
name.
monospace italic - Denotes arguments to monospace text
where the argument is to be replaced by a specific value.
monospace bold - denotes language keywords when used

outside example code.
<and> - Angle brackets enclose replaceable terms for assembler

syntax where they appear in code or code fragments. They appear
in normal font in running text. For example:
MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2>

The Opcode_2 value selects which register is accessed.
Timing diagrams
The figure named Key to timing diagram conventions explains the

components used in timing diagrams. Variations, when they occur,
have clear labels. You must not assume any timing information that
is not explicit in the diagrams. Shaded bus and signal areas are
undefined, so the bus or signal can assume any value within the
shaded area at that time. The actual level is unimportant and does
not affect normal operation.
Timing diagrams
Signals
The signal conventions are:

Signal level - The level of an asserted signal depends on
whether the signal is active-HIGH or active-LOW. Asserted

means HIGH for active-HIGH signals and LOW for active-
LOW signals.
Prefix P - Denotes AMBA 3 APB signals.
Suffix n - Denotes AXI, AHB, and AMBA 3 APB reset
signals.
About the AMBA 3 APB
The APB is part of the AMBA 3 protocol family. It provides a low cost
interface that is optimized for minimal power consumption and reduced
interface complexity.
The APB interfaces to any peripherals that are low-bandwidth and do not
require the high performance of a pipelined bus interface. The APB has
unpipelined protocol.
All signal transitions are only related to the rising edge of the clock to
enable the integration of APB peripherals easily into any design flow.
Every transfer takes at least two cycles.
The APB can interface with the AMBA Advanced High-performance
Bus Lite (AHB-Lite) and AMBA Advanced Extensible Interface (AXI).
You can use it to provide access to the programmable control registers of
peripheral devices.
Changes for AMBA 3 APB Protocol
Specification v1.0
This version includes:

A ready signal, PREADY, to extend an APB transfer.
An error signal, PSLVERR, to indicate the failure of a
transfer.
Transfers
Write transfers
Two types of write transfer are described in this
section:
With no wait states
With wait states.
With no wait states

The write transfer starts with the address, write data, write signal and select signal all changing
after the rising edge of the clock. The first clock cycle of the transfer is called the Setup phase.
After the following clock edge the enable signal is asserted, PENABLE, and this indicates that
the Access phase is taking place. The address, data and control signals all remain valid
throughout the Access phase. The transfer completes at the end of this cycle.
The enable signal, PENABLE, is de-asserted at the end of the transfer. The select signal,
PSELx, also goes LOW unless the transfer is to be followed immediately by another transfer to
the same peripheral.
With wait states
Figure shows how the PREADY signal from the slave can extend
the transfer. During an Access phase, when PENABLE is HIGH, the
transfer can be extended by driving PREADY LOW. The following
signals remain unchanged for the additional cycles:
address, PADDR
write signal, PWRITE
select signal, PSEL
enable signal, PENABLE
write data, PWDATA.
Write transfer with wait states
PREADY can take any value when PENABLE is LOW. This
ensures that peripherals that have a fixed two cycle access can
tie PREADY HIGH.
NOTE - It is recommended that the address and write signals

are not changed immediately after a transfer but remain stable
until another access occurs. This reduces power consumption.
Read transfers
Two types of read transfer are described in this

section:
With no wait states
With wait states.
With no wait states
Figure shows a read transfer. The timing of the address, write, select, and
enable signals are as described in Write transfers on page 2-2. The slave
must provide the data before the end of the read transfer
With wait states
Figure shows how the PREADY signal can extend the transfer. The
transfer is extended if PREADY is driven LOW during an Access phase.
The protocol ensures that the following remain unchanged for the
additional cycles:
address, PADDR
write signal, PWRITE
select signal, PSEL
enable signal, PENABLE.
Figure shows that two cycles are added using the PREADY signal.
However, you can add any number of additional cycles, from zero
upwards.
Error response
You can use PSLVERR to indicate an error condition on an APB

transfer. Error conditions can occur on both read and write
transactions.
PSLVERR is only considered valid during the last cycle of an APB
transfer, when PSEL, PENABLE, and PREADY are all HIGH
It is recommended, but not mandatory, that you drive PSLVERR
LOW when it is not being sampled. That is, when any of PSEL,
PENABLE, or PREADY are LOW.
Error response contd..
Transactions that receive an error, might or might not have changed the
state of the peripheral. This is peripheral-specific and either is acceptable.
When a write transaction receives an error this does not mean that the
register within the peripheral has not been updated. Read transactions that
receive an error can return invalid data. There is no requirement for the
peripheral to drive the data bus to all 0s for a read error.
APB peripherals are not required to support the PSLVERR pin. This is
true for both existing and new APB peripheral designs. Where a
peripheral does not include this pin then the appropriate input to the APB
bridge is tied LOW.
Write transfer
Figure shows an example of a failing write transfer that completes
with an error.
Read transfer
A read transfer can also complete with an error response, indicating that
there is no valid read data available. Figure 2-6 on page 2-7 shows a read
transfer completing with an error response.
Mapping of PSLVERR
When bridging:
From AXI to APB An APB error is mapped back to
RRESP/BRESP = SLVERR. This is achieved by mapping
PSLVERR to the AXI signals RRESP[1] for reads and BRESP[1]
for writes.
From AHB to APB PSLVERR is mapped back to HRESP =
ERROR for both reads and writes. This is ac

Operating States
Figure shows the operational activity of the APB.
The state machine operates through the following
states:
IDLE - This is the default state of the APB.
SETUP - When a transfer is required the bus moves

into the SETUP state, where the appropriate select
signal, PSELx, is asserted. The bus only remains in the
SETUP state for one clock cycle and always moves to
the ACCESS state on the next rising edge of the clock.
Contd....
ACCESS - The enable signal, PENABLE, is asserted in the

ACCESS state. The address, write, select, and write data
signals must remain stable during the transition from the
SETUP to ACCESS state. Exit from the ACCESS state is
controlled by the PREADY signal from the slave:
1 - If PREADY is held LOW by the slave then the peripheral bus remains in
the ACCESS state.
2 - If PREADY is driven HIGH by the slave then the ACCESS state is exited
and the bus returns to the IDLE state if no more transfers are required.
Alternatively, the bus moves directly to the SETUP state if another transfer
follows.
Signal Descriptions
AMBA 3 APB signals

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APB Protocol v 1.

This section describes the conventions that this specification uses:

This specification uses the following typographical conventions:

Italic - Highlights important notes, introduces special

commands, file and program names, and source code.

Monospace - Denotes a permitted abbreviation for a command or option.

monospace bold - denotes language keywords when used

<and> - Angle brackets enclose replaceable terms for assembler

MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2>

The figure named Key to timing diagram conventions explains the

The signal conventions are:

whether the signal is active-HIGH or active-LOW. Asserted

This version includes:

With wait states.

With no wait states

NOTE - It is recommended that the address and write signals

Two types of read transfer are described in this

With wait states.

With no wait states

write signal, PWRITE

select signal, PSEL

enable signal, PENABLE.

You can use PSLVERR to indicate an error condition on an APB

Figure shows an example of a failing write transfer that completes

From AHB to APB PSLVERR is mapped back to HRESP =

ERROR for both reads and writes. This is ac

IDLE - This is the default state of the APB.

SETUP - When a transfer is required the bus moves

ACCESS - The enable signal, PENABLE, is asserted in the

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