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    Current Simulation Time Value of Clock Signal Reset

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    sumanaachar
    This document contains questions about Verilog HDL concepts including data types, modules, ports, simulation, coding styles, and system tasks. It asks about declaring arrays, parameters and variables of different types. Questions cover topics like top-down and bottom-up design methodologies, shift registers, ripple carry counters, port connections, hierarchical names and stimulus blocks.

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    Current Simulation Time Value of Clock Signal Reset

    Uploaded by

    sumanaachar
    57 views3 pages
    This document contains questions about Verilog HDL concepts including data types, modules, ports, simulation, coding styles, and system tasks. It asks about declaring arrays, parameters and variables of different types. Questions cover topics like top-down and bottom-up design methodologies, shift registers, ripple carry counters, port connections, hierarchical names and stimulus blocks.

    Original Description:

    INTERVIEW QUESTIONS ON vlsi

    Original Title

    VLSI IC

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    This document contains questions about Verilog HDL concepts including data types, modules, ports, simulation, coding styles, and system tasks. It asks about declaring arrays, parameters and variables of different types. Questions cover topics like top-down and bottom-up design methodologies, shift registers, ripple carry counters, port connections, hierarchical names and stimulus blocks.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    57 views3 pages

    Current Simulation Time Value of Clock Signal Reset

    Uploaded by

    sumanaachar
    This document contains questions about Verilog HDL concepts including data types, modules, ports, simulation, coding styles, and system tasks. It asks about declaring arrays, parameters and variables of different types. Questions cover topics like top-down and bottom-up design methodologies, shift registers, ripple carry counters, port connections, hierarchical names and stimulus blocks.

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    © All Rights Reserved
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    You are on page 1of 3

    1. Explain Typical Design flow of VLSI IC.

    2. What is design methodology? Explain Top-down design methodology with an example of


    fulladder using two half adders. Design half adders using basic gates.
    3. What is design methodology? Explain bottom-up design methodology with an example of 3-
    bit ripple carry counter using TFF using DFF.
    4. With a neat block diagram for 4-bit ripple carry counter explain design hierarchy. Explain the
    top-down approach of Verilog code for 4-bit ripple carry counter using TFF. Design TFF using
    DFF.
    5. Explain the necessity of HDL
    6. Discuss the trends in HDL
    7. List Different abstraction levels in Verilog HDL
    8. What is Logic synthesis? What does logic synthesis tool do?
    9. Discuss importance of HDL
    10. Define and explain module with an example.
    11. Define Lexical conventions. List and explain each.
    12. Define verilog data type. Explain i) Integer ii) reg
    13. Define verilog data type. Explain i) time ii) real
    14. Define verilog data type. How is array declared?
    Declare i) multi-dimensional array of each element 1-bit wide.
    ii) array of 10 elements with each element of 4 bit wide
    15. Define verilog data type. How is array declared?
    Declare i) array to count integer value.
    ii) array to store 100 simulation time
    16. Define verilog data type. How is array declared?
    Declare i) array of 16 bit vector wire
    ii) Array of 2 dimensional matrix to store binary bits in each element
    17. What is simulation?
    18. What is string? How to declare a string in Verilog HDL.
    19. Explain system task. Define i) $display
    ii) $time Give an example each
    20. Explain system task. Define i) $finish
    ii) $monitor
    iii) $stop Give an example each

    21. Write a Verilog description of SR latch using gate level description. Also write stimulus block
    22. Explain kinds of stimulus applied with an example each
    23. Write a note on i) registers ii) memories iii) vectors
    24. Write a note on i) parameter ii) arrays iii) nets
    25. Explain value sets and strength levels in Verilog
    26. Use $monitor to display the value of clock signal that toggles every 5 screen time units and
    reset value that goes down up every 15 screen time units. Let the monitor statement display
    Current simulation time value of clock signal = reset =
    27. Mention the difference between stop and $finish using an example
    28. Explain compiler directive with an example
    29. Declare following variables in Verilog
    a. An 8-bit vector net called a_in
    b. A time variable called snap_shot
    c. A 32-bit storage called address in Little endian format.
    30. Explain little endian and big endian format. Explain with an example in Verilog declaration.\
    31. Explain vector part select with various examples
    32. Define parameter. Declare a parameter cache_size equal to 512
    33. Define array. Declare array that contains 20 elements of the type integer
    34. Declare a memory MEM containing 256 words of 64 bits each
    35. What would be the output of following statement
    a. Latch = 4’d12;
    $display(the current value of latch = %b\n”,latch);
    What is %b, \n ?
    b. in_reg = 3’d12;
    $monitor($time, “register value in_reg = %b\n” in_reg);
    c. ‘define MEM_SIZE 1024
    $display(the maximum memory size is %h”,MEM_SIZE);
    36. Declare a toplevel module as “stimulus”. Define din 4bit, clk 1-bit as registers and dout 4bit
    as wire. Instantiate a “shift_register” module that has A(4-bit),clock(1-bit) and Out(4 bit)
    output. No need to write any logic of internal functions. Write a Verilog code to connect
    ports by ordered list.
    37. Write a stimulus block for 4-bit ripple carry counter.Explain components of simulation
    38. Define identifiers, keywords,escaped identifiers with an example
    39. Explain Verilog port list with an example
    40. What are port connection rules in Verilog
    41. How to connect ports to external signals? Explain with example
    42. Explain Design Hierarchy ? hierarchical path name ? explain with an example of SR latch
    43. What are basic components of module? Which components are mandatory?
    44. Does a module that does not interact with its environment have any i/o ports? Does it have
    a port list in module definition?
    45. Declare a toplevel module as “stimulus”. Define din 4bit, clk 1-bit as registers and dout 4bit
    as wire. Instantiate a “shift_register” module that has A(4-bit),clock(1-bit) and Out(4 bit)
    output. No need to write any logic of internal functions. Write a Verilog code to connect
    ports by name
    46. Declare a toplevel module as “stimulus”. Define din 4bit, clk 1-bit as registers and dout 4bit
    as wire. Instantiate a “shift_register” module that has A(4-bit),clock(1-bit) and Out(4 bit)
    output. No need to write any logic of internal functions. Write the hierarchical names for
    din,clk,out
    47. Declare a toplevel module as “stimulus”. Define din 4bit, clk 1-bit as registers and dout 4bit
    as wire. Instantiate a “shift_register” module that has A(4-bit),clock(1-bit) and Out(4 bit)
    output. No need to write any logic of internal functions. Write the hierarchical names for
    shift_register, clock, A
    48. List string format specification in display system task.
    49. Explain number specification Verilog
    50. What is instance? Explain with an example.

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