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Verilog For Testing Module 6

This document discusses test benches (test fixtures) in Verilog for testing digital designs. It explains that a test bench is an additional Verilog module used to simulate a design and generate stimulus and verify responses. A test bench contains the design under test and virtual wires connected to its inputs and outputs. It generates stimulus, applies it to the design, and compares outputs to expected values to verify correctness. Creating an effective test bench that thoroughly tests a design can be a complex task.

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Kent Genzen Corpus
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22 views

Verilog For Testing Module 6

This document discusses test benches (test fixtures) in Verilog for testing digital designs. It explains that a test bench is an additional Verilog module used to simulate a design and generate stimulus and verify responses. A test bench contains the design under test and virtual wires connected to its inputs and outputs. It generates stimulus, applies it to the design, and compares outputs to expected values to verify correctness. Creating an effective test bench that thoroughly tests a design can be a complex task.

Uploaded by

Kent Genzen Corpus
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Test Benches (Test Fixtures)

Verilog for Testing

Jim Duckworth, WPI 1 Verilog for Testing - Module 6


Overview
• We have concentrated on Verilog for synthesis
• Can also use Verilog as a test language
• Very important to conduct comprehensive verification on
your design
• To simulate your design you need to produce an additional
module that includes your synthesizable Verilog design.
– Usually referred to as a TEST BENCH or TEST FIXTURE
• Not hardware, just additional Verilog!

Jim Duckworth, WPI 2 Verilog for Testing - Module 6


Test Bench
• A virtual platform containing the design to be tested
(UUT) and virtual wires connected to the UUT inputs and
outputs.
• To exercise and verify the correctness of a design to be
implemented in hardware
• Has three main purposes
– to generate stimulus for simulation
– to apply this stimulus to the module under test and to collect output
responses
– to compare output responses with expected values
• Test Bench should be created by a different engineer than
the one who created the synthesizable Verilog

Jim Duckworth, WPI 3 Verilog for Testing - Module 6


Test Bench – Virtual Platform

Module
Apply to be Verify
Stimulus Tested Responses
(UUT)

Jim Duckworth, WPI 4 Verilog for Testing - Module 6


Test Bench Overview
• A Test Bench module consists of
– Port list has NO ports
– Instantiate module to be tested (UUT)
– Declare internal signals to wire to UUT inputs and outputs
– Verilog statements to provide stimulus and verify UUT responses
– Designing a test bench that has good coverage can be a very
involved project!

Jim Duckworth, WPI 5 Verilog for Testing - Module 6


Test Bench - general structure
module decoder_tf;

internal signal declarations

UUT: test_component instantiation

signals to generate stimulus

statements to verify responses

endmodule

ina
inb out1
UUT
inc

Jim Duckworth, WPI 6 Verilog for Testing - Module 6


Example Decoder – is the design correct?

Verilog for Testing - Module 6


Jim Duckworth, WPI 7
Create Test Fixture
• Select Simulation View
• Select Project => New Source

• Select decoder source to associate with test fixture


Verilog for Testing - Module 6
Jim Duckworth, WPI 8
Outline of Test Fixture produced

Verilog for Testing - Module 6


Jim Duckworth, WPI 9
Apply input stimulus

Verilog for Testing - Module 6


Jim Duckworth, WPI 10
Simulate Behavioral Model

Verilog for Testing - Module 6


Jim Duckworth, WPI 11
Testing sequential logic
• Creating clock signal

• Can also ‘restart’, ‘run’, and add internal signals to wave

Verilog for Testing - Module 6


Jim Duckworth, WPI 12

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