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Verilog For Modeling - Module 9b

This document discusses Verilog modeling and provides examples of modeling basic components like AND gates and flip-flops, as well as more complex memories like SRAM and DDR SDRAM. It shows how to create Verilog models with parameters to customize behavior, add timing checks to models, and use models for testing other Verilog modules. Commercial memory models are also briefly mentioned.

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47 views

Verilog For Modeling - Module 9b

This document discusses Verilog modeling and provides examples of modeling basic components like AND gates and flip-flops, as well as more complex memories like SRAM and DDR SDRAM. It shows how to create Verilog models with parameters to customize behavior, add timing checks to models, and use models for testing other Verilog modules. Commercial memory models are also briefly mentioned.

Uploaded by

benny.mao.sh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Verilog for Modeling

Module 9

Jim Duckworth, WPI 1 Verilog for Modeling - Module 9


Overview
• General examples
– AND model
– Flip-flop model
– SRAM Model
• Customizing Models
– Generics in VHDL
• DDR SDRAM Model
– Parameters in Verilog
• Commercial memory models

Jim Duckworth, WPI 2 Verilog for Modeling - Module 9


Verilog for Modeling
• We have covered
– Verilog for Synthesis
– Verilog for testing (simulation)
• Now - Verilog for modeling
• Describes the expected behavior of a component or device
• Can be used to test other components
– for example a model of a CPU could be used to test:
• UART
• DRAM memory controller
• cache controller

Jim Duckworth, WPI 3 Verilog for Modeling - Module 9


AND gate model

Jim Duckworth, WPI 4 Verilog for Modeling - Module 9


Simulation Results

Jim Duckworth, WPI 5 Verilog for Modeling - Module 9


D flip-flop model

Jim Duckworth, WPI 6 Verilog for Modeling - Module 9


Timing Check Tasks in Verilog
• Specify block can be used to specify setup and hold times for signals
– specify and endspecify (Use specparam to define parameters in specify
block)
• $setup (data, clock edge, limit)
– Displays warning message if setup timing constraint is not met
– $setup(d, posedge clk, 10)
• $hold (clock edge, data, limit)
– Displays warning message if hold timing constraint is not met
– $hold(posedge clk, d, 2)
• $width (pulse event, limit)
– Displays warning message if pulse width is shorter than limit
– $width(posedge clk, 20) – specify start edge of pulse
• $period (pulse event, limit)
– Check if period of signal is sufficiently long
– $period(posedge clk, 50)

Jim Duckworth, WPI 7 Verilog for Modeling - Module 9


Adding setup and period timing checks

Jim Duckworth, WPI 8 Verilog for Modeling - Module 9


Detecting timing violations

WARNING: at 225 ns: Timing violation in /d_model_tf/uut/ $period( clk:175 ns, :225 ns, 60 ns)
WARNING: at 275 ns: Timing violation in /d_model_tf/uut/ $period( clk:225 ns, :275 ns, 60 ns)
WARNING: at 325 ns: Timing violation in /d_model_tf/uut/ $setup( d:321 ns, clk:325 ns,10 ns)
WARNING: at 325 ns: Timing violation in /d_model_tf/uut/ $period( clk:275 ns, :325 ns, 60 ns)

Jim Duckworth, WPI 9 Verilog for Modeling - Module 9


Using Specparam

Jim Duckworth, WPI 10 Verilog for Modeling - Module 9


Test Bench – no models
• SRAM connections are open

open
UUT
Adding the SRAM model
• New testbench

SRAM
UUT
Model
Very Simple SRAM Model

Jim Duckworth, WPI 13 Verilog for Modeling - Module 9


Viewing Contents of Array

Select SRAM then


right mouse click
=>Memory Editor

Jim Duckworth, WPI 14 Verilog for Modeling - Module 9


Adding Timing Checks and Delay

Jim Duckworth, WPI 15 Verilog for Modeling - Module 9


Testing with Test Bench

Jim Duckworth, WPI 16 Verilog for Modeling - Module 9


Warning Messages

Jim Duckworth, WPI 17 Verilog for Modeling - Module 9


DDR SDRAM Model

Jim Duckworth, WPI 18 Verilog for Modeling - Module 9


DDR SDRAM Model (cont’d)

Jim Duckworth, WPI 19 Verilog for Modeling - Module 9


DDR SDRAM Model (cont’d)

Jim Duckworth, WPI 20 Verilog for Modeling - Module 9


DDR SDRAM Model (cont’d) - VHDL

Jim Duckworth, WPI 21 Verilog for Modeling - Module 9


Jim Duckworth, WPI 22 Verilog for Modeling - Module 9
ISSI SRAM – Verilog Model (partial)
• // IS61LV25616 Asynchronous SRAM, 256K x 16 = 4M; speed: 10ns.
• // Note; 1) Please include "+define+ OEb" in running script if you want to check
• // timing in the case of OE_ being set.
• // 2) Please specify access time by defining tAC_10 or tAC_12.

• // `define OEb
• `define tAC_10
• `timescale 1ns/10ps

• module IS61LV25616 (A, IO, CE_, OE_, WE_, LB_, UB_);

• parameter dqbits = 16;


• parameter memdepth = 262143;
• parameter addbits = 18;
• parameter Toha = 2;

• parameter Tsa = 2;

• `ifdef tAC_10
• parameter Taa = 10,
• Thzce = 3,
• Thzwe = 5;
• `endif

• `ifdef tAC_12
• parameter Taa = 12,
• Thzce = 5,
• Thzwe = 6;
• `endif

• input CE_, OE_, WE_, LB_, UB_;


• input [(addbits - 1) : 0] A;
• inout [(dqbits - 1) : 0] IO;
•
• wire [(dqbits - 1) : 0] dout;
• reg [(dqbits/2 - 1) : 0] bank0 [0 : memdepth];

Jim Duckworth, WPI 23 Verilog for Modeling - Module 9


Micron SRAM on Nexys3
board
Complete model is > 1300 lines!

Jim Duckworth, WPI 24 Verilog for Modeling - Module 9


Jim Duckworth, WPI 25 Verilog for Modeling - Module 9
Jim Duckworth, WPI 26 Verilog for Modeling - Module 9
Jim Duckworth, WPI 27 Verilog for Modeling - Module 9

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