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·OP-AMPS
AND LINEAR
INTEGRATED CIRCUIT
..
TECHNOLOGY
RAMAKANT A. GAYAKWAD
Missouri Institute of Technology

Kansas City, Missouri
Prentice,Hall of India l?ir~® loma'ft®~

New Delhi-110001
1987
\I
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·.· ·: .
. .;:..
This Indian Reprint-Rs. 65.00

(Original U.S. Edition-Rs. 651.00)
·.•
OP-AMPS AND LINEAR INTEGRATED CIRCUIT TECHNOLOGY ~
'··.....:
by Ramakant A. Gayakwad
PRENTICE-HALL INTERNATIONAL, INC., Englewood Cliffs.

PRENTICE-HALLINTERNATIONAL, INC., London.
PRENTICE-HALL OF AUSTRALIA, PTY. LTD., Sydney.
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© 1983 by Prentice-Hall, lnc., Englewood Cliffs, N.J., U.S.A. All rights

reserved. No part of this book may be reproduced in any form, by
mimeograph or any other means, without permission in writing from the
publishers.
ISBN-0-87692-4 75-5
The export rights of this book are vested solelv with the publisher.
This Eastern Economy Edition is the only authorised, complete and

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Reprinted in India by special arrangement with Prentice-Hall, Inc.,

Englewood Cliffs, N.J., U.S.A. 1
Printed by Jay Print Pack Private Limited, Mew Delhi-110015 and

Published by Prentice-Hall of India Private Limited, M-97, Connaught
Circus, New Delhi-110001.
To my father and mother
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Contents
PREFACE KV
FOREWARD
1 DIFFERENTIAL A/VD CASCODE AMPLIFIERS 1
1-1 Introduction 1
1-2 Differential Amplifier 1
1-3 Differential Amplifier Circuit Configurations 3
1-4 Dual-Input, Balanced-Output Differential Amplifier 4
1-4.1 DC Analysis 4
1-4.2 AC Analysis 5
1-4.3 Inverting and Noninverting Inputs 9
1-4.4 Common-Mode Rejection Ratio 10
'
1-5 · Dual-Input, Unbalanced-Output Differential Amplifier 11
1-5.l· DC Analysis 11
1-5.2 AC Analysis 12
1-6 Single-Input, Balanced-Output Differential Amplifier 14
1-6.J DC Analysis 14
v
1-7 Single-Input, Unbalanced-Output Differential Amplifier 17
1-7.1 DC Analysis 18
1-8 FET Differential Amplifiers 21
1-9 Differential Amplifier with Swamping Resistors 21
1-10 Constant Current Bias 25
1-11 Current Mirror 29
1-1 l Cascaded Differential Amplifier Stages 35
1-13 Level Translator 37
1-14 Cascode or CE-CB Configuration 42
1-14.1 DC Analysis 43
1-14.2 AC Analysis 44 ,
Summary 47
Questions 47
Problems 48
Experiments: 54
1-1 Differential Amplifier Using Constant Current Bias 54
1-2 Cascaded Differential Amplifier with Level Translator 57
1-3 Cascode Amplifier 60
2 INTRODUCTION TO OPERATIONAL AMPLIFIERS 64 I'
2-1 Introduction 64
2-2 The Operational Amplifier 64
2-3 Block Diagram Representation of a Typical Op-Amp 65
2-4 Analysis of Typical Op-Amp Equivalent Circuits 65
--2,.5 Schematic Symbol 72
2-6 Integrated Circuits 72
2-7 Types of Integrated Circuits 73
2-8 Manufacturers' Designations for Integrated Circuits 74
2-9 Development of Integrated Circuits 76
2-9.1 SS/, MS/, LSI, and VLSI Packages 78
2-10 Integrated Circuit Package Types, Pin Identification,
and Temperature Ranges 78 1
2-10.1 Package Types 78
2-10.2 Pin Identification 80
2-10.3 Temperature Ranges 80
2-11 Ordering Information 81
2-12 Device Identification 82
vi Contents
2-13 Power Supplies for Integrated Circuits 83
Summary 84
Questions 85
Problems 85
3 1/t!TERPRETATION OF DATA SHEETS AND CHARACTERISTICS

~AN~~~ . 81/
I
3-1 Introduction 87
3-2 Interpreting a Typical Set of Data Sheets 87
3-3 The Ideal Op-Amp 105
3-4 Equivalent Circuit of an Op-Amp 106
3-5 Ideal Voltage Transfer Curve I 07
3-6 Open-Loop Op-Amp Configurations 107
3-6.1 The Differential Amplifier 108
3-6.2 The Inverting Amplifier 108 1· ...
3-6.3 The Noninverting Amplifier 109

Summary 111
Questions 111
Problems 112
4 AN OP-AMP WITH N.EGATIVE FEEDBACJ<
4-1 Introduction 113

4-2 Block Diagram Representation of Feedback Configurations 114
4-3 Voltage-Series Feedback Amplifier 116
4-3.J Negative Feedback 116
4-3.2 Closed-Loop Voltage Gain 117
4-3.3 Difference Input Voltage Ideally Zero 118
4-3.4 Input Resistance with Feedback 119
4-3.5 Output Resistance with Feedback 120
4-3.6 Bandwidth with Feedback 121
4-3.7 Total Output Offset Voltage with Feedback 122
1-3.8 Voltage Follower 123
4-4 Voltage-Shunt Feedback Amplifier 125
4-4.1 Closed-Loop Voltage Gain 126
4-4.2 Inverting Input Terminal at Virtual Ground 127
4-4.3 Input Resistance with Feedback 128
4-4.4 Output Resistance with Feedback 129
4-4.5 Bandwidth with Feedback 129
4-4.6 Total Output Offset Voltage with Feedback 130
Contents vii·
4-4.7 Current-to-Voltage Converter 130
4-4.8 Inverter 131
4-5 Differential Amplifiers 133
4-5.1 Differential Amplifier with One Op-Amp 133
4-5.2 Differential Amplifier with Two Op-Amps 135
4-5.3 Differential Amplifier with Three Op-Amps 137
4-5.4 Output Resistance and Bandwidth of Differential Amplifiers
with Feedback 140
Summary 141
Questions 142
Problems 142
Experiments: 144 .
4-1 Noninverting Amplifier with Feedback 144
4-2 Inverting Amplifier with Feedback 147
4-3 Differential Amplifier with Feedback 149
THE PRACTICAL OP-AMP 153

5-2 Input Offset Voltage 153
5-2.1 Offset-Voltage Compensating Network Design 155
5-3 Input Bias Current 164
5-4 Input Offset Current 170
5-5 Total Output Offset Voltage 172
5-6 Thermal Drift 174
5-6.1 Error Voltage 177
5- 7 Effect of Variation in Power Supply Voltages on Offset Voltage 182
5-8 Change in Input Off set Voltage and Input Offset Current
with Time 186 ·
5-9 Other Temperature- and Supply Voltage-Sensitive Parameters 187
5-10 Noise 190
5-11 Common-Mode Configuration and Common-Mode
Rejection Ratio 192
Summary 195
Questions 196
Problems 196
Experiments: 198
5-1 Measuring and Setting Offset Voltage 198
5-2 Using the Offset Voltage Compensating Network 201
viii Contents
6 FREQUENCY RESPOJtJSE OF AN OP-AMP

6-2 Frequency Response 205
6-3 Compensating Networks 206
6-4 Frequency Response of Internally Compensated Op-Amps 208
6-5 Frequency Response of Noncompensated Op-Amps 208
6-6 High Frequency Op-Amp Equivalent Circuit 209
6-7 Open-Loop Voltage Gain as a Function of Frequency 210
6-8 Closed-Loop Frequency Response 216
6-9 Circuit Stability 217
6-10 Slew Rate 218
6-10.1 Causes of Slew Rate 220
6-10.2 Slew Rate Equation 221 .,
6-10.3 Effect of Slew Rate in Applications 222
6-10.4 Difference between.Bandwidth, Transient Response,
and Slew Rate 224
Summary 224
Questions 225
Problems 225
Experiments: 227
6-1 Frequency Response of Noncompensated Op-Amp 709C 227
6-2 Measuring Slew Rate 230
I
?___; GENERAL LINEAR APP!ICAT/0,'VS 233---
7-2 DC and AC Amplifiers 234
7-2.1 DC Amplifier 234
7-2.2 AC Amplifier 234
7-3 AC Amplifiers with a Single Supply Voltage 238
7-4 The Peaking Amp!ifier 240
7-5 Summing, Scaling, and Averaging Amplifiers 242
7-5.J Inverting Configuration 242
7;5,2 Noninverting Configuration 244
7-5.3 Differential Configuration 246
7-6 Instrumentation Amplifier 248
7-6.l Instrumentation Amplifier Using Transducer Bridge 249
7-7 Differential Input and Differential Output Amplifier 255
Contents ix
7-8 Voltage-to-Current Converter with Floating Load 257
7-8.1 Low-Voltage DC Voltmeter 258
7-8.2 Low-Voltage AC Voltmeter 259
7-8.3 Diode Match Finder 261
7-8.4 Zener Diode Tester 262
7-8.5 Light-Emitting Diode Tester 262
7-9 Voltage-to-CurrentConverter with Grounded Load 262
7-10 Current-to-Voltage Converter 264
7-10.1 DAC Using Current-to-Voltage Converter 264
7-10.2 Detecting Current through Photosensitive Devices 265
7-11 Very High Input Impedance Circuit 266
7.:.12 The Integrator 268
7-13 The Differentiator 271
Summary 275
Questions 275
Problems 276
Experiments: 278
7-1 AC Inverting Amplifier 278
7-2 An Integrator 280
,8
'..__/
; ACTIVE FILTERS AND OSCILLATORS 283

8-2 Active Filters 283
8-3 First-Order Low-Pass Butterworth Filter 286
8-3.1 Filter Design 188
8-3.2 Frequency Scaling 288
8-4 Second-Order Low-Pass Butterworth Filter 290
8-4.1 Filter Design 291
8-5 First-Order High-Pass Butterworth Filter 293
8-6 Second-Order High-Pass Butterworth Filter 295
8- 7 Higher-Order Filters 297
8-8 Band-Pass Filters 299
8-8.1 Wide Band-Pass Filter 299
8-8.2 Narrow Band-Pass Filter 302 I
8-9 Band-Reject Filters 304

8-9.1 Wide Band-Reject Filter 304
8-9.2 Narrow Band-Reject Filter 305
8-10 All-Pass Filter 307
8-11 Oscillators 308
x Contents
8-11.1 Oscillator Principles 309
8-11.2 Oscillator Types 310
8-11.3 Frequency Stability 310
8-12 Phase Shift Oscillator 310
8-13 Wien Bridge Oscillator 312
8-14 Quadrature Oscillator 313
8-15 Square-Wave Generator 315
8-16 Triangular-Wave Generator 317
I
8-17 Sawtooth-Wave Generator 321
8-18 Voltage-Controlled Oscillator 322
Summary 325
Questions 327
Problems 327
Experiments: 328
8-1 First-Order Low-Pass and High-Pass Filters 328
8-2 Wien Bridge Oscillator 330 .
8-3 Square-Wave, Triangular-Wave, or Sawtooth-Wave Generator 332
(!_j COMPARATORSAND CONVERTERS 336

9-2 Basic Comparator 336
9:..3 Zero-Crossing Detector 338
9-4 Schmitt Trigger 340
·9.5 Comparator Characteristics 343
9-6 Limitations of Op-Amps as Comparators 343
9- 7 Voltage Limiters 344
9-8 High-speed and Precision-Type Comparators 347
9-9 Window Detector 348
9-10 Voltage-to-Frequency and Frequency-to-Voltage Converters 350
9-10.1 V/F Converter 350
9-10.2 Ff V Converter 357
9-11 Analog-to-Digital and Digital-to-Analog Converters 361
9-11.i D/A Converters 362
9-11.i AID Converters 367
9-12 Clippers and Clampers 370
9-12.1 Positive and Negative Clippers 370
9-12.2 Small-Signal Half-Wave Rectifiers 373
9-12.3 Positive and Negative Clampers 375
Contents xi
9-13 Absolute-Value Output Circuit 377
9-14 Peak Detector 380
9-15 Sample-and-Hold Circuit 381
Summary 383
Questions 384
Problems 384
Experiments: 385
9-1 Comparator and Schmitt Trigger 385
9-2 Digital-to-Analog Converter Using the R-2R Ladder Network 388
10 SPECIALIZED IC APPLICATIONS 391

10-2 Universal Active Filter 391
10-2.1 Design Procedure 393
10-3 The 555 Timer 401
10-3.1 The 555 as a Monostable Multivibrator 401
10-3.2 Monostable Multivibrator Applications 406
10-3.3 The 555 as an Astab/e Multivibrator 407
10-3.4 Astable Multtvibrator Applications 410
10-4 Phase-Locked Loops 412
10-4.1 Operating Principles 413
10-4.2 Monolithic Phase-Locked Loops 418
10-4.3 565 PLL Applications 423
10-5 Power Amplifiers 427
10-5.1 Power Amplifiers Using Power Boosters 427
10-5.2 Monolithic Power Ampfifiers 429
10-6 Volt83C- Regulators 435
10-6.1 Positive Voltage Regulator Series with Seven Voltage Options 436
10-6.2 Switching Regulators 439
10-6.3 Voltage References 439
10- 7 Voltage Inverter 440
10-7.1 VI-7660 Applications 441
Summary 444
Questions 445
Problems 445
Experiments: 446
10-1 The 555 Timer as a Monostable and Astable Multivibrator 446
10-2 NE565 Phase-Looked Loop as a Frequency Multiplier 451
xii Contents
11 SELECTED IC' SYSTEM PROJECTS 456

11-2 Power Supply: Application of the Voltage Regulators 457
11-3 Audio Function Generator: Application of the Function
Generator IC 460
11-4 LED Temperature Indicator: Application of the V/F Converter
and the 555 Timer 466
11-5 Digital DC Motor Speed Controi: Application of the D/A
and F/V Converters 475
11-6 Appliance Timer: Application of the 555 Timers 481
11-7 Siren/Alarm: Application of the LM380 487
11-8 Suggested IC Projects 489
APPENDIX A 492
APPENDIX B 494
APPENDIX C ANSWERS TO SELECTED PROBLEMS 496
BIBLIOGRAPHY 499
INDEX 501
Contents xiii
___ .. ,_..
" _.,.... , _
. . .. "...."-'"'''''... .. ,, ,...... _.... __ ..--.. ... ..--,·--- .......
, ,,, -, , __
,_,, , .._,_ .._,.. .., _
Preface
-·---·-------·-· ...- . ..... --·· ·-··--·· -··-----------·- .. ....-.... ,
This book is designed primarily for students taking courses in op-amps and linear
integrated circuits. It may also help designers and hobbyists interested in knowing
more about linear ICs so that these ICs may be used effectively in microcomputer
interfacing. Linear ICs such as op-amps, converters, comparators, and detectors have
become a fundamental part of today's electronic systems. Therefore, basic principles
of operation, electrical specifications, and limitations of these linear ICs are essential
to know. I believe this book is the right blend of theory and practice and presents the
theory in a practical way, which is most needed in industry today.
This book requires a knowledge of amplifier analysis, algebra, and some
trignometry. It presents an in-depth discussion of the internal construction and operat-
ing principles of the op-amp and other important linear ICs such as the 555 timer,
380 audio-power amplifier, 565 phase-locked loop, and 9400 V/F and F/V converter.
Illustrations and timing diagrams used throughout the book will give the student a
concrete idea of the operating principles and internal construction of the ICs. Each
chapter .contains extensive examples that emphasize the main topics. In addition, at
the end of each chapter is a summary of major points, key topic questions, and many
practical problems. Laboratory experiments at the end of most chapters demonstrate
the use and operation of the I Cs discussed.
Thi.s book is full of a variety of practical circuits not discussed elsewhere. For
example, it .unveils the mystery behind versatile devices 'such as op-amps and timers
by analyzing their equivalent circuits using timing diagrams wherever applicable. This
approach is especially helpful. in understanding the electrical characteristics, limita-
tions, and practical uses of !Cs and eliminating the "black magic" surrounding op-
amps and other ICs. In addition, all the circuits discussed, including those in
xv
experiments, have been built and tested to prove the theories behind them. Unlike
other books in the field, this book has a separate chapter devoted to IC systems, in
which a group of discrete ICs is used to form simple but practical systems. Such
exercises are valuable and much needed in industry. These IC system projects will
not only expose the student to practical aspects of system design but also help the
student to gain confidence in building and troubleshooting the various ICs.
To help the reader understand the basic operational amplifier principles and
analysis techniques, the book starts with a review of discrete differential amplifiers.
In this chapter the basic amplifier principles are used in the analysis and design of
direct-coupled amplifiers-differential and cascade. Chapter 1 ais.o provides analysis
and aes1gn of constant current sources and current mirrors: Chapter 2 presents a
complete analysis of equivalent circuits of typical op-amps and their characteristics.
Interpretation of 741 op-amp data sheets and a list of important parameters for ac
and de applications are the content of Chapter 3. Chapter 4 covers the effect of nega-
tive feedback with different feedback configurations. Chapter 5 provides the practical
considerations for an op-amp and looks at different techniques to improve the accu-
racy and performance of op-amp circuits. Frequency response and frequency-depen-
dent parameters of the op-amp are discussed in Chapter 6.
General op-amp applications are covered in Chapter 7, while Chapter 8 presents
filter and oscillator applications using op-amps. Additional op-amp applications such
as comparators and converters are discussed in Chapter 9. In addition, special func-
tions such as frequency-to-voltage and voltage-to-frequency conversion, digital-to-
analog and analog-to-digital conversion, and comparators using specially designed
ICs are also included in Chapter 9. Chapter IO deals with the analysis and applica-
tions of some of the most commonly used special-purpose I Cs. These I Cs include the
FLT-UT universal filter, 555 timer, 565 phase-locked loop, 380 audio power amplifier;
and the 7800 and 7900 voltage regulator series. Finally, Chapter 11 provides a basic
knowledge of system construction and design using various !Cs discussed previously ..
These practical systems demonstrate the operating principles and the validity of the
I Cs used. In addition, Chapter 11 provides some systems in block diagram form. These
projects should prove practical, interesting, and challenging.
The linear ICs presented in this book represent the best overall choices for each
type. I strongly believe that the practical approach taken here is more beneficial than
pure theory for the majority of students. In short, the entire book is practically
oriented: it proves the theories and reinforces the concepts involved in a practical
way. It should be enjoyable to both students and teachers.
I am grateful to my colleague Maris Roze for his careful review of the manu-
script. Being the author of an English book, he was able to provide many helpful
suggestions.
I am also grateful to Edward Vl,ilson, Vice President of Accreditation Bell and
Howell Schools, for writing a forward. Many thanks to academic deans Duane Gow-
ing and Thomas Colvin at Missouri Institute of Technology for their continued help
and encouragement. I also wish to thank all the academic deans at the other Bell and
Howell schools for their assistance in having the manuscript reviewed. Of course I
must thank my colleagues at M.I.T. as well as the faculty at the other Bell and Howell
schools for reviewing the manuscript, and giving me technical advice.
xvi Preface
But most of all, I want to thank my wife, Pratibha, for her patience and
understanding while I spent many, many hours in the preparation of this book.
Ramakant A. Gayakwad
Missouri Institute of Technology
Kansas City, Missouri
Preface xvii
--~;-----------·-·-,----
Foreword
Electronics engineering technology has undergone profound change over the past few
years, and we can expect that such change will accelerate over the next decade.
· Advances in integrated circuit technology, especially those which led to the develop-
'ment of the microprocessor, have had significant impact on -both industry and
educati'on. · ·
Despite the power of the microprocessor, its capabilities are severely limited
unless it can communicate with the predominantly analog "real world." This require-
ment for an interface between the analog and digital domains has motivated the
semiconductor industry to continue development of linear integrated circuits of ever-
increasing complexity. As more and more functions are integrated onto a single chip,
the emphasis on traditional discrete device analysis must shift toward analysis.of the
more complex integrated devices. It would be a grave error, however, to neglect dis-
crete devices altogether as they not only provide the basis for understanding the linear
'integrated circuit, but are still used extensively in specialized applications, especially
those related to interfacing.
This text is an important contribution to electronics engineering technology
education because it maintains a reasonable balance between discrete and integrated
circuitry. Beyond its balanced approach, however, the text excels in its presentation of
practical, detailed examples and carefully designed and tested laboratory 'experiments.
This text can serve as the basis for a strong f undamental linear electronics
sequence in an electronics engineering technology program; in addition, it can pro-
xix
vide students in related fields as well as people in industry with an excellent source of
relevant material to assist in individual professional development programs.
Edward A. Wilson
Vice President, Accreditation
Bell&: Howell Education Group
xx Foreword
------·----------·---·--· ..···- ..--.-- ,- ·----- _. . , _,, __
, _
1
Diflerential and Cascode Amplifiers
1-1 INTRODUCTION
The first part of this chapter is devoted to an in-depth analysis of differential amplifier
types using r-parameters. The cascaded differential amplifiers are presented in a
stage-by-stage analysis. Detailed numerical examples are included in this analysis.
The results of all types of differential amplifiers are summarized at the end of first
part as a quick and convenient cross-reference. The latter part of the chapter presents
the cascode amplifier analysis.
Since the differential amplifier is the basic building block of operational ampli-
fiers, the discussion of differential amplifiers in this chapter sets the groundwork for
analysis and design procedures for the operational amplifiers. The analysis of differ-
ential amplifiers not only clarifies the operation of the operational amplifier but also
makes the characteristics of the operational amplifier easy to understand. In addition,
the analysis procedure which is developed in this chapter provides a means of checking
operational amplifier parameters such as voltage gain, input and output resistances
which are specified on the manufacturers' data sheets.
1-2 DIFFERENTIALAMPUFIER
Let us reconsider the emitter-biased circuit. Figure 1-1 shows two identical emitter-
biased circuits in that transistor Q1 has the same characteristics as transistor Q1,
Rs, = Rs1, Re, = Re1, and the magnitude of +
Vee is equal to the magnitude of
- VBE· Remember that the supply voltages +
Vee and - VBB are measured with
1
+Vee +Vee
f.lc1 Rc2
C1 c,
81 e,
01 02
E1 e,
REI Ru.
Flpre 1-1 Two identical emitter-

-VEE -VEE biased circuits.
+Vee
Re Re
C1 Vo c,
+
81 82
01 a,
E1 E2
RE
Flpre 1-2 Dual-input, balanced-

-VEE output differential amplifier.
respect to ground. To obtain~ single circuit such as the one in Figure 1-2, we should
reconnect these two circuits as follows:
1. Reconnect + Vcc supply voltages of the two circuits since the voltages are of the
same polarity and amplitude. 'Similarly, reconnect -V.._..supply voltages.
2. Reconnect the emitter E1 of transistor Q1 to the emitter E,. of transistor Q,..
(This reconnection places R_.1 in parallel with R_.2.)
3. Show the input signal 111a1 applied to the base B1 of transistor Q1 and t11ai
applied to the base Bi of transistor Q,..
4. Label the voltage between the collectors C1 and c,.
as 110• (The 110 is the output
voltage.)
2 Differential and Cascode Amplifiers Chap. 1

The circuit of Figure 1-2 depicts these changes and is referred to as a differential
amplifier. Note that in the circuit of Figure 1-2, Re1 = Re2; hence their subscripts are
omitted for simplicity. In addition, the parallel combination of RE1 and RE2 is denoted
by RB.
The differential amplifier of Figure 1-2, as its name implies, amplifies the
difference between two input signals V1n1 and v1n2· (The differential amplifier is also
referred to as a difference amplifier.) The circuit. show in Figure 1-2 is a basic differential
amplifier circuit from which we can derive the remaining three differential amplifier
1
circuit configurations.
1-3 DIFFERENTIAL AMPLIFIER CIRCUIT CONFIGURATIONS
The four differential amplifier configurations are the following:
1. Dual-input, balanced-output differential amplifier

2. Dual-input, unbalanced-output differential ampli!!:_r
3. Single-input, balanced-output differential amplifier
4. Single-input, unbalanced-output differential amplifier
The configurations listed above are defined by the number of input signals used and
the way an output voltage is measured. If we use two input signals, the configuration
is said to be dual input; otherwise, it is a single-input configuration. On the other hand,
if the output voltage is measured between two collectors, it is referred to as a balanced
output, because both collectors are at the same de; potential with respect to ground.
However, if the output is measured at one of the collectors with respect to ground, the
configuration is called an unbalanced output. Before proceeding any further with the
circuit analysis, some general observations on the differential amplifier are in order.
Two matched semiconductors of the same type (BJTs or FETs) are required for
the differential amplifier. All the components in the two emitter-biased circuits, which
constitute a differential amplifier, must be matched in all respects for proper operation.
Furthermore, the magnitude of the supply voltages + Vee and - VBE must be equal.
Fortunately, a variety of matched transistor pairs is readily available for differential
amplifier applications. A multistage amplifier with a desired voltage gain can be
formed using a direct connection between successive stages of differential amplifiers.
The beauty of the direct connection between stages is that it removes the lower cutoff
frequency imposed by the coupling capacitors. Therefore, the differential amplifier is
capable of amplifying de as well as ac input signals. 1.1 instrumentation systems differ-
ential amplifiers are widely used to compare two input signals.
In the analysis to foIJow we use r-parameters instead of h-parameters for a num-
ber of reasons:
1. Because of the nature of r-parameters, ac analysis of differential amplifiers with

r-parameters is simpler, more straightforward, and less cumbersome.
2. Unlike with h-parameters, there is no need to manipulate the r-parameters at
different operating levels (different IE and VeE values) except for the ,, value.
Sec. 1-3 Differential Amplifier Circuit Configurations 3

3. The performance equations obtained are easy to remember since they are not
as complex or as lengthy as h-parameter equations would be.
4. Above all, the results obtained using r-parameters compare favorably with the
actual results.
1-4 DUAL-INPUT, BALANCED-OUTPUT DIFFERENTIAL

AMPLIFIER
The circuit shown in Figure 1-2 is a dual-input, balanced-output differential amplifier.

Notice that the two input signals (dual input), v,ni and v,02, are applied to the bases
B1 and B2 of transistors Q1 and Q2• The output v0 is measured between the two
collectors, C1 and C2, which are at the same de potential. Because of the equal de
potential at the two collectors with respect to ground, the output is referred to as a
balanced output.
1-4.1 DC Analysis
To determine the operating point values Ueo and VeEa) for the differential amplifier
-of Figure 1-2, we need to obtain a de equivalent circuit. The de equivalent circuit can
be.--01;>.tained simply by reducing the input signals Vin I and v1n2 to zero. The de equivalent
circuit thus obtained is shown in Figure 1-3. Note that the internal resistances of the
"·
·· input .signals are denoted by R10 because R,ni = R1a2• Since both emitter-biased
sections of the differential amplifier are symmetrical (matched in all respects), we need
to determine the operating point for only one section. We shall determine the lea and
VeEa values for transistor Qt only. These lea and VeEa values can then be used for
transistor Q2 also.
ApplyingKirchhoff's voltage law to the base-emitter loop of the transistor Q1
(see Figure .1-3):
(1-1)
but
Thus the emitter current through transistor Qt- is determined directly from Equation
(1-1) as follows:
IE= VEE - VBE (1-2)
2RE + R,a/ Pde
where VBE = 0.6 V for silicon transistors
V8E = 0.2 V for germanium transistors. ·
Generally, R10/ Pde« 2RE. Therefore! Equation (1-2) can be rewritten as
I - VEE - VBE (1-3)
E - 2Re
From Equation (I-3) we see that the value of Re sets up the emitter current in transis-
tors Q1 and ·Q2 for a given value of VEE· In other words, by selecting a proper value
of RE, we can obtain
.
a desired
'
value of emitter current for a known value of -VEE.
4 Differentialand CascodeAmplifiers Chap.1

Ic i Re
C1
01
Vee Vee
- E, \ E2 -
.._____ ____, i
I'
R1n
IeL Ie
Figure 1-3 De equivalent circuit of

the dual-input, balanced-output
differential amplifier.
Notice that the emitter current in transistors Q1 and Q2 is independent of collector

resistance Re.
Next we shall determine .the collector-to-emitter voltage VeEQ· The voltage at
the emitter of transistor Q1 is approximately equal to - VBE if we assume the voltage
drop across R, to be negligibly small. Knowing the value of emitter current IE ( = le),
0
we can obtain the voltage at the collector Ve, as follows:

Ve = Vee - Reie
Thus the collector-to-emitter voltage VeE is
VeE = Ve - VE
= (Vee - Rele) - (- VBE)
•
= Vee + VBE - Rele (1-4)
Hence, for both transistors we can determine the operating point values (IeQ and
VeEQ) by using Equations (1-2) and (I-4), respectively. Note that IE = IeQ and
VeE = VeEQ··
Remember that the de analysis equations (1-2) and (1-4) are applicable for all
four differential amplifier configurations as long as we use the same biasing arrange-
ment (as discussed above) for each of them. That is, knowing the de analysis procedure
for one configuration (dual input, balanced output), we do not have to repeat the de
analysis procedure for the remaining three configurations.
1-4.2 AC Analysis
To perform ac analysis to derive the expression for the voltage gain Ad and the input
resistance R, of the differential amplifier shown in Figure 1-2:
1. Set the de voltages + Vee and - VEE at zero.
2. Substitute the small-signal T-equivalent models for the transistors.
Sec. 1-4 Dual-Input, Balanced-Output Differential Amplifier "5

Figure l-4(a) shows the resulting ac equivalent circuit of the dual-input, balanced-
output differential amplifier.
1-4.2(a) Voltage gain. Before we proceed in deriving the expression for

the voltage gain Ad, the following should be noted about the circuit in Figure 1-4(a):
1. /£1 = /£2; therefore, r,1 = ,..,2• For this reason, the ac emitter resistance of
transistor Q1 and Q2 is simply denoted by r,.
2. The voltage across each collector resistor is shown out of phase by 180° with
respect to the input voltages V1n1 and v102• This polarity assignment is in accord-
ance with the common-emitter configuration. As we have seen, the differential
t~:1---C-,~~i.-,~~~~-+~r,~_~-E-,::-2~-_~r.~+~~~~~ic2~~-C2~+-•1
Yc1 ---o--t Mll...------'IIIMl-----c-- t----o--, vc2
+ +
Re
®
(a)
Voltage
----T---+-i
o)
Figure 1-4 Dual-input, balanced-output differential amplifier. (a) Ac equivalent

circuit. (b) Input and output waveforms.
6 Differential and Cascode Amplifiers Chatr.-1

amplifier is basically constructed in a common-emitter configuration using two
identical common-emitter circuits.
3. Note the assigned. polarity of the output voltage v0• This polarity simply indi-
cates that the voltage at collector C2 is assumed to be more positive with respect
to that at collector Ci, even though both of them are negative with respect to
ground.
Writing Kirchhoff's voltage equations for loops I and II in Figure l-4(a) gives us
111111 - R1111ibl - r,i,1 - RE(i,, + i,1) = 0 (1-5)
v,111 - R1112iu - r,i,,. -,R.e(i,1 + i,,.) = 0 (1-6)
Substituting current relations ibl = i,i/ Pac and iu = i,1/ Pac yields
VIAi -
R1111.
,,...--1,1 -
. - R B\l,1
,,,,1 1
,. + l,1. ) = 0·
Pac
V1A2 -
RIA,.'
,,...--1.,. -
't '
r,1,2, - ,. + i d )
R.B\l,1 -:-
0
Pac
Generally, R1111/Pac and R,._2/Pac values are very small; therefore, we shall neglect
them here for simplicity and rearrange equations above as follows:
(1-7)
(Rs)i,1 + (r, + Rs)i,2 = V1111 (1-8)
Equations (1-7) and (1-8) can be solved simultaneously for t.. and;,,. by using Cramer's
ra~: -
t11111 Rs
= V1A2 r, + Rs
r, + Rs
111
Rs
Rs r, + Rs
+ Rs)vi., - Vi.2.Rs
_ (r, (l-9a)
- v, + Rz)2 - (R.)2
Similarly,
r, + Rs V1a1
I.,.= Rs j112
, r, + Rs s
Rs r, + Rs
_ (r, + Rs>vi.2 - (R,?!7.. 1
(l.9b)
- (r, + Rs)2 - (R11)
The output voltage is
= -Rel,,. - (-Rei,,)
= Rci~1 - Rel,,.
= Rc(.i,1 - i,2) since I, ,...., t, (1-10)
Sec. 1-4 Dual-Input, Balanced-OutputDifferentialAmplifier 7

Substituting the current relations i,1 and i,2 in Equation (1-10), we get
V = R
O
c
[(r,v.+ +RE)V1n1
RB)2 -
- (RB)V1n2 _ (r,
(RE)2
+ RE)V1n2
(r,+ RE)2
- (RE)vlnl]
- (RE)2
_ R (r, + RE){V1n1 - V1n2) + (R£)(V1n1 - V1n2)
- c (r. + RE)2 - (RE)2
_ R (r, + 2R£)(V1n1 - V1n2)
- er;+ 2r,RE+ Ri - Ri
= R/r, + 2RE)(V1nt - V1n2)
rsr. + 2R8)
(l-11)
Thus a differential amplifier amplifies the difference between two input signals,
as expected. Figure 1-4(b) shows the input and output waveforms of the dual-input,
balanced-output differential amplifier. By defining v,d = v101 - V;n2 as the difference
in input voltages, we can write the voltage-gain equation of the dual-input, balanced-
output differential amplifier as follows:
(1-12)
Notice that the voltage-gain equation of the differential amplifier is independent of

R8 since RE did not appear in the gain equation (1-12). Another point of interest is
that this equation is identical to the voltage-gain equation of the common-emitter
amplifier. The latter is obvious because the differential amplifier employs a common-
emitter configuration.
1-4.2(b) Differential input resistance. Differential input resistance is
defined as the equivalent resistance that would be measured at either input terminal
with the other terminal grounded. This means that the input resistance R11 seen from
the input signal source Vint is determined with the signal source V1n2 set at zero.
Similarly, the input signal source v1n, is set at zero to determine the input resistance
R11• seen from the input signal source v1n2. Usually, the source resistances Rini and
R1n2 are very small and hence will be ignored in the derivation of input resistances
R11 and R12• In equation form,
_ Vinti
R ,1--,-
lb1 u1,,=0
i,.f Pac .,,,aO

=
Vial I
Substituting the value of t.. from Equation (1-9a), we get
R 11 _ 1 ~cVlal
- + RB tat - (RBXO)
(r,
v, + Rs)2 - (RB)2
_ P.c(r! + 2r,RB)
- '·+RB
_ P.cr,(r, + 2RB) (1-13)
- r, + Rs
8 Differentialand CascodeAmplifiers Chap. 1

Generally, RE~ r,. which implies that v: + 2RE) ......, 2RE and r, + RE -- RE.
Therefore, Equation (1-13) can be rewritten as
R _ Pacr,(2RE)
II - (RE)
= 2ft.cr, (l-14)
Similarly, the input resistance R,2 seen from the input signal source Vu,2 is defined as
R tl -- -.-
VtD21
lb2 ,;,.,•o
VtD2
= i.2/
I
Pac fl•1•0
Substituting the value of i-2 from Equation (l-9b), we obtain
(1-15)
However, r, + 2RE ,...., 2RE, and r, + RE ......, RE if RE~ r.. Therefore, Equation
(1-15) can be rewritten as
R _ p •• r.(2RE)
12 - RE
= 2ft10r, ( 1-16)
1-4.2( c) Output resistance. Output resistance is defined as the equivalent

resistance that would be measured at either output terminal with respect to ground.
Therefore, the output resistance R01 measured between collector C1 and ground is
equal to that of the collector resistor Re (see Figure 1-4). Similarly, the output resis-
tance R02 measured at collector C2 with respect to ground is equal to that of the
collector resistor Re, Thus
(1-17)
The current gain of the differential amplifier is undefined; therefore, the current-
gain equation will not be derived for any of the four differential amplifier configura-
tions. Furthermore, like the common-emitter amplifier, the differential amplifier is
a small-signal amplifier; therefore, it is generally used as a voltage amplifier and not
as a current or power amplifier.
1-4.3 lnflerting and Noninflerting Inputs
In the differential amplifier circuit of Figure 1-2 the input voltage v1 1 is called the
D
noninverting input because a positive voltage v1 I acting alone produces a positive

D
output voltage. This can be seen from voltage-gain Equation (1-11). Similarly, the
positive voltage v1 2 acting alone produces a negative output voltage; hence V1 2
D 0
iscalled the inverting input [see Equation (l-11)]. Consequently, the base terminal B,
Sec. 1-4 Dual-Input, Balanced-Output DifferentialAmplifier 9

to which Vm1 is applied is referred to as the noninverting input terminal, and the base
terminal B2 is called the inverting input terminal.
1-4.4 Common-Mode Rejection Ratio
An important characteristic of the dual-input, balanced-output differential amplifier

is its ability to suppress undesired disturbances .that might be amplified along with
the desired signal. When the matched pair of transistors are used in the differential
amplifier, the unwanted signals, such as 60-Hz noise or hum pickup, would appear as
common to both input bases, and therefore the net output would theoretically be zero.
The practical effectiveness of rejecting the common signal, however, depends on the
degree of matching between the two common-emitter stages forming the differential
amplifier. In other words, more closely equal are the currents in the input transistors
Q1 and .Q2; the better is the common-mode signal rejection (see Figure 1-5). When
the same voltage is applied to both input terminals of a differential amplifier, the
differential amplifier is said to operate in the common-mode configuration.
The ability of a differential amplifier to reject a common-mode signal is expressed
by its common-mode rejection ratio· (CMRR). It is the ratio of differential gain A,
to the common-mode gain Acm· In equation form,
CMRR = A, (1-18)
Acm
The common-mode voltage gain Acm can be determined as follows. Apply a known
voltage Vcm to both input terminals of the differential amplifier as shown·in Figure 1-5,
and measure the resultant output voltage Vocm· Then, using Equation (1-19), calculate
Acm•
_
A cm--- Vocm
(1-19)
Vcm
+Vee
Vo c Yocm
Figure 1-S Differential amplifier in common-mode configuration.

Ideally, we expect Acm to be zero, that is, Vocm = 0 V. In other words, we would like
to have CMRR of a differential amplifier ideally equal to infinity. Thus, in practice,
it is advantageous to use differential amplifier with higher CMRR since this amplifier
·, is better able to reject common-mode signals.
1-S DUAL-INPUT, UNBALANCED-OUTPUT DIFFERENT/AL

AMPUFIER
In this configuration two input signals are used; however, the output is measured at
only one of the two collectors with respect to ground. The output is ref erred to as an
unbalanced output because the collector at which the output voltage is measured is at
some finite de potential with respect to ground. In other words, there is some de
voltage at the output terminal without any input signal applied. Let us assume that
the output is measured at the collector of transistor Q2 with respect to ground (see
Figure 1-6).
+Vee
c, c, .....--------<>
e,
a,
E,
/
I
Figure 1-6 Dual-input, unbalanced-output differential amplifier.
1-1.1 DC Analysis .
The de analysis procedure for the dual-input, unbalanced-output differential amplifier

is identical to that of the dual-input, balanced-output differential amplifier because
both configurations use the same biasing arrangement. Therefore, the emitter current
and emitter-to-collector voltage for the dual-input, unbalanced-output differential
amplifier is determined from Equations (1-2) and (1-4), respectively. These equations
are repeated here for convenience:
I • -l - v•• - v..
-. CQ - 2R_.+ R.,J/J,c
Ve• = Vc.ao = Vee + v.. - Rcleo
Sec. 1-5 Dual-Input, Unbaianced-OutputDifferentialAmplifier ,,

1-5.2 AC Analysis
Figure 1-7(a) shows the ac equivalent circuit of the dual-input, unbalanced-output

differential amplifier with small-signal· T-equivalent models substituted for the
transistors.
ic, ic2
c,
- -
-
r.
+ r• - E1 • E2
+
--- i., i.2
ib, t- B, 82
- t ib2
+ +
Re
+
®
(al
Voltage
Yc2 = Yo
v
,- ./ c1
I '~
I \
I \
I I
----T----
(bl
Figure 1-7 Dual-input, unbalanced-output differential amplifier. (a) Ac

equivalent circuit. (b) Input and output waveforms, assuming that the de output
voltage is zero.
1-5.2(a) Voltage gain. Writing Kirchhoff's voltage equations for loops I

and II in Figure l-7(a) gives us
V1n1 - R1n,i•1 - r.i,1 - Ril...i., + i.i) = 0
V1.n2 - R1.n2in - r.i,2 - Ril...i., + i.i) = 0
Since these equations are the same as Equations (1-5) and (1-6), the expressions for
t.. and i,2 will be the same as in Equations (1-9a) and (1-9b), respectively. That is,

.,
. '_ (r. + RE)v1.. 1 - (RB)v1..,,
'•t - + RE)2 -
(r, (RB)2
· _ (r, + RE)V1n2 - (RE)V1n1
1•2
- (r2 + RE)2 - (RE)2
Substituting the value of ie2 yields

I
R (r, + RB)v1.. 2. - (RE)vi .. 1
Vo = - e tr. + RB)2 - (RE)2
= Re (RE)V1n1 - (r, + RE)V1 2 n

r,(r, + 2RE)
Generally, RB~ r,; hence,.+ RE - RB and r, + 2RB - 2RE. Therefore,
v = R (RE)v1 .. 1 - (RE)V1112
o e . 2r,RE
= Ref.E(v1 .. 1 - V1 .. 2)
2r,R8
= R2e {Vint - V1112) (1-20)

'·
.A.,= V0 = Re (1-21)
. v,11 2r,
Thus the voltage gain of the dual-input, unbalanced-output differential amplifier is
half the gain of the dual-input, balanced-output differential amplifier [see Equations
(1-12) and (1-21)]. The input and output waveforms of dual-input, unbalanced-output
differential amplifier are shown in Figure 1-6(b). Notice also that in the dual-input,
unbalanced-output differential amplifier the de voltage at the output terminal is the
error voltage in the desired output signal. Therefore, to reduce the undesired de
voltage to zero, this configuration is generally followed by a circuit called a level
translator circuit. (Refer t? Section 1-13 for more information.) ·
1-5.2(b) Differential input resistance. The only difference between the

circuits in Figures 1-2 and 1-6 is in the way output voltage is measured. However, the
input resistance seen from either input source does not depend on the way the output
voltage is measured. Therefore, the input resistance R, seen from either input source
of the circuit of Figure 1-6 should be the same as that of the circuit in Figure 1-2 and
is given by Equation {l-1.4). That is,
R,1 = R,2 = 2P.cr,
1-5.2(c) Output resistance. The output resistance R0 measured at col-
lector C2 with 'respect to ground is equal to the collector resistor Re (see Figure 1-7).
Thus
Sec. 1-5 Dual-Input, Unbalanced-Output Differential Amplifier 13

1-6 SINGLE-INPUT, BALANCED-OUTPUT DIFFERENT/AL
AMPLIFIER
Figure 1-8 shows the single-input, balanced-output differential amplifier. In this figure
the (single) input is applied to the base of transistor Q1, and the output is measured
between the two collectors which are at the same de potential. Therefore, the output
is said to be a balanced output.
+Vee
Re Re
C1 Yo ~
+
81 82
+
01 o,
- E1 E2 +
+
Re
Figun 1-8 Single-input, balanced-

-VEE output differential amplifier.
1-6.1 DC Ana/pis
The de analysis procedure and bias equations for the single-input, balanced-output
differential amplifier are identical to those of the two previous configurations because
the de equivalent circuit for all three configurations is the same. Thus the bias equations
[Equations (1-2) and (1-4)] are
_ _ Vzz - Vaz
IB - 1ea - 2Rz + R1a/ft,e
Ves = _Veso = Vee + Vaz - Rcleo
1-6.2 AC Analysis
The ac equivalent circuit of the single-input, balanced output differential amplifier

with a small-signal T-equivalent models substituted for the transistors is shown in
Figure 1-9(a).
1-6.2(a) Voltage gain. Before we derive the expression for the voltage gain
A,, the following should be noted about the circuit in Figure l-9(a).
1. During the positive half-cycle of the input signal (or when V1a is the positive
voltage), the base-emitter voltage of the transistor Q1 is positive and that of
transistor Q1 is negative, ar ·shown in Figure 1-8. This means that the collector
14 Differential and CascodeAmplifiers Chap. 1

------vo----C2--i=·1
-- - -
ic1 i., E1'E2 i.2 r• ic2
C1 I r.
v.1 1----1--..A.JW.,------~A,--------1-- v
+ ~ + ~
81
- tibl
Ac
+
t ..
0
(a,!
Voltage
----T--...-.
(bl
Figure 1-9 Single-input, balanced-output differential amplifier. (a) Ac equiva-

lent circuit. (b) Input and output waveforms.
current in transistor Q1 increases and that in transistor Q2 decreases from the

operating point value lea· This change in collector currents during the positive
half-cycle of the input signal is indicated in Figure 1-9(a), in which the currents.
of both sources ic1 and ic2 are shown to be in the same direction. In fact, during
the negative half-cycle of the input signal (or when vlA is the negative voltage),
the opposite action takes place; that is, the collector current of transistor Q 1
decreases and that in transistor Q2 increases.
2. The polarity of voltage across each collector resistor is consistent with the
.direction of current sources t.. and ic2• Thatis, the voltage across the collector
resistor of transistor Q2 is positive, and that across the collector resistor of
transistor Q,·is negative with respect to ground [see Figure 1-9(a)].
Sec. 1-6 Single-Input, Balanced-Output Differential Amplifier 15

3. Note the assigned polarity of the output voltage v0• According to this polarity,
the output voltage is equal to the voltage at collector C2 minus the voltage at
collector C1•
Writing Kirchhoff's voltage equations for loops I and II of Figure l-9(a)gives us

Vin - Riaibl - r,i,1 - REiE = 0 (1-22)
(1-23)
Substituting current relations iE = (i,1 - i12), ib1 - i,i/P •• , and iu ,._, i-2/P.0, we get
Ria l,. 1
Vin - -p -
- - (R E)(.111
r,l.i -
. )
l,2 =- 0
ac
Vin - Ria·
-pl,1 - · - r,1,2
r,1.i · -O
-
ac
Generally, the Rini p •• value is very small; therefore, for simplicity we shall neglect it
and rearrange the equations above as follows:
(1-24)
(r,)i,1 + (r,)i,2 = Vin . (1-25)
Equations (1-24) and (1-25) can be solved simultaneously for t.. and i,2 by using
Cramer's rule:
Vin -REI
•
l,i -
- I Vin
, r. + RE
'·
-RE 1-
-
tr.
r,Vin + REVln
+ RE)r, + REr,
r, r,
_ (r, + RE)vln (l-26a)
- r,(r, + 2RE)
Similarly
r,+ RE Vin I
I
i,2 =
I
'·
r.-+ RE
r, .
--=..RE
r,
1-
Vin. . _ (,. + RE)v1.. - (r.)Vin
(r, + RE)r, + REr,
_ (RE)Vin (l-26b)
- rsr. + 2RE)
= Rci,2 - (-Rcic1)
= Rc(i.'JJ + i. 1)
(1-27)
Substituting the current relations t.. and i12 in Equation (1-27), we get
V0 -- R [
- c r,(r,
(RE)V1n
+ 2RE)
+ (r, + RE)vlD.
r,(r, + 2RE)
J
_ R (r, +
2RE)v111
- c r.(r, +
2RE)
Re
=-Via
,, (1-28)
(1-29)
Notice that the voltage gain of the single-input, balanced-output differential amplifier
is equal to that of the dual-input, balanced-output differential amplifier [see Equations
(1-12) and (1-29)]. The input and output waveforms of the single-input, balanced-
output differential amplifier are shown in Figure l-9(b).
1-6.2(b) Differential input resistance. The input resistance R, seen

from the input signal source is determined as follows:
R, = ~In = ~ = P~cVta
zbl z,d P.c z.i
Substituting the value of i11 from Equation (l-26a), we get
R, = P.cvla = P.cr~(r, + 2RE)
(r, + RE)V1n r, + RE
r,(r, + 2RE) (1-30)
= 2p.c,, ir RE~,,
1-6.2(c) Output resistance. Recall that the output resistance R0 is the

equivalent resistance that would be measured at either output terminal with respect
to ground. Therefore, the output resistance R01 measured at the collector C1 and the
output resistance R02 measured at the collector C2 is given by Equation (1-17):
1-7 SINGLE-INPUT, UNBALANCED-OUTPUT DIFFERENTIAL

AMPLIFIER
This differential amplifier configuration is not commonly used, for several reasons:
1. Although identical to the common-emitter amplifier, it not only requires more

components but also yields less voltage .. gain than the former one.
2. There exists a de output voltage without any input signal applied.
Nevertheless, we shall include the analysis and derivations of the performance

equations in order to make the differential amplifier discussion complete. In this
configuration an input signal can be applied to the base of either transistor and the
output can be measured at either collector. In Figure 1-10 the input is applied to the
base of transistor Q 1, and the output is measured at the collector of transistor Q2•
Sec. 1-7 Single-Input, Unbalanced-OutputDifferential Amplifier 17

+Vee
Re Re
Ve2
C1 ~
+
81 82
01 02 Vo
+
- E1 E2 + -1
+
Figure 1-10 Single-input, unbalanced-output differential amplifier.
1-7.1 DC Analysis
The de equivalent circuit for this configuration is identical to that of the dual-input,
balanced-output configuration shown in Figure 1-3. Therefore, the lea and VcEQ
equations obtained from Figure 1-3 are applicable to this configuration also. These
equations are repeated here for convenience:
I - L - VEE - VBB
B - eQ - 2RE + Rio/Pde
VeB = VcBQ =Vee+ VBB - Ralca
1-7.2 AC Analysis
The ac equivalent circuit of single-input, unbalanced-output differential amplifier is

shown in Figure 1-ll(a).
1-7.2(a) Voltage gain. The equivalent circuit shown in Figure 1-1 l(a) is
identical to that shown in Figure 1-9(a), except in the way in which the output voltage
is measured. Therefore, the current relations (1-26a) and (l-26b) derived for the
circuit of Figure 1-9(a) are also valid for the circuit shown in Figure 1-1 l(a). The out-
put voltage is
since i, ~ i,
Substituting the i.2 value from Equation (1-26b) yields
v0 - Re (RE)vl,,
- rsr. + 2RB)

icl
c, + r, -
ic2
-
E1, E2
..... + r• -
- ..... C2
i,1 i.2
B, 82
! ib2
+ +
Re Re Re Vo
+ @
,. !
•e
0
(al
Voltage
-----T--...-
(bl
Flpre 1-11 Sing)~input, unbalanced-output differential amplifier. (a) Ac

equivalent circuit. (b) Input and output waveforms, assuming that the de output
voltage is zero.
if s»> r.
(1-31)
(1-32)
The input and output waveforms of a single-input, unbalanced-output differential

amplifier are shown in Figure 1-1 l(b).
1-7.2(b) Differential input resistance. The input resistance R, of this

con.figuration is identical to that of the previous one. That is,
Sec.1-7 Single-Input. Unbalanced-Output Differential Amplifier 19

TABLE 1-1 PROPERTIES OF THE DIFFERENTIAL AMPLIFIER CIRCUIT CONFIGURATIONS
Input Output
C'onliguration Circuit Voltage gain resistance resistance
I. Dual input, Rn =· 2fJ,crc Roi = Re

balanced output R12 = 2(J><r• R02 = Re
2. Dual input, Ru = 2fl,cr•

unbalanced output R12 = 2fJ,c r.
3. Single input,
balanced output R; = 2fJ,crc
+Vee
4. Sin&le input,
unbalanced output
20
1-7.2(c) Output resistance. The output resistance R0 measured at col-
lector C,. with respect to ground is equal to the collector resistor Re (see Figure 1-10).
Thus
Ro=Rc
Properties of all the four types of differential amplifiers discussed above are sum-
marized in Table 1-1.
1-8 FET DIFFERE1'TIALAMPLIFIERS

In the differential amplifier configurations just discussed we have us.eci"BJTs. But if
we require very high input resistance, we can use FETs instead. Fortunately, the
voltage-gain equations derived for these configurations using BJT~ can also be used
for configurations using FETs, except fo,r the following replacements:
Re--+ RD
I
'· --+ s;
For instance, the voltage gain of the JF'.ET dual-input, balanced-output differential
amplifier obtained from Equation {l-12) is
.A.,
v
= v,., R
.....!. = --1L_ = g,,.RD (1-33)
. 1/g,,.
1-9 DIFFERENTIALAMPUFIER WITH.SWAMPING RESISTORS
By using external resistors R's in series with each emitter. the dependence of voltage
gain of the differential amplifiers on variations in r, can be reduced. Using KB also
increases the linearity range of the.differential amplifiers. Figure 1-12 shows the dual-
input, balanced-output differential amplifier with emitter resistors R's. Generally, the
value of R's is large enough to swamp the effect of, •. For this reason R's is sometimes
referred to as a swamping resistor.
The emitter current in each transistor can be determined by writing Kirchhoff's
voltage equation around the base-emitter loop of transistor Q 1 with v,e 1 = vlD2 = O V:
-R,nlB - VBB - KE/E - RE(2/E) + Vu= 0
(Note that-we have omitted the subscripts because of symmetry between two halves
of the differential amplifier.) ·
Substituting Ia::::: IB//J4c and simplifying, we get
(1-34)
Remember that the emitter current Equation (1-34) is also valid for the three remaining
differential amplifier configurations with emitter resistor R~. The voltage between
collector and emitter [Equation (1-4)] remains unchanged and will be repeated here
Sec. 1 -9 Differential Amplifier with Swamping Resistors 21

+Vee
Re Re
c, Yo c;
+
e, e,
a, a,
E, E2
R'E R'E
Figure 1-12 Dual-input, balanced-

output differential amplifier with
-Vee emitter resistors R's.
for convenience:
Ves = Vcc + Va.e - Rele
When external resistors J(E are added to each emitter lead, the new voltage gain
and new input resistance can be obtained for any configuration simply by replacing
r, by tr, + J(E). For instance, the voltage gain of the dual-input, balanced-output
differential amplifier of Figure 1-12 becomes
A.,= Vo= Re (1-35)
v,., r, + R~
and the new input resistance becomes
R11 = R,2 = 2ft.c(r, + J(E) (1-36)
Keep in mind that the output resistance with or without R~ is the same [see Equation
(1-17)]. That is,
Roi= Roi= Re
Thus the use of J(E reduces the voltage gain but increases the input resistance,
as can be seen from Equations (1-35) and (1-36), respectively.
Example 1-1
The foilowing specifications are given for the dual-input, balanced-output differential
amplifier of Figure 1-2: Re= 2.tk.O, RE= 4.7 k.O, R1a1 = R1a2 = 500, +Yee=
10 V, - YEE = -10 V, and the transistor is the CA3086 with /J4,: = Pac
= 100 and
YsE = 0.715 V typical.
(a) Determine the lea and Yeza values.
(b) Determine the voltage gain.
(c) Determine the input and output resistances.
22 Differential end CescodeAmplifiers Chap. 1

Solution
(a)· To determine lea and Ve.aa values, we have to substitute the known values in Equa-
tions (1-2) and (1-4) as follows: ·
Vu - Vu 10 - 0.715
+
lea = I.a = 2R.a RIA/Pde = 9.4 Idl + 50/100 = 0·988 mA
Vesa =Vee+ v.'1 - Relea
= 10 + 0.715 - (2.2 Idl)(0.988 mA)
= 8.54 V
(b) The ac emitter resistance
25mV 25mV
r. = I.a niA = 0.988 mA = 25•3 O
Therefore; substituting the known values in voltage-gain equation (1-12), we obtain
A. t'o. Re 2.2k0 8696
" = ""' = 7; = 25.3 = '
(c) The input resistance seen fromeach input source is given by Equation (1-14):
Rn = R,2 = 2/J.er. = (2)(100)(25.3) = 5.06 kO
The output resistance seen looking back into the circuit from each of the two output
terminals is given by Equation (1-17):
R01 = R 2 = 2.2 Idl
0
Example 1-2
Repeat Example 1-1 for the (a) dual-input, unbalanced-output and (b) single-input,
balanced-output differential amplifiers. ·
Solution
(a) Since the component values remain unchanged and the biasing arrangement is
same, the lea and VeBa values as well as input and output resistance. values for the
dual-input, unbalanced-output configuration must be the same as those for the dual-
input, balanced-output configuration (see Table 1-1). Thus
lea = 0.988 mA
VeBa = 8.54 V
Rn = R,2 = 5.06 Idl
R0 = 2.2Idl
However, the voltage gain of the dual-input, unbalanced-output differential amplifier
using Equation (1-21) is
Re 2.2 kO
A ' = 2r. = (2)(25.3) = 43 .4 8
(b) Because the same biasing arrangement and same component values are used in
both configurations, the results obtained in Example 1-1 for the dual-input, balanced-
output configuration are also valid for the single-input, balanced-output configuration.
That is,
lea = 0.988 mA
Ve.aa = 8.54 V
Sec.1-9 Differential Amplifier with Swamping Resistors 23

A,= 86.96
R, = S.06k.Q
R01 = R = 2.2 Jdl
0,.
Example 1-3
For the dual-input, balanced-output differential amplifier of Example 1-1:
(a) Determine the output voltage (v0) if v141 = 50 mV peak to peak (pp) at 1 kHz
and 1'1112 = 20 mV pp at 1 kHz.
(b) What is the maximum peak-to-peak output voltage without clipping?
Solution
(a) In Example 1-1 we have determined the voltage gain of the dual-input, balanced-
output differential amplifier. Substituting this voltage gain (A, = 86.96) and given
values of input voltages in Equation (1-11), we get
R
'Vo = -2.
r.
(111111 - t1142) = 86.96(50 mV - 20 mV)
= 2.61 V pp
(b) Note that in Figure 1-2 the output voltage 110 is measured across the collectors.
Therefore, to calculate the maximum peak-to-peak output voltage, we need to deter-
mine the voltage drop across each collector resistor:
VRc = Rclc
Substituting le = lea = 0.988 mA (see Example 1-1), we get
VRc = (2.2 k.Q)(0.988 mA) = 2.17 V < VcE = 8.54 V (see Example 1-1)
This means that the maximum change in voltage across each collector resistor is
±2.17 (ideally) or 4.34 V pp. In other words, the maximum peak-to-peak output
voltage without clipping is (2)(4.34) = 8.68 V pp.
Remember that the maximum peak-to-peak output voltage without clipping
would have been 4.34 V pp if the same circuit was used as the dual-input, unbalanced-
output differential amplifier.
Example 1-4
Repeat Example 1-1 if 100-0 resistors R'E are placed externally in series with each
emitter (see Figure 1-12). '
Solution
(a) Substituting in Equations (1-34) and (1-4), we can determine the values of lea and
VcEQ, respectively:
Lco- _ VEE - VBB
p
10 - 0.715
2RE +
R'.E R111/ de + 9400 100 50/100 + +
VcEQ
=0.977mA
= Vee + VBE
,
- Rclco
= 10 + 0.715 - (2.2 kQ)(0.977 mA)
= 8.57 V
(b) The ac emitter resistance
25 mV 25
r. = /z mA = 0.977 = 2S.S9 !l

Therefore, substituting in Equation (1-35), the voltage gain is
_ Re_ _ 2.2 kQ _
A 11 - R' E ..:-. r, - 100 T· ?, 59 - 17. 5,-
-J,
(c) The input resistance is given by Equation (l-36):

R11 = Rn. = 2ft.c(R'E+ r,)
= (2)(100)(100 + 25.59)
= 25.12 kQ
The output resistance is indepegdent of R'E values and therefore is the same as in
Example 1-1. That is,
R01 = R02 = 2.2 kQ
Comparing the voltage gain and the input resistance values obtained in Examples 1-1
and 1-4, we can verify that the use of R'E reduces the voltage gain but increases· the
input resistance significantly.
1-10 CONSTANT CURRENT BIAS
In the differential amplifiers discussed so far the combination of RE and VEE is used
to set up the de emitter current. We can also use constant current bias to set up the
de emitter current if desired. In fact, the constant current bias is better because it
provides ·current stabilization and, in turn, assures a stable operating point for the
differential amplifier. Figure 1-13 shows the dual-input, balanced-output differential
amplifier using a resistive constant current bias. Notice that the resistor RE is replaced
by a constant current transistor ( Q3) circuit. The de collector current in transistor Q3
is established by resistors, R1, R2, and RE and can be determined as follows. Applying
the voltage-divider rule, the voltage at the base of transistor Q3 (neglecting base
loading effect) is
V _ -R2VEE
B3 - R1 + R2
V E3 = V BJ - V BE3 _ R2VEE
- - R1 + R2 - BE3
V
Therefore,
] _ l _ V £3 - (- VEE)
E3 - C3 - RE
L _ VEE - [R2VEEl(R1 + R2)] - VBE3
CJ - RE
Because the two halves of the differential amplifier are symmetrical, each has
half of the current lc3• That is,
]Et =]El= lc3 = VEE - [R2VEE/\R1 + R2)] - Vu3 (l-37)
2 -RE
The collector current 1c3 in transistor Q3 is fixed and must be invariant because no
signal is injected into either the emitter or. the base of Q3• Thus the transistor Q3 is a
source of constant emitter current for transistors QI and Q2 of the differential amplifier
(see Figure 1-13) .
.Sec. 1-10 ConstantCurrent Bias 25

+Vee
Re. Re
Vo +
o,
i 1.3
R2 Vu
03
+ Ve3
A, +
RE
Figure 1·13 Dual-input, balanced-output differential amplifier usjng constant

current bias.
Recall that in the analysis of the differential amplifier circuits with emitter bias,
we required that RB~, •. Besides supplying constant emitter current, the constant
current bias also provides a very high source resistance since the ac equivalent of the
de current source is ideally an open circuit. Therefore, all the performance equations
obtained for the differential amplifier configurations using emitter bias are also
applicable to differential amplifiers with constant current bias. For instance, the
voltage-gain equation (1-12) is valid for the differential amplifier of Figure 1-2 as well
as for that in Figure 1:.13 with constant current bias.
To improve the thermal stability of the constant current transistor Q3,, resistor
1(1 is replaced by diodes !)1 and D2, as shown in Figure 1-14(a). The base· of Q3 is
biased with the voltage divider containing components R2, Du and D2• Diodes D1
and D2 help to hold the emitter current /£3 constant even though the temperature
changes. Note that /2 flows to the node at the base of Q3 and then divides into paths
ID and /83• If the temperature of Q3 increases, its base-emitter voltage VsB3 decreases.
In silicon units, VBE decreases 2 mV/°C, and in germanium units, Vi,E decreases
1.6 m V/°C. This reduced VBE3 tends to raise the voltage drop across RB and, in turn,
current /B3• However, the voltage drops across D1 and D2 also decrease, causing a
greater portion of /2 to contribute to ID, that is, causing ID to increase. This causes
ls3 to decrease, which prevents any significant increase in /£3,
For better performance, a transistor array such as CA3086 may be used in
Figure I-I 4(a) as a .constant current bias. Here an isolated transistor is used, and

To the junction of
01 and ~ emltten
+
-
12
Rz -
V13
+
-
o,
113
+
v,n -
o,
VE3
02
+
Re i IE3
(al
•substrate
8 11 14
CA3086
7 6 5
(bl
To the junction of
o, and 02 emittel'1
+
- -
12
R2
V13
113,
+
v,E3 -
03
Ve3
Vz
lzi: +
Re i le3
Figure 1·14 (a) Constant current bias

with diode compensation for variations
in Y.u, (b) Functional diagram of
CA3086. (c) Constant current bias
(cl using zener.
27
needed diodes are formed by using transistors connected for diode operation,
although discrete diodes will work as well. The functional diagram of the CA3086 is
shown in Figure 1-14(b ).
The· emitter current JE3 in Figure 1-14(a} is determined as follows. Assuming
that the voltage drop across the diodes is equal and denoting it by VD, the voltage
at the base of transistor Q 3 is
VB]= -VEE+ 2VD
VE3 = VB] - VBE3 = -V.EE + 2VD - VBE3
I.El _
-
VEl - (-Vu)_
-
2Vo - VBEl
RB RB
Assuming that the transistor Q3 has the same characteristics as diodes D1 and D2,
that is, if VD = V8E3, then ·
IB3 = VD (1-38)
RE
Thus for a given value of RE the emitter current /E3 depends on the voltage
drop across the diodes. But the voltage drop across the diodes is a function of the
current (ID) through them (according to the diode characteristic curve). However,
current ID is a part of current /2, which is determined by the value of R2• Obviously,
the smaller the value of R2, the larger is the drop across the diodes and, in turn, the
greater is the emitter current /E3 for a given value of RE. This means that we can
· change the value of /E3 by varying either the R2 value or the RE value [see Equation
(1-38)].
To design the constant current bias circuit of Figure l-14(a), we will use the
~~~~: .
1. Choose a desired I El value.

2. Assuming that V0 = 0.7 V, determine the value of RB using Equation (1-38).
3. Assuming that /2 = IE3 and VD1 = VD2 = 0.7 V, determine the value of R2
from the following relation:
R _ VEE - 1.4 (1-39)
2 - IE3
Very often a zener diode is used in place of the diodes as shown in Figure 1-14(c).
zeners are available over a wide range of voltages and can have matching temperature
coefficient of voltage to those of transistors.
Referring to the circuit of Figure l-14(c), the voltage at the base· of transistor
Q3~ I
Va3 =-VEE+ Vz
I
Then the voltage at the emitter is
VE3 =-VEE+ Vz - VBEl
Therefore, the current /E3 is

Substituting and simplifying, we obtain
I E3 _
-
Vz - VBEl
(1-40)
RE
The value of R2 should be selected so that /2 ~ 1.2/z,, where lz, is the minimum current
required to cause the zener diode to conduct in the reverse region, that is, to block the
rated voltage Vz. The value of lz, is specified on the data sheets of a zener diode.
Thus the value of R2 can be calculated using the equation
R _ VEE- Vz (1~41)
2 T 12
where /2 ~ 1.2lz,. The conclusion is quite simple: The zener diode is useful for
maintaining a constant base voltage and in tum the constant emitter current in a
constant current bias circuit.
1-11 CURRENT MIRROR
The circuit in which the output current is forced to equal the input current is said to
be· a current mirror circuit. Thus in a current mirror circuit the output current is a
mirror image of the input current. The block diagram and the schematic circuit of the
current mirror is shown in Figure 1-15(a) and (b), respectively. Once the current /2
is set up, the current lc3 is automatically established to be nearly equal to /2• The
current mirror is a special case of constant current bias and therefore can be used to
set up constant emitter currents in differential amplifier stages. Note that the current
mirror circuit requires fewer components than constant current bias circuits. Because
To the junction of
01 and 02 emitters
Ve3
Isourc:1 Current
mirror
l,lnk
+ - f- -
12
-
193
+
i 03
Ie3 12
i
E!!
R2
Ie4
IM Vee3 -
l ,ou,.,. = I sink 04
+
(a) -Vee4
(bl
Figure1-15 (a) Block diagram of current mirror. (b) Current mirror circuit.
Sec. 1-11 Current Mirror 29

of its simplicity and ease of fabrication, the current mirror circuit is most commonly
used in integrated amplifiers such as differential and operational amplifiers.
Remember that for the proper operation of the circuit it is necessary to construct
a current mirror using a transistor array such as the CA3086 in which a needed diode
is formed by using an adjacent transistor [see Figure 1-15(b)]. When used this way, the
transistor array helps to acbi~ve the required collector current thermal stability in a
current mirror circuit.
Since Q3 and Q, are identical transistors, their base-emitter voltages must be
the same, and their base and collector currents must also be approximately equal:
v••, = v.z,
le,= le,
ls3 = 1.,
Summing currents at node v.,, we obtain
/2 =le,+ I
= le, + 21s,= le3 + 21s3 (1-42)
=le,+ 2(}~)
= le,(l + l)
Generally, pdt; is large enough so that 2/ Pde is negligibly small. For instance, pdt; =
100 for the CA3086. Thus the collector current of Q3 is nearly equal to the current /2•
(1-43)
The current /2 is obtained by writing the Kirchhoff's voltage equation for the
base-emitter loop of the transistor Q3:
-R,.12 - Vu3 + VEE= 0
Rearranging, we get
[ _ VEE - VBE3
2 - R2 (l-44)
Thus, using Equation (I-42J, an appropriate value of R2 can be chosen to set a·

desired value of collector current in a current mirror circuit. Remember that for
satisfactory operation of the circuit, two identical transistors are necessary. .
Example i-s
The following specifications are given for the JFET differential amplifier shown in
Figure 1-16: R0 = 3.9 kfl, Ra= l1M!l, RB= 1.5 kfl, R2 = 82 !l, RID.1 = R1n2 =
50Q, V.vo = +lOV, and -VEE= -IOV. Assume that Q1 and Q2 are matched
JFETs with g,,. = 8000 µmhos, Q3 is a BJT with VsE = 0.6 V and = Pac Pde
= 100,
and D1 is the 1N3826 zener with Vz = 5.1 V and /z, = 49 mA. Determine:
(a). The emitter current in transistor Q3•
(b) The voltage gain of the differential amplifier.
(c) The input resistance of the differential amplifier.

Ro Ro
Va
+
01 02
AG RG
D1
Figure 1-16 · JFET differential amplifier with zener constant" current bias.
Solution
(a) Using Equation (1-40), we can determine the value of emitter current in transistor
Q3.
_ Vz - VBE3 _ 5.1 - 0.6 _ A
I El - RE - 1.5 kn - 3 m
(b) The voltage gain of the JFET dual-input, balanced-output differential amplifier is
given by
Ad = gmRD = (8000 µmhos)(3.9 kn) = 31.2
(c) The input resistance seen from either input source is equal to the gate resistance
R0• That is,
R11 = R,2 = 1 Mn
Example 1-6
Design a dual-input, balanced-output differential amplifier with a constant current
bias (using diodes) to satisfy the following requirements:
Differential voltage gain Ad = 40 ± 10
Current supplied by the constant current bias circuit = 4 mA
Supply voltages Vs= ±10 V
Solution. First, we design a constant current bias circuit following the steps outlined
in Section 1-10.

1. The desired value of emitter current I1n = 4 mA (see Figure 1-17}.
2. We assume that the diodes Di and D2 are identical and that VDi = VD2 =
0.7 V. Rearranging Equation (1-38), we get
RB= VD
IB3
Substituting yields
RE = 0·7
4mA
V = 175 n (use 150 0)
3. The value of R2 can be calculated using Equation (1-39):
R2 = VEE]: 1.4 =
1~
;l.4 = 2.15 kn (use 2 kfi)
Next, we determine the value of the collector resistor Re using Equation (1-12).
Since JE3 = 4 rnA,
25rnV
IB1 = IE2 = 2rnA and r, = 2 rnA = 12.5 n
Therefore, to obtain the differential gain of 40, the required value of the collector resis-
tor is
Re = (A4)r. [from Equation (1-12))
= (40)(12.5) = 500 n (use 560 0)
Figure 1-17 shows the dual-input, balanced-output differential amplifier with compo-
nent values. Note that for proper operation of the amplifier circuit the use of a
transistor array such as CA3086 is recommended.
+10V
Ac soon
Non inverting - +
input
Inverting
input
-10 V
Figure 1-17 Differential amplifier of Example 1-6.

Example 1-7
Design the single-input, balanced-output differential amplifier shown in Figure 1-18(a)
to meet the following specifications:
Input resistance R, > 600 k.O

Peak-to-peak output voltage swing ::::;; 5 V
Supply voltages Vs = ± 10 V
Solution. The circuit shown in Figure 1-18(a) requires two Darlington transistor pairs.
We will choose the CA3018 or SK3542 silicon transistor array, which consist of a Dar-
lington-connected transistor pair and two isolated transistors, as shown in Figure
1-18(b). The isolated transistors can be used to form the current mirror circuit. Remem-
ber that we need two transistor arrays. The following specifications apply for each
transistor in the CA3018 transistor array: hPE = 100, h1, = 110, and Vse = 0.715 V.
The desired input resistance for the single-input, balanced-output configuration is
600 k.O. Therefore, using Equation (1-30), for the Darlington pair
R,, = 2P c-r(2r,3)
1
where PacT = total current gain of the Darlington pair

= (110)(110) = 12.1 k
2r,3 = ac emmiter resistance of the Darlington pair Q3Q4 = Q5Q6
Substituting yields
600 k.O = (2)(12.1 k)(2r,3)
Therefore, the ac emitter resistance of transistor Q3 ( = Q5) is
600k!l
r,3 = 48.2 k = 12.4 n
But
25mV
7•3
= 1£3 mA
Therefore,
2SmV
Je3 = 1'2.4Il" = 2.02 mA
Let us choose Je3 = Iss = 2 mA. This means that the current mirror circuit must
supply 2/£3 = 4 mA. To form the current mirror circuit we can use two isolated
transistors in the CA3018, and the value of R2 needed can be calculated by using
Equation (1-44):
Substituting, we obtain
10 - 0.715
R2 = 4 mA = 2.32 k.O (use 2.2 k.O)
Assume that the voltage drop across collector resistor Re determines the peak-to-peak
output voltage swing. The expected output voltage swing in the circuit of Figure 1-18(a)
is 5 V pp. Since the output is "differential," the voltage drop across each collector
resistor is 2.5 V pp or ±1.25 V. In other words, Rele = 1.25 V. Substituting, le=
2 mA we get
Re= 625 n (use 620 !l)

+10 V
Re Re
Vo
+
Non inverting
input
03 05
Inverting
input
R2
t 2leJ
01
02
-10 V
(a)
12
-----'--0
s-----~ 3
7 4
Case and substrate

(b)·
Figure 1-18 (a) Darlington-pair differential amplifier of Example 1-7.

(b) CA3018 transistor array (metal can).
34
Thus for the single-input, balanced-output differential amplifier of Figure 1-18(a),
we need the following components: ,
Two transistor arrays: CA3018
Re= 620!2
R2 = 2.2 k!l
1-12 CASCADED DIFFERENTIAL A/flfPLIFIER STAGES
Having gone through an analysis of the differential amplifier circuit configurations,

1et us see how differential amplifiers can be cascaded (connected in series). Figure 1-19
shows a typical two-stage differential amplifier. The first stage is a dual-input, bal-
anced-output differential amplifier. The second stage is another differential amplifier
driven by the output of the first differential amplifier. A single-ended (unbalanced)
output is taken from this second stage. Both stages use the emitter biasing technique
(the combination of RB and VBE) to set up the emitter currents in the differential pairs.
In many cases the matching of transistors as well as resistor values is essential
for proper operation of the differential stages. For this reason the use of transistor
arrays such· as CA3086 (or SK3543) is recommended. A transistor array such as
CA3086 provides inherent advantages unique to integrated circuits: electrical and
thermal matching, compactness, and ease of physical handling.
Vee +10 V
I
Re4 1.2 kn
2.2kn Re3 1.2 kn
Rc1 2.2kn Rc:2
Vo
Non inverting
Vol
03 04
l
input R'E R' E
ioo a ioo n
Vld
Inverting
input
Re1 4.7 kn Re2 15kn·
-VEE -10 V
Figure 1-19 Cascaded differential amplifier of Example 1-8.
Sec. 1-12 Cascaded Differential Amplifier Stages

Eumple i-8
For the cascaded differential amplifier shown in Figure 1-19, determine:
(a) The collector current and collector-to-emitter voltage for each transistor.
(b) The overall voltage gain.
(c) The input resistance.
(d) The output resistance.
Assume that the transistor array CA3086 is used (for which hPE = 100 typical, h1• =
100, and Vu = 0.715 V). The pin diagram of the CA3086 is shown in Figure 1-14(b).
Solution
(a) To determine the collector current and collector-to-emitter voltage of transistors
Q1 and Q2, we assume that the inverting and noninverting inputs are grounded. The
collector current Uc,..., IE) in Q1 and Q2 is obtained by substituting the known values
in Equation (1-2):
I VBB - VBE 10 - 0.715 O 988 mA

Bl = 2RBI + R1n/Pdc = 2(4.7 kO) + 0 = •
That is, lc1 = lc2 = 0.988 mA.
We can calculate the voltage between collector and emitter for Q1 and Q2 using
the collector current as follows:
Vc1 = Vee - Rc1lc1 = 10 - (2.2 ill)(0.988 mA) = 7.83 V = Vc2
Since the voltage at the emitter of Q1 and Q2 is -0.715 V,
VcBt = VcE2 = Ve1 - VE1 = 7.83 + 0.715 = 8.545 V
Next, we will determine the collector current in Q3 and Q, by writing the Kirchhoff's
voltage equation for the base-emitter loop of the transistor Q3:
Vee - Rc2lc2 - VsE3 - R'i;IB3 - Rs2(2IE3) + VEE= 0
10 - (2.2 k0)(0.988 mA) - 0.715 - (100)(JE3) - (30 kO)h3 + 10 = 0
10 - 2.17 - 0.715 + 10 - (30.1 kO)ls3 = 0
17.12
/El = 30.1 id} = 0.569 mA = IE,
Hence the voltage at the collector of Q3 and Q, is

Vc3 = Ve,= Vee - Rc3lc3 = 10 - (1.2 k0)(0.569 mA)
= 9.32V
Therefore,
VcE~ = VcE, = Ve3 - VBJ = 9.32 - 7.12 = 2.2 V
Thus, for Q1 and Q2:
lcQ = 0.988 mA
VeBQ = 8.545 V
and for Q3 and Q4:
IeQ = 0.569 mA
VeEQ = 2.2 V
[Note that the output terminal (Ve,) is at 9.32 V and not at zero volts.]
(b) First, we calculate the ac emitter resistance r, of each stage and then its voltage
gain.

25mV 25mV
r.1 = J;;- = 0.988 mA = 25.3 n = r.,_
25mV 25mV
re3 = 7;;- = 0.569 mA = 43.94fi = r••
The first stage is a dual-input, balanced-output differential amplifier; therefore, its

voltage gain is
A,n = Vot = Rei II R11.
vu re1
where I
Rn. = input resistance of the second stage
= 2p•• (r,3 + R'e)
= (200)(143.94) = 28.79 k!l
A dl
_ 2.2 kn 1128.79 k!l _
- 25.3 - 80 . 78
The second stage is a dual-input, unbalanced-output differential amplifier with swamp-

ing resistor J?!E, the voltage gain Of Which is .
Ad2 =~ = Re• = 287.88

1.2 k!l = 4 17
Vot· 2(R'.e + r,4) '
Hence the overall voltage gain is
A,1 = (A"1)(A"2) = (80.78)(4.17) = 336.85
Thus we can obtain a higher voltage gain by cascading differential amplifier stages.
(c) The input resistance of the cascaded differential amplifier is the same as the input
resistance of the first stage, that is,
R, = 2P (r,1)
10 = (200)(25.3) = 5.06 k!l
(d) The output resistance of the cascaded differential amplifier is the same as the
output resistance of the last stage. Hence, using Equation (1-17),
Ro = Re = 1.2 ldl
1-13 LEVEL TRANSLATOR
From the results of the cascaded differential amplifier of Example 1-8, the following
observations can be made:
1. Because of the direct coupling, the de level at the emitters rises from stage to
stage. This increase in de level tends to shift the operating point of the succeeding
stages and, therefore, limits the output voltage swing and may even distort the output
signal. For example, in the circuit of Figure 1-19, the voltage at the emitters of Q1
and Q2 of the first stage is -0.715, whereas that at the emitters of Q3 and Q. of second
stage is ·7.12 V.
If used as a single stage, the voltage at the emitters of Q, and Q4 would have been
-0.715 V. Thus the increase in the emitter voltage of the second stage and in turn the
change in its operating point are due to the cascading of differential amplifier stages.
2. The voltage at the output terminal of the second·stage in Figure 1-19 is well
above ground. This de level is undesirable because it tends to limit the peak-to-peak
Sec. 1-13 Level Translator · 37

output voltage swing without distortion and also contributes to the error in the de
output signal.
Therefore, in Figure 1-19 a final stage should be included to shift the output de
level at the second stage down to about zero volts to ground. Such a stage is referred
to as a level translator or shifter. Thus in the cascaded differential amplifier to shift
the output de level down to zero volts, the final stage must be followed by a level
translator circuit. Although there are a variety of level translator circuits, an emitter
.follower with a voltage divider is the simplest among them [see Figure 1-20(a)]. The
output of the second differential stage of Example 1-8 can work into the voltage-
divider emitter-follower stage of Figure 1-20(a). Thus a positive 9.32 at the output
terminal ( Vc4) of the second stage in Figure 1-19 can produce zero volts at the junction
Input -----f
R,
O V de
Output
R2
-VEE
l
(a)
Input---
O Vdc
/
Output Output
! !
(bl (cl
Figure 1-20 Level translator circuits. (a) Emitter follower with voltage divider.
(b) Emitter follower with constant current bias. (c) Emitter follower with current
mirror.

of R1 and R,. with proper selection of components. Better results are obtained by using
an emitter follower either with a diode constant current bias or a current mirror instead
of the voltage divider, as shown in Figure l-20(b) and (c), respectively. Note that the
resistive or zener constant current bias can also be used with the emitter follower in
forming a level translator.
Example 1-9
Design a level translator circuit as shown in Figure 1-20(b) for the cascaded differential
amplifier of Example 1-8.
Solution. We need to shift 9.32 Vat the collector of Q4 down to zero volts at the col-
lector of Q6 [see Figures 1-19 and 1-20(b)]. Following the design steps listed in Section
1-10, we first design the diode constant current bias circuit and then select an appro-
priate value for R so that the voltage at the collector of Q6 is zero volts. Let us choose
1£6 = 3 mA and Vs= ±10 V. Therefore, using Equation (1-38), the value of RB is
RE = r:: = 3 ~A = 233.3 n (use 270 !l)
Substituting the known values in Equation (1-39) yields
R1 _
-
VEE - 1.4 _ 10 - 1.4 _ 2 87
1£6 - 3 mA - ·
1.n (
=" use 2· 7
'·")
=..:
Assuming that 1'11£, = 0.7 V, the voltage at the emitter of Q, is
VE, = VB, - VBE, = 9.32 - 0.7 = 8.62 V
Since the voltage at the collector Q6 is to be zero and le, = Ic6 = 3 mA, the required
value of R is
R = ~:,' = 38 !~ = 2.87 k!l (use a 3-k!l potentiometer)
Thus the desired level translator circuit components are:

R = 3-k!l potentiometer
RE= 270!2
R,. = 2.7 kn
Di, D1, Q, and Q6 = CA3086
Example 1-10
For the cascaded differential amplifier of Figure 1-21, determine:
(a) The IcQ and VcEQ for each transistor.
(c) The maximum peak-to-peak output voltage swing.
(Assume that the CA3086 transistor array is used for which Pac = Pde = 100 and
VBE = 0.715 V.)
Solution. The circuit in Figure 1-21 consists of three stages:
1. Dual-input, balanced-output differential amplifier

2. Dual-input, unbalanced-output differential amplifier
3. Level translator circuit
All the stages use current mirror biasing. Especially notice the way current mirror
transistors Q4, Q1, and Q9 are connected. The bases of these transistors are tied
Sec. 1-13 Level Translator 39

together to the base of transistor Q3• For this reason the collector currents in these
transistors (Q3, Q.c, Q,, and Q9) are equal and are set up by a 2.2-kO base resistor
(see Figure 1-21).
2.7 k!l
2.1 kn 1.skn
6.84 V
4.3 V
01
+ +
vid
3.69 V
1.6 kU
/=!OV
i 4.22 mA i 4.22 mA
t2mAf
--
4.22 mA
2.2kfl
R2
-Is
+ 04
-
Is
07
- Is
03
Figure 1-21 Cascaded differential amplifier of Example 1-10.
Another interesting point about this circuit is that there is no collector resistor
used for Q, since the output is single-ended and is measured at the collector of tran-
sistor Q6. To determine the de conditions, we assume that the input terminals are
shorted to ground. '·
(a) We can determine the collector currents in current mirror transistors Q.c, Q,, and
Q9 using Equation (1-44):
Substituting gives us
I2 = 10 - 0.715 _ 22 mA
2.2 k!l - 4 .
This means that
,
Ico1 = Icoz = lea, = lcQ6 = 2.11 mA
Ico• = 4.22 mA since /Ea = /e9
Knowing these collector currents, we can calculate the collector-to-emitter voltages as
follows:

Ve, = Ve2 = Vee - Re1le1 = 10 - (2.7 k!l)(2.11 mA) = 4.3 V
Therefore,
VeEQI = VeEQ2 = 4.3 - (-0.715) = 5.015 V
VEs = VE6 = (4.3 - 0.715) = 3.59 V
Ve6 = Vee - Rcelc« = 10 - (1.5 k!l)(2.11 mA) = 6.84 V
Hence
VCEs = 10 - 3.59 = 6.41 V
VeE6 =t 6.84 - 3.59 = 3.25 V
Finally,
VEB = 6.84 - 0.715 :== 6.125 V and Vea= 10 V
Therefore,
VeEB = 10 - 6.125 = 3.875 V
(b) The ac emitter resistances are
25 mV 25 mV
r.1 = r,« = ~ = 2_11 mA = 11.85 !l
25 mV 25 mV
r,« = --y;;- = 4_22 mA = 5.92 !l
and input resistance of the second stage is

R12 = 2ftacr•6 = (200)(11.85) = 2.37 k!l
Therefore, the voltage gain of the first stage is
Adi = Rei II R,.2 = 2.7 k!l 112.37 k!l = 1065
r.1 11.85
The input resistance of the third stage (looking into the base of Q8) is
R13 = P.cCr,a + REa) = (100)(5.92 + 1.5 k!l) = 150.6 k!l
Hence the voltage gain of the second stage is
A42 = Re6 II R,3 = 1.5 k!l II 150.6 k!l = 62 66
2r,6 (2)(11.85) ·
The voltage gain of the third stage is
A43,...., 1
Thus the overall gain of the circuit in Figure 1-21 is
A-., = (A41)(A42)(A43) = (106.5)(62.66)(1) = 6673.3
(c) The third stage in Figure 1-21 is the level translator circuit and in addition, the
voltage gain of this stage is unity. Therefore, the maximum peak-to-peak output voltage
swing is determined by the voltage drop across the collector resistor of transistor Q6•
The voltage drop across collector resistor of Q6 is
Vi.skn = (1.5 k!l)(2.11 mA) = 3.17 V
Hence the maximum peak-to-peak output voltage swing is
v 0 = ±3.17 V or 6.34 V pp
Sec. 1-13 Level Translator 41 .

1-14 CASCODE OR CE-CB CONFIGURATION
Each of the small-signal amplifier configurations :-CE, CB, and CC has some unique
advantages as well as drawbacks. The specific property of the amplifier configuration
can be enhanced, a specific drawback can be removed, or a special feature can be added
by connecting two configurations. Since there are three configurations, we can form
nine possible combinations, each having two configurations. But unfortunately, out
of these nine possible combinations, some do not improve the amplifier's performance
in any way and are, therefore, not practical. The most commonly used combinational
configurations are the following:
1. Common collector-common collector (CC-CC) connection

2. Common collector-common emitter (CC-CE) connection
3. Common collector-common base (CC-CB) connection
4. Common emitter-common emitter (CE-CE) connection
5. Common emitter-common base (CE-CB) connection
The Darlington pair can be used to obtain a CC-CC configuration. The Dar-
lington pair is a composite two-transistor device in which the collectors of two tran-
sistors are tied together and the base of the second transistor is driven by the emitter
of the first. The principal advantages of this configuration are that the input resistance
and the current gain are increased by a factor /3 over those in the standard CC
configuration.
Another example of the CC-CC configuration is the double follower circuit in
which complementary transistors are connected in the CC-CC configuration. The
main features of this circuit are that the output voltage is equal to the input voltage
and that a very high current gain is provided.
To obtain the CC-CE configuration, we can use the Darlington pair in place of a
single transistor in CE configuration. The principal advantage of this configuration is
that its current gain and input resistance is improved by a factor f3 over that of the
CE amplifier. Note that these increases are achieved at the sacrifice of a slight decrease
in voltage gain.
The single-input, unbalanced-output differential amplifier of Figure 1-10
utilizes the CC-CB configuration. This configuration basically has the same input
characteristics as the CC amplifier and the same output characteristics as the CB
amplifier.
If the main objective is to obtain a very large voltage or power gain, we can use
the CE-CE configuration. The complementary pair can also be utilized in forming the
CE-CE configuration. Recall that in forming the dual-input, balanced-output differ-
ential amplifier, we also have to use two symmetrical CE sections (see Figure 1-2).
Thus the CE-CE is the most commonly used configuration.
The CE-CB configuration (usually referred to as the cascade amplifier) is shown
in Figure 1-22. Note that the CE and CB stages are direct-coupled. This configuration,
of course, has basically the same input characteristics as the CE amplifier and the
same output characteristics as the CB amplifier. More specifically, it has high output
resistance and is inherently more stable. The high output resistance attainable is
42 · Differential and Cascode Amplifiers Chap. 1

useful in achieving.large amounts of voltage gain. Also, in this configuration no
high-frequency feedback occurs from the output back to the input, and the input Miller
capacitance effect is at a minimum because the voltage gain of the CE configuration is
very low. Therefore, a· CE-CB configuration is inherently more stable and hence
ideally suited for high-frequency applications.
1-14.1 DC Analysis
In the cascode amplifier of Figure 1-22, R1, R2 and R3 form a bias network for Q1
and Q2; Cs1 and Cs2 provide ac signal ground paths from the Q1 emitter and Q2 base,
respectively; and C, is the coupling capacitor. For the proper operation of the circuit
we require that transistors Q1 and Q2 be identical. Keep in mind that for de conditions
all capacitors are assumed to be open-circuit.
Because of identical transistors and the direct coupling between the CE-CB
stages,
/E1 = IE1. or lei·= lc2 and /B1 = IB1.
This means that we need to determine the emitter current of Q1 only. Applying the
voltage-divider rule, we get
V _ R1Vcc (1-45)
RI - R1 + R1. + R3
VEI = VRI - VBEI
Therefore,
+Vee
Re
R·3 co
~v
0
Cs2J
Ve2 02
(CB)
l
R2
a,
(CE)
C;
Ve,
R,
Re Cs,
Figure 1-22 Cascode amplifier.
Sec. 1-14 Cascode or CE-CB Configuration 43

Substituting yields
(1-46)
Thus once we know the emitter current of Q 1, we can determine all the currents in
and voltages at the three transistor terminals for Q1 and Q2 if desired.
1-14.2 AC Analysis
The small-signal T-equivalent circuit for the cascode amplifier is shown in Figure 1-23.
Since we are considering only the low-frequency performance, we assume all capacitors
as short-circuit elements. We will determine the low-frequency, small-signal properties
of the cascode circuit: the voltage gain, current gain, and input resistance.
e, +
e,
Figure 1-~ Small-signalT-equivalent circuit of cascode amplifier.
Note that in Figure 1-23, RB= R1 IIR2;· r.. - r62 since /£1 - /£2; and Va1 is
the output voltage of the CE stage. Since Q 1 and Q2 are identical transistors, Pdci =
Pdc2 and P,c1 = P,c2; therefore, we will omit subscripts in the calculations that follow.·
1-14.2(a) Voltage gain. For the input circuit in Figure 1-23,
Vin= (,.1)(i.1) since RB~ ,.1
Val -(re2)(i.2)
=
Since ie2 = t.. and t.. - i.i, this implies that i.2 - i.1• Therefore, the voltage gain A.
of the CE stage is
(1-47)
The output voltage
but
and
Therefore, substituting the value of i.1 gives us
Va = -(Re)(- Vai)
'•'l
Then the voltage gain of the CB stage is
Re Vo
-=- '(1-48)
r., Val
Thus the overall voltage gain of the CE-CB configuration is
A = V0 _ V01 ~ = _Re (1-49)

II
Vin
-
Vin Vat r.,
Note that rd = r a.
1-14.2(b) Current gain. The current gain A, of the CE-CB configuration

can be expressed as
but
Therefore,
Applying the current-divider rule to the input circuit, we get

. _ Rsi1n
'bl - xvtz:
Rs + acr<l
where Rs = R1 II R2
Also, t., = P.cib1
Therefore, the current-gain equation becomes
_
A ,- PacRs
(1-50)
Rs+ Pacr.1
1-14.2(c) Input resistance. For the input circuit
Substituting
we have
Solving for the ratio v1n/iiu we get for the input resistance:
R, = Vin = p.cr.1Rs (1-5_1)
i,n Rs + Pacr.1
The cascode amplifier of Figure 1-22 is not encountered very often in discrete
circuitry because of the following drawbacks:
1. The amplifier requires a large number of resistors and capacitors to provide

bias and prevent undesirable feedback.
2. Unlike the integrated circuit (IC) cascode amplifier, it does not offer much
Sec. 1-14 Cascade or CE-CB Configuration 45

flexibility. For instance, the CA3095E is a differential cascode amplifier, which
means that it can be used as a differential as well as a cascode amplifier. Some
IC cascode amplifiers are even available with an automatic gain control (AOC)
arrangement and a provision for thermal stability. Obviously, such amplifiers
are usually a little more complex in structure than the basic circuit shown in
Figure 1-22.
Example 1-11
The following specificationsare given for the cascade amplifier of Figure 1-22.
R1 = 27 k!l Re= 1.8 kO C, = 10 µF
R2 = 39 k!l = 10 µF
RE= 1 k!l C0
R3 = 47 k!l C11 = 100 µF
Vee= 12 Y C,2 = 100 µF
Assume that the 2N3393 transistors are used with P,c = 140, Poe= 125, and Vu=
0.63 Y. Determine:
(a) The de conditions for both transistors.
(c) The overall current gain.
(d) The input resistance.
Solution
(a) Substituting in Equation (1-45), we get
u R1 Vee (21 k!l)(12) y
"JU = R, + R2 + R3 = 27 ffi + 39 ffi + 47 k.{l = 2.87
Therefore,
VB1 = VRI - VBBl = 2.87 - 0.63 = 2.24 Y
VEI _ 2.24 Y _ 24 mA
I El _
- RB - Tid'f - 2 .
Thus,
IB1 = lei = /£2 = lc2 = 2.24 mA
V = V. - R3 Vee = 12 - (47 k!l)(12) = 7 01 y
Bl cc R, + R,. + R3 113 ill .
Hence,
VE2 = Vei = Va2 - VBB2 = 7.01 - 0.63 = 6.38 Y
VeE1 = Vci - VEt = 6.38 - 2.24 = 4.14 Y
Since
Vc2 = Vee - Relc2 = 12 - (1.8 k0)(2.24 mA) = 7.97 Y
then
VcE2 = Ve2 - VB2 = 7.97 - 6.38 = 1.59 Y
(b) The ac emitter resistances of {l1 and Q2 are
25mY
r,1 = r,2 = ~
25mY
= 2_24mA = 11.16n
Substituting in Equation (1-49),we have the overall voltage gain
A,,=-~:=-\~.~= 161.3

(c) RB = R'1 II R,. = 27 k!l 1139 k!l = 15.95 k!l and Pac = 125
Substituting these values in Equation (1-50), we get
A,= P cRB
1 (125)(15.95 k!l)
RJJ + PacRB 15.95 k!l + (125)(11.16 !l) = l1 4 ·9
(d) Input resistance is given by Equation (1-51):
R, = Pacr•;/B = (125)(11.16)(15.95 k!l) = l 28 k!l
RB + acr.1 15.95 k!l + (125)(11.16) · ·
SUMMARY
1. The differential amplifier consists of two symmetrical common emitter sections and is
capable of amplifying the difference between two input signals. The differential amplifier
can amplify ac as well as de input signals because it employs direct coupling.
2. There are four types of differential amplifier configurations:
(a) The dual input, balanced output
(b) The dual input, unbalanced output
(c) The single input, balanced output
(d) The single input, unbalanced output
These configurations are defined according to the number of input signals used and the
way output is measured. When we use two inputs, the configuration is said to be dual
input; otherwise, it is a single input. If the output voltage is measured between two
collectors, the configuration is referred to as a balanced output.On the other hand, if the
output is measured at either collector with. respect to ground, the configuration is said to
be unbalanced output.
3. For proper operation of the differential amplifier, a transistor array and matched com-
ponents must be used. The differential amplifier can be biased by using emitter bias (a
combination of Rz and Vss), constant current bias; or current mirror techniques.
4. In a cascaded differential amplifier, the output of the first stage is used as an input for the
second stage, the output of the second stage is applied as an input to the third stage, and
so on. Because of direct coupling between the stages, the operating point of succeeding
stages changes.
5. Generally, in a cascaded differential amplifier the last dual-input, unbalanced-output
stage, is followed by a level translator. The function of the level translator is to make the
de voltage at the output terminal .zero,
I
6. The cascode amplifier is composed of direct-coupled common-emitter and common-base

configurations. It provides a large amount of voltage gain at higher frequencies.
QUESTIONS
1-1. What is a differential amplifier?

1-2. What are the four differential amplifier configurations? Which one is not commonly
used, and why?
1-3. What does the term "balanced output" mean?
Chap. 1 Questions 47
1-4. What is the main advantage of constant current bias over emitter bias?
1-5. Explain the differences between constant current bias and current mirror.
1-6. What is a level translator circuit? Why is it used with the cascaded differential amplifier?
1-7. What is a cascode amplifier? List the characteristics of the cascode amplifier.
PROBLEMS
1-1. An emitter-biased dual-input, balanced-output differential amplifier has the following

specifications: I Vccl =I-Yul= 10 V, Rei =Rei= 2.7 Hl, and RE= 3.9 k.Q; the
transistor array is CA3086 with Pac Pde =
= 100 and V8s = 0.715 V. Calculate:
(a) The operating current and voltage values for each transistor
(b) The voltage gain
(c) The input resistance of the circuit
1-2. Repeat Problem 1-1 for the dual-input, unbalanced-output differential amplifier.
1-3. Repeat Problem 1-1 with RE = 5.6 kQ.
1-4. Repeat Problem 1-1 with Rei =Rei= 5.6 k.Q.
1-5. Repeat Problem 1-3 for the single-input, balanced-output configuration.
1-6. Repeat Problem 1-4 for the dual-input, unbalanced-output configuration.
1-7. Repeat Problem 1-4 for the single-input, balanced-output configuration.
1-8._ For the dual-input, balanced-output differential amplifier of Problem 1-1:
(a) Draw the output voltage waveform if V111i = 5 mV pp and V111i = 2 mV pp at
1 kHz. Assume that the collector Ci is negative with respect to collector C2 (see
Figure 1-2).
(b) Determine the maximum peak-to-peak output voltage swing without clipping.
1-9. Repeat Problem 1-8 for the dual-input, unbalanced-output configuration.
1-10. Repeat Problem 1-8 if 180-Q resistors R'E are placed externally in series with each emit-
ter (see Figure 1-12).
1-11. Design a zener constant current bias circuit as shown in Figure 1-14(c) according to the
following specifications:
(a) Emitter current ls3 = 5 mA.
(b) 1N3825 Zener diode with Vz = 4.7 V and lz, = 53 mA.
(c) CA3086 transistor with Pac =Pde= 100 and VBE =0.715 V.
(d) Supply voltages V, = ±9 V.
1-12. The JFET dual-input, balanced-output differential amplifier uses the Zener constant
current bias circuit designed in Problem 1-11. Determine the voltage gain and the input
resistance of the amplifier if RD= 3.9 k.Q, Ra= 1 MQ, and g,,. = 4000 µmhos.
1-13. Design the dual-input, balanced-output differential amplifier using diode constant cur-
rent bias to meet the following specifications:
(a) Supply voltages (V,) = ±12 v.,
(b) Emitter current (IE) in each differential amplifier transistor = 1.5 mA.
(c) Voltage gain< 60.
1-14. Design the dual-input, balanced-output differential amplifier with the current mirror
bias according to the following specifications:
(a) Supply voltages (V,) = ±10 V.
(b) Maximum output voltage swing = 4 V pp.
48 Differentialand CascadeAmplifiers Chap.1

1-15. Design the single-input, balanced-output differential amplifier with diode constant
current bias to meet the following specifications:
(a) Voltage gain< 10.
(b) Input resistance R, > 20 k!l.
1-16. For the modified current mirror circuit shown in Figure 1-24, determine the emitter
current in transistor Q3• Assume that the CA3086 transistor array is used. For each
transistor in the array, Pde = Pac = 100 and VBE = 0.715 V.
+10V
Re 2.2 k!l
4.7 k!l
-10 V
Figure 1-24 Modified current mirror circuit of Problem 1-16.
1-17. Referring to the circuit of Figure.1-25, determine:

(a) The current through collector resistor Re,
(b)The collector current in each transistor.
Assume that the CA3086 transistor array is used.
+10 V
Re
1 k!l
5.6k!l
a,
-10V
Figure 1-15 Modified current mirror circuit of Problem 1-17.
. Chap. 1 Problems 49
1-18. For the single-input, balanced-output differential amplifier shown in Figure 1-26,
determine ·
(a) The operating point values (/cg and VcEg).
(b) The voltage gain.
(c) The input resistance.
(d) The maximum peak-to-peak output voltage.
Assume that Pac = Pde = 100, VBB = VDt = 0.715 V, Vz = 6.2 Y, and lz, = 41 mA.
+lOV
Re 4.7 kn 4.7kn Re
03
+
Dl v,E -
02
-lOV
Flpre 1-26 Differential amplifier of Problem 1-18.
1-19. For the cascaded differential ~plifier of Figure 1-27, determine:

(a) The de conditions for each stage.
(c) The maximum peak-to-peak output voltage swing.
Assume that the CA3086 tllansistor array is used.
1-20. Repeat Problem 1-19 for the circuit shown in Figure t-28.
1-21. Repeat Problem 1-19 for the circuit shown in Figure 1-29.
1-24. Repeat Problem 1-19 for the circuit shown in Figure 1-32. Assume that the input
common mode voltage Vc.11 is 3.5 V.
1-25. Repeat Problem 1-19 for the circuit sho~ in Figure 1-33.
1-J.6. Desip the lew:l translator circuit using diode constant current bias for the circuit in
Problem 1-19. Refer to Figure 1-20(b).
Differential and CascodeAmplifiers Chap. 1

+8 V
1.a kn
s.Gkn 1.a kn
~6kn
Vo
03 04
J
+ 180 180
02
4.7 k.{2 3.3kn
-av
Figure 1-27 Cascaded differential amplifier of Problem 1-19.
+10 V
1.8 kn
2.1 kn
2.7 k!}_
10kf2
10 kn
2.2 kn
-10 V
+12 V
3.Skn
5.6kn
3.Skn a..
100
100
+
5.1 kn
2.2kn 5.&kn
-12 V
3.3kn
4.7kn
4.7 kn
a.2 kn
i......~~~~..._~~~~~~~~~~ ..........,..-9V
Figure 1-30 Cascaded differential amplifier of Problem J-22.
3.9kn
6.Bkn
6.Skn
aakn 6Skn
a..
1okn
5.1 kn
5.1 kn
2.1kn
1.2 kn
Flpre 1-31 Cascaded differential amplifier of Problem 1-23.
+12 V
io en 5.6kn 1okn
03
Out;,ut 1 o-- .. ---o Outp,t 2
2kn 2kn
1.un
2.1 kn
Flpre 1-32 Schematic diagram of µA730 differential amplifier.
63
+6 V
1.15 kn 1.15 kn 3kn 3kn
3.2kn
01
4.7 kn
02
z.z en
1.5 kn
-6V
Figure 1-33 Cascaded differential amplifier of Problem 1-2S.
1-27. Design the level translator circuit using zener constant current bias for the circuit in
Problem 1-20. Refer to Figure 1-14(c).
1-28. For the circuit in Problem 1-21, design the level translator circuit using current mirror
bias. Refer to Figure 1-20(c).
1-29. For the cascode amplifier shown in Figure 1-22, determine:
(a) The de conditions for each -transistor.
(c) The overall current gain.
(cl) The input resistance.
Assume that R1 = 12 ill, R,. = 20 ill, R3 = 24 ill, Re = 1.8 ill, Rs = 1 ldl,
C, = C = 10 µF, C.s1 = C.s2 = 100 µF, and Vee = 12 V. The transistors are
0
2N3393 with /Jae= 125 and Vu= 0.63 V.

1-30. Repeat Example 1-11 with Rs = 2.2 ill.
1·31. Repeat Problem 1-29 with Ik'= 1 ill.
EXPERIMENT1-1
DIFFERENTIALAMPUFIER USING (iONSTANT CURRENT BIAS
Objectiva
In this experiment you will design a constant current source and current mirror
networks and use them to bias the differential amplifier. At the end of this experi-
ment you should be able to:

1. Measure and record the de conditions in a differential amplifier using constant
current bias and current mirror bias.
2. Explain the difference between a constant current bias and current mirror bias.
Equipment
1. Dual-trace oscilloscope
2. Audio-frequency generator
3. Low-voltage power supply
4. Multimeter
Materials
1. CA3086 transistor array or equivalent
2. 2.2-Jill resistor
3. 3-kQ potentiometer
4. Two 180-Q matched resistors
5. Two small-signal diodes
6. Assorted components selected by the experimenter according to design
Procedure
1. Design a constant current bias circuit using diodes so that the emitter current in
each differential amplifier· transistor is 1 mA.
2. Measure the 2.2 Jill resistor with ohmmeter and then adjust the 3 kQ potenti-
ometer to this value.
3. Connect the circuit of Figure El-1.l(a) using the constant current bias network
designed in step 1. However, do not turnon the signal generator at this time.
4. Using the voltmeter, measure the de voltages at the emitter and collector of
each transistor. Record these values in Data Table El-1.1. Similarly, measure
the de emitter current in each transistor with the multimeter set to the de current
mode. Enter the measured values in Data Table El-1.1.
DATA TABLE E1-1.1

DC measurements
Vc1 Vc2 VcJ = VE1 = VE2 VE3 lc1 lc2 Ics
Figure
El-1.l(a)
Figure
El-1.l(b)
5. Tum on the signal generator and set it to 1 kHz. Connect the oscilloscope
probes of channels 1 and 2 to the collectors of transistors Q 1 and Q2, respectively.
Exp. 1-1 Differential Amplifier Using Constant Current ·Bias 65

+10V +10V
2.2kn 2.2 kn 2.2kn 2.2kn
0 Vo
0 Vo
+
o 0
0 0
© © ©0 @
01
0
R2
02
RE
R2
© @
@
@
-10V -10V
(al (bl
Figure El-1.1 (a) Differential amplifier using constant current bias. (f>) Differ-
ential amplifier using current mirror bias.
The ground leads of both channels must be connected to the ground point. -Set
thechannel selector switch on thescope to ADD mode and channel 2 polarity
switch on INVERT. Set the volts/cm switches of both channels to the same
value. Adjust the amplitude of the signal applied to the differential amplifier so
that the output waveform is a measurable sine wave. Measure the input and
output voltages and record the measured values in Data Table El-1.2;
DATA TABLE E1-1.2

AC measurements
.
Voltage gain
Input amplitude Output amplitude,
at 1 kHz, t11n1PP tlo pp Measured Calculated
Figure
El-1.l(a)
Figure
El-1.l(b)
Differentialand CascodeAmplifiers Chap. 1

6. Design a current mirror circuit so that the emitter current in each differential
amplifier transistor is 1 mA.
7. Connect the circuit of Figure El-1.1 (b) using the current mirror circuit designed
in step 6. However, do not tum on the signal generator at this time.
\
8. Repeat steps 4 and 5 for the circuit in Figure El-1.l(b).
Questions
1. Describe the difference between a current mirror and constant current bias
networks. '
2. How does the experimental voltage gain compare with the calculated value?
Give reasons if they differ by more than 20 %,
EXPERIMENT 1-2
CASCADED DIFFERENTIAL AMPLIFIER WITH LEVEL
TRANSLATOR
Objectives
In this experiment you will design a level translator circuit and use it to shift a de
output level in cascaded differential amplifier down to approximately zero volts. At
the end of this experiment you should be able to :
I. Measure and record the de conditions in a cascaded differential amplifier.
2. Explain the use of level translator circuit in a cascaded differential amplifier.
3. Explain the purpose of cascading differential amplifier stages.
Equipment
I. Dual-trace oscilloscope
4. Multimeter
Materials
I. Two CA3086 transistor arrays or equivalent
2. Two 2.2-k!l matched resistors
3. i.z-in resistor
4. Two 180 n matched resistors
5. 4.7-n resistor
6. 1N3826 zener diode: Vz = 5.1 V and lz, = 49 mA
'7. z.z-sn resistor
8. 82-n resistor
9. Components selected by the experimenter according to level translator design
Exp. 1 ·2 CascadedDifferential Amplifier with Level Translator 67

Procedure
1. Connect the circuit shown in Figure El-2.l(a) but do not turn on the signal
generator at this time. Measure the voltages at the emitter and collector of each
differential amplifier stage. Record the measured valuse in Data Table El-2.1.
DATA TABLE E1 ·2.1
First differential amplifier stage Second differential amplifier stage
Vet Vc2 VBI = VB2 IBt IB2 Ve3 Ve• VB3 = VB4 IBJ IB4
Similarly, measure the emitter currents in each differentialamplifier stage. Enter

these values in Data Table El-2.1.
2. Tum on the signal generator and connect the scope probe to the collector of
transistor Q4• Set the signal generator frequency at 1 kHz. Adjust the amplitude
of the input signal so that the output is undistorted but measurable sine wave.
You may use the voltage divider arrangement across the signal generator in
order to obtain a very small input amplitude. Measure and record the input and
output voltages in Data Table El-2.2.
DATA TABLE E1-2.2
Voltage
Input Output gain
amplitude, amplitude,
1J1n PP 1Jo PP Measured Calculated
'
3. Design a level translator circuit as shown in Figure El-2.l(b). Connect the input
terminal of the level translator circuit to the collector of transistor Q4 and set
the signal generator to O V. Measure the voltages at the emitter and collector of
each transistor. Record the measured values in Data Table El-2.3. Similarly,
measure the emitter current in each transistor. Enter the measured values in
Data Table El-2.3.
4. Tum on the signal generator and connect the scope probe to the collector of-
transistor Q7• Set the signal generator frequency at' 1 kHz and adjust the ampli-

>o o--4)
>
....
0
® c! ® G ...
0
G
+ a:
0 >
8 0
@T 8
....
8 ·3
.gu
...
G ....
a:
....0(,I
;;;
c
~
u;:,.
.s
>o o---{:>
e..:
u
!E
".c.
c:
~ ~
~ ® ]
c
c: c ~
@ ~
2
.... G 0"'
0 N
C'i
~
:a
13
e ..,
0
c:
0
CID
G
!El
~
z
"O
s
0 s :g
>
....
0
+
e e
>
....I
0
...N
...~•
c
~
N
N
c~ © j
c:
~
e e
M
<"i
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N
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69
DATA TABLE E1·2.3
Vc1 Vci VE1 = Vzi Vc3 Ve, Vz3 VB, Vcs Ve, VB, Ye1
·:1 .
. -
lz1 IE2 ]z3 ]z, Iz; IB, l1n
tude of the input signal so that the output is measurable sinewave. Measure and
record the input and output voltages in Data Table El-2.4.
DATA TABLE E1-2.4
Voltage gain
Input amplitude, Output amplitude,
tl!n pp Vo pp Measured Calculated
Questions
1. How does the experimental voltage gain compare to the calculated value, with
and without level translator circuit? Give reasons if the values differ by more
than 20%.
2. What is the main purpose of cascading differential amplifier stages?
3. Explain the use of level translator circuit in cascaded differential amplifier.·
EXPERIMENT 1-3
CASCODE AMPLIFIER
Objectives
In this experiment you will investigate the de conditions and ac operation of the
,
cascode amplifier. At the end of this experiment you should be able to:
I. Measure and record the de conditions in a cascode amplifier.

2. Measure and record input and output signals using an oscilloscope.
3. Construct a Bode plot of frequency versus voltage gain in dB.
4. Calculate the bandwidth of the amplifier.
60 Differentialand CascadeAmplifiers Chap. 1

Equipment
1. Oscilloscope
4. Multimeter
Materials
1. Two 2N3393 transistors

2. 47-k.O resistor
3. 39-k.O resistor
4. 27-k.O resistor
5. 1.8-k.O resistor
6. 1-k.O resistor
7. Two 10-µF capacitors
8. Two 100-µF capacitors
9. Semilog paper
Procedure
1. Connect the circuit shown in Figure El-3.1. With the signal generator set to
O V, measure the voltages at and currents in both the transistor terminals.
Record these measured values in Data Table El-3.1.
DATA TABLE E1-3.1
VBI Vc1 VE1 VB2

. Vc:z. VE:Z. lei /Bl lcz IB:Z.
2. Now tum on the signal generator, and set it to 50 Hz sine wave. Connect the
scope across the output terminals and set the amplitude of the input sine wave
so that the output waveform is a measurable sine wave. In order to obtain a very
small input amplitude, a voltage-divider arrangement may be used across the
signal generator. Measure the input and output voltages and record these
values in Data Table El-3.2.
3. Change the frequency setting of the signal generator to 70 Hz and again measure
and record the input and output voltages in Data Table El-3.2. Complete Data
Table El-3.2.
Exp. 1 -3 CascodeAmplifier 81
+12 V
1.a kn
47 kn 10 µF
+ c--<>
r+
A;n
100 µF
39 kn
C2
l
Vo
10 µF
a,
21 kn
lkn 100' µF
Figure El-3.1 Cascodc amplifier.
DATA TABLE E1·3.2
Input Input Output

frequency amplitude, amplitude, Voltage gain, Voltage gain
(Hz) '!lin PP 'Ila pp A, = 1Jo/1J1n (dB)
1. 50
2. 70
3. 100
4. 300
5. 700
6. 1,000
7. 3,000
8. 7,000
9. 10,000
10. 30,000
11. 70,000
12. 100,000
13. 500,000
I
4. Draw a Bode plot of frequency versus voltage gain in dB on semilog paper.

Determine from the graph the ferquencies at which the midband frequency gain
is down by 3 dB. Using these frequencies, 'calculate the bandwidth of the
amplifier.
62 Differential and Cascode Amplifiers . Chap, 1

Questions
1. Compare the cascode amplifier with the RC-coupled CE amplifier for de bias
and ac (midband frequency) operation.
2. Why isn't the cascode amplifier of Figure El-3.1 encountered very often in
discrete circuitry?
3. Explain the use of cascode amplifier in electronic circuitry.
Exp. 1-3 CascadeAmplifier

2
Introduction
to Operational Amplifiers
2-1 INTRODUCTION
In Chapter 1 you studied the two important types of direct-coupled amplifiers-

differential and cascode. You saw that when cascaded, the differential amplifier yields
a very high voltage gain. However, in differential amplifiers the matching of resistors
and transistors is essential for the proper operation of the circuit. For this reason the
differential amplifier and the cascode amplifier are manufactured as individual inte-
grated circuits, and the differential amplifiers, in particular, are used as "building
blocks" for more elaborate circuits called operational amplifiers. The cost of integrated
amplifiers is currently so low that they have effectively displaced the discrete amplifiers.
In this chapter we study the basic structure of the operational amplifier (op-amp)
and then analyze some typical operational amplifier circuits. We will also investigate
the op-amp symbol, types of op-amps, different grades of op-amps, and op-amp
development-among other things.
2-2 THE OPERATIONAL AMPLIFIER
An operational amplifier is a direct-coupled high-gain amplifier usually consisting of

one or more differential amplifiers and usually followed by a level translator and an
output stage. The output stage is generally a push-pull or push-pull complementary
symmetry pair. An operational amplifier is available as a single integrated circuit
package.
The operational amplifier is a versatile device that can be used to amplify de as
well as ac input signals and was originally designed for computing such mathematical
64 Introduction to Operational Amplifiers Chap. 2

functions as addition, subtraction, multiplication, and integration. Thus the name
operationalamplifier stems from its original use for these mathematical operations and
is abbreviated to op-amp. With the addition of suitable external feedback components,
the modem day op-amp can be used for a variety of applications, such as ac and de
signal amplification, active filters, oscillators, comparators, regulators, and others.
2-3 BLOCK DIAGRAM REPRESENTATION OF A TYPICAL

OP-AMP
I
Since an op-amp is a multistage amplifier, it can be represented by a block diagram as
shown in Figure 2-1.
The input stage is the dual-input, balanced-output differential amplifier. This
stage generaJly provides most of the voltage gain of the amplifier and also establishes
' the input resistance of the op-amp. The intermediate stage is usually another differ-
ential amplifier, which is driven by the output of the first stage. In most amplifiers the
intermediate stage is dual input, unbalanced (single-ended) output. Because direct
coupling is used, the de voltage at the output of the intermediate stage is well above
ground potential. Therefore, the level translator (shifting) circuit is used after the
intermediate stage to shift the de level at the output of the intermediate stage down-
ward to zero volts with respect to ground. The final stage is usually a push-pull com-
plementary amplifier output stage. The output stage increases the output voltage
swing and raises the current supplying capability of the op-amp. A well-designed
output stage also provides low output resistance.
Noninvertir;ig
input
Level Output
Input Intermediate shifting
stage stage stage
Inverting
input
Dual-input, Dual-input, Such• Complementary
balanced-output unbalanced output emitter follower symmetry
differential differential using constant ~II
amplifier amplifier current IOUrce mnplifier
Figure 2-1 Block diagram of a typical op-amp.
2-4 ANALYSIS OF TYPICAL OP-AMP EQUIVALENT C/RCU"S
First we consider a specific op-amp with a simpler equivalent circuit and perform
the analysis of this circuit to determine the input resistance and voltage gain. Then
the op-amp with a more complex equivalent circuit will be presented. However,
instead of a quantitative analysis, a qualitative analysis will be used for this complex
op-amp equivalent circuit.
While there are a variety of op-amps, each with specific inner design features
such as internal frequency compensation, FET inputs, Darlington inputs, current
Sec. 2-4 Analysis of Typical Op-Amp Equivalent Circuits

sources as active loads, input voltage and output -current limiter, and many others,
the analysis of specific op-amp equivalent circuits will provide a good basis for
understanding the inner operation and construction of the op-amp and aid in selecting
a proper op-amp for a desired application.
Example 2-1
The equivalent circuit of the Motorola op-amp MC 1435 is shown in Figure 2-2.
(a) Determine the collector current in each transistor and the de voltage at the output
terminai.
(b) Calculate the voltage gain of the op-amp.
(c) Determine the input resistance of the op-amp.
Assume that the Pac= P~ = 150 and VBB = 0.7 V for each transistor.
Solution. Figure 2-2 should give you an idea of the internal structure of the op-amp.
A close examination of this equivalent circuit reveals that it consists of four stages,
as shown in Section 2-3. These stages are labeled in Figure 2-2 and are separated by
dashed lines: Transistors Q1 and Q2 form the first differential amplifier stage, which
uses a constant current bias provided by transistor Q3 and associated resistors. This
first stage has invertingand noninverting inputs and hence can be driven with two inputs
or a single input. The second differential amplifier formed by transistors Q4 and Q,
uses an emitter bias and is driven by the outputs of the first differential amplifier. The
single-endedoutput of the second differentialamplifierdrives a level translator (emitter
follower), which is composed of transistor Q6 and a 15-kO resistor. The output of the
level translator drives a complementary transistor pair Q7 and Q., which produces
the final output voltage.
(a) To determine the collector current and the collector-to-emitter voltage of the first
differential amplifier stage, the inverting and noninverting input terminals arc assumed
to be connected to ground. Referring to Figure 2-2, the collector current in transistor
Q 1 and Q2 is then determined as follows:
Vc1 = Vee - (6.7 kO)Ic1
= 6 - (6.7 kO)lc1
vE. = Vet - Vas,
= 5.3 - (6.7 kO)Ic1
Since 1113 is negligiblysmall,
I Vs•+ Vu
" = 9.1 m + 5.5 m
11.3 - (6.7 k!l)Ic1
= 14.6k!l
Ya3 = (5.5 kn)/, - Vu
_ 5 S kO [11.3 - (6.7 k!l)Ic,J _ 6
- . 14.6kfl
Vs3 = V83 - Vab
= ;/6 "£u1.3 - (6.7 k!l)lc1J - 6.7
J _ +
BJ -
VE3
3.3 mVEE
(5.5 k!l/14.6 k!l)[l 1.3 - (6.7 k!l)/c1J- 6.7 +6

= 3.3 ill

--e
>0 o....---lt>
r,-1......._---ltlt~,.,.,__---------- -r-
- J
It
0
ft
--------- --- ~
+
.. lll ,...
>
... c:
(i"--1-----==IB~-Jii;i.n;._
~
J ]I ....0
- -------(, --
c:~
> .;~>1""~~;·~..-+-::-~~--J >

'f
f
J-r-----
I
m<'i ..
...
=r
+
iii! !Et
o" >
N s
c.;
--
GI
.§
~ !a.
!I ·- E
0.!!"U.
.! .
~
__________________J_
::J, ""
+
r !' ..
i ..J
.§
jl
i-
17
But /_.3 = 2Ici· Therefore,
(S.S ill)(l 1.3) (S.S k{l)(6.7 k{l)/c1 0.7
2Ici = (14.6 k0)(3.3 kO) (14.6 k0)(3.3 kO) - 3.3kll
2lc1 + 0.765/ci = 1.29 mA - 0.212 mA
LCl = 1.08 mA ......., 0 39 A ,
2.765 = ' m
This collector current can be used to compute the collector currents of the remaining
stages as follows:
Ye, = Yee - (6.7 ill)lc1
=6- (6.7 k0)(0.39 mA) = 3.39 V
Ys, = Yet - Yss,
= 2.69V
Hence
21z, _Vs,+ Vu
- 14.6k0
= 2.69 +6
ls, 29.2 kO = 0.298 mA
Ve, = Vee - (3.8 kO)Ic,
=6- (3.8 k0)(0.298 mA) = 4.87 V
Vs,= Ve, - Vas,
= 4.87 - 0.7 = 4.17 V
Therefore,
I _Vs,+ Y.u
.Bf - 15 ldl
4·17 6
-- + -- 0 ·678 mA
1skll
V.1r, = Ve, = V87 + Va_.1
= 4.17 + 0.7 = 4.87 V
Hence
_ Vee - V.1r,
I1 - 400
4.87 -- 2 . 83 mA
-- 6 -400
Since le, = 181 and le, ::::'. I.1r,,

11 =le,+ ls,
= ls, = 2.83 mA
The voltage Y•• at the output ten1)inal is
V.1r, = -Vu+ (2 ldl)I.1r1
= -6 + (2 ldl)(l.83 mA)
= -0.34 V ::'. 0 V as expected
Thus
. le, = lei ::::'. 0.39 mA
Introduction to Operational AmplifiM CMp. 2

lcs ,_, 0.78 mA
le4 = le, ,_, 0.298 mA
Ic« ,_, 0.678 mA
le, = 18a = 18.8 µA
!Ea= 2.83 mA
VEa = -0.34 V
(b) Voltage gain of the level translator as well as that of the output stage is approxi-
mately 1. To calculate the voltage gains of the differential amplifier stages, we need to
know their ac emitter resistances. The ac eaiitter resistance of each stage can be cal-
culated using the collector current obtained in part (a):
25 mV 25 mV ,_,
r,1 = r,« = I;;- = 0.39 mA = 64.1 Q
25 mV 25 mV ,_,
r,4 = r,5 =I;;-= 0.298 mA = 83.89 Q
25 mV 25 mV ,_,
r,« = IE6 . = 0.678 mA.= 36.87 n
Therefore, the voltage gain (Ad1) of the dual-input, balanced-output differential ampli-
fier is
Adi = Rei 112Pac(r,,) = 6.7 kQ 11(2)(150)(83.89)
r,1 64.1
= 82.55
And the voltage gain (Ad2) of the dual-input, unbalanced output-differential amplifier is
A _ Re, IIPacCrd + 15 kQ) _ 3.8 knll(150)(15.04kQ)
"2 - 2r,5 - (2)(83.89)
= 22.6
Thus the overall voltage gain of the op-amp is
A" = (A.,1)(A.,2) = (82.55)(22.6)
= 1865.63
(c) The input resistance of the op-amp is the same as the input resistance of the first
differential amplifier stage, and is given by Equation (1-14):
R1 = 2Pacr,,
= (2)(150)(64.1) = 19.23 kQ
This completes the analysis of MC1435 op-amp.
Figure 2-3 shows the schematic diagram of the 741 op-amp that has become an
industry standard. This unit is a high-gain, stable amplifier that features internal
compensation. A desired phase control at high frequencies is provided-by a 30-pF
capacitor that is fabricated on the chip. Since the equivalent circuit of the 741 op-amp
is more complex than that of the 1435, we will perform a qualitative (rather than
quantitative) analysis of the circuit.
The input differential amplifier consists of transistors Q1-Q, and Q2-Q4• A
differential input signal is applied between the bases of transistors Q1 and Q2• The
Sec. 2-4 Analysis of Typical Op-Amp Equivalent Circuits 89

..
::,
c.
+
s
0 I
> >
......c:
CC: N
c:
~
:: 0
a: It)
...
ci
c:
.. s
a: -
.,
ci
... c:
a:~
s
u,
:I.
-o
(J M
'-~l..~~Y./'v~~~~~~~~~~~~~--1r-..,.~, ci ~~~~--..------i
I
I
t
I
!
.!: a:
.~c:
...c 0
It)
·e
!?
ci ...c5c
ii= ::,
.E c:
8
M I
I
I
I
I
I
I
-.
I
I
I
... c:
a: ~ I
lil
I ~
I o
I -
I
I
I
___________ JI
...i=
c5c
::,
70
maximum input signal capacity of the input differential stage is increased by PNP
transistors Q3 and Q4, since the base-emitterjunction of Q3 is in series with the base-
emitter junction of Q, and the base-emitter junction of Q4 is in series with that of Q2•
Since the signal levels normally encountered do not exceed the voltage across both of
the series junctions, the input differential stage is practically indestructible.
The constant base current in Q3 and Q4 is supplied by a constant current source
consisting of transistors Q9 and Q10 and diode-connected transistors Q8 and Q11•
This constant base current in transistors Q3 and Q4 in turn establishes the operating
current for the input differential stage. The1diode-connected transistors Q8 and Q11
stabilize the base potentials of transistors Q9 and Q10, respectively.
A controlled current source is formed by transistors Q5 and Q6 and resistors
R1, R2, and R3• The emitter current of-transistors Q5 and Q6 can, however, be con-
trolled by varying a 10-kO-potentiometer that is externally connected between the
offset null terminals and by connecting the wiper to the negative supply. (For more
information on offset null capabilities of the 741,, refer to Section 5-2). Transistor Q7
supplies the base currents to transistors Q5 and Q6• Since transistors Q5 and Q6 are
identical (and R1 = R2), their base currents must be equal, and in turn their collector
currents must also be equal at all times. The collector voltage of transistor Q5 controls
the operation of transistor Q,; that is, any change in Q5 collector voltage produces
identical changes in transistor Q5 and Q6 collector currents via transistor Q7•
The output of the differential stage is taken at the junction of transistors Q4
and Q6, which act as a complementary-symmetry amplifier. For example, suppose
that a differential input signal applied between Q1 and Q2 causes the collector currents
of Q., Q3, and Q5 to increase, and the collector currents of Q2 and Q4 to decrease.
This differential input signal also causes the collector voltage of Q5 to increase, which
in turn causes the collector currents of Q5 and Q6 to increase. Thus at the junction of
transistors Q4 and Q6, the net change in current is twice that of Q4 alone. This action
verifies that transistors Q4 and Q6 act as a complementary-symmetry amplifier. The
output at the junction of Q4 and Q6 is proportional to the differential input signal.
The output of the differential stage is applied to the common collector amplifier
formed by Q16 and R9• The output of Q16 drives the common emitter amplifier, which
is a bias source for transistors Q18 and Q,9• The CE amplifier is composed of Q17,
R8 and constant current load formed by Q13• Transistors Q13 and Q12 form a current
mirror which establishes the current through transistors Q"' Q18, and Q19• In fact,
the currents in collectors of Q13 is equal to the current through R5• The network
consisting of transistor Q 18, Q 19, and R 1 0 is designed to bias the output complementary
symmetry stage formed by transistors Qu, Q20 and resistors R6, R, in the linear
region. These transistors also separate the bases of Q14 and Q20 by two diode drops
and in tum temperature-compensate currents in Q14 and Q20• The output is-measured
at the junction of R6 and R,, which are in the emitter circuits of Q 14 and Q20, respec-
tively.
Transistor Q22• performs two functions. It serves as a buffer between Q17 and
Q20 and also provides a negative feedback to Qw The current limiting for the output
complementary-symmetry stage is provided by-transistors Qw Q2i, and Q23• If the
output (load) current exceeds the safe limit, the voltage drops across R6 and R,
increase, causing QB and Q21 to turn on, which in tum causes Q23 to tum on. This
Sec. 2-4 Analysis of Typical Op-Amp Equivalent Circuits 71

--,-
action however, turns off Q16 and in turn Q11, which reduces the emitter currents in
Q22• The reduction in the currents of Q22 causes the currents in Q18 and Q19 to
decrease, which in turn lowers the currents in Q14 and Q20• The diode-connected
transistor Q24 is a temperature-compensating diode for transistor Q23•
2-5 SCHEMATIC SYMBOL
Given an op-amp schematic diagram like the one in Figure 2-2 or 2-3, we can save time
by using a schematic symbol for the entire circuit. Figure 2-4 shows the most widely
used of such symbols for a circuit with two inputs and one output. For simplicity,
power supply and other pin connections are omitted. Since the input differential
amplifier stage of the op-amp is designed to be operated in the differential mode, the
differential inputs are designated by the ( +) and ( - ) notations. The· ( +) input is the
noninverting input. An ac signal (or de voltage) applied to this input produces an· in-
phase (or same polarity) signal at the output. On the other hand, the(-) input is the
inverting input because an ac signal (or de voltage) applied to this input produces an
180° out-of-phase (or opposite polarity) signal at the output.
Noninverting v,
input ~---1
Inverting 0----1 Figure 2-4 Schematic symbol of

input v2 op-amp.
In Figure 2-4,
v1 = voltage at the noninverting input (volts)
v2 = voltage at the inverting input (volts)
v0 = output voltage (volts)
All these voltages are measured with respect to ground
A = large-signal voltage gain that is specified
on the data sheets for an op-amp
2-6 INTEGRATED CIRCUITS
The circuits shown in Figure 2-2 and 2-3 are integrated circuits (ICs), meaning that all
the components in each circuit are fabricated on the same "chip." ICs have become a
vital part of modern electronic circuit design. They are used in the computer industry,
automobile industry, home appliances, ccmmunication, and control systems, where
they permit miniaturization and superior performance not possible with discrete
components. ICs are now being used in all types of electronic equipment because of
the long, trouble-free service they provide. In addition, they are economical because
they are mass produced. ·
Classified according to their mode of operation, !Cs are of two basic types:
digital or linear.

Digital /Cs are complete functioning logic networks that are equivalents of basic
transistor logic circuits. They are used to form such circuits as gates, counters,
multiplexers, demultiplexers, shift registers, and others. Since a digital IC is a complete
predesigned package, it usually requires nothing more than a power supply, input, and
output.
Digital circuits are primarily concerned with only two levels of voltage (or
current): "high" and "low." Therefore, accurate control of operating-region charac-
teristics is not required in digital circuits, unlike in linear circuits. For this reason,
digital circuits are easy to design and are produced in large quantities as low-cost
devices.
Linear /Cs are equivalents of discrete transistor networks, such as amplifiers,
filters, frequency multipliers, and modulators, that often require additional external
components for satisfactory operation. For example, external resistors are necessary
to control the voltage gain and frequency response of an op-amp. In linear circuits the
output electrical signals vary in proportion to the input signals applied or the physical
quantities (parameters) they represent_Since the electrical signals are analogous to
the physical quantities, linear circuits are also referred to as analog circuits.
Of all presently available linear !Cs, the majority are operational amplifiers.
With suitable external components, the op-amp is used in amplifiers, active filters,
integrators, differentiators, and in countless other applications. A wide variety of
special-purpose linear JCs is available for uses in comparators, voltage regulators,
digital-interface circuits, and in radio-frequency and power amplifiers.
In addition to the op-amp and special-purpose linear ICs, component arrays are
also available in IC form. Such arrays may consist of groups of isolated transistors,
diodes, and resistors as well as of Darlington pairs or individual stages such as differ-
ential and cascade amplifiers.
Op-amps are further classified into two groups: general-purpose and special-
purpose. General-purpose op-amps may be used for a variety of applications, such as
integrator, differentiator, summing amplifier, and others. An example of a widely used
general-purpose op-amp is the 741/351. On the other hand, special-purpose op-amps
are used only for the specific applications they are designed for. For example, the
LM380 op-amp can be used only for audio power applications.
2-1 TYPES OF INTEGRATED. CIRCUITS
Integrated circuits may be classified as either monolithic or hybrid. Most linear !Cs
are produced by the monolithic process in that all transistors and passive elements
(resistors and capacitors) are fabricated on a single piece of semiconductor material,
usually silicon. "Monolithic" is a Greek-based word meaning "one stone."
In monolithic /Cs all components (active and passive) are formed simultaneously
by a diffusion process. Then a metallization process is used in interconnecting these
components to form the desired circuit. Electrical isolation between the components
in monolithic LCs can be achieved by any one of the three isolation techniques:
dielectric, beam-lead, or PN-junction. However, the PN-junction isolation is most
economical and is, therefore, commonly used.
Sec. 2- 7 Ty~es of lntegrate"dCircuits 73

·- -- ---::;;--
The monolithic process makes low-cost mass production of I Cs possible. Also,

monolithic ICs exhibit good thermal stability because all the components are inte-
grated on the same chip very close to each other.
However, the large values of resistance and capacitance that are required in
some linear circuits cannot be formed using the· monolithic process. Moreover, there
is no method available to fabricate transformers or to form large values of inductors in
integrated-circuit form. However, if these components are required in a given appli-
cation, external discrete components can be used with the IC.
In hybrid !Cs, passive components (such as resistors and capacitors) and the
interconnections between them are formed on an insulating substrate. The substrate
is used as a chassis for the integrated components. Active components such as transis-
tors and diodes, as well as monolithic integrated circuits, are then connected to form a
complete circuit. For this reason, low-volume production methods are best suited to
hybrid IC technology.
Hybrid ICs are further classed as thin-film or thick-film, depending on the
method used to form the resistors, capacitors, and related interconnections on the
substrate. When a suitable material is1evaporated on a substrate in forming resistors,
capacitors, and interconnections, a thin-film hybrid IC is obtained. On the other hand,
in a thick-film hybrid IC the resistors, capacitors, and interconnections are etched on
the substrate by silk screening.
2-8 MANUFACTURERS' DESIGNATIONS FOR INTEGRATED

CIRCUITS
In the United States alone there are well over 30 IC manufacturers producing millions
of !Cs per year. Each manufacturer uses a specific code and assigns a specific type
number to the ICs it produces. That is, eacn manufacturer uses its own identifying
initials followed by its own type number. For example, the 741 type of internally
compensated op-amp was originally manufactured by Fairchild and is sold as the
µA741, where "µA" represents the identifying initials used by Fairchild. Initials used
by some of the well-known manufacturers of linear I Cs are as follows:
Fairchild µA
µAF
National Semiconductor LM
LH
LF
TBA
Motorola MC
MFC
RCA CA
CD
Texas Instruments SN

Sprague ULN
ULS
ULX
Intersil ICL
IH
Siliconix, Inc. L
Signetics N/S
NE/SE
SU
Burr-Brown BB
Remember that the initials used by manufacturers in designating digital ICs may
differ from those used for linear ICs. For example, "DM" and "CD" are the initials
used for digital monolithic and CMOS (complementary metal-oxide semiconductor)
digital ICs, respectively, by National Semiconductor.
In addition to producing their own I'Cs, a number of manufacturers also produce
one another's popular ICs. In second-sourcing such ICs, the manufacturers usually
retain the original type number of the IC in their own IC designation. For example,
Fairchild's original µA741 is also manufactured by various other manufacturers under
their own designations, as follows:
National Semiconductor LM 741

Motorola MC 1741
RCA CA 3741
Texas Instruments SN 52741
Signetics N 5741
Note that the last three digits in each manufacturer's designation are 741. All
these op-amps have the same specifications and, therefore, behave the same.
More information is available in the linear industry's cross reference guides on
the types of I Cs manufactured by different manufacturers. An industry cross-reference
guide is generally included in the manufacturer's data book.
Since a number of manufacturers produce the same IC, for convenience we shall
refer to such ICs by their type numbers and delete manufacturers' identifying initials.
For example, instead of referring to an op-amp as a µA741 or MC1741, we shall refer
to it simply as a 741.
Some linear ICs are available in different classes, such as A, C, E, S, and SC.
For example, the 741, 741A, 741C, 741E, 741S, and 741SC are different versions of the
same op-amp. The 741 is a military-grade op-amp (operating temperature range:
-55 to 125°C) and the 741C is a commercial-grade op-amp (operating temperature
range: 0 to 70°C/75°C). On the other hand, the 741A and 741E are improved versions
of the 741 and 741C, respectively, in that they have improved electrical specifications
over their counterparts. The 741C and 741E are identical to the 741 and 741A except
that the former have their performance guaranteed over a Oto 70°/75°C temperature
Sec. 2-8 Manufacturers' Designations for Integrated Circuits 75

range, instead of -55 to 125°C. The 741S and 741SC are military- and commercial-
grade op-amps, respectively, with higher slew rate (rate of change of output voltage
per unit of time) than the 741 and 741C.
2-9 DEVELOPMENT OF INTEGRATED CIRCUITS
The development of linear ICs can be traced back to early 1960s, when arrays were
first fabricated on a single silicon chip. The arrays are combinations of isolated
components such as diodes and transistors or individual stages such as differential
amplifiers and Darlington pairs. The use of such IC arrays helped minimize the
temperature-drift problem inherent in discrete transistor and diode circuits. It also
greatly reduced the size of discrete electronic circuits.
In 1963 Fairchild Semiconductor introduced the first IC op-amp, its µA702,
which set the stage for the development of other IC op-amps. The unequal supply
voltages, such as + Vee = -12 V and - VEB = -6 V; relatively low input resistance
(40 kn typically); and low voltage gain (3600 V/V) were the major drawbacks of the
µA702 op-amp. For these reasons the µA702 was not universally accepted.
In 1965 Fairchild introduced the µA709, an improved op-amp compared to the
µA702. More specifically, the µA709 had symmetrical supply voltages such as+ Vee=
· +15 V and -VEB = -15 V; much higher input resistance (400 kn, typically); and
a voltage gain of 45,000 V/V. The µA709 was the first quality op-amp and is, therefore,
remembered for its historical significance. The µA 709 is also regarded as a first-
generation op-amp. Another example of a first-generation IC is the MC1537. The
disadvantages of first-generation I Cs are as follows:
1. No short-circuit protection. The op-amp is susceptible to burnout if output is

accidentally shorted to ground.
2. A possible latch-up problem. Output voltage can be latched up to some value and
then fails to respond to changes in input signal applied.
3. Requires an external frequency-compensating network (two capacitors and a
resistor) for stable operation. This means that when an external compensating
network is not used, the op-amp may oscillate. Ideally, these compensating
components should be internally integrated so that no extra work of connecting
them to the op-amp is required.
The next major advancement in IC op-amp technology came in 1968 with the
introduction of the Fairchild µA741, an internally compensated op-amp. Unlike the
µA709, it has short-circuit protecti9n, has no latch-up problem, and is inherently
stable. Besides that, it has very high input resistance (2 MO, typically), extremely high
voltage gain (200,000 V/V), and offset null capability. It is regarded as a classic among
IC op-amps because of its performance, versatility, and economy. It is one of the
most widely used general-purpose op-amps in industry even a decade after its intro-
duction. The 741 is an example of second-generation op-amps. Other examples of
second-generation op-amps are the LMlOI, LM307, µA748, and MC1558. General-

purpose op-amps such as the 741 and 307 are used in the greatest percentage of
applications.
The design philosophy and technology used in the 741 was implemented in
later-generation op-amps to enhance and optimize their performance characteristics.
This trend gave birth to a variety of special-purpose op-amps. These devices had one
or more of the following distinguishing features: high slew rate, that is, high rate of
change of output voltage per unit of time; wide bandwidth; high input resistance;
very low input currents and voltage offsets or drifts; programmability, and other
characteristics. For example, the LM318 is ,a high-speed op-amp with 15-MHz
small-signal bandwidth and guaranteed 50-V / µs slew rate. The key features of the
µA771 op-amp are a low input bias current of200 pA and a high slew rate of 13 V/µs,
typically. The µA714 is a precision op-amp with low offset voltage (75 µV), low input
offset current (2.8 nA), low offset voltage drift ( 1.3 µV / I C), and low noise. The
0
µA791 op-amp is a power amplifier with output current capability of 1 A, whereas

the µA 776 is a multi-purpose programmable op-amp. Thus most later-generation I Cs
have the improved electrical specifications and hence exhibit superior performance
over preceding-generation ICs. 'r
New directions in linear ICs are aimed at the development of building-block

circuits which not only include consumer circuits (audio, radio, and TV), but also
industrial circuits (timers, regulators, etc.) The prime example of this concept is the
emergence of cost-saving quad devices such as the LM324 and M C474 l. The trend is
to increase component density and yield while keeping the cost down through
improved technology. Today's state of the art developments are concerned with
BI-FET and laser trimming technology. National Semiconductor is the developer of
BI-FET technology, which has introduced wide bandwidths and fast slew rates,
together with low bias currents and low input offset currents. For example, the
LF351 and LF353 BI-FET op-amps have low input bias and offset currents (200 and
100 pA, respectively), a large unity gain bandwidth (4 MHz), and a fast slew rate
(13 V/µs). In addition, these op-amps have the same pin-outs as the 741 and 1458
(dual 741), respectively. This means that designers can immediately upgrade the
overall performance of existing designs by simply placing LF351/LF353 op-amps into
sockets presently hosting the 741 types. Laser trimming technology, at the same time,
has achieved lower input offset voltages. Trimming and BI-FETtechnologies are com-
bined (TRIMFET, for short) by Motorola to provide precision input characteristics
at a low cost. Motorola's MC34001/MC34002/MC34004 single, dual, and quad
op-amps are the best examples of TRIMFET technologies. These devices are pin-
compatible with the 741, 1458, and 324 (quad) op-amps and have nearly identical
electrical characteristics to those of the LF351/LF353.
The growth of IC technology and the implementation of new techniques is more
evident in the development of digital I Cs. Advances in semiconductor technology have
had a remarkable effect on the development of digital I Cs. The best current example
of such developments is the MC68000 microprocessor, which has 70,000 active
components integrated on a single chip. The fabrication of such a complex and
powerful digital IC was made possible through dry plasma etching, projection printing,
and HMOS (high-density, short-channel MOS) circuit design techniques. In short,
Sec. 2-9 Development of Integrated Circuits 77

advances in technology have made ICs easy to use, more reliable, and more flexible
in application, while maximizing performance.
2-9.1 SS/, MS/, LSI, and VLSI Packages
ICs are classified according to the number of components (or gates, in the case of
digital ICs) integrated on the same chip, as listed below:
Small-scale integration SSI

Medium-scale integration MSI
Large-scale integration LSI
Very large scale integration VLSI
In the SSI package, the number of components integrated on the same chip is
typically < 10. Most of the arrays fall into this group. In the MSI IC, the number of
components is < 100, whereas the LSI package includes > 100 components -. Almost
all the linear integrated circuits and integrated combination logic circuits are MSI
packages. Most of the sequential logic circuits are of the LSI type. In the VLSI
package, the number of components formed on the same chip is typically > 1000. A
classic example of a VLSI package is Motorola's MC68000 microprocessor IC, which
houses some 70,000 components on the same chip.
As IC technology progresses and more efficient manufacturing techniques allow
the manufacture of more complex yet better quality ICs, the price of an IC package
continues to fall. A typical example would be the hand-held calculator. Current cal-
culator prices are remarkably below the levels established when these devices were
introduced in the late 1960s.
2-10 INTEGRATED CIRCUIT PACKAGE TYPES, PIN

IDENTIFICATION, AND TEMPERATURE RANGES
2-10.1 Package Types
Figure 2-5 shows the three basic types of linear IC packages:
l. The flat pack

2. The metal can or transistor pack
3. The dual-in-line package (for short DIP)
In the flat pack, the chip is enclosed in a rectangular ceramic case with terminal
leads extending through the sides and ,ends as shown in Figure 2-S(a). The flat pack
comes with 8, 10, 14, or 16 leads. These leads accommodate the power supplies, inputs,
outputs, and several special connections required to complete the circuit.
In the metal can or transistor pack, the chip is encapsulated in a metal or plastic
case [see Figure 2-5(b)-(d)]. The transistor pack is available with 3, 5, 8, 10, or 12 pins.
Most of the voltage-regulator ICs, such as the LMI 17, have 3 pins. Power op-amps
and audio power amplifiers are usually available in 5-pin packages. The metal can

T0-5 Style package T0-5 Style package with
Ceramic flat package
with straight leads dual-in-line formed
leads (DI L-CAN)
8-lead version
14-lead version 8, 10, and 12-lead versions
(c)
{al {b)
Dual-in-line welded-seal
T0-5 Style package ceramic package
Dual-in-line plastic package
with radial formed leads
{d) 8, 14, and 16-lead versions 14, and 16-lead versions
(el (f)
Figure 2-5 Types of IC packages: (a) flat pack; (b-d) metal can; (e, f) dual-in-
line package. (Courtesy of RCA Corporation.)
package is best suited for power amplifiers because metal is a good heat conductor
and consequently has better dissipation capability than the flat-pack or dual-in-line
package. In addition, the metal can package permits the use of external heat sinks.
Most of the general-purpose op-amps come in 8, IO, or 12-pin packages.
In the dual-in-line package (DIP), the chip is mounted inside a plastic or ceramic
case, as shown in Figure 2-5(e) and (f). The DIP is the most widely used package type
because it can be mounted easily. The 8-pin dual-in-line packages are referred to as
mini DIPs. Dual-in-line packages are also available with 12, 14, 16, and 20 pins. In
general, as the density of components integrated on the same chip increases, the
number of pins also goes up. This is especially true in digital !Cs. For example, there
are 64 pins on the MC68000 microprocessor chip, compared to 40 pins on MC6800
micro-processor.
. Table 2-1 is a summary of the number of pins and types of packages in which
Jinear integrated ·c_ircuits are presently available. On the other hand, almost all digital
!Cs are DIP packages. Metal can packages are also available with dual-in-line formed
leads (DIL-CAN) and with radial formed leads as shown in Figure 2-5(c) and (d).
Different outlines exist within each package style to accommodate various die sizes
and number of pins (leads). For example, T0-99, T0-100, and T0-101 are some of
the outlines available in a transistor pack.
Sec. 2-10 Integrated Circuit Package Types, Pin Identification, and Temperature Ranges · 79
TABLE 2-1 LINEAR INTEGRATED CIRCUIT PACKAGES AND PIN NUMBERS
Type of package
Number Metal can or Dual-in-line (DIP)

of Flat pack transistor pack package (ceramic
pins (ceramic) (metal or plastic) or plastic)
3 No Yes No
5 No Yes No
8 Yes Yes Yes (mini DIP)
10 Yes Yes No
12 No Yes Yes
14 Yes No Yes
16 No No Yes
20 No No Yes
2-10.1 (a) Selecting an IC package.· If the IC is used for experimentation/

breadboarding purposes, the best choice is the DIP package, because it is easy to
mount. The mounting does not require bending or soldering of the leads. The DIP is
also suitable for mounting on printed circuit boards because of its lead coristruction
and more spacing between the. leads. Generally, the ceramic DIP is more expensive
than the plastic DIP, but the ceramic mainly dissipates more heat.
The flat pack is more reliable and lighter than a comparable DIP package and is,
therefore, suited for airborne applications. On the other hand, the metal can is the
best choice, if the IC is to be operated at relatively high power and expected to
dissipate considerable heat.
When all three packages are available for a specific application, the choice can
be made based on the relative cost and ease of fabrication/bread boarding the IC.
Some applications may not allow a choice of package because the IC is available in
only one package style.
2-10.2 Pin/dentification
Although there has been a tendency to standardize IC terminal connections, the

various manufacturers still use their own systems. Most manufacturers use the pin
designations -, depicted in Figure 2-6 for the three types of packages.
2-10.3 TemperatureRanges
All !Cs manufactured fall into one of the three basic temperature grades:
I
1. Military temperature range: -55 to + 125°C
(or -55 to +85°C)
2. Industrial temperature range: -20 to +85°C
(or -40 to +85°C)
3. Commercial temperature range: Oto +10°c
(or Oto +75°C)

Tab
Dot
14-lead version
(a) (b)
Small
Notch identation · Notch Dot
(c)
Figure 2-6 Typical pin designations for different packages: (a) flat pack,
(b) metal can, (c) DIP.
The individual data sheets specify exact values of the IC parameters and condi-
tions under which these parameters are determined. The standard practice is to
specify IC parameters at room temperature, that is, 25°C.
The military- and. commercial-grade ICs differ in specifications for supply
voltages, input current and voltage offsets and drifts, voltage gains, and others. The
military grade devices are almost always of superior quality, with tightly controlled
parameters, and consequently cost more. Commercial-grade ICs have the worst
tolerances among the three types but are the cheapest. In short, performance and cost
are the important factors in selecting an IC.
2-11 ORDERING INFORMATION

Generally, in ordering an IC the following information must be specified: device type,
package type, and temperature range. The device type is a group of alphanumeric
characters such as µA741, LM741, and MC1741. These characters refer to the data
sheet that specifies the device's functional and electrical characteristics. The basic
package type-flat pack, transistor pack, or DIP-is represented by one letter. The
military, industrial, or commercial temperature range is either numerically specified
or included in the device type number or represented by a letter.
Sec. 2-11 Ordering Information 81

Unfortunately, the manufacturers do not have a consistent format by which the
ordering information should be specified. For example, the ordering information for
Fairchild's 741 mini DIP with commercial temperature range is as follows:
µA741 T C
Device t_yp_e P_a_c-kai'- ~mercial
(op-amp) (mini DIP) temperature
range (0 to 70°C)
On the other hand, the ordering information format for a typical Motorola IC
is as follows:
MC34001 P 0° to 70°C
Device type ----- 7

Package type ------...
Temperature range
(op-amp) (plastic DIP) (commercial)
In National Semiconductor ICs the temperature range is denoted in the device
number itself:
LM101A F
Device type
.> '"--.....
Package type
and (flat pack)
temperature range
In National's linear ICs, a 1-2-3 numbering system is used to represent the
temperature range. For example, in LM101/LM201/LM301 the 1 denotes a military
temperature range device, the 2 denotes an industrial temperature range device, and
the 3 denotes a commercial temperature range device.
Note that the package letter designations and temperature range nomenclatures
are independently defined by each manufacturer. Therefore, the best source of
information for ordering an IC is the data book.
2-12 DEVICE IDENTIFICATION
The IC is identified by marking the device type number on the face of the IC. This
number is usually accompanied by the date code, indicating the year and week the
device was manufactured. Figure 2-7 shows an example of Fairchild's device identifi-
cation method.
Devicetype (toltage regulator)
µA723PC
Fairchild Year Weekof the year Figure 2-7 Device identification.

2-13 POWER SUPPLIES FOR INTEGRATED CIRCUITS
Most linear ICs (particularly op-amps) use one or more differential amplifier stages,
and differential amplifiers require both a positive and negative power supply for
proper operation of the circuit. This means that most linear I Cs need both a positive
and a negative power supply. A few linear I Cs (especially earlier op-amps) use unequal
power supplies, and some ICs require only a positive supply. For example, the 702
op-amp requires unequal power supplies, whereas the 324 requires only a positive
supply. When a single supply is used, it is normally necessary to connect an extra
circuit to the IC. Some dual-supply op-amp ICs can also be operated from a single
supply voltage, provided that a special external circuit is used with it. Digital ICs, on
the other hand, generally require only one positive supply voltage. [An exception is
the emitter-coupled logic (ECL)IC.]
The two power supplies required for a linear IC are usually equal in magnitude,
+ 15 V and -15 V, for example. These power supply voltages must be referenced to a
common point or ground. Unfortunately, as in the case of ordering information,
manufacturers do not agree on power supply labeling. For example, Fairchild uses
V+ to indicate the positive voltage and V- to indicate the negative voltage or Vs
to indicate both positive and negative voltages. On the other hand, Motorola uses the
symbols + Vee and - VBB (as in discrete transistor circuits) to represent positive and
negative voltages, respectively. We will follow Motorola's notation of the power
supplies.
Figure 2-8 shows power supply connections for the 741/351 op-amp. The
numerals adjacent to terminals are pin numbers. Thus for the 741/351 op-amp, pin 7
is a positive supply pin and pin 4 is a negative supply pin. The remaining pins on the
741/351 are omitted for the sake of simplicity.
+Vee
Noninverting
input 6
1>----oOutput
Inverting
input
Figure 2-8 Typical linear IC op-amp

power supply connections.
Instead of using two separate power supplies, we can use a single power supply
to obtain+ Vee and ~ VBB, as shown in Figure 2-9. In Figure 2-9(a) the value of RR
should be > 10 ldl so that it does not draw much current from the supply Vs. The
two capacitors provide for decoupling (bypass) of the power supply; they range in
value from 0.01 to 10 µF. In Figure 2-9(b) Zener diodes are used to obtain symmetrical
supply voltages. The value of Rs should be chosen such that it supplies sufficient
current for the diodes to operate in the avalanche mode. The potentiometer is used in
Figure 2-9(c) to assure equality between + Vee and -VEE values. Diodes D1 and D2
are intended to protect the IC if the positive and negative leads of the supply voltage
Vs are accidentally reversed. Note that these diodes could also be connected in
Figure 2-9(a) and (b).
Sec.2-13 Power Suppliesfor IntegratedCircuits 83

__ ...,.,..,.,_ +V cc = +V z 1
+ 01
Vs.=..
-T 02
(a) (b)
01
Vs
'----te.t----------- -VEE :!! - -
2
02
(cl
Figure 2-9 Different arrangements of obtaining positive and negative supply

voltages for an op-amp.
SUMMARY
1. An operational amplifier is a direct-coupled high-gain amplifier consisting of one or more

differential amplifiers, usually followed by a level translator and an output stage. The block
diagram representation of the op-amp helps to visualize its internal construction.
2. In integrated circuits (ICs) all the components are fabricated on the same chip (chassis).
Classified according to their mode of operation, I Cs are of two basic types: digital or
linear. Digital ICs are complete functioning logic networks that are equivalents of basic
transistor logic circuits. On the other hand, linear ICs are equivalents of discrete transistor
networks such as amplifiers, filters, frequency multipliers, and modulators. Most linear
ICs are produced by a monolithic process in that all transistors and passive elements
(R and C) are fabricated on a single piece of semiconductor material. In hybrid ICs, passive
components and the interconnections between them are formed on an insultating substrate.
Active components and monolithicICs are then connected to form a complete circuit.
3. Each manufacturer uses a specific code and assigns a specific type number to the ICs it
produces. Since the invention of the op-amp in early 1960s, there have been a number of
op-amp (IC) generations. Later-generation ICs have improved specifications and hence
exhibit superior performance.
4. Linear ICs are available in three basic types: the flat pack, the metal can, and the dual-
in-line (DIP) package. Almost all digital ICs are DIPs.
5. Most linear ICs require both a positive and a negative supply. The standard supply voltages
for op-amps are ±15 V. On the other hand, most digital ICs require only one positive
supply voltage.
84 Introduction to Operational Amplifiers Chap.2

QUESTIONS
2-1. What is an op-amp?
2-2. List four basic building blocks of an op-amp.
2-3. What is the advantage of using a schematic symbol for an op-amp?
2-4. Explain briefly the difference between digital and linear ICs.
2-5. What-is the difference between monolithic and hybrid ICs?
2-6. List the disadvantages of first-generation op-amps, such as the 709.
2-7. What is the major difference between SSI, MSI, LSI, and VLSI ICs?
2-8. List three types of linear IC pac(ages.
2-9. What are the three operating temperature ranges of the IC?
2-10. What is the major difference between the power supply requirements of linear and
digital ICs?
2-11, Name two recent op-amps (1980 technology) that are direct replacements for the 741
op-amp (1960 technology).
PROBLEMS
2-1. Referring to the LH0005 op-amp equivalent circuit shown in Figure 2-10, determine
(a) the collector current through each transistor and (b) the de voltage at the output
terminal. (Assume that each transistor has Pde = Pac
= 100 and VBE = 0.7 V.) (c) Draw
+Vee= 10V
2kn
10 kn 10 kn
Output
12kn
3
12 kn
6 8
-Vee =-10V
Figure 2-10 Equivalent circuit of the LHOOOS for Problem 2-1. (Courtesy of
National Semiconductor.)
the block diagram for the circuit shown in Figure 2-10 and explain the function of each
block.
2-2. For the op-amp of Problem 2-1, determine:
(a) The overall voltage gain
(b) The input resistance
(c) The maximum output voltage .swing
86 Introduction to OperationalAmplifiers Chap. 2

3
Interpretation of Data Sheets

and Characteristics of an Op-Amp
~--· ...._, _
3-1 INTRODUCTION
In present-day electronic systems a basic building block is the op-amp. Therefore, a
better understanding of the characteristics of op-amps and of their importance to
overall circuit operation is essential. The manufacturers supply data sheets for the
!Cs they produce. These data sheets provide a wealth of information: absolute maxi-
mum ratings, intended·applications, electrical characteristics,performance limitations, ..
pin diagrams, equivalent circuits of the devices, and more. To get the most use out of
these data sheets, we must be able to interpret properly the information presented in
them. The lack of standardization of the IC specifications,which includes package type
designations, device nomenclature, pin configuration, and ordering information, also
makes it imperative to refer to the data sheets.
The purpose of this chapter is to explain how to read the typical op-amp data
sheet, to define most electrical ·parameters given there, and to evaluate their signifi-
cance. Proper interpretation of data sheet should not only help to understand the
characteristics of the op-amp but should also help to select a proper op-amp for a
desired application. After these considerations,the chapter discussesequivalent circuit
and open-loop op-amp configurations.
3-2 INTERPRETING A TYPICAL SET OF DATA SHEETS
Figure 3-1 shows data sheets for a Fairchild µA741 op-amp. Although the series
includesthe 741, 741A, 741C, and 741E models, the schematic diagrams and electrical
parameters for all of them are the same, with only the values of the parametersdiffering
87
1,1A741
FREQUENCY-COMPENSATED OPERATIONAL AMPLIFIER
FAIRCHILD LINEAR INTEGRATED CIRCUITS
GENERAL DESCRIPTION- The µA741 is I high perf0<mancemonolithic Operational Amp)lfler CONNECTIONDIAGRAMS

constructed using the Fairchild Planar• epitaxial proceu. I~ is Intended for • wide rangeof 1nalog
appllcetlon1. High common mode voltl(le rangeand absence of latch-up tendencies make the 11A741- 8-PINMETAL CAN
ide1I tor usees a voltage follower. The high gain ind wide rangeof operating voltageprovidessuperior (TOPVIEW)
performancein integrator, summing amplifier, and gener1I feedbackappllc1tlon1. PACKAGEOUTLINE 68
PACKAGECODE H
NC
• NO FREQUENCYCOMPENSATIONREQUIRED
• SHORTCIRCUIT PROTECTION
• OFFSETVOLTAGE NULL CAPABILITY
• LARGE COMMONMODE AND DIFFER.ENTIALVOLTAGE RANGES
• LOW POWERCONSUMPTION
• NO LATCH-UP
ABSOLUTEMAXIMUM RATINGS
Supply Voltage Note: ·Pin 4 connected to C.M
µA741A,µA741,11A741E t22 V
11A741C t18 V
Internal Power Dissipation (Note 1) ORDER INFORMATION
TYPE PART NO.
Metil Can 500mW.
µA741A µA741AHM
Moldedind Hermetic DIP 670mW µA7'1 µA741HM
Mini DIP 310mW µA7'1E µA741EHC
Flatpak 570mW µA741C 11A741HC
Dltterenti1I Input Voltage t30V
Input Voltege (Note 2) t15 V
StorageTamperetureRa11ge
Metal Can, Hermetic DIP, end Flatpek -66°C to +150°C
Mini DIP, MoldedDIP -ss•c 10 +12s0c 14-PINDIP
OperatingTemperature Range (TOPVIEW)
Military (11A741A, 11A741) -55°C to +125°C PACKAG°EOUTLINESBA, 9A
Commercial (µA741E,µA741C) . o•c 10 +10°c PACKAGECODES D P
Pin Temperature (Soldering)
Metal Can, Hermetic DIPs,and Flaio-k (60 11 300"C
Molded DIP1 (1(11) 260"C
Output Short.Circuit Duration (Not131 Indefinite NC
8,,PINMINt DIP 10-PIN FLATPAK NC

(TOPVIEW) (TOPVIEW)
PACKAGE OUTLINES 6T 9T PACKAGEOUTLINE 3F -0,FSET
NUll
PAqKAGECODES R T PACic;,AGECODE F
-IN
-OFFSET +IN
NC
NULL NC NC
-0,FS(T NC v-
-IN V• NULL
-IN v+
NC
•IN OUT
•IN '-t::=:::::JOUT
v-· + OFFSET v- + OffSET
NULL HULL
ORDER INFORMATION
TYPE PART NO.
,..A741A ,..A741ADM
ORDER INFORMATION ORDER INFOAMATJON ,..A741 ,..A741DM
TYPE PART NO. TYPE PART NO. 11A741E µA741EDC
11A741C 11A741TC µA741A )IA741AFM 11A7,1C ,..A741DC
µA741C µA741RC )IA741 11A741FM )&A74JC ,..A741PC
Notes on following peges. •Ptan•r ia • petented Falrchlld procet11.
Figure 3-1 Data sheets for the µA741. (Courtesy of Fairchild. Camera and Instrument
Corporation.)
88
. µA741A
ELECTRICAL CHARACTERISTICS: VS• t15 V, TA• 26"C unleu otherwise 1peelfltd.
CHARACTERISTICS (see deflnltionll CONDITIONS MIN TYP MAX UNITS

Input Offset Voltege Rs<500 0.8 '3.0 mV
Average Input Offset Volttge ['lrlft 15 1Nt•C
Input Offset Current 3.0 30 nA
-
Average Input Offset Current Drift 0.5 nA/•C
Input Sias Currant 30 80 nA
Power Supply Rejection Retio Vs• +20, -20; Vs· -20, +10V, Rs• 600 15 60 µVIV
Output Short Circuit Currant I 10 25 40 mA
-
Power Diulpetion vs- t20V 80 160 mW
Input Impedance vs- t20V 1.0 6.0 Mn
urge Signel Volttge Gein Vs• t20V, RL • 2k0, VouT • t15V 60 V/mV
Tr1nsient Response I Rise Tim, 0.25 0.8 ,..,
(UnltY Gain) I Overshoot 6.0 20
Bandwidth (Nott 4) .. .437 1.5
"
MHz
Slew Reta (Unity Gain) V1N • t10V 0.3 0.7 v,,..
The following specifications epply for -55°C <TA< +125°C
..
Input Offset Volttge 4.0 mV
-
Input Offset Current 70 nA
Input Blas Current 210 nA
Common Modeflejection Retlo vs- t20V, V1N • t15V, Rs• 500 BO 95 dB
Adjustment For Input Offset Voltege Vs• t20V 10 mV
Output Short Circuit Current 10 40 mA
l-55°C 165 mW
Power Dissipation vs- r
t20V +125°C 135 mW
Input Impedance Vs• t20V 0.5 l',10
IRL•10RO t16 v
Output Voltage Swing vs- t20V, 1 RL • 2k0 t15 v
Vs• t20V, RL • 2k0, VouT • t15V 32 V/mV
Large Signal "'.oltage Geln
vs- t5V, RL • 2k0, VouT • t2 V 10 V/mV
NOTES
1. ·R1tin9 1ppll11 tp 1mbl1nt temperoture1 up to 70°C. Above 70°C emblent d1r1te llneerly at 6.3mWl°C for the metel c,n, 8.3mWl°C for
the OIP end 7. lmWl°C for the Fletpek.
2. For eupply voltagr11I•• then t16V1 the atHolute maximum Input vol~ is equal to the 1upply voi;aee.
3. Short circuit mey be to ground or eltt,er eupply, Retlng eppllet to +1215 C c,11 temperoture or 715 C emblent temperature.
0.315
<I. ,Celculeted value from:,. BWIMHz) • RIM Time (µel
Figure 3-1 (Continued?
89
µA741
ELECTRICAL CHARACTERISTICS: VS• ot16 V, TA• 26°C unless otherwise specified.
CHARACTERISTICS (see definitions) CONDITIONS MIN TYP MAX UNITS

Input Offset Voltage Rs ..:; 10 kn· 1.0 6.0 mV
Input Offset Current 20 200 nA
Input Bios Current 80 600 nA
Input Resistance 0.3 2.0 MO
Input Cepacihnce 1.4 pF
Offset Voltage Adjustment Range t15 mV
Large Signal Voltage Gain RL > 2 kn, voor - t10 V 50,000 200,000
Output Resistance 76 n
Output Short Circuit Current 26 · mA
Supply Curn,nt 1.7 2.8 mA
Power Consumption 60 8!5 mW
Transient Reiponse Rite time 0.3 Ill

(Unity Gain) V1N • 20 mV, RL • 2 kn.cl<; 100 pF
Owrshoot 5.0
SI-Rate RL > 2 kn 0.5 "
V/111
The following specifications 1pply for -6s"C <;TA<; +126°C:

Input Offset Voltege Rs..:; 10 kn 1.0 6.0 mV
TA•+126"C '7.0 200 nA
Input Offset Current
TA·-ss0c 86 600 nA
TA •+12s0c 0.03 0.6 µA
Input Bias Current
TA•-ss0c 0.3 1.5 llA
Input Voltage Range t12 t13 v
Common Mode Rejectior; F- Rs..:; 10 kn 70 90 dB
Supply Voltage Rejection Ratio Rs..:; 10 kn 30 150 µVIV
Large Signal Voltage Gain RL > 2 kn, vour • ±10 V 26,000
Output Voltage Swing

RL > 10 kn ±12 tT4 v
RL > 2 kn t1Q ±13 v
TA •+12s0c 1,6 2.6 mA
Supply Curr1nt
TA·-ss0c 2.0 3.3 mA
TA•+12pC · 45 75 mW
Po-r Consumption
TA•-56°C 60 100 mW
TYPICAL PERFORMANCE CURVES FOR µA741A AND µA741
OPEN LOOP VOLTAGE GAIN OUTPUT VOLTAGE SWING INPUT COMMON MODE
AS A FUNCTION OF AS A FUNCTION OF VOLTAGE RANGE AS A
"'
SUPPLY VOLTAGE
•..
SUPPLY VOLTAGE
..
FUNCTION OF SUPPLY VOLTAGE
-,,"t,,.,•ltft .wcu.,•m"t
.-
... • ·is·c
' ~,,.... i.--- .. .. ....... / .., .. /

/
~
............. .," iI : /
/ /
v /
i •
)"
I
. v ./
/
I
/
II lo" / I
i
'
.. .. • I
•
SUH\Y'ICl..lAtl • ! V
. • I
• ..
SUffl.T WClfMI •IV
•
Figure 3-1 (Continued)
90
µA741E
ELECTRICAL CHARACTERISTICS: VS• ±16 V, TA~ 25°C unless otherwise specified.
CHARACTERISTICS lsee definitions) CONDITIONS MIN TYP MAX UNITS

Input Offset Voltage Rs< son 0.8 3.0 mV
Average Input Offset Voltage Drift 15 µV/•C
Input Offset Current 3.0 JO nA
Average Input Offset Current Drift 0.5 nA/°C
Input Bias Current JO 80 nA
Power Supply Rejection·Ratio vs· +10. -20; Vs= +20, -1ov. Rs= son · 15 50 µVIV
Output Short Circuit Current
Power Dissipation vs- ±20V .
. 10 25
80
40
150
mA
mW
Input I mpedanoe Vs c ±20V 1.0 6.0 Mn
Large Signal Voltage Gain Vs• ±20V, AL= 2k0, vour = ±t5V 50 V/mV
Transient Response I Rise Time 0.25 0.8 us
!Unity Gain) I Overshoot 6.0 20 %
Bandwidth INote 4) .437 1.5 MHz
Slel)I Rate I Unity Gain) V1N = ±10V. 0.3 0.7 V/µs
The following specifications epply for 0° C < TA < 70° C
Input Ofhet Voltage 4.0 mV
Input Bias Current 210 nA
~mmon Mode Rejection Ratio Vs •_±20V, V1N = ±15V, Rs= son 80 95 dB
Adjustment For Input Offset Voltage Vs• t20V 10 mV
Output Short Circuit Current 10 40 mA
Power Dissipation Vs• ±20V 150 mW
Input lml)edanoe vs- ±20V 0.5 Mn
I AL c ioen ±16 v
Output Voltage Swing vs· ±2ov.1
AL =2kn ±15 v
vs- ±20V, AL• 2kn, vour • :t 15V 32 V/mV
Large Sl~el Voltage Gain
Vs· ±5V, AL· 2kn, vour • ,2 v 10 V/mV
EQUIVALENT CIRCUIT INVERTING INPUT
NON·
INVERTING
INPUT
OFFSET
NULL
OFFSET
NULL
Figure3-1 (Continued)
91
µA741C
ELECTRICAL CHARACTERISTICS: Vs• t15 V, TA• 25°C unlfflotherwl• apeclfied.
CHARACTERISTICS (- definitions) CONDITIONS MIN TYP MAX UNITS

Input Offset Voltage Rs .. 10 kn 2.0 8.0 mV
Input Offset Current 20 200 nA
Input Bies Current 80 500 nA
Input Resistance 0.3 2.0 Mn
Input Cepacitance- 1.4 pF
Offset Voltlll' Adjustment Aenge t15 mV
1nput Voltage R1nge t12 ~13 v
Common Mode R~ fletio Rs.;; 10 kn 70 90 dB
Supply Voltage Rejection Ratio Rs..;; 10 kn 30 160 JJ>VIV
Large Sign1I Voltage Gain RL > 2 kn, vour • t10 V 20,000 200.000
Output Voltage Swing
AL> 10 kn t12 t14 v
RL > 2 kn t10 t13 v
Output Resistance 75 n
Output Short Circuit Current ·25 mA
Supply Current 1.7 2.8 mA
Power Consumption 60 85 mW
Transient R"ponae
RiM time 0.3
(Unity Geinl
Overshoot
V1N • 20 mV, RL • 2 kn, CL..;; 100 pF
5.0 "''
Slew Rate AL> 2 kn 0.5 "'
V/JJ,I
The following specifications apply for 0°C..;; TA..;; +70°C:

Input Offset Voltage 7.5 mV
Input Bias Current 800 nA
urge Signal Voltage Gain AL> 2 kn, VoUT • t10 V 16,000
Output Voltage Swing AL> 2 kn t!O t13 v
TYPICAL PERFORMANCECURVES FOR µA741E AND µA741C
OPEN LOOP VOLTAGE GAIN OUTPUT VOLTAGE SWING INPUT COMMON MODE
AS A FUNCTION OF AS A FUNCTION OF VOLTAGE AANGi AS A
SUPPLY VOLTAGE SUPPLY VOLTAGE FUNCTION OF SUPPLY VOLTAGE
• •,.·n c • O"c,r,,-,a"c
11
• " ..... . "''•'""'' ~

.. ~.,,.. I-""
> "
!iiii .. /
,
/
..... t> _...I' /
a• :: "
'1 •
v ~ .. /
/
I' .
/
i / I II /
• e
L ., /
u /
v
,, ./
IO
o 1 4 • , a a "
w,'1.TYOUAQ·:v
" • 20 •
' • •' • D
•
SUffl.Y¥1l.rA••tV
92
TYPICAL PERFORMANCE CURVES FOR µA741A, µA741, µA741 E AND µA741C
POWER CONSUMPTION OPEN LOOP VOLTAGE GAIN OPEN LOOP PHASE RESPONSE
AS A FUNCTION OF AS A FUNCTION OF AS A FUNCTION OF
SUPPLY VOLTAGE FREQUENCY FREQUENCY
...
... -
,oo
,.,, _l,,.c
.. J <,
11s
'•
11,v
•1' c I\ Vs··'l!IY
'• • •11 C
v ...
<,
/
/
••'
-, \
/ ••' I <, ---r-..
/
/ '\ "'
0
.i-r ..
SU,,,1,.VVOI.TACil• •Y
.. ,. 10-1
I 10 IOD
flllOUlfrtCY. "'
\ .... ,oo 10,. 100. ....
INPUT OFFSET CURRENT INPUT RESISTANCE ANO OUTPUT RESISTANCE

AS A FUNCTION OF INPUT CAPACITANCE ASIA AS A FUNCTION OF
SUPPLY VOLTAGE FUNCTION OF FREQUENCY
,oo ... FREQUENCY
... i.u' ·-
, •• 11·c
... .,.,.., ·'n'"c
' I\
H .. ~ rr I '
I
'' ·', I I
~
•oo rlti -tr. ·t I
~
I
··~.~~~-~,--~~....,.~~~.. '•oo
II 'I I
.... I
fll(0Uf"(Y • Ml lfl(OUtlrolCY, "''
OUTPUT VOLTAGE SWING OUTPUT VOLTAGE SWING ABSOLUTE MAXIMUM POWER

AS A FUNCTION OF AS A FUNCTION OF DISSIPATION AS A FUNCTION
,. LOAD RESISTANCE
vs• .!,v
, ... •1' c
., ""
... i-
- FREQUENCY
.,., ,, ...
»t-1-++.....,-+++t-+--+-,...-+fa•nc
,.
It •
..
10,.U
...
OF AMBIENT TEMPERATURE
... r\.
I
/
I ,. ... »Al41AAHO
.. r••
~ " '\.
..
~ ,.
~
..
I
i ...
'
I
..--- '\.
: e= ,,
,-- ....., .. 11
.
.,A14t(
! "
J
~
=r •
i '
r "
.. '\.
,oo
...
101
I
01 OS 10
\.040 llll'STAIICI •
U
•n
,o 10 •,oo ...
JIIIIQVIHCY. "'
......... . M n , .. "'
INPUT NOISE VOLTAGE INPUT NOISE CURRENT
AS A FUNCTION OF A$ A FUNCTION OF BROADBAND NOISE FOR
. FREQUENCY FREQUENCY VARIOUS BANDWIDTHS
,00,---,-,...,..,.---,~,,...,..,..,..~---,~~~
;,,n
i i"
~i ,41• .--
r,
......_.................-H -+-++++-t
.......
.
0
:
i
~ till l-+-Hi-+-+ttt--+-H-tt--+-+ttt-t
~
i
i i
ltlllOUltlCV • l>f1
' 100
$0Ulll:CI IIUISTANCI •
... n
....
98
TYPICAL PERFORMANCE CURVES FOR µA741A AND µA741
INPUT BIAS CURRENl INPUT RESISTANCE OUTPUT SHORT~IRCUIT CURRENT

AS A FUNCTION OF AS A FUNCTION OF AS A FUNCTION 0 ..
AMBIENT TEMPERATURE AMBIENT TEMPERATURE AMBIENT TEMPERATURE
""' '" "
...
vs• .,,v J
I '
' i
.. ..,1 •• ,~ v
1 .,
.....
.........
I I r-,
I
I I i ' _.... .... r-,
' I i i .,..v v r-...
--
.........
r-, i I i
,
i "t- LL I I
0
... I "
I
. .. ... I ... " -ICI .,o
" . 100 l.C, ' 0·IO -JO
" . 100 ...
INPUT OFFSET CURRENT POWER CONSUMPTION FREQUENCY CHARACTERIITICI
AS A FUNCTION OF AS A FUNCTION OF . AS A FUNCTION OF
... _v(I .. ,\,., I

I
:
l
.., .. ,Av
I
:
.......
'
I
-~ i
" - .,.~ ......
............. ...... ...... ,? .. ·- ....,.
. ~ .......:..
I i .............
i
5I
IO
~ ....
"i..,,i:: ~
·~ ....
~~ i....
I I
. I i
... .,.
"
TIWIU,Tl,1,it
i
.. • C:
i
100 ·160
0I
-· -JO
.. ..
TIWIIIATUIIII - 'C
100 1tCI
TYPICAL PERFORMANCE CURVES FOR µA741E AND µA741C

INPUT BIAS CURRENT INPUT RESISTANCE INPUT OFFSET CURRENT
AS A FUNCTION OF AS A FUNCTION 0 .. AS A FUNCTION 0 ..
AMBIENT TEMPERATURE AMBIENT TEMPERATURE AMBIENT TEMPERATURI
10
..l=E:E::EPEE
• IOl---+-+--4--4---1--.---1
a
! 10!--..i:;=:-t--+-+----i--+----i
>-· ··-
i
:
··~-+--+---t--+--+--+---1
.
1
!
;
1
•f--+-t---+...;::~...i:::--+--i~-- ~--
8
-r---
f ,ot---+-+--+-+--+-+----1
i
.--.-.- .......-,......._...,-.....- ....- .....
·,
T(M,tllATUllll C: t
.....-1"-,-,.
. .,. ;'•tt
....._..,,_..__...,- .....- .....
Tllilli't.llATUfll- -e
·.~-1~,-. ,. . . ,. , -.,.,-~. . .,_.,--~.
TlwtHTUlll • 'C
"'"'j""
POWER CONSUMPTION OUTPUT SHORT CIRCUIT .:URRENT FREQUENCY CHARACTERISTICS

AS A FUNCTION OF AS A FUNCTION OF AS A FUNCTION OF
I "'
"1''10Y - • --
..
r---.. . . .
<,
<;
, ........... <,
.,......
i t---+---lf--+- -
",!---,~.-~,.-~,.-..__.._
....._ ... I
IO lO 40 SO IO ~ 10l040totD10
11wo ...,u111 c; T(WtU,fUlll • C ,u..,.,••n.1111 c
94
COMMON
RATIO
0
MODE REJECTION
OVERSHOOT TRANSIENT RESPONSE AS A FUNCTION OF
TRANSIENT RESPONSE TEST CIRCUIT
... FREQUENCY
"
..
j
,,111
,.,,....,.-
,,.v--
,; sTE ADY
STATE
. '\. .
vs·:,,...
f •ZS C
.
.. - RESPONSE I\
I
~
ii
. I
I
•ovr
•,
'\
"\.
I "'\
-
Yf!OV_ 20mV 2k
~
.i1tnj '•
•i·1'0,-
Ci•'tbtl
I\(
de
IOKIDllllllMDlM•
,.... ,.
1.0 I,) 1.1 ,')
flf:Qt.OC,. "'
FREQUENCY CHARACTERISTICS
AS A FUNCTION OF VOLTAGE OFFSET VOLTAGE FOLLOWER
SUPPLY VOLTAGE NULL CIRCUIT LARGE SIGNAL PULSE RESPONSE
~ vs '.l tN
,..,. n c
au,,.,,,
\
I
'""'" \
... >- \
-~ O»ID»«1».•10•to
flMC ..
TYPICAL APPLICATIONS
UNITY-GAIN VOLTAGE FOLLOWER NON-INVERTING AMPLIFIER
~ :[;:>· 0
OuT,VT
c: :~·
IHfl'Uf 111111
.i'7ii1
0
OUTPUT
R1N• 400 Ml'"! GAIN Al A2 BW AtN

C1N• 1 pF 10 1 kn 9kl1 100 kHz 400Mn
RouT < < 1 n 100 10011 9.9 kn 10 kHz 2BOMn
B.W. • 1 MHz 1000 100 n 99.9 kn 1 kHz 80Ml1
INVERTING AMPLIFIER CLIPPING AMPLIFIER
our,uT
GAIN Al R2 BW A1N
1 10 kn 10 kn 1 MHz 10 kn
EouT R2
10 1 kn 10 kri 100 kHz 1 kn --
E1N
•-if
Rl
I EouT I< Vz • 0.1 v
100 1 kn 100 kn 10 kHz 1 kn
1000 10011 100 kn 1 kHz 10011 where v z • Zener breekdown volteg•
95
TYPICAL APPLICATIONS (Cont'd)
SIMPLE INTEGRATOR SIMPLE OIFFERENTIATOR
'"""
IIlf 1•111.tU 1\/\T. rvV
IN,VT t• l t"I lJTI
'" 10,n ~ (10 111,.
OVTl"VT OUTl'VT
Al 1.1,n 'll ,o,n
dE1N
EouT • - R2C
dt
LOW DRIFT LOW NOISE AMPLIFIER HIGH SLEW RATE POWER AMPLIFIER
....
'""" OUTl'UT
Voltage Gain• 103

Input Offset Voltage Orih • 0.6 µV/°C
Input Offset Current Drift• 2.0 pA/°C
NOTCH FILTER USING THE µA741 AS A GYRATOR
NOTCH FREQUENCY AS A
. FUNCTION OF C ·1
Trim R3 such that .....

Al RJ I'--
R2 - 2 R4
r-;
.,,,n I"-
!',"-
"
a.au .... IO
CA,ACnoa c1 • "'
96
from one model to another. For instance, the 741A has the best tolerance (tightly
controlled parameters) and costs the most. At the other extreme, the 741C has the
worst tolerance and consequently costs the least. In this section we consider only the
741C op-amp specifications.
Generally, the information found on data sheets can be broken down into the
following groups:
1. At the top of the data sheet is a device number and a brief description of the
basic type of the device, such, as frequency-compensated· op-limp, low-power
op-amp, or /ow-cost programmable op-amp.
2. Next, a general description is given that includes the construction process of the
device, intended applications, and a list of the main features. ,,
3. Absolute maximum ratings for the proper operation of the device are then speci-' ·
fled. These ratings are limiting values of operating and environmental conditions
applicable to the device and should not be exceeded.
4. The pin configuration (connection diagram), package types, and order infor-
mation is given.
5. The internal schematic diagram (equivalent circuit) is shown.
6. Electrical characteristics and parameter values under specific conditions are
also given.
7. Typical performance curves such as voltage gain versus supply voltage, output
voltage swing as a function of frequency, and power consumption as a function
of temperature are provided.
8. Finally, typical applications and test circuits for the device are illustrated.
Let us now take a close look at the µA741C data sheets with reference to the
information outlined above.
1. The Fairchild 741 is an internally frequency compensated operational
amplifier.
2. The 741 is a monolithic IC constructed by a special process called "planer
epitaxial." It is suited for integrator, summing amplifier, voltage follower, and other
general feedback applications. The features of the 741 are as follows:
a. No external frequency compensation required

b. Short-circuit protection
c. Offset null capability
d. Large common-mode and differential voltage ranges
e. Low power consumption
f. No latch-up problem
3. Absolute maximum ratings are specified for supply voltage, input and
differential input voltages, storage and operating temperature ranges, soldering pin
temperature, and output short-circuit duration. Supply voltage and operating tem-
perature range are given for Models 741, 741A, 741C, and 741E, whereas internal
Sec.3-2 Interpreting a Typical Set of Data Sheets 97

power dissipation, storage temperature range, and soldering pin temperature are
listed for all package types: flat pack, metal can, and DIP. For safe and proper opera-
tion of the device, these ratings should not be exceeded even under the worst operating
conditions.
4. The 741 is available in ·all ·three package types: 8-pin metal can, 10-pin flat
pack, and 8- or 14-pin DIP. The pin diagram for all these packages is shown on the
data sheets. Order information is included for each package as well.
5. The equivalent circuit diagram illustrates the internal structure of the 741
op-amp. This diagram helps to clarify the capabilities and limitations of the op-amp.
Note that all the 741 models have the same equivalent circuit.
6. For the 741C, two sets of electrical. specifications are given. One set of
specifications applies at room temperature (TA) of 25°C, whereas the other set applies.
+
to the commercial temperature range .0 to 70°C. Since our main interest at this point
is in the definition and significance of such parameters rather than their values, we
shall discuss· the parameters at 25°C. These parameters are applicable at supply
. voltages + +
Vee = 15 V and - VEE = -15 V. The electrical parameters are defined
in the following paragraphs.
Input Offset Voltage. Input offset voltage is the voltage that must be applied
between the two input terminals of an op-amp to null the output, as shown in Figure
3-2. In the figure Vdci and Vd02 are de voltages and R, represents the source resistance.
We denote input offset voltage by V,a· This voltage Via could be positive or negative;
therefore, its absolute value is listed on the data sheet. For a 741C the maximum value
of V,a''is 6 mV de. The smaller the value of V,a, the better the input terminals are
matched. For instance, the 714C precision op-amp has V,a = 150 µV maximum.
+Vee= +15 V
v: = (V dcl - V dc2 )R
V dcl
dc2
t-:--'\NV',,..............___-1
Rs s
10 kS1
6
-Vee= -15 V
Figure 3-2 Defining input offset voltage Via, (Pin numbers for 8-pin mini DJP.)
Input Offset Current. The algebraic difference between the currents into the
inverting and noninverting terminals is referred to as input offset current L; (see
Figure 3-3). In the form of an equation,
(3-1)
where JB1 is the current into the noninverting input, IB2 the current into the inverting
input.
The input offset current for the 741C is 200 nA maximum. As the matching
between two input terminals is improved, the difference between IB1 and IB2 becomes
smaller; that is, the I., value decreases further. For instance, the precision op-amp
98 Interpretation of Data Sheets and Characteristics of an Op-Amp Chap. 3 ·

+Vee= +15 V
Figure 3-3 Defining input offset

-Vee =-15V current I,0•
714C has a maximum value of /10 equal to 6 nA, a dramatic improvement over older
technology.
Input Bias Current. Input bias current /8 is the average of the currents that
flow into the inverting and noninverting input terminals of the op-amp. In equation
form,
(3-2)
/8 = 500 nA maximum for the 741C, whereas 18 for the precision 714C is·±7 nA.
Note that the two input currents 181 and /82 are actually the ba:se currents of the
first differential amplifier stage.
Differential Input Resistance. Differential input resistance R1 (often referred
to as input resistance) is the equivalent resistance that can be measured at either the
inverting or non inverting input terminal with the other terminal connected to ground.
For the 741 C the input resistance is a relatively high 2 MO. However, for FET input
op-amps this value is amazingly large. For example, R1 = 1000 Gn (1012 0) for the
µAF771 FET input op-amp.
Input Capacitance. Input capacitance C1 is the equivalent capacitance that can
be measured at either the inverting or noninverting terminal with the other terminal
connected to ground. A typical value of C, is 1.4 pF for the 741 C. This parameter is
not listed on all op-amp data sheets.
Offset Voltage Adjustment Range. One of the features of the 741 family
op-amps is an offset voltage null capability. The 741 op-amps have pins 1 and 5
marked as offset null for this purpose. As shown in Figure 3-4, a 10-k!l potentiometer
can be connected between offset null pins 1 and 5, and the wiper of the potentiometer
can be connected to the negative supply - VEE· By varying the potentiometer, the
+Vee=+15V
-Vee=-15V Figure 3-4 Offset voltage adjustment

10 k.!'2 range.

output offset voltage (output voltage without any input applied) can be reduced to
zero volts. Thus the offset voltage adjustment range is the range through which
the input offset voltage can be adjusted by varying the 10-kn potentiometer. For the
741C the offset voltage adjustment range is ±15 mV. Very few op-amps have the
offset voltage null capability, some of these being the 301, 748, and 777. This means
that for most op-amps we have to design an offset voltage compensating network in
order to reduce the output offset voltage to zero. The design of such a network is
presented in Chapter 5.
Input Voltage Range. When the same voltage is applied to both input termi-
nals, the voltage is called a common-mode voltage Yem and the op-amp is said to be
operating in the common-mode configuration (see Figure 3-5). For the 741C the
range of the input common-mode voltage is ± 13 V maximum. This means that the
common-mode voltage applied to both input terminals can be as high as + 13 V or as
low as -13 V without disturbing proper functioning of the op-amp. In other words,
the input voltage range is the range of common-mode voltages over which the offset
specifications apply. Obviously, the common-mode configuration is used only for
test purposes to determine the degree of matching between the inverting and non-
inverting input terminals.
Common-Mode Rejection Ratio. The common-mode rejection ratio (CMRR)
is defined in several essentially equivalent ways by the various manufacturers.
Generally, it can be defined as the ratio of the differential voltage gain Ad to the
common-mode voltage gain Acm; that is,
CMRR = Ad (3-3)
Acm
The differential voltage gain Ad is the same as the large-signal voltage gain A which is
specified on the data sheets; however, the common-mode voltage gain can be deter-
mined from the circuit of Figure 3-5 using the equation
A = Vocm (3-4)
cm Vcm
where Vocm = output common-mode voltage

vcm = input common-mode voltage
Acm = common-mode voltage gain
Generally, the Acm is very small and Ad = A is very large; therefore, the CMRR
is very large. Being a large value, CMRR is most often expressed in decibels (dB).
For the 741 C, CMRR is 90 dB typically. Note that this value of CMRR is determined
under the test condition that the input source resistance R, < 10 k!l. In Figure 3-5
R, is assumed to be zero because most of the practical voltage sources have negligible
source resistances. 1
The higher the value of CMRR, the better is the matching between two input
terminals and the smaller is the output common-mode voltage. For the 714C precision
op-amp CMRR = 120 dB. This means that the 714C has a better ability to reject
common-mode voltages such as electrical noise than the 741 Candis preferred in noise
environments.
Interpretation of Data Sheets and Characteristicsof an Op-Amp Chap.3

+Vee= +15 V
±13 V vcm
-Vee= -15 V
Figure 3.5 Common-mode configuration
Supply Voltage Rejection Ratio: The change in an op-amp's input offset

voltage V,0 caused by variations in supply voltages is called the supply voltage rejection
ratio (SVRR). A variety of terms equivalent to SVRR are used by different manufac-
turers, such as the power supply rejection ratio .(PSRR) and the power supply sensitivity
(PSS). These terms are expressed either in microvolts per volt or in decibels. If we
denote the change in supply voltages by AV and the corresponding change in input
offset voltage by A V,0, SVRR can be defined as follows:
SVRR. = ~o (3-5)
For the 741C, SVRR = 150 µV/V. On the other hand, for the 714C,
SVRR = 20 log (; ;,) = 104 dB (3-6)

or, equivalently,
SVRR = 6.31 µV/V
This means that the lower the value of SVRR in microvolts/volt, the better for op-amp
I
performance. ·
Note that for the 741C (and most other op-amps) SVRR is measured for both
supply magnitudes increasing or· decreasing simultaneously, with R, ~ 10 kn.
However, there are some op-amps for which SVRR is separately specified as positive
SVRR for positive voltage and negative SV RR for negative supply voltage.
Large-Signal Voltage Gain. Since the op-amp amplifies difference voltage
between two input terminals, the voltage gain of the amplifier is defined as
It . _ output voltage
vo age gam - differential input voltage
that is,
(3-7)
Because output signal amplitude is much larger than the input signal, the voltage
gain is commonly called large-signal voltage gain. Under the test conditions RL > 2 kn
and V = ± 10 V (or 20 V peak to peak), the large-signal voltage gain of the 741 C is
0
200,000 typically (see Figure 3-6).

Outpui Vo./tageSwing. The output voltage swing V0max of the 741C is guar-
anteed to be between -13 and +
13 V for RL > 2 kO, that is, giving a 26-V peak-to-
peak undistorted sine wave for ac input signals. In fact, the output voltage swing
r
Sec. 3-2 Interpretinga Typical.Set of Data Sheets 101
+Vee= +15 V
3
6
">----~output
V0 = Av,d
RL~2k.!1
-Vee=-15V
Figure 3-6 Determining voltage gain.
indicates the values of positive and negative saturation voltages of the op-amp. The
output voltage never exceeds these limits for given supply voltages + Vee and - VEE.
Output Resistance. Output resistance R0 is the equivalent resistance that can
be measured between the output terminal of the op-amp and the ground ( or common
point). It is 75 n for the 741 C op-amp.
Output Short-Circuit Current. Nobody would deliberately want to short the
output terminal of the op-amp to ground, but if such an event were to happen acci-
dentally, the current through the short would certainly be much higher in value than
either IB or /10• This high current may damage the op-amp if it does not have .output
short-circuit protection. Recall, however, that the 741 family op-amps do have
short-circuit protection circuitry built in.
The short-circuit current /,c = 25 mA for the 741C op-amp. This means that the
built-in short-circuit protection is guaranteed to withstand 25 mA of current in
protecting the op-amp.
Supply Current. Supply current I, is the current drawn by the op-amp from
the power supply. This parameter is not given on most of the op-amp data sheets.
For the 741C op-amp the supply current/,= 2.8 mA.
Power Consumption. Power consumption Pc is the amount of quiescent power lt..,
(v·IA = 0 V) that must be consumed by the op-amp in order to operate properly. The
amount of power consumed by the 741C is 85 mW.
Transient Response. ·The response of any practically useful network to a given
input is composed of two parts: the transient and steady-state response. The transient
response is that portion of the complete response before the output attains some
fixed value. Once reached, this fixed value remains at that level and is, therefore,
·referred to as a steady-state value. The response of the network after it attains
.',1\t::~; •
a fixed
value is independent of time and is called the steady-state response. Unlike tn¢.~steac;fy..,
state response, the transient response is time-variant. The rise time and the perfeh~
of
overshoot are the characteristics of the transient response. The time required by the ·
output to go from zero to 90% of its final value is called the rise time. Conversely,
overshoot is the maximum amount by which the output deviates from the steady-state
value. Overshoot is generally expressed as a percentage.
The transient response test circuit for the 741 C as well as the response of this
test circuit for V10 = 20 m V de is included in the data sheets. The rise time is 0.3 µs
and overshoot is 5 % for the 741 C op-amp.
The transient response is one of the important considerations in selecting an
102 Interpretation of Data Sheets and Characteristics of an Op-Amp Chap. 3

op-amp in ac applications. In fact, the rise time is inversely proportional to the unity
gain bandwidth of the op-amp. This means that the smaller the value of rise time, the
higher is the bandwidth.
-
Slew Rate. Slew rate (SR) is defined as the maximum rate of change of output
voltage per unit of time and is expressed in volts per microseconds. In equation form,
SR= dV.,
dt maximum
V/µs (3-8)
Slew rate indicates how rapidly the output of an op-amp can change in response to
changes in the input frequency with'Input amplitude constant. The slew rate changes
with change in voltage gain and is normally specified at unity (+I) gain. The slew rate
of an op-amp is fixed, therefore, if the slope requirements of the output signal are
greater than the slew rate, then distortion occurs. Thus slew rate is one of the impor-
tant factors in selecting the op-amp for ac applications, particularly at relatively high
frequencies. One of the drawbacks of the 741 C is its low slew rate (0.5 V/ µs), which
limits its use in relatively high frequency applications, especially in oscillators,
comparators, and filters. The newer op-amps-LF35 l, µAF77 l, and M C3400 I-which
are direct replacements for 741, have a slew rate of 13 V/µs. In high-speed op-amps
especially the slew rate is significantly improved. For instance, the 318 has a slew rate
of 70 V/µs.
On the data sheets of some op-amps you may find additional electrical param-
eters that are related to their intended applications. These electrical parameters
include gain-bandwidth product, average temperature coefficients of input offset
voltage and current, long-term input offset voltage and current stability, and equiva-
lent noise voltage and current. Besides that, there is one more parameter that is
applicable to only dual and quad op-amps: channel separation.
Gain-Bandwidth Product. The gain-bandwidth product (BW) is the band-
width of the op-amp when the voltage gain is 1. Although for the 741-op-amp it is not
listed under electrical characteristics, from the open-loop voltage gain versus frequency
graph it can be found to be approximately 1 MHz. Equivalent terms for gain-band-
width product are closed-loop bandwidth, unity gain bandwidth, and small-signal
bandwidth. The newer op-amps LF351 ,nd MC34001, which are direct replacements
for the 741, have a gain-bandwidth product of 4 MHz.
· Average Temperature Coefficient of Input Offset Voltage ( and Current). These
parameters are also referred to as average input offset voltage or current drift. The
average temperature coefficient of input offset voltage is the average rate of change in
input offset voltage per unit change in temperature expressed as µV/°C. Similarly, the
average .temperature coefficient of input offset current is the average rate of change in
input offset current per unit change in temperature and is usually expressed as pAf°C.
Both of these parameters are generally given for the instrumentation and precision
type op-amps. For example, for the precision op-amp 714C, the average temperature
coefficient of input offset voltage f:.V, /AT = 0.5 µVf°C typically, and the average
0
temperature coefficient of input offset current A/10/ AT= 12 pAf°C.

Long-Term Input Offset Voltage ( and Current) Stability. A V, At is the average
0/
rate of change in input offset voltage per unit of time and is generally expressed as

µV/week. It is also referred to as input offset voltage drift with time. Similarly, D.!10/ !).(
is the average rate of change in input offset current per unit of time in pA/week.
Again, these parameters are normally given for instrumentation and precision-type
op-amps. For instance, the precision-type op-amp 714C has D.V10/M = 0.1 µV/week
typically. The value of D.!10/M is negligible for the 714C; hence it is not listed on the
data sheet.
Equivalent Input Noise Voltage and Current. Since electrical noise is random
in nature, it is expressed as a root-mean-square value. Standard industry practice is
to express the noise as a power density. The equivalent input noise voltage is, there-
fore, expressed as square voltage (V2/Hz) and the equivalent input noise current as
square noise current (A2/Hz). Using input noise voltage and input noise current versus
frequency curves given on the data sheets (see Figure 3-1), the minimum amount of
signal power that is necessary to overcome the noise signal and produce a measurable
output signal can be determined. As a general rule, the signal-to-noise ratio must
be at least larger than by a factor of 10.
Channel Separation. This parameter is specified in the data sheets of dual and
quad (four) op-amps such as the µAF772 and µAF774, respectively. It is a measure of
the amount of electrical coupling between op-amps that are integrated on the same
chip. Because of the physical closeness of op-amps in dual and quad packages, when
a signal is applied to the input of only one op-amp, some signal will appear at the
output of other op-amps. The amplitude of these output signals is approximately the
same and can be calculated using channel separation and a given input signal. Channel
separation is also called amplifier-to-amplifier coupling.
The 774/348 is a true quad 741 and has a channel separation of -120 dB. This
means that if a signal is applied to one of the op-amps, the signal at the outputs of
the undriven op-amps will be at least 120 dB (equivalent to a ratio of 106) below the
signal output of the driven op-amp.
Thus as more and more data are made available on op-amp characteristics, it
becomes easier to select a proper op-amp for a desired application.
A list of parameters that should be considered for ac and de applications is given
in Table 3-1. Depending on the application, a designer sets priorities among these
parameters and then selects a suitable op-amp for his or her needs.
7. Typical performance curves included on the data sheets of the 741 C are the
graphs of electrical parameters that are affected by mainly three factors:
a. Change in supply voltage
b. Change in operating frequency
c. Change in temperature
The graphs of parameters that are ajfected by each of these factors are as listed
below:
Supply-voltage-dependent parameters. Voltage gain, output voltage swing, input
common-mode voltage range, power consumption, and input offset current.
Frequency-dependent parameters. Voltage gain, input resistance, output resis-
tance, output voltage swing, input noise voltage and noise current, and CMRR.

TABLE 3-1 PARAMETER EVALUATION FOR AC
AND DC APPLICATIONS
For ac applications, For de applications,

consider: consider:
Input resistance Input offset voltage

and input offset current
Output resistance Input resistance
Large-signal voltage gain Output resistance
Output voltage swing I Power supply rejection
ratio
Transient response Large-signal voltage gain
Slew rate Output voltage swing
Gain-bandwidth product Average input offset
voltage and current drifts
Average input offset voltage Long-term input offset
and current drifts voltage stability
Long-term input offset
voltage stability
Equivalent input noise
voltage and current
Temperature-dependent parameters. Absolute maximum power dissipation,

input bias current, input offset current, power consumption, input resistance,
output short-circuit current, transient response, and gain-bandwidth product.
In short, the information obtained from the performance curves _can be used to
improve the op-amp's performance.
8. Finally, a collection of amplifier applications with circuit diagrams is included
on the data sheets. These are the applications in which the op-amp is guaranteed to
perform satisfactorily. Such applications of the 741C include voltage follower,
inverting and noninverting amplifiers, clipping amplifier, simple integrator, and differ-
entiator, and others.
We have seen that a wide range of important information, including a pin
diagram, electrical characteristics, and applications, is included on the data sheets of an
op-amp. To get the most out of this device, it is essential to refer to the data sheets.
3-3 THE IDEAL OP-AMP
An ideal op-amp would exhibit the following electrical characteristics:
1. Infinite voltage gain A.

2. Infinite input resistance R,, so that almost any signal source can drive it and
there is no loading of the preceding stage.
3. Zero output resistance R0, so that output can drive an infinite number of other
devices.
Sec. 3-3 The Ideal Op-Amp 105

4. Zero output voltage when input voltage is zero.
5. Infinite bandwidth, so that any frequency signal from O to oo Hz can be amplified
without attenuation.
6. Infinite common-mode rejection ratio, so that the output common-mode noise
voltage is zero.
7. Infinite slew rate, so that output voltage changes occur simultaneously with
input voltage changes.
There are practical op-amps that can be made to approximate some of these
characteristics using a negative feedback arrangement. In particular, the input
resistance, output resistance, and bandwidth can be brought close to ideal values by
this method, Chapter 4 includes a discussion of negative feedback configurations.
3-4 EQUIVALENT CIRCUIT OF AN OP-AMP

Figure 3-7 shows an equivalent circuit of an op-amp. This circuit includes important
values from the data sheets, namely A, R,, and R0• Note that Av,., is an equivalent
Thevenin voltage source and R0 is the Thevenin equivalent resistance looking back
into the output terminal of an op-amp.
+Vee
Noninverting V1
input o---~-+-....,
r--"""VINv---~--,o Output
Inverting V2 Yo=Avid
input o----'--+-_,
Figure 3-7 Equivalent circuit of an op-amp.
The equivalent circuit is useful in analyzing the basic operating principles of

op-amps and in observing the effects of standard feedback arrangements. For the
circuit shown in Figure 3-7, the output voltage is
V0 = Av,., = A(v1 - V2) (3-9)
where A = large-signal voltage gain
vu · difference (differential) input voltage
v1 = voltage at the noninverting input terminal with respect to ground
v2 = voltage at the inverting terminal with respect to ground
106 Interpretation of Data Sheets and Characteristics of an Op-Amp Chap.3

Equation (3-9) indicates that the output voltage v0 is directly proportional
to the algebraic difference between the two input voltages. In other words, the op-amp
amplifies the difference between the two input voltages; it does not amplify the input
voltages themselves. For this reason the polarity of the output voltage depends on
the polarity of the difference voltage.
3-5 IDEAL VOLTAGE TRANSFER CURVE

I
Equation (3-9) is the basic op-amp equation, in which the output offset voltage is
assumed to be zero. This equation is useful in studying the op-amp's characteristics
and in analyzing different circuit configurations that employ feedback. The graphic
representation of this equation is shown in Figure 3-8, in that the output voltage v0
is plotted against input difference voltage v,d, keeping gain A constant.
Note, however, that the output voltage cannot exceed the positive and negative
saturation voltages. These saturation voltages are specified by an output voltage
swing rating of the op-amp for given values of supply voltages. This means that the
output voltage. is directly proportional to the input difference voltage only until it
reaches the saturation voltages and that thereafter output voltage remains constant,
as shown in Figure 3-8.
The curve shown in Figure 3-8 is called an ideal voltage transfer curve, ideal
because output offset voltage is assumed to be zero. In normal op-amp use (with
negative feedback), this voltage is near zero and is ignored for simplicity of calculation.
Notice that the curve is not drawn to scale. If drawn to scale, the curve would be
almost vertical because of the very large values of A.
Positive saturation
voltage+ V ut < +V cc
Slope= A
-v1c1
Negative saturation
voltag~-v .. 1 <-VEE Figure 3-8 Ideal voltage transfer
curve.
3-6 OPEN-LOOP OP-AMP CONFIGURATIONS
In the case of amplifiers the term "open-loop" indicates that no connection, either
direct or via another network, exists between the output and input terminals. That is,
the output signal is not fed back in any form as part of the input signal, and the
"loop" that would have been formed with feedback is open.
Sec. 3-6 Open-Loop Op-Amp Configurations 107

When connected in open-loop configuration, the op-amp simply functions as a
high-gain amplifier. There are three open-loop op-amp configurations:
1. The differential amplifier
2. The inverting amplifier
3. The noninverting amplifier
These configurations are classed according to the number of inputs used and the
terminal to which the input is applied when a single input is used.
3-6,.1 The Differential Amplifier
Figure 3-9 shows the open-loop differential amplifier in which input signals Vint and
V1n2 are applied to the positive and negative input terminals. Since the op-amp ampli-
fies the difference between the two-input signals, this configuration is called the
differential amplifier.
+Vee
>-----<lv0= A(vinl -v1n2l
Figure 3-9 Open-loop differential

amplifier.
The op-amp is a versatile device because it amplifies both ac and de input

signals. This means that Vint and v1n2 could be either ac or de voltages. The source
· resistances R1n1 and R1n2 are normally negligible compared to the input resistance R,.
Therefore, the voltage drops across these resistors can be assumed to be zero, which
then implies that v1 = V1n1 and v2 = v1n2• Substituting these values of v1 and v2 in
Equation (3-9), we get
V0 = A(V1n1 - V1n2)
Thus, as expected, the output voltage is equal to the voltage gain A times the difference
between the two input voltages. Also notice that the polarity of the output voltage is
dependent on the polarity of the input difference voltage (v1n1 - V1n2). In open-loop
configurations, gain A is commonly referred to as open-loop gain.
I
3-6.2 The Inverting Amplifier
In the inverting amplifier only one input is applied and that to the inverting input
terminal. The noninverting input terminal is grounded (refer to Figure 3-10). Since
v1 = 0 V, and v2 = Vin from Equation (3-9),
v0 • -Av1n
108 Interpretation of Data Sheets and Characteristics of ar Op-Amp Chap. 3

Figure 3-10 Inverting amplifier.
The negative sign indicates that the output voltage is out of phase with respect to
input by 180° or is of opposite polarity. Thus in the inverting amplifier the input
signal is amplified by gain A and j.s also inverted at the.output.
3-6.3 The Noninverting Amp/Hier
Figure 3-11 'shows the open-loop noninverting amplifier. In this· configuration the
input is .applied ·to the noninverting input terminal,· and· the .inverting terminal is
connected to ground.
In the circuit of Figure 3-11, v1 ·. V1.a and v2 = 0 V. Therefore,. according to
· ..... Equation (3-9), .· . · . . ·.. . . · ·
. · .. ~ .
'•
. ' v = Av,_:
•,' 0 '. - . .
This means that the output voltage is larger than. the 'iri~t voltage by gain A and is in
phase with the input signal.
In all three open-loop configurations any input' signal (differential or single)
that is only slightly greater than zero drives the output to saturation level. This results
from the very high gain (A) of the op-amp. Thus, when operated open-loop, the output
of the op-amp is either negative or positive saturation or switches between positive
and negative saturation levels. For this reason the open-loop op-amp configurations
are not used in linear applications. ·
+Vex;
v,
Yid v0= Av;0
V2
RL2:2kn
-VEE
Figure 3-11 Noninverting amplifier.
Sec. 3-6 Open-Loop O'p-Amp Configurations 109

Example 3-1
Determine the output voltage in each of the following cases for the open-loop differ-
ential amplifier of Figure 3~9:
(a) v101 = 5 µV de, V102 = -7 µV de
(b) v1o1 = 10 mV rms, v1o2 = 20 mV rms
The op-amp is a 741 with the following specifications: A = 200,000, R, = 2 MQ,
R0 = 75 Q, +Vee= +15 V, -VEE= -15 V, and output voltage swing= ±14V.
Solution
(a) By Equation (3-9):
v = 200,000[(5)(10-6) - ( - 7)(10-6)]
0 = 2.4 V de
Remember that v0 = 2.4 V de with the assumption that the de output voltage is zero
when the input signals are zero.
(b) Equation (3-9) is valid for both ac and de input signals. However, the restriction on
ac input signals is that they must be of the same frequency (see Figure 3-12). By
Equation (3-9):
v 0 = 200,000((10)(10-3) - (20)(10-3)] = -2000 V rms
Thus the theoretical value of output voltage v0 = -2000 V rms. However, the op-amp
saturates at ±14 V. Therefore, the actual output waveform will be clipped as shown
in Figure 3-12. This nonsinusoidal waveform is unacceptable in amplifier applications.
10y2 mV
O V ----------------
-10v'2ni"V
.,i
-14 V peak ......,_ ... Fi~e 3-ll Waveformsfor

Example 3-1.
The normal solution to this problem is to use a negative feedback which is discussed
in Chapter 4.
110 kita;pretation of Data Sheets and Characteristics of an Op-Amp Chap.3

Example 3-2
Determine the output voltage for the inverting amplifier shown in Figure 3-10, if
(a) v,11 = 20 mv de
(b) v111 = -50 µV peak sine wave
Assume that the op-amp is a 741.
Solution. By Equation (3-9):
(a) v0 = -Av1 = -(2)(103)(20)(10-3)
11 = -4000 V
This is the theoretical value; the actual value ,'l'ill be a negative saturation voltage of
-14 v.
(b) v0 = -'Av1n = -(2)(103)(-50)(10-6) = 10 V peak
This means that the output is a positive sine wave, since it is less than the output voltage
swing of ± 14 V or 28 V peak to peak.
SUMMARY
t. The manufacturers supply data sheets for the !Cs they produce. These data sheets include
absolute maximum ratings, electrical characteristics, pin diagrams, equivalent circuits,
intended applications of the devices, and more. To get most use out of these sheets, a
proper interpretation of them is essential.
2. Generally, the information found on the op-amp data sheets can be broken down into the
following groups: device type, absolute maximum ratings, connection diagram, equivalent
circuit, electrical characteristics, and typical applications.
3. An ideal op-amp has infinity voltage gain, input resistance, CMRR, and slew rate, together
with zero output resistance and output offset voltage.
4. The equivalent circuit is useful in analyzing the basic'operating principles of an op-amp
and in observing the effects of feedback arrangements.
5. The voltage transfer characteristic curve of an op-amp is the graph of output voltage versus
differential input voltage.
6. Differential, inverting, and noninverting amplifiers are the three open-loop op-amp con-
figurations in which the output signal is not fed back in any form as part of the input·
signal. When operated open-loop, generally the op-amp's output is either positive or nega-
tive saturation or switches· between positive and negative saturation levels. This action is
undesirable in linear applications; hence open-loop configurations are rarely used in linear
applications.
QUESTIONS
3-1. What information is contained in the typical op-amp data sheet?

3-2. Explain why proper interpretation of op-amp data sheets is important.
3-3. Define the following electrical parameters: input offset. voltage, input resistance, CMRR,
output voltage swing, slew rate.
3-4. List the parameters that should be considered for ac and de applications.

3-5. What are the three factors that affect electrical parameters of an op-amp?
3-6. What are the characteristics of an ideal op-amp?
3-7. What is a voltage transfer curve of an op-amp?
3-8. List three open-loop op-amp configurations.
3-9. Explain why open-loop op-amp configurations are not used in linear applications.
PROBLEMS
3-1. For the µAF771 op-amp, PSRR = 70 dB minimum. What is the numerical value of
PSRR?
3-2. For a given op-amp, CMRR = 105 and differential gain Ad= 105, Determine the
common-mode gain Acm of the op-amp.
3-3. The output voltage of a certain op-amp circuit changes by 20 V in 4 µs. What is its
slew rate?
3-4. In the differentialamplifier of Figure 3-9, v1n1 = 2.1 V de and v1n2 = 2.0 V de. Deter-
mine the output voltage va. Assume that the op-amp is a 741, with supply voltages =
±15V.
3-5. Repeat Problem 3-4 for the following values of inputs: v1n1 = -25 µV rms and v1n2
= 20µVrms.
3-6. Referring to the circuit of Figure 3-10, determine Va if v1n = -15 µV de. Assume that
the op-amp is a 741 and that supply voltages = ±15 V.
3-7. Repeat Problem 3-6 for V1n = -10 µV rms.

4
An Op-Amp
with Negative Feedback
- · --- ..--,,-, .. __..

-,,-, .... ,,. ,_,,, .. _, .. .._,._.,,, . ._........ _ ........-........ - ........ - ........ .... ..... _........ -....·--, ....... -, ....... _.... ,-- ....
,,, ,_ _,,,, _,,,
4-1 INTRODUCTION
In Chapter 3 the characteristics of the op-amp and interpretation of its parameters

are discussed. Recall that clipping occurs in open-loop configurations when the
output attempts to exceed the saturation levels of the op-amp. In other words, because
the open-loop gain of the op-amp is very high, only the smaller signals (of the order
of microvolts or less) having very low frequency may be amplified accurately without
distortion, However, signals this small are very susceptible to noise and almost
impossible to obtain in the laboratory.
Besides being large, the open-loop voltage gain of the op-amp is not a constant.
The voltage gain varies with changes in temperature and power supply as well as mass
production techniques. The variations in voltage gain are relatively large in open-loop
op-amps in particular, which makes the open-loop op-amp unsuitable for many
linear applications. In most linear applications the output is proportional to the input
and is of the same type.
In addition, the bandwidth (band of frequencies for which the gain remains
constant) of most open-loop op-amps is negligibly small-almost zero. For this reason
the open-loop op-amp is impractical in ac applications. For instance, the open-loop
bandwidth of the 741 C is approximately 5 Hz. (Refer to the voltage gain versus
frequency graph supplied on the data sheets.) However, in almost all ac applications
a bandwidth larger than 5 Hz is needed.
For the reasons stated above the open-loop op-amp is generally not used in
linear applications. Nevertheless, in certain applications the open-loop op-amp is
purposely used as a nonlinear device; that is, a square-wave output is obtained by
113
deliberately applying a relatively large input signal. Open-loop op-amp configurations
are most suitable in such applications.
We can select as well as control the gain of the op-amp if we introduce a modifi-
cation in the basic circuit. This modification involves the use of feedback; that is, an
output signal is fed back to the input either directly or via another network. If the
signal fed back is of opposite polarity or out of phase by 180° (or odd integer multiples
of 180°) with respect to the input signal, the feedback is called negative feedback. An
amplifier with negative feedback has a self-correcting ability against any change in
output voltage caused by changes in environmental conditions. Negative feedback
is also known as degenerative feedback because when used it degenerates (reduces)
the output voltage amplitude and in turn reduces the voltage gain.
On thy other hand, if the signal fed back is in phase with the input signal, the
feedback is called positive feedback. In positive feedback the feedback signal aids the
input signal. For this reason it is also referred to as regenerative feedback. Positive
feedback is necessary in oscillator circuits.
When used in amplifiers, negative feedback stabilizes the gain, increases the
bandwidth, and changes the input and output resistances. Of course, the price paid
for these improvements is reduced voltage gain. Other benefits of negative feedback
include a decrease in harmonic or nonlinear distortion and reduction in the effect of
input offset voltage at the output. Negative feedback also reduces the effect of varia-
tions in temperature and supply voltages on the output of the op-amp.
Negative feedback and its effect on the performance of an op-amp are the
subject of this chapter. First the block diagrams for different op-amp configurations
using negative feedback are presented. Then specific arrangements of these feedback
configurations are studied in more, depth.
4-2 BLOCK DIAGRAM REPRESENTATION OF FEEDBACK

CONFIGURATIONS
An op-amp that uses feedback is called a feedback amplifier. A feedback amplifier is

sometimes referred to as a closed-loop amplifier because the feedback forms a closed
loop between the input and the output. A feedback amplifier essentially consists of
two parts: an op-amp and a feedback circuit. The feedback circuit can take any form
whatsoever, depending on the intended application of the amplifier. This means that
the feedback circuit may be made up of either passive components, active components,
or combinations of both. This chapter, in order to develop the basic feedback concepts,
presents only purely resistive feedback circuits.
A closed-loop amplifier can be represented by using two blocks, one for an
op-amp and another for a feedback tircuit. There are four ways to connect these two
blocks. These connections are classified according to whether the voltage or current is
fed back to the input in series or in parallel, as follows:
1. Voltage-series feedback
2. Voltage-shunt feedback
114 An Op-Amp with Negative Feedback Chap. 4

3. Current-series feedback
4. Current-shunt feedback
The four types of configurations are illustrated in Figure 4-1. In Figure 4-l(a)
and (b) the voltage across load resistor RL is the input voltage to the feedback circuit.
The feedback quantity (either voltage or current) is the output of the feedback circuit
and is proportional to the output voltage. On the other hand, in the current-series
and current-shunt feedback circuits of Figure 4-l(c) and (d), the load current iL
(output current) flows into the feedback circuit. The output of the feedback circuit is
the feedback quantity (either voltage or current), which is proportional to the load
current iL.
Op-amp Vo AL Vin
+
-
- t-
j in
i,
la
Op-amp Vo AL
Feedback Feedback
circuit circuit
(a)
-- (b)
'---0-p-·a_m_p~
-~j L
Feedback Feedback
circuit circuit
(cl (d)
Figure 4-1 Feedback configurations. (a) Voltage-series. (b) Voltage-shunt.

(c) Current-series. (d) Current-shunt. Arrows indicate the signal flow directions.
Note that in all four of these configurations the signal direction through the
op-amp is from the input to output. On the other hand, in the ideal case the signal
direction through the feedback circuit is exactly opposite: from output to input.
The voltage-series and voltage-shunt feedback configurations are important
because they are most commonly used. An in-depth analysis of these two configura-
tions is presented here, computing voltage gain,. input resistance, output resistance,
and bandwidth for each. The other two configurations are not discussed in this chapter.
However, the interested reader may analyze the latter using the same procedures as
illustrated for the first two configurations.
Sec.4-2 Block Diagram Representation of Feedback Configurations 115

f
4-3 VOLTAGE-SERIES FEEDBACK AMPLIFIER
The schematic diagram of the voltage-series feedback amplifier is shown in Figure

4-2. The op-amp is represented by its schematic symbol, including its large-signal
voltage gain A, and the feedback circuit is composed of two resistors R1 and R,.
The circuit shown in Figure 4-2 is commonly known as a noninverting amplifier
with feedback (or closed-loop noninverting amplifier) because it uses feedback, and the
input signal is applied to the noninverting input terminal of the op-amp.
+vee
v,d
_...
+
r--------,
+I RF
v r II R1
_I
Figure 4-2 Voltage-series feedback
I amplifier (or noninverting amplifier
r-Feedback
L .1 circuit with feedback).
Before proceeding, it is necessary to define some important terms for the

voltage-series feedback amplifier of Figure 4-2. Specifically, the voltage gain of the
op-amp with and without feedback, and the gain of the feedback circuit are defined
as follows:
open-loop voltage gain (or gain without feedback) A =
v,,
Va
closed-loop voltage gain (or gain with feedback) A,= Va

VIA
gain of the feedback circuit
4-3.1 Negative Feedback
Referring to the circuit of Figure 4-2, Kirchhoff's voltage equation for the input loop
is
(4-1)
where v1a. = input voltage
v1 = feedback voltage
v« = difference voltage
Recall, however, that an op-amp always amplifies the difference input voltage
v"'. From Equation (4-1), this difference voltage is equal to the input voltage VIA
minus the feedback voltage v1. In other words, the feedback voltage always opposes
the input voltage (or is out of phase by 180° with respect to the input voltage); hence
the.feedback is said to be negative.

Returning now to the analysis of the voltage-series feedback amplifier, we
should note that it will be performed by computing closed-loop voltage gain, input
and output resistances, and the bandwidth.
4-3.2 Closed·Loop Voltage Gain
As defined previously, the closed-loop voltage gain
However, by Equation (3-9),

Va = A(v1 - v2)
Referring to Figure 4-2, we see that
Vi= Vin
- - R1Va
Vz - v, - R1 + RP
Therefore,
Rearranging, we get
Thus
AP = ~= A(Ri +
RP) (exact) (4-2)
Vin R1 +RP +
AR1
Generally, A is very large (typically 10'). Therefore,
AR1 ~ (R1 + R,) and (R1 + R, + AR 1) ,.._, AR1
Thus
(ideal) (4-3)
Equation (4-3) is important because it shows that the gain of the voltage-series
feedback amplifier is determined by the ratio of two resistors, R1 and Rp. For instance,
if a gain of 11 is desired, we can then choose R1 = 1 kn and RF= 10 kn or R1 =
100 n and RF = 1 kn. In other words, in setting the gain the ratio of R1 and RF is
important and not the absolute values of these resistors. As a general rule, however,
all external component values should be less than 1 Mn so that they do not adversely
affect the internal circuitry of the op-amp. This is especially true for older-generation
!Cs such as the 709 and 741.
Another interesting result can be obtained from Equation (4-3). As defined
previously, the gain of the feedback circuit (B) is the ratio of v1 to Va. Referring to
Figure 4-2, this gain is
(4-4)
Sec. 4-3 Voltage-Series Feedback Amplifier 117

Comparing Equations (4-3) and (4-4), we can conclude that
I
AP = 7i (ideal) (4-5)
This means that the gain of the feedback circuit is the reciprocal of the closed-loop
voltage gain. In other words, for given R1 and RP the values of AP and Bare fixed.
Besides that, Equation (4-5) is an alternative to Equation (4-3), and its simpler form
makes it easier to remember.
Finally, the closed-loop voltage gain AP can be expressed in terms of open-loop
gain A and feedback circuit gain Bas follows. Rearranging Equation (4-2), we get
A(R, + RP)
A p-- R, + RP
R. +RF+ AR.
R1 + RF R1 + RF
Using Equation (4-4) yields
A
AF= 1 + AB (4-6)
where Ap = closed-loop gain

A = open-loop gain
B = gain of the feedback circuit
AB = loop gain
A one-line block diagram of Equation (4-6) is shown in Figure 4-3. This block diagram
illustrates a standard form for representing a system with feedback and also indicates
the relationship between different variables of the system. In short, the block diagram
approach helps to simplify the analysis of complex closed-loop networks, particularly
if they are composed of nonresistive feedback circuits.
Summing junction
Figure 4-3 Block diagram

representation of noninverting amplifier
B
with feedback.
4-3.3 DifferenceInput VoltageIdeallyZero
Let us reconsider Equation (3-9), which can be rewritten as )
since A is very large (ideally infinite),

(4-7a)
That is,
v1 ~ v2 (ideal) (4-7b)

Equation (4- 7b) says that the voltage at the noninverting input terminal of an op-amp
is approximately equal to that at the inverting input terminal provided that A is very
large. This concept is useful in the analysis of closed loop op-amp circuits. For example,
ideal closed-loop voltage gain [Equation (4-3)] can be obtained using the results above
as follows. In the circuit of Figure 4-2,
R1Vo
,= R1 +RP
Substituting these values of v1 and v2 in Equation (4-7b), we get
That is,
4-3.4 Input Resistance with Feedback
Figure 4-4 shows a voltage-series feedback amplifier with the op-amp equivalent
circuit. In this circuit R, is the input resistance (open-loop) of the op-amp, and R,p
is the input resistance of the feedback amplifier. The input resistance with feedback is
defined as
+
Vin ......
Figure 4-4 Derivation of input resistance with feedback.

However,
and
Therefore,
-AR Vin
- 'Av1n/(I + AB)
= R,(I + AB). (4-8)
This means that the input resistance of the op-amp with feedback is (I + AB) times
that without feedback.
4-3.6 Output Resistance with Feedback
Output resistance is the resistance determined looking back into the feedback amplifier
from the output terminal as shown in Figure 4-5. This resistance can be obtained by
using Thevenin's theorem for dependent sources. Specifically, to find output resistance
with feedback RaP, reduce independent source V1n to zero, apply an external voltage
va, and then calculate the resulting current ia. In short, the RaP is defined as follows:
<t
(4-9a)
Writing Kirchhoff's current equation at output node N, we get

t, = i, + t,
since R, + R II R, » Ra, i »
1 0 ib. Therefore,
Figure 4-5 Derivation of output resistance with feedback.

The current 10 can be found by writing Kirchhoff's voltage equation for the output
loop:
Vo - Rio - Av,., = 0
• - Vo - Av,.,
lo - R
0
However,
V14 = Vi - Vi
=0-v1
I
R1Vo = -Bv
- Ri + R11 °
Therefore,
Substituting the value of t, in Equation (4-9a), we get
(4-9b)
This result shows that the output resistance of the voltage series feedback amplifier is
1/(1 + AB) times the output resistance R0 of the op-amp. That is, the output resistance
of the op-amp with feedback is much smaller than the output resistance without
feedback.
4-3.6 Bandwidth with FHdback
The bandwidth of an amplifier is defined as the band (range) of frequencies for which
the gain remains constant. Manufacturers generally specify either the gain-bandwidth
product or supply open-loop gain versus frequency curve for the op-amp, For the
741 .op-amp the latter is typical.
Figure 4-6 shows the open-loop gain versus frequency curve ofthe.741C op-amp.
From this curve for a gain of 200,000, the bandwidth is approximately 5 Hz. On
the other extreme, the bandwidth is approximately 1 MHz when the gain is unity. The
frequency at which the gain equals 1 is known as the unity gain-bandwidth. It is the
maximum frequency the op-amps can be used for. Furthermore, the gain-bandwidth
product obtained from the open-loop gain versus frequency curve of Figure 4-6 is
equal to the unity gain-bandwidth of an op-amp. However, this holds true only for
those op-amps which, like the 741, have just onebreak frequency below unity gain-
bandwidth.
Since the gain-bandwidth product is. constant, obviously the higher the gain,
the smaller the bandwidth, and vice versa. As we have seen, if negative feedback is
used, gain A decreases to A/(1 + AB). Therefore, to obtain the closed-loop bandwidth,
the open-loop bandwidth must be multiplied by the same factor by which the gain is
divided, that is, by the factor (I + AB). In short, ·
Sec. 4-3 Voltage-SeriesFeedbackAmplifier 121

104
c:
-~ 103
4)
!
0 102
>
10 --------------
10-1 L..-..l....-.....L.---l.---"'.._--:"~-'7"::---:-;::'
1 10 100 1 k 10 k 100 k 1 M 10 M Figure 4-6 Open-loop gain versus
Frequency (Hz) frequency curve of the 741C.
bandwidth with feedback = (bandwidth without feedback)(! + AB)

fp = /o(l + AB) (4-lOa)
or alternatively,
Ii _ unity gain-bandwidth
P - closed-loop gain
UBW
- --x;- (4-lOb)
For instance, let us assume that the 741C is used in the circuit of Figure 4-2 and
that the desired voltage gain is 10; then the closed-loop bandwidth/., [using Equation
(4-lOb)] will be approximately 1 MHz/IO= 100 kHz.
The closed-loop bandwidth can also be determined from the open-loop gain
versus frequency plot. To do this we locate the closed-loop voltage gain value on the
gain axis and draw a parallel line through this value to the frequency axis. Then we
project the point of intersection of the line with the curve on the frequency axis and
read the value of the closed-loop bandwidth. Using this procedure in Figure 4-6, the
bandwidth is approximately 100 kHz for a closed-loop gain of 10.
4-3.7 Total Output Offset Voltage with Feedback

,
In an op-amp when the input is zero, the output is also expected to be zero. However,
because of the effect of input offset voltage and current, the output is significantly
larger, a result in large part of very high open-loop gain. That is, the high gain aggra-
vates the effect of input offset voltage at the output. We call this enhanced output
voltage the total output offset voltage V00r. In an open-loop op-amp the total output

offset voltage is equal to either the positive or negative saturation voltage. The satura-
. tion voltages are specified on the data sheets as output voltage swing.
Since with feedback the gain of the noninverting amplifier changes from A to
A/(l + AB) [Equation (4-6)], the total output offset voltage with feedback must also
be 1/(1 + AB) times the voltage without feedback. That is,
total output offset _ total output offset voltage without feedback
voltage with feedback - 1 + AB
or
V _ ±V,11
ooT - 1 + AB (4-11)
where 1/(1 + AB) is always less than 1 and ± V,.1 = saturation voltages. Note that
v••r is either positive or negative voltage.
Negative feedback can also be used to reduce significantly the effect of noise,
variations in supply voltages, and of changes in temperature on the output voltage of
a noninverting amplifier. In fact, the higher the value of (1 + AB), the smaller is the
effect of noise and of variations in supply voltages and changes in temperature on the ·
output voltage of a noninverting amplifier.
From the analysis above it is clear that the noninverting amplifier with feedback
exhibits the characteristics of the perfect voltage amplifier. That is, it has very high
input resistance, very low output resistance, stable voltage gain, large bandwidth,
and very little (ideally zero) output offset voltage.
4-3.8 Voltage Follower
The lowest gain that can be obtained from a noninverting amplifier with feedback is
1. When the noninverting amplifier is configured for unity gain, it is called a voltage
follower because the output voltage is equal to and in phase with the input. In other
words, in the voltage follower the output follows the input.
Although it is similar to the discrete emitter follower, the voltage follower is
pref erred because it has much higher input resistance, and the output amplitude is
exactly equal to the input.
To obtain the voltage follower from the noninverting amplifier of Figure 4-2,
simply open R1 and short Rp. The resulting circuit is shown in Figure 4-7. In this
+Vee
F~ 4-7 Voltage follower.
l: - .
~--
figure all the output voltage is fed back into the inverting terminal of the op-amp;
consequently, the gain of the feedback circuit is I (B = AF = 1).
Since the voltage follower is a special case of the noninverting amplifier, all the
formulas developed for the latter are indeed applicable to the former except that the
gain of the feedback circuit is I (B = I). The applicable formulas are:
AF= 1
R,F = AR,
RoF = ~o
fp = Afo
V :____ ±V ..t
oor---y-
since (I + A) ,....., A.
The voltage follower is also called a noninverting buffer because when placed
between two networks, it removes the loading on the first network. ·
Example 4-1
The 741C op-amp having-the following parameters is connected as a noninverting
amplifier (Figure 4-2) with R1 = 1 kn and Rp = 10 kn:
A= 200,000
R1 = 2 Mn
R0 = 75n
/0 ,...,5Hz
supply voltages = ±15 V
output voltage swing = ± 13 V
Compute the values of Ap, R1p, R p, fp, and VoaT·
0
Solution. Let us first calculate the value of B. Then the closed-loop parameters AF,
R1p, R0p,fp, and V007 can be obtained by using Equations ( 4-6), (4-8), (4-9b), (4-lOa),
and (4-11), respectively.
R1 1 kn 1
B = R1 + Rp = 1 kn + 10 kn = TI
1 +AB= 1 + 2~·~ = 18,182.8
Ap = :~·~ = 10.99
R,P = 2 Mn(18,182.8) = 36.4 on

t5n
RaP = 18,182.8 = 4.12 m.Q
Je= (5 Hz)(18,182.8) = 90.9 kHz
±13V
VooT = 18,182.8 = ±0.715 mV
Note that the (±) sign indicates that V 00 r could be of either polarity.

In the example above, the voltage gain· calculated using the exact equation
[Equation (4-2)] is 10.99. The gain would have been 11 ifwe had used the ideal voltage-
gain equation [Equation (4-3)]. Thus the difference error is very small (0.09%) and can
be ignored. That is, for all practical purposes we may use the ideal voltage-gain equa-
tion, provided that A ~ A,. Remember that as A, approaches A, the difference error
also increases. · :
Example 4-2
Repeat Example 4-1 for the voltage follower of Figure 4-7.
I
Solution. For the voltage follower, B = 1; therefore, 1 + AB = 200,000. To com-
pute the closed-loop parameters we merely substitute the known values into Equations
(4-6), (4-8), (4-9b), (4-lOa), and (4-11).
A,= 1
R,, = 2 M!2(200,000) = 400 GO
750
R0p = 200,000 ~ 0.375 mQ
f, = (5 HzX200,000) = 1 MHz
±13V
VooT = 200 ()()() = ±65 µV
'
Thus the input and output resistances of the voltage follower approach ideal values,
and the bandwidth is equal to the maximum operating frequency of the op-amp. In
addition, since (I +
AB) = A, the smallest possible value for V00r is possible.
4-4 VOLTAGE-SHUNT FEEDBACK AMPUFIER
Figure 4-8 shows the voltage-shunt feedback amplifier using an op-amp. The input
voltage drives the inverting terminal, and the amplified as well as inverted output
signal is also applied to the inverting input via the feedback resistor R,. This arrange-
R, V2 RF
AL
--- Ia!
jln
r- - -, +
Vo -
IRF-iF
I
I
I
+ v,
I I Yo RL
L_f_...J -VEE
Feedback
circuit
Figure 4-8 Voltage-shunt feedback amplifier (or inverting amplifier with

feedback).
Sec. 4-4 Voltage-Shunt FeedbackAmplifier 125

ment forms a negative feedback because any increase in the output signal results in a
feedback signal into the inverting input, causing a decrease in the output signal.
Note that the noninverting terminal is grounded, and the feedback circuit has
only one resistor Rp. However, an extra resistor R1 is connected in series with the input
signal source Vin· .
First we derive the formulas for the voltage gain, input and output resistances,
bandwidth, and the total output offset voltage. Then we study the special cases of
this configuration.
4-4.1 C/osed.:.Loop Voltage Gain
The closed-loop voltage gain AF of the voltage-shunt feedback amplifier can be

obtained by writing Kirchhoff's current equation at the input node v2 [see Figure
4-8] as follows:
(4-12a)
Since R, is very large, the input bias current Ia is negligibly small. For instance,
R, = 2 MQ and !8 = 0.5 µA for the 741C. Therefore,
That is,
Vin - V2. - Vz - Vo
(4-12b)
R, - RF
However, from Equation (3-9),
Since v1 = 0 V, ,
Substituting this value of v2 in Equation (4-12b) and rearranging, we get

Vin + vof A -(vof A) - Vo
R1 - RF
AF= V0 = _ ARP (exact) (4-13)

Via R, + RF + AR,
The negative sign in Equation (4-13) indicates that the input and output signals
are out of phase by 180° (or of opposite polarities). In fact, because of this phase
inversion, the configuration in Figure 4-8 is commonly called an inverting amplifier
with feedback.
Since the internal gain A of the op-amp is very large (ideally infinity), AR1 ~
~1 +RF.This means that Equatioq (4-13) can be rewritten as
(ideal) (4-14)
This equation shows that the gain of the inverting amplifier is set by selecting a ratio
of feedback resistance RF to the input resistance R1• In fact, the ratio Rp/R1 can be
set to any value whatsoever, even to less than 1. Because of this property of the gain
126 .!\11 Op-Amp with Neqativa Feedback Chap.4

equation, the inverting amplifier configuration with feedback lends itself to a majority
of applications as against those of the noninverting amplifier.
Let us now rewrite Equation (4-13) in the feedback form of Equation (4-6), for
a couple of reasons. First, it facilitates analysis of the inverting amplifier with feedback.
Second, it helps compare and contrast inverting and noninverting amplifier configura-
tions, as we shall soon see. However, to express Equation (~i3) in the form of
Equation (4-6), we must represent the current-summing junction at the input terminals
of an amplifier as a voltage-summing junction (see Figures 4-8 and 4-9).
Summing junction
v, Figure 4-9 Block diagram of

inverting amplifier with feedback using
B a voltage-summing junction as a model
for current-summing.
To begin with, we divide both numerator and denominator of Equation (4-13)

by R,:
A
A,= -1 + (Ri/R,)(l + A)
Since A is very large, 1 + A ,_, A ; hence
A
A,= -1 + A(R /R,)
1
(4-15)
A comparison of Equation (4-15) with the feedback Equation (4-.6) indicates that we
can equate
(4-16)
Note that in actuality B = 1/R,; however, the representation B = Ri/R, is possible

because the voltage-shunt case is again modeled as a voltage amplifier. Thus the
magnitude of the ideal closed-loop gain is
IA,I = _!_ = Rl' (4-17)

B R1
The one-line block diagram of the inverting amplifier with feedback is shown in
Figure 4-9. However, remember that here a voltage-summing junction is merely
being used as a model for what is actually current-summing. This approach facilitates
the analysis of the inverting amplifier and also enables us to express the performance
equations in the same form as those for the noninverting amplifier.
4-4.2 Inverting Input Terminal at Virtual Ground
Refer again to the inverting amplifier of Figure 4-8. In this figure, the noninverting
terminal is grounded, and the input signal is applied to the inverting terminal via
resistor R1• However, as discussed in Section 4-3.3, the difference input voltage is
ideally zero; that. is, the voltage at the inverting terminal (v2) is approximately equal
Sec. 4-4 Voltage-Shunt Feedback Amplifier 127

to that at the noninverting terminal (v1). In other words, the inverting terminal
voltage v2 is approximately at ground potential. Therefore, the inverting terminal is
said to be at virtual ground. This concept is extremely ifseful in the analysis of closed-
loop inverting amplifier circuits. For example, ideal closed-loop gain [Equation·
(4-14)) can be obtained using the virtual ground concept, as follows:
In the circuit of Figure 4-8,
That is,
Via - V2 _ V2 - Va
R1 - RP
However,
Therefore,
Via Va
R1 = -RP
or I
Ap =Va= _RP
Via R,
This is the same result obtained in Equation (4-14).
4-4.3 Input Resistance with Feedback
The easiest method of finding the input resistance is to Millerize the feedback resistor
Rp, that is, split RP into its two Miller components, as shown in Figure 4-10.
In the circuit of Figure 4-10, the input resistance with feedback R,p is then
R,p=R1+1~PAll(R,) (exact) (4-18)
+Vee
--
A'" ;:, 0 !1
Figure 4-10 Inverting amplifier with Millerized feedback resistor.
128 An Op-Amp with Negative Feedback Chap. 4 ·

Since R, and A are very large,
Hence
RIP= R1 (ideal) (4-19)
4-4.4 Output Resl&tancewith Feedback
The output resistance with feedback R p is the resistance measured at the output
0
terminal of the feedback amplifier. Thp output resistance of the noninverting amplifier
was obtained by using Thevenin's theorem, and we can do the same for the inverting
.amplifier. Thevenin's equivalent circuit for R0F of the inverting amplifier is shown in
Figure 4-11. Note that this Thevenin's equivalent circuit is exactly the same as that for
noninverting amplifier (Figure 4-5) because the output connections in both amplifiers
are the same. This means that the equation for the output resistance R0p of the inverting
amplifier must be identical to that of the noninverting amplifier [Equation (4-9b)].
Specifically,
. R
RoP = 1 + oAB (4-20)
However, note that B = R1/Rp for the inverting amplifier.
4-4.5 Bandwidth with Feedback
As mentioned previously, the gain bandwidth product of a single break frequency

op-amp is always constant. We also saw that the gain of the amplifier with feedback
is always less than the gain without feedback. Therefore, the bandwidth of the amplifier
v, -----Nlh------
Figure 4-11 Thevenin's equivalent circuit for R0p of the inverting amplifier.
Sec. 4-4 Voltage-Shunt FeedbackAmplifier 129

with feedback f, must be larger than that without feedback. This means that the
equation for the bandwidth of the inverting amplifier can be written as
f, = fo(l + AB) (4-21a)
or, equivalently,
}; = unity gain bandwidth (4-21b)
P closed-loop gain
where!., is the break frequency of the op-amp and B = R1/Rp, Note that the equation
for the bandwidth of the inverting and noninverting amplifier is the same except the
B value.
To find the closed-loop bandwidth of the inverting amplifier, use Equation
(4-21a) if lo is known and use Equation (4-2lb) if unity gain bandwidth is given.
However, to calculate the bandwidth graphically from the gain versus frequency
curve, we can use the same procedure that was outlined for the noninverting amplifier.
4-4.S Total Output Offset Voltaga with Feedback
When the temperature and power supply voltages are fixed, the output offset voltage
is a function of the gain of an op-amp. However, we saw that the gain of the op-amp
with feedback is always less than that without feedback. Therefore, the output offset
voltage with feedback V00r must always be smaller than that without feedback. Speci-
fically,
total output offset · _ total output offset voltage without feedback
voltage with feedback - 1 + AB
That is,
V _ ±V .. i (4-22)
ooT - 1 + AB
where ± V,. 1 = saturation voltages
B = Rd RF for the inverting amplifier
A = open-loop gain of the op-amp
Note again that the V00r equation for the inverting amplifier is the same as that for
the noninverting amplifier except for the B value.
In addition, because of the negative feedback the effect of noise, variations in
supply voltages, and changes in temperature on the output voltage of the inverting
amplifiers are significantly reduced.
Finally, the two special cases of the inverting amplifier with feedback are the
current-to-voltage converter and the inverter.
4-4.7 Current-to-VoltagfJ Converter
Let us reconsider the ideal voltage-gain Equation (4-14) of the inverting amplifier,

Therefore,
Va= -(~:)R,
However, since v1 = 0 V and Vi = V2,
Vin_·
Ri - 'in
Va= -iiuRP (4-23)

This means that if we replace the Vin ind R1 combination by a current source i1n as
shown in Figure 4-12, the output voltage v, becomes proportional to the input current
iin· In other words, the circuit of Figure 4-12 converts the input current into a propor-
tional output voltage.
Figure 4-12 Current-to-voltage

converter.
One of the most common uses of the current-to-voltage converter is in sensing

current from photodetectors and digital-to-analog converter applications, which are
discussed in more depth in Chapter 7.
4-4.8 Inverter
If we need an output signal equal in amplitude but opposite in phase to that of the
input signal, we can use the inverter. The inverting amplifier of Figure 4-8 works as
an inverter if R1 = R,. Since the inverter is a special case of the inverting amplifier,
all the equations developed for the inverting amplifier are also applicable here. The
equations can be applied by merely substituting A for (1 + AB), since B = 1.
Example 4-3
n
For the inverting amplifier of Figure 4-8, Ri = 470 and R, = 4.7 k!l. Assume that
the op-amp is the 741 having the same specifications as those giv.en in Example 4-1.
Calculate the values of A,, R,,, R0,, I», and YaoT•
Solution. From Equation (4-16),
470 1
B = 4.7ill = 10
Then 1 +AB,_ 20,000. Therefore, using Equations (4-15), (4-18), (4-20), (4-21a),
and (4-22), the values of the closed-loop parameters are:
Sec. 4-4 Voltage-ShuntFeedbackAmplifier 131

AF -- 200,000 _ -10
20,000 -
R,, = 410 n + (i= 112 Mn) = 410 n

15n
R0, = 20 000
= 3.75 m!l
'
f, = (5 Hz)(20,000) = 100 kHz
±13V
VooT = 2Q.OOO = ±650 µV
•
Example 4-4
For the inverting amplifier of Example 4-3, determine the value of output voltage if the
input is a 1-V peak-to-peak sine wave at 1 kHz. Also sketch the output waveform.
Assume that V00r is zero.
Solution. Using the value of the gain calculated in Example 4-3, the output voltage is
v0 = -(10)(1) = -10 V peak to peak
The input and output waveforms are shown in Figure 4-13.
For quick review, the results of noninverting and inverting amplifiers are
summarized in Table 4-1.
TABLE 4-1 SUMMARY OF RESULTS OBTAINED FOR NONINVERTING

AND INVERTING AMPLIFIERS
Parameter Noninverting amplifier Inverting amplifier
1. Voltage gain Ap = A(R, + Rp) (exact) A, = R1 +-AR, ( t)

R1 + R, + AR1 R, + AR1 exac
A -A
1 + AB 1 + AB
= 1 + R,, (idea!) -- -R,
R, (ideal)
R1
2. Gain of the B= R1 B=R1
feedback circuit R1 + R, R,
R,, = R1(1 + AB)
3. Input resistance
RIP = R1 + (1 ! A I R,)
4. Output R R
resistance oP = 1 +RoAB oP = 1 +RoAB
5. Bandwidth fp = /o(l + AB) fp = /o(l + AB)
UBW UBW
=~ - --x;-
6. Total output v. · _ ±Vut v. _ ± v.. t
offset voltage oaT - 1 + AB ooT - 1 + AB
As mentioned earlier, current-shunt and current-series feedback configurations

seldom find use in practice; therefore, they will not be discussed here. However,
interested readers may analyze them following the same procedure as used for voltage-
series and voltage-shunt feedback configurations.
132 An Op-Amp with Negative Feedback Chap.4

5V
-5V Figure 4-13 Waveforms for

f..--1 ms---j Example 4-4.
4-5 DIFFERENTIAL AMPLIFIERS
We will now study the closed-loop differential amplifier configurations. Specifically,

we evaluate three different arrangements· of the differential amplifier with negative
feedback. We classify these arrangements according to the number of op-amps used.
That is,
1. Differential amplifier with one op-amp

2. Differential amplifier with two op-amps
3. Differential amplifier with three op-amps
Generally, the differential amplifiers are used in instrumentation and industrial

applications to amplify differences between two input signals, such as the outputs of
the Wheatstone bridge circuits. Differential amplifiers are preferred in these applica-
tions because they are better able to reject common-mode (noise) voltages than single-
input circuits such as inverting and noninverting amplifiers. They also present a
balanced input impedance.
4-5.1 Differential Amplifier with One Op-Amp
Figure 4-14 shows the differential amplifier with one op-amp. We will analyze this
circuit by. deriving voltage gain, and input resistance. A close examination of Figure
4-14 reveals that the differential amplifier is a combination of inverting and non-
inverting amplifiers. That is, when u, is reduced to zero the circuit is a noninverting
amplifier, whereas the circuit is an inverting amplifier when input v,. is reduced to
zero.
4-5.1 (a) Voltage gain. The circuit in Figure 4-14 has two inputs, v.., and
v,.; we will, therefore, use the superposition theorem in order to establish the relation-
ship between inputs and output. When v,. = 0 V, the configuration becomes an
Sec. 4-5 Differential Amplifiers 133

+Vee
,_ --o v • -- RF (v - v l
o R, x v
Figure 4-14 Differential amplifier with one op-amp. R1 = R2 and Rp = R3•

inverting amplifier; hence the output due to v,. only is
v = _ Rp(Vx) (4-24a)
°" R,
Similarly, when v,. = 0 V, the configuration is a noninverting amplifier having a
voltage-divider network composed of R2 and R3 at the noninverting input. Therefore,
v, = R3(Vy)
R2 + R3
and the output due to Vy then is
That is,
v = Rp(vy) (4-24b)
ay R,
Thus, from Equations (4-24a) and (4-24b), the net output voltage is
Va = Vax + Vay
v = _RP(v _ v) =·_Rp(v,.1)
a R, " y . R1
or the voltage gain
(4-25)
Note that the gain of the differential amplifier is the same as that of the inverting
amplifier.
4-5.1 (b) Input resistance. Assume that when both input signals are zero,
the output voltage is also zero. That is, the total output offset voltage V00T is zero:
Therefore, with V00T = 0 V, R1 = R2, and RP= R3, the input resistance between
either input terminal v,. or Vy and ground is
(4-26)

If we need a variable gain, we can use: the differential amplifier of Figure 4-15.
In this circuit R1 = R2, R., = R3, and the potentiometer RP = R4• Therefore, depend-
ing on the position of the wiper in RP, voltage gain can be varied from the closed-loop
gain of -2R;/R1 to the open-loop gain of A.
Figure 4-15 Differential amplifier with

variable gain.
Example 4-5
In the circuit of Figure 4-14, R1 = R2 = 1 k!l, Rp = R3 = 10 k!l, and the op-amp
is a 741C.
(a) What are the gain and input resistance of the amplifier?
(b) Calculate the output voltage v0 if v., = 2.7 V pp and .Vy= 3 V pp sine waves at
100 Hz.
Solution
(a) Substituting known values in Equations (4-25) and (4-26), we obtain A0 and .R,17:
10 k!l
A0 = -Tid'f = -10
R17 = 1 k!l + 10 k!l = 11 k!l

(b) Rearranging Equation (4-25) yields
= -(10)(2.7 - 3) = 3 V pp sine wave at 100 Hz
4-5.2 Differential Amp/Hier with Two Op-Amps
Recall that the gain expression for the differential amplifier of Figure 4-14 is the same
as that of the inverting amplifier of Figure 4-8 [see Equations (4-14) and (4-25)]. We
can increase the gain of the differential amplifier and also increase the input resistance
R,7 if we use two op-amps. Such a circuit is shown in Figure 4-16. In. fact, the charac-
teristics of this amplifier are identical to those of the noninverting amplifier.
4-5.2(a) Voltage gain. A close examination of the circuit of Figure 4-16

shows that it is composed of two stages: first, the noninverting amplifier, and second,
the differential amplifier with unequal gains. By finding the gain of these two stages,
we can obtain the overall gain of the circuit as follows:
Sec.4-6 DifferentialAmplifiers 136

Figure 4-16 Differential amplifier with two op-amps.
The output v, of the first stage is
v, = (1 + ;:)vy (4-27a)
By applying the superposition theorem to the second stage, we can obtain the output
voltage:
V0 = _R~~z) + (1 + ;:)vx (4-27b)
Substituting the value of v, from Equation (4-27a), we get
Therefore,
(4-28)
4-5.2(b) Input resistance. The input resistance R,P of the differential

amplifier is the resistance determined looking into either one of the two noninverting
input terminals with the other grounded (see Figure 4-16). Note, however, that the
first stage (A 1) is a noninverting amplifier; therefore [from Equation (4-8)], its input
resistance is
_R,p 1 = R,_( 1 + AB) (4-29a)
where R, = open-loop input resistance of the op-amp
B= R1
R2 + R3

Similarly, with Vy shorted to ground (e, = 0 V), the second stage (A2) also becomes a
noninverting amplifier whose input resistance can then be written as
R,n = RtC I + AB) (4-29b)
where R, = open-loop input resistance of the op-amp
B = R1
R1 +R,
However, since R, = R3 and R, = R2, the R,,1 -=I=- R,,2. This is the drawback of the
differential amplifier of Figure 4-16. Nevertheless, with proper selection of compo-
nents, both R,,1 and R,,2 can be mlde much larger than the source resistances, so
that the loading of the input sources does not occur.
Example 4-6
The following specifications are given for the differential amplifier of Figure 4-16:
R1 = R3 = 680!2, R, = R2 = 6.8 k!l, v.,. = -1.5 V pp, and v1 = -2 V pp sine
waves at 1 kHz. The op-amp is a 741C. Calculate (a) the voltage gain and the input
resistance and (b) the output voltage of the amplifier. Assume that the output is initially
nulled ( V00T = 0 Y). ·
Solution
(a) From Equation (4-28),
6.8 kn
AD = 1 + 680IT = 11
The input resistance can be calculated using Equations (4-29a) and (4-29b).
R
IFl -
- c2 Mn)[1 + <6.8
2)00')<6·8 kn)]
kQ + 6800
- 364 an
-
R = (2 MO) [1 + 6.8
(2)(10')(680) n] - 36 4 an
"2 kn + 680 n - · u
(b) Output voltage can be calculated by rearranging Equation (4-28):
V0 = (1 + ~:)v.,. 1
= (11)(-1.5 + 2) = 5.5 V pp sine wave at 1 kHz
4-5.3 DifferentialAmplifier with Three Op-Amps
The advantages of the two differential amplifiers discussed above can be combined in
a single differential amplifier having variable voltage gain and very high input resis-
tance. However, to achieve this desirable combination, three op-amps must be used,
4-5.3(a} Voltage gain. The differential op-amp of Figure 4-17 consists of

two stages. The first stage is composed of op-amps A 1 and A 2, while the second stage
is formed by op-amp A3• Therefore, to find the overall voltage gain AD of the amplifier,
the voltage gain of each stage must be determined. To begin with, the first stage can
be viewed as two separate differential amplifiers, as shown in Figure 4-18. The output
voltages of these differential amplifiers can be found by applying the superposition
theorem. For Figure 4-18(a),
Sec.4-5 Differential Amplifiers 137

R,
~-ov =-(1 + _2R")(RF)v

o Ri; R, xv
-----First stage--------Second stage----
Figure 4-17 Differential amplifier with three op-amps.
v.0-----1
R_. R_.
Rs Rs
R_. R_.
v, v.
(a) (b)
Figure 4-18 Deriving the voltage gain of the first stage of the circuit in Figure
4-17.
(4-30a)
and for Figure 4-18(b ),
(4-30b)
However, the output voltage of the first stage is

· Therefore, from Equations (4-30a) and (4-30b),
_ 2R4 + R,( )+ R4
R4 + R, V.,, + R, ( )
Vz, - - Vy R4 e, - V,
_ 2R4 + R, + R4
- R4 + R, v.. R4 + Rs v;
Simplifying and rearranging the voltage gain of the first stage gives
v; 2R4 + R, (4-30c)
Vxy = Rs
Next, using Equation (4-25), the gain of the second stage is
(4-30d)
Thus, from Equations (4-30c) and (4-30d), the overall voltage gain is
AD= Vz, V0 = -(2R4 + R5) Rp
V.,,y Vz, · R, R1
or
(4-31)
Remember that the gain can be changed by varying potentiometer Rs. Of course, R5
should never be set to zero or infinity. If R, is set to zero, voltage gain Equation (4-31)
becomes indeterminent; whereas if R, is set to infinity (open R,), the first stage acts
as a voltage follower.
4-5.3(b) Input resistance. The input resistance of the differentialR,,

amplifier in Figure 4-17 is the same as the input resistance of the first stage, that is,
the resistance determined at input v.,, and Vy looking into the circuit with the other
terminal grounded.
In Figure 4-18a, for instance, when v, is reduced to zero, that is, when v,. is
grounded, the circuit is a noninverting amplifier. Applying the concepts developed for
the noninverting amplifier, the input resistance determined at input v.,, is
R" = R,(1 + A2~.. : ~,) (4-32)
Similarly, the input resistance determined at input v,. will be the same as that given in
Equation (4-32).
A simple modification in the differential amplifier of Figure 4-17 is to replace
·the first stage by voltage followers, as shown in Figure 4-19. The main advantage of
this circuit is that it has the highest input resistance of the three amplifiers; this resis-
tance is given by
R" = R,(l + A) (4-33a)
where R, = input resistance of the op-amp
A = large-signal voltage gain of the op-amp
However, the voltage gain of the circuit in Figure 4-19 is equal to the voltage gain of
Sec.4-5 Differential Amplifiers 139

+Vee
+Vee
Figure 4-19 Special case of differential amplifier with three op-amps.
the differential amplifier with one op-amp; that is,
AD=~= _R, (4-33b)

v,,, R1
4-5.4 Output Ruiflance and Bandwidth of Differential

Amplifiers
Recall that the closed-loop op-amp configurations-noninverting, inverting, and

differential amplifier-employ negative feedback arid use the same type of output
connections. Therefore, the output resistance of all three configurations must be
identical. In other words, the output resistance of the differential amplifier should be
the same as that of the noninverting or inverting amplifier, except that B = I/AD.
That is,
R
ol' = 1 +RoA/AD (4-34)
where AD = closed-loop gain of the differential amplifier

R0 = output resistance of the op-amp
A = large-signal voltage gain of the op-amp
Remember that AD is different for each of the differential amplifier configurations.
As in the case of noninverting or inverting amplifiers, the bandwidth of differ-
ential amplifiers also depends on the closed-loop gain of the amplifier, and is given by
I
Ii = unity gain bandwidth (4_3Sa)
" closed-loop gain AD
or alternatively,
(4-35b)

where lo is the open-loop break frequency of the op-amp. For example, the output
resistance and bandwidth of the differential amplifier with one op-amp will be as
follows:
Example 4-7
The following specifications are givfn for the differential amplifier of Figure 4-17:
R4 = 3.9 k!l, R5 is a 5-k!l potentiometer, R1 = R2 = l k!l, and RP= R3 = 4.7 k!l.
The op-amps are 741C's and the supply voltages are ±15 V. If R5 is set at 3 k!l, cal-
culate (a) the voltage gain, (b) the input resistance, (c) the output resistance, and (d)
the bandwidth of the differential amplifier.
Solution
(a) Substituting the given values in Equation (4-31), the voltage gain is
A
D
= -[l it-(2)(3,9k!l)J4.7kn
3k{l Tien-
__ 1692
'
Note that the negative sign indicates the phase reversal between differential input and
output.
(b) Using Equation (4-32),
R IP = 200' 0000[1 + <200,000 ><3·9 kn + 3 k!l)J

(2)(3.9 kQ) + 3 k{l
- 256
-
an
(c) Output resistance can be obtained substituting the values in Equation (4-34):
75!l
Ro, = l + 200,000/ 16.92 = 6·3 rn!l
.(d) Finally, the bandwidth of the amplifier is given by Equation (4-35b):
I,= 5( l + 2~:~) = 59.12 kHz
Su-MMARY
1. The very high voltage gain of the .open-loop op-amp as well as its variation with tempera-
ture, power supply, and production yield makes the ·open-loop op-amp configuration
unsuitable for linear applications.
2. The introduction of negative feedback stabilizes the gain; however, it is also smaller than
the open-loop gain. On the other hand, positive feedback is necessary in oscillator circuits.
3. There are four closed-loop configurations using negative feedback: voltage-series, voltage-
shunt, current-series, and current-shunt. These configurations are labeled according to
whether the voltage or current is fed back to the input in series or in parallel.
4. The voltage-series negative feedback configuration is commonly called a noninverting
amplifier with feedback, while the voltage-shunt feedback configuration is called an invert-
ing amplifier with feedback. The ideal closed-loop gain of these two configurations depends
Cj,ap.4 Summary 141

only on the feedback network (components) and is independent of the-internal .gain A
of the op-amp.
5. The use of negative feedback in a noninverting amplifier "increasesthe input impedance and
bandwidth, and decreases the output resistance, total output-offset voltage, and the effect
of varying environmental conditions on the gain. The same results .are obtained for the
inverting amplifier using negative feedback, except for input resistance. The input resis-
tance of the inverting amplifier is relatively smaller because it depends on the resistance
connected in series with the input signal source.
6. A special case of the noninverting amplifier is the voltage follower, while she current-to-
voltage converter and the inverter are two special cases of the inverting amplifier. The volt-
age follower has a gain of unity. The current-to-voltage converter produces output voltage
proportional to input current, and the inverter has an output equal in· amplitude but
opposite in phase to that of the input.
7. Negative feedback is also used in differential amplifiers. According to the number of op-
amps used, the differential amplifier configurations are alassified as differential amplifier
with one op-amp, differential amplifier with two op-amps, and ·differential amplifier with
three op-amps. The differential amplifier with one op-amp has the same characteristics as
the inverting amplifier, while the amplifier with two op-amps ·has the same characteristics
as the noninverting amplifier. Very high input resistance and variable gain are the features
of the differential amplifier with three op-amps ..
QUESTIONS
4-1. Give two reasons why an open-loop op-amp is unsuitable for linear applications.
4-2. What is feedback? List two types of feedback. Which type is used in linear applications?
4-3. List the four negative feedback configurations. Which two configurations arc most com-
monly used?
4:4. Explain briefly why negative feedback is desirable in amplifier applications.
4-5. What is the effect of negative feedback in noninverting amplifiers?
4-6. How does negative feedback affect the perf ormancc of an inverting amplifier?
4-7. In what way is the voltage follower a special case of the noninvcrting amplifier?
4-8. List two special cases of inverting amplifiers.
4-9. What are the three differential amplifier configurations? Briefly compare and contrast
these configurations.
PROBLEMS
I
4-1. The open-loop gain A of a particular op-amp varies from 15,000 to 20,000 over the
operating temperature range 25° to 35°C. This op-amp is used in the circuit of
Figure 4-2 with R1 = 470 Q and R, = 47 kO.
(a) Calculate the closed-loop gain at both temperature extremes.
(b) Compute the percentage variation in the open-loop gain and in the closed-loop
gain; explain the results.

4-2. The following specifications apply to the noninverting amplifier of Figure 4-2:
Op-amp is the 741C with: Feedback circuit
A= 200,000 Ri = 1.8 kn
R, =2 Mn Rr = 18 kn
Ro= 75 n
lo~5Hz
UBW~ 1 MHz
Supply voltages = ± 15 V I.
Maximum output voltage swing = ± 13 V
(a) Calculate the exact closed-loop gain.

(b) Calculate the ideal closed-loop gain.
(e) Explain the results obtained in parts (a) and (b).
+3. Repeat Problem 4-2 with R1 = 470 n and Rp = 47 k!l.
4-4. The 714C is configured as a noninverting amplifier as shown in Figure 4-2. The follow-
ing data are given for the circuit:
A= 400,000 R1 = 4700
R, = 33 M!l RP= 4.7 k!l
R0 = (i()Q
Supply voltages = ±1.5 V
Maximum output voltage swing= ±13 V
Unity gain bandwidth = 0.6 MHz
Compute the closed-loop parameters A,, Ri,, Ro,,f,, and VooT•
4-5. Repeat Problem 4-4 with R1 = 100 Cl.
4-6. For the noninverting amplifier of Problem 4-4, compute the output voltage 110 and then
sketch it if v10 = 100 mV pp sine wave at 1 kHz. Assume that the op-amp is initially
nulled.
4-7. The op-amp of Probtem s-s is used in a voltage follower. Compute the closed-loop
parameters A,, RIP, Ro,,/,, and VooT•
4-8. The 741C is configured as an inverting amplifier as shown in Figure 4-8, with R1 =
1 k!l and R, = 10 k!l.
(a) Calculate the exact closed-loop gain.
(b) Calculate the ideal closed-loop gain.
(c) Compare and explain the results of parts (a) and (b).
(For op-amp specifications, refer to Problem 4-2.)
4-9. Repeat Problem 4-8 with R1 = 100 Cl.
4-10. The 714C is connected as an inverting amplifier with R1 = 1 k!l and R, = 4.7 k!l.
Compute the closed-loop parameters A,, RIP, R0,J,, and VooT· (Refer to Problem 4-4
for the op-amp parameters.)
4-11. Repeat Problem 4-10 with R, = 1 k!l. What is the name of this circuit?
4-12. For the inverting amplifier of Problem 4-10, t11a = 1 V pp sine wave at 100 Hi.
(a) Compute the output voltage v0•
(b) Draw the output voltage waveform, assuming that the output is initially nulled.
Chap.4 Problems 143

4-13. The input current into the current-to-voltage converter of Figure 4-12 varies from
500 µA to 1 mA. Calculate the variations in the output voltage if R, = 4.7 k!l. Assume
that the op-amp is a 714C with its output initially nulled.
4-14. The 741C is used for the differential amplifier of Figure 4-14 with R1 = R2 = 100 0
and R, = R3 = 3.9 kO.
(a) Calculate the closed-loop voltage gain.
(b) Calculate the input resistance RIP assuming that the circuit is initially nulled.
(The 741C parameters are given in Problem 4-2.)
4-15. For the differentiai amplifier of Problem 4-14, compute the output voltage if v.,, =
-3.2 V and v7 = -3.0 V. Assume that the circuit is initially nulled.
4-16. In the variable-gain differential amplifier of Figure 4-15, R1 = R2 ·= 100 0 R, = R3
= 2.2 k!l, R,. = 10 kO, and R,. is a 20-k!l potentiometer. The op-amp is a 714C.
Compute the gain of the differential amplifier if (a) R, = 10 k!l and (b) ~P = S ill.
4-17. The following specifications apply to the differential amplifier of Figure 4-16: R2 =
·R, = 2.2 kO, R3 = R1 = 1 k!l, v.,, = 700 mV pp, and Vy = 500 mV pp sine waves
at 500 Hz; the op-amp is a 741C. Assume: that the op-amp is initially nulled. Calculate:
(a) The voltage gain.
(b) The bandwidth.
(c) The input resistance seen by each signal source.
(d) The output resistance.
(e) The output voltage of the amplifier.
(For the electrical parameters of the 741C, refer to Problem 4-2).
4-18. For the differential amplifier of Figure 4-17, R,. = 1 kn, R, is a to~k!l potentiometer,
R1 = R2 = 1.5 kO, and R, = R3 = 15 kO. The op-amps are 741Cs with supply
voltages = ±15 V. If R, is set at 5 kO, calculate:
(a) ·The voltage gain.
(b) The input resistance seen by each signal source.
(c) The output resistance.
(d) The bandwidth of the differential amplifier.
EXPERIMENT 4-1
NONINVERTING AMPUFIER WITH FEEDBACK
Ob/ectivu
In this experiment you will study' the effect of negative feedback on the performance
of the noninverting amplifier. At the end of this experiment you·should be able to:
1. Verify that the gain of the noninverting amplifier depends on the feedback
components and not on the internal gain of an op-amp.
I
2. Confirm that the use of negative feedback increases the bandwidth and decreases
the output offset voltage of the op-amp.
3. Understand that the voltage follower is a special case of the noninverting
amplifier.
4. Discuss the differences between the noninverting amplifier and the voltage
follower. i .:

Equipment
3. ± 15-V power supply
4. Multimeter
Materials
1. 741 or 351 op-amp

2. Two 1-kn resistors
4. 100-kn resistor
Procedure
1. Connect the 741/351 op-amp as shown in Figure E4-1.l(a). The pin numbers
indicated in this figure refer to an 8-pin mini DIP.
2. With the voltmeter, measure the output voltage and enter the measured value in
Table E4-1.l(a).
TABLE 14-1.1
(a) de measurements (with via = 0 V)
Configuration Output offset voltage
Noninverting amplifier
without feedback
Noninverting amplifier
with feedback
Voltage follower
(b) ac measurements
Output voltage, Vo Voltage gain, v0/v1a
Noninverting amplifier Noninverting amplifier

Input Input with feedback with frccdback
voltage, frequency, Voltage Voltage
1'!a 1.. R, = IOkO R, = 100 kC follower R, = 10 kC R, = lOOkC follower
lOOmV 1 kHz
SOmV 1 kHz
SOmV 100Hz ~
Exp. 4-1 Noninverting Amplifier with Feedback 145

+15 V +15 V
VooT 6
Vo
RL RL
10 kn 1okn
-15 V -15 V
(a) (b)
Figure E4-1.1 (a) Open-loop op-amp with input terminals connected to ground.
(b) Noninverting open-loop op-amp. .
3. Disconnect the resistor Rs connected to the noninverting input from ground

and apply a I 00-m V pp sine wave at I. kHz through Rs to the noninverting
terminal, as shown in Figure E4-1.l(b),. Using the dual-trace oscilloscope,
observe the input and output waveforms simultaneously. Change the input
amplitude to 50 m V pp and observe the input and output waveforms. Then
change the input frequency to 100 Hz and again obser.ve the input and output
waveforms.
4. Connect the circuit as shown in Figure E4-1.2(a). With v1n = 0 V, measure the
output voltage using the voltmeter and enter the measured value in Table
E4-1.I(a).
+15V +15V
6 6
Vo Vo
+ +
-15 V -15 V
RL RL
ro en 10 kn
R, RF 10 kn
1kn
(al (bl
Figure E4-1.2 (a) Noninvcrting amplifier with feedback. (b) Voltage follower.
5. Apply a v1n = 100 mV pp side wave at .l kHz to the noninverting input and
measure the output voltage. Enter the measured. value in Table E4-l.l(b).
Change the input amplitude to 50 m V pp and measure the output amplitude
using the scope. Next, change the input frequency to 100 Hz and again measure
the output amplitude. Each time enter the measured value in Table E4-l.l(b).
6. Change the value of R, from 10 k!l to 100 k!l and repeat step 5.
146 An Op-Amp with NegativeFeedback Chap. 4

7. Connect the circuit of Figure E4-1.2(b). With v,n = 0 V, measure the output
voltage using the voltmeter and enter the measured value in Table E4-1.l(a).
8. Repeat step 5 for the circuit of Figure E4-1.2(b).
9. Complete Table E4-1.l(b).
Questio,_ps
1. List the amplifiers with the highest and lowest output offset voltage; then give
the reason for the difference. ,
2. What is the input offset voltage for the voltage follower?
3. What type of output waveform is obtained in step 3? Explain why.
4. What is the gain of the noninverting amplifier when RP= 10 kO and RF=
100 kQ? What conclusion can be drawn from these results?
5. Referring to the data in Table E4-1.l(b), does the gain of the noninverting
amplifier change when the input an_iplitude or frequency is changed? Explain
your answer.
6. For the voltage follower, what is the relationship between the input and output
voltages?
7. Explain how a voltage follower is a special case of the noninverting amplifier
with feedback.
EXPERIMENT 4-2
INVERTING AMPLIFIER WITH FEEDBACK
Objectives
In this experiment you will study the effect of negative feedback on the performance
of the inverting amplifier. At the end of this experiment you should be able to:
I. Verify that the input and output voltages of the inverting amplifier are out of
phase by 180°.
2. Confirm that the gain of the inverting amplifier with feedback depends on
external components and not on the internal gain of the op-amp.
3. Verify that the closed-loop bandwidth of an inverting amplifier depends on its
closed-loop gain.
4. Understand that the inverter is a special case of the inverting amplifier.
Equipment
Exp.4-2 InvertingAmplifier with Feedback

Materials
I. 741 or 351 op-amp

2. I-kn resistor
3. Three IO-kn resistors
4. I 00-kn resistor
Procedure
I. Connect the 741/351 op-amp as shown in Figure E4-2.I(a). The pin numbers
indicated refer to an 8-pin mini DIP.
2. Set v1n = 100 mV at 100 Hz sine wave and observe the input and output wave-
forms on the scope simultaneously. Make sure that the scope is used in the
proper triggered mode. Enter the amplitudes of the input and output voltages
in Table E4-2. l. Change the input frequency to 500 Hz and again observe the
TABLE E4-2.1
Output voltage, 110 Voltage gain, 1Jo/111n
Inverting amplifier Inverting amplifier

Input Input with feedback with feedback
voltage, frequency,
1Jin fin R, = lOkn R, = lOOkn Inverter R, = lOkn R, = lOOkn Inverter
lOOmV lOOHz
lOOmV 500 Hz
lOOmV 1 kHz
Frequency at which output

Configuration ~ starts decreasing
Inverting amplifier with feedback

co Rr= 10 kn
(ii) R, = 100 kn
Invert cf
input and output waveforms. Enter the input and output amplitudes in Table
E4-2.1.
3. Change the frequency of the input to 1 kHz, keeping the amplitude the same
(t·1,, = 100 mV pp). Measure the input and output amplitudes and enter the
1
results in Table E4-2. I.
4. Slowly increase the frequency of the input until the output amplitude just starts
. decreasing. Record this value of frequency in Table E4-2. l.
5. Change R, from IO kn to JOO kn and repeated steps 2, 3, and 4.
6. Connect the circuit of Figure E4-2. l(b) and again repeat steps 2, 3, and 4.
7. Complete Table E4-2. I.
148 An Op-Amp with Negative Fe.dback Chap.4

R, RF R,
1k11 10k11 10k11 to xn
+15V +15V
+ +
Vin - v.
Vin -
6
I
RL
10 kn
-15 V -15 V
(a) (b)
Figure E4-2.1 (a) Inverting amplifier with feedback. (b) Inverter.
Questions
1. What is the phase shift between the input and output voltages of an inverting
amplifier?
2. Does the gain of the inverting amplifier with RP = 10 kn remain constant over
100 Hz to 1 kHz? Explain why or why not.
3. What determines the gain of the amplifier?
4. Do the gains of the inverting amplifier and inverter start decreasing at the same
frequency? Explain your answer.
5. What is the difference between an inverting ~mplifier and an inverter?
EXPERIMENT4-3
DIFFERENTIALAMPUF/ER WITH FEEDBACK
Objectives
In thisexperiment you will learn how the differential amplifier works. At the end of
this experiment you should be able to:
1. Verify that the differential amplifier amplifies the algebraic' difference between
two input voltages.
2. Verify that the gain of the differential amplifier with feedback depends on
external components and not on the internal gain of the op-amp.
3. Confirm that the bandwidth of the differential amplifier depends on its gain.
Equipment
Exp.4-3 Differential Amplifier with Feedback 149

Materials
1. 741 or 351 op-amp

2. 2N3391 transistor
3. 1-kn resistor
4. 2-k!l resistor
5. ro-xn resistor
6. 22-k!l resistor
7. Three 47-kn resistors
9. Two 470-k!l resistors
10. 3-kn potentiometer
11. Three 5-µF capacitors
Procedure
1. Construct the circuit of Figure £4-3.1. Connect channels I and 2 of the scope to
points x and y, set v1n = 100 mV at 1 kHz sine wave, and adjust the 3-~
potentiometer so that the voltages at points x and y are equal in amplitude.
+15 V
47k!l
5µF Vx R1
x 47k!l 100k!l
5µF
2N3391
+ y R2
Vin - 22k!l
5µF
Vy 47k!l
2kU R3 RL .
100k!l -15 v 10 k!l
E C B
0 Bonom view of 2N3391
Figure E4-3.l Differential amplifier with-feedback, (Pin numbers refer io 8-pin mini DIP.)

2. Measure the input voltages v; and v,, and output voltage v0• Enter the measured
values in Table E4-3.l(a).
TABLE E4-3.1
(a) If the voltage at the noninverting input terminal leads that at the inverting terminal
by 180°:
11,: pp t!y pp Vxy PP1 110 pp Voltage gain, Calculated voltage gain,
(V) (V) (V) (V) 11o/11xy Rp/R1
(b) If the voltage at the inverting input terminal leads that at the noninverting input ter-
minal by 180°:
""' pp Vypp t!,:y pp Vo pp Voltage gain, Calculated voltage gain,

(V) (V) (V) (V) t!o/Vxy Rp/R1
...
(c) 100-kO resistors replaced by 470-kO resistors:
Vx pp t!y pp t!xy pp 110 pp Voltage gain, Calculated voltage gain,

(V) (V) (V) (V) 11o/11xy Rp/R1
(d) The frequency at which .the output voltage of the differentialamplifier starts decreasing:
______ Hz.
3. Switch off the input voltage V1n and power supply voltages ±
15 V. Then recon-
nect the noninverting input terminal to point x and the inverting input terminal
to point y, respectively. Tum the input and power· supply voltages on and
measure the vx, v,.. and v0 voltages using the scope. Enter the results in Table
E4-3.l(b).
4. Switch off the input voltage and power supply voltages and replace the 100-kn
resistors by the 470-k!l resistors. Turn on the vi .. and ± 15-V supply -voltages.
Measure vx, v,,. and v0 voltages using the scope and enter the results.jnr'Table
E4-3.l(c). ..
5. Increase the frequency of the input signal vlA until the amplitude ofthe.output
voltage v0 starts decreasing. Enter this value in Table E4-3.l(?). ·
6. Complete Table E4-3.1.
Differential Amplifier with Feedback

,-. 151
Exp. 4-3
'
Questions
1. What conclusion can be drawn from the results of Table E4-3.l(a) and (b)?
2. How is the gain of the differential amplifier set?
3. What is the significance of the frequency at which the output voltage of the
differential amplifier starts decreasing?
152 An Op-Amp with NegativeFeedback Chap. 4

5
The Practical Op-Amp
5-1 INTRODUCTION
In preceding chapters we have seen that the op-amp may be used· as an inverting,
noninverting, or differential amplifier, and that the negative feedback can be used to
stabilize the-voltage gain and increase the bandwidth of the op-amp circuit. However,
up to this point in our discussion we have treated the op-amp as an ideal device that
gives us the desired results, such as high input impedance, low output impedance,
high voltage gain, and broader bandwidth, if we use appropriate external compo-
nents. We have also treated the op-amp as though 'it responds equally to both ac and
de input voltages. However, these ideal characteristics are not fully present in the
practical op-amp circuits. The practical op-amp has some de output voltage, called
output offset voltage, even though both inverting and noninverting input terminals are
grounded. Such an output offset voltage is an error voltage and is therefore undesir-
able. In this chapter we discuss the properties of the practical op-amp that produce
the output offset voltage. We also see that it is- necessary to incorporate additional
circuitry to increase the effectiveness of the op-amp, especially if it is used as a de
amplifier.
5-2 INPUT OFFSET VOLTAGE

Input offset voltage V,0 is the differential input voltage that exists between two input
terminals of an op-amp without any external inputs applied. In other words, it is the
amount of the input voltagJ that should .be applied between two input terminals in
order to force the output voltage to zero [see Figure 5-l(a)]. Let us denote the output
163
(al (bl
Figure 5-1 (a) Input offset voltage in an op-amp. (b) Output offset voltage in
an op-amp.
offset voltage due to input offset voltage Yt0 as V00• The output offset voltage V00 is
caused by mismatching between two input terminals. Even though all the components
are integrated on the same chip, it is not possible to have two transistors in the input
differential amplifier stage with exactly the same characteristics. This means that the
collector currents in these two transistors are not equal, which causes a differential
output voltage from the first stage. The. output of first stage is amplified by following
stages and possibly aggravated by more mismatching in them. Thus the output voltage
caused by mismatching between two input terminals is the output offset V00• Figure
5-1 (b) shows the output offset voltage in an op-amp without feedback.
The output offset voltage V00 is a de voltage; it may be positive or negative in
polarity depending on whether the potential difference between two input terminals
is positive or negative. It is impossible to predict the polarity of the input offset voltage
since it is dependent on mismatching between two input terminals. Therefore, on· the
data sheets the value of the input offset voltage V,0 is listed as an absolute maximum
value. For example, for a 741, V,0 = 6 mV maximum, whereas for a 740, V,0 = 20 mV
maximum, which means that the maximum potential difference between two input
terminals in a 741 op-amp can be as large as 6 mV de; that is, voltage at the noninvert·
ing input terminal may differ from that at the inverting input terminal by as much as
6 m V de, or vice versa. This input offset voltage gives rise to an output offset voltage
V00• Thus we need to apply a differential input voltage of specific amplitude and
correct polarity in order to reduce the output offset voltage V00 to zero. This voltage is
referred to as input offset voltage V,0• The V1o value for op-amps of the same type. may
not be the same in amplitude and polarity because of mass production, but it will
always be less than the maximum value given on the specification sheets. For example,
if we take three different 74ls and use them one at a time as in Figure 5-l(b) and mea-
sure the corresponding output offset voltage for each of them, we find that the output
offset voltage in these three op-amps is not of the same amplitude and polarity, which
means that input offset V,0 is not of the sable amplitude and polarity even though the
op-amps are of the same type. To reduce V00 to zero, we need to have some circuit at
the input terminals of the op-amp which will give us the flexibility of obtaining V,0 of
proper amplitude and polarity. Such a circuit is called an input offset voltage com~n-
sating network. Before we apply external input to the op-amp, with the help of an
offset voltage compensating network we reduce the output offset voltage V00 to zero;
154 The Practical Op-Amp Chap. 5

the op-amp is then said to be nulled or balance1, Before we get into the design of a
compensating network, it is worth noting that the compensating network is not needed
for those op-amps that have offset null pins, such as 741, 748, 777, and 201. For the
741-type op-amp the manufacturer recommends that a 10-kn potentiometer be placed
across offset null pins 1 and 5 and a wiper be connected to the negative supply pin 4
as shown in Figure 5-2. Adjustment of this pot will null the output.
+15V
6 V00=0V
2
R·L
-15 V
Figure 5-2 Voltage offset null circuit

10kS1 for 741.
Refer to the 741 equivalent circuit of Section 2-4. By varying the position of the
wiper on the 10-kn potentiometer, we are trying to remove the mismatch between
inverting and noninverting input terminals of the op-amp. Adjust the wiper until the
output offset voltage is reduced to zero. See the analysis of the 741 op-amp circuit in
Section 2-4.
5-2.1 Offset-VoltageCompensatingNetwork Design
The op-amp with offset-voltage compensating network is shown in Figure 5-3. The
compensating network consists of potentiometer R,, and resistors Rb and R,,. If we
are planning to make use of the op-amp as an inverting amplifier, the compensating
network should be connected to the noninverting input terminal of the op-amp. The
circuit in Figure 5-3 can be used as a noninverting amplifier since the compensating
network is connected to the inverting input terminal of the op-amp.
'+Voe
V00•0V
Figure 5-3 Op-amp with offset voltage

compensating network.
Sec.5-2 Input Offset Voltage 155

Note that the potentiometer R0 is connected to+ Vee and -VEE and the voltage
across Re is the voltage at the inverting input terminal V2, By adjusting the wiper on
R0, voltage V 2 can be made to equal voltage V1 : that is, Vi0 can be made zero, which
forces V00 to go to zero. Say, for example, that V00 is positive, which implies that
Vi > V2• This means that V2 should be increased until it equals V1; the increase can
be accomplished by moving the wiper toward Vee· On the other hand, if V00 is nega-
tive, that is, V2 > V1, the wiper can be moved toward - VEE until V00 is reduced to
zero.
To establish a relationship between V, supply voltages and the compensating
0,
components, we first have to Thevenize the circuit, looking back into R0 from point
T.
The maximum Thevenin's equivalent resistance Rmax occurs when the wiper is
at the center of the potentiometer, as shown in Figure 5-4(a). Thus
The maximum Thevenin's equivalent voltage Vmax is equal to either Vee or -VEE
when the wiper is uppermost in the potentiometer or lowest in the potentiometer [see
Figure 5-4(b) and (c)].
Supply voltages Vee and - VEE are equal in magnitude; therefore, let us denote
their magnitude by voltage V. Thus Vmax = V.
Next we redraw the compensating network using the maximum Thevenin's
voltage and resistance as shown in Figure 5-5. Applying the voltage-divider rule to
+Vee
~.
2 T
T
R.
l
Ra
T
Ra
2
l
R max =-
R.
4
v .... x=+Vcc
1
V max= -Vee
{a) {b) {cl
Figure 5-4 (a) Thevenin's equivalent for resistance Rmax· (b, c) Thevenin's
equivalent for voltage Vmax·
R"'"" T
v .....
Figure 5-5 Compensating network
with maximum Thevenin's equivalent
resistance and voltage.
168 The Practical Op-Amp Chap.5

the circuit in Figure 5-5, we get
V2 - R. V (5-1)
- Rmax + Rb + R. max
where V2 has been expressed as a function of maximum Thevenin's voltage Vmax

and maximum Thevenin's resistance Rmu· But the maximum vaiue 'Of V2 can be equal
to V,o, since I V1 - V2 I = Vi Thus Equation (5-1) becomes
0•
V -
lo - Rm.~ +R.Rb + R. Vmsx (5-2)
There are too many unknowns in Equation (5-2). To simplify Equation (5-2), let us
make the assumption that Rb > Rmax > R., where Rmax = Raf 4. An explanation for
this assumption is in order. The bias currents in the op-amp are fixed and -very small,
in the range of nanoamperes. Therefore, the bias current in an inverting terminal of
the op-amp in Figure 5-3 will also be very small and fixed. In no case will the bias
current be larger than the value listed on the' data sheets. To null the op-amp the
required variation in the voltage across R~ is also small, on the order of millivolts;
in the case of some op-amps it is even on the order of microvolts. This means that not
only the current through R. should be small, but the value of R. should also be very
small. The bias current in an inverting terminal and the current through R. are derived
from the current through Rb. Since two of these currents will be very small, the current
through Rb will be significantly smaller than the current through Ra. To accomplish
this we needed Rb> Ra, which implies that Rb> Rmax since Rmax = Ra/4. Thus the
assumption Rb > Rmax > R. is valid. Using this assumption, we can say that Rmax +
Rb + R. ~ Rb. Therefore, Equation (5-2) can be rewritten as·
(5-3)
where
Vmax = V = I Vccl = 1-VEEI
V, = R.V
o Rb :
Note that Vio depends on the magnitude of the supply voltages +
Vee and - VEE·
Equation (5-4) will be used to design the compensating network. We. will obtain
the value of Via from the data sheet of a given op-amp, whereas the value of V will be
fixed according to the supply voltages chosen; once these two values are known, we·
will establish the relationship between Rb and R Then we will select the value for R.
0•
to compute the value of Rb. The value for R. will be selected to be less than 100 so n
that Rb and Ra values will not be too large.
Example 5-1
Design a compensating network for the LM307 op-amp. The op-amp uses ±10-V
supply voltages.
Solution. The value of Via specified on the data sheets of the LM307 is 10 m V maxi-
mum .' The value of V = I Vccl = 1-VEEI. = 10 V. Substituting these values in Equa-
Sec. 5-2 Input Offset Voltage 157

tion (5-4), we get
10 mY = Rc(10 Y)
Rb
lOY
Rb= 10 mYR,
If we select R, = 10 n, the value of Rb should be

Rb = (lOOO)R, = 10,000 n
Since Rb> Rmax, let us choose Rb= lORmax, wnere
Ra
R max =4
Rb= (lO)~a
R 10 kn .
Ra = 2.~ = ~ = 4-kn potentiometer
If a 4 kn potentiometer is not available, we may prefer to use the next lower value
available, such as 3 kn, so that the value of Ra will be larger than Rb by a factor of 10.
If we select a 3-kn potentiometer as the Ra value, Rb is 13.3 times larger than Ra, Thus
Ra = 3-kn potentiometer
Rb= lOkn
R, = ion
The final circuit, which also includes the pin connections for the LM307, is shown in
Figure 5-6.
After the circuit in Figure 5-6 is breadboarded, we will adjust the potentiometer
R until the output is reduced to zero. This nulled op-amp circuit now can be used as
0
a noninverting amplifier by applying an external voltage to the noninverting input·

terminal. But the magnitude of the input voltage applied has to be very very small to
avoid any distortion and clipping of the output signal. A small input voltage is needed
+Vee
+10 V
+Vee
+10 V 7
3
v.
R, V2
3kU ;;:,,-,11--~--v,Nv-~--<>-~~~o---l
lOkU 2
4
R,
-10 V io n
=v « -10 V
-Vee
Figure 5-<i Offset voltage compensating network for LM307.

because the voltage gain of the op-amp without feedback is extremely high, ideally
infinity. Because of the high risk of distortion and clipping of the output signal, op-
amp in open-loop configuration is not used in linear circuit applications.
Let us now examine the effect of V, in amplifiers with feedback. The non-
0
inverting and inverting amplifiers with feedback are shown in Figure 5-7. To determine
the effect of V,0 in each case, we have to reduce the input voltage Vin to zero.
A,
(al
A,
v = (- RF ) V, -
o A, '"
(bl
Figure 5-7 (a) Noninverting amplifier with feedback. (b) Inverting amplifier
with feedback.
With v1n reduced to zero, the circuits of both noninverting and inverting ampli-
fiers are the same as the circuit in Figure 5-8. We assume here and in future cases that
the internal resistance R1n of the input signal voltage is negligibly small.
We wish to express V in terms of external components R1, RP, and the specified
00
input offset voltage V, for a given op-amp. In the figure, the noninverting input
0
terminal is connected to ground; therefore, we assume voltage V1 at the noninverting

input terminal to be zero. The voltage V2 at the inverting input terminal can be deter-
mined by applying the voltage-divider rule:

Figure 5-8 Closed-loop noninverting
or inverting amplifier with v1n = 0 V.
(5-5)
Therefore, (5-6)
(5-7)
Therefore,
V
00 = (1 + ~:) V, = (A 0 00) V,0 (5-8)
where A = 1 + Rp/R1• Thus when an op-amp is used in a closed-loop configuration

00
as either a noninverting or inverting amplifier, we can compute the maximum possible

output offset voltage V caused by the input offset voltage V by using Equation ··
00 10,
(5-8). According to this equation, for a given op-amp the amount of V depends on 00
the values of external components R1 and RP, that is, A Therefore, the smaller the
00•
value of A the smaller will be the value of V for a given val tie of Vi In the extreme
00, 00 0•
case when R1 » RF, A 00 ~ 1 and V V Thus, in practice all op-amp circuits

00 ~ 10•
will have some output offset voltage V To null the output offset voltage V we can
00• 00,
use a compensating network identical to the one that was used to null the open-loop
op-amp circuit. The closed-loop noninverting and inverting amplifiers with their
compensating networks are shown in Figure 5-9.
The offset-voltage compensating networks in Figure 5-9 will be designed by using
Equation (5-4). The compensating network is connected in the noninverting terminal
for the inverting amplifier and in the inverting terminal for the noninverting amplifier.
Note that the voltage gain of the neninverting amplifier with compensating network
is Ap = 1 + [Rp/(R1 + Re)]. The gain changes because the Thevenin equivalent
resistance of the compensating network, which is approximately equal to Re, is in
series with R1• In fact, this result is based on the assumption that Rb> R > Re. 0
Before an external input Vin is applied, the op-amp in Figure,5-9 should be nulled by
adjusting the wiper in pot R 0•
The closed-loop differential amplifier is somewhat more difficult to null because
160 The Practical Op-Amp

+Vee
>-----o Vo = (1 +
.
_R_F_) V;n
R1 + RC
V1
if Rb> R, > RC
+
(a}
R, V2 RF
Vin
+Vee
R,
Rb v0=(,~)v1n
RL
Re -Vee
-Vee
..., (bl
Figure 5-9 (a) Compensated noninverting amplifier with feedback. (b) Com-
pensated inverting amplifier "".ith feedback.
the use of the compensating network can change the common-mode rejection ratio.
(See Section 5-11 for further information on the common-mode rejection ratio.)
Figure 5-10 shows the differential .amplifier with its input offset voltage compensating
network. In order to maximum CMRR, we should use R1 = R2 and RP= R3 + Re.
The compensated differential amplifier shown in Figure 5-11 uses the op-amp
with the offset voltage null pins. Note that R1 = R2 and RP= R3• This amplifier
circuit has two advantages over the one in Figure 5-10. One advantage is that it is
simpler, since it uses fewer components, and the other is that the offset null circuit
does not affect the CMRR. A voltage follower may be nulled using a similar compen-
sating network, as shown in Figure 5-12.
The voltage drop across Re is used to cancel the offset voltage. Even though
Rb > R0 and Re, their finite values cause the gain of the voltage follower to increase

R,
Figure 5-10 Differential amplifier with offset-voltage compensating network.
10 rn
Figure 5-11 Differential amphfier with offset voltage null circuit (pins l and 5
are offset null pins for 741 op-amp).
slightly (see the v expression in Figure 5-12). This insignificant error in gain usually
0
can be ignored, since Re < Rb + Rof4.

The offset-voltage compensating network discussed above is a versatile circuit.
It is applicable to all op-amp types and can be used in different operating modes

+Vee
-v .. lR max
R.
=-4
Figure 5-12 Voltage follower with, offset-voltage compensating network.
without any modifications. It also allows nulling without interfering with the internal
circuitry of an op-amp.
Example 5-2
The op-amp in the circuit of Figure 5-13 is the LM307 with Via = 10 mV de maximum.
What is the maximum possible output offset voltage, Vaa, caused by the input offset
voltage Via?
Solution. To find the maximum possible value of Vaa, we reduce the input voltage
v,n to zero. The closed-loop gain of the amplifier is
Aaa =1 + ~: = 1 + \0 :i = 11
Since Via = 10 mV de maximum, the Vaa might be as large as

Vaa = Aaa Vra = (11)(10 mV de) = 110 mV de
1 kn 10 kn
-10 V
Figure 5-13 Noninverting amplifier with feedback.
Sec.5-2 Input Offset Voltage 163

This means that the output terminal can be either at a negative or a positive. HO mV
de with respect to ground even though v;n = 0 V.
Example 5-3
Design an input offset-voltage compensating network for the circuit in Figure 5-13.
Solution. We have designed the compensating network for the LM307 in Example 5-1.
We can use the same circuit and connect it in the inverting terminal as shown in Figure
5-14.
Applying Thevenin's theorem across Re, the equivalent resistance RTH = Re
because Re < Ra <Rb.Also, the value of R1 is much larger than Re. This means that
the closed-loop gain of the noninverting amplifier will not be affected by the use of the
compensating network, that is,
RF 10 kO
AF= 1 + R1 +Re= 1 + 1 kO +ion= 11
Note that we have distinguished between the voltage gains A00 and Ap. The voltage gain
A00 = 1 + Rp/R1 is used to calculate the maximum possible output offset voltage
V due to the input offset voltage Vi both in the inverting and noninverting amplifiers
00 0
(see Figure 5- 7). On the other hand, the voltage gain Ap = 1 + Rp/ R1 of the noninvert-
ing amplifier of Figure 5-7(a) or the voltage gain AP = -.f?.p/R1 of the inverting ampli-
fier of Figure 5-7(b) is used to compute the output voltage v0 due to the input voltage
+10 V
R, R,
3kn .>-,..._~-.,W1,~~..--~--.,.w..~~.-~~.JV\Mr~~~
1 kn 101sn
io n
-10 V
>-<D6-+--.n Vo ~ (1 + :: )v,n
since R1 >> Re
-10V
Figure 5-14 Compensated noninverting amplifier with feedback.
5-3 INPUT BIAS CURRENT
An input bias current IB is defined as the average of the two input bias currents, /JJ1
and IB2, as shown in Figure 5-15; that is,
] _
B-
IB1 +2 IB2
(5-9)

Figure 5-15 Input bias currents in an
op-amp.
where /01 = de bias current ftowin/ into the non inverting input
IB2 = de bias current flowing into the inverting input
In Figure 5-15, both input terminals are grounded, so that no input voltage is applied
to the op-amp. But the plus-minus supply voltages are necessary to bias the op-amp
properly.
Actually, the input bias currents IB, and ln2 are the base bias currents of the two
transistors in the input (first) differential amplifier stage of the op-amp. Even though
both of the input transistors are identical, it is not possible to have In, and /B2 exactly
equal to each other because of the internal imbalance between the two inputs. In this
section we assume that the specified input bias current IB is equal to either one of the
two input currents In, and /82; that is,
IB = l;:Jt = lnz (5-10)
The value of input bias current In is very small, in the range of a few to a few hundred
nanoamperes. It is a de current and is specified on the op-amp data sheets. For exam-
ple, IB is 500 nA maximum at supply voltages = ± 15 V de, for µA 74 I, whereas it is
75 nA maximum for MLM !OJA. The value of IB has been significantly reduced in
later-generation op-amps.
Even though very small, the input bias current /B can cause a significant output
offset voltage in circuits using relatively large feedback resistors. This output offset
voltage may not be as large as that caused by the input offset voltage, but certain
precautions must be taken to minimize it.
First we obtain the expression for the output offset voltage caused by the input
bias current IB in the inverting and noninverting amplifiers, and then devise some
scheme to eliminate or minimize it. The noninverting or inverting amplifier with
V;n = 0 Vis redrawn in Figure 5-16. We assume for the duration of this section that
the input offset voltage Vi is zero; that is, there is no output offset voltage due to
0
V,0• Let V018 be the output offset voltage due to input bias current IE.
In the figure, the input bias current IE, and ln2 are flowing into the noninverting
and inverting input leads, respectively. The noninverting terminal is connected to
ground; therefore, the voltage V1 = 0 V. The controlled voltage source AV,0 = 0 V
since V10 = 0 V is assumed. With output resistance R0 negligibly small, the right end
of RF is essentially at ground potential; that is, resistors R1 and RF are in parallel and
the bias current ln2 flows through them. Therefore, the voltage at the inverting terminal
is
V2 = (R1 II RF)ln2 (5-11)
V _ R1RP I (5-12)
2 - R1+ RF Bl
Sec. 5-3 Input Bias Current 165

--i,
+Vee
-12
V;0 = OV assumed
V1
101 t
Figure 5-16 Output offset voltage due to input bias current in a noninverting or
inverting amplifier.
Writing a node voltage equation for node V2, we get

11 + 12 = ln2
(5-13)
where V01B = output offset voltage due to input bias current

R1 = input resistance of the op-amp (see Figure 5-16)
Rearranging Equation (5-13), we get
Vars = v2 (-1 + _l + __!__)

s, R1 RP R,
Since R, is extremely high (ideally oo ), 1 / R, ~ 0 mhos. Therefore,
Vars = v 2 R1 +
RP (5-14)
RF R1RF
Substituting in Equation (5-14) the value of V2 from Equation (5-12), we get
v
ols
= R1RFIB2
R1 + RF
(RI + Rp)
RI
vols= RFIB2 (5-15)
From Equation (5-10),
vols= RPIB (5-16)
I
According to Equation (5-16), the amount of output offset voltage V01s is a
function of feedback resistor RF for a specified value of input bias current /8• The
amount of V01s can be increased by the use of relatively large feedback resistors.
Therefore, the use of small feedback resistors is recommended.
To eliminate or reduce the output offset voltage V01s due to input bias current
IB, we have to devise some scheme at the input by which voltage V1 can be made equal

to V2. In other words, if voltages V1 and V2 caused by the currents IB1 and JB2 can be
made equal, there will be no output offset voltage V0 ,s.
From Equation (5-12), we
have
(5-17)
where
R = R1Rp
P R1 +Rp
Equation (5-17) implies that we must express voltage V1 at the noninverting
input terminal as a fucction of IB1 And some specific resistor RaM· This can be accom-
plished as follows. The input bias current IB1 does not produce any voltage at the
noninverting input terminal because this terminal is directly connected to ground
(see Figure 5-16). If we could connect the proper value of resistor RaM in the non-
inverting terminal, the voltage V1 would be
V1 = (RoM)IB1 (5-18)
In order to have voltage V1 equal to V2, the right-hand sides of Equations (5-17) and
(5-18) must be equal; that is, ·
RplB2 = RaMIB1 (5-19)
Now if the currents 181 and l_-,12 are equal, Equation (5-19) implies that
RP= Rau (5-20)
or
(5-21)
Thus the proper value required of an RaM resistor connected in the noninverting
terminal is the parallel combination of resistors R1 and Rp. However, the use of RoM
may not completely eliminate the output offset voltage V01,, because the currents
IB1 and JB2 are not exactly equal. Nevertheless, the use of RaM will minimize the amount
of output offset voltage V01s; therefore, the RoM resistor is referred to as the "offset
minimizing resistor" (see Figure 5-17).-
Note that if we reduce both the inputs to zero (that is, v1n1 = v1n2 = 0 V) in
the closed-loop differential amplifier, the resulting circuit becomes the same as in
fl,
vol0=ov
it 181 = 182
Figure 5-17 RoM reduces the output

Is1 offset voltage V01s caused by the input
bias current IB.
Sec.5-3 Input Bias Current 167

Figure 5-17. This means that there is no need to use a separate resistor RoM in the
differential amplifier cirucits. Figure 5-18 shows the noninverting and inverting
amplifiers with offset minimizing resistor RoM·
~----Q (1 + ::)
V0 = Vin
v,
vole ~av
(a)
R, V2 RF
Is2 + +Vee
vo =(- R,
RF) V,
,n
v,
V018;;; 0V
R1RF -Vee RL
R =--- t1s2
OM R, + RF
(bl
Figure 5-18 (a) Noninverting amplifier with offset rnuurmzrng resistor RoM,
(b) Inverting amplifier with offset minimizing resistor RoM·
Example 5-4
(a) For the inverting amplifier of Figure 5-19, determine the maximum possible output
offset voltage due to (1) the input offs;t voltage Vi and. (2) the input bias current /8•
0
The op-amp is a type· 741.

(b) What value of RoM is needed to reduce the effect of input bias current /8?
Solution
(a) From the 741 op-amp data sheets we have
Vi0 max = 6 mV de
18 max= 500 nA de at TA= 25°C and Vs= ±15 V

A1 AF
470n. V2 47 kn.
+Vee
I02t
7
2
6
Vo
V1
3
Ie1 t 4
AL
10 kn.
-Vee Figure 5-19 Inverting amplifier of

. Example 5-4.
1. Since R1 = 470 n and R2 = 47 kO, the output offset due to V,0 might be as
large as
V00. = ( 1 + ~;) Vio
= (1 + :;0kR)<6mV)
= 606mVdc
Remember that this means that the voltage at the output terminal may
be below or above the ground potential by 606 m V de without any external
input signal v1n.
2. The value of feedback resistor RF = 47 kO; therefore,
vols= RFIB
= (47 k0)(500 nA)
= 23.5 µV de
Again, this means that the output offset voltage V01s could be positive or negative
with respect to ground by as much as 23.5 µV de.
From the results in parts 1 and 2, it is obvious that V00 ~ V018; that is, input
offset voltage V,0 is potentially a greater problem than input bias current IB.
(b) The value of RoM to be used is
R1RF
R OM= R1 +Rp
_ (470 0)(47 kn) = 470 n
- 4700 + 47k0
Example 5-5
Repeat Example 5-4 if R1 is replaced by 1 kQ and RF by 100 kn.,
Solution
(a)
1. The closed-loop voltage gain
R lOOkO .
A00 = 1 + = 1 R7 + 1 kn = 101 ts unchanged
Sec. 5-3 Input Bias Current 169

Therefore, the output offset voltage V00 due to Vi0 is also unchanged; that is,
V00 = 606 mV de as in Example 5-4.
2, With RP = 100 kO, the V01s is
V01s = (100 k0)(550 nA) = 50 mV de
This is relatively larger output offset voltage than in Example 5-4. Thus V01s
becomes larger and therefore potentially troublesome, with larger values of
feedback resistor Rp.
(b) The value of RoM we can use is
RoM = 1 kO 11100 kO = 9900
Since a 990-0 resistor is not a standard value, in practice we may use a 1-kO resistor
as RoM·
5-4 INPUT OFFSET CURRENT
We have seen in Section 5-3 that the use of RoM in series with the noninverting terminal
reduces the output offset voltage V01s due to ls. However, the value of RoM was derived
based on the assumption that the input bias currents Is, and Is2 are equal. In practice,
these currents are not equal because of the internal imbalances in the op-amp's
circuitry. The input offset current [10 is used as an indicator of the degree of mismatch-
ing between these two currents. The value of !10 specified on the data sheets indicates
the maximum amount by which the two input bias currents may differ. In fact, the
smaller this value, the better.
The input offset current 110 is defined as the algebraic difference between two
input bias currents ls1 and ls2, In equation form,
!10 = \ ls1 - ls2 \ (5-22)
For a 741-type op-amp, maximum !10 = 200 nA de. This means that IB, may be
larger than JB2 or !82 may be larger than 181, at the most by 200 nA. In other words,
the maximum difference between ls, and 182 can be as large as 200 nA. In FET input
op-amps, the value of 110 is extremely small. For example, the maximum 110 is 0.3 nA
for the µA740C op-amp.
In a circuit like that in Figure 5-17, there will be an output offset voltage due to
the input bias currents !81 and 182• In other words, the output offset voltage in a case
like this can be expressed as a function of input offset current I1o. Let V01., be the
output offset voltage caused by the input offset current /10• In order to separate the
effect of input offset current from that of input offset voltage, let us again assume
that Vi0 = 0 V.
Referring to Figure 5-20, we will ;xpress the voltages V1 and V2 as a function of
!Bi and Is2, for given values of R1 and RP as follows:
V1 = R0Mls1 (5-18)
V2 = Rpls2 (5-12)
where

R,.
Figure 5-20 Output offset voltage

V01,,, caused by the input offset
current /10 in an inverting or
noninverting amplifier.
Applying the superposition theorem, we will now find the output offset voltage
due to V1 and V2 in terms of /91, In2, and Rp. We know, from Equation (5-15), that
Here the negative sign is used because V2 is the voltage at the inverting input terminal.
This output offset voltage V0182 is due to voltage V2 only in terms of /82 and Rp.
Similarly, the output offset voltage V01s1 due to V1 only in terms of /81 and RP can be
obtained as follows:
V.181 = V1 (1 + ~:) (5-23)
where V1 = voltage at the noninverting input terminal

(1 + ~:) = gain of the noninverting amplifier
Substituting in Equation (5-23) the value of V1 from Equation (5-18), we get
Vo181 = (R0Mf s1)( 1 + ~:)

R1RP I R1 RP + (5-24)
- R. +RP Bl R1
(5-25)
Therefore, the maximum magnitude of the output offset voltage due to 181 and /82 is
= Rp(ls1 - ls2)
V01., = Rp(/10) (5-26)
where vols1 + VO/Bo = v.i.. is the output offset voltage due to 110 and 110 =
I 181
- 181 I the input offset current. Thus for a given value of input offset current /10,
the amount of output offset voltage V0i.. depends on the value of feedback resistor
Rp. As in the two previous cases, the V01,, is also a de voltage and could be positive or
negative with respect to ground. Since /10 is generally much smaller than /8, the output
offset caused by /10 is always smaller than that caused by 18•
Sec. 5-4 Input Offset Current 171

Example 5-6
For · the inverting amplifier in Figure 5-21, determine the maximum output offset
voltage V01i, caused by the input offset current /10. The op-amp is a type 741.
Solution. For the 741 op-amp, I,~ = 200 nA max. Therefore,
Vo1,. = (Rp)/10
= (100 Hl)(200 nA)
= 20 mY de
R, RF
1 kn 100 kn
+15 V
7
2
6
Vo
3
AL
10 k.n
ROM -15 \/
sso n
Figure 5-21 Inverting amplifier of
Example 5-6.
Example 5-6 illustrates that we may not be able to eliminate completely the
output offset voltage due to unequal input bias currents, even though a proper value
of RoM is being used .. However, the output offset voltage has been reduced from
50 m V (in Example 5-5) to 20 m V (in Example 5-6) with the use of RoM, which is a
significant change.
5-5 TOTAL OUTPUT OFFSET VOLTAGE
We know that in a circuit like the orie in Figure 5-19, the output offset voltage V00
caused by V, could be either positive or negative with respect to ground. Similarly,
0
the output offset voltage V018 caused by 18 could also be either positive or negative
with respect to ground. If these output offset voltages are of different polarities, the
resultant output offset will be very little. On the other hand, if both of these output
offset voltages are of the same polarity, the maximum amplitude of the total output
offset would be
(5-27)
By the same token, in a curcuit such as that in Figure 5-21, the total output offset
voltage V r Can be given by the expression
00

vooT = ( 1 + ~:) V1o + (Rp)l,o (5-28)
Note the difference between Equations (5-27) and (5-28). The only difference in the
circuits of Figure 5-19 and 5-21.is the RoM resistor. Therefore, since I,o < IB, the·use
of the RoM resistor in the .noninverting or inverting amplifier assures a reduction in
the current generated output offset voltage.
.
Example 5-7 '
Compute the maximum possible total output offset voltages in the amplifier circuits
shown in Figure 5-22. The op-amp is the MCI 536 with the following specifications:
V10 = 7.5 mV maximum

110 = 50 nA maximum
IB = 250 nA maximum at T,4 = 25°C
A,
1 kn
+28 V
-28 V
(al.
A,
1 kfl
+28 V
3
4
AoM -28 V
990.n
Figure S-22 (a) MC1556 inverting
amplifier of Example 5-7. (b) MC1556
inverting amplifier of Example 5- 7
(bl with RoM,
Sec. 5-6 Total Output Offset Voltage 173 -

Sqlution. In the circuit shown in Figure 5-22(a), the current generated output offset
voltage is due to the input bias current Ia in the inverting lead. Therefore, to compute
the total output offset voltage, we have to use Equation (5-27):
YooT = (1 + ~:) V, + (Rp)Is

0
= (1 + 1?tfl)(7.5 mV) + (10k!l)(250nA)

= 82.5 mV + 2.5 mV = 85 mV
The RoM is used in the circuit of Figure 5-22(b), which means that the current-generated
output offset is caused by the input offset current Ito· Therefore, using Equation (5-28),
we get
YooT = ( 1 + ~:) Vio + (Rp)Ito
= (1 + \0{8)(7.5 mV) + (10 k!l)(50 nA)
= 82.5 mV + 0.5 mV = 83 mV
Thus it is obvious that the input offset voltage Vto is potentially a more troublesome
problem than the input bias current Ia and the input offset current Ito·
5-6 THERMAL DRIFT
In previous sections we learned to compensate for the effects of input offset voltage
and input bias currents. In our discussion so far, we have assumed that the parameters
Vt0, 18, and 110 are constant for a given op-amp. However, in practice, the values of
V,0, Is, and Ito vary with:
1. Change in temperature
2. Change in supply voltages: + Vee and -VBE
3. Time
· In this section we discuss the effect of these factors on the performance of a given
op-amp circuit.
The most serious variation in the values of Vt0, Is, and I,0 is due to the change
in temperature. Before we proceed further to find the change in output offset voltage
due to the change in temperature, let us define the term "thermal drift." The average
rate of change of input offset voltage per unit change in temperature is called thermal
voltage drift and is denoted by !:,. Vi0/ ll.T. It is expressed in µV f°C. By the same concept,
we can also define the thermal drift in the input offset current and input bias current
as follows:
!? = thermal drift in the input offset current (pA/°C)
!~ = thermal drift in the input bias current (pAf°C)

- It is important to note that the "drift" is not a constant value; thatis, it is not uniform
over a specified operating temperature range. Furthermore, the value of the input
offset voltage or current may increase or decrease with increasing temperature, as
-shown in Figure 5-23(a) and (b). Referring to the graph in Figure 5-23(c), we can see
that the value of the input bias current is'riot decreasing at a constant rate with the
increasing temperature. The curves shown in Figure 5-23 are for the MCl 741 op-amp.
Note that in Figure 5-23(a) and (b) the normalized values of the input offset
voltage and input offset current are plotted versus temperature. This means that the
input offset voltage and current are pssumed to be zero at room temperature (25°C).
Now if the change in temperature from 25°C is denoted by 11T, the change in input
offset voltage and input offset current corresponding to this change in temperature
11T is represented by 11 Vi0 and 11/10, respectively. In fact, once we calculate these values
from the graphs in Figure 5-23, for a desired operating temperature range, we can
obtain ·
11j.
0 = thermal voltage drift
!? = thermal current drift
But this procedure is time consuming and also involves mathematical manipulation.
Therefore, some manufacturers specify the average value of the drift in offset voltage
and offset current over an entire operating temperature range instead. On the data
sheet these values are listed as the average temperature coefficients of input offset
voltage and input offset current. Ids worth mentioning that the average temperature
coefficient of input bias current is not listed on the data sheets. Instead, a graph of
/8 versus temperature may be furnished by some manufacturers [see Figure 5-23 (c)].
For example, for the LM101A op-amp the average temperature coefficient of input
offset voltage (that is, thermal voltage drift) is
~0 = 15 µVj°C maximum
and the average temperature coefficient of input offset current is
fT = 200 pAJ°C maximum

~
No information is available on the change in input bias current versus temperature.
In fact, when we use an RoM resistor, we are not concerned about the change in input
bias current as a function of change in temperature. Note again that these values are
denoted as absolute values on the data sheets because they may be positive in one
temperature range and negative in another. More specifically, for the LM101A this
means that the input offset voltage may change at most by ± 15 µVj°C change in
temperature about 25°C. Similarly, the change in input offset current can be at most
±200 pA/°C change in temperature from 25°C.
Sec. 5-6 Thermal Drift 175

sE +2.0 .----.---r--"T"""--r----,.---,----.
CIJ
E
0 +1.0
>
i
:::0
s
Q.
0 ---- ---==---- -,----------i
.s I
>- 0
I
I
"tl
-1.0 I
-oi~
CIJ
Slope can be either polarity

E I
5 I
z -2.0
--~5~5--~2~5--~o---+·2-5--+-5~0--+~7~5--+__.100--+--'125
TA, ambient temperature (°C)
(a)
+10.--- ....... -- ....... --..-------~-----~

<(
.s...
c:
t
::, +5.0
u
I...
::, 0
Q.
.!: . I
...
"tl
.!! I
I
-oi~
CIJ
-5.0 I
Slope can be either polarity
E
0
I
I
z -10..._ __ ..___ ..._ _.___ ..... __ __.__ __,,
-55 -25 0 +25 +50 +75 +100 +125
(b)
...
c:
t::,
u
"'
"'
:.0
...
::,
Q.
.s
- CD

(c)
Figure 5-23 (a) Normalized V,0, input offset voltage versus temperature curve
of MC1741. (b) Normalized 110, input offset current versus temperature curve of
MC1741. (c) Input bias current 18 versus temperature curve of MC1741. (Cour-
tesy of Motorola Semiconductor Inc.)
176
5-6.1 Error Voltage
Next we should like to find the change in the total output offset voltage caused by the
input offset voltage and input offset current drifts. This is important in evaluating the
amplifier performance. To get a clear idea of the point, we should consider a· specific
case.
Let us consider the inverting amplifier with RoM and compensating network as
shown in Figure 5-24. We assume that the amplifier has been nulled at room tempera-
ture (25°C); that is, the effects of V,0 and /10 have been reduced to zero by use of the
potentiometer arrangement shown in Figure ?-24. We have seen that the values of·
V,0 and /10 drift (change) with temperature. According to Equation (5-28), any change
in the values of V,0 and I,0 results in a change in the· total output offset. voltage.
Therefore, the total output offset voltage will not be zero at any temperature other
than room temperature. This means that the desired output accuracy will be affected
by the presence of the output offsets at all temperatures other than 25°C. We can
conclude that thermal drifts are the major problem and not the output offsets.
R1
>-----ova={- RF )v;n
R1
VooT = 0 Vat 25° C
RL
Figure 5-24 Completely compensated inverting amplifier.
To determine the effect of voltage and current drifts· on the performance of an

amplifier, we first need to find the average change in total output offset voltage per
unit change in temperature. This value is obtained from Equation (5-28) and is given
by Equation (5-29):
/lVooT _
AT -
(1 + RF) AV,o + (R )
R1 AT AT
F
ll/10 (5-29)
where !l V00T/AT is the average change in total output offset voltage per unit change in
temperature, in µVf°C, We know that the voltage and current drifts can be either
positive or negative since they are specified as absolute values on the data sheets.
Therefore, to obtain the maximum possible average change in total output offset
voltage per unit change in temperature, we shall assume that the two drift effects are
cumulative (additive). In other words, the !lV00T/!lT value obtained from Equation
Sec. 6-6 ThermalDrift 177

(5-29) will also be an absolute value,. meaning that it could be either positive or
negative. We can now obtain the maximum possible change in total output offset
voltage A V00T resulting from a change in temperature AT by multiplying both sides of
Equation (5-29) by AT. Let us define this .maximum possible change in total output
offset voltage A V00T. as the "error voltage" and denote it by Ev. Therefore, from
Equation (5-29), we heve
AVooT = (1 + ~:)(~ 0) AT+ (Rp)(!?) AT

Ev= (1 + ~:) (~ 0) AT+ (Rp)(f;) AT (5-30)
As we have mentioned before, Ev could be either positive or negative. Thus the

expression for the output voltage for the inverting amplifier in Figure 5-24 may be
written as
(5-31)
where Ev is the error voltage.
But v0 is expected to be directly proportional to Vin, which means that we would
like to have Ev at zero. According to Equation (5-31), Ev= 0 V is possible only if
either voltage and current drifts were zero or change in temperature AT was zero.
Practically, neither of these two conditions is possible. In other words, in practice all
amplifiers will exhibit some finite error Ev resulting from the change in temperature.
However, if the amount of error is excessive for the application we have in mind, we
can then consider a precision-type op-amp. High-performance precision op-amps
are available that feature extremely low thermal voltage and current drifts. For
example, the LH0044A has AV,0/AT= 0.1 µVf°C and A/10/AT= 5pAf°C. But
-remember that we cannot get something for nothing; we also have to pay a higher
price for. these precision-type op-amps than for the general-purpose types. All in all,
it is a trade-off between performance and cost.
It should be noted that the effect of voltage and current drifts is most pronounced
in de amplifiers, especially when the amplitude of the input to be amplified is relatively
small. In fact, voltage and current drifts can also impose a serious problem in ac
amplifiers, particularly if relatively large input voltage is to be amplified by an amplifier
operating at its maximum capacity. The amplifier is said to be operating at its· maxi-
mum capacity when the amplitude of the output voltage is equal to the saturation
voltages. In any given amplifier circuit the saturation voltages are assumed to be
slightly smaller than the supply voltages + Vee and - VEE·
Example 5-8
Refer to the inverting amplifier in Figure 5-24. The op-amp is the LM307 with the fol-
lowing specifications: 1
A[J. = 30 µv;:cmaximum
0
f7~maximum = 300 pA/°C

Vs= ±15V
R1 = 1 k.O, R2 = 100 k.O, and RL = 10 k.O

Assume that the amplifier is nulled at 25°C. Calculate the value of the error voltage
Ev and the output voltage at 35°C if
(a) Vin = 1 mV de
(b) Vin = 10 mV de
Solution. The change in temperature !l.T = 35° - 25° = J0°C. Using this 'change
in temperature, we can: calculate Ev and then V values as shown below.
0
(a) Substituting known values in Equation (5-30), we get
Ev = ( 1 .+ ~~)(~ 0) sr + (Rptrr) sr
= (1 + l~khn)erfc:V)(looq + (IOOkn)(3~tA)(looq
= 30.3 rnV + 0.3 mV = 30.6 mV
For Vin = l mV de, the output voltage V using Equation (5-31) is
0
Va = ( - ~~) Vin ± EP
100 kn) (1 mV) ± 30.6 mV
= - ( Tin
= -100 mV ± 30.6 mV
= -130.6 mV or -69.4 mV
Thus the error voltage of ±30.6 mV de may cause the output voltage to equal
-69.4 mV de or -1~0.6 mV de as the temperature varies from 25 to 35°C.
(b) All the other factors are unchanged except the Vin value; therefore, the value of
error voltage is still equal to ±30.6 mV. Substituting in Equation (5-31) the known
values, we have
V0 = (-~~) Vin ± s;
= (-!~n)(lo mV) ± 30.6 mV
= -1000 mV ± 30.6 mV = -1030.6 mV or -969.4 mV

This means that V0 can be equal to -969.4 mV or -1030.6 mV as the temperature
changes between 25 and 35°C.
Let us now take a. close look at the results in parts (a) and (b). Even though the
amount of error is the same in both cases, the percentage error in V0 is larger· in part
(a) because the amplitude of the inputis smaller .. Thus for a given op-amp circuit and a
given temperature change, the. percentage error in the output voltage increases as the
amplitude of the input signal is decreased. The percentage error in output voltage can
be reduced significantly if we use a precision-type op-amp. .
Example 5-9
Refer again to the amplifier circuit in Figure 5-24. Use the same circuit specifications
that are given in Example 5-8. Assume that the amplifier is nulled at 25°C. If V1n ia
10-mV peak sine wave at 1 kHz:
(a) Calculate Ev and Va values at 55°C.
(b) Draw the output voltage waveform at 55°C.

Solution. The change in temperature AT is (55° - 25°) = 30°C.
(a) First we calculate the error voltage and then the output voltage:
Eu= (1 + ~7)(~ 0) AT+ (Rp)(f~) AT

= (1 + l~ Jr)(3~.fcV)(30°C) + (100 k!l)(3~~A) (30°C)
= 90.9 mV + 0.9 mV
= 91.8 mV de
V0 =(-~;)via± Eu
= (-!TJ!l)(lo mV) ± 91.8 mV

""== -1000 mV peak± 91.8 mV de
This means that the 1000-mV peak ac voltage signal rides either on a +91.8-mV or
a -91.8-mV de level. When the signal rides on a positive de level, it is said to be shifted
up, whereas if it rides on a negative de level, it is said to be shifted down. Thus the
1000-mY peak ac voltage signal is either shifted up or down at the most by 91.8 mV.
(b) The waveform in Figure 5-25 is drawn assuming that the ac voltage signal is shifted
up by 91.8 mY.
Yo
mV
1091.8
T 1000 mV peak
91.8
_j_
0 !+----+------'.&.-----
-908.2
Figure 5-25 Waveform of Example
5-9.
It is clear from Example 5-9 that the error voltage causes a de level shift in ac
amplifiers. A comparatively small de level shift may be tolerated. However, a relatively
large de level shift in an ac amplifier can cause the output waveform to distort. Namely,
a de level shift, depending on its polarity, can clip off either a positive peak or a negative
peak portion of the ac output waveform. Again, to reduce the amount of de level shift
in an ac amplifier, we may use precision-type op-amps.
Thus far we have discussed the 9ffect of drifts on the performance of an inverting
amplifier. The same problems arise in a noninverting amplifier. Figure 5-26 shows the
completely compensated noninverting amplifier.
Recall that the total output offset voltage Equation (5-28) is applicable to invert-
ing as well as noninverting amplifiers. Therefore, the error voltage equation (5-30)

must also. be applicable to both amplifiers, since it is derived from Equation (5-28).
We have seen that the .gain of the noninverting amplifier with an offset-voltage
compensating network is equal to 1 + [Rp/(R1 + Re)] (see Figure 5-26). Therefore,
the expression for the output voltage of noninverting amplifier may be written as
(5-32)
where
Remember that if Re < R1, the voltage gain of the noninverting amplifier becomes
equal to (I + Rp/R1).
Example 5-10
Repeat Example 5-8 for the noninverting amplifier shown in Figure 5-26. Assume
that s;« R1,
Solution. The error voltage E. is the same as in Example 5-8; that is, E. = 30.6 mV.
(a) If Vin = 1 mV de, then
Va = (1 + !;) Vin ± E.
= (UH)(l mV) ± 30.6 mV
= +70.4mVor +131.6mVdc
(b) If Vin = 10 mV de, then
Va = (101)(10mV) ± 30.6 mV
= +979.4 mV or +1040.6mV de
R,
~-t----ov = (1 + _R_F_) v
o A, + Re ,n
V ooT = 0 V at 25° C
Figure 5-26 Completely compensated noninverting amplifier.

5-7 EFFECT OF VARIATION IN POWER SUPPLY VOLTAGES
ON OFFSET VOLTAGE
In the preceding section we studied the effect of input offset voltage and input offset
current thermal drifts on the output voltage of inverting as well as noninverting
amplifiers. As we have mentioned before, the V,0, 110, and 18 values are also susceptible
to the changes in the supply voltages+ Vee and - VEE· Obviously, because the op-amp
is capable of amplifying de inputs, it is sensitive to changes in its supply voltages.
This section is concerned with the effect of variation in supply voltages + Vee and
- VEE on the values of V,0, 110, and 18 and, in turn, the effect of changes in V,0, /10,
and 18 on output offset voltage.
Once we select the specific values for supply voltages + Vee and - VEE in a given
op-amp amplifier, we do not change them deliberately. However, sometimes these
voltages may change as a result of poor regulation and filtering. A poorly regulated
power supply gives different values depending on the size and type of load connected
to it. On the other hand, a poorly filtered power supply has a ripple voltage riding on
some specific de level.
Figure 5-27(a) shows the input bias current versus supply voltage curve for the
LHOOOl op-amp. A glance at output offset voltage V010 [Equation (5-16)] reveals that
for a given value of RP any change in /8 causes a change in V0,a. Of course, you will
recall that w~ can use the RoM resistor to minimize the effect of /8 or of changes in it
on the output offset voltage V01a.
Even though input bias currents change due to the change in supply voltages,
the input offset current should remain relatively constant because it is the absolute
value of the difference between two input bias currents [see Figure 5-27(b)]. Thus, in
practice, if we use a proper value of the RoM resistor in a given amplifier circuit,
I I I I
80 ._ TA"' -56° c - 8 ,-. -
~ ~ TA"' -56° c
E. 60 - - E. 6
...c c
~
~:, :;
u
o
..."'
:.0
...
40 - ' TA"'+25°C
- !
0
4 -
TA"' +25° C
-
:,
c.
...
:,
.s c.
c
20 ._ - 2 - -
TA"' +125° c TA"' +125° C
0 I I 0 I I
5 10 15 20 5 10 15 26
Supply voltage (±V) Supply voltage (±V)
(a) (b)
Figure S-27 (a) Input bias current I 8, versus supply voltage for LHOOOl op-amp, (b) Input
offset current /;0, versus supply voltage for LHOOOI op-amp. (Courtesy of National Semi-
conductor.)

there will-be a negligible change in the current-generated output offset voltage due to
the change in supply voltages. Therefore, manufactureres do not furnish curves like
those in Figure 5-27 for all op-amps.
Recall that the supply voltages change because of poor regulation and filtering.
For a given op-amp any change in the values of the supply voltages results in a change
in the input offset voltage, which in turn causes a change in the output offset voltage.
The change in op-amp's input offset voltage caused by variations in the supply voltages
is generally specified on the data sheets by a variety of terms: The input offset
voltage sensitivity, the power supply irejection ratio, the power supply sensitivity, and
the supply voltage rejection ratio are some of them. All of these terms are equivalent
since they convey the same information. These terms are expressed either in microvolts
per volt or in decibels. For example: The supply voltage rejection ratio (SVRR) for the
µA741 is!!. V1o/!!.V = 150 µV/V maximum and it is typically 20 log(!!. V/!!. Vi.) = 96 dB
for the LM307, where !!. Vis the change in supply voltages +
Vee and - VEE, and !!. Vi.
is the resulting change in the input offset voltage.
Given a supply voltage rejection ratio in microvolts per volt, we can obtain an
equivalent value in decibels (dB) or vice versa. For instance, SVRR (!!.Vi./!!. V) of
150 µV/V is equivalent to
20 log (svkR) = 20 log (!!.1'.',~/!!.V) = 20 log (150 ~V/V) = 20 log(:~~)= 76.48 dB
Similarly, a SVRR of 96 dB is equivalent to 15.85 µV/V as follows. Since 20 log

(1/SVRR) = 96 dB,
log (svkR) = ~~
1
SVRR = 1Q4.8
l
SVRR = 104.8
= 15.85 µV/V
Note that the higher the value of SVRR in dB, the lower is the change in input offset
voltage due to the change in supply voltages, or in other words, the lower the value of
SVRR in µV/V, the better for op-amp performance. In fact, ideally the value of
SVRR in µV/V should be zero.
Now we should like to find for a given amplifier the change in output offset
voltage due to the supply voltage rejection ratio. Refer again to the completely
compensated inverting amplifier circuit shown in Figure 5-24. Let us assume that the
amplifier is nulled initially. Suppose that after the circuit is in operation for a while,
the supply voltages change in value due to poor regulation. We know that any change -
in the supply voltages results in a change in the input offset voltage. And according
to Equation (5-8), any change in input offset voltage results in a change in the output
offset voltage. Therefore, using Equation (5-8) we can establish a relationship between
the change in output offset voltage and SVRR as follows: ·
v•• = (l + ~:) v,. (5-8)
Sec. 5-7 Effect of Variation in Power Supply Voltages on Offset Voltage 183
where (1 + RF/R1) is a constant for given values of R1·and Rp. Therefore, the average
change in V00 per unit change in supply voltages can be
f:..:vo = (1 + !:) (~o) (5-33)
Multiplying both sides of Equation (5-33) by AV, we get
AV00 = (1 + !:)(~ 0) AV (5-34)
where A V00 = change in output offset voltage (volts)

AV= change in supply voltages+ Vee and -VEE
~0 = supply voltage rejection ratio (µV/V)
Remember that A V00 is a de voltage, and it could be either positive or negative. Thus
all practical op-amps are affected by changes in the supply voltages, and therefore
regulated supplies are recommended.
Example 5-11
The amplifier in Figure 28(b) is nulled when the low de supply is 20V [see Figure 5-28(a)].
Because of poor regulation, low de voltage varies with time from 18 to 22 V. Determine
(a) the change in the output 'offset voltage caused by the change in supply voltages,
. and /b) the output voltage V0, if Vin = 10 mV de. The op-amp is the LM307 with
SVRR = 96dB. .
Solution
(a) The variation in low de voltage from 18 to 22 V, compared to its desired value of
20V (+Vee= +10 V, and -VEE= -10 V) implies that the change in supply voltages
AV= 2 V. The supply voltage rejection ratio in µV/V equivalent to 96 dB is
20 log (sv~R) = 96 dB
1 )
log ( SVRR 96
= 20
1
SVRR = lOU
SVRR = 15.85 µV/V
That is,
~0 = 15.85 µV/V
Substituting known values in Equation (5-34),
1~Jf)(15.8µV/V)(2V)
AV00 = (1 +
= (101)(31.6)(10-6)
, = 3.20mV
It is worth noting that the AV value is the same regardless of whether it is com-
puted from the change in low de supply or change in + Vee or - V.sB· In this example,
as a worstcase situation, suppose that - VEE remains constant at -10 V; then the
+ Vee has to vary from 8 to 12 V as a result of change in low de voltage. This means
184 The PracticalOp-Amp Chap. 5

+Vee
r:··~
R c
+ 10 kn
Low de
supply
R
1okn 0.01 µF
-Vee
(al
RF
R1 100 kn
lkn
Figure 5-28 (a) Supply voltages for

the inverting amplifier'.(b) Inverting
(bl amplifier of Examples 5-11 and 5-12.
that the change !J. Vin supply voltage+ Vee is 2 Vin either direction from lOV. In fact,
for some op-amps the positive ( - VEE constant) and negative (+Vee constant) supply
voltage rejection ratios are specified on the data sheets. For example, the µA1458C
op-amp has positive power. supply sensitivity = 30 µV /V and negative power supply
sensitivity = 30 µV/V.
(b) The total output voltage, including the change ·in output offset voltage AV 00, is
given by
R,) . .,,,.1 .. ±' . .u voo
' vo = ( -R A
1 '
. = ( ·-Tkn
100 kn) (10 mV): ± 3.2 mV
= -1000 mV ± 3.2 mV
= -1003.2 mV or -996.8 mV
It can be seen from Example 5-11 that the variation in supply voltages could be
troublesome in small-signal op-amp amplifiers.
Sec. 5- 7 Effect of Variation in Power Supply Voltages on Offset Voltage 185

Example S-12
Referring to Figure 5-28(b), suppose that the circuit is nulled when the voltage across
terminals + Vee and - VEE measures 20 V de. Also suppose that, because of poor
filtering, 10 mV rms ac ripple is measured across the terminals + Vee and - VEE·
While the input signal v1n = 0 V, how much ripple voltage can we expect at the output
if the op-amp is the LM307?
Solution. The SVRR = 15.85 µV/V for the LM307, and because of poor filtering,
ll V = 10 mV rms. ·Substituting known values in Equation (5-34), we get an output
ripple voltage of
llVoo = (1 + lfk~!l)(15.8iµV)(10mV)
= 16 µV_
5-8 CHANGE IN INPUT OFFSET VOLTAGEAND INPUT OFFSET

CURRENT WITH TIME
Under operating conditions the characteristics of all semiconductor devices, such as

diodes and transistors, change to some extent with time. The amount of change in
semiconductor characteristics then affects the performance of a circuit, in particular
its linearity and accuracy. Since an op-amp is composed of transistors and diodes
among other things, the op-amp's input offset voltage and input offset current changes
(drifts) with time. For long-term stability the amount of change in input offset voltage
and input offset current with time is crucial. On some op-amp data sheets the input
offset. voltage and input offset current drifts with time are specified and are denoted by
llVi01M and ll/10/M, respectively. Generally, llV10/llt is expressed in microvolts per
week and ll/10/ llt in nanoamperes per week. For example, for the LH0041 C the typical
values of llV10/llt = 5 µV/week and ll/10/M = 2 nA/week . .Remember that the drifts
in V10 and /10 with time are the absolute values, meaning that V,0 may increase or ··
decrease typically by 5 µV/week in the case of the LH0041C. Similarly, the typical
change in /10 could be as much as eitherv-l-Z nA or -2 nA per week for the LH0041C.
Thus, with the help of Equation (5-28), we should be able to determine the
maximum possible change in output offset voltage as a function of input offset voltage
and input offset current drifts with time over a certain time period.
vooT = ( l + ;~) Vio + (Rp)l,o (5-28)
Therefore, the average change in V00r per unit time is
llV00r =
Lit
(1 + RP)
R 1
flV,
flt
0 + (R p
) flf,0
flt
(5-35)
I
Multiplying both the sides of Equation (5-35) by Lit, we get
flV00r = (1 + ;~)(/ll;o) flt+ (Rp)(t;a) flt (5-36)
where flt = time elapsed (weeks)

~0 = input offset voltage drift with time (volts/week)

~0 = input offset current drift with time (amperes/week)
A V00r = change in output offset voltage (volts)
Note that Equation (5-36) is applicable to noninverting as well as inverting amplifiers.

Thus, in practice, the output offset voltage in all op-amp circuits will change
with time. To maintain the desired accuracy and linearity of a system it is necessary
to calibrate all the op-amps in that system periodically.
Example 5-13
Suppose that the circuit in Figure 5-24 is initialJy nulled. Assume also that room
temperature and the voltage across terminals+ Vee and -VEE remain constant. Deter-
mine the maximum possible change in output offset voltage after one month if the op-
amp is the LH0041C. Assume that R1 = 1 k!l, RP= 100 k!l, and RL = 10 kn.
Solution. For the LH0041C, AVi0/At = 5 µV/week and AI,0/At = 2 nA/week. Due
to the time drift, At = 4 weeks,
1
AVooT = ( .+ ~:) ( Al;0) At + (Rp)( ~: 0) At
= (1 + 1~k~0)cs x 10-6)(4) + uoo k0)(2 x 10-9)(4)
= 2.02 mV + 0.8 mV = 2.82 mV
5-9 OTHER TEMPERATURE- AND SUPPLY VOLTAGE-SENSITIVE

PARAMETERS
The error voltage. in the op-amp's output voltage is not the only possible result of
temperature changes. A collection of other temperature-sensitive characteristics for
the µA 74lC op-arrip is shown in Figure 5-29. The curve in Figure 5-29(a) shows that
the input resistance R, of the 741 C op-amp increases with an increasing temperature,
when supply voltage equals ± 15 V. Recall that the input resistance of an op-amp is
defined as the equivalent resistance which would be measured at either an inverting· or
noninverting input terminal with the other terminal· grounded, A changing input
resistance, which is the load resistance on the signal source, can cause a drifting input
signalamplitude. ·In fact, for a given signal source, the amount of drift in input signal
amplitude depends on the relative· values of the external components and also on the
operating mode of the op-amp amplifier (inverting or noninverting). Thus for a given
signal source and op-amp circuit, we can minimize the drift in input signal amplitude
without affecting the desired performance of the circuit if we select relatively .small
values for external components.
· The power consumption as a function of ambient temperature curve for the
741C op-amp is shown in Figure 5-29(b). As can be seen from this curve, the power
consumption, which is the de power required to operate the op-amp under no-load
conditions, decreases with increasing ambient temperature.
Finally, as shown in Figure 5-29(c), the output short-circuit current of the 741C
· op-amp decreases with an increasing temperature. In other words, the amount. of
Sec.5-9 Other Temperature· and Supply Voltaqe-Sensitb/e Parameters 187

;1
II
10 100
V5 = 20 V
70
90
~
a::E 60 E
c
.,o
c
s
a.
80
.
!9
·.;;
3.0
E
ac
e 0
u 70
:ia. ~
2.0 ::0
.:: CL
60
V5=:t15V
1.0 50
0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70
Temperature (°Cl Temperature (°Cl
(al (bl
30
28
~
.s 26
c:
e
..5
o
:,
24
e
-~
22
0
s:
f./l
20
18
0 10 20 30 40 50 60 70
Temperature (°Cl
(cl
P'~ure 5-29 (a) Input resistance as a function of temperature. (b) Power consumption as a
function of temperature. (c) Output short-circuit current as a function of temperature.
(Courtesy of Fairchild Camera and Instrument Corporation.)
output current obtainable with the output terminal shorted to ground or to either
+ Vee or - v EE supply decreases with inJreasing temperature.
Figure 5-30 shows a typical collection of supply voltage-sensitive parameters of
the 741 C op-amp. The open-loop voltage gain in dB increases as the supply voltage-
values are increased, as shown in Figure 5-30(a). The open-loop voltage gain varies
between 82 and 100 dB as the supply voltages are changed from ±2 V to ± 18 V,
respectively, when the ambient temperature is 25°C. Note that the voltage gain in dB
is equal to 20 log (Vout/V1 0).

40r---r---,.--..---------~
36 0° c s T" s 10° c
~ 32
R~ > 2 kfl
en
a:,
-0
95
"i. 28
c 90 '5 24
-~ &
g 20
E
0
85 ~
8, 16
> $
80 ~ 12
I a
75
4
0 __.___ ..__.....1,.. _ __,, _ _.,
2 4 6 8 10 12 14 16 18 20 5 10 15 20
Supply volta~ (±Vl Supply voltage (±V)
(al (b)
15....--.....--~--~-----~ 100 .---..---.---~---~-~

0° c = r" c + 10° c r" = 25° c
14
s
+I
80
&
c
12
Ic
~ 10 .!2 60
~
o> 8
e
Cl.
~
-g"' 6
8 40
E
e
0
4
r
&.
E
E 20
0
(.J
2
o....__........._ ........__ ..__ .........~ ........--"' 0 ..__.._
_ _.___ ,___ _.__ __,,_---I
5 10 15 20 5 10 15 20
Supply voltage (±V) Supply voltage l±V)
(c) (d)
as
Flgme 5-30 (a) Open-loop voltage gain a function of supply voltage. (b) Output voltage
swing as a function of supply voltage. (c) Input common-mode voltage range as a function
of supply voltage. {d) Power consumption as a function of supply voltage. (Courtesy of
Fairchild Camera and Instrument Corporation.)
The curve in Figure S-30(b) shows the output voltage swing as a function of
supply voltages ± Vcc and - V.u, The peak-to-peak output swing depends on the
value of the supply voltages and is always less than that value. For example, when the
supply voltage is ±15 V, the peak-to-peak output swing is 26 V, as shown in Figure
5-30(b).
Figure 5-30(c) shows' that the input common-mode voltage range (CMVR)
increases with increasing supply voltage values. That is, the range of common-mode
Sec. 5-9 Other Temperature- and Supply Voltage-Sensitive Parameters 189

input voltage over which the op-amp operates within specifications increases when
the supply voltage values are increased. The CMVR varies between ±2 V and ± 14 V
as the supply voltages are changed from ±5 V to ± 17.5 V, respectively [see Figure
5-30(c)]. For instance, when the supply voltage is ±5 V, the common-mode voltage
could be as high as either +2 V or as low as -2 V.
The power consumption as a function of supply voltage curve is shown in
Figure 5-30(d). It can be seen here that the amount of de power required to operate
the op-amp under no-load conditions increases with an increase in supply voltages.
Note that the curve is drawn at 25°C.
5-10 NOISE
A major source of interference with the desired signal in electronic systems composed
of either discrete (separate) components or integrated circuits is noise. Any unwanted
signal associated with the desired signal is noise. Because it is the combined effect of
many sources, noise is random in nature and hard to predict or analyze. In any electro-
nic system, noise can come from many external sources as well as be self-induced, a
result of the circuitry itself. Examples of external noise sources are switching of
rotating machinery, ignition systems, and various control circuits. Natural phenome-
na such as lightning may also be external noise sources.
The self-induced or internal noise may be caused by the ac random voltages and
currents generated within conductors and semiconductors of one circuit as a result
of the switching of another circuit. The rate of change of current and voltage per unit
of time, the speed of operation of the circuit, and the type of coupling between two
circuits are some of the factors that determine the amount of noise induced in a given
circuit.
There are different types of noise phenomena associated with op-amps: Schottky
noise, thermal noise, and 1//noise are the most important among them. The thermal
noise increases with an increase in temperature. Like thermal noise, the amount of
Schottky noise is greater with wider bandwidths and larger resistances; on the other
hand, 1/f noise increases with a decrease in frequency f. Sometimes, manufacturers
provide the data on noise, as shown in Figure 5-31. Figure 5-31(a) and (b) show the
input mean square noise voltage (V2/Hz) and mean-square noise current (A2/Hz) at
various frequencies for the µA741 op-amp. These noise characteristic curves indicate
that the noise level is higher at lower frequencies. Broadband noise versus source
resistance curves for the 741 op-amp are shown in Figure 5-3l(c). A glance at these
curves reveals that the wider bandwidths for a given value of source resistance generate
more noise; also, larger source resistances for a given bandwidth appreciably increase
the noise level.
To reduce the effect of electr~cal noise on ICs, several schemes have been
commonly used. Physical shielding of the I Cs and associated wiring helps to prevent
external electromagnetic radiation from inducing noise into the internal circuitry.
Special buffering and filtering circuits can be used between the electronic circuits and
signal leads. To provide a path for any radio frequency (RF), all linear IC power
supply terminals should generally be bypassed to ground. The breadboard layout

-o=
V5 = 15 V
;:; T,.. = 25° C
:r 1 <>22
....
....
5
c:
1023
3
u
51
'sc:
..
e
:,
1024
i
c:
m 1 ()215
~
1011 L-- .................................... ..__ ............................. __._ ....... ......_. 1028 .__ ................................ ..._....._ ............... __.__.. ...... ...__.
10 100 1 kn 10 kn 100 kn 10 100 1 kn 10kn 100 kn
Frequency (Hz) Frequency ( Hz)
(al (b)
I
100
~
>
..
..;!,
:,
Q. 10 10-100 kHz
..
.!:
0
1~ 10-10'kHz
e
51 10-1 kHz
'sc:
~
~
0.1
100 1 kSl 1okn 100 kn
Source resistance (n)
(cl
Figure 5-31 (a) Input noise voltage versus frequency. (b) Input noise current versus
frequency. (c) Broadband noise for various bandwidths. (Courtesy of Fairchild Camera
and Instrument Corporation.)
should be such that the bypass capacitors are as near the JC terminals as possible.
Internal noise generation can be reduced by keeping input and output lead lengths
as short as practically possible. Use one common tie point near the IC for all grounds.
In a high electrical noise environment an IC with a high degree of noise immunity will
minimize the amount of special care needed for proper circuit operation.
Among inverting, noninverting, and differential amplifiers, the latter type offers
the best immunity to induced noise. The differential amplifier circuit is shown in
Figure 5-32. In this circuit, v., is the desired differential input signal to be amplified,
Sec. 5-10 Noise 191

Difference input For maximum CMAR
voltage vd R1 = R2, RF= R3
>---.....a Vo =- Ao yd + vno
where vno = output noise
Figure 5-32 Noise in a differential amplifier.
and v,,, is the noise voltage induced into each input terminal with respect to ground.
Since R1 = R2 and R, = R3, the voltage at the inverting and noninverting input
terminals will be amplified by the .same factor R,/R1• Thus, if the noise voltage to
ground at the inverting terminals ls the same as the noise voltage to ground at the
noninverting terminal, the noise voltage at the output should be negligibly small if
not zero. Thus the ratio of the output noise voltage to the input noise voltage in
practice will be much smaller than 1.
With proper component selection such that both inverting and noninverting
input impedances are equal, both of the induced noise voltages v111 are equal in
amplitude and phase. Therefore, in differential amplifier circuits the noise voltages at
the output are greatly reduced.
S-11 COMMON-MODE CONFIGURATION AND COMMON-MODE

REJECTIONRATIO
When the same input voltage is applied to both input terminals of an op-amp, the
op-amp is said to be operating in an common-mode configuration. Since the input
voltage applied is common to both the inputs, it is referred to as a common-mode
voltage Vcm, as shown in Figure 5-33. A common-mode voltage Vcm can be ac, de,
or a combination of ac and de.
Because ideally an op-amp amplifies only differential input voltages, no
common-mode output voltage Vocm should appear at the output. However, due to
imperfections within an actual op-amp, some common-mode voltage Vocm will appear
at the output. The amplitude of this Vocm is very small and often insignificant compared
to Vcm· Therefore, in practice the ratio of the output common-mode voltage Vocm to
the input common mode voltage /Jcm, which is called the common-mode voltage
gain Acm, is generally much smaller than 1. In equation form,
A = Vocm (5-37)
cm Vcm
Ideally, the common-mode voltage gain Acm is zero.

Although Acm is usually not specified on the op-amp data sheets, Acm can be

~---o = Acm Yem
V ocm
where A~m< 1 typically
"cm
(a)
I
>--+--0\locm • Acm"cm
(b)
Figure 5-33 Op-amp connected in common-mode configuration. (a) Without

feedback. (b) With feedback.
calculated for a given op-amp by applying a known· value of common-mode input

voltage tlcm and measuring the resultant output common-mode voltage Vocm· Op-amp
manufacturers usually list a common-mode rejection ratio CMRR. The CMRR is
defined in several essentially equivalent ways by the various manufacturers. Generally,
it can be defined as the ratio of the differential gain AD to the.common-mode gain Acm,
that is, ·
CMRR = AD (5-38)
· Acm
Note that in Figure 5-33(a), AD is equal to internal gain A of the op-amp.

The CMRR can also be expressed as the ratio of the change in input offset
voltage to the total change in common mode voltage. Thus
CMRR = V,o (5-39)
Vcm
From Equations (5-37) and (5-38), we can then establish the relationship betweelf
the ti.cm and CMRR:
CMRR= AD= AD
Acm izx:
ADtlcm
=--
Sec. 5-11 Common-Mode Configuration and Common-Mode Rejection Ratio 193

l
I
!
(5-40)
Equation (5-40) indicates that the higher the value of CMRR, the smaller will be
the amplitude of the output common-mode voltagev0cm· Generally, the CMRR value
is very large and is therefore usuallyspecified in decibels (dB), where
CMRR (dB) = 20 log (i:) (5-4la)
or from Equation (5-39),

CMRR (dB)= 20 log (v; Vcm )
lo
(5-4lb)
The value of CMRR listed on the data sheets is specified for the open-loop
common-mode op-amp configuration as shown in Figure 5-33(a). For example, for
µA741C op-amp CMRR (dB)= 90 dB. However, the CMRR value listed on the data
sheets can be used as an approximate value for the closed-loop common-mode
configuration shown in Figure 5-33(b). Being the ratio of differential gain AD to the
common-mode gain A.m, CMRR should be the-same for open-loop as well as closed-
loop common-mode configurations [see Equation (5-38)].
Whether CMRRis defined as in Equation.(5-38) or (5-3~). it is a measure of the
degree of matching between two input terminals; that is, the larger the value of CMRR
(dB), the better is the matching between the two input terminals and the smaller is
the output common-mode voltage Vocm· On the other hand, a large voltage Vocm for
a given common-mode input voltage v.m is an indication of a large degree of imbalance
between the two input terminals or of poor common-mode rejection. Thus, in practice,
it is advantageous to use op-amps with higher CMRRs since these op-amps have
better ability to reject common-mode voltage such as 60-Hz induced noise voltages.
The CMRR is a function of frequency and decreases as the frequency is increased as
100
90 Vs"'±16V
TA .. 25° c
;;; 80
~
.2 70
ec
.2 60
&l
-~ 50
]"' 40
E
c
0
E 30
E
8 20
10
Figure 5-34 Common-mode rejection
ratio as a function of frequency.
10 100 1 k!l 10 k!l 100 k!l 1 M 10 M (Courtesy of Fairchild Camera and
Frequency (Hz) Instrument Corporation.)
The Practical Op-Amp Chap. 5

Example 5-14
In the circuit of Figure 5-32, if R1 = R2 = I kO, RP= R3 = 10 kO, ·vd = 5 mV
sine wave at I kHz, and t•n, = 2 mV at 60 Hz, calculate (a) the output voltage at 1 kHz
and (b) the amplitude of the induced 60-Hz noise at the output. The op-amp is the
µA741 with CMRR (dB) = 90 dB.
Solution
(a) The closed-loop differential gain of the circuit is
A _ Rp _ 10 kO _ JO
D_Ri_Tfil_
I
since the input signal is applied in a differential mode, it is amplified by the differential
gain Av. Therefore, at 1 kHz the output signal is
v0 = Avvd = (10)(5 mV) = 50 mV
(b) The 60-Hz noise voltage vn, appears in common mode at the input terminals of
the op-amp; therefore, t'n1 = Vern· Thus, using Equation (5-40), we can calculate the
value of output common-mode voltage v cm· In order to implement Equation (5-40),
0
we first have to convert the CMRR (dB) value into its equivalent numerical value.
The CMRR (dB) = 90 dB implies that
20 log CMRR = 90 dB
90
logCMRR = 20
CMRR = 104-S
CMRR = 31,622.78
Therefore,
AvVcm (10)(2;mV)
Vocm = CMRR = 31,6i2.78
= 0.63 µV at 60 Hz
Thus the op-amp used in the differential mode is an effective circuit in reducing
noise problems. since the 60-Hz output is much smaller than the input induced 60-Hz
noise. The differential-mode op-amp circuit is particularly helpful in reducing induced
input noise voltages when the smali-amplitude differential input signal is being ampli-
fied.
SUMMARY
1. All operational amplifiers have finite values of input offset voltage, input offset current,
and input bias current. These values. result in a de output offset voltage.
2. The op-amp can be nulled by using an offset-voltage compensating network. The amount
of output offset voltage due to input bias currents can be significantly reduced if we use
offset minimizing resistors.
3. The input offset voltage and current tend to drift with change in temperature; the drift
results in a finite de error voltage in the desired output voltage at temperatures other than
25°C.-
4, The amount of error voltage affects the accuracy of the de amplifiers and limits the
amplitude of the ac signal that can be amplified without distortion.
Chap. 5 Summary 195

5. The input offset voltage of an op-amp changes with the change in supply voltages; the
change in input offset voltage in turn causes a change in output offset voltage. To keep
the change in output offset voltage to a minimum, use a regulated power supply or use
an op-amp with a relatively high supply voltage rejection ratio.
6. The op-amp's input offset voltage and input offset current changes with time. Therefore,
for better long-term stability, use an op-amp with smaller drifts in input offset voltage
and current per unit of time, and also calibrate the op-amp circuit periodically.
7. The input resistance, power consumption, and output short-circuit current of an op-amp
are temperature-sensitive parameters. On the other hand, the open-loop voltage gain,
output voltage swing, power consumption, and common-mode voltage range are all
supply voltage-dependent parameters.
8. Any unwanted signal associated with the op-amp's desired output signal is noise. Schottky
noise, thermal noise, and 1/f noise are the most important types of noise associated with
op-amps.
9. The differential op-amp offers the best immunity to induced noise, since input noise
voltages appear as common-mode voltage.
10. The common-mode rejection ratio of an op-amp is the ratio of differential gain to the
common-mode gain. The larger tp.e CMRR value, the smaller is the common-mode
output voltage. ·
QUESTIONS
5-1. Define input offset voltage and explain why it exists in all op-amps.
5-2. Why is it necessary to use an external offset voltage compensating network with
practical op-amp circuits?
5-3. What is the offset minimizing resistor RoM?
5-4. Why is a resistor RoM not needed in differential op-amp circuits?
5-5. Why is the output offset voltage generated by the input bias current always larger than
that generated by the input offset current?
5-6. What are the factors that affect the input offset voltage, input bias, and input offset
currents?
5-7. What is thermal drift? How does it affect the performance of an op-amp circuit?
5-8. What is error voltage? How can it be reduced?
5-9. Define supply voltage sensitivity. What is meant by a poorly regulated power supply?
5-10. What is an electrical noise? What precautions can be taken to minimize the effect of
noise on an op-amp circuit?
5-11. Define the common-mode rejection ratio (CMRR) and explain the significance of a
relatively large value of CMRR.
PROBLEMS
5-1. For the inverting amplifier shown in Figure 5-7(b), if R1 = 100 Q and Rp = 4.7 k!l,
what is the maximum possible output offset voltage V00? The op-amp is an LM307
with V10 = 10 mV and supply voltages ±15 Y.

5-2. Repeat Problem 5-1 if the LM307 op-amp isreplaced by a µA715 for which Via= 5
mV maximum.
5-3. Design an input offset voltage compensating network for the µA 715 op-amp of Prob-
blem 5-2. Draw the complete circuit diagram.
5-4. The µA715 op-amp is to be used as a voltage follower with the offset-voltage compen-
sating network designed in Problem 5-3 (see Figure 5-12). Compute the output voltage
Va if the input is 1 V pp sine wave.
5-5. (a) For the noninverting amplifier of Figure 5-7(a), R1 = 100 n and Rp = 10 kO.
Determine the maximum possible output offset voltage due to (I) the input offset
voltage V,~ and (2) the input bias current 18• The op-amp is an LM307 with Via =
10 mV and 18 = 300 nA.
(b) What value of RoM is needed to reduce the effect of input bias current 18?
5-6. For the inverting amplifier in . Figure 5-21, determine the maximum output offset
voltage Va,,, if the op-amp is an LM.307 with I,a = 70 nA.
5-7: Compute the maximum possible total output offset voltage Vaar in the amplifier cir-
cuits shown in Figure 5-22. Assume that the op-amp is an LM307 with supply voltages
±15 V.
5-8. Repeat Problem 5-7 if the op-amp is a µA741.
5-9. Refer to the inverting amplifier in Figure 5-24. The op-amp is a type 307 with the fol-
lowing specifications:
~a = 30 µVj°C maximum
fT = 0.3 nA/°C maximum
Vs= ±15 V
R1 = 1 k!l, R, = 100 k!l, and RL = 10 kO
Assume that the amplifier is nulled at 25°C. Calculate the value of the error voltage
and the output voltage V at 35°C if
0
(a) Via == 1 mV de
(b) Vin = 10 mV de
5-10. Repeat Problem 5-9 with the type 307 op-amp configured as a noninverting amplifier.
Refer to Figure 5-26.
5-11. The LM311 op-amp is used as an inverting amplifier, as shown in Figure 5-24, with
the following specifications:
A Via = 30 µV/~C Al,o = 10 nA/°C Vs=±15V

AT I ' AT '
R, = 8.2 kO, RL = 101dl
Assume that the amplifier is nulled at 25°C. If Vin is 20 m V peak sine wave at 100 Hz:
(a) Calculate Ev and v0 values at 45°C.
(b) Draw the output voltage waveform at 25°C and at 45°C.
5-12. Repeat Problem 5-11 with the same op-amp reconnected as a noninverting amplifier.
5-13. Referring to Figure 5-24, suppose that the circuit is nulled when the voltage across
terminals + Vee and - VEE measures 24 V.dc. Because of poor regulation, the voltage
across terminals + Vee and - VEE varies with time from 20 to 28 V. Determine:
(a) The change in the output offset voltage caused by the change in de supply.
Chap. 5 Problems 197

(b) The total output voltage V0 if Vin = 5 mV de. The op-amp is the MC1741, and
R1 = 100 0 and R1 = 4.7 kO.
5-14. Repeat Problem 5-13 with Rp = 10 kO and V;n = 10 mV peak sine wave at 100 Hz
Also draw the output waveform.
5-15. Repeat Problem 5-13 if the same op-amp is reconnected as the noninverting amplifier
shown in Figure 5-26. Use the same values for R1 and Rp.
5-16. Referring to Figure 5-26, suppose that the circuit is nulled when the voltage across
terminals + Vee and - VEE measures 30 Y de. Also suppose that because of poor
filtering, 10 mV rms ac ripple is measured across the terminals + Vee and - VEE· While
the input signal v1n = 0 Y, how much ripple voltage can we except at the output if the
op-amp is an LM312 with SYRR = 96dB typical? Use R1 = 1 kO, and Rp =
47 kO.
5-17. Determine the maximum possible change in output offset voltage in the circuit of Figure
5-24 after 6 months if the op-amp is the LH0041C with the following specifications:
L\V /),,/
1),,/0 = 5 µY/week and /),,;• = 2 nA/week
R 1 = 82 Q and Rp = 8.2 kO
Assume that the circuit is· initially nulled and that room temperature and the voltage
across terminals + Vee and - VEE remain constant.
5-18. Repeat Problem 5-17 with the op-amp LH0041 C configured as shown in Figure 5-26.
Use the same specifications as given in Problem 5-17.
5-19. In the circuit of Figure 5-32, if R1 = R2 = 1 kO, Rp = R3 = 47 kO, v4 = 10 mV
sine wave at 1 kHz, and t'ni = 1 mY at 60 Hz, calculate:
(a) The output voltage at 1 kHz.
(b) The amplitude of the induced 60-Hz noise at the output.
The op-amp is the µA741 with CMRR (dB) = 90 dB.
5-20. Repeat Problem 5-19 if the µA741 op-amp is replaced by a LM312 for which CMRR
(dB) = 100 dB typical.
5-21. In the circuit of Figure 5-33(b), R1 = 100 n, RF = 4.7 kO, and the op-amp is µA741
with CMRR (dB) = 90 dB. If the amplitude of the induced 60-Hz noise at the output ·
is 5 mV (rrns), calculate the amplitude of the common-mode input voltage Vcm·
5-22. Repeat Problem 5-21 with the op-amp LM312. Use CMRR (dB) = 100 dB.
EXPERIMENT 5-1
MEASURING AND SETTING OFFSET VOLTAGE
Objectives
In this experiment you will measure the output offset voltage and then use a "nulling"
circuit to set it to zero. Also, you w~I investigate how an output offset voltage may
vary under certain conditions. At the end of this experiment you should be able to:
1. Measure the output offset voltage and then calculate the value of input offset
voltage from it.
2. Design an offset voltage compensating network.
3. Set the output offset voltage to zero using a "nulling" circuit.

4. Discuss the effect of feedback and change in supply voltages on the output
offset voltage and in turn on input offset voltage.
Equipment
J. Variable low-voltage power supply
2. Multimeter
Materials
1. 741 op-amp
2. 307 op-amp
3. 100-kQ resistor
4. 10-kQ resistor
5. 1-kQ resistor
6. Assortment of resistors chosen by the experimenter
Procedure
J. Connect the circuit as shown in Figure E5-l.l(a) using the 741 op-amp.
2. Turn the de supply voltage(± 15 V) on. With the multimeter set to the de voltage
mode, measure the output offset voltage V00 and record it in Table E5-1.1.
3. Measure the 1-kQ and 100-kQ resistor values and then connect the circuit using
the 741 op-amp as shown in Figure E5-1.l(b). Repeat step 2.
TABLE E5-1.1
Yoo in open-loop Yoo in closed-loop

Op-amp configuration configuration
741
307
TABLE ES-1.2
Supply voltage, ± Vs Output offset Input offset

Op-amp (V) voltage, Yoo voltage, V,0
±6
±9
741
±12
±15
±6
±9
307
±12
±15
Exp. 5-1 Measuring and Setting Offset Voltage 199

l
i
R1 RF
ikn ioo kn
+15V
+15V
7 7
3 2
6 6
v; v.: v; V°".
2 3
4 4
-15V -15 V
(a) (b)
Figure E5-l.l (a) Offset voltage in an open-loop op-amp circuit. (b) Offset
voltage in a closed-loop op-amp circuit.
4. Change the supply voltage(± Vs) from ±6 V through ±15 V and measure the
corresponding output offset voltage V00• Record these values in Table E5-I .2.
5. Calculate the magnitude of input offset voltage V,0 from Equation (5-1. I). For
maximum accuracy use the measured values of R1 and Rp.
(5-1.1)
Complete T~ble E5-l.2.
6. Next connect the 10-kil potentiometer as shown in Figure E5-l.2. Note that the
supply voltage is set to ± 15 V. Connect the voltmeter at the output terminal and
vary the potentiometer until the meter reads "zero" volts. (Note: Do not expect
exact zero output since it may be difficult to obtain.) However, for maximum
accuracy be certain to use the appropriate meter range.
7. Repeat steps 1 through 5 using the 307 op-amp.
1 kn 100 kn
+15 V
7
2
6
>--o--- v 00 == 0 v
3 5
4
-15 V
Figure E5-1.2 Offset-null arrangement

lOkn of the 741 op-amp.
200 The Practical Op-Amp Chap .. 5

8. For the 307 op-amp, design an offset voltage compensating network using the
supply voltage of ± 15 V and the corresponding Vio value.
9. Construct the compensated op-amp circuit as shown in Figure E5-l.3. Connect
the voltmeter at the output terminal and adjust the Ro potentiometer for "zero"
output voltage. Remember that you may not be able to force the output voltage
to exactly zero.
R,
1 kfl 100 kn
+15V
7
2
+15 V
6
~<>---V 00
:: 0V
3
4
-15 V
-15 V
Figure ES-1.3 Op-amp with offset

voltage compensating network.
Questions.
1. Compare the V00 value measured in open-loop configuration with that in

closed-loop configuration and give the reason(s) for this difference.
2_. 'Why is input offset voltage not directly measured between the two input
terminals?
3. Based on the input offset voltages obtained (at ±15 V) for the 741 and 307,
which op-amp is better balanced? Explain. ,
~- Discuss briefly the effect of feedback and change in supply voltage on the
. . input/output offset voltage.
5. Referring to the equivalent circuit of the 74l OP-lllttJ>, discuss why nulling is
possible with offset null circuitry (10-k.O potentiometer).
6. Which one of the two offset null circuits is easier to use in setting the output
offset to zero? Explain.
EXPERIMENT5-2
USING THE OFFSET VOLTAGE CQMPENSATINGNETWORK
Objectives
In this experiment you will investigate the versatility of a compensating network. At
the end of this experiment you should be able to:
1. Measure the output offset voltage in a noninverting amplifier, differential
amplifier, and voltage-follower circuits.
EXJ;>. 5-2 Using the Offset Voltage Compensation Network 201

2. Set the output voltage in the circuits above to zero using the same compensating
network.
Equipment

2. Multimeter
Materials
1. 307 op-amp
4. Assortment of resistors chosen by the experimenter
Procedure
1. Construct the noninverting amplifier of Figure E5-2.1. Measure the output
offset voltage and record it in Table E5-2. l.
2. Connect the compensating network shown in Figure E5-2.2 using the same
component values for R,., Rb, and Re as in Experiment 5-1. Next, in Figure
E5.,.2.1 disconnect the left-side terminal of R1 from ground and reconnect it to
point C of the compensating network of Figure E5-2.2.
R,
1 kn ioo en +15 V
+15 V
7
2
3 -15 V
4
-15V
Figure ES-2.1 Offset voltage in a noninverting amplifier Figure ES-2.2 Offset voltaae compen-
(t11n = 0 V). sating network.
3. With the voltmeter connected at the output terminal of the op-amp, vary the
potentiometer R,. until output v9ltage is zero. Remember that you may not be
able to force output voltage to exactly zero.
4. Next, connect the voltage follower shown in Figure E5-2.3. Measure output
offset voltage with the voltmeter and record it in Table E5-2.1.
5. Using the compensating component values obtained in Experiment 5-1, recon-
nect the voltage-follower circuit as shown in Figure E5-2.4.

+15 V
7
2
6
v:
3
4
Figure E5-2.3 Offset voltage in voltage

.L.15 V follower (1110 = 0 V).
+15 V
Re
R,s.--'\il\/V\--+----1\/1/\r-r---~
+15 V
-15V 7
2
6
>--o---ov 00 :: ov
3
4
-15 V
Figure E5-2.4 Compensated voltage follower (1110 = 0 V).
6. With the voltmeter connected at the output, vary the potentiometer Ra until
output voltage is reduced to ze~o.
7. Connect the differential amplifier of Figure E5-2.5 and measure the output offset
voltage. Record the measured value in Table E5-2. l.
8. Do the following modifications in Figure E5-2.5: Disconnect the lower end of
R3 -and reconnect it to point C of the compensating network of Figure E5-2.2.
9. With the voltmeter connected' at the output terminal, vary the potentiometer Ra
until the output voltage is reduced to zero.
TABLE EI-Z.1
Configuration
Noninverting emplifier
Voltage follower
Differential amplifier
Exp.5-2 Using the Offset Voltage Compensating Network 203

RF
1
1 kn 100 kn
+15 V
7
2
6
V""
1 kn 3
4
-15V
Figure ES-2.S Offset voltage in a
differential amplifier. .
Questions
From the experimental data, comment on the following:
1. Is the output offset voltage the same in noninverting and differential amplifier
circuits? Why or why not?
2. Does the output offset voltage in the noninverting amplifier equal that in the
voltage follower? Briefly explain your answer.
3. Comment on the importance of the compensating network· in op-amp circuits.

-- ...-- ...-·..--·---·-·-· -· ..-·--· -
Frequency Response of an Op-Amp
6-1 INTRODUCTION
As we have seen in Chapter 3, some of the characteristics of the op-amp are .frequency
dependent. One of the most important of these characteristics is the open-loop voltage
gain A.. The gain A decreases as the operating frequency increases. This variation in
gain as a function of frequency imposes a limitation not only on the performance of
the op-amp but also on its use in ac applications. This chapter investigates the factors
responsible for variations in open-loop gain as a function of frequency. It will also
discuss the differences between internally and externally compensated op-amps and
the effect of negative feedback on variations in open-loop gain. The chapter concludes
with another important frequency-dependent parameter: slew rate and its effect on
op-amp applications.
6-2 FREQUENCY RESPONSE
Up to now we have treated the gain of the op-amp as a constant. However, it is a

complex number which is a function of frequency. Therefore, at a given frequency the
gain will have a specific magnitude as well as a phase angle. This means that the
variation in operating frequency will cause the variation in gain magnitude and its
phase angle. The manner in which the gain of the op-amp responds to different fre-
quencies is called the frequency response. A graph of the magnitude of the gain versus
frequency is called a frequency response plot. This plot is included on the data sheets
of most of the op-amps. Although gain magnitude may be expressed either in decibels
206
(dB) or as a numerical value, the frequency is always plotted on a logarithmic scale.
Remember that in order to accommodate large frequency ranges, the frequency is
assigned a logarithmic scale, just as the gain magnitude is expressed in dB to accom-
modate very high gain, of the order of 1 osor higher. The frequency response for the
amplifiers is obtained from the experimental results by measuring its input and output
voltages at different frequencies.
Another technique used in the ac analysis of networks is the Bode plot, composed
of magnitude versus frequency and phase angle versus frequency plots. In magnitude
versus frequency plots the magnitude is always taken in dB. Although both frequency
response and Bode plots indicate the effect of frequency variation on gain, the Bode
plot is basically an approximate method and is generally used for stability determina-
tion and network design.
6-3 COMPENSATING NETWORKS
As the operating frequency increases, the magnitude of the gain decreases, and the
phase angle of the gain increases. That is, the phase shift of the output signal increases
with respect to input signal, while its amplitude decreases with an increase in the
operating frequency. This phase shift, which increases with frequency, has a cumula-
tive effect on the phase shift produced by the use of the feedback circuit when the
a
op-amp uses feedback. Thus, for a given frequency,. the total phase shift between
the input and output signals is equal to the phase shift due to feedback network plus
the phase shift due to the internal circuitry of the op-amp. If at any frequency total
phase shift (feedback plus internal) becomes 360° and the magnitude of the loop gain
is unity (I AB I = 1), the circuit may become unstable and break into oscillation. This
condition is called positive feedback. Under this condition, even though the amplifier
is configured for negative feedback, it is actually producing positive feedback. In
fact, this is the most unreliable and unacceptable situation in amplifier applications.
One solution to this problem is to make sure that the total phase shift (phase of
AB) never reaches 360° over the entire operating frequency range of the amplifier.
This can be accomplished by using a circuit called a compensating network. These
compensating networks control the phase shift and thus improve the stability of
amplifier circuits. Compensating networks typically consist of capacitors and resistors.
The phase lag and phase lead are the most commonly used compensating networks in
op-amps. These two networks are indicative of their functions since phase lag contrib-
utes a negative phase angle and phase lead a positive phase angle.
In internally compensated op-amps the compensating network is designed into
the circuit to control the phase shift of the op-amps. On the other hand, external
(discrete) compensating components, namely resistors and/or capacitors, are added
at designated terminals in noncornpensated op-amps. Some of the op-amps need as
many as four compensating components. For example, the µA726C requires two
resistors and two capacitors. For proper operation the manufacturer recommends
appropriate compensating components for the uncompensated op-amps. The 741 C
is an internally compensated op-amp, while the 709C is a noncompensated op-amp.
The open-loop frequency response curves of these op-amps are shown in Figure 6-1.
206 Frequsncv Response of an Op-Amp Chap. 6

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~ ...
+ + + + + + I
(8PI u1e6 e6ei1011 dooj-uado '8P (M) 1°v
207
6-4 FREQUENCY RESPONSE OF INTERNALLY COMPENSATED
OP-AMPS
Let us examine the open-loop frequency response of the internally compensated

op-amp. In the plot of Figure 6-I(a), in order to accommodate the entire operating
range, the gain as well as the frequency are assigned logarithmic scales. In addition,
the voltage gain is expressed in dB. The unity gain bandwidth of the 741 C is approxi-
mately 1 MHz and has a single break frequency / before the unity gain bandwidth.
0
Recall that at the break frequency / the open-loop gain is down 3 dB or 0. 707 of its
0,
value at O Hz (de). The gain of the op-amp remains essentially constant from O Hz to
the break frequency f., and thereafter rolls off at a constant rate, namely 20 dB per
decade (tenfold increase in frequency) [see Figure 6-l(a)]. Thus the open-loop. band-
width is the frequency band extending from O Hz to /0, or simply f.. Hence the open-
loop bandwidth of the 741C is approximately 5 Hz.
In the 741 op-amp a 30-pF _capacitor is the internal compensating component
(Figure 2-3), which helps to control the open-loop gain to allow it to roll off at a rate
of 20 dB/decade. Therefore, regardless of the closed-loop gain used, for frequencies
higher than the closed-loop break frequency, the gain will always roll off at a rate of
20 dB/decade. In fact, this roll-off rate assures us of stable circuit operation at any
gain. The internally compensated op-amps are sometimes simply called compensated
op-amps and generally have very small open-loop bandwidths.
6-5 FREQUENCY RESPONSE OF NONCOMPENSATED

OP-AMPS
Op-amps requiring external compensating components are called noncompensated

op-amps. They are sometimes called tailoredfrequency response op-amps because the
user has to provide the compensation if it is needed to tailor the response. The open-.
loop gain characteristics of the noncornpensated op-amp are altered by the compen-
sating components as shown in Figure 6-l(b). The roll-off rate with various
compensating components that are specified along the gain versus frequency curves
is about 20 dB/decade. Note that the open-loop bandwidth of a 709C decreases from
the outermost compensated curve to the innermost. That is, if C1 = 10 pF, R1 = 0,
and C2 = 3 pF, the bandwidth is approximately 5 kHz, while if C1 = 5000 pF,
R1 = 1.5 kn, and C2 = 200 pF, the bandwidth is 100 Hz, as shown in Figure 6-l(b).
The frequency compensation circuit of the µA709 is shown in Figure 6-l(c). The
uncompensated op-amps offer relatively broader open-loop bandwidths, as can be
seen from Figure 6-l(a) and (b).
Next, we must obtain the general mathematical expression for the gain, primarily
to confirm that it is a complex quantity and is a function of frequency. Then, to prove
the validity of this equation, we need to construct the gain versus frequency plot
from it. However, to derive the gain equation, a high-frequency op-amp model must
first be developed.
208 Frequency Response of an Op-Amp Chap. 6

6-6 HIGH-FREQUENCY OP-AMP EQUIVALENT CIRCUIT
What causes the gain of the op-amp to roll off after a certain frequency is reached?
Obviously, there must be a capacitive component in the equivalent circuit of the
op-amp since its reactance decreases as the frequency increases. This means that we
have to include a capacitor in the high-frequency model of the op-amp at the output
terminal. But how do we account for this capacitor? Two major sources are respon-
sible for capacitive effects:
I
1. The physical characteristics of semiconductor devices. Recall that op-amps are
composed of BJTs and FETs which contain junction capacitors. These junction
capacitors are very small (of the order of picofarads) and act as open circuits
at low frequencies but take finite values at higher frequencies. In fact, 'as fre-
quency increases, the reactances of these capacitors decrease.
2. The internal construction of the op-amp is a second source of capacitive effects.
In op-amps a number of transistors as well as resistors and sometimes a capacitor
are integrated on the same material, called a substrate. In fact, the substrate
acts as an insulator and helps to separate these components. The various
components are connected by conducting paths, and the paths are separated
by insulators. However, whenever two conducting paths are separated by an
insulator, it acts as a capacitor. This means that because of its construction the
op-amp may contain a number of such stray capacitors.
The cumulative effect of these capacitors due to the characteristics of semi-

conductor devices and the internal construction of the op-amp causes the gain to
decrease as the frequency increases.
For an op-amp with only one break frequency we will represent all the capacitive
effects by a single capacitor, as shown in Figure 6-2. This figure represents the high-
frequency model of the op-amp with a single break frequency. Similarly, op-amps
with more than one break frequency may be represented by using as many capacitors
as the break frequencies they have.
Note that the high-frequency model of Figure 6-2 is a modified version of the
Y1
+
Yid R, Yo
r
Y2
Figure 6-2 High-frequency model of

an op-amp with single break frequency.
Sec. 6-6 High-Frequency Op-Amp Equivalent Circuit 209

l
equivalent circuit of the op-amp presented in Chapter 2. Here we have simply added
a capacitor e at the output..
6-7 OPE!V-LOOP VOLTAGE GAIN AS A FUNCTION

OF FREQUENCY
Let us now obtain an expression for the gain as a function of frequency. From Figure
6-2, using a voltage-divider rule, we get
_ ~jXc ( )
Va - R - ·x Av,d
a J C
Since -j = 1/j and Xe= 1/2nfe,

1/j2nfe
Va = Ra + 1/j2nfe(Av,d)
Av,d
= 1 + j21tf Rae
Hence the open-loop voltage gain is
A
AoL = 1 + j21tf Rae
Letf. = 1/2nRaC; then
A
AoL = 1 + j(f/fa) (6-1)
where AoL = open-loop voltage gain

A = gain of the op-amp at O Hz (de)
f = operating frequency (hertz)
f. = break frequency 'of the op-amp (hertz)
Note that the break frequency f. depends on the value of C and of output resistance
Ra. Therefore, f. is fixed for a given op-amp.
Equation (6-1) is important because it indicates that the open-loop gain of the
op-amp AoL is a complex quantity and is a function of operating frequency. Being
complex in nature, the gain can be expressed in a polar form as follows. The open-loop
gain magnitude is
(6-2a)
and phase angle
(6-2b)
w~ere co = 21tf a~d i~ used to indica? that th~ magnitude of gain and_ phase an~le of
gain are functions of frequency. Using Equation (6-2a), we can obtain a magnitude
versus frequency plot, while the phase angle versus frequency plot can be obtained by
using Equation (6-2b);
Before proceeding with the graphical representation of Equation (6-2), we will
present a qualitative analysis .of it. Examine first the magnitude Equation (6-2a). At
O Hz the denominator is I, and the open-loop gain AoL is equal to A. In fact, for

any frequency less than / the gain is approximately constant and is equal to A.
0
However, at frequencies above / the denominator value increases, causing the gain
0,
AoL to decrease. Thus, as the frequency increases, the gain AoL continues to drop.
As for the phase shift Equation (6-2b), at O Hz the phase shift between input and
output voltage is zero. In fact, for any frequency below /0, the absolute value of the
phase shift is less than 45°. Above / the absolute value of the phase shift" increases
0
toward 90° with increases in frequency.

Now let us verify the validity of Equation (6-2) by using it to plot the Bode
diagrams for the 741C op-amp. Let us begin by expressing magnitude Equation (6-2a)
in dB:
20 log AoL(ro) = 20 log [,Jl +A(///o)2]
AoL(w) dB= 20 log
A - 20 log ,J + (ir
1 (6-3)
Since /0 ~ 5 Hz and A = 200,000 for the. 741C, let us substitute these values in
Equation (6-3):
Aoi(ro) dB = 20 log 0.2 M - 20 log ,J 1 + ( { r
We will now determine the gain in dB at different frequencies, including atlo:
At/= 0 Hz, AoL(w) dB= 106.02 - 20 log ,J 1 + ( ~ r~ 106
At/= 5 Hz= lo, AoL(ro) dB= 106.02 - 3.01 ~ 103

Atf= 50Hz, AoL(ro) dB= 106.02 - 20.04 ,.._, 86
At/= 500Hz, AoL(ro) dB = 106.02 - 40 ,.._, 66
Atf= 5 kHz, AoL(w) dB = 106.02 - 60 ~ 46
At/= 50 kHz, AoL(w) dB= 106.02 - 80 ,.._, 26
At/= 100 kHz, AoL(co) dB= 106.02 - 86.02 = 20
Atf= 1 MHz, AoL(co) dB= 106.02 - 106.02 = 0
From the gain calculations above the following observations can be made:
1. The open-loop gain AoL(co) dB is approximately constant from O Hz to the break

frequency / 0•
2. When the input signal frequency f is equal to the break frequency lo, the gain
A0L(co) dB is 3 dB down from its value at O Hz. For this reason the break
frequency is sometimes called the -3 dB frequency. It is also known as the
corner frequency.
3. The open-loop gain A0L(co) dB is approximately constant up to the break
frequency lo, but thereafter it decreases 20 dB each time there is a tenfold increase
(one decade) in frequency. Therefore, it may be said that the gain rolls off at
the rate of 20 dB/decade. Stated another way, the gain rolls off at the rate of
6 dB/octave, where octave represents a twofold increase in frequency. This can
Sec. 6-7 Open-Loop Voltage Gain as a Function of Frequency . -,'Z.11

be seen from the difference in gain at 50 and· 100 kHz. Thus we can decsribe the
roll-off rate as either -6 dB/octave or -20 dB/decade.
4. Finally, at some specific value of the input signal frequency, the open-loop gain
AoL(co) dB is zero. This specific frequency is called the unity gain bandwidth.
Other equivalent terms for it are gain-bandwidth product, closed-loop bandwidth,
small-signal bandwidth, and unity gain crossover frequency. Remember that the
unity gain bandwidth is equal to the gain bandwidth product only if an op-amp
has a single break frequency before the unity gain bandwidth. This is precisely
the case for op-amps like 741. The unity gain bandwidth of the 741C is approxi-
mately 1 MHz and is verified by the decibel gain calculation at/== I MHz. Note
that a gain of O dB is the same as a numerical gain of I.
The magnitude of the open-loop gain in dB versus frequency plot is shown in

Figure 6-3(a). Note that this plot is almost a duplicate of the frequency response in
Figure 6-1 (a), which proves the validity of the gain Equation (6-2a). Thus if we know
the break frequency and the gain of the op-amp, it is possible to plot the frequency
response using Equation (6-2a).
Next, we will obtain the data for the phase angle versus frequency curve using
Equation (6-2b). The phase angles may be computed at the same frequencies as were
used to calculate the open-loop voltage gain AoL in dB.
if,(co) = =tarr ' ( {) (6-2b)
Atf= 0 Hz, if,(co) = -tan-1( ~) = 0°
Atf=/0 = 5 Hz, if,(co) = -tan-1( ~) = -45°

Atf= 50 Hz, if,(co) = -84.29°
Atf = 500 Hz, if,(co) = -89.43°
Atf= 5 kHz, if,(co) = -89.94°
Atf= 50kHz, if,(co) = -89.99°
Atf = 100 kHz, <f>(co) = -90°
Atf= I MHz, <f>(co) = -90°
The phase angle versus frequency plot is shown in Figure 6-3(b). From this plot it is
obvious that the phase angle of the op-amp with a single break frequency varies
between O and -90°. In other words, the phase shift between the input and output
voltages is 90° maximum; that is, tl!e output voltage lags the input voltage by 90°.
Remember that to implement gain Equation (6-1), we must know the de gain A
and break frequency f.. However, the break frequency is obtained only from the
frequency response. In other words, a frequency response plot is necessary to write
the gain equation. In short, using a frequency response plot, you can obtain all the
information pertinent to the gain of the op-amp as a function of frequency.

2
120
a:,
"C 100
3
..J
0 80
<:
c·
·~ 60
"'en
.'!!
0 40
>
0.
0
.!2 20
c
"'c.
0 0
Frequency (Hz)
(a)
4 a 81 2 4681 2 4681 2 4 6 81 2
+20
t
e
0
"' -20
e,
"'
"C
.s
"'
"Et
c
-40
..
"'"'"'
.J::.
~ -60
-80
-100
1 10 100 1 k 10 k 100 k 1 M
Frequency (Hz)-
Figure 6-3 (a) Gain in dB versus frequency. (b) Phase angle versus frequency.
213
Example 6-1
The 741C is connected as a noninverting amplifier. What maximum gain can be used
that will still keep the amplifier's response flat to 10 kHz?
I
Solution. The gain that will produce a flat response up to approximately 10 kHz can
be obtained from the frequency response curve of the 741C. To do this, project a 10-
kHz frequency vertically on the curve as shown in Figure 6-4 and then read the corre-
sponding value of the gain on the vertical axis. This value of gain is equal to 40 dB,
that is 100.
cc +120
~
c: +100
"3,
8, +80
!!I
0
>
a. +60
0
.Q
.,i::.a. +40
0
ai +20
"t)
3 0
..J
0
-c -20
1.0 10 100 1 .0 k 10 k 100 k 1 .0 M 10 M Figure 6-4 741C frequency response
Frequency (Hz) plot for Example 6-1.
Up to this point we have been studying op-amps with only one break frequency.
Actually, the op-amp has more than one break frequency because there are quite a
few capacitors present, as pointed out in Section 6-6. Often, the upper break fre-
quencies are well above the unity gain bandwidth and are, therefore, not shown in
the frequency response plot. Since each break frequency contributes at the most a
90° phase shift, the presence of multiple break frequencies should, therefore, be
evident in the phase response plot. One such plot is shown in Figure 6-S(b). Our major-
concern is the number of break frequencies before the unity gain bandwidth because
(1) we seldom use an op-amp above its unity gain bandwidth, and (2) a stable circuit
always requires a phase angle less than 180°.
Using the concepts developed for a single break frequency op-amp, we can
write the gain equation for the multiple break frequency op-amp, as shown in Example
6-2.
Example 6-2
Using the frequency response and phase response curves shown in Figure 6-5. obtain
the gain equation for the MC1556 op-amp, Also determine the approximate values of
the break frequencies.
Solution. Figure 6-5(b) shows that the phase shift is almost -180° at 10 MHz. This
means that two break frequencies must be present, since each break frequency con-
tributes at the most -90°.
Therefore, the gain equation can be written as

+140
iii
~
c: +120
·~
.,a, +100
1S
0 +80
>
0.
0
.2 +60
c.,
0. +40
0
rri +20
"O
3., 0
0
<! -20
1.0 10 100 1.0k 10k 100k 1.0M 10M lOOM
Frequency (Hz)
(al
-94.5° I
I
I
I
-135 I
I
-157.5 ---------------r---- 1
-1eo ......~ .......~-'-~--1.~~.,__~~~__,__,.__..____,
1.0 10 100 1.0 k 10 k 100 k 100 M Figure 6-5 (a) Frequency response and
(b) phase response curves of the
Frequency (Hz)
MC1556. (Courtesy of Motorola
(bl Semiconductor.)
A
(6-4a)
AoL = [l + j(f/fo1)][l + j(f//01)]
which is simply an extension of Equation (6-1), where
!01 = first break frequency
!02 = second break frequency
However, from the graph of Figure 6-5(a) the first break frequency is approximately
at 6 Hz. The value of the second break frequency can be computed by substituting a
specific known value of the phase shift in a phase angle equation. The equation is
q,(ro) = -tan-1(.L)
r: - tan-1(.L)
fol
(6-4b)
The phase shift is -157.5° at about 3 MHz [see Figure 6-5(b)]. Substituting these values
in the equation above, we get
Sec. 6-7 Open- Loop Voltage Gain as a Function of Frequency .215

-157.5 = =tan"! (3 MHz) - tan-• (3 MHz)
6Hz lo2
tan~·e 7a~z) = 67.50
3MHz
=r:":
Jo2
= tan (67.50)
3 MHz
lo2 = tan (67.50) = 1.24 MHz
Thus the gain equation with break frequency values is as follows:
A . 140,000
ot, = '[l + j(f/6)][1 + j(//1.24 MHz)]
where A,.._, 140,000 or 103 dB, /01 = 6 Hz, and /02 = 1.24 MHz.
6-8 CLOSED-LOOP FREQUENCY RESPONSE
So far the discussion has been centered around the nature of the open-loop frequency
response. Since the op-amp is generally used in a closed-loop configuration, a study
of the closed-loop performance of the amplifier is in order.
We saw that the open-loop gain AoL is constant only up to the first break
frequency. Therefore, the bandwidth of the op-amp is simply the first break frequency
/01; that is, /01 is the maximum useful frequency of the open-loop op-amp. But this
bandwidth j'., is very small, and therefore the open-loop configuration is of little use
practically. To increase the bandwidth of an op-amp and thus make it a versatile
device, a negative feedback must be used. Ideally, of course, we expect the bandwidth
to be infinite so that the gain is the same at all frequencies.
As shown in Chapter 4, the maximum bandwidth of a single break frequency
op-amp is equal to its unity gain bandwidth. Recall that the 741C has a unity gain
bandwidth of approximately I MHz. This means that for 741C the product of the
coordinates (gain and frequency) of any point beyond the break frequency (5 Hz) on
the open-loop frequency response curve is about 1 MHz. That is, given a voltage gain,
the closed-loop bandwidth can be determined using a frequency response curve. For
instance, if the 741C is wired for a gain of 100 or 40 dB, its bandwidth will be about
10 kHz. This bandwidth is obtained by projecting to the right on the open-loop
frequency response curve from 40 dB and reading the frequency on the horizontal
axis corresponding to the point of intersection (see Figure 6-4).
Often, the manufacturers' data sheets give the frequency response for various
closed-loop gains. For example, Figure 6-6 shows the frequency response of 709C for
various closed-loop gains using recommended compensation networks. Obviously,
if high gain and relatively wide bandwidth,are required, the compensating components
for curve I should be used. Note that the closed-loop frequency response curves of
Figure 6-6 can be obtained from the open-loop frequency response of Figure 6-l(b)
by using the same procedure as stated above for the 741C (see Figure 6-4).
Remember that besides using the graphical method, depending on the amplifier
configuration, Equation (4-10) or (4-21) can also be used to compute closed-loop
bandwidth.

80
V5=±15V
TA= 25• c
C1 = 10 pF, R1 = 0, <; = 3 pF
60
iii
~
c
·3., C1 = 100 pF, R1 = 1.5 kn, C:z = 3 pF
40
&
l!
0>
c. I
C1 = 500 pf, R1 = 1.5 kn, C:z = 200 pF
1 20
10
Curve 3
e
C1 = 5000 pF, R1 = 1.5 kn, c, = 200 pF
0
Curve4
Figure 6-(; Frequency response of the

-20 "---_......_ __ _.... ....__ __,____ µA109C for various closed-loop gains.
100 1 k 10 k 100 k 1 M 10 M (Courtesy of Fairchild.Camera and
Frequency (Hz) Instrument Corporation.)
6-9 CIRCUIT .STABILITY
According to feedback theory, the circuit is said to be stable if the magnitude of its
loop gain A0LB (open-loop gain AoL x gain of the feedback circuit B) is less than
unity when the phase· angle reaches 180°. That is,
[IAoLBl]l;ccu)•l80' < l (6-5a)
where AoL = open-loop voltage gain
B = gain of the feedback circuit
tf,(ro) = phase angle of the loop gain AoLB
In other words, the phase angle of the loop gain A0LB must be less than 180° when its
magnitude is unity. Thus
[~ro)] 11.Aoi,Bl• I < J 80° (6-5b)
One method of determining circuit stability is to use the open-loop frequency
and phase response curves. To determine the stability of an amplifier with a resistive
feedback network, the frequency corresponding to· the closed-loop gain I A, I = l/B
is found on the open-loop frequency response curve. The phase shift at this frequency
is then read on the phase response curve. Note that at this frequency the magnitude of
the loop gain A0LB is I. Therefore, if the phase shift is less than 180°, the circuit is
stable. If the phase shift is more than 180°, the circuit is unstable. The same rule holds
for nonresistive feedback amplifiers except that the phase shift of both the open-loop
op-amp and the feedback network must be considered.
Example 6-3 ·
The MC1556 is wired up as a noninverting amplifier with a gain of 10. Determine the
stability of the amplifier using the frequency response and the phase response curves
Sec. 6-9 Circuit Stability 217

Solution. From the frequency response of Figure 6-5(a), the frequency corresponding
to the closed-loop gain of 10 (20 dB) is 100 kHz. Note that at 100 kHz, AoL = AF;
that is,
,~~I= = 1 IAoLBI
(see Figure 6-7).
From Figure 6-5(b), the phase shift at 100 kHz is about -94.5°. Since -94.5°
< 180°, the amplifier is stable. Remember that the phase shift due to the feedback
network is zero because the network is purely resistive.
+140
+120
+100
iii
~ +80
c:
"i., +60
fl"'
0 +40
>
+20
0
-20
1.0 1O 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M Figure6-7 Frequency response plot
' showing AaL = A, or A0I)A, = 1 at
Frequenc. (~) ff /=/, = lOOkHz.
6-10 SLEW RATE
Another important frequency related parameter of an op-amp is the slew rate. The
slew rate, as mentioned in Chapter 3, is the maximum rate of change of output voltage
with respect to time, usually specified" in V/ µs. For example, a 1 V/ µs slew rate means
that the output rises or falls no faster than l V every microsecond. Ideally, we would
like an infinity slew rate so that the op-amp's output voltage would change simulta-
neously with the input. Practical op-amps are available with slew rates from 0.1 V/µs
to well above 1000 V/µs. The National Semiconductor LH0063C has a slew rate of
6000 V/µs.
Generally, the slew rate is specified for unity gain and is measured by applying
a step input (de) voltage. Slew rate is sometimes given indirectly in data sheets as
output voltage swing as a function of frequency or as voltage follower large-signalpulse
response (see Figure 6-8). Often, the slew rate improves with higher closed-loop gains
and de supply voltages, as shown in Figure 6-9(a) and (b). The slew rate is also-a
function of temperature and generally decreases with an increase in temperature, as
shown by Figure 6-9(c). The slew rate of some op-amps is improved when they are
wired with feedforward compensation. The 101 and 108 are such op-amps, the com-
pensation connections for which are given in the data sheets.

36
V5=±15V
32 TA = 25° c
RL=10kf2
c,,
c:
·~ 24
;
a.
5 20
0
~
8, 16
s
~ 12
i
e,
Frequency (Hz)
(a)
10
8
V5,.t15V
6 r,. • 2s c 0
4 I
s 2
Output I
I
8, I
!l Input----'
..
0
>
::,
c.
0 I
I
; -2 I
0 I
-4 I
-6
L----
-8
Figure ~ Specifying slew rate
-lOl-.......L~..J....._J,~..J...~.I-.--L~...L....__J~--1..---1
O 10 20 30 40 50 60 70 80 90
for
indirectly the 741C as (a) output
voltage swing versus frequency and (b)
nmetµ,l voltage follower large signal pulse
response. (Courtesy of Fairchild
(b) Camera and Instrument Corporation.)
219
100 24
v.s= ±15 V
TA = 25° C 20
80 AL = 10 kfl TA = 25° C
AL = 10 kfl
16 No comp.
] 60 ]
z..
.....I!
~
...I! 12
..
:!:
ii>
40
..
:!:
in 8
20
4
0 0
10 100 6 10 14 18 22
Closed-loop gain Supply voltage (V)
(al (b)
35
V5=±15V
30
AL=lOkfl
25
!
z~ 20
I! 15
..
3:
in
10
0 10 20 30 40 50 60 70
Temperature (°Cl
(cl
Figure 6-9 Slew rate of the µA715C. (a) Increases with closed loop gain. (b) Increases
with supply voltage. (c) Decreases with increase in temperature. (Courtesy of Fairchild
Camera and Instrument Corporation.)
6-10.1 Causes of Slew Rate
The unity gain 'bandwidth is the small-signal high-frequency limitation on the use of
the op-amp. Slew rate, on the other Hand, is a large-signal phenomenon. A large signal
is one whose amplitude is comparable with the power supply voltages. Typically, the
large signal is of the order of volts, while a small signal is in the range of milli- or even
microvolts. Slew rate is caused by current limiting and the saturation of internal
stages of an op-amp when a high-frequency, large-amplitude signal is applied. The
resulting current is the maximum current available to charge the compensation

capacitance network. We know that the capacitor requires a finite amount of time to
charge and discharge. This means that internal capacitors prevent the output voltage
from responding immediately to a fast-changing input. The rate at which the voltage
across the capacitor rises is
(6-6)
Thus slew rate limiting is caused by this capacitor charging rate, in which the voltage
across the capacitor is the output voltage.
6-10.2 Slew Rate Equation I
Since the slew rate on a data sheet is generally listed for a unity gain, let us consider
the voltage follower shown in Figure 6-10. Furthermore, let us assume that the input
is a large-amplitude and high-frequency" sine wave. The equation for the sine wave is
Vin = Vp sin cot
or
(6-7)
...---r---,
Figure 6-10 Deriving the slew rate equation.
The rate of change of the output is

dvo
dt
= v co cos cotp
and the maximum rate of change of the output occurs when cos cot = l. That is,
dvo
dt
I max
= v co
P
or
SR = 2nfVp V/s
V/µs (6-8)
where SR= slew rate in (V/µs)
f = input frequency (hertz)
Vp = peak value of the output sine wave (volts)
For output free of distortion, the slew rate determines the maximum frequency of
Sec. 6-10 Slew Rate 221

operation for a desired output swing. Stated another way, with a lower frequency the
slew rate determines the maximum undistorted output voltage swing. Thus, as long
as the value of the right-hand side of Equation (6-8) is less than the slew rate of the
op-amp, the output waveform will always be sinusoidal. If either the frequency or
the amplitude of the input signal is increased to exceed the slew rate of the op-amp,
the output will distort.
6-10.3 Effect of Slew Rate in Applications
The slew rate has important effects on both open-loop and closed-loop op-amp
circuits. Figure 6-11 (a) shows the open-loop configuration using the 741C. Since the
open-loop voltage gain is very large, the output will go to about + 14 V and then to
-14 V each time the input sine wave crosses zero volts, as shown in Figure 6-11 (b ).
The time taken by the output to go from + 14 V to -14 V can be determined by using
the slew rate of the 741C listed in the data sheet. The slew rate can also be calculated
from the slope of the voltage-follower large-signal pulse response curve of Figure
6-8(b).
Vin
+VP
+15V
ov
-VP
I
I
I
56 JJS
Vo
-j I~
I
+4 V
ov
-14 V
(a) (bl
Figure 6-11 (a) Open-loop configuration using 741C. (b) Input and output
waveforms.
The 741C has a typical slew rate of 0.5 V/ µs; therefore,

28 V
0.5 V/µs = 56 µs
must be the minimum time between the zero crossings. Hence the maximum input
frequency should be '
1
fmox = (2)(56 µs) = 8.93 kHz
However, at this frequency the output may be a triangular instead of square wave.
Therefore, to have a more square-wave output either we keep the input frequency
below !max or choose an op-amp with a faster slew rate. However, faster slew rate

op-amps are sometimes characterized by overshoot and ringing, which cause the
output to take longer to reach a steady state than with slower slew rate op-amps.
For this reason, .settling time is another important parameter that should be con-
sidered, especially in applications such as digital-to-analog (D/A) or analog-to-digital
(A/D) converters.
Next, consider the effect of slew rate on the inverting amplifier with feedback.
Figure 6-12 shows the 741C op-amp used as an inverting amplifier with a gain of 50.
From the voltage gain versus frequency curve of the 741C in Figure 6-l{a), obviously
the amplifier will operate with a gain 1of 50 up to about 20 kHz (50 x 20 kn =
1 MHz). Using Equation (6-8), the maximum output voltage at 20 kHz is
= (211:)(20 k)(Vp)
0. 5 106
- (0.5)(106) -
VP - (211:)(20 k) - 3.98 V peak
or
v. . 7.96 V peak-to ..peak sine wave
A,
10011 5k11
AoM
10011 -15 V
Figure 6-12 Inverting amplifier with a gain of 50.
Hence, for the output to be a sine wave, the maximum input signal should be less than
7·96 = 159 mV peak to peak
50
We can also easily read the maximum output voltage swing from the curve
showing output voltage swing as a function of frequency in Figure 6-8(a). This curve
enables us to estimate the maximum output swing without distortion for different
frequencies. From the curve the maximum output voltage at 20 kHz is approximately
14 V pp. This value, however, is much higher than the value calculated above for the
following reasons:
1. The graph in Figure 6-8(a) is approximate because the same graph is to be used
for different grades of op-amps (741, 741A, 741E, and 741C), even though the
slew rate of the 741C is 0.5 V/µs and that of the 741A is 0.7 V/µs.
2. The slew rate computed from the graph is much higher than the slew rate
Sec. 6-10 Slew Rate 223

(0.5 V/ µs) specified in the data sheets of the 741 C. For instance, referring to
Figure 6-8(a), the output voltage swing is 28 V pp at 10 kHz, which in turn
implies a slew rate of
SR= (2n)(l4)(10 k)(I0-6) = 0.88 V/µs
In short, the graph of Figure 6-8(a) should be used as a rough. estimate. of

output voltage swing or slew rate and not as an accurate measure.
6-10.4 Difference between Bandwidth, Transient Response,

and Slew Rate
Table 6-1 is a summary of three important ac parameters of the op-amp: bandwidth,

transient response, and slew rate. A clear idea of the differences between these param-
eters is important in ac applications.
TABLE 6-1 SUMMARY OF AC PARAMETERS
Bandwidth Transient response Slew rate
I. A small-signal phenomenon A small-signal phenomenon A large-signal phenomenon

2. Band of frequencies for That part of the total The maximum time rate of
which the gain remains response before the change of the output
constant response reaches a steady voltage
state
3. Depends on compensating Composed of overshoot Slew rate limiting depends
components and closed- and rise time; rise time on both frequency and
loop gain is related to bandwidth amplitude; often
and overshoot is a increases with closed-
measure of stability loop gain and power
supply voltages
4. If exceeded, results in a Affects settling time If exceeded, results in
reduction of output distortion
voltage but causes no
distortion
SUMMARY
1. Frequency response is the manner in which the gain magnitude and the phase angle
between the input and output res9ond to different frequencies.
2. Compensating networks are used to control the phase shift and thus improve the stability
of the op-amps. These networks are typically composed of resistors and/or capacitors. The
compensating network is either designed into the circuit or is added at designated terminals.
3. In internally compensated op-amps the compensating network is designed into the circuit.
On the ocher hand, a compensating network is added externally in noncompensated
op-amps. Generally, open-loop noncornpensated op-amps have wider bandwidths than
those of compensated op-amps.
224 Fr;,q~·.:r,cy Hespoose of an Op-Amp Chap. 6

4. Because of capacitances within the op-amp, the gain decreases and the phase shift between
input and output voltages increases as frequency increases.
S. The open-loop gain of the op-amp is relatively constant at frequencies below the break
frequency but decreases at a rate of -20 dB/decade after each break frequency.
6. The very small bandwidth of an open-loop op-amp limits its use. The closed-loop op-amp
has the advantage of a much larger bandwidth.
7. To achieve a stable circuit, the phase angle of the loop gain must be less than 180° when its
magnitude reaches unity.
8. Slew-rate limiting occurs with all large, fast-changing signals. If slew rate is exceeded,
distortion of the output waveform resuljs,
QUESTIONS
6-1. What is a frequency response?

6-2. Briefly explain the need for compensating networks in op-amps.
~-3. What is the difference between compensated and noncompensated op-amps?
6-4. How does the high-frequency model differ from the equivalent circuit of an op-amp?
Explain.
6-5. Define the break frequency and bandwidth.
6-6. Explain the effect of negative feedback on the frequency response.
6-7. What is a slew rate? List causes of the slew rate and explain its significance m
applications.
6-8. Explain the difference between the slew rate and transient response.
PROBLEMS
6-1. The 741C is connected as an inverting amplifier and is required to have a closed-loop
gain of 20. What is its bandwidth? Is the circuit stable?
6-2. The 709C is used as a noninverting amplifier with a gain of 50 dB. What is its bandwidth
if C1 = 500 pF, R1 = 1.5 H2, and C2 = 20 pF?
6-3. Repeat Problem 6-2 with a gain of 70 dB,.
6-4. Repeat Problem 6-2 with the compensating components as follows: C1 = 5,000 pF,
R1 == 1.5 kil, and C2 = 200 pF.
6-S. What maximum gain can be used while keeping the amplifier's response flat to 1 kHz?
Assume that the 741 C is wired as an inverting amplifier.
6-6. The frequency response of a certain op-amp is shown in Figure. 6-13. Write the open-
loop gain equation for the op-amp as a function of break frequencies and de gain A.
6-7. Determine the magnitude of the open-loop gain and the phase shift between the input
and output for the op-amp in Problem 6-6 if the frequency of operation is IO MHz.
Is the circuit stable? Explain.
6-8. Compute the unity gain bandwidth of the op-amp whose frequency response is given
in Figure 6-13.

I
I
iii 64 ----4---
~ 1
] I
..J
0 I I
< 33 ----l----t---
II I
I
I I
0.7 M Unity cross-over
fol frequency
Frequency (Hz)
Figure 6-13 Frequency response for Problem 6-6.
6-9. Noncompensated op-amp MC1539 has a de gain A = 120,000 and the following break
frequencies: /01 = 5 kHz, /01 ,...,· 320 kHz, /.3 = 1 MHz, and/., = 2 MHz. Write the
open-loop gain equation for the op-amp as a function of break frequencies and de gain
A. Then plot the Bode diagrams.
6-10. For the op-amp of Problem 6-9, compute the phase shift between input and output
signals at 50 kHz and 1.5 MHz.
6-11. The µA709C is connected as shown in Figure 6-14: What is its bandwidth when the
20 kn pot is adjusted to (a) 1 kn and (b) 10 kn? [Hint: Use characteristic curves of
Figure 6-l(b).]
R,
ioo n 20 kn
c,
500 pF
Figure 6-14 Amplifier of Problem 6-11.
6-12. The µA709C is wired up as a noninverting amplifier for a gain of 1000 and is required
to give a flat. response to about 300 kHz. What compensating components would you
recommend for the op-amp? (Hint: Refer to the characteristic curves shown in Figure
6-6.)

6-13. The 741C is connected as an inverting amplifier for a gain of 100. Determine the
stability of the amplifier at this gain.
6-14. The 741 C is used as an inverting amplifier with a gain of 50. The sinusoidal input signal
has a variable frequency and maximum amplitude of 20 mV peak. What is the maxi-
mum frequency of the input at which the output will be undistorted? Assume that the
amplifier is initially nulled.
6-15. Determine the slew rate of the 741C using the voltage-follower large-signal pulse
response of Figure 6-8(b).
6-16. An inverting amplifier using the 741C must have a flat response up to 40 kHz. The gain
of the amplifier is 10. What maxirriurn peak-to-peak input signal can be applied without
distorting the output? [Refer to the op-amp characteristic in Figure 6-8(a).]
6-17. Determine the slew rate of the 715C if it is used as a noninverting amplifier with a gain
of (a) 5 and (b) 50. [Note: Refer to Figure 6-9(a).]
6-18. When an 8 V peak-to-peak square wave of 3.6 MHz frequency is the input to a.voltage
follower, the output is a triangular wave, as shown in Figure 6-15. What is the slew
rate of the op-amp?
Figure 6-15 Waveform of Problem

6-18.
6-19. In Problem 6-18, what must the minimum slew rate of the op-amp be in order to get
· the square-wave output?
6-20. The 715C is connected as a noninverting amplifier with a gain of 10. If the input is a
sine wave at a frequency of 2 MHz, what is the largest undistorted output voltage?
[Refer to the op-amp characteristic in Figure 6-9(a).]
EXPERIMENT 6-1
FREQUENCY RESPONSE OF NONCOMPENSATED
OP-AMP 709C
Objectives
In this experiment you will plot the frequency response of the noncompensated op-amp
709C with two different sets of compensating networks. After you complete this
experiment, you should be able to:
1. Explain the effect of compensating networks on the bandwidth of the amplifier.
Exp. 6-1 Frequency Response of Noncompensated Op-Amp 709C 227

2. Select a suitable compensating network for a desired bandwidth and closed-loop
gain.
Equipment
1. Oscilloscope
2. Audio-frequency generator: /mu. = 1 MHz
3. ± l5-V power supply
Materials
1. 709C op-amp
2. Two 100-n resistors
3. 1. s-in resistor
4. 10.0-kn resistor
5. 20-pF capacitor
6. 200-pF capacitor
7. 500-pF capacitor
8. 5000-pF capacitor
9. Semilog paper
Procedure
1. Connect the op-amp as an inverting amplifier, as shown in Figure E6-1.l with

C1 = 5000 pF, R1 = 1.5 kn, and C2 = 200 pF. Note that the pin numbers
refer to the 14-pin DIP. If you have the 8-pin mini DIP, refer to the data sheet
of the 709C.
R,
100.n 10k!l
Figure E6-1.1 709C configured as an inverting amplifier with a gain of 100.
2. Turn on the de supply voltages and signal generator. Connect the scope at the
output terminal of the amplifier. Then set the generator frequency at 100 Hz
sine wave and adjust the amplitude of the input so that the output is a measur-
228 FrequencyResponseof an Op-Amp Chap. 6

able, undistorted sine wave. Measure the input and output voltages and enter the
values in Table E6-l. l.
TABLE E6-1.1
Input Input Output Voltage gain

Compensating frequency, amplitude, amplitude, Voltage gain, (dB)=
components (Hz) Vin pp Vo pp Vo/Vin 20 log (vo/V1n)
C1 = 5000pF, 100 I
R1 = 1.5 Hl 300
C2 = 200pF 700
1,000
3,000
7,000
10,000
30,000
70,000
100,000
C1 =_500pF, 100
R1 = 1.5 kn 300
C2 = iOpF 700
1,000
3,000
7,000
10,000
30,000
70,000
100,000
500,000
700,000
1,000,000
3. Change the frequency of the input to 300 Hz and again measure the input and
output voltages with the scope. Enter the measured values in Table E6-1.1.
Repeat the procedure for the remaining frequencies.
4. Turn off the supply voltages and the signal generator. Replace the compensating
capacitors with the following values: C1 = 500 pF and C2 = 20 pF.
5. Repeat steps 2 and 3 to complete Table E6-1.1.
6. Draw the frequency response plots for the 709C op-amp using both the
compensating networks, and determine the bandwidths.
Questions
1. Which set of compensating components used with 709C results in a larger
bandwidth?
2. How do these bandwidths compare with those obtained from the open-loop
frequency response of the 709C for various values of the compensation? (The
open-loop frequency response is given in the data sheets of the 709C.)
Exp: 6-1 Frequency Response of Noncompensated Op-Amp 709C 229

EXPERIMENT 6-2
MEASURING SLEW RATE
Objectives
In this experiment you will measure the slew rate of the 741C op-amp using sine and
square waves. When you complete this experiment, you should have the following
knowledge and capabilities:
1. Given a particular op-amp, you should be able to measure its slew rate using
either a sine- or square-wave input.
2. You should be able to verify that slew rate limiting depends on both amplitude
and frequency.
3. You should also be able to verify that the output distorts if slew rate is exceeded.
4. For a specified frequency and amplitude of the output, you should be able to
select an op-amp with a suitable slew rate.
Equipment
1. Oscilloscope
2. Sine- and square-wave audio-frequency generator: f max = 1 MHz
3. ± 15- V power supply
Materials
1. 741C op-amp
2. 100-Q resistor
3. 10-kn resistor
4. 1-kn po.tentiometer
Procedure
1. Connect the 741C as shown in Figure E6-2.l(a). Turn on the supply voltages
and signal generator, making sure that the generator is set on the sine wave.
2. Connect the scope at the output terminal and· adjust the signal generator so that
the output is· 1 V peak sine wave at 1 kHz.
3. Slowly increase the frequency of the signal generator until the output is just
barely distorted. Enter this value of frequency and the amplitude of the output
in Table E6-2.1.
4. Calculate the slew rate using the' following equation:
SR= 2nfVp V/µs
106
where VP = the peak output amplitude (volts)
f = frequency (hertz)
Enter the calculated value of the slew rate in Table E6-2.1.
230 Frequency Responseof an Op-Amp Chap. 6

90011
10011
+15V
6 6
Vo Vo
I
RL AL
10 k11 10 k11
(al (bl
Figure E6-2.1 Measuring slew rate with (a) voltage follower and (b) noninvert-
ing amplifier.
TABLE E&-2.1
Maximum input
Input frequency applied Output amplitude Siew rate
Network waveform (Hz) (V) (V/µs)
1. Voltage Sinusoidal
follower
2. Voltage Square
follower wave
3. Noninvert- Sinusoidal
ing
amplifier
5. Switch the signal generator to a square-waveinput and repeat step 2.

6. Slowly increase the frequency of the input until the outpu~ is just barely a
triangular wave. Enter this value of frequency as well as the output a.11\plitude
in Table E6-2. l.
7. Calculate the slew rate using the following equation:
SR= AV 0 V/µs
At
where A V0 = change in the output voltage amplitude (volts)
At = time required for AV0 (µs). ·
8. Connect the 741C as shown in Figure E6-2.l(b). Tum on the supply voltages
and switeh the signal generator back to sine wave. Repeat steps 2, 3, and 4.
Exp. 6-2 Measuring Slew Rate 231

You may have to increase an amplitude of the input signal in order to cause an
output to distort.
Questions
1. How does the slew rate of the voltage follower using sine wave compare to that
with square wave? If the values are more than 20 % apart, give the reasons.
2. Is the slew rate of the noninverting amplifier the same as the voltage follower?
What conclusion can be drawn from this comparison?
3. Compare the slew rate you measured at unity gain to that given in the data
sheet of the 741C. If the difference is more than 20%, give the reasons.

--------·-------·
General Linear Applications
-·-·····---·-·-···-··-·-· -·····-·-··- ..·--·---- ....··-------·-·--·-· ..------
7-1 INTRODUCTION
All op-amps are basically alike in being direct-coupled high-gain differential ampli-
fiers. However, many different specific op-amps are available because no one circuit
design can possibly optimize all the de and ac parameters. For particular applica-
tions, op-amps are designed to optimize a parameter such as high slew rate, wide
bandwidth, high gain, or low power consumption. Therefore, to achieve the best
performance in a desired application, it is essential to select a suitable op-amp.
Often, a choice has to be made between performance and cost since an op-amp
optimized for a particular parameter is more expensive than a general-purpose
op-amp. ·
The op-amp parameters were defined and discussed in Chapter 3. These param-
eters are very useful in circuit design as well as in selecting an op-amp for a specific
application. Also, Chapter 6 showed how data sheet information can be used to
determine circuit stability. The. data books contain a wealth of information, and we
should consult them to select the most suitable device for a desired application.
Having considered the op-amp's basic construction, characteristics, parameter
limitations, and various configurations, our next logical step is to discuss op-amp
applications. Since there are literally countless applications of op-amps, they will be
arranged into the following categories: general linear applications, filter and ocsil-
lator applications, comparator and detector applications, special integrated circuit
applications, and selected system applications. Each category will include the most
important applications in that area. Thus the remainder of the book is devoted
entirely to op-amp applications. We begin with general linear applications in this
233
chapter. Recall that in linear circuits the output signal is of the same nature as the
input and varies in accordance with the input within the limits set by the saturation
levels and slew rate. The first part of the chapter presents the important types of
amplifiers and the last part discusses simple modifications of basic amplifier con-
figurations.
In all these applications a general-purpose op-amp such as the 741 will be used.
Remember that no one op-amp has all the de and ac parameters optimized, and the
741 is no exception. However, using the concepts developed in this chapter, the reader
may select a more specific op-amp that will improve the performance and accuracy
of the circuit.
7-2 DC AND AC AMPLIFIERS
As pointed out in Chapter 4, the properties of closed-loop amplifiers depend primarily

on characteristics of the feedback network rather than those of the op-amp itself.
Since a typical feedback network is composed of resistors and capacitors, the accuracy
and stability of circuits using them can be improved significantly because these com-
ponents are available in conditions of high precision and low drift.
7-2.1 DC Amplifier
Basically, an op-amp can amplify two types of signals: de and ac. In a de amplifier
the output signal changes in response to changes in its de input levels. A de amplifier
can be inverting, noninverting, or differential, as shown in Figure 7-1. To reduce the
output offset voltage to zero, that is, to improve the accuracy of the de amplifier,
the offset null circuitry of the op-amp should be used. For op-amps without offset
null capability, the external offset voltage compensating network should be used,
as shown in Figure 7-2. Otherwise, a high-precision op-amp such as the µA714,
which has smaller offsets and drifts, must be used. Recall that all the circuits in Figures
7-1 and 7-2 have been discussed previously and their output voltage equations derived.
7-2.2 AC Amplifier
The circuits of Figures 7-1 and 7-2 respond to ac input signals as well. However, if
the designer needs the ac response characteristics of the op-amp, that is, low- and
high-frequency limits, or if the ac input is riding on some de level, it is necessary to
use an ac amplifier with a coupling capacitor. For example, in an audio receiver system
which consists of a number of stages, because of thermal drift, component tolerances,
and variations, the de level is produced, To prevent the amplification of such de
levels the coupling capacitors must be used between the stages. Figure 7-3 shows the
ac inverting and noninverting amplifiers with coupling capacitors.
The coupling capacitor not only blocks the de voltage but also sets the low-
frequency cutoff limit, which is given by
!L = I (7-1)
21tCi(R,F +R 0)
234 General Linear Applications Chap. 7

R, A, R,
6 6
v:
lOkn .___ __,

(al (bl
A, R,
v.
R,
v;» - R, IV, -V,I
6
A7• A1
v, -v .. Al
R3 • R,
lOkn
le)
Figure 7-1 (a) Inverting amplifier, (b) noninverting amplifier, and (c) differential amplifier
with offset null circuitry.
where IL =
low-frequency cutoff or low end of the 'bandwidth
C, = capacitance between two stages being coupled or de blocking
capacitor
R" = ac input resistance of the second stage
R0 = ac output resistance of the first stage or the source resistance
Remember that the high-frequency cutoffIn or high end of the bandwidth depends
on the closed-loop gain of the amplifier.
Thus the bandwidth of the amplifier,
BW = (In - IL) (7-2)
depends on the desired value of IL and the closed-loop gain of the amplifier. The
required value of capacitor C, can be calculated using Equation (7-1). The coupling
capacitor C,, besides providing a low-frequency cutoff limit, also helps to eliminate
de level amplification from stage to stage. In Figure 7-3, for example, the input voltage
Sec. 7-2 DC and AC Amplifiers 235

(al
+Vee
A,
Rb
Ac
-VEE
V0 ~ (1+ ::)v,n
if A, + RC~ A,
RL
v;
-Vee
(b)
A, RF
vx
A2 Vo = - RF (Vx -Vvl
R,
if A,= A2, R3 + RC= RF
f"
Vv AL
Rb -Vee
A,
RC
-Vee
(cl
Figure 7-2 (a) Inverting amplifier, (b) noninverting amplifier, and (c) differential
amplifier with external offset-voltage compensating network.
236 ·'
Coupling c1
capacitor ..._
10 kn
(a)
A1
Coupling c
capacitor~ I
10 kn
(b)
Figure 7-3 (a) Ac inverting amplifier. (b) Ac noninverting amplifier. (Pin num-
bers are for the 14-pin DIP.)
v1n could be a preceding amplifier output with a de level; the coupling capacitor C,
will block this de level. Thus the coupling capacitor prevents the amplification of the
de level.
Figure 7-3(a) shows an ae inverting amplifier, the closed-loop gain of which is
still
Sec. 7-2 DC and AC Amplifiers 237

A, ,_, - ~: (7-3)
since the reactance of C, is negligible within the bandwidth. Similarly, the closed-loop
gain of the noninverting amplifier of Figure 7-3(b) is
(7-4)
Example 7-1
In the circuit of Figure 7-3(a), R1,. = SO 0, C, = 0.1 µF, R1 = 100 0, R, = 1 ill,
RL = 10 k!l, and supply voltages = ±15 V. Determine the bandwidth of the
amplifier.
Solution. Recall that the input resistance of the inverting amplifier with feedback is
R,, = R1 + R,;,...., 100 0
The source resistance R111 = R = SO 0.

0 Therefore, from Equation (7-1),
1
IL = (2,r)(lO-')(lSO) = 10.6 kHz
Since A,= -R,/R1 = -10, the high-frequency cutoff/a using Equation (4-21b) is
.. r _ unity gain bandwidth _ 1 MHz _ kHz
JH- A, -10- 100
Thus, from Equation (7-2), BW = 100 kHz - 10.6 kHz = 89.4 kHz.
7-3 AC AMPLIFIERS WITH A SINGLE SUPPLY VOLTAGE
An ac amplifier can be powered by a single supply voltage if an additional coupling

capacitor is used on the output of an amplifier, as shown in Figure 7-4. This capacitor
blocks de; therefore, an output offset voltage as well as a de level in the output signal
has little effect on the operation of the amplifier. Besides that, in Figure 7-4(a) positive
de level is intentionally inserted using a voltage-divider network at the noninverting
input terminal so that output can swing both positively as well as negatively. Further-
more, the de level inserted is generally ( + Vcc/2), so that the positive output swing
equals the negative. This is accomplished by selecting R2 = R3• In the inverting
amplifier of Figure 7-4(a), the voltage at the noninverting terminal is approximately
( +Ycc/2) V de. Since the reactance of input capacitor C, at O Hz (de) is infinity, the
resistor R1 is an open component; hence the circuit effectively operates as a voltage
+
follower, producing an output of ( Vcc/2) V de. However, with ac input single v111,
the reactance of the input coupling capacitor C, is negligible, and the ac output
voltage e, at frequencies within the bandwidth is v0 = (-R,/R1)v111• Thus, as shown in
Figure 7-4(b) the ac output is riding on a de level of ( + Vcc/2) volts. The output
coupling capacitor C0 blocks this de voltage, and the resultant waveform is therefore
ac. Note that the maximum peak-to-peak output voltage swing is approximately
equal to + Vee volts. The noninverting ac amplifier using a single supply is shown in
Figure 7-4(c). Again, at O Hz or de the input capacitors C, and C1 act as open
components; therefore, the circuit effectively operates as a voltage follower, producing
238 GeneralLinearApplications Chap.7

ov
c1 R, RF
0.1 µF
+Vee v'0
co
1ookn Vee
R2 Vo
2
Vee Vo'
+- 2 ov t
roo ea R3 RL
1okn
Vo
ov
(a)
(b)
R,
+Vee v'0
Vee
-2-
0.1 µF ov
le)
(d)
Figure 7-4 {a) Ac inverting amplifier with single supply. (b) Its input and output wave-
forms. (c) Ac noninverting amplifier with single supply. (d) Its input and output wave-
forms.
239
the de output voltage of ( + Vee/2) volts. Note that the noninverting amplifier requires
an extra capacitor C 1 to produce an output de level of ( + Vee/2) volts. At frequencies
within the bandwidth the input .capacitors Cr.and C1 have negligible reactances; as .
. a result, the ac output voltage v of the amplifier is·
0
. V0 .: ( l + ~:)v,n
. The total output. voltage (de plus ac) ti., is as shown in Figure 7-4(d). The output
capacitor C0 blocks de voltage of(+ Vcc/2) volts, and hence the ac output voltage v0
results. . . . . . ' . .
Although :the.741C was
used as an ac amplifier with. a single supply voltage,
some op-amps, such as the LM124 series, are designed specifically to operate on a
single supply. These op-amps have a.wide power supply range and low input offsets.
For example, for the.LM324;
Power s~pply range = 3 to 30 V de
IB . 45 nA
'Ira....:.. 5 nA
V,0 = 2 mV
. Supply .current dr~in . ·. 800 ·µA independent of supply voltage·
·Example 7-2
' .
For the noninverting amplifier of Figure 7-4(c), R1a == 50 n;. C, = C1 ==: 0.1 µF,
R.1 = R1 = R3 = 100 ill, ~~ =:·1 MQ, and +Vee= +15-V. Determine (a) the
bandwidth of the amplifier and (b)' maximum output voltage swing. . ·
. .. . . : . ·.· :
Solution
(a) The ac input resistance _of. the amplifier is
R,P·,_, 100 kO II 100 k!l = 50 k!l
Therefore, from Equation (7-1),
1 . .
·. IL= (2nXI0-·7.)(50 k!l + sonj ~ 31.8 ~
The gain of the amplifier is (1 t Rp/ R 1) = 11. Hence from Equation (4- lOb)
· _ unity gain bandwidth _ 1 MHz :__ kH
jj8 - Ap - -1-1- - 90 ..91 z
.
and
BW = /H - IL.= 90.91 kO ., 0.0318 _kn,==°= 90.8S"°kHz .·
(b) The ideal maximum output voltage swing = + Vee = + 15 V pp.
1-4 THE PEAKING AMPLIFIER
The peaking response, that is, the frequency· response that peaks at a certain frequency
.can be obtained by using a parallel LC network with the op-amp. Figure 7-5(a)
shows a peaking amplifier that uses a parallel LC network in the feedback path.
The frequency response of the amplifier is shown in Figure 7-5(b). The resonant
240 GeneralLinearApplications Chap. 7

L
R1 RF Peak amplitude
c
....;,-
t
>o
c.·
·;;;
o
Vo
RL
RoM = .R1 II RF
-Vee 10 kn fp
-15 V 'Frequ~ncy
(a) (b)
Figure 7-5 The peaking amplifier. (a) Schematic diagram, (b) .Frequency response.
frequency or peak frequency at which the peaking occurs is determined by the com-
bination of L and C.
(7-5a)
where Qcoll = figure of merit of the coil. The impedance of the parallel-Zr" network
is very large at the resonant frequency. Therefore, the gain of the amplifier at reso-
nance is maximum and given by
AF= _RFIIRP (7-5b)
R1
where R11 = equivalent parallel resistance of the tank circuit= (Q;0uR) and,
R = internal resistance of the coil.
The impedance of the parallel LC network below and above the peak frequency is
less than R 11; therefore the gain of the amplifier is less than (RF II Rp/ R1) at any other
frequency than j]; Note that using Equation (7-5b) the impedance. of the tank circuit
R11 at resonance can easily be computed from the measured value of gain and known
values of R1 and RF. The bandwidth of the peaking amplifier of Figure (7-5a) can be
determined by using the following equation: ·
BW = f11 . (7-5c)
Qp
where /11 = peaking frequency
and, Q11 . figure of merit of the parallel resonant circuit = (RF II RPI XL)
Example 7-3
The circuit of Figure 7-5(a) is to provide a gain of 10 at a peak frequency of 16 kHz.
Determine the values of all components.
Sec. 7-4 The Peaking Amplifier· 241

\
Solution. The gain times peak frequency= (10)(16 kHz) = 160 kHz. Therefore, the
741C can be used in the circuit of Figure 7-5(a) since its 1 MHz unity gain bandwidth
is larger than 160 kHz.
Although any combination of L and C that provides the peak frequency of
16 kHz can be used, the value of the capacitor should be less than 1 µF to avoid.
leakage problems. Similarly to reduce the large .size of the inductors, it should be less
than 1 H in value. Let C = 0.01 µF. Then, using Equation (7-5a), the value of the
inductor is:
1
L = (2n)''(fp)2( C)
1
L = (4,r2)(16 k)2(10 S) = 9.9 mH
Let L be 10 mH. Also, Jet the internal resistance R of the inductor be 30-0. Then,
_ XL_ (21t)(16k)(lO)(l0-3) = 33 S
Qcou-R-. 30 .
and,
R.P = (Qc011)2(R) = (33.5)2(30) = 33.67 ill
Since a gain of 10 is needed at 16 kHz, let R1 be equal to 100 !l; therefore using
Equation (7-5b) the value of RF is
lO = (Rp)(33.67k)
lOO(RF + 33.67k)
that is,
RF = 1.03 k!l. (Use RF =1 ill)
To minimize the effect of input bias currents, use RoM approximately equal to
R1 II RF = 100 n. Thus, the component values are as follows:
Op-amp: 741C
R1 = 1oon
RF= 1 k!l
L= 10 mH having R1 = 30!l
C = 0.01 µF
7-5 SUMMING, SCALING, AND AVERAGING AMPLIFIERS
This section shows how the inverting, noninverting, and differential configurations
are useful in such applications as summing, scaling, and averaging amplifiers.
7-5.1 Inverting Configuration
Figure 7-6 shows the inverting configuration with three inputs V.,, Vb, and Ve. Depend-
ing on the relationship between the feedback resistor RF and the input resistors
R.,, Rb, and Re, the circuit can be used as either a summing amplifier, scaling amplifier,
or averaging amplifier. The circuit's function can be verified by examining the expres-
SiCf.l. for the output voltage V which is obtained from Kirchhoff's current equation
0,

--
1.
R. V2
-IF
F_lF
--
Rb
Ib
RC
+V c o----J\l\/1fJI,----' +
IC
RL Figure 7-6 Inverting configuration

with three inputs can be used as a
summing amplifier, scaling amplifier, or
averaging amplifier.
written at node V2• Referring to Figure 7-6,

I, + t, + Jc = JB + Ip (7-6)
Since R, and A of the op-amp are ideally infinity, IB = 0 A and V1 = V2 ~ O V.
'Therefore, ·
V 0 + Vb + Ve = _ V 0
Ro Rb Re s,
or
(7-7)
7-5.1 (a) Summing amplifier. If in the circuit of Figure 7-6, R =Rb= 0
R~ = R, for example, then Equation (7-7) can be rewritten as

V0 = ~ 1;.(Vo + Vb + Ve) (7-8a)
'This means that the output voltage is equal to the negative sumof all the inputs times
the gain of the circuit Rp/R; hence the circuit is called a summing amplifier. Obviously,
when the gain of the circuit is 1, that is, R =Rb= Re = RP, the output voltage is
0
equal to the negative sum of all input voltages. Thus

Va = -(Vo + Vb + Ve) (7-8b)
7-5.1 (b) Scaling or weighted amplifier. If each input voltage is ampli-

fied by a different factor, in other words, weighted differently at the output, the
circuit in Figure 7-6 is then called a scaling or weighted amplifier. This condition
can be accomplished if R,., Rb, and Re are different in value. Thus the output voltage
of the scaling amplifier is
V0 = -(;:v . +;:vb+ ;;vc) (7-8c)
where
Sec. 7-5 Summing, Scaling,and Averaging Amplifiers 243

7-5.1 (c} Averaging circuit. The circuit of Figure 7-6 canbe used as an aver-
. aging circuit' in which the output voltage. is equal to the average of all the input
voltages. This is accomplished by using all input resistors of equal value, Ra = Rb =
R. = R say. In addition; the gain by which each input is amplified must be equal to
1 over the number of inputs;. thatis, ...
RF . l
R=n-
where n is the. number of inputs.
Thus,' if there are three inputs (as shown in Figure 7-6), we want RF/R = 1/3.
Consequently, from Equation (7-7). · ·
V0 = -(Va+ ~b + v.) (7-8d)
Remember that in the applications above the inputs Va, Vb, and v. could be either
ac or-de. These circuits are commonly used in analog computers and audio mixers,
in which a number of inputs is added up (mixed) to produce a desired output.
In Figure 7-6 the offset minimizing resistor RoM is used to minimize the effect of
input bias currents on the output offset voltage. However, to reduce the output offset
voltage to zero, the offset voltage compensating network must be used, especially
when the inputs are de voltages.
Example 7-4
In the circuit of Figure 7-6, Va= +l V, Vi= +2 V, Ve= +3 V, Ra= Rb= Re=
3 k.O, RF= I k.O, RoM = 2700, and supply voltages= ±15 V. Assuming that the
op-amp is initially nulled, determine the output voltage V 0•
Solution. Using Equation (7-Sa), we obtain .

· 1 k.O .
Vo= - 3 kQ(l + 2 + 3) = -:-2 V
This value is equal to the average of three inputs with a negative sign.
7-5.2 Noninverting Configu,:ation
If input voltage sources and resistors areconnected to the noninverting terminal as

shown in Figure 7-7, the circuit can be used either as a summing or.averaging amplifier
through selection of appropriatevalues of resistors, namely R1 and Rp.
Again, to verify the functions of the circuit, the expression for tne output voltage
must be obtained. Recall that the input resistance R,F of the noninverting amplifier
· is very large (see Figure 7-7). Therefore, using the superposition theorem, the voltage
V1 at the noninverting terminal is ·· ·
_ R/2 1 . R/2 R/2
Vi - R + R/2 Va+ R + RJ2 Vb+ R + R/2 Ve
or
V 1 := Va + Vb·+ Ve
.• ·3 .3 3
= Va + Vb3 +. V. (7-9)
Hence the output voltage V is 0

. R; RF
+Vee
Vo= (1 + ::)(v• + ~b + v.)

+v,
R'L
+Vb -Vee I
R
+v. Figure 7-7 Noninverting configuration
with three inputs can be used as
AR1 averaging amplifier or summing ·
RIF ;;;;; R;
R1 + RF amplifier.
(7-IOa)
7-5.2(a} Averaging amplifier. Equation (7-lOa) shows that the output

voltage is equal to. the average of all input voltages times the gain of the circuit
(l + RF/R1), hence the name· averaging amplifier. Depending on the application
requirement, the gain (l + RF/R1) can be set to a specific value. Obviously, if the
voltage follower is used, the output voltage will be equal to the average of all input
voltages.
Note that there are two basic differences between this averaging amplifier and
that using the inverting configuration [see Equations (7-8d) and (7-lOa)]:
1. No sign change or phase reversal occurs between the average of the inputs
and output ..
2. The noninverting input voltage V1 is the average of all inputs, where as in the
inverting averaging amplifier, the output is th~ average of all inputs, with a
negative sign. ·
7-5.2(b) Summing amplifier. A close examination of Equation (7-lOa)

reveals. that if the gain (1 + Rp/R1) is equal to the number of inputs, the output
voltage becomes equal to the sum of all input voltages. That is, if (I + RF/R1) = 3
[from Equation (7-lOa)],
(7-IOb)
Hence the circuit is called a noninverting summing amplifier.
Again, when the 'circuit of Figure 7-7 is used as either ari averaging or summing
amplifier, offset" null circuitry or anoffset null cotnpensating network must be "used
to improve its accuracy.
Sec. 7-5 Summing, Scaling, and AveragingAmplifiers 246

Example 7-S
In the circuit of Figure 7-7, supply voltages= ±15 V, Va= +2 V, Vb= -3 V, V,
= +4 V, R = R1 = 1 kQ, and Rp = 2 kQ. Determine the voltage Vi at the non-
inverting terminal and the output voltage Va. Assume that the op-amp is initially
nulled.
Solution. Using Equation {7-9),
V 1-
_2-3+4_1V
3 -
which is the average of three inputs: +2 V, -3 V, and !J--4 V. From Equation (7-lOa),
V0 = (1 + im)(l) = 3 V
which is the sum of the three inputs.
1-5.3 Differential Configuration
Using a basic differential op-amp configuration, a subtractor and a summing amplifier

may be constructed as described below.
7-5.3(a) A subtractor . A basic differential amplifier can be used as a

subtractor as shown in Figure 7-8. In this figure input signals can be scaled to the
desired values by selecting appropriate values for the external resistors; when done
so the circuit is referred to as scaling amplifier. However, in Figure 7-8, all external
resistors are equal in value, so that the gain of the amplifier is equal to 1.
R R
+Vee
Figure 7-8 Basic differential amplifier

used as a subtractor.
From this figure, the output voltage of the differential amplifier with a gain of l is
[see Equation (4-25)]
That is,
(7-11)
Thus the output voltage V is equal to the voltage Vb applied to the noninverting
0
terminal minus the voltage Va applied to the inverting terminal; hence the circuit is
called a subtractor.

7-5.J(b) Summing amplifier. A four-input summing amplifier may be
constructed using the basic differential amplifier of Figure 7-8 if two additional input
sources are connected, one each to the inverting and noninverting input terminals
through resistor R (see Figure 7-9). ·
+Vee
R
R
+VCO--"'V'll'lllr-- ...
Figure 7-9 Summing amplifier using

differential configuration.
The output voltage equation for this circuit can be obtained by using the
superposition and Thevenin's theorems. For instance, to find the output voltage due
to V0 alone, reduce all other input voltages Vb, Ve, and V., to zero as shown in Figure
7-IO(a). Then Thevenize the circuitto the left of node V2• The resulting circuit is shown
in Figure 7-lO(b). In fact, this circuit is an inverting amplifier whose output voltage is
R V
VOii = - R/2-i° = -v..
Similarly, the output voltage due to Vb alone is
v..b = -Vb
+v. R R
R
3
(al lb)
Figure 7-10 Deriving the output voltage equation for the summing amplifier of Figure 7-9.
Sec. 7-5 Summing. Scaling, and Averaging Amplifiers 247

Now ·if input voltages Va, Vb, and Vd are set to zero, the circuit in Figure 7-9
becomes a noninverting amplifier in which the voltage V1 at the noninvertinginput is ·
. R/2 . Ve
V, = R + R/2 Ve = 3.
This means that the output voltage due to Ve alone is
. V,,c ~ (1 + .,{J2)v, =·(3)(~e) . Ve

Similarly, the output voltage due to input voltage Vd alone is
vod.....: vd
Thus the output voltage due to all four input voltages is given by
Vo = Voa + Vob + V.e + Vod
= --'-- Va
- Vb + Ve +
Vd (7-12)
Notice that the output voltage is equal to the sum ·of the input voltages applied to
the noninverting terminal plus the negative sum of the input voltages applied to the
inverting terminal. Even though in Figure 7-9 the gain of the summing amplifier is I,
any scale factor can be used for the inputs by selecting proper external resistors.
Example 7-6
In the circuit of Figure 7-9, R = 1 kn, V = +2 V, Vi= +3 V, Ve = +4 V,
0
Vd = +5 V, and supply voltages= ±15 V. Determine the output voltage V Assume 0•
that the op-amp is initially nulled.

v. = -2 - 3 + 4 + 5 = +4 V
7-6 INSTRUMENTATION AMPLIFIER

In many industrial and consumer applications the measurement and control of phys-
ical conditions are very important. For example, measurements of temperature and
humidity inside -a dairy or meat plant permit the operator to make necessary adjust-
ments to maintain product quality. Similarly, precise temperature control of plastic .
furnace is needed to produce a particular type of plastic.
Generally, a transducer is used at the measuring site to obtain required informa-
tion easily and safely. The transducer is a device that converts one form of energy
into another. For example, a strain gage when subjected to pressure or force (phys-
ical energy) undergoes a change in its resistance (electrical energy). An instrumenta-
tion system is used to measure the output signal produced by a transducer and often
a
to control the physical signal producing it. Figure 7-11 shows simplified form of
such a system. The input stage is composed of a preamplifier and some sort of trans- ·
ducer, depending on the physical quantity to be measured. The output stage may use
devices such as meters, oscilloscopes, charts, or magnetic recoders. In automatic
instrumentation systems the output stage also includes an automatic process controller
that compensates for. changes in operating conditions.
In Figure 7-11 the connecting lines between the blocks represent transmission
lines, especially when the transducer is at a remote test site monitoring hazardous
248 .General Linear Applications Chap. 7

Transmission lines
.Physical quantity __ -..t lnputstaqe

Intermediate Output
to be measured stage stage
Transducer I Instrumentation Indicator and ·

+ preamplifier amplifier automatic process
controller
Figure 7-11 Block diagram ofan instrumentation system.
conditions such as high temperatures or the liquid levels of flammable. chemicals.

These transmission lines permit signal transfer from unit to unit. The length of trans-
mission iines depends primarily on the physical -quantities to be monitored and ·on
system. requirements. . .
The signal source of the instrumentation amplifier is the.output of the transducer.
· Although some transducers produce outputs with sufficient strength to permit their
use directly, many do not. To .amplify the low-level output signal of the transducer
so thatit can drive.the indicator or display is the major function of the instrumenta-
tion amplifier. In short, the instrumentation amplifier· is intended for precise, low-
level signal amplification where low noise, low thermal. and time drifts, high input
resistance, and accurate closed-loop gain are required. Besides that, low power con-
sumption, high common-made rejection ratio; and high slew rate are desirable for
superior performance.
There are many instrumentation operational amplifiers, such as the µAn,s,
ICL 7605, and LH:0036,. which make a circuit extremely stable and accurate. These
ICs are, however, relatively expensive; they _are very precise special-purpose circuits
· in which most 'of the electrical parameters, such as offsets, drifts, and power consump-
tion, are minimized, ·whereas input resistance, CMRR, and supply range are opti-
mized. Some instrumentation amplifiers are even available in modular form to suit
special installation requirements.
Obviously, the requirements for instrumentation op-amp are more rigid than
those for general-purpose applications. However, where the requirements are not too
strict, the general-purpose op-amp can be employed in the differential mode. The
differential amplifiers discussed in Chapter 4 can be employed as instrumentation
amplifiers. We will call~ such .amplifiers differential instrumentation amplifiers. Since
'most of the instrumentation systems use a transducer in a bridge circuit, we will con-
sider a· simplified differential instrumentation system arrangement using a transducer
· bridge circuit.
7-6.1 Instrumentation Amplifier Using Transducer Bridge
Figure 7-12 shows a simplified differential instrumentation amplifier using a transducer

bridge. A resistive transducer whose resistance changes as a function of some physical
energy is connected in one arm of the bridge with a small circle around it and is
Sec. 7-6 lnstr.umentation Amplifier 249

denoted by (RT± l:!.R), where RT is the resistance of the transducer and l:!.R the change
in resistance RT.
The bridge in the circuit of Figure 7-12 is de excited but could be ac excited as
well. For the balanced bridge at some reference condition:
Vb= Vo
or
RJVdc) RA(Vdc)
RB + Re -. RA + RT
That is,
(7-13)
Generally, resistors RA, RB, and Re are selected so that they are equal in value to.the
transducer resistance RT at some reference condition. The reference condition is the
specific value of the physical quantity under measurement at which the bridge is ·~
balanced. This value is normally established by the designer and depends on the
transducer's characteristics, the type of physical quantity to be measured, and the
desired application. .
The bridge is balanced initially at a desired reference condition. However, as
the physical quantity to be measured changes, the resistance of the transducer also
changes, which causes the bridge to unbalance (V0 ;:/=. Vb). The output voltage of the
Resistive
transducer
+Vee
+ v.
vdc
+Vee
-Vee
v; v.b Vo
+Vee
-Vee RL
RF (CJ
-Vee
R.m
Indicating
meter
Figure 7-12 Differential instrumentation amplifier using transducer bridge.
250 General Linear Application's .Chap. 7

bridge can be expressed as a function of the change in resistance of the transducer,
as described below.
Let the change in resistance of the transducer be 11R. Since RB and Re are fixed
resistors, the voltage Vb is constant. However, voltage V varies as a function of the
0
· change in transducer resistance. Therefore, according to the voltage divider rule,

v - RA(Vdc)
0
- RA + (Rr + 11R)
V _ Rs(Vdc)
b - KB+ Re
Consequently, the voltage V b across the output terminals of the bridge is
0
Vob = Vo - Vb
-
RAVdc
=--~~'--c-=
R11 + s; + 11R
However, if RA= RB= Re= Rr = R, say then
V 11R(Vdc)
ob = - 2(2R + !iR) (7-14)
The output voltage V b of the bridge is then applied to the differential instrumenta-
0
tion amplifier composed of three op-amps (see Figure 7-12). The voltage followers
preceding the basic differential amplifier help to eliminate loading of the bridge
circuit. The gain of the basic differential amplifier is (Rp/ R 1); therefore, the output
V of the circuit in Figure 7-12 is
0
V _ V (RP)._ -(/iR)Vdc R;
0
ob
- R; - 2(2R + 11R)R 1
(7-15)
This means that V is a function of the change in resistance !iR of the transducer.
0
Since the change in resistance is caused by change in physical energy, a meter con-
nected at the output can be calibrated in terms of the units of that physical energy.
If a transducer operates within its specified limits, the change in resistance !iR can be
assumed to be linear.
Before proceeding with specific bridge applications, let us briefly consider the
important characteristics of some resistive types of transducers. In these resistive
types of transducers the resistance of the transducer changes as a function of some
physical quantity. The thermistors, photoconductive cells, and strain gages are some
of the most commonly used resistive transducers; hence they will be further discussed
here.
Thermistors are essentially semiconductors which behave as resistors, usually
with a negative temperature coefficient of resistance. That is, as the temperature of a
thermistor increases, its resistance decreases. The temperature coefficient of resis-
tance is expressed in ohms per unit change in degrees Celsius (°C). Thermistors with
a high temperature coefficient of resistance are more sensitive to temperature change
and are therefore well suited to temperature measurement and control. Thermistors
are available in a wide variety of shapes and sizes. However, thermistor beads sealed
in the tips of glass rods are most commonly used because they are relatively easy to
mount.
Sec. 7-6 Instrumentation Amplifier 251

The photoconductive cell belongs to the family ·Of photodetectors (photosensi-
tive devices) whose resistance varies with an incident radiant energy or with light.
As the intensity of incident light increases, the resistance of the cell decreases. The
resistance of the photoconductive cell in darkness is typically of the order of 100 kn.
Generally, the resistance of the cell in darkness and at particular light intensities is
listed on the data sheet. The intensity of light is expressed in meter candles (lux).
Materials such as cadmium sulfide and silicon, whose conductivity is a function
of incident radiant energy, are used for photoconductive cells. Some cells are extremely
sensitive to light and hence can be used into the ultraviolet and infrared regions.
The 'photoconductive cell is typically composed of a ceramic base, a layer of photo-
conductive material, a moisture-proof enclosure, and metallic leads. Photoconductive
cells are also known as photocells or light-dependent resistors (LDRs).
Another important resistive transducer is the strain gage, whose resistance
changes due to elongation or compression when an external stress is applied. The
stress is defined as force per unit area [Newtons/(meter)2) and can be related to
pressure, torque, and displacement. Therefore, a strain gage may be used to monitor
change in. applied pressure, torque, and displacement by measuring the corresponding
change in the gage's resistance. ·
Two basic types of strain gages are the wire and semiconductor. Semiconductor
strain gages are much more .sensitive than the wire type, and therefore provide better
accuracy and resolution. T)1e sensitivity of a. strain gage is defined as unit change iii.
a
resistance per unit change.in length and is dimensionless quantity. · ,,
The thermistor, photocell, and strain g~ge·are all passive transducers, meaning
that they require external voltage (ac or de) for their operation.
7-6.1 (a) 'Temperature indicator : ·The circuit ofFigure 7-12 canbe used
as a temperature indicator ff the transducer in the bridge circuit is a thermistor and
the output meter is calibrated in degrees centigrade or Fahrenheit. The bridge can .be
balanced at a desired reference condition, say ·2s°C. As the temperature varies from
its ref ere nee value, the· resistance of the thermistor changes .and the bridge becomes
unbalanced. This unbalanced bridge in turn· produces the meter movement. The
meter can be calibrated to read a desired temperature range by selecting an appro-
priate gain for the differential instrumentation amplifier. In Figure 7-12· the meter
movement is dependent on the amount of imbalance in the bridge, that is, the change
.::1R in the value of the thermistor resistance. The .::1R for the thermistor, however,
can be determined as follows: .::1R = (temperature coefficient of resistance) (final
temperature - reference temperature.) See Exarnplez-Z,
Example 7-7
In the circuit of Figure 7-12, R1 = I kn, Rp = 4.7 kn, RA = RB= Re = 100 kn,
Vdc = +5 V, and op-amp suppjy voltages = ± 15.V. The transducer is a thermistor
with the following specifications: Rr = 100 kQ. at a reference temperature of 25°C;
temperature coefficient of resistance = -1 kn/°C or I %/ C. Determine the output
0
voltage at 0°C and at 100°C.

Solution. At 25°C, RA = RB = Re= Rr = 100 kn. Therefore, the bridge is bal-
anced ( V = Vb) and V = 0 V. However, at 0°C the change .::1R in the resistance of
11 0
1im
the thermistor is .::1R =;= ( - (0°C - 25°C) = 25 kQ
252 General Linear Applications, Chap. 7

Therefore; using Equation 7-15, at 0°C,
-(25 K)(5) 4.7 K
Vo = 2(200 K + 25 K) • 1K = - I .3 l V
Similarly, at, 100°C, ~R = -lo~ n(l00°C - 25°C) = -75 xo and,
-( - 75 K)(5) 4.7 K
Vo = 2(200 K .:_ 75 K) • TK = 7.05 V
Thus, when V0 = -1.31 Y, the !Tfter face can be marked as 0°C and when V0 =
7.05 V, it can be marked as 100°C. Note that at 25°C, V0 = 0 Y; therefore, a center-
zero meter is required. Assuming that the resistance-temperature characteristic of the
thermistor is linear, the meter may be interpolated linearly between 25° to 0°C and
25° to 100°C.
Thermistors with relatively higher resistance (Rr > 1 M!l) and sensitivity (tem-
perature coefficient of resistance > 3 %/°C) are best suited for remote measurements
because the effect of transmission line resistance is negligible.
7-6.1 (b) Temperature controller. A simple and inexpensive tempera-

ture control circuit may be constructed by using a thermistor in the bridge circuit
and by replacing a meter with a relay in the circuit of Figure 7-12. The output of the
differential instrumentation amplifier drives a relay that controls the current in the
heat-generating circuit. A properly designed circuit should energize a relay when
the temperature of the thermistor drops below a desired value, causing the heat unit
to turn on.
7-6.1 (c) Light-intensity meter. The circuit in Figure 7-12 can be used
as a light-intensity meter if a transducer is a photocell. The bridge can be balanced
for darkness conditions. Therefore, when exposed to light, the bridge will be unbal-
anced and cause the meter to deflect. The meter can be calibrated in terms of lux to
measure the change in light intensity.
The light-intensity meter using an instrumentation bridge amplifier is more
accurate and stable than single input inverting or noninverting configuration
because the common-mode (noise) voltages are effectively rejected by the differen-
tial configuration.
7-6.1 (d) Measurement of flow and thermal conductivity. A flow

meter or a thermal conductivity meter may be constructed using the circuit of Figure
7-12, provided that two thermistors are used adjacent to each other in the bridge. For
instance, assume that Re and R; represent two identical thermistors. For the flow
measurement one thermistor is sealed in a small-cavity copper cylinder and the other
installed in a small copper pipe. When no air flows through the pipe, the bridge can be
balanced so that the output voltage is zero. When air flows over the thermistor, its
temperature decreases and in turn the resistance increases, causing the bridge to be
unbalanced. This unbalanced voltage is then amplified by the differential instrumenta-
tion amplifier and applied to the meter. Thus the amount of meter deflection is
proporational to the flow rate of the air in the pipe. The meter can be calibrated in
(meter)3/s to accommodate a desired flow rate range.
Sec. 7-6 Instrumentation Amplifier 253

For the thermal conductivity measurement, two thermistors are mounted in
separate small copper cylinders. With air in both cylinders, the bridge can be balanced,
and hence the output will be zero. When air in one cylinder is replaced by a medium
being tested, which has a different thermal conductivity than air, the bridge becomes
unbalanced. This happens because the temperature of the thermistor changes, thus
changing its resistance. Suppose that the medium being tested is carbon dioxide
(C0)2• Because of its lower thermal conductivity, C02 will increase the temperature
of the thermistor, which will cause a decrease in the thermistor's resistance. This
results in unbalancing the bridge, which in turn produces a meter deflection. The
meter can be calibrated in terms of relative thermal conductivity (cal/s-crn-X').
7-6.1 (e) Analog weight scale. By connecting a strain gage in the bridge,
the circuit of Figure 7-12 can be converted into a simple and inexpensive analog
weight scale.
In the analog weight scale, strain gage elements are connected in all four arms
of the bridge. The elements are mounted on the base of the weight platform so that
when an external force or weight is applied to the platform, one pair of elements in
the opposite arms elongates, whereas the other pair of elements in the opposite arms
compresses. In other words, when the weight is placed on the platform, Rr1 and
RT3 both decrease in resistance, and Rrz and Rr4 both increase in resistance, or vice
versa (see Figure 7-13).
To differential
instrumentation
amplifier
Figure 7-13 Strain-gage bridge circuit
for analog weight scale Rr1 = Rrz =
Rr3 = Rr4.
When no weight is placed on the platform, the bridge is balanced Rri = Rrz =
RTJ = RT4 = R, say, and the output voltage of the weight scale can be zero. When a
weight is placed on the scale platform, the bridge becomes unbalanced. Assuming
that Rri and RT3 decrease in resistance and Rrz and 'Rr4 increase in resistance by the
same number of ohms !),.R, the unbalanced voltage· V.,b is given by
V.,bl= + Vdc ( ~) (7-16)
where Vdc = de excitation voltage of the bridge

R = Rn = Rr2 = RT3 = Rr4 = unstrained gage resistance
!),.R = change in gage resistance
Remember that if the decrease in gage resistance Rn and Rr3 is !),.R, the increase in
resistance of Rr2 and RT4 is also !),.R.
254 General Linear Applications . Chap. 7

The voltage V.,6 is then amplified by the differential instrumentation amplifier,
which drives the meter. Since the gain of the amplifier is ( + Rp/ R1 ), the output voltage
V0 is
Vo -- vde (lR
!,.R) RF
R1 (7-17)
The gain of the amplifier can be selected according to the sensitivity of .the strain
gage and the full-scale deflection requirements of the meter. The meter can be calib-
rated in terms of kilograms. ,
For better accuracy and -resolution, a microprocessor-based digital weight
scale may be constructed. However, such a scale is much more complex and expensive
than the analog scale.
Example 7-8
The circuit of Figure 7-12 is used as an analog weight scale with the following speci-
fications. The gain of the differential instrumentation amplifier = 100. Assume that
Vic = + 10 V and that the op-amp supply voltages = ± 10 V. The unstrained resistance
of each of the four elements of the strain gage is 100 n. When a certain weight is placed
on the scale platform, the output voltage V0 = 1 V. Assuming that the output is ini-
tially zero, determine the change in the resistance of each strain-gage element.
Solution. Using Equation (7-17),
1 =
s«
(10)100(100)
Therefore, l!,.R = 0.1 n. This means that Rr1 and Rn will decrease by 0.1 n if Rr; and
Rr4 increase by 0.1 n when a certain weight is placed on the scale platform.
7-7 DIFFERENTIALINPUT AND DIFFERENTIALOUTPUT

AMPLIFIER
In all the applications discussed so far, the op-amp is used with a single-ended or
unbalanced output. However, in certain applications a differential output is required.
The differential input and differential output amplifier is most commonly used as
preamplifier and in driving push-pull arrangements.
Figure 7-14(a) shows one possible arrangement of a differential input and dif-
ferential output amplifier using two identical op-amps, that is, a dual op-amp. For
example, the µAF772 dual op-amp incorporates two well-matched op-amps. The
connection diagrams of the 8-pin mini DIP and 14-pin DIP are shown in Figure
7-14(b). The analysis of the circuit in Figure 7-14(a) can be accomplished by deter-
mining the output of each op-amp due to the differential input. Using the superposi-
tion theorem, the output V due to inputs v. and Vy is
0.,,
(7-18a)
Similarly, the output V07 is

(7-18b)
Sec. 7-7 Differential Input and Differential Output Amplifier 255

R, RF
+Vee
v..
v. +
+
-VEE
R, RF
Vo
v;
+Vee
(al
14
-In A Offset
nu.II A
2 13
+In A V+ A 8
Out A v+
Offset
n~II A Out A
-In A Out B
v- NC
+In A -In B
Offset
n,,lt B Out B 4 5
9 v- +In B
+In B V+ B
8 8-pin mini dip
-In 8
Offset
nllll B µAF772
14-pin dip
µAF772
(b)
Figure 7-14 (a) Differenda1 input and differential output amplifier using a dual
op-amp. (b) The connection diagram of a typical dual op-amp. (Note especially
the difference between the supply voltage and offset-null connecrions.) (Courtesy
of Fairchild Camera and Instrument Corporation.)
256
However, the diff erentia1 output V0 is
Va :!:: Vax -- Vo>•
Therefore, from Equations (7-18a) and {7-18b),
Vo= (1 + ~:)vx - (~;)vy -·· (1 ·: 1:)v. · (~~:)v .

= (l + 2:1P)(Vx- Vy)
or I
(7-18c)
This means that the differential input and output arc in phase or of the same polarity
provided that Vin = Vx - Vy and V~ = V V,._,.. 0.., ---
The differential input and output amplifier of Figure 7-1.4(a_l is very useful in
noisy environments, especially if the input signal is relatively smaller because it
rejects the common-mode noise voltages. 'Recall also that the output voltage swing
with differential output is twice as large as that with a single-ended output.
Another important advantage of the differential" input and output amplifier is
that it produces a bipolar output with a single supply.
Example 7-9
The differential input and output amplifier of Figure 7-141.a) is used as a preamplifier
and requires a differential output of at least 3.7 V. Deterrnme the gain of the circuit
if the differential input v1n = 100 mV.
Solution. Using Equation (7-1 Sc), we get
3.7 = (1 + ~:t)ooo100-3,
1 + 2RP
R1
= 37 or RF = l 8RI
If R1 = 100 n, then RP.= 1.8 kQ.
7-8 VOLTAGE-TO-CU.RRENTCONVERTER- WITH FLOATING

LOAD
figure 7-15 shows a voltage-to-current converter in which load resistor R1. is floating
(not connected to ground). The input voltage is applied to the noninverting input
terminal, and the feedback voltage across R, drives the inverting input terminal.
This circuit is also called a current-series negative feedback amplifier because the
feedback voltage across R1 (applied to the inverting terminal) depends on the output
currentr, and is in series with the input difference voltage v,a-
Writing Kirchhoff's voltage equation for the input loop.
Vin= V1d + 111
But v td :::: 0 V, since A is very large; therefore,
Vin= Vt
V111 = R1io
Sec.7-8 Voltage-to-Current Converter with Floating Load 257

v,
-
-
i0 = output current
Figure 7-15 Voltage-to-current

converter with floating load.
or
• Vin (7-19)
i, = R1
This means that in the circuit of Figure 7-15, an input voltage v,n is converted into
an output current of v, /R,. In other words, input voltage v,n appears across R,. If
0
R1 is a precision resistor, the output current (i = v,nl R 1) will be precisely fixed.

0
The voltage-to-current converter can be used in such applications as low-

voltage de and ac voltmeters, diode match finders, light-emitting diodes (LEDs),
and zener diode testers .
. 7-8.1 Low-Voltage DC Voltmeter
If in the converter circuit of Figure 7- 1 5, we replace the load resistor RL by an ammeter

(D'Arsonval meter movement) with a full-scale deflection of l mA, the resulting
circuit is the de voltmeter of Figure 7-16. This figure shows an external offset voltage
compensating network which is used because it makes the nulling of the op-amp
relatively easy. Using the offset null circuitry of the 741 (10-kn potentiometer), the
op-amp sometimes cannot be nulled because the output is very sensitive to even
slight variations in wiper position.
The Thevenin equivalent resistance of the compensating network is approxi-
mately equal to 926 n ( 12.5 kn 111 kn). Therefore, when the switch is in x 1 position,
R1 = 926 + 100 = 1.026 kn - 1 kn
If v,. = 1 Y, then
-
I .-y= r; . . . ., I V -
I kn-
I
m
A
I
This means that I V causes the full-scale deflection· of the ammeter.

If the range switch is changed to >: 10 position (926 n +
9 kn......., 10 kn), it will
require a 10-Y input to get full-scale deflection. Thus successively higher resistance
values are required to measure relatively higher input voltages. However, the input
voltage range for the 741 C op-amp is -±: 14 V. Therefore, with ± 15 V supply voltages,

Offset-voltage
compensating D'Arsonval meter
movement 1 mA
r---:e1=~----,
I
I
I
I
12 kn
9kn
full-scale deflection
I +15 V I
I I 1kS1 X 10 Switch
I I
I X2
10kfl ~--'VVVy,-~----;-l
---~w.,,,,,..----' X 1
I
1 kn I
-15 V I
I 2
I
I
I
L-----------__J 3
-15 V
926n
Figure 7-16 De voltmeter with 1 to 13 V full-scalerange.
the maximum input voltage has to be< ±14 V. In Figure 7-16 the maximum full-
scale input voltage of 13 V can be applied when the range switch is in x 13 position.
Thus by calibrating the face of the ammeter in volts, a de voltmeter with a
full-scale voltage range of 1 to 13 V can be constructed. Note that meter resistance
Rm does not affect 10• Only V;11 and R1 determine the 10 value.
A centered-zero ammeter can be used to measure positive as well as negative
input voltages. To improve the accuracy of voltage measurements, the ammeter
should be nulled each time before input voltage is applied.
7-8.2 Low-Voltage AC Voltmeter
It is also possible to modify the meter movement so that it will indicate values of ac
voltage or current. A combination of an ammeter and a full-wave rectifier can be
employed in the feedback loop to form an ac voltmeter, as shown in Figure 7-17.
In this circuit an alternating current is converted into a direct current. During the
positive half-cycle of the ac input diodes D1 and D3 conduct, whereas diodes D2
and D 4 conduct during the negative half-cycle of V111, Thus the current through the
ammeter flows only in one direction (A to B) for the entire cycle of the ac input.
In other words, the ammeter registers the average (de) value of the rectified current.
The amount of deflection of the pointer must be considered for proper scale calibra-
tion. For full-wave rectification, meter current can be expressed as
(7-20a)
or
(7-20b)
Sec. 7-8 Voltage-to-Current Converter with Floating Load 269

Bridge
rectifier
A
- io
i0 f
0
-t
6.B k.11
4.7 k.11
t B
+Vee +15 V
Rm
X 6.B
2k.\1 X 4.7 io
Switch 2
X2 1 mA full-scale
1 k.11 '.'1;0 6 meter movement
X 1
A1 3
-Vee-15V
Figure 7-17 Ac voltmeter.
where i0 = de meter current (amperes)

v10 = ac rms input voltage (volts)
R1 = resistance in series with the meter (ohms)
Using Equation (7-20b), the ammeter face can be calibrated to read an rms value of
the input voltage.
Rectifier-type meters are designed primarily for ac frequencies in the audio
range. However, because of the low slew rate of the 741 C op-amp, the frequency of
the input signal should be less than 4 kHz for proper operation of the voltmeter.
Also, the peak inverse voltage (PIV) of the diodes is recommended to be larger than
the saturation voltages of the op-amp.
Example 7-10
In the circuit of Figure 7-17, for the indicated values of resistors, determine the full-
scale range for the input voltage.
Solution. The full-scale meter movement is 1 mA. Therefore, substituting minimum
and maximum values of resistor ·R1 in Equation (7-20b), we can determine the range
1
for the input voltage.
V1n(rms)lminimum = (l.1)(1 kn)(l mA) = 1.1 Y
V1n(rms)lmoximum = (1.1)(6.8 kQ)(l mA) = 7.48 Y
Thus the full-scale input voltage ranges from I.I to 7.48 V rrns or 3.1 to 21:16 V peak
to peak. Note that since the input voltage range for the 741C is± 14 Y, the input voltage
swing must be less than 28 V peak to peak for safe operation of the circuit.

7-8.3 Diode Match Finder
In some circuits; such as the ring modulator and Foster-Sealy discriminator, it is neces-
sary to have matched diodes with equal voltage drops at a particular value of diode
current. The circuit shown in Figure 7-18 can be used in finding matched diodes and
is obtained from Figure 7-15 by replacing RL with a diode.
v'.,
"M\/5054·1
LED
Zener diode 1 N4735
Rectifier diode 3
1N4001
--
Switch
R,
Ia
100.n +15 V
k
18;:;; 0 lh 2
-15 V
10 kil Offset null circuit
Figure 7-18 Diode match finder.
When the switch is in position I, the rectifier diode 1 N4001 is placed in the
feedback loop; the current through th is loop is set by input voltage Vin and resistor
R1• For V1n =IV and R1 = JOOQ, the current through the diode is
Io= ~1; = 1bo = 10 mA

As long as Via and RI are constant, the current 1 will be constant. The voltage drop
0
across the diode can be found either by measuring the voltage across it or the output
voltage. The output voltage is equal to (Via +
Vn). To avoid an. error in output
voltage, the op-amp should be initially nulled.
Thus the matched diodes can be found by connecting diodes one after another
in the feedback path and measuring the voltage across them. A desired testing current
1 can be established by selecting an appropriate combination of V1n and R1•
0
Example 7-11
In the circuit of Figure 7-18 when the switch is in position 1, Vin = 0.5 Y and V = 0
1.2 Y. Determine the current through the diode and the voltage drop across it. Assume
that the op-amp is initially nulled.
Sec. 7-8 Voltage-to-Current Converter with Floating Load 261

Solution
_ Via _ 0.5 _ 5 A
1a - 7f; - 100 - m
VD= Va - Via= 1.2 - 0.5 = 0.7 V
7-8.4 Zener Diode Tester
The circuit of Figure 7-18 becomes a zener diode tester when the switch is placed in
position 2. This circuit can be used to find the breakdown voltage of zener diodes.
Via and R1 set the zener current at a constant value. If this current is larger than the
knee current (T,k) of the zener, the zener blocks V, volts. For example, the 1N4735
zener in the circuit of Figure 7-18 has l,k = 1 mA and V, = 6.2 V. Since the current
through the zener is
V 1
la= RI~= 100 = lOmA >l,k
the voltage across the zener will be approximately equal to 6.2 V.

Matched zeners are useful in obtaining split(±) supply voltages from a single
supply.
7-8.5 Light-Emitting Diode Tester
The circuit of Figure 7-18 can be converted into a light-emitting diode (LED)
tester when the switch is in position 3. Again the LED current is set at a constant
value by Via and R1• The LEDs can be tested for brightness one after another at
this current. Matched LEDs with equal brightness at a specific value of current are
useful as indicators and display devices in digital applications.
In all the applications described above it should be remembered that the
maximum current through the load (ammeter, rectifier and zener diodes, or LED)
cannot exceed the short-circuit curent of the op-amp. For the 7MC this current is
25 mA.
7-9 VOLTAGE-TO-CURRENT CONVERTER WITH GROUNDED

LOAD
Another version of the voltage-to-current converter is shown in Figure 7-19. In this

circuit one terminal of the load is grounded, and load current is controlled by an
input voltage. The analysis of the circuit is accomplished by first determining the
voltage V, at the noninverting input terminal and then establishing the relationship
between V1 and the load current. '
Writing Kirchhoff's current equation at node V1,
/1 +I,.= i:
V, 0 -
R
V1 + VO -R V1 = I
L
Vin+ Vo - 2V, = hR

A R
+
Load
Figure 7-19 Voltage-to-current

converter with grounded load.
Therefore,
VI _
-
Vi,. + Vo - hR
2 (7-21a)
Since the op-amp is connected in the noninverting mode, the gain of the circuit in
Figure 7-19 is 1 + R/R = 2. Then the output voltage is
V0 = 2 V1 = Vi .. + Vo - hR
That is,
or
I - V1,. (7-21b)
L-R
This means that the load current depends on the input voltage Vi,. and resistor R.
Notice that all resistors must be equal in value.
The voltage-to-current converter of Figure 7-19 may also be used in testing such
devices as zeners and LEDs forming a ground load. However, the circuit will perform
satisfactorily provided that load size < R value.
Example 7_-12
In the circuit of Figure 7-19, Vi,. = 5 V, R = 10 kO, and Vi = 1 V. Find (a) the load
current and (b) the output voltage Va. Assume that the op-amp is initially nulled.
Solution
(a) Using Equation (7-21b),
IL= ~n = 105kh = 0.50 mA

(b) Since Vin= hR, from Equation (7-21a), Va= 2Vi = 2 V.
Sec. 7-9 Voltage-to-Current Converterwith GroundedLoad 263

7-10 CURRENT-TO-VOLTAGE CONVERTER
In Chapter 4 the current-to-voltage converter was presented as a special case of the

inverting amplifier in which an input current is converted into a proportional output
voltage. One of the most common uses of the current-to-voltage converter is in
digital-to-analog circuits (DACs) and in sensing current through photodetcctors
such as photocells, photodiodes, and photovoltaic cells. Photosensitive devices
produce a current that is proportional to an incident radiant energy or light and
therefore can be used to detect the light.
7-10.1 DAC Using Current-to-Voltage Converter
Figure 8-20 shows a combination of a DAC and current-to-voltage converter. The

eight-digit binary signal is the input to the MC1408 DAC and V is the corresponding 0
analog output of the current-to-voltage converter. The output of the MC1408 is

current / the value of which depends on the logic state (0 ro I) of the binary inputs
0,
as indicated by the following equation:
I O
= v,.r(D1
R, 2
+ D64 ...i.
.
Ds
8
+ D,
16
+ 32
D3 + D2
64• T
I Di
128
+ 256
Do) (7-22a)
where / = output current of the DAC (mA)

0
R 1 = resistance (kQ)
V,.r = reference voltage (volts)
D0 through D1 = .eight binary inputs
This means that 1 is zero when all the inputs are logic "O" and 1 is maximum when
0 0
all the inputs are 'logic "I." Thus the value of 1 is a function of the state of eight
0
binary inputs. The variations in 10 can be converted into a desired output voltage
range by selecting a proper value for RF since
(7-22b)
where /0 is given by Equation (7-22a). It is common to parallel RF with a capacitance
C to minimize overshoot and ringing. Note that in Figure 7-20 the output voltage
V of the current-to-voltage converter is positive because the direction of input
0
current / is opposite to that in Figure 4-12.

0
Example 7-13
In the circuit of Figure 7-20, V,.r = 2 V, R1 = 1 kQ, and RF = 2.7 kQ. Assuming
that the op-amp is initially nulled, determine the range for the output voltage V 0'.
Solution.· When all the binary inputs D0 through D7 are logic 0, the current 10 = O;
therefore, the minimum value of V = 0 Y. However, 0 when all the inputs are logic 1,
the / [using Equation (7-22a)] is
0
2 ( I , I
11
I
lo= 1 kQ 2 T 4 + 8 +J6 + 32 +
1 1 l
64 + 128
t)
+ 256
= 1.992 mA
Hence fhe maximum value of output voltage is
V0 = i.s, = (1.992 mA)(2.7 k.Q) = 5.38 Y
Thus the output voltage range is O to 5.38 V.

+5 V
IMSBD7 06
5
6
13
14 t----<l--'VVV\,-----'">
.·1 kit
I
v ,.,
2V
05 7 15
8-digit
04 8 MC1408 ·
binary
input 03 9 DACI
02 10
I
LSB
Dl
DO
11
12
16 3 2
4
--
I0
+15 v
15 pF
-15 V
Offset null
circuit
10 kn
10 = V ,., ( 07 + 06 + 05 + 04 + 03 + 02 + 01 + _QQ)
A1 2 4 a 16 32 64 128 256
Figure 7-20 DAC using current-to-voltage converter.
7-10.2 DetectingCurrent through Photosensitive Devices
Photocells, photodiodes, and photovoltaic cells give an output current that depends
on the intensity of an incident radiant energy or light and is independent of the load.
The current through these devices can be converted to voltage by using an I-to-V
converter and can be used as a measure of the amount of light or radiant energy
incident in the device.
Figure 7-21 shows a photocell, the CL5Q5L, connected to the 1-to-V converter.
Note that since the photocell is a passive transducer, it requires an external voltage
Vdc- The Clairex CLSOSL photocell has the following specifications:
. .
Resistance when illuminated (at 0.61 lux) = 1.5 kn
Minimum dark resistance= 100 kn
Measurement voltage= 10 V
Temperature range= -50° to 75°C
Example 7-14 ·
In the circuit of Figure 7-21, Vdc = 5 V and Rp = 3 kn .. Determine the change in the
output voltage if the photocell is exposed to a light of 0.61 lux from a dark condition.
Assume that the op-amp is initially nulled.
Sec. 7-.10 Current-to-Volcage Converter 265 .

C 75 pF
v: -r sv
+15 V
v:
where 10 = R
. T
Offset null
circuit
10 kn
Figure 7-21 /-to- V converter used to measure the current through the photo-
cell.
Solution. The resistance RT of the CL505L in darkness is ioo.m. The minimum out-
put voltage in darkness is
Vom10 = -~~Rp = -100\0(3k!l) = -0.15V

When the CL505L is illuminated, its resistance RT = 1.5 k!l. Therefore, the maximum
output voltage is
Vomax = - ~; s, = -1.5\0(3 k!l) = -10 V
Thus V0 varies from -0.15 V to -10 V as the photocell is exposed to light from a
dark condition. The capacitor C is used to reduce high-frequency noise.
The circuit in Figure 7-21 can be used as a light-intensity meter by connecting

at the output a meter that is calibrated for light intensity. The de voltage Vdc in
Figure 7-21 can be eliminated if a ph6tovoltaic cell is used instead of a photocell.
The photovoltaic cell is a semiconductor jucntion device that converts radiation
energy into electrical power. It is a self-generating transducer because it does not
require external voltage. The most common example of a photovoltaic cell is the
soler cell used in space applications and watches.
The lower limit on current measurement with an 1-to-V converter is set by
the bias current 18 of the op-amp. This means that op-amps with smaller /8, values
such as the µA 714 (/8 = 3 nA), can be used to detect lower currents.
1-11 VERY HIGH INPUT IMPEDANCE CIRCUIT
Recall that the voltage follower has the highest input resistance of any op-amp cir-
cuit [see section (4-3.8)). For this reason it is used to reduce voltage error caused by
source loading and to isolate high-impedance sources from following circuity. Figure

7-22(a) shows a direct-coupled de voltage follower in which the input voltage is
directly applieu to the noninverting input terminal. Bias current Is for the op-amp
is supplied through the input source resistances R1.-
I
r, = Is >-----o Vo = Vin
II
(al
(bl
Figure 7-22 (a) De-coupled voltage follower. (b) Ac-coupled voltage follower
with input resistance bootstrapped.
If the input source resistance is high (or if the voltage follower is driven from
high-input source resistance) because of the voltage drop across it, the voltage at
the noninverting input will be in error.' In other words, the output and input voltages
will ·.not be eqaul, To remedy this problem an op-amp with low input bias current
should be chosen as a voltage follower when working from high-input source resis-
tances. Obviously, the best choices are op-amps specially designed as buffers or
'voltage followers. These op-amps have low bias currents and generally higher slew
rates. For example, the LM310 has Is= 10 nA maximum and SR= 30 V/µs.
When an ac input voltage rides on a de level, in order to block the de level a
coupling capacitor must be used in series with the input, as shown in Figure 7-22(b).
But whenever a voltage follower is ac-coupled, it is necessary to connect a bias
resistor to provide a ground path for l»- However, this bias resistor drastically reduces
the input resistance of the follower circuit. In fact, the input resistance is equal to
the bias resistance. Therefore, to get higher input resistance the bias resistance is
bootstrapped as shown in Figure 7-22(b). In this circuit the input is applied through
a coupling capacitor C1 to the top of R1, and simultaneously the output voltage is
coupled through capacitor C2 to the bottom of R1• Since the gain of the circuit is 1,.
the voltage drop across R1 is (vio - v0), which is almost zero. Therefore, the current
through R1 is almost zero, and the input resistance, in turn, is incredibly high.
Voltage followers are useful in such applications as active filters, sarnple-and-
hold circuits, and bridge circuits using transducers.
Sec. 7-11 Very High Input ImpedanceCircuit 267

7-12- THE INTEGRATOR
A circuit in which the output voltage waveform is the integral of the input voltage
waveform is the integrator or the integration amplifier. Such a circuit is obtained by
using a basic inverting amplifier configuration if the feedback resistor RP is replaced
by a capacitor CP [see Figure 7-23(a)].
R,
-i~
V1
>---+---o V0 = - --1
R1 CF
J'
O
v,n dt
(a)
1 V
OV ---+---+------~ t (s)
-1 V
0.5 1.5 2
T 3T
2 T 2 2T
--1 v
w
-1 v
w
(b) (c)
Figure 7-13 (a) The integrator circuit. (b, c) Input and ideal output waveforms
using sine wave and square wave, respectively. R1 Cp = 1 second and V00 = 0 Y
assumed.

The expressionfor the output voltage va can be obtained by writing Kirchhoff's
current equation at node v2: · ·
t, = IB + ip
:~ince IB is negligibly small,
Ii
. I
Recall that the relationship between current through and voltage across the capacitor
~ I
.i l
. -- cdvc
-
c dt
' j
Therefore,
I i·.0·- V2 C ( d)( )
I R1 = p dt V2 - Va
However, ·il1 = v2 ~ 0 because A is very large. Therefore,
V111 = Cp .!}_(-v )
R1 dt a
The · )utput voltage can be obtained by integrating both sides with respect to time:
Li; L c, ftdt = (-va) dt
•' = Cp(-va) + Val,~o

Therefore,
Va = - R 1C
1 P
J'
O
V111 dt (7-23)
Equation (7-23) says that the output voltage is directly proporational to the negative
integral of the input voltage and inversely proporational to the time constant R1 Cp.
For example, if the input is a sine wave, the output will be a cosine wave; or if the
input is a square wave, the output will be a triangular wave, as shown in Figure 7-23(b)
and (c), respectively. Note that these waveforms are drawn with the assumption that
R1 C; = 1 second and Vaa = 0 V.
For accurate integration of the input waveform, the time period of the input
signal T must be longer than or equal to R1 Cp. Again, the RoM is used to minimize
the effect of input bias current on the output offset voltage. The input offset voltage
Via and the part of the input current charging capacitor CF produce the error voltage
at the output of the integrator. Therefore, in the practical integrator shown in Figure
7-24, a resistor iRP is connected across the feedback capacitor CF to provide de
stabilization. In bther words, RP limits the Iow-frequency gain and hence minimizes
the variations injthe output voltage. Generally, RP~ 10R1• The integrator is most
commonly used fn analog computers and .analog-to-digital (ADC) and signal-wave-
shaping circuits. I
I
i 269
Sec. 7-12 The Integrator
-.-.- ---·--·-- ---~-
......... '::_·"':
~-----ovo·= --C 1
A1 F
ft
o
Vin dt
Figure 7-24 .Practical integrator.
Example 7-15
In the circuit of Figure 7-23, R1 Cp = ls, and the input is a step (de}' voltage, as shown
in Figure 7-25(a). Determine the output voltage and sketch it. Assunze that the op-amp
is initially nulled.
2V
ov t (s)
2 3 4
(a)
Vo
ov t (s)
-2.
-4
-6
Figure 7-25 (a) Input and (b) output

(bl waveforms for Example 7-15.
I
Solution. The input function is constant beginning at t = O seconds. That is, Vi... =
2 V for O ~ t ~ 4. Therefore, using Equation (7-23),
t-4
V0 = -
f 2 dt
=
=
-[t
-(2
0
2 dt r
+ 2 dt +
+ 2 + 2 + 2) == -8
s:
V
2 dt + s: J 2 dt
270 General Linear Applications

\;..
· ... '.
~-.·:
-------·-·--------·---
Active Filters and Oscillators
----·-·-·" __ __
_,,_,._,......- ..-··---·-··---··--··· ..-·- ..· -....,: _ .....- ..... , ,,_,,,,,,, ,, ,, ,_
8-1 INTRODUCTION
In Chapter 7 you saw how op-amp circuits are used to provide ac/dc amplification,
perform such mathematical operations as summing, averaging, differentiation, and
integration, convert l-to-V and V-to-1 signals, and provide very high input imped-
ance. This chapter presents another important field of application using op-amps:
filters and oscillators. The chapter begins with the analysis and design of basic and
inexpensive filter types and then discusses the various oscillator circuits. At the end
of the chapter, a voltage-controlled oscillator (VCO).,using the NE/SE566 integrated
circuit is presented.
8-2 ACTIVE FILTERS
An electric filter is often a frequency-selective circuit that passes a specified band of

frequencies and blocks or attenuates signals of frequencies outside this band. Filters
may be classified in a number of ways:
J. Analog 'or digital

2. Passive or active
3. Audio (AF) or radio frequencv (RF)
Analog filters are designed to process analog Signals, while digital filters process
analog signals using digital techniques. Depending on the type of elements used in
their construction, filters may be classified as passive or active. Elements used in
283
passive filters are resistors, capacitors, and inductors. Active filters, on the other hand,
employ transistors or op-amps in addition to the resistors and capacitors. The type
of element used dictates the operating frequency range of the filter. For example, RC
filters are commonly used for audio or low-frequency operation, whereas LC or crystal
filters are employed at RF or high frequencies. Especially because of their .high Q
value (figure of merit), the crystals provide more stable operation at higher frequencies.
First, this chapter presents the analysis and design of analog active-RC (audio-
frequency) filters using op-amps. In the audio frequencies, inductors are ofteh not
used because they are very large, costly, and may dissipate more power. Inductors
also eminate magnetic fields.
An active filter offers the following advantages over a passive filter:
1. Gain and frequency adjustment flexibility. Since the op-amp is capable of provid-
ing a gain, the input signal is not attenuated as it is in a passive filter. Besides
that, the active filter is easier to tune or adjust.
2. No loading problem. Because of the high input resistance and low output resis-
tance of the op-amp, the active filter does not cause loading of the source or load.
3. Cost. Typically, active filters are more economical than passive filters. This is
because of the variety of cheaper op-amps and the absence of inductors.
Although active filters are most extensively used in the field of communications
and signal processing, they are employed in one form or another in almost all sophis-
ticated electronic systems. Radio, television, telephone, radar, space satellites, and bio-
medical equipment are but a few systems that employ active filters.
The most commonly _used filters are these:
1. Low-pass filter
2. High-pass filter
3. Band-pass filter
4. Band-reject filter
5. All-pass filter
Each of these filters uses an op-amp as the active element and resistors and
capacitors as the passive elements. Although the 741 type op-amp works satisfactorily
in these filter circuits, high-speed op-amps such as the LM318 or the ICL8017 improve
the filter's performance through their increased slew rate and higher unity gain band-
width.
Figure 8-1 shows the frequency response characteristics of the five types of
filters. The ideal response is shown by dashed curves, while the solid lines indicate the
practical filter response. A low-pass foter has a constant gain from O Hz to a high
cutoff frequencyf H· Therefore, the bandwidth is also fe, AtfH the gain is down by 3 dB;
after that(!> JH) it decreases with the increase in input frequency. The frequencies
between O Hz and f H are known as the passband frequencies,. whereas the range of
frequencies, those beyond fe, that are attenuated includes the stopband frequencies.
Figure 8-l(a) shows the frequency response of the low-pass filter. As indicated
by the dashed line, an ideal filter has a zero loss in its passband and infinite loss in
284 Active Filters and Oscillators Chap. 8

The output voltage waveform is drawn in Figure 7-25(b); the waveform is called a
ramp function. The slope of the ramp is - 2 volts/sec. Thus, with a constant voltage
applied at the input the integrator gives a ramp at the output.
1-13 THE DIFFERENTIATOR

Figure 7-26(a) shows the differentiator or differentiation amplifier. As its name
implies, the circuit performs the mathematical operation of differentiation; that is,
the output waveform is the derivative pf the input waveform. The differentiator may
be constructed from a basic inverting amplifier if an input resistor R1 is replaced by
a capacitor C1.
The expression for the output voltage can be obtained from Kirchhoff's cur-
rent equation written at node v,. as follows:
ic = 18 + i,
(al
100
80
Closed-loop response of basic
differentiater: 20 dB/decade
ai 60
~
c:
·;;
(!) 40 Closed-loop response of
practical differentiator:
-20 dB/decade
20
,... ,,,, "

.
,"
, . ~I
I
-20
1.0 f 102 f ,er t 10'4 f r, 1()5 f
Relative frequency ( Hz)
(bl
Figure 7-26 Basic differentiator. (a) Circuit. (b) Frequency response.
Sec. 7-13 The Differentiator 271

Since IB ~ 0,
C d( ) _ V:i. - V0
I dt Via - V:i. - RF
But v1 = v2 ~ 0 V, because A is very large. Therefore,
C dV10 __ V0
l dt - RF
or
(7-24)
Thus the output v0 is equal to the RFC1 times the negative instantaneous rate of
change of the input voltage v10 with time. Since the differentiator performs the reverse
of the integrator's function, a cosine-wave input will produce a sine-wave output, or
a triangular input will produce a square-wave output. However, the differentiator of
Figure 7-26(a) will not do this because it has some practical problems. The gain
of the circuit (RF/ Xc1) increases with increase in frequency at a rate of +O dB/decade.
This makes the circuit unstable. Also, the input impedance Xc1 decreases with increase
in frequency, which makes the circuit very susceptible to high-frequency noise. When
amplified, this noise can completely override the differentiated out put signal. The
frequency response of the basic differentiator is shown in Figure '1-26(b). In this
figure, J;, is the frequency at which the gain is O dB and is given by '
1
la = 2nRFC1 (7-25)
Also, f. is the unity gain bandwidth of the op-amp, and J is some relative operating
frequency.
Both the stability and the high-frequency noise problems can be corrected by
the addition of two components: R1 and CF, as shown in Figure 7-27(a). This circuit
is a practical differentiator, the frequency response of which is shown in Figure 7-26(b)
by a dashed line. From frequency J to fb, the gain increases at 20 dB/decade. How-
ever, after fb the gain decreases at 20 dB/decade. This 40-dB/decade change in gain
is caused by the R1 C1 and RFCi, combinations. The gain-limiting frequency fb is
given by
1
I, = 2nR1C1 (7-26)
where R1 C1 = RFCF. Thus R1 C1 and RFCF help to reduce significantly the effect of
high-frequency input, amplifier noise, and offsets. Above all, it makes the circuit
more stable by preventing the increase in gain with frequency. Generally, the value
of I, and in turn R1 C1 and RFCF values should be selected such that
, 1: <fb <!c (7-27)
where
fb = I = -=-----I~
2nR1C1 2nRFCF
J. = unity gain bandwidth

0.005 µF
C1 RF
0.1 µF 1.5 kn
dv;n
'>------o Vo= -RFC1 -
dt
if RFC1 > R,c,or RFCF
(a)
7V
!) V P----+-------4.---.....--~
4,r
t (ms)
-1V
(b) (cl
Figure 7-27 Practical differentiator. (a) Circuit. (b) Sine-wave input and result-
ing cosine-wave output. (c) Square-wave input and resulting spike output.
The input signal will be differentiated properly if the time period T of the input
signal is larger than or equal to RpC1• That is,
T>RFCl
Figure 7-27(b) and (c) show the sine-wave and square-wave inputs and resulting
Sec. 7-13 The Differentiator 273

differentiated outputs, respectively, for the practical differentiator. A workable
differentiator can be designed by implementing the following steps (see Example 7-16):
1. Select f.. equal to the highest frequency of the input signal to be differentiated.
Then, assuming a value of C1 < 1 µF, calculate the value of Rp.
2. Choose!,,= 20f.. and calculate the values of R1 and C, so that R1C1 = RpCp.
The differentiator is most commonly used in waveshaping circuits to detect

high-frequency components In an input signal and also as a rate-of-change detector
in FM modulators.
Example 7-16
(a) Design a differentiator to differentiate an input signal that varies in frequency
from 10 Hz to about 1 kHz.'
(b) If a sine wave of 1 V peak at 1000 Hz is applied to the differentiator of part (a),
draw its output waveform.
Solution
(a) To design a differentiator we simply follow the steps outlined above:
1./o=lkHz
1 [from Equation (7-25)]
2nRpC1
Let C1 = 0:1 µF; then
1
Rp = (21t)(IOl)(lO-') = 1.59k!l
Let s, be 1.5 k!l.
2. lb = 20 kHz
1 [from Equation (7-26)]
1
R1 = (21t)(i)(I04)(IO ') = 79.5 n
Let R1 be 82 n,
Since R1 C1 = RpCp,
= (82)(10-') ,...., 0 0055 µF
Cp
1.5k{l = .
Let c, be 0.005 µF
Finally, RoM = R1 IIRp ~ 78 0 (use 82 il).
The complete circuit with component values is shown in Figure 7-27(a).
(b) Since V" = 1 V and f = 1000 Hz, the input voltage is
vm = V" sin rot
= sin (211:)(IOl)t
Hence, from Equation (7-24), 1
dvin
Vo= - RC
p l dt
1,
= -(1.5 k0)(0.1 µF) [sin (2n)(l03)t]
= -(1.5 k0)(0.1 µF)(21t)(IOl) cos [(21t)(lOl)t]
= -0.94 cos [(21t)(103)t]
The input and differentiated output waveforms are as shown in Figure 7-l7(b).
274 General Linear Applications ' Chap. 7

SUMMARY
1. So many different op-amps are available because no one circuit design can possibly
optimize all the de and ac parameters. To select the most suitable device for a desired
application, it is therefore necessary to refer to the op-amp data book.
2. Op-srnps are designed to optimize a parameter such as high slew rate, wide bandwidth,
or low power consumption. However, the use of a general-purpose op-amp such as the
741 will give satisfactory results in most applications.
3. Altiiough a direct-coupled op-amp can amplify both ac and de inputs, a capacitive
coupling is used when ac response characteristics are needed or when it is essential to
block the de associated with the inpu't signal. An ac amplifier can be powered by a single
supply, provided that a de level is injected at the input and removed at the output by
using a voltage divider and coupling capacitor, respectively. Besides that, the output
voltage swing is limited to a single supply voltage.
4. A peaking or narrow bandpass response can be obtained by using a parallel LC circuit
in the feedback path of an inverting amplifier.
5. Summing, scaling, and averaging amplifiers can be constructed by using inverting,
noninverting, and differential configurations.
6. The instrumentation amplifier is intended for precise, low-level signal amplification where
low noise, low thermal and time drifts, and high input resistance are required. Various
r'ifferential amplifier configurations can be used as instrumentation amplifiers, depending
on the application requirements. When employed in conjunction with the transducer
bridge and indicating meter, the instrumentation amplifier can be used for a variety of
applications, such as temperature and light indicators, temperature controller, and analog
weight scale.
7. The differential input and output amplifier can be used as a preamplifier and also in
driving push-pull arrangements.
8. The V-to-J converter can be used in such applications as de and ac voltmeters, diode,
zener, and LED testers.
9. The 1-to-V converter, on the other hand, is used with digital-to-analog circuits as well as
in testing photosensitive devices.
10. Using a bootstrap technique, the input impedance of an ac ·voltage follower can .be
increased significantly.
11. The integrator and differentiator are most commonly used in signal wave-shaping
applications. In addition, the integrator is used in analog computers and the differentiator
is used as a rate-of-change detector in FM modulators. ·
QUESTIONS
7-1. Briefly explain the difference between the de and ac amplifiers.

7-2. What is the major advantage and disadvantage of a single-supply ac amplifier?
7-3. What determines the peak frequency fp in the peaking amplifier?
7-4. Explain the difference between (a) inverting and differential summing amplifiers and
(b) inverting and noninverting averaging amplifiers.
7-5. What is an instrumentation amplifier? List three applications of the instrumentation
amplifier besides those discussed in this chapter.

7-6. Explain briefly the characteristics of a thermistor, photocell, and strain gage.
7-7. What is the major difference between the photocell and the photovoltaic cell?
7-8. Explain briefly the advantages of the differential input and output amplifier.
7-9. What modifications are needed in the de voltmeter circuit of Figure 7-16 so that it may
be used to measure higher de voltages (> ± 13 V)?
7-10. The maximum ideal value of current /0 in the circuit of Figure 7-lh is equal to the out-
put short circuit current of the op-amp. True or false?
7-11. ls there any limitation on the size of the load in the V-to-I converter with grounded
load of Figure 7-19? Explain.
7-12. If a 741 C is configured as an I-to-V converter, what is the lowest value of current that
may be measured?
7-13. Explain the difference between the de and ac voltage followers.
7-14. Explain the difference between the integrator and differentiator and give one applica-
tion of each.
PROBLEMS
(In all of the following problems, assume that the op-amp is 'initially nulled and the supply
voltages = ± 15 V unless otherwise specified.)
7-1. In the circuit of Figure 7-l(a), RF = 4.7 kQ, R1 = 100 n, RL = 10 k.Q, and RoM =
100 n. Determine the output voltage V if Vin = 100 mV.
0
7-2. Repeat Problem 7-1 for the circuit in Figure 7-l(b).

7-3. For the noninverting amplifier of Figure 7-3(b), Rin = 50 n, Ci = O.Ql µF, R1 = 1 kQ,
RoM = 820 n, Rp = 5.6 kQ, RL = 10 kQ. Determine:
(a) The gain
(b) The bandwidth of the amplifier.
7-4. For the inverting amplifier with a single supply shown in Figure 7-4(a), R1n = 50 n,
R1 = 10 kil, R2 = R3 = Rp = 100 kil, C, = C = 0.1 µF.
0
(a) Determine the bandwidth of the amplifier.

(b) Determine the maximum ideal output voltage swing.
(c) Sketch the output voltage waveform v~ and v0 if v1n = 200 mVP sinewave at
1 KHz.
7~5. The peaking amplifier of Figure 7-5(a) has the following values: R1 = 1 kil, L =
100 µH with 3 n internal resistance, C = 0.01 µF, RF= 6.8 kil, RoM = 820 n, and
RL = 10 kil. Determine:
(a) The peak frequency fp,
(b) The gain of the amplifier at fp,
(c) The bandwidth of the amplifier
7-6. In the circuit of Figure 7-6, Va= 100 mY, Vb= -200 mY, Ve= 300 mV, Ra= 3 kil,
Rb= 2.2 kil, Re= 1 kil, Rp = 4.7 kQ, RoM = 470 n, and RL = 10 kil.
(a) Determine the output voltage V 0•
(b) Identify the circuit from its operation.

7-7. Repeat Problem 7-6 with Ra = Rb = Re = 1 kil.
7-8. The circuit of Figure 7-7 is to be used as an averaging amplifier with the following
specifications: V = Vi= 1.5 Y, Ve= 3 V, R1 = R = 1.5 kil, and V = 5.2 V.
0 0
Determine the required value of Rp.

.....
'
7-9. In the circuit of Figure 7-9, Va= 1 V, Vi= 2 V, Ve= -3 V, and Va= -4 V;
R = 1 kn, RL = 10 k!l. Determine the output voltage V0•
7-10. In the circuit of Figure 7-12, R1 = 1.8 kn, RF = 4.7 kn, RA = RB = Re = 500 kn,
Vic = 10 V, and supply voltages = ±15 V. The transducer is a thermistor with the
following specifications. Rr = 500 kn at 25°C. The temperature coefficient of resis-
tance = ~ 10 knj°C. If the temperature changes from 0°C to 70°C, find the variations
in (a) the input signal Vab and (b) the output signal V 0•
7-11. The transducer in the circuit of Figure 7-12 is a CL605L photocell with the following
specifications: minimum dark resistance = 500 kn; resistance at 0.61 meter-candle
(lux) = 7.5 kn. Using the circuit specifications of Problem 7-10, determine the input
voltage Vab and output voltage V0 (a) at a dark condition and (b) at 0.61 lux.
7-12. For the strain gage bridge circuit shown in Figure 7-13, show that
Vob = + Vdc( ~/)

Assume that under the strained condition the resistance of RT! and RT3 decreases and
that of Rn and Rr4 increases by the same amount tiR n. Also, Rr1 = Rn = Rr3 =
Rr4 = R under the unstrained condition.
7-13. The circuit of Figure 7-12 uses a strain gage and has the following specifications. The
unstrained resistance of each of the four. elements of the strain gage is 120 n, Vac =
5 V, and the op-amp supply voltages = ± 10 V. R1 = 100 n and RF = 47 kn. Deter-
mine the output voltage V0 if the change in the resistance of each strain gage element
is 0.1 n.
7-14. In the differential amplifier of Figure 7-14(a), the desired output. voltage V0 = 5 V.
Determine the required value of differential input voltage Vin if R1 = 100 Q and RF=
22 kn. The op-amp supply voltages= ±10 V.
7-lS. In the circuit of Figure 7-16, Vin = 2 V and the switch is in ·position 1. Determine the
current through the meter.
7-16. A 100-µA full-scale meter movement is used in the ac voltmeter of Figure 7-17. Deter-
mine the full-scale input voltage v1;, if R1 = 4.7 kQ.
7-17. In the circuit of Figure 7-18, if R1 = 1.5 k!l and Vin= 5 V, determine (a) the current
through the diode and (b) the output voltage V 0•
7-18. Repeat Problem 7-17 if a diode is replaced by a zener with V = 5.1 V and J&k = 1 mA.
1
7-19. Determine the load current Is: in the circuit of Figure 7-19 ifR = 10 k!l and Vi.n = 2 V.
For the proper operation 'of this circuit the value of the load has to be less than R
Why?
7-20. Referring to the circuit of Figure 7-20, determine the output voltage V0 if D0 through
D3 are connected to ground and D4 through D, are connected to +5 V (logic 1.)
7-21. In the circuit of Figure 7-21, Vdc = 10 V, the dark resistance of the CL505L is 100 k!l,
and Rp = 10 kn. Determine the output voltage for the dark condition. What is the
function of capacitor C?
7-22. In the integrator circuit of Figure 7-24, the input is a sine wave with a peak-to-peak
amplitude of 5 Vat 1 kHz. Draw the output voltage waveform if R1 Cp = 0.1 ms and
RF = 10R1• Assume that the voltage across Cp is initially zero.
7-23. In the differentiator circuit of Figure 7-27(a), the input is a sine wave with a peak-
to-peak amplitude of 3 V at 200 Hz. Sketch the output voltage waveform.
7-24. Design a differentiator that will differentiate an input signal with /max = 100 Hz.

EXPERIMENT 7-1
AC INVERTING AMPLIFIER
Objectives
In this experiment you will study the characteristics of an ac amplifier and an amplifier
that uses a single power supply. At the end of this experiment you should be able to:
1. Verify that the low-cutoff frequency depends on the value of the input capacitor-
resistor combination and the high-cutoff frequency depends on the gain of the
amplifier.
2. Select the proper values of external components for a desired bandwidth.
3. Discuss the differences between an ac amplifier with two supply voltages and
one with a single supply voltage.
Equipment
1. Oscilloscope
2. Audio-signal generator
Materials
1. 741 or 351 op-amp

2. Three IO-kn resistors
4. 470-kn resistor
5. 0.01-µF capacitor
7. Semilog paper
Procedure
l. Connect the circuit as shown in Figure E7-l.l(a).

2. Set vm = 100 mV pp at 100 Hz sine wave. Using the scope, measure the input
and output voltages and enter the results in Table E7-1.1.
3. Repeat step 2 for the frequencies listed in Table E7-l.l.
4. Next, connect the circuit of Figure E7-l.I(b) and repeat steps 2 and 3.
5. Complete Table E7-l. l.
6. Using the data of Table E7-I.1, plot the frequency versus gain in dB curves for
the inverting amplifier with dual and single supply on the semilog graph paper.
Use the log scale for frequency and linear scale for gain.
7. From the graphs first find the low-cutoff and high-cutoff frequencies and then
determine the bandwidths.
8. Calculate the theoretical bandwidths for the amplifiers shown in Figure E7-I.I.

(al
C1 R1 RF
0.01 µF 470kn
+15V Vo
R2 roo en
RL
10kn
R3 1ookn
(b)
Figure E7-1.1 Ac inverting amplifier with (a) dual supply and (b) single supply.
(Pin numbers refer to the 8-pin mini DIP.)
TABLE E7-1.1
Output voltage, v0, of Voltage gain (dB)

an ac inverting Voltage = 20 log (110/t11n)
amplifier with: gain,
Input voltage, Input frequency, ~ Dual Single
tlh, pp Ii.. (Hz) Dual supply Single supply tlJn supply supply
100
1,000
1,300
4,000
lOOmV 7,000
10,000
13,000
20,000
50,000
100,000
Questions
1. How do the calculated bandwidths compare with the measured bandwidths?

If the difference is more than 20 %, give the reasons.
2. In Figure E7-1.l(a), if C, is change to 0.1 µF, what would the new low-cutoff
frequency be?
3. What determines the high-cutoff frequency of an amplifier?
4. For a high-cutoff frequency of 50 kHz, what should be the gain of an amplifier?
5. What are the advantages and disadvantages of a single-supply amplifier?
EXPERIMENT 7-2
AN INTEGRATOR
Objectives
In this experiment you will learn what integration is and how the integrator works.
At the end of this experiment you should be able to:
1. Determine the integral of certain waveforms.

2. Select the components for proper integration.
3. Learn how to use the dual-trace scope to measure the phase shift between input
and output waveforms.
Equipment
2. Audio-function generator
Materials
1. 351 op-amp
2. Two IO-kn resistors
3. 100-kn resistor
Procedure
1. Connect the circuit as shown in Figure E7-2.1. (The pin numbers indicated
in this figure refer to the 8-pin mini DIP).
2. Set the function generator for a square-wave output and adjust its amplitude
to 1 V pp. Set the frequency of the square wave at 1 kHz initially.

100 kn
10 k!l 0.01 µF
+
~-
RoM
10 k!l
Figure E7-2.1 Integrator. (Pin

numbers refer to the 8-pin mini DIP.)
3. Connect one channel of the scope at the input and the other at the output
terminal of the op-amp and slowly adjust the input frequency until the output
is as good (linear) a triangle wave as possible. Measure the amplitude and
frequency of the input and output waveforms. Enter the measured values in
Table E7-2.l.
4. Repeat step 3 for C, = 0.05 µF and 0.1 µF.
5. Set the function generator for a sine-wave output. Adjust the amplitude of the
sinewave to 1 V pp and set the frequency at 1 kHz initially. Remove the 0.1-µF
capacitor and reconnect the 0.01-µF capacitor in its place.
6. Connect one channel of the scope at the input and the other at the output
terminal of the op-amp. Adjust the frequency of the input until the output is
a negative-going cosine wave. Make sure that the scope is triggered properly.
Measure the frequency and amplitude of the input and output waveforms.
Enter the measured values in Table E7-2. l.
TABLE E7-2.1
Input waveform Output waveform

R1 Cp
(kn) (µF) Type Amplitude Frequency Type Amplitude Frequency
10 0.01 Square 1 V pp
Square 1 V pp
10 0.05
Square 1 V pp
-
10 0.1
10 0.01 Sine 1 V pp
Questions
1. For proper integration, what must be the relationship between R1 Cp and input
frequency?
Exp. 7-2 An Integrator 281

2. What characteristic is common to both the integrator and amplifier?
· 3. From the results of Table E?-2.1, discuss the relationship between the amplitude
of the triangle wave and the amplitude and frequency of the square wave.
4. When the input of an integrator is a sine wave, what is the phase shift between
the input and output?
5. What parameter must be considered in selecting an op-amp for integrator
application?
6. If the input to an integrator is a pulse waveform (20 % duty cycle), what is its
output waveform?
7. In the integrator of Figure £7-2. l, what is the function of RP?

Ideal Ideal
response reponse
I
I
Pass- --,~...--- ~Pass--
band I : band
......_ ,__Stop band Frequency Stop band I
----------------.- Frequency
fH fl
(al (b)
Gain, 12
Vin
Ideal
L Ideal
response
r----..::- -, r--::.-...---
1
0.707 0.707 Pass-
band-
...._.,_.-----~------ Frequency ......_ .__--"'.__--'------1-- Frequency

fl fc fH fl fc fH
(c) (d)
Voltage
v,n
-1
(e)
Figure 8-1 Frequency response of the major active filters, (a) Low-pass. (b) High-pass. (c)
Band-pass. (d) Band-reject. (e) Phase shift between input and output voltages of an all-pass
filter.
its stopband. Unfortunately, ideal filter response is not practical because linear
networks cannot produce the discontinuities. However, it is possible to obtain a
practical response that approximates the ideal response by using special design
techniques as well as precision component values and high-speed op-amps.
Sec.8-2 Active Filters 285

Butterworth, Chebyshev, and Cauer filters are some of the most commonly used
practical filters that approximate the ideal response. The key characteristic of the
Butterworth filter is that it has a flat passband as well as stopband. For this reason,
it is sometimes called e fiat-fiat filter. The Chebyshev filter has a ripple passband and
flat stopband, while the Cauer filter has a ripple passband and a ripple stopband.
Generally, the Cauer filter gives the best stopband response among the three. Because
of their simplicity of design, the low-pass and high-pass Butterworth filters are dis-
cussed here.
Figure 8-1 (b) shows a high-pass filter with a stopband O < f < JL and a passband
f > fL· JL is the low cutoff frequency, and f is the operating frequency. A band-pass
filter has a passband between two cutoff frequencies jj, and/L, where jj, > JL, and two
stopbands: 0 < f < JL and f > /8. The bandwidth of the band-pass filter, therefore,
is equal to (/8 - !L). The band-reject filter performs exactly opposite to the band-pass;
that is, it has a bandstop between two cutoff frequencies f" and fL and two pass bands:
0 < f < JL and f > f 8. The band-reject is also called a band-stop or band-elimination
filter. The frequency response of band-pass and band-reject filters is shown in Figure
8-l(c) and (d). In these figures.Jc is called the center frequency since it is approximately
at the center of the passband or stopband.
Figure 8-l(e) shows the phase shift between input and output voltages of an
all-pass filter. This filter passes all frequencies equally well; that is, output and input
voltages are equal in amplitude for all frequencies, with the phase shift between the
two a function of frequency. The highest frequency up to which the input and output
amplitudes remain equal is dependent on the unity gain bandwidth of the op-amp.
At this frequency, however, the phase shift between the input and output is maximum.
Before proceeding with specific filter types, let us reexamine the filter character-
istics, especially in the stopband region. As shown in Figure 8-l(a)-(d), the actual
response curves of the filters in the stopband eithervsteadily dec!Sase or increase or
both with increase in frequency. The rate at which the gain of the -filter changes in the
stop band is determined. by the order of the filter. For example, for the first-order
low-pass filter the gain rolls off at the rate of 20 dB/decade in the stopband that is,
for f > f 8; on the other hand, for the second-order low-pass filter the roll-off rate is'
40 dB/decade; and so on. By contrast, for the first-order high-pass filter the gain
increases at the rate of 20 dB/decade in the stop band, that is, unti If= fL; the increase
is 40 dB/decade for the second-order high-pass filter; and so on.
8-3 FIRST-ORDER LOW-PASS BUTTERWORTH FILTER
Figure 8-2 shows a first-order low-pass Butterworth filter that uses an RC network
for filtering. Note that the op-amp is ,used in the noninverting configuration; .hence
it does not load down the RC network. Resistors R1 and RP determine the gain of
the filter.
According to the voltage-divider rule, the voltage at the noninverting terminal
(across capacitor C) is
(8-la)

R,
10kil 10 kil
Voltage gain
+Vee
+15V
-20 dB/decade
I
I I
0.707 AF I
I
.__ Passband.+++-Stop
__._ band+e- _.,_ Frequency
fH
(a) (b)
Figure 8-2 First-order low-pass Butterworth filter. (a) Circuit. (b) Frequency response.
where
j = ,.;=T and -;
.x.c = t
j21tfC
Simplifying Equation (8-la), we get
_ V111
v, - I+ j21tfRC
and the output voltage
That is,
Vo -
- (1 + R,)
R, l + j'atf. RC
V111
or
V0 A; (8-lb)
. V111 = 1 + j(fffn)
where v = gain of the flit.er as a function of frequency
0
V111
A, = I + ~; = passband gain of the filter

f = frequency of the input signal
fn =
2n~C
= high cutoff frequency of the filter
The gain magnitude and phase angle equations of the low-pass filter can be obtained
by converting Equation (8-lb) into its equivalent polar form, as follows:
I I V0
Vin = ,./1
Ap
+ (f/fn)2 (8-2a)
.
¢, = -tan·1 ( 1-)
!H
(8-2b)
where ¢, is the phase angle in degrees.
Sec. 8-3 . First-Order Low-Pass Butterworth Filter 287

The operation of the low-pass filter can be verified from the gain magnitude
Equation (8-2a):
1. At very low frequencies, that is,/ <!H,
2. Atf=JH,
3. At/> IH,
I I= Jt =
V.0
V,n "L,
0.107Ap.
I I<vVo
In
Ar •
Thus the low-pass filter has a constant gain AP from O Hz to the high cutoff frequency
fH· AtJH the gain is 0.707Ap, and after/Hit decreases at a constant rate with an increase
in frequency [see Figure 8-2(b)). That is, when the frequency is increased tenfold (one
decade), the voltage gain is divided by 10. In other words, the gain decreases 20 dB
.(= 20 log 10) each time the frequency is increased by 10. Hence the rate at which the
gain rolls off after fH is 20 dB/decade or 6 dB/octave, where octave signifies a twofold
increase in frequency. The frequency J = JH is called the cutoff frequency because the
gain of the filter at this frequency is down by 3 dB ( = 20 log 0. 707) from O Hz. Other
equivalent terms for cutoff frequency are -3 dB frequency, break frequency, or corner
frequency.
8-3.1 Filter Design
A low-pass filter can be designed by implementing the following steps:
1. Choose a value of high cutoff frequency fH·

2. Select a value of C less than or equal to 1 µF. Mylar or tantalum capacitors
are recommended for active filters.
3. Calculate the value of R using
1
R=--
21tfHC
4. Finally, select values of R1 and RP dependent on the desired passband gain AP
using
8-3.2 Frequency Scaling
The procedure that is used to convert an original cutoff frequency le to a new cutoff
frequency JiI is called frequency scaling. Frequency scaling is accomplished as follows.
To change a high cutoff frequency, multiply R or C but not both by the ratio of the
original cutoff frequency to the new cutoff frequency. In filter design the needed values
of R and C are often not standard. Besides that, a variable capacitor C is not com-

monly used. Therefore, choose a standard value of capacitor, and then calculate the
value of resistor for a desired cutoff frequency. This is because for a nonstandard
value of resistor a potentiometer can be used (see Examples 8-1 and 8-2).
Example 8-1
Design a low-pass filter at a cutoff frequency of 1 kHz with a passband gain of 2.
Solution. Following the design steps described above,
1. fH = 1 kHz.
2. Let C = 0:01 µF.
3. Then R = 1/(27t)(l03)(10-8) = 15.9 kn. (Use a 20-kQ potentiometer.)
4. Since the passband gain is 2, R1 and Rp must be equal. Therefore, let R1 = Rp
= 10 kQ. The complete circuit with component values is shown in Figure 8-2.
Example 8-2
Using the frequency scaling technique, convert the 1-kHz cutoff frequency of the low-
pass filter of Example 8-1 to a cutoff frequency of 1.6 kHz.
Solution. To change a cutoff frequency from 1 kHz to 1.6 kHz, we· multiply the 15.9-
kQ resistor by
original cutoff frequency = 1 kHz =
0 625
new cutoff frequency 1.6 kHz ·
Therefore, new resistor R = (15.9 kQ)(0.625) = 9.94 kQ. However, 9.94 kQ is not a
standard value. Therefore, use R = 10 kQ potentiometer. Thus the new cutoff fre-
quency is
1
fH = (27t)(0.01 µF)(9.94 Hl)
= 1.6 kHz
Example 8-3
Plot the frequency response of the low-pass filter of Example 8-1.
Solution. To plot the frequency response, we have to use Equation (8-2a). The data
of Table 8-1 are, therefore,obtained by substituting various values for fin this equation.
TABLE 8-1 FREQUENCY RESPONSE DATA FOR EXAMPLE 8-3
Input Gain Magnitude

frequency, f magnitude, (dB)=
(Hz) J Vo/Vin I 20 log I Vo/Vin I
I. 10 2 6.02
2. 100 1.99 5.98
3. 200 1.96 5.85
4. 700 1.64 4.29
5. 1,000 1.41 3.01
6. 3,000 0.63 -3.98
7. 7,000 0.28 -10.97
8. 10,000 0.20 -14.02
9. 30,000 0.07 -23.53
10. 100,000 0.02 -33.98
Sec.8-3 First-Order Low-Pass Butterworth Filter 289

Equation (8-2a) will be repeated here for convenience:
I I = ~1 +
V0
V1n
Ap
(f/fa>2
where tfp = 2 and /8 = I .kHz. The data of Table 8-1 are plotted as shown in Figure
8-3.
+20
+10
co
~ O dB
c:
·.;
Cl
QJ
en -20 dB/decade
s -10
0
>
-20
-30
1-4------Passband-----++-----Stop band,-----~
10 100 . fH = 1 k 10 k 100 k
Frequency(Hz)
Figure 8-3 Frequency response for Example 8-3.
8-4 SECOND-ORDER LOW-PASS BUTTERWORTH FILTER
A stop-band response having a 40-dB/decade roll-off is obtained with the second-order

low-pass filter. A first-order low-pass filter can be converted irito a second-order type
simply by using an additional RC network, as shown in Figure 8-4.
Second-order filters are important because higher-order filters can be designed
using them. The gain of the second-order filter is set by R1 and RP, while the high
cutoff frequency /8 is determined by R2, C2, R3, and C3, as follows:
I l
fH = ---;===-=~= (8-3)
21t,./R2R3C2C3
Furthermore, for a second-order low-pass Butterworth response, the voltage gain
magnitude equation is
(8-4)
290 Active Filters and Oscillators Chap.8

R,
27 kSl 15.8 kSl

Voltage gain
+Vee
+15 V
-40 dB/decade
0.707AF
Ci
0.0047 µF
fH
Frequency
(a) (bl
Figure 8-4 Second-order low-pass Butterworth filter. (a) Circuit. (b) Frequency response.
where AP = 1 + ~: = passband gain of the filter

J= frequency of the input signal (hertz)
/8 = ,.,/ 1 = = high cutoff frequency (hertz)
2n R2R3C2C3
8-4.1 Filter Design
Except for having twice the roll-off rate in the stopband, the frequency response of
the second-order low-pass filter is identical to that of the first-order type. Therefore,
the design steps of the second-order filter are identical to those of the first-order
filter, as shown below:
1. Choose a value for the high cutoff frequency /8•

2. To simplify the design calculations, set R2 = R3 =Rand C2 = C3 = C. Then
choose a value of C < 1 µF.
3. Calculate the value of R using Equation (8-3):
I
R = 2nJHC
4. Finally, because of the equal resistor (R2 = R3) and capacitor (C2 = C3) values,
the passband voltage gain AP = (1 + RP/ R1) of the· second-order low-pass
filter has to be equal to l.586. That is, RF = 0.586R1• This gain is necessary
to guarantee Butterworth response. Hence choose a value of R1 < 100 kQ and
calculate the value of Rp.
As outlined in Section 8-3.2, the frequency scaling method of the first-order

filter is also applicable to the second-order low-pass filter.
Sec. 8-4 Second-Order Low-Pass Butterworth Filter 291

Example 8-4
(a) Design. a second-order low-pass filter at a high cutoff frequency of 1 klli .
. (b) Dtaw the frequency response of the network in part (a).
Solution
(a) To design the second-order low-pass filter, simply follow the steps presented above:
1. fH = 1 kHz.
2. Let C2 = C3 = 0.0047 µF.
3-. Then
l
R2 = R3 = (21t)(l03)(47)(10-IO) = 33.86 lill
(Use R2 = R3 = 33 kn.)
4. Since Rp must be equal to 0.586R1, let R1 equal 27 kQ. Therefore,
RP = (0.586)(27 kQ) = 15.82 lill
(Use Rp = 15.8 lill.) Thus the required components are:
R2 = R3 = 33 kQ
C2 = C3 = 0.0047 µF
R1 = 27 kQ and Rp·= 15.8 kQ
Recall that the first-order low-pass filter at a cutoff frequency of 1 kHz was
designed in Example 8-1. Since the cutoff frequency of the second-order low-pass
filter is also 1 kHz,.we could use the resistor and capacitor values obtained in Example
8-1, That is, R2 = R3 ~ 15.9 kO, and C2 = C3 = 0.01 µF. However, the values of
R1 and Rp must be chosen such that RP = 0.586R1• Therefore, let R1 = 27 lill and
Rp = 15.8 kQ.
(b) The frequency response data shown in Table 8:2 are obtained from the magnitude
TABLE 8-2 FREQUENCY RESPONSE DATA FOR EXAMPLE 8-4.
Frequency, f Gam magnitude, Magnitude (dB)=

(Hz) J Vo/Vin J 20 log J Vo/Vin I
1. 10 1.59 4.01
2. 100 1.59 4.01
3. 200 1.58 4.00
4. 700 1.42 3.07
5. 1,000 1.12 1.00
6. 3,000 0.18 -15.13
7. 7,000 0.03 -29.80
8. 10,000 0.02 -35.99
9. 30,000 , 1.76 x 10-3 -55.08
10. 100,000 1.59 x 10-4 -75.99
Equation (8-4) by substituting various values from 10 Hz to 100 kHz for f. Equation
(8-4) is repeated here for convenience:
292 Active Filters and Oscillators Ch.ap. 8

where Ap = 1.586 and !H = l kHz. The frequency response of the second-order low-
pass filter of Example 8-4 is shown in Figure 8-5.
+10
•-•-----.;;;;;·~}3dB
O dB
-10 \/-40 dB/docad,

ai
\
~ -20
.. ;
"'
0,
QI
0,
!9
0 -30 •
> \
-40
-50
t-ot------- Passband-----~---Stopband
"\ ••
-60
10 100 10 k 100 k
Frequency (Hz)
8-5 FIRST-ORDER HIGH-PASS BUTTERWORTH FILTER
High-pass filters are often formed simply by interchanging frequency determining

resistors and capacitors in low-pass filters. That is, a first-order high-pass filter is
formed from a first-order low-pass type by interchanging components R and C.
Similarly, a second-order high-pass filter is obtained from a second-order low-pass
filter if R and Care interchanged, and so on. Figure 8-6 shows a first-order high-pass
Butterworth filter with a low cutoff frequency offL· This is the frequency at which the
magnitude of the ~fil
is 0.707 times its passband value. Obviously, all frequencies
higher than}~ are l:~
1sband frequencies with the highest frequency determined by the
closed-loop bandwidth of the op-amp.

Note that the high-pass filter of Figure 8-6(a) and the low-pass filter of Figure
8-2(a) are the same circuits, except that the frequency ·determining components (R
and C) are interchanged.
For the first-order high-pass filter of Figure 8-6(a), the output voltage is
RP) j2nfRC
Vo= (1 + R1 1 + j2nfRC Vin
or
(8-5)
Se~.8-5 First-Order High-Pass Butterworth Filter 293
.L - )re- czcen
R, Voltage gain
io xn 10k!l
20 dB/decade
AF ------~----
0.707AF
I
I
I
Stopband-e-e-,.__ Passband -
fL Frequency
(a) (b)
Figure 8-6 (a) First-order high-pass Butterworth filter. (b) Its frequency
response.
where AP = .I + ;:· ·- passband gain of the filter

f = frequency of the input signal
l "·
IL = lnRC = low cutoff frequency
Bence the magnitude of the voltage gain is
(8-6)
Since high-pass filters are formed from low-pass filters simply by interchanging R's
and C's, the design and frequency scaling procedures of the low-pass filters are also
applicable to the high-pass filters (see Sections 8-3.1 and 8-3.2).
Example 8-5
(a) Design a high-pass filter at a cutoff frequency of 1 kHz with a passband gain of 2.
(b) Plot the frequency response of the filter in part (a).
-Solutlon
(a) Use the same values of R and C that were determined for the low-pass filter of
Example 8-1, since IL= IH = 1 kHz. That is, C = O.Dl µF and R = 15.9 kn. Simi-
larly, use R1 = R, = 10 kn, since A, = 2.
(b) The data for the frequency response plot can be obtained by substituting for the
input frequency I values from 100 Hz to 100 kHz in Equation (8-6). These data are
included in Table 8-3. Equation (8-{>) is repeated here for convenience:
I 1-
V0
Vtn - ~1
Ap(J/ IL)
+ (//JL)2
where Ap = 2 and IL = l kHz. The frequency response data of Table 8-3 are plotted
in Figure 8-7. In the stopband (from 100 Hz to 1 kHz) the gain increases at the rate
of 20 dB/decade. However, in the passband (after I= IL = 1 kHz) the gain remains
constant at 6.02 dB. The upper-frequency limit of the passband is set by the closed-loop
bandwidth of the op-amp.

TABLE 8-3 FREQUENCY RESPONSE DATA FOR THE
FIRST-ORDER HIGH-PASS FILTER OF EXAMPLE 8-5
Frequency, I Gain magnitude, Magnitude (dB)=

(Hz) I Vo/Vin I 20 log I na/vin I .
1. 100 0.20 -14.02

2. 200 0.39 -8.13
3. 400 0.74 -2.58
4. 700 1.15 1.19
I
5. 1,000 1.41 3.01
6. 3,000 1.90 5.56
7. 7,000 1.98 5.93
8. 10,000 1.99 5.98
9. 30,000 2 6.02
10. 100,000 2 6.02
+10
OdB
a:, -10 _
"l:I
.E
c:
'iii
c., -20
-30
100 10k 100k 1M
I Frequency (Hz)
' .
8-6 SECOND-ORDER HIGH-PASS BUTTERWORTH FILTER
a
As in the case of the first-order filter, second-order high-pass filter can be formed
from a second-order low-pass filter simply by.interchanging the frequency determining
resistors and capacitors. Figure 8-S(a) shows the second-order high-pass filter.
The voltage gain magnitude equation of the second-order high-pass filter is
as follows: ·
(8-7)
where A, = 1.586 = passband gain for the second-order Butterworth response

f = frequency of the input signal (hertz)
IL . low cutoff frequency (hertz)
Sec. 8-6 Second-Order High-Pass Butterworth Filter 295
R,
Voltage gain·
27 k.Sl 15.8 k.Sl
40 dB/decade
Stop
band ......1-4---Passband -----,~
Frequency
(al (bl
Figure 8-8 (a) Second-order high-pass Butterworth filter. (b) Its frequency response.
Since second-order low-pass and high-pass filters are the same circuits except that the
positions of resis~rs and capacitors are interchanged, the design and frequency
scaling procedures for the high-pass filter are the same as those for the low-pass filter.
Example 8-6
(a) Determine the low cutoff frequency IL of the filter shown in Figure 8-8(a).
(b) Draw the frequency response plot of the filter.
Solution
(a) IL= , 1
21t,v R2C2R3C3
1
21t~(33 k0)2(0.0047 µF)2,..,,, l kHz
I
(b) The frequency response data in Table 8-4 are obtained from voltage-gain-magni-
tude Equation (8-7), which is repeated here for convenience:
j
l
V0
V111
l=~ 1
Ap
+ UL/1) 4
TABLE 8-4 FREQUENCY RESPONSE DATA FOR SECOND-ORDER

HIGH-PASS FILTER OF EXAMPLE 8-6
Input frequency, Gain magnitude, Magnitude (dB) =

/(Hz) I vsl»,« I 20 log I 'L'o/Vin I
1. 100 0.01586 -35.99

2. 200 0.0634 -23.96
3. 700 0.6979 -3.124
4. 1,000 1.1215 0.9960
5. 3,000 1.5763 3.953
6. 7,000 1.5857 4.004
7. 10,000 1.5859 4.006
8. 30,000 1.5860 4.006
9. 100,000 1.5860 4.006

+10
O dB
CD
"CJ
c ~10
c
·;;;
.,
Cl
Cl
s I
0
>
-30
-----------Passband----------~
100 10 k1 100 k 1M
Frequency (Hz)
where AF = 1.586 and IL = 1 kHz. The resulting frequency response plot is shown in
· Figure 8-9. .:
8-7 HIGHER-ORDER FILTERS
From the preceding discussions of filters we can conclude that in the stopband the
gain of the filter changes at the rate of 20 dB/decade for first-order filters and at
40 dB/decade for second-order filters. This means that as the order of the filter is
increased, the actual stopband response of the filter approaches its ideal stopband
characteristic.
Higher-order filters, such as third, fourth, fifth, and so on, are formed simply
by using the first- and second-order filters. For example, a third-order low-pass filter
is formed by connecting in series or cascading first- and second-order low-pass filters;
a fourth-order low-pass filter is composed of two cascaded second-order low-pass
sections, and so on. Although there is rio limit to the order of the filter that can be
formed, as the order of the filter.increases, so does its size. Also, its accuracy declines,
in that the difference between the actual stopband response and the theoretical
stopband response increases with an increase in the order of the filter. Figure 8-10
shows third- and fourth-order low-pass Butterworth filters. Note that in the third-order
filter the voltage gain of the first-order section is one, and that of the second-order
section is two. On the other hand, in the fourth-order filter the gain of the first section
is 1.152, while that of the second section is 2.235. These gain values are necessary to
guarantee Butterworth response and have to remain the same regardless of the filter's
cutoff frequency. Furthermore, the overall gain of the filter is equal to the product of
the individual voltage gains of the filter sections. Thus the overall gain of the third-
order filter is 2.0, and that of the fourth order is ( 1.152)(2.235) = 2.57.
Sec. 8-7 Higher-Order Filters 297

Since the frequency-determining resistors are equal, and the· frequency-deter-
mining capacitors are also equal, the high cutoff frequencies of the third=and fourth-
order low-pass filters in Figure 8-lO(a) and (b) must also be equal. That is,
First-order Second-order
low-pass low-pass
section section
21 kn 15.8 kn
+Vee
+15 V
i C
0.01 µF
-VEE c
0.01 µF
c
O.Ql µF 1
(al
-------Second-order low-pass section-------t------Second-order low-pass section-----

R'F
R, 18 kn 22kn
15 kn 2.2 kn
c
+ c 0.01 µF
c
0.01 µF 0.01 µFl
(b)
Gain, I Vo I
Yin
-=-~-=-~-~!lo..
AF ~-...
Third order {-60 dB/decade roll-off)
0.707AF
Founh order (-BO dB/decade roll-off)
Frequency
{cl
Figure 8-10 (a) Third-order and (b) fourth-order low-pass Butterworth filters. (c) Their
frequency responses. A1 and A2 dual op-amp: 1458/353.
298 Active Filters and Oscillators Chap.a

1
!H = 2nRC (8-8)
As with the first- and second-order filters, the third- and fourth-order high-pass
filters are formed by simply interchanging the positions of the frequency-determining
resistors and capacitors in the corresponding low-pass filters. The high-order filters
can be designed by following the procedures outlined for the first- and second-order
filters. However, note that the overall gain of the higher-order filters is fixed because
all the frequency-determining resistors and capacitors are equal.
Generally, the minimum-orders filter required depends on the application
specifications. Although a higher-order filter than necessary gives a better stopband
response, the higher-order type is more complex, occupies more space, and is more
expensive.
8-8 BAND-PASS FILTERS
Basically, there are two types of band-pass filters:
1. Wide band pass

2. Narrow band pass
Unfortunately, there is no set dividing line between the two. However, we will define
a filter as wide band pass if its figure of merit or quality factor Q < l 0. On the other
hand, if Q > 10, we will call the filter a narrow band-pass.filter. Thus Q is a measure
of selectivity, meaning the higher the value of Q, the more selective is the filter or the
narrower its bandwidth. The relationship between Q; the 3-dB bandwidth, and the
center frequency fe is given by
Q = fe = fe (8-9a)
BW !H-!L
For the wide band-pass filter the center frequency le can be defined as
le= ~!HfL (8-9b)
where f 8 = high cutoff frequency
· JL = low cutoff frequency of the wide band-pass filter
In a narrow band-pass filter, the output voltage peaks at the center frequency.
8-8.1 Wide Band-Pass Filter
A number of possible circuits will realize the band-pass responses. A wide band-pass
filter can be formed by simply cascading high-pass and low-pass sections and is
generally the choice for simplicity of design and performance. To obtain a ±20 dB/
decade band-pass, first-order high-pass and first-order low-pass sections are cascaded;
for a ±40-dB/decade band-pass filter, second-order high-pass and second-order low-
pass sections are connected in series, and so on. In other words, the order of the
band-pass filter depends on the order of the high-pass and low-pass filter sections.
Sec. 8-8 Band-Pass Filters 299

Figure 8-11 shows the ±20-dB/decade wide band-pass filter, which is composed
of a first-order high-pass filter and a first-order low-pass filter. To realize a band-pass
response, howevt!r,fH must be larger thanfL, as illustrated in Example 8-7.
First-order First-order
high-pass low-pass
section section
R' 1 R'F
R, RF
lOkn 10 kn
10 kn 10 kn
f L: 200 Hz
(al
I
Gain, I vo I
Vin
+20 dB/decade
-20 dB/decade
Stop -----Passband-~...+--oi----Stop -
band band
Frequency
(bl
Figure 8-11 (a) ±20-dB/dccade-wideband-pass filter. (b) Its frequency response.

A1 and A2. dual op-amp: 1458/353.
Example 8-7
(a) Design a wide band-pass filter with IL = 200 Hz, !H = I kHz, and a passband
gain= 4.
(b) Draw the frequency response pi)t of this filter.
(c) Calculate the value of Q for the filter.
Solution
(a) A low-pass filter with/8 = 1 kHz was designed in Example 8-1; therefore, the same
values of resistors and capacitors can be used here, that is, R' = 15.9 k!l and C' =
0.01 pF. As in the case of the high-pass filter, it can be designed by following the steps
of Section 8-3.1 :

1. IL=200 Hz.
2. Let C = 0.05 µF.
3. Then
1 1
R = 2nfLC = (2n)(200)(5)(10-8)
= 15.9 kQ
Since the band-pass gain is 4, the ~ain of the high-pass as well as low-pass sections
could be set equal to 2. That is, injiut and feedback resistors must be equal in value,
say 10 kQ each. The complete band-pass filter is shown in Figure 8-1 l(a).
(b) The voltage gain magnitude of the band-pass filter is equal to the product of the
voltage gain magnitudes of the high-pass and low-pass filters. Therefore, from Equa-
tions (8-2a) and (8-6),
Va I AFT(fflL) .
I Vin = ~[1 + (flfL)2][1 + (f!JH)2]
(8-10)
where AFT = total passband gain

I= frequency of the input signal (hertz)
IL = low cutoff frequency (hertz)
IH = high cutoff frequency (hertz)
Here APT = 4, IL = 200 Hz, and In = 1 kHz. The frequency response data in Table
8-5 are obtained by substituting into Equation (8-10) the values of I from 10 Hz to.
TABLE 8-5 F.REOUENCY RESPONSE DATA FOR THE BAND-PASS

FILTER OF EXAMPLE 8-7
-
Input frequency, Gain magnitude, Magnitude (dB)=
/(Hz) I Vo/Vin I 20 log I Vo/Vin I
1. 10 0.1997 -13.99
2. 30 0.5931 -4.54
3. 100 1.780 5.01
4. 200 2.774 8.861
5. 447.2 3.33 10.46
6. 700 3.151 9.969
7. 1,000 2.774 8.861
8. 2,000 1.780 5.001
9. 7,000 0.5655 -4.95
10. 10,000 0.3979 -8.004
10 kHz. The frequency response plot is shown in Figure 8-12.

(c) From Equation (8-9b),
le= ~(1000)(2001:;= 447.2 Hz
Substituting this value in Equation (8-9a),
Q = 10:~\ 00 = o.56
Thus Q is less than 10, as expected for the wide band-pass filter.
Sec. 8-8 Band- Pass Filters 301

+15
+10
+5
CD
.s -20 dB/decade
c
"'"' O dB
~"'"'
0
>
-5
-10
-15 Bandwidth
10 100 fl= 200 10 k 100 k
fc :: 447
Frequency (Hz)
8-8.2 Narrow Band-Pass Filter

»
The narrow band-pass filter using multiple feedback is shown in Figure 8-13. As
shown in this figure, the filter uses only one op-amp. Compared to all the filters
discussed so far, this filter is unique in the following respects:
1. It has two feedback paths, hence the name multiple-feedbackfilter.

2. The op-amp is used in the inverting mode.
Generally, the narrow band-pass filter is designed for specific values of center
frequency Jc and Q, or fe and bandwidth [see Equation (8-9a)]. The circuit components
are determined from the following relationships:
To simplify the design calculations, choose C1 = C2 = C.
R1 - Q (8-11)
- 21tfeCAp
R2 - Q (8-12)
--'2nfeC(2Q2 - Ap)
R3 ·_S2_ (8-13)
1tfeC
where Ap is the gain at fe, given by
(8-14a)
302 Active Fitters and Oscillators Chap. 8

(a)
v
Gain, I 2- I
Vin
Frequency
Figure 8-13 (a) Multiple-feedback
narrow band-pass filter. (b)-l.ts
(b) frequency response.
The gain Ap, however, must satisfy the condition

Ap < 2Q2 (8--14b)
Another advantage of the multiple feedback filter of Figure 8-13 is that its
center frequency Jc can be changed to a new frequency f~without changing the gain
or bandwidth. This is accomplished simply by changing R2 to R;, so that
R; = R2 (fir (8-15)
(see Example 8-8).
Example 8-8
(a) Design the bandpass filter shown in Figure 8-13(a) so that fc = 1 kHz, Q = 3,
and Ap = 10.
(b) Change the center frequency to 1.5 kHz, keeping Ap and the bandwidth constant.
Solution
(a) Choose the values of C1 and C2 first and then calculate the values of R1, R2, and
R3 from Equations (8-11) through (8-13). Let C1 = C2 = C = 0.01 µF.
Sec. 8-8 Band-Pass Filters 303

3
R1 = (21t)(l03)(10-s)(lO) = 4.77 k!l
3 .
R2 = (2n)(l0'3)(10-8)[2(3)2 - 10] = 5·97 k!l
3
R3 = (1t)(l03)(10-s) = 95.5 k!l
Use R1 :== 4.7 k!l, R2 = 6.2 k!l, and RJ = 100 k!l.
(b) Using Equation (8-15), the value of R; required to change the center frequency
from 1 kHz to 1.5 kHz is
R; = (5.97 k!l)(//~) = 2.65 k!l
(Use R; = 2.7 Q.)
8-9 BAND-REJECT FILTERS
The band-reject filter is also called a band-stop or band-elimination filter. In this filter,
frequencies are attenuated in the stopband while they are passed outside this band,
as shown in Figure 8-1 (d). As with band-pass filters, the band-reject filters can also
be classified as ( l) wide band-reject or (2) narrow band-reject. The narrow band-
reject filter is commonly called the notch filter. Because of its higher Q (> 10), the
bandwidth of the narrow band-reject filter is much smaller than that of the wide
band-reject filter.
8-9.1 Wide Ban.d-RejectFilter
Figure 8-14(a) shows a wide band-reject filter using a low-pass filter, a high-pass
filter, and a summing amplifier. To realize a band-reject response, the low cutoff
frequency JL of the high-pass filter must be larger than the high cutoff frequency [»
of the low-pass filter. In addition, the passband gain of both the high-pass and low-pass
sections must be equal (see Example 8-9). The frequency response of the wide band-
reject filter is shown in Figure 8-14(b ).
Example 8-9
Design a wide band-reject filter having IH = 200 Hz, IL = 1 kHz.
Solution. In Example 8-7 a wide band-pass filter was designed withfL = 200 Hz and
fir = 1 kHz. In this example these band frequencies are interchanged, that is, IL =
1 kHz and In = 200 Hz. This means that we can use the same components as in Exam-
ple 8-7, but interchanged between high-pass and low-pass sections. Therefore, for the
low-pass sectiori, R' = 15.9 k!l and C' = 0.05 µF, while for the high-pass section
R = 15.9 k!l and C = O.Ql µF
I
Since there is no restriction on the passband gain, use a gain of 2 for each section.
Hence let
R1 =RP= R'1 = R'r, = 10 k!l
Further, the gain of the summing amplifier is set at 1; therefore,
R2 = R3 = R4 = 10 ill
Finally, the value of RoM = R2 II R3 I R4 ,...., 3.3 ill.

10 kn 10 kn
-VEE 10 kn
-15V
-VEE
RaM
-15 V
3.3kn
R~ 10 kn
(a)
Vo
Gain, I -
'(in
- . I
Passband --i-ReJect -,-.-Passband -
I band
I
AF= 2 ---- ... -1- - - - - - -1------
1. I
1.414
fc = ~ =.447.2 Hz Frequency
(b)
Figure 8-14 Wide band-reject filter, (a) Circuit. (b) Frequency response. For all
A 1, A2, and A 3 use quad op-amp µAF774/MC34004.
The complete circuit is shown in Figure 8-14(a), and its response is shown in
Figure 8-14(b). The voltage gain changes at the rate of20 dB/decade abovefn and below
fL, with a maximum attenuation occurring at fc-
8-9.2 Narrow Band-Reject Filter
The narrow band-reject filter, often called the notch filter, is commonly used for the
rejection of a single frequency, such as the 60-Hz power line frequency hum. The
most commonly used notch filter is the twin-T network shown in Figure 8-15(a). This
is a passivefilter composed of two "T" -shaped networks. One T network is made up
Sec. 8-9 Band-Reject Filters 305

R R
c c
Vin Vo
R
2C
2
(al
(bl
v
Gain, I~ I
Vin Bandwidth
AF = 1 1-----,
0.707
Figure 8-15. (a) Twin-T notch filter.

Frequency (b) Active notch filter. (c) Frequency
(cl response of the active notch filter.
of two resistors and a capacitor, while the other uses two capacitors and a resistor.
The "notch-out" frequency is the frequency at which maximum attenuation occurs;
it is given by ·
(8-16)
Unfortunately, the passive twin-T network has a relatively low figure of merit Q.
However, the Q of the network can be increased significantly if it is used with the
voltage follower as shown in Figure 8-15(b). Here the output of the voltage follower
is fed back to the junction of R/2 and 2C. The frequency response of the active notch
filter of Figure 8-15(b) is shown ilt Figure 8-15(c). The most common use of notch
filters is in communications and biomedical instruments for eliminating undesired
frequencies. In order to design an active notch filter for a specific notch-out frequency
f N, choose the value of C < I µF and then calculate the required value of R from
Equation (8-16). For the best response, the circuit components should be very close
to their indicated values.

Example 8-10
Design a 60-Hz active notch filter.
Solution. Let C = 0.068 µF. Then, from Equation (8-16), the value of R is
1 1
R = 2nfNC = (2n)(60)(68)(10-9) = 39.ot kn
(Use 39 kQ.) For R/2, parallel two 39-kQ resistors; for the 2C component, parallel
two 0.068-µF capacitors.
I
8-10 ALL-PASS FILTER
As the name suggests, an all-pass filter passes all frequency components of the input
signal without attenuation, while providing predictable phase shifts for different
frequencies of the input signal. When signals are transmitted over transmission lines,
such as telephone wires, they undergo change in phase. To compensate for these
phase changes, all-pass filters are required. The all-pass filters are also called delay
equalizers or phase correctors. Figure 8-16(a) shows an all-pass filter wherein RP= R1•
The output voltage v0 of the filter can be obtained by using the superposition theorem:
1 o kn 1 o kn
>--+---n v = 1 - j21rfRC
o 1 + j2,rfRC Vin
-Vee
-15 V
(a)
Voltage
(b)
Figure 8-16 All-pass filter. (a) Circuit. (b) Phase shift between input and output
voltages.
Sec. 8-10 All-Pass Filter ,307

Vo = -V;a ·x Via (2)
+ R-jXe
-1 e
(8-17)
But -} = 1/j and Xe= I/21t/C. Therefore, substituting for Xe and simplifying, we
get
Vo= V;a (-1 + j2nJR~ + 1)
or
Vo 1 - j2nf RC (8-18)
Via = 1 + j'Inf, RC
where J is the frequency of the input signal in hertz.
Equation (8-18) indicates that the amplitude of vJv: is unity; that is, I v I = I 'l.lia I 0
throughout the useful frequency range, and the phase shift between v and v1a is a 0
function of input frequency f The phase angle <p is given by
¢ = -2tan-1 (2nftC) (8-19)
where <p is in degrees, Jin hertz, R in ohms, and C in farads. Equation (8-19) is used
to find the phase angle e if/, R, and Care known. Figure 8-16(b) shows a phase shift
of 90° between the input v1a and output v That is, u, lags v,a by 90°. For fixed values
0•
of R and C, the phase angle ~ changes from O to -180° as the frequency J is varied
from O to oo . In Figure 8-16(a), if the positions of R and C are interchanged, the
phase shift between input and output becomes positive. That is, output v0 leads input
Vin·
Example 8-11
For the all-pass filter of Figure 8-16(a), find the phase angle <p if the frequency of v;0
is 1 kHz.
<p = -2 tan-1 [(21t)(103)(1\9)(103)(10-S)J
= -90°
This means that the output voltage v0 has the same frequency and amplitude but lags
V;n by 90°, as shown in Figure 8-16(b).
With the advancement of integrated-circuit technology, a number of manufac-

turers now offer ready-to-use universal filters having simultaneous low-pass, high-pass,
and band-pass output responses. Notch and all-pass functions are also available by
combining these output responses in the uncommitted op-amp. Because of its versatil-
ity, this filter is called the universal filter. It provides the user with easy control of the
gain and Q factor. The universal filter, sometimes called a stat.e-variable filter, is
presented in Chapter 10.
I
8-11 OSCILLATORS
Thus far we have examined op-amps wired as amplifiers or filters. This section will
introduce the use of op-amps as oscillators capable of generating a variety of output
waveforms, Basically, the function of an oscillator is to generate alternating current

or voltage waveforms. More precisely, an oscillator is a circuit that generates a
repetitive waveform of fixed amplitude and frequency without any external input
signal. Oscillators are used in radio, television, computers, and communications .
. Although there .are different types of oscillators, all of them work on the same basic
principle.
8-11.1 Oscillator Principles
An oscillator as such is a type of feedback amplifier in which part of the output is

fed back to the input via a feedback1circuit. If the signal fed back is of proper magni-
tude and phase, the circuit produces alternating currents or voltages. To visualize
the requirements of an oscillator, consider the block diagram of Figure 8-17. This
diagram looks identical to that of the feedback amplifiers of Chapter 4 (see Figures
4-3 and 4-9). However, here the input voltage is zero (v10 = 0). Besides that, the
feedback is positive because most oscillators use positive feedback. Finally, the
closed-loop gain of the amplifier is denoted by Av rather than Ap.
Summing junction
Amplifier Vo
1--v-d-i Amplifier 1-----.--vo
Av Av
Output Output
Feedback Feedback
circuit circuit
B Vr B
~
Figure 8'-17 Oscillator block diagram.
In the block diagram of Figure 8-17,

V4 =VI+ Via
v0 = Avv4
v1 = Bv 0
Using these relationships, the following equation is obtained:
However, Vin = 0 and Vo =;t:. 0 implies that

AvB = 1 (8-20)
Expressed in polar form,
AvB = I /0° or 360° (8-21)
Equation (8-21) gives the two requirements for oscillation: (1) the magnitude of the
loop gain A.B must be at least 1, and (2) the total phase shift of the loop gain A.B
must be equal to 0° or 360°. For instance, as indicated in Figure 8-17, if the amplifier
causes a phase shift of 180°, the feedback circuit must provide an additional phase
Sec. 8-11 Oscillators 309

shift of 180° so that the total phase shift around the loop is 360°. The waveforms
shown in Figure 8-17 are sinusoidal and are used to illustrate the circuit's action. The
type of waveform generated by an.oscillator depends on the components in the circuit
and hence may be sinusoidal, square, or triangular. In addition, the frequency of
oscillation is determined by the components in the feedback circuit.
8-11.2 Oscillator Types
Because of their widespread use, many different types of oscillators are available.
These oscillator types are summarized in Table 8-6.
TABLE 8-6 OSCILLATOR TYPES
Types of components Frequency of Types of waveform

used oscillation generated
1. RC oscillator 1. Audio frequency (AF) I. Sinusoidal

2. LC oscillator 2. Radio frequency (RF) 2. Square wave
3. Crystal oscillator 3. Triangular wave
4. Sawtooth wave etc.
8-11.3 Frequency Stability
The ability of the oscillator circuit to oscillate at one exact frequency is called frequency
stability. Although there may be a number of factors that cause changes in oscillator
frequency, the primary factors are temperature changes and changes in the de power
supply. Temperature and power supply changes cause variations in the op-amp's
gain, in junction capacitances and resistances of the transistors in an op-amp, as well
as in external circuit components. In most cases these variations can be kept small by
careful design, by using regulated power supplies, and by temperature control.
Another important factor that determines frequency stability is the figure of
merit Q of the circuit: The higher the Q, the greater the stability. For this reason,
crystal oscillators are far more stable than RC or LC oscillators, especially at higher
frequencies. LC circuits and crystals are generally used for the generation of high-
frequency signals, while RC components are most suitable for audio-frequency
applications. Here we discuss audio-frequency RC oscillators only. We begin with
the sinusoidal oscillators.
8-12 PHASE SHIFT OSCILLATOR
Figure 8-18 shows a phase shift oscillttor which consists of an op-amp as the amplify-
ing stage and three RC cascaded networks as the feedback circuit. The feedback circuit
provides feedback voltage from the output back to the input of the amplifier. The
op-amp is used in the inverting mode; therefore, any signal that appears at the inverting
terminal is shifted by 180° at the output. An additional 180° phase shift required for
oscillation is provided by the cascaded RC networks. Thus the total phase shift around

Amplifier--. -R- - - - - - fl - - - - -,
I 1 F
I
33 kfl I
I
+Vee I
+15 V I
I
I
01 ..........--IN4735
02 V2 = 6.2 V
I v 01 = v 02 = 0. 7 v
I
L------------- _J
I c c c ,
I
I 0.1 µF 0.1 µF 0.1 µF I
I
I R R R
I 3.3 kfl 3.3 kfl 3.3 kfl
I
I
I
Feedback----+i I
circuit L - - - - ...,
(v2 + V01)
= 6.9 V
-(v, + Vo2l f = 0.065

= -6.9 V
T O
RC
5 ms
Figure 8-18 Phase shift oscillator and its output waveform.
the loop is 360° (or 0°). At some specific frequency when the phase shift of the cascaded
RC networks is exactly 180° and the gain of the amplifier is sufficiently large, the
circuit will oscillate at that frequency. This frequency is called the frequency of
oscillation lo and is given by
1 0.065
fa= 2rc,.,.fo RC = RC (8-22a)
At this frequency, the gain Av must be at least 29. That is,
l~:I = 29
or
(8-22b)
Sec.8-12 Phase Shift Oscillator 311

Thus the circuit will produce a sinusoidal waveform of frequency J. if the gain is 29
and the total phase shift around the circuit is exactly 360°. For a desired frequency
of'.oscillation, choose a capacitor C, and then calculate the value of R from Equation.
(8-22a). A desired output amplitude, however, can be obtained with back-to-back
zeners connected at the output terminal. For more information on zeners, refer to
Section 9- 7.
Example 8-12
Design the phase shift oscillator of Figure 8-18 so that fo = 200 Hz.
Solution. Let C = 0.1 µF. Then from Equation (8-22a),
0.065
R = (200)(1Q-?) = 3.25 kn
(Use R = 3.3 kn.)
To prevent the loading of the amplifier because of RC networks, it is necessary
that R1 > lOR. Therefore, let R1 = IOR = 33 kn. Then, from Equation (8-22b),
Rp = 29(33 kn) = 957 kn
(Use RP = 1 Mn potentiometer.)
When choosing an op-amp, type 741 can be used at lower frequencies ( <1 kHz);
however, at higher frequencies, an op-amp such as the LM318 or LF351 is recom-
mended because of its increased slew rate.
8-13 WIEN BRIDGE OSCILLATOR
Because of its simplicity and stability, one of the most commonly used audio-frequency
oscillators is the Wien bridge. Figure 8-19 shows the Wien bridge oscillator in which
the Wien bridge circuit is connected between the amplifier input terminals and the
output terminal. The bridge has a series RC network in one arm and a parallel RC
network in the adjoining arm. In the remaining two arms of the bridge, resistors R1
and RP are connected (see Figure 8-19).
The phase angle criterion for oscillation is that the total phase shift around the
circuit must be 0°. This condition ..occurs only when the bridge is balanced, that is,
at resonance. The frequency of oscillation 1 is exactly the resonant frequency of the
0
balanced Wien bridge and is given by

1 0.159
(8-23a)
lo = 21tRC = RC
assuming that the resistors are equal in value, and capacitors are equal in value in
the reactive leg of the Wien bridge At this frequency the gain required for sustained
oscillation is given by ·
A• ..L ! = 3
That is,
or
(8-23b)

Amplifier
~----------------,
I A 1 AF I
I I
I I
I I
I Pot at 24 k.11 I
I I
I I
I I
I I
I I
I I
I
I
IL -15 V JI
r-----------------,
A C I
I 3.3 k.11 0.05 µF

I
I
I
I A 3.3 k.11 c
I
I
I
I I
L---------------- _J
Feedback
circuit
Figure 8-19 _Wien bridge oscillator.
The Wien bridge oscillator is designed using Equations (8-23a) and (8-23b), as
illustrated in Example 8-13.
Example 8-13
Design the Wien bridge oscillator of Figure 8-19 so that I., = 965 Hz.
Solution. Let C = 0.05 µF. Therefore, from Equation (8-23a),
0.159 ·
R = (5)(10-8)(965) = 3·3 ill
Now, let R1 = 12 kO!
. I
Then, from Equation (8-23b),
I RP = (2)(12 ill) = 24 ill
(Use s, = 50 kO potentiometer.)
8-14 QUADRATURE OSCILLATOR
. As its name implies, the quadrature oscillator generates two signals (sine and cosine)
that are in quadrature, that is, out of phase by 90°. Although the actual location of
the sine and cosine is arbitrary, in the quadrature oscillator of Figure 8-20 the output
of A I is labeled a sine and the output of A2 is a cosine. This oscillator requires a dual
op-amp and three RC combinations. The first op-amp A I is operating in the non-
inverting mode and appears as a noninverting integrator. The second op-amp A2 is
working as a pure integrator. Further, A2 is followed by a voltage divider consisting
Sec. 8-14 Quadrature Oscillator -313

Amplifier
r----------------------------------~
c,
100 kn 0.01 µF Sine Cosine
i i
100 kn 0.01 µF
( .
_ (,I.IC . I( ,j_f. .
L-------------------~ I
I
: RoM
I 100 kn
I
I I
I I
L J
I
r,' ., J]. I 100 kn I
2,
- I.{,.
\.. 'v I l C3i 0.01 µF ;
I I
IL JI
Feedback
circuit
Figure 8-20 Quadrature oscillator. A1 and A2: dual op-amp 1458/353.
of R3 and C3• The divider network forms a feedback circuit, whereas A 1 and A2 form
the amplifier stage.
The total phase shift of 360° around the loop required for oscillation is obtained
in the following way. The op-amp A2 is a pure integrator and inverter. Hence it
contributes -270° or (90°) of phase shift. The remaining -90° (or 270°) of phase
shift needed are obtained at the voltage divider R3C3 and the op-amp A1• The total
phase shift of 360°, however, is obtained at only one frequency fa, called the frequency
of oscillation. This frequency is given by
1
fa= 21tRC (8-.24a)
where R1C1 = R2C2 = R3C3 =RC.At this frequency,

I 1
Av= Ii= 1.414 (8-24b)
which is the second condition for oscillation.

Thus to design a quadrature oscillator for a desired frequency fa, choose a
value of C; then from Equation (8-24a), calculate the value of R. To simplify design
calculations, choose C1 = C2 = C3 and R1 = R2 = R3• In addition, R1 may be a
potentiometer in order to eliminate any possible distortion in the output waveforms.

Example 8-14
Design the quadrature oscillator of Figure 8-20 so that lo = 159 Hz. The op-amp is
the 1458/772.
Solution. Let C = 0.01 µF. Then, from Equation (8-24a),
0.159
R = (1S9)(10-s) = 100 kn
Thus C1 = C2 = C3 = 0.01 µF and R1 = R,. = R3 = 100 kn. R1 may be a 200-kn
potentiometer, which can be adjusted for undistorted output waveforms.
I
Using the oscillator principles of Section 8-11.1, a number of other sine-wave

RC oscillators, such as the twin-T and biquad (biquadratic), can also be designed.
Before proceeding with the other types of oscillators, consider the difference
between the signal generator and the function generator. The function generator has
more than one function, such as sine wave, square wave, and triangular wave; the
signal generator often generates only one type· of waveform, such as a sine wave.
However, both types of generators have amplitude and frequency modulation capa-
bilities, unlike the oscillator. Since the generator and the oscillator are equivalent
terms, they can be used interchangeably. Usually, circuits producing sine waves are
called oscillators, while those generating a square wave, triangular wave, or sawtooth
wave are called generators.
8-15 SQUARE-WAVE GENERATOR
In -contrast to sine-wave oscillators, square-wave outputs are generated when the

op-amp is forced to operate in the saturated region. That is, the output of the op-amp
is forced to swing repetitively between positive saturation + V.. i (~ + Vee) and nega-
tive saturation - V,u (~ - VEE), resulting in the square-wave output. One such
circuit is shown in Figure 8-2l{a). This square-wave generator is also called a free-
running or astable multivibrator. The output of the op-amp in this circuit will be in
positive or negative saturation, depending on whether the differential voltage v,d is
negative or positive, respectively.
. Assume that the voltage across capacitor C is zero volts at the instant the de
supply voltagesvl- Vee and .; VEE are applied, see Figure 8-2l{b)]. This means that'
the voltage at the inverting terminal is zero initially. At the same instant, however,
the voltage v1 at the noninverting terminal is a very small finite value which is a
function of the output offset voltage V r and the values of R1 and R2 resistors. Thus
00
the differential input voltage v,d is equal to the voltage v1 at the noninverting terminal.
Although very small, voltage Vi will start to drive the op-amp into saturation. For
example, suppose that the output offset voltage V r is positive and that, therefore,
00
voltage Vi is also positive. Since initially the capacitor C acts as a short circuit, the
gain of the op-amp is very large (A), hence v1 drives the output of the op-amp to its
positive saturation + V,u· With the output voltage of the op-amp at + V,u, the
capacitor C starts charging toward + V,.. through resistor R. However, ~s soon as
the voltage v2 across capacitor C is slightly more positive than Vi, the output of the
op-amp is forced to switch to a negative saturation - V,u· With the op-amps' output
Sec.8-15 Square-Wave Generator 315

Output Voltage across
voltage capacitor
c v, R Vo V2
V°··· Rs
-A/Nv-
lOkSl +v,.,:: Vee...,._ ........_
Yid
R, V2
lOkSl ~
Rs
R2 -v.,., :: -Vee
11.6 kn (20-kn pot.) -T~
. R,
[ v, I= -- JV,.,I
(al
R1 + R2
fO = .!. = -1- if R2= 1.16R1

T 2RC
Figure 8-21 (a) Square-wave generator. (b) Waveforms of output voltage v0

and capacitor voltage v2 of the square-wave generator.
voltage at negative saturation - V.. u the voltage v1 across R, is also negative, since
V1 = Ri -t R
R
2 (-V,u) (8-25a)
Thus the net differential voltage v,d = Vi - v2 is negative, which holds the output
of the op-amp in negative saturation. The output remains in negative saturation until
the capacitor C discharges and then recharges to a negative voltage slightly higher
than -vi [see Figure 8-21(b)]. Now, as soon as the capacitor's voltage v2 becomes
more negative than -v1, the net differential voltage v,d becomes positive and hence
drives the output of the op-amp back to its positive saturation + V,.1• This completes
one cycle. With output at + V,.1, voltage v1 at the noninverting input is·
V1 = Ri ! R2 ( + V,u) (8-25b)
The time period T of the output waveform is given by
T = 2RC In (2R1 + Rz)

R2.
(8-26a)
or
I 1
(8-26b)
lo= 2RC ln[(2R1 + R2)/R2]
Equation (8-26b) indicates that the frequency of the output 10 is not only a function
of the RC time constant but also of the relationship between R1 and R2• For example,
if R2 = 1.16R., Equation (8-26b) becomes
l
lo = 2RC (8-27)
316 Active Filters and Oscillators

Equation (8-27) shows that the smaller the RC time constant; the higher ·the output
frequency la, and vice versa. As with the sine-wave oscillators, the highest frequency
generated by the square-wave generator is also set by the slew rate of the op-amp.
An attempt to operate the circuit at relatively higher frequencies causes the oscillator's
output to become triangular. In practice, each inverting and noninverting terminal
needs a series resistance Rs i6 prevent excessive differential current flow because the
inputs of the op-amp are subjected to large differential voltages. The resistance Rs
used should be 100 k!l or hjgher.
I
A reduced peak-to-peak output. voltage swing can
be obtained in the square-wave generator of Figure 8-2l(a) by using back-to-back
zeners at the output terminal.
I
Example 8-15
Design the square-wave oscillator of Figure 8-21(a) so that!.,= 1 kHz. The op-amp
is a 741 with de supply voltages= ±15 V.
Solution. Use R2 = l.16R1, so that the simplified frequency Equation (8-27) can be
applied. Let R1 = 10 kn. Then
R2. = (l.16)(10 ill) = 11.6 kO
(Use R2 = 20 k!l potentiometer.) .
Next, choose a value of C and calculate the value of R from Equation (8-27).
Hence let C .= 0.05 µF. By Equation (8-27),
1
R = (10)(10-8)(103) = 10 kQ
Thus
R1 = lOk!l
R2 = 11.6 k!l (20 Jdl potentiometer)
R = lOk!l
C = 0.05 µF
8~16 TRIANGULAR-WAVE GENERATOR
Recall that the output waveform of the integrator is triangular if its input is a square
wave (refer to Section 7-12). This means that a triangular-wave generator can be
formed by simply connecting an integrator to the square-wave generator of Figure
8-21. The resultant circuit is shown in Figure 8-22(a). This circuit requires a dual
op-amp, two capacitors, and at least five resistors. The frequency of the square wave
and triangular wave is the same. For fixed R1, R2, and C values, the frequency of the
square-wave as well as the triangular wave depends on the resistance R [see Equation
(8-26b)]. As R is increased or decreased, the frequency of the triangular wave will
decrease or' increase, respectively. Although the amplitude of the square wave is
constant (± V,u), the amplitude of the triangular wave decreases with an increase in
its frequency, and vice versa. [see Figure 8-22(b)].
The input of integrator A2 is a square wave, while its output is a triangular wave.
However, the output of A2 to be a triangular wave requires that 5R3C2 > T/2, where
Tis the period of the square-wave input. As a general rule, R3C2 should be equal to
Sec. 8-16 Triangular-Wave Generator 317

c R
10kfl
100 kfl 0.01 µF
-Vee
-15 V
11.6 kfl
-Vee
-15 V
(a)
Voltage
+v ..t :::: +Vee
-V,.,:::: -VEE
l
(b)
Figure 8-22 Triangular-wave generator. (a) Circuit. (b) Its output waveform.
A1 and A2: dual op-amp 1458/353.
T. To obtain a stable triangular wave, it may also be necessary to shunt the capacitor
C2 with resistance R4 = 10R3 and connect an offset voltage compensating network
at the noninverting terminal of A2• As with any other oscillator, the frequency of the
triangular-wave generator is limited by the slew rate of the 0p-a~p. Therefore, high
slew rate op-amps should be used for the generation of relatively higher frequencies.
Another triangular-wave generator which requires fewer components is shown
in Figure 8-23(a). The generator consists of a comparator A I and an integrator A2.
The comparator A 1 compares the veltage at point P continuously with the inverting
input that is at O y. When the voltage at P goes slightly below or above O Y, the output
of A 1 is at the negative 9r positive saturation level, respectively.
To illustrate the circuit's operation, let us set the output of A 1 at positive satura-
tion + + +
v.. , (- Vee)- This V,.. is an input of the integrator A2. The output of A2,
therefore, will be a negative-going ramp. Thus one end of the voltage divider R2-R3

Vo'
Jl.I1_
R, c,
I 10 k.n 0.05µF
I
p
R3
40 kil ( 50 kil pot)

to
I
D2
,I 1N4735
V2=6.2V
Vo
NV
R2 10 k.n I
-VEE
~ -15 V
(al
Voltage
+v .. , = +T4 V
+V R•mp = 3.5 V
OV k=--+-'7"'~-11--~....,.-+---- time
-VRamp = -3.5 V
--~~~T~~~-- 0.5ms
(bl
Figure 8-23 Triangular wave generator. (a) Circuit. (b) Its waveforms. A 1 and
A2 dual op-ampr 1458/353.
is the positive saturation voltage + V,&l of A 1 and the other is the negative-going ramp
of A2• When the negative-going ramp attains a certain value - VRamp, point Pis slightly
below O V; hence the output of A 1 will switch from positive saturation to negative
saturation -V,,t (~ -VE£). This means that the output of A2 will now stop going
negatively and will begin to go positively. The output of A2 will continue to increase
until it reaches + VR.mp· At this time the point Pis 'Siightiy above O V; therefore, the
,
output of A1 is switched back to the positive saturation level + V,11• The sequence
then repeats. The output waveform is as shown in Figure 8-23(b).
The frequency of the square wave and the triangular wave is the same. The
amplitude of the square wave is a function of the de supply voltages. However, a
desired amplitude can be obtained by using appropriate zeners at the output of A I
[see Figure 8-23(a)].
Sec. 8-16 Triangular-Wave Generator 319

The 'amplitude and the frequency of the triangular wave can be determined as
follows:
From Figure 8-23(b), when the output of the comparator A1 is+ v.. 0.the output
of the integrator A2 steadily decreases until it reaches - VRamp· At this time the output
of Al switches from+ Vm to - V,w Just before this switching occurs, the voltage at
point P ( -l-input) is O V. This means that the - VR,mp must be developed across R2,
and + V,u must be developed across R3• That is,
or
- VRamp = -;: ( + v.. 1) (8-28a)
Similarly, + VR,mp, the output voltage of A2 at which the output of Al switches from
- v.• 1 to + v.. 0 is given by
+ VR,mp = - RR: (-V,u) (8-28b)
Thus, from Equations (8-28a) and (8-28b), the peak-to-peak (pp) output amplitude of
· the triangular wave is
vo(pp) = + VR,mp - (- v~,mp)
= (2)RR2 (V .. 1) p,;'.:,·t , ..
~~ -··~r·. !·: • (8-29)
3 ./
where v.. 1 = I + v,.1 I = I . .:. . v,.1 I- Equation (8-29) indicates that the amplitude. of
the triangular wave decreases with an increase in R3•
The time it takes for the output waveform to swing from - VR,mp to + VR,mp
(or from+ VR,mp to - VR,mp) is equal to half the time period T/2. [see Figure 8-23(b)].
This time can be calculated from the integrator output Equation (7-23) by substituting
v, = -V..1 and Vo= vo(pp):
C). vo(pp) = - R }C J.T/2 -i "I
·-::, I I o
( .. V1,1) dt :::.- \, t :: \,I<:,·.
l
<z.-23)
1.
= (;:·c) ( r) ·
Hence
I_ - vo(pp) (R C)
2 - Vut I I
or
(8-30a)
where v.• 1 =I+ V,.1 I= I -V,.1 I· Suestituting the value of vo(pp) from Equation
(8-29), the time period of the triangular wave is .
(8-30b)
The frequency of oscillation then is
J.0
= R3 (8-30c)
4R1C1R2

Equation (8-30c) shows that the frequency of oscillation!., increases with an increase
in R3•
The triangular-wave generator is designed for a desired amplitude and frequency
/0 by using Equations (8-29) and (8-30c).
Example 8-16
Design the triangular-wave generator of Figure 8-23 so that fa = 2 kHz and vo(pp)
= 7 V. The op-amp is a 1458/772 and supply voltages = ±15 V.
Solution. For the 1458, v.. t = 14
I
V. Therefore, from Equation (8-29),
R2 7
R3 = (2)(14)
R2 =~3
Let R2 = 10 ill; then R3 = 40 ill. (Use a 50-ill potentiometer.)

Now, from Equation (8-30c),
40 ill
2 kHz= (4)(R1 C1)(10kO)
Therefore, R1 C1 = 0.5 ms. Let C1 = 0.05 µF; then R1 = 10 ill. Thus R1 = R2 =

10 ill, C1 = 0.05µF, and R3 = 40 ill (50 ill potentiometer) [see Figure 8-23 (a)].
8-17 SAWTOOTH-WAVE GENERATOR
The difference between the triangular and sawtooth waveforms is that the rise time of
· the triangular wave is always equal to its fall time. That is, the same amount of time
is required for the triangular wave to swing from - VRamp to + VRamp as from + VRamp
to -VRamp [see Figure 8-23(b)]. On the other hand, the sawtooth waveform has
unequal rise and fall times. That is, it may rise positively many times faster than it
falls negatively, or vice versa. The triangular-wave generator of Figure 8-23(a) can be
converted into a sawtooth-wave generator by simply connecting a potentiometer to
the noninverting input terminal of the integrator A2• The resultant circuit is shown
in Figure 8-24(a). Depending on the R4 setting, a certain de level is inserted in the
output of A2• Now, suppose that the output of A1 is a square wave and the potentio-
. meter R4 is adjusted for a certain de levei. This means that the output of A2 will be a
triangular wave, riding on some de level that is a function of R4 setting. The duty
cycle of the square wave will be determined by the polarity and amplitude of this de
level. A duty cycle less than 50% will then cause the output of A2 to be a sawtooth
[see Figure 8-24(b)]. With the wiper at the center of R,, the output of A2 is a triangular
wave. For any other position of R4 wiper, the output is a sawtooth waveform. Speci-
fically, as the R, wiper is moved toward - VEE, the rise time of the sawtooth wave
becomes longer than the fall·time, as shown in Figure 8-24(b). On the other hand, as
the wiper is moved toward + Vee, the .fall time becomes longer than the rise time.
Also the frequency of the sawtooth wave decreases as R4 is adjusted toward + Vee
or -VEE. However, the amplitude of the sawtooth wave is independent of the R4
setting.
Sec. 8-17 Sawtooth-Wave Generator 321

v~JLfl
I 10 kfl 0.05 µF
I
40 kfl (50-kfl pot.)

:::
I
I
I
~ R4
+Vee_..,___, -Vee
Duty cycle
adjust
(a)
Voltage
-+-•~1
•-T----j
time
Fall
time
(bl
Figure 8-24 Sawtooth-wave generator. (a) Circuit. A 1 and A2 dual op-amp:

1458/353. D1 and D2: IN4735 with V= = 6.2 Y. (b) Output waveform when
noninverting input of A2 is at some negative de level.
8-18 VOLTAGE-CONTROLLED OSCILLATOR
In all the preceding oscillators, the freq,uency is determined by the RC time constant.
However, there are applications, such as frequency modulation (FM), tone generators,
and frequency shift keying (FSK), where the frequency needs to be controlled by means
of an input voltage called control voltage. This function is achieved in the voltage-
controlled oscillator (VCO), also called a voltage-to-frequency converter. A typical
example is the Signetics NE/SE 566 VCO, which provides simultaneous square-wave
and triangular-wave outputs as a function of input voltage. Figure 8-25(b) is a block

+v
6 8
Modulation
Ground 8 +V inp~t Current Scmitt Buffer
5 sources trigger amplifier 3
NC 2 7 c,
NE/SE 566
Square-wave vco
output 3 6 R1
Buffer
amplifier 4
Triangle-wave · Modulation
output 4 5 input
7
(a)
(b)
+V
R1
0.001 µF ~
.Su; +8
Modulating
input
Ci
6 8 -
c. 0-
:, >
c. -
5
+6
+4
4 M/1. 0
~c Ve "E +12
5 0
~ +10
M
c +8
3 c.
7 5 +6
9-
:, +4
0
C1
time
(d)
2(+V-Vc)
fo :!
R1C1 (+V)
where :! ( + V) $ V c ~ ( + V)
4
and 2 kn < R 1 < 20 kn
(c)
Figure 8-25 Voltage-controlled oscillator 566. (a) Pin configuration. (b) Block diagram.
(c) Typical connection diagram. (d) Output waveforms. (Courtesy of Signetics Corpora-
tion.)
323
diagram of the 566. The frequency of oscillation is determined by an external resistor
R1 a.id capacitor C1, and the voltage Ve applied to the control terminal 5 [see Figure
~.25(c)]. The triangular wave is generated by alternately charging the external capac-
itor C1 by one current source and then linearly discharging it by another [see Figure
8-25(b)]. The charge-discharge levels are determined by Schmitt trigger action. The
Schmitt trigger also provides the square-wave output .. Both the output waveforms are
buffered so that the output impedance of each is 50 n. The typical amplitude of the
triangular wave is 2.4.V pp and that of the square wave 5.4 V pp.
Figure 8-25(c) is a typical connection diagram. In this arrangement, the RIC I
combination determines the. free-running frequency, and the control voltage "Ye at
terminal 5 is set by the voltage divider formed with R2 and R3• The initial voltage Ve
at terminal 5 must be in the range
! (+ V) < Ve < +V (8-3la)
where + V is the total supply voltage. The modulating signal is ac coupled with the
capacitor C and must be < 3 V pp. The frequency of the output waveforms is
approximated by
(8-3lb)
where 'E.1 should be in the range 2 kn< R1 < 20 kn. For a fixed Ve and constant
C1, the frequency la can be varied over a 10: 1 frequency range by the choice of R1
between 2 and 20 kn. Similarly, for a constant R1C1 product, the frequency la can
be modulated over a 10: 1 range by the control voltage Ve, In either case the maximum
output frequency is 1 MHz. A small capacitor 0.001 µF should be connected between
pins 5 and 6 to eliminate possible oscillations in the control current source.
If the VCO is to be used to drive standard logic circuitry, a dual supply of ±5 V
is recommended so that the square-wave output has the proper de levels for logic
circuitry.
The VCO is commonly used in converting low-frequency signals such as electro-
encephalograms (EEG) or electrocardiograms (EKG) into an audio-frequency range.
These audio signals can then be transmitted over telephone lines or two-way radio
communication for diagnostic purposes or can be recorded on a magnetic tape for
documentation or further reference. For more information on the VCO applications,
refer to Section 10-4.
Example 8-17
In the circuit of Figure 8-25(c), + V = 12 V, R2 = 1.5 ill, R1 = R3 = 10 ill, and
C1 = 0.001 µF.
(a) Determine the nominal frequency of the output waveforms.
(b) Compute the modulation in the output frequencies if Ve is varied between 9.5 and
11.5 v. 1 ·. .
(c) Draw the square-wave output waveform if the modulating input is a sine wave,
Solution
(a) Using the voltage-divider rules, the initial control voltage Ve at terminal 5 is
V. = (lO kQ)(l2) = 10 43 V
c ll.5k!l .

Voltage
Voltage I
- --- - - ... ...
time
... - .... - .... - Figure 8-26 Input and Output

waveforms for Example 8-17.
From Equation (8-31b), the approximate nominal frequency / is 0
,..., (2)(12 - 10.43)

f. = (l04)(10-9)(12) = 26.17 kHz
(b) The modulation in the output frequencies can be calculated from Equation (8-3lb)
by substituting for Ve, first 9.5 V and then 11.5 V, as follows:
,..., (2)(12 -e- 9.5)
f. = (l04)(l0-9)(l2) = 41.67 kHz
,..., (2)(12 - U.5)
f. = (104)(10-9)(l2) = 8.33 kHz
Thus the change in the output frequencies is
41.67 kHz - 8.33 kHz = 33.34 kHz
(c) During the positive half-cycle of the sine-wave input, the control voltage Ve will
increase. Therefore, according to Equation (8-3lb) the frequency of the output wave-
form will decrease and the time period will increase. Exactly the opposite action wili
take place during the negative half-cycle of the input, as shown in Figure 8-26.
SUMMARY
1. A filter is often a frequency selective circuit that passes a specified band of frequencies
and attenuates signals of frequencies outside this band.
2. Filters may be classified in a number of ways: analog or digital, passive or active, audio
or radio frequency. ·
3. The most commonly used filters are the following:
(a) Low-pass filter
(b) High-pass filter
(c) Band-pass filter
(d) Band-reject filter
(e) All-pass filter
Chap.8 Summary 326

A low-pass filter has a constant gain from O Hz to a certain frequency called the cutoff
frequency IH, at which the gain is down by 3 dB. Above IH, the·gain decreases with an
increase in frequency. On the other hand, a high-pass filter passes all the frequencies
above a certain frequency called the low cutoff frequency IL· The upper cutoff frequency
of the high-pass filter, however, depends on the bandwidth of the op-amp. A band-pass
filter has a passband between two. cutoff frequencies IH and IL such that IH > IL· Any
input frequency outside this passband is attenuated. The band-reject filter performs
exactly opposite to the band-pass, in that it has a stopband between two cutoff frequencies
IH and IL· Finally, the all-pass filter has input and output amplitudes equal at all frequen-
cies; however, the phase shift between the two is a function of frequency.
4. The order of the filter indicates the rate at which the gain changes while the input fre-
quency is approaching or exceeding the cutoff frequency of the filter. For example, in
the first-order low-pass filter, for I> IH, the gain decreases at the rate of 20 dB/decade,
whereas in the first-order high-pass filter the gain increases at the rate of 20 dB/decade
until I= IL· Similarly, in the second-order filter the change in the rate of the gain is
40 dB/decade, in the third-order 60 dB/decade, and so on.
5. In order to convert a low-pass filter into a high-pass filter or vice versa, simply inter-
change frequency-determining components that is, resistors and capacitors.
6. Higher-order filters can be formed by simply using first- and second-order filters. For
example, a third-order filter is constructed by cascading a first- and second-order filters;
a fourth-order is formed by cascading two second-order filters; and so on.
7. There are two types of band-pass filters: wide band pass and narrow band pass. A wide
band-pass filter can be formed simply by cascading high-pass and low-pass sections.
On the other hand, the multiple-feedback filter is one of the narrow band-pass filters.
8. As with band-pass filters, band-reject filters can be either a wide band-reject or narrow
band-reject. The wide band-reject filter is formed using a high-pass filter, a low-pass
filter, and a summing amplifier. The outputs of low-pass and high-pass filters are added
together through a summing amplifier. The narrow band-reject filter, often called the
notch filter, uses the twin-T network. It is usually used for the rejection of a single fre-
quency such as 60-Hz power line frequency hum.
9. The all-pass filter does just what its name suggests. It provides unity gain with predictable
phase shifts for different input frequencies.
10. Basically, the function of an oscillator is to generate alternating current or voltage
waveforms. Oscillators are classified according to the type of components used, the fre-
quency of oscillation, and the type of waveform generated. There are two requirements
for oscillation:
(a) The magnitude of the loop gain A.B must be greater than or equal to 1.
(b) The total phase shift of the loop gain must be 0°.
The Wien bridge, the phase shift, and the quadrature oscillators are the most commonly
used sinusoidal oscillatoss, In all these oscillators the frequency of oscillation is a func-
tion of the RC time constant.
11. A square-wave output waveform i~ generated if the output of the op-amp is forced to
swing repetitively between positive and negative saturation. One way to obtain the
triangular wave is to integrate the square wave. Therefore, the triangular-wave generator
can be formed by using a comparator and an integrator.
12. The sawtooth waveform has a rise time many times longer than the fall time, or vice versa.
The triangular-wave generator using a comparator and an integrator can be converted to
obtain a sawtooth waveform.

13. The oscillator whose output frequency depends on the amplitude of the input voltage is
called a voltage-controlled oscillator (VCO) or voltage-to-frequency (Y/F) converter.
The YCO is used in phase-locked-loop circuits and for frequency modulation (FM),
among other things.
QUESTIONS
8-1. '
Define a filter. How are the filters classified?
8-2. List the most commonly used filters.
8-3. What is a passband and a stop band for a filter?
8-4. What are the advantages of active filters over passive ones?
8-5. What is the Butterworth response?
8-6. What is an all-pass filter? Where and why is it needed?
8-7. Define an oscillator.
8-8. What are the two requirements for oscillation?
8-9. How are oscillators classified?
8-10. What is frequency stability? Explain its significance.
8-11. What is the difference between the sawtooth wave and the triangular wave?
8-12. In the sawtooth generator of Figure 8-24(a), how does the potentiometer R4 affect the
frequency and amplitude of the output waveform?
8-13. What is YCO? Give two applications that require VCO.
PROBLEMS
8-1. Design a first-order low-pass filter so that it has a cutoff frequency of 2 kHz and a pass-
band gain of 1.
8-2. Convert the 2 kHz low-pass filter of Problem 8-1 to a cutoff frequency of 3 kHz.
8-3. Obtain the frequency response data similar to that in Table 8-1 for the filter of Problem
8-1. Construct the frequency response plot from this data.
8-4. Design a second-order low-pass filter at a cutoff frequency of 1.2 kHz.
8-5. Design a first-order high-pass filter at a cutoff frequency of 400 Hz and a passband gain
of 1.
8-6. Obtain the frequency response data similar to that in Table 8-3 for the filter of Problem
8-5. Construct the frequency response plot from the data.
8-7. In the circuit of Figure 8-8, C2 = C3 = 0.047 µF, R2 = R3 = 3.3 kn, R1 = 27 ill,
and Rp = 15.8 ill.
(a) Determine the low cutoff frequency IL of the filter.
(b) Obtain the frequency response data and draw the frequency response plot for the
filter.
8-8. Design a wide band-pass filter with IL = 400 Hz, IH = 2 kHz, and a passband gain
= 4. Also draw an approximate frequency response plot for the filter.
Chap.8 Problems 327
'
I
L
8-9. (a) Design a narrow band-pass filter so that Jc = 2 kHz, Q = 20, ·and Ap = 10.
(b) Change the center frequency Jc to 1 kHz, keeping gain and bandwidth constant.
8-10. Design 'a wide band-reject filter using first-order high-pass and low-pass filters having
!L = 2 kHz and !H = 400 Hz, respectively.
8-11. Design a 400-Hz active notch filter.
8-12. For the all-pass filter of Figure 8-16(a), determine the phase shift</> between the input
and output at f = 2 kHz. To obtain a positive phase shift </>, what modifications are
necessary in the circuit?
8-13. Design a phase shift oscillator so that fa = 1 kHz.
8-14. Design a Wien bridge oscillator that will oscillate at 2 kHz.
8-15. In the circuit of Figure 8-20, R1 = R2 = R3 = 82 kn and C, = C2 = CJ = 0.05 µF.
Determine the frequency of oscillation.
8-16. In the square-wave generator of Figure 8-21(a), if R1 = 12 kn, R2 = 13.92 kn, R =
100 kn, and C = 0.01 µF, what is the frequency of oscillation?
8-17. Design an integrator that can be used with the signal generator of Problem 8-16 so
that the combination can be used as a triangular-wave generator.
8-18. In the triangular-wave generator of Figure 8-23(a), R2 = 1.2 kn, R3 = 6.8 kn, R1 =
120 kn, and C1 = O.ot µF. Detefmine (a) the peak-to-peak output amplitude of the
triangular wave and (b} the frequency of the triangular wave.
8-19. For the VCO of Figure 8-25(c), determine the change in output frequency if Ve is varied
between 9 V and 11 V. Assume that + V = 12 V, R2 = 15 kn, R3 = 100 kn, R1 = ·
6.8_kn, and C1 = 75 pF.
8-20. In the VCO of Figure 8-25(c), if + V = 15 V, Ve = 13 V, and C1 = 0.0068 µF,
determine the approximate change in output frequency if R1 is varied from 4 kn to
18 kn.
EXPERIMENT 8-1
FIRST-ORDER LOW-PASS AND HIGH-PASS FILTERS
Objectives
In this experiment you will verify the operation of first-order low-pass and high-pass
filters. At the end of this experiment you should be able to:
I. Explain the difference between the low-pass and high-pass filters.

2. Construct a frequency response plot for the low-pass andhigh-pass filters from
the experimental data.
3. Discuss the differences between the theoretical and experimental results.
I
Equipment
1. Oscilloscope
2. Audio-signal generator
328 Active Filters end Oscillators Chap.8

Mate.rials
I. 741 or 351 op-amp
2. 3.3-ldl resistor
3. Two 10-ldl resistors
5. Semilog paper
Procedure ,
I. Connect the circuit as shown in Figure E8-l.1. Apply power to the circuit. Adjust
the input voltage v1n to 1 V peak to peak and the frequency to 100 Hz.
10 kn
+15 V
3.3 kn
-15 V
Figure ES-1.1 First-order low-pass

filter. (Pin numbers ref~r to the 8-pin
mini DIP.)
2. Using the oscilloscope, measure the output voltage and enter the measured
value in Table E8-l .1. ·
TABLE E8-1.1 DATA FOR LOW-PASS FILTER
Frequency (Hz) Vo pp (Y) 11o/11in 20 log 110/111n
1. 100 ·
2. 300
3. 700
4. 1,000
5. 2,000
6. 5,000
7. 8,000
8. 10,000
3. Vary the generators frequency and complete Table E8-l.1.

4. Calculate the cutoff frequency f 8 and the passband gain using the following
equations:
1
!8 = 2nRC
passband gain in (dB)= 20 log ( 1 + ;:)

Exp. 8-1 First-Order Low-Pass and High-Pass Filters 3Z9
L
5. Interchange the resistor R with capacitor C. Adjust the input voltage v,n to I· V
pp and frequency to 100 Hz. Measure output voltage using the scope, and enter
the measured value in Table E8- I .2.
6. Vary the generator's frequency and complete Table E8-1.2.
TABLE ES-1.2 DATA FOR HIGH-PASS FILTER
Frequency (Hz) Va pp (V) Vo/V1n 20 log 110/111n
1. 100
2. 300
3. 700
4. 1,000
5. 2,000
6. 5,000
7. 8,000
8. 10,000
7. Calculate the cutoff frequency IL and the passband gain using the following
equations:
1
IL= 21tRC
passband gain (dB)= 20 log ( 1 + ~:)

8. Construct the frequency versus voltage gain (in dB) plot for the low-pass filter
using the data of Table E8-l.1. Similarly, construct the frequency response plot
for the high-pass filter using the data of Table £8-1.2. Remember that the fre-
quency is assigned a logarithmic scale while amplitude is assigned a linear scale.
From the graphs determine 3-dB frequencies/a and/L, respectively.
Questions
1. What is the difference between the low-pass and high-pass frequency response
~~? .
2. How do the theoretical cutoff frequencies of the low-pass and high-pass filters
compare to their corresponding experimental cutoff frequencies? If they differ
by more than 10 ~{. suggest causes.
EXPERIMENT 8-2
WIEN BRIDGE OSCILLATOR
Objective
In this experiment you will construct the Wien bridge oscillator and verify its opera-
tion. At the end of this experiment you should be able to:

1. Measure the outp:ut voltage amplitude and frequency using an oscilloscope.
2. Determine the effect of different RC combinations on the frequency of oscil-
lation.
3. Explain the use of zener diodes in limiting the output voltage amplitude.
Equipment
1. Oscilloscope
2. Digital multimeter
3. ± 15 V power supply
Materials
1. 741 or 351 op-amp
2. 1 N4735, 6.2-V zeners
3. Two 3.3-.kn resistors
5. tz-en resistor
6. Two 0.01-µF capacitors
Procedure
1. Connect the circuit as shown in Figure E8-2. l. Make sure that the resistance
RP (50-kn potentiometer) is set to approximately 20 kn.
01 *
I
1N4735
02'*1N4735
I
v
Figure ES-2.1 Wien bridge oscillator. (Pin numbers refer to the 8-pin mini DIP.)
Exp. 8-2 Wien Bridge Oscillator 331

2. Tum the de power on and measure the amplitude and frequency of the output
waveform using the oscilloscope. If the circuit fails to oscillate, gradually
increase the value of R, until the circuit starts oscillating. The output should be
a sustained sine-wave. Enter the measured values in Table E8-2. l.
3. Connect the two I N4735 zeners back to back between the output terminal of
the op-amp and ground, and again measure the output amplitude. Enter the
measured value in Table E8-2.l. The IN4735 are 6.2-V zeners.
TABLE E8-2.1
Output amplitude Frequency of the output

PP (V) waveform (Hz)
R c Without With Calculated

(kn) (µF) zeners zeners Measured lo = 0.159/RC
1. 10 0.05
2. 10 O.ot
3. 3.3 0.05
4. Replace the 0.05-µF capacitors with the 0.01-µF capacitors. Repeat steps 2 and
3. . .
5. Replace the IO-kn resistors with the 3.3-kn resistors and the 0.01-µF capacitors
with the 0.05-µF capacitors. Repeat steps 2 and 3.
6. Reduce the pot R, slowly until the oscillations stop; then disconnect the pot
and measure its value with the ohmmeter. The value .of the pot R, is = __ n.
Questions
1. How does the value of the RC combination affect the frequency of oscillation?
2. What is the difference in output amplitude with and without the zeners?
3. How can the output voltage swing be limited to ±5 V?
4. In step 6, when the value of R, was reduced, the oscillations stopped. Explain
why.
EXPERIMENT 8-3
SQUARE-WAVE, TRIANGULAR-WAVE, OR SAWTOOTH-WAVE
GENERATOR
Objectives
In this experiment you will verify the operation of square-, triangular-, and sawtooth-
wave generators. At the end of this experiment you should be able to:
1. Discuss the differences between the square, triangular, and sawtooth waveforms.

2. Explain the operation of the comparator.
3. Explain the operation of the integrator that converts a square wave into a
triangular wave.
4. Discuss the effect of external components on the frequency of oscillation.
Equipment
3. ± 15 V power supply
Materials
1. 1458 or 353 op-amp
2. Two "4.7-kfl resistors
3. Three 10-kfl resistors
4. 50-kfl potentiometer
5. I Mn potentiometer
7. Linear graph paper
Procedure
1. Connect the circuit as shown in Figure £8-3.1. Make sure that the R3 is set at
40 kn (4R2).
2. Apply the de power and monitor the output waveforms of A 1 and A2 using the
oscilloscope. Connect channel 1 and channel 2 of the scope to the output
terminals of A 1 and A2, respectively. Measure the amplitude and frequency of
the output waveforms. Enter the measured values in Table E8-3. l.
c,
0.05 µF
+15 V
-15 V
Figure ES-3.1 Square-, triangular or sawtooth-wave generator. (Pin numbers

refer to the 8-pin mini DIP.)
Exp. 8-3 Square-Wave, Triangular-Wave, or Sawtooth-Wave Generator 333

I
I
- I
TABLE E8-3.1
Square-wave Triangular-wave
R1 R3 output, v~ output, va
(kn) (kn)
Amplitude Frequency Amplitude Frequency
1. 10 40
2. 4.7 18.8
3. Draw the output waveforms using the same scale on the linear graph paper.
4. Switch the de power off; then change the value of R1 to 4.7 kn and reset the
value of R3 to 18.8 kQ (4R1).
5. Repeat steps 2 and 3.
6. Tum the de power off. Disconnect the noninverting terminal of A1 from ground.
Now connect one terminal of the 1-Mn potentiometer to the negative supply
(- VEE = -15 V), the other Jerminal to the positive supply, and the wiper to
the noninverting input terminal of A1.
7. Tum on the de power. Connect voltmeter between the noninverting terminal of
A2 and ground. Also connect channels 1 and 2 of the scope to the output
terminals of A1 and A2, respectively. Adjust the wiper in the 1-_Mn potentiometer
so that the voltage at the noninverting terminal of .A2 is -5 V. Measure the
amplitude and frequency of the output waveforms at this setting. Enter the
measured values in Table E8-3.2. Complete Table E8-3.2.
TABLE EB-3.2
Square-wave Sawtooth-wave
Voltage-at the output, Va output, tio
noninverting
terminal of A2 (V)
Amplitude Frequency Amplitude Frequency
1. -5
2. -10
3. +5
4. +10
8. When the voltage at the noninverting terminal is -10 V, draw the output wave-
forms on linear graph paper. Use the same scale for both the waveforms.
I
Questions
1. Is the amplitude and frequency of the square wave a function of R2 and R3

-values ?
2. How do the R1 and R3 values affect the amplitude and frequency of the triangle '
wave?
334 Active filters and Oscillators Chap. 8

3. Is there any difference in the amplitude and frequency of the square and
triangular waveforms for a fixed value of R2 and R3? Explain your answer.
4. What is the difference between the square-wave outputs in steps 3 and 8?
Explain why.
5. How does the voltage at the noninverting terminal of A2 affect 'the sawtooth
waveform?
6. What is the relationship between the rise times and fall times of the sawtooth
waveform when the voltage at the noninverting terminal is -5 V and +s V?
I
Exp. 8-3 Square-Wave, Triangular-Wave, or Sewtooth-Weve Generator 335
L
9
Comparators and Converters
9-1 INTRODUCTION
The amplifier, filter, and oscillator applications presented so far illustrate a fair
sampling of typical op-amp uses. However, op-amps are used in many other circuits,
where they are employed under specific names. Such functions include comparators,
detectors, limiters, and digital interface devices, namely, converters. In this chapter
we discuss comparators, limiters, detectors, and converters using a general-purpose
op-amp. To obtain far better performance, we shall also look at integrated circuits
designed specifically as comparators and converters.
A comparator, as its name implies, compares a signal voltage on one input of
an op-amp with a known voltage called the reference voltage on the other input. In its
simplest form, it is nothing more than an open-loop op-amp, with two analog inputs
and a· digital output; the output may be ( +) or ( - ) saturation voltage, depending on
which input is the larger. Comparators are used in circuits such as digital interfacing,
Schmitt triggers, discriminators, voltage-level detectors, and oscillators.
9-2 BASIC COMPARATOR
Figure 9-l(a) shows an op-amp used as a comparator. A fixed reference voltage v,.r
of l V is applied to the ( - ) input, and the other time-varying signal voltage v111 is
applied to the ( +) input. Because of this arrangement, the circuit is called the
noninverting comparator. When V1ti is less than vre t, the output voltage u; is at - Vm
336
Vo
+ RL
10 k!2
R -Vee
I
v,rl~
1 Vi-
(al
v,n v,n
VP VP
v,., = 1 V
ov ov
-v .. , = -1
I
-VP
I
I
-VP
I I I
Vo
lv,n > v.:

I
Vo
v,n
I
> v,;
I
I
'
+v .. , +v,..,
ov ov
-v .. , -v ...
v,n < vre:f v,n < V,01

(bl (cl
Figure 9-1 (a) Noninverting comparator and its input and output waveforms,
(b) If v,.r is positive. (c) If Vrer is negative.
(- - VEE) because the voltage at the (-) input is higher than that at the ( +) input.
On the other hand, when v111 is greater than V,.r, the (+)input becomes positive with
respect to the(-) input, and v0 goes to + V.. t( · + Vee). Thus v0 changes from
one saturation level to another whenever V1u - V,.,, as shownin Figure 9-J(b). In
Sec. 9-2 Basic Comparator 337
.. \.
short, the comparator is a type of analog-to-digital converter. At any given time the
v waveform shows whether v1n is greater or less than
0 vrer- The comparator is some-
times also called a voltage-level detector because for a desired value of v,.r, the
voltage level of the input v111 can be detected.
In Figure 9-J(a) the diodes DI and 02 protect the op-amp from damage due to
excessive input voltage Vin· Because of these diodes, the difference input voltage v14
of op-amp is clamped to either 0.7 V or -0.7 V; hence the diodes are called clamp
diodes. There are some op-amps with built-in input protection; in such op-amps the
input diodes D 1 and 02 are unnecessary. The resistance R in series with v1n is used to
limit the current through Dl and 02. To reduce offset problems, a resistance RoM ~
R is connected between(-) input and V,.r [see Figure 9-l(a)].
If the reference voltage V,.r is negative with respect to ground, with sinusoidal
signal applied to the ( +) input, the output waveform will be as shown in Figure
9-l(c). When Vin > Vror, Vo is at+ v.. t; on the other hand, when Vin < vre ,, Vo is at
- v.• t- Obviously, the amplitude of v10 must be large enough to pass through V,.r
if the switching action is to take place.
Figure 9-2(a) shows an inverting comparator in which the reference voltage V,.r
is _applied to the (+)input and v1n is applied to the(-) input. In this circuit, V,., is
obtained by using a 10-kO potentiometer which forms a voltage divider with the de
supply voltages + Vcc and - Vu and the wiper connected to the (+)input. As the
wiper is moved toward -VEE, v,.r becomes more negative, while if it is moved
toward + Vee, V,,r becomes more positive. Thus a V,., of a desired amplitude and
polarity can be obtained by simply adjusting the 10 kn potentiometer. With the
_sinusoidal input waveform, the output v0 has the waveform shown in Figure 9-2(b)
or (c), depending on whether V,0, is positive or negative, respectively.
9-3 ZERO-CROSSING DETECTOR
An immediate application of the comparator is the zero-crossing. detector or sine

wave-to-square wave converter. The basic comparator of Figure 9-l(a) or Figure 9-2(a)
can be used as the zero-crossing detector provided that V,.r is set to zero ( V,.c = 0 V).
Figure 9-3(a) shows the inverting comparator used as a zero-crossing detector. The
output voltage v0 waveform in Figure 9-3(b) shows when and in what direction an
input signal v10 crosses zero volts. That is, the output v0 is driven into negative satura-
tion when the.input signal '-'1.n passes through zero in the positive direction. Conversely,
when '-'1.n passes through zero in the negative direction,. the output v0 switches and
saturates positively.
In some applications, the input '-'1a may be a slowly changing waveform, that is,
a low-frequency signal. Therefore, it will take '-'m more time to cross O V; therefore,
t10 may not switch quickly from one saturation voltage to the other. On the other
hand, because of the noise at the op-amp's input terminals, the output v0 may fluctuate
between two saturation voltages + v.., and - V..0 detecting zero reference crossings
for noise voltages as well as t'1.n, Beith of these problems can be cured with the use of
regenerative or positive feedback that causes the output v0 to change faster and elimi-
nate any false output transitions due to noise signals at the input.
338 Comparators and Converters Chap. 9

+Vee
RP v.:
10 kfl
(a)
OV
+v,., ...__ __
-vO '-'
V --------------
-VP
+v.., ~
I
I
I I I
I +v.,
ov O V 1----4----"-----J.- t
-v.,
<, -:
-v., t,-----
v,n > v,..
(bl (c)
Figure 9-2 (a) Inverting comparator with input and output waveforms. (b) If
Yror is positive. (c) If V.. r is negative.
339
+
(al
I
+v..,
- .
ov -
-v ••
(bl
Figure 9-3 (a) z.ero-crosaina detector. (b) Its typical input and output
waveforms.
9-4 SCHMITTTRIGGER
Figure 9-4(a) shows an inverting comparator with positive feedback. This circuit con-
verts an irregular-shaped waveform to a square wave or pulse. The circuit is known as
the Schmitt trigger or squaring circuit. The input voltage 111a triggers (changes the
state of) the output e, every time it exceeds certain voltage levels called upper thresh-
old voltage v.. , and lower threshold voltage Vi., as shown in Figure 9-4(b).
340 Comparators and Converters Chap.9

+Vee
+15 V
{a)
VP=0.5 V
Vu1-=25mV
OV.....+~~~ ........ ~~~--.4-~~~~--
V11"' -25mV
-VP-= -0.5 V +v.,
r
Yo
I Hvsteresis
,. voltage
- (Vu,-V11)
ov
-V.•-14V
- {cl
{b)
Figure 9-4 (a) Inverting comparator as Schmitt trigger. (b) Input and output wave-
forms of Schmitt trigger. (c) f1o versus t11a plot of the hysteresis voltage.
In Figure 9-4(a), these threshold voltages are obtained by using the voltage
divider R1 - R2, where the voltage across R1 is fed back to the ( +) input. The
voltage across R1 is a variable reference 'threshold voltage which depends on the
value and polarity of the output voltage v0• When v0 = + V. • ., the voltage across
R1 is called the upper threshold voltage, Va,· The input voltage V1a must be slightly
Sec. 9-4 SchmittTrigger 341

more positive than Vut in order to cause the output v., to switch from + v.. t to - v.. r-
A S I ong as V1u < T/rut, v. !S
.
at.. ~ l/ Jot· !using
r .
,
1 ....... e-divid
tne iJ. ouage _,•I 4,' l
e.T" rue,
.,
1
R, ., .
Vut = --·--'~:-
,..., .)
a . ..,,
_1_ ~ \ 1 (9-la)
.\.'I..! , .!iz
On the other hand, when ·vr = - V,~·., the voltage across R.1 is referred to as
lower threshold voltage, V11. ·~'i.. must b: slightly more negative than Va in order to
cause v0 to switch from -V,.i to -+- 1,:,,. In other words, for v10 values greater than
Vi:. v, is at - Vnt· Va is given by the following equauon:
v.
I·
= __ {··~_;__
'/ •• + R,. r-v
~
°'
. .. ,. (9-lb)
Thus if the threshold (uiu3-~·: V,, f,n-: ,-1: ar., made larger tbm the input noise voltages
the positive feedback ,vi'.;. etiminat- he false output transitions. Besides that, the
positive feedback, l:-ec;,.;;;;~ cf its :·eg-:;!1-;fa .ive action, will make u; switch faster between
+ Vat and - V.,1· In Figure 9-:!{8). "t:::i:,t1:.nc.:. :<G;,r "- R.1 II Rz is used to minimize
the offset problems.
Figure 9-4(b) shows t;,2.:: ~h·,, o·,.tr.,•.1! of tk ~-,ehrr-.it.t trigger is a square wave when
the input is a sine v/ave. ~eca!l font"· ti!ightly i_liff,~rei:,t version of the Schmitt trigger is
used in the tria..1gular-w~v1.; and sawtooth-wave generators of Figures 8-23 and 8-24,
respectively. In these g~,1~·;·,1to;·:; .:,. l\Oui1r1•;::tir,g comparator is used as a Schmitt
trigger. When the input i;: ; ~.-:,·,.~ ~:;;la.,· v:=?t\ e. the output of the Schmitt trigger is a
square wev«, whereas if zhc input is ~. sawtooth \vavc, the output is a pulse waveform.
The comparator with positive feedback is said to exhibit hysteresis, a deadband
condition. That is, when the input of i.he comparator exceeds Vut, its output switches
from + V;n: to - V,~t and reverts oack to its original state, + Vw, when the input
goes below Vi, [see Figure 9-A(c::)]. The hysteresis voltage is, of course, equal to the
difference between Vu1 and v., Tberetore,
Vil:,• = ~/·u1 -·- }'n
(9-2)
Example 9-1
In the circuit of Fi.zu.r:;; 9~;_a), R; = 100 ;(l, Rz = :56 ill, v1,i = 1 V pp sine wave, and
the op-amp is type 741 with s1.1!,p1; volrages = ± 15 V. Determine the threshold volt-
ages Yut and Vii and draw the output waveform.
Soimren. For 741 the maximum output. ,;ohage swing is ±14 V, that is, + V.at =
14 V, and -V..a~ = -.M V. Frn,:1 Equations (9-la) and (9-lb),
- lCO,.
v·u~ = ,;- ·: ·10,g> = ·-,
.,o,_u i.) rn {
11
o mv
i'f'
T" 2"°
;-H ·-=-·~f6,100~---,.-,J·1 ~·
..i\•.:, ••
= -
T.b.e ,o,.,tput~0 :,P:i.vdom h 1-11·~·.:.rn In Figtrre 9-4(~). 'From Equation (9-2), the hysteresis
volm~ Yir1 = 30 m V,
Comperators and Converters Chap.9

9-5 COMPARATOR CHARACTERISTICS
The important characteristics of a comparator are these:
1. Speed of operation
2. Accuracy
3. Compatibility of output
The output of the comparator must' switch rapidly between saturation levels and
also respond instantly to any change of conditions at its inputs. This implies that
the bandwidth of the op-amp comparator must be rather wide; in fact, the wider the
bandwidth, the higher is the speed of operation. As discussed in Section 9-4, the speed
of operation of the comparator is improved with positive feedback (hysteresis).
The accuracy of the comparator depends on its voltage gain, common-mode
rejection ratio, input offsets, and thermal drifts. High voltage gain requires a smaller
difference voltage (hysteresis voltage) to cause the comparator's output voltage to
switch between saturation levels. 01,1 the other hand, a high CMRR helps to reject
the common-mode input voltages, such as noise, at the input terminals. Finally, to
minimize the offset problems, the input offset current and input offset voltage must
be negligible; also, the changes in these offsets due to temperature variations should be
very slight.
Since the comparator is a form of analog-to-digital converter, its output must
swing between two logic levels suitable for a certain logic family such as transistor-
transistor logic (ITL).
9-6 UMITATIONS OF OP-AMPS AS COMPARATORS
A general-purpose op-amp such ~s the 741 can be used in relatively less critical
comparator applications in which speed and accuracy are not major factors. As
illustrated in Section 9-4, with positive feedback (hysteresis), the switching speed of
the op-amp comparator can be improved and false transition due to noise can be
eliminated. Besides that, an offset voltage compensating network and offset minimiz-
ing resistor can be used to minimize offset problems. However, the output voltage
swing of an op-amp is relatively large because it is designed primarily as an amplifier.
In other words, the output of an op-amp comparator is generally not compatible
with a particular logic family such as the TTL, which requires input voltages of
either approximately +5 V or O V. Therefore, to keep the output voltage swing within
specific limits, op-amps are used with externally wired components such as zeners or
diodes. The resulting circuits, in which the outputs are limited to predetermined values,
are called limiters. The next section presents an analysis of typical limiters in order to
suggest other such possibilities ..
Sec. 9-6 Limitations of Op-Amps as Comparators 343

9-1 VOLTAGE LIMITERS
Several op-amp comparator circuits with output voltage limiting are shown in Figures
9-5 through 9-7. In the circuit of Figure 9-5(a), the zener diodes Di and D2 are con-
nected in the feedback path; this arrangement limits the positive and negative values
of the output voltage Va. When the input voltage v10 crosses O V and increases in the
positive direction, the output voltage Va increases in the negative direction until diode
Di is forward biased and D2 goes into avalanche conduction. Therefore, the maximum
+Vee
(a)
- I I
-(Vz + V01)
Figure 9-5 (a) Basic comparator with
positive and negative output voltage
limiting. (b) Its input and output
(bl waveforms.

negative value of v0 is equal to (Vz + VD1), where Vz = zener voltage and VD1 =
the voltage drop across theforward-biased zener D1 (= 0.7 V typically). On the other
hand, when Vin crosses O V and starts increasing in the negative direction, v0 starts
increasing positively until diode D2 is forward biased and D1 goes into avalanche
conduction. Thus the maximum positive v0 is equal to Vz +VD2, where Vz is the
zener voltage and VDl the voltage drop across the forward-biased zener D2 ( = 0. 7 V
typically). Thus the output voltage swing is limited to +(Vz + 0.7) and -(Vz +
0.7.)
[see Figure 9-5(b)].
Note that in the circuit of Figure 9-5(a), since the input terminals of the op-
amp are at virtual ground (v1 = v2 ~ 0 V), the input voltage Vin appears across R,
and v appears across D1 and D2• The resistance RoM is used to minimize offset
0
problems.
If there is a need to limit the swing of the output voltage v to a positive direction
0
only, a combination of zener and rectifier diodes is used as shown in the circuit of
Figure 9-6(a). When the .input voltage v1n crosses O V and increases in the positive
direction, the output voltage v0 is at - v.. ,. This happens because diode D2 is reverse
biased, causing the op-amp to operate in the open-loop configuration. However, when
v1n crosses O V and starts increasing in the negative direction, v0 starts increasing posi-
tively until D2 is forward biased and D1 goes into avalanche conduction. Therefore,
the maximum positive v0 = Vz + VD2 [see Figure 9-6(b)].
In the circuit of Figure 9-6(a), if the position of D1 and D2 diodes is inter-
Vin
VP
o, D2
av
-VP
+Vee
v.
v.
RL
-Vee
Jakn
RoM= R
Vz + Vo2
av
(al
-v ...
(bl
Figure 9-6 (a) Basic op-amp comparator with positive voltage limiting. (b) Its input
and waveforms.
Sec. 9- 7 Voltage Limiters

changed, the output voltage v0 will then be limited in a negative direction to -(Vz +
VD2), However, the maximum positive v0 = + v..t- .
Finally, if only a single zener is used in the feedback path of an op-amp as
shown in Figure 9-7(a), the output voltage v0 is limited to+ Vz and -VD, where Vz
in the zener voltage' and VD the voltage drop across the .Iorward-biesed zener
(= +0.7 V typically) [see Figure 9-7(b)]. The exact opposite result can be obtained by
reversing the direction of the zener diode. That is, v0 will be limited to - Vz and +VD·
Voltage limiters are commonly used in communications devices such as TV
and FM receivers. ·
Example 9-2
In the circuit of Figure 9-7(a), v1n = 500 mV peak 60-Hz sine wave, R = 100 n,
1N3826 zener with Vz = 5.1 V, and the supply voltages = ±15 V. Determine the out-
put voltage swing. Assume that the voltage drop across the forward-biased zener =
0.7V.
Solution. During the positive half cycle of the input waveform, the output voltage
would be at - VD = -0.7 V because the zener wlll be forward biased. However, during
the negative half cycle of v...,, v0 would be at + Vz = +5.1 V since the zener will be
reverse biased into zener breakdown. Thus, the use of a zener diode in the feedback
path limits v0 to +5.1 V and -0.7 V. This output voltage swing will, therefore, make
the op-amp comparator of Figure 9-7(a) compatible with TIL.
Vin
VP
R 0
.+ ov
+Vee
-VP
Yo
RoM"'
. A -VEE
RL
10k!l
Vo
v.
!al -Vo
(bl
Figure 9-7 (a) Basic op-amp comparator with positive and negative limiting. (b) Its input
and output waveforms.
Comparators and Converters Chap. 9

Although op-amps. can be usec, ·.L ,.;( !ip::1£·,,i.or~, specially designed comparators
1
outperform the op-amp types. T~1e :.;.r-:!t;ia:1:, ,.l;;s•g11Gc, devices are optimaized for the
most desirable parameters, such ,J.$ ::;!.Jf:ed and accuracy. Besides that, their output
is compatible with RTL DTL i'l'L, ;,;,;J i,F)S logic. A variety of integrated
comparators are avai.aoie, iw.:JL'.du:~ ::"[rf·1Ep•.ll, low-power, low-offset Voltage, high-
speed, and precision voltage (''Jti°'./'-r:... xrs The i11formation included on the com-
parator data sheers is identical ro iu.;1( nn ur-:.:imp Jam sheets in most cases. A typical
comparator d,rn~ sheet includes :, ,,·:·;i~i'1i ,J-·c:·.'fip;·;r,n ,A the device, a schematic dia-
gram, a connection diagram, ,tt°)~ L:~,- 1Mt;,::irn.l.!m n:,L,1gs, electrical characteristics,
typical performance curves, ·.:i,d ;:.;.:1=·ti,:atio,·:s. Electrical parameters such as response
time, positive output level, n;;g.c'?JJVt o:HiJ~E lever, s,!'O!J{; current, strobe release time,
and saturation voltage 2.n .ypical :Ji' s,:::;:;·.1)-"r;;orn. These parameters are defined as
follows. The response !i.'71'! is the in~~r.1d ·:,f. ·.we-.;11 the application of' an input step
function and the time when the ulltµ:rt ~ ,v'.'::,:;,:: t11,~ logic threshold voltage. The posi-
tive output level or output hi6h vohage i,~ the higi1 output voltage level with a given
load and the inp: ..rt drive equal to or g1.cate: thar, a specified value. The negative
output level or output low voltage is !b,~ nt!3;..dvt: de output voltage with the comparator
saturated by a differential ini.;:u~ ':..1.t11.,11 t~1 o: greater than a specified voltage. The
strobe current is the current out oT th~ strobe rerminal when it is at the zero logic
level. The strobe release time' is tht: time r,;:;q~i,.:;d for the output to rise to the logic
threshold voltage after the :;~r0b,c (:!~·minsl has been driven from zero to the one
logic level. 11..1e saturation :;<.,hat;2 is ti'ie low-output voltage level with the input drive
equal to or greater than a specified value, f·urthcrmo.re, parameters such as strobe
current and strobe release time. are only listed for comparators with strobe capability.
The µA31 l precision comparator is designed for low-level signal detection and
high-level output drive capability. It can operate from + 15· V op-amp supplies down
to the single +S-V supply 'Js;d for lC kigii:; In addition, its output can drive RTL,
DTL, TTL, and MOS logic, .~:1 weli as inmvs or relays. Outputs can also be wire
01too. The input slew rate can v.;; increased by increasing the input stage current.
· The µA3li ~s input offaei: vcHtt;.i t,;;Jan1~ing and TTL strobe capability [see Figure
9-8(a)]. The steobe capability ~now::, the compnrator's output to either respond to
input signals or be independent ,:J! ;.;,p;:~ ~ig.c~ls. The response time is typically 200 ns
for a 100.·mV input step ·;;:;ih 5·r.,.iY overdrive.
The µAF311 ic a FET illput comparator that b.as input currents (I,0 and /B)
more than 1000 times lower than for the µAJ 11. Except for this difference, the pAF311
has the same characteristics and features as the µA3 i 1.
As shown in Figure 9-8(b), tt-e U/l!lH4 has two totally separate comparators
with Independent strobe capability. Compared to the 3i1·s. it has lower response
"time (30 ns typical) at the expense <.'( h:.;her input currents.
The features of che ICL800l include Jo·.-, mpu: cm rents, low power consumption
(30 mW), arid 250 ns response time. An ourpuc stage enables the designer to control
the output voltage swing. That is, he positive output !evi:;t can be adjusted to suit a
desired logic family by changing V + [see Figure 9-8i:...:;j.
The µA760 is a high-speed di.Ierential voltage comparator with complementary
Sec. 9-8 High-Spoed and Precision-Tvpe Comparators 347

GND
Strobe
+Yee
+Vee
9
2 5
8
7
6
3 Balance/strobe -Vee
6
12
Balance TTL
Strobe
2N2222
1 kn 13
2
+Vee
Strobe
(al (bl
+Vee
+Vee
5 Input 2 4
11
13 .
Output 1
Output 2
10
7 Input 1
10 2
-VEE
(cl (di
Figure 9-8 Connection diagrams of comparators. (a) µA311: when not used,
strobe terminal (6) should either be open or connected to positive supply. (b)
LM1414: pin 4 NC. (c) ICL8001: pin connections shown arc for 14-pin DIP
package. (d) µA7W: pin connections shown arc for 14-pin DIP package.
TIL outputs. It bas a typical response time of 16 ns and operates from supplies of
±4.5 to ±6.5 V [see Figure 9-8(d)]. Its1typical applications are high-speed analog-to-
digital converters and zero-crossing detectors.
S-9 WINDOW DETECTOR

Sometimes there is a need to determine when an unknown input is between two
precise reference thresholds V.,, and Vi,. This determination can be made by a circuit
called the window detector. Figure 9-9(a).shows such a circuit using a dual comparator

+Vee
1 • 14 - -VEE
I
- ~ +Vee
2 13
12
-
-- 3
4
88
4115/04 11 - High
7, 11, 14 10
-
- 5 9 - Go
-
6
Strobe Low - 7 8 -
- Common
2N2222 -----.aTTL (b)

Strobe
lkn
(a)
r---------------------------,
I I
Upper limit 12 R, 101
input Vu,
l
I
,91 Go
Input
signal Yin
1 71
I
I
Low
03 I
81
Common
I
I
I I
L--------- -- - -- - -- - -- -- -- - __ .J
(cl
vu, <v.., vii <v.., «v .. Y111<V11

High On Off •Off
Go Off On Off
Low Off Off On
(d.
Figure 9-9 (a) Window detector usin1 LM1414. 11le BB 4415/04 window detector. (b) Pin
diagram. (c) Block diqram. (d) Transfer charactcriatica.(Courtesy of Burr-Brown Research
Corp.)
349
LM 1414. An unknown voltage v1n is applied to the(-) input of comparator C1
Ct LM 1414) and to the (+)input of comparator C2 (remaining t LM1414). An
upper threshold voltage Vut is applied to the (+)input of C1, whereas the lower
threshold voltage Va is connected to the ( - ) input of C2• In addition, the outputs
of CI and C2 are connected to form a single output v When v1n is between Vu, and
0•
Vil, the output v is high. However, when v,n goes above Vut or drops below Vi,, the
0
output v switches low or to O V. As a visual aid an appropriate lamp circuit may be

0
connected at the output of the comparator. The window detector can also be "strobed"
when needed. Window detectors are usually used in industrial alarms, level detectors
and controls, digital computers, and production-line testing.
The Burr-Brown 4115/04 is a hybrid JC window detector that is available in
a 14-pin double-width DIP. Figure 9-9(b) and (c) show the pin diagram and block
diagram of the 4115/04. As shown in Figure 9-9(c), the inputs are diode protected
and the value of the input voltages can be as high as ± 15 V. The device has three
mutually exclusive outputs, HIGH, LOW, and GO, and sinks up to 200 mA of cur-
rent when an output is on. The required power supply voltages are ± 15 V while the
maximum load supply voltage + VL can be up to +30 V. For proper operation of
the device, separate connections should be made from each power supply common
( + Vee, - VEE, and + VL) to the device common, that is, pin 8. The 4115/04 is designed
to drive TTL and DTL logic devices as well as lamps and relays.
9-10 VOLTAGE-TO-FREQUENCY AND FREQlJENCY-TO-VOLTAGE

CONVERTERS
The SE/NE 566 voltage-to-frequency converter is discussed in Section 8-18. This

section investigates the Teledyne 9400 series, which can be used as voltage-to-
frequency (V/F) or frequency-to-voltage (F/V) converters. The series includes the
9400, 9401, and 9402 converters. These converters have the same 'internal circuitry
and connection diagrams, but they differ slightly in electrical characteristics. A com-
plete V/F or F/V system can be formed simply by using two external capacitors, three
resistors, and a reference voltage. In addition, the 9400 series consists of CMOS and
bipolar devices that can operate on dual or single supply voltages.
9-10.1 VJF Convener
The 9400 is designed for pulse- and square-wave outputs having a frequency range of
1 Hz to 100 kHz. Furthermore, the input can be either current or voltage, and the
output can interface with most forms of logic. When it is used as a V/F converter,
the equivalent circuit (inside the dashed box) and connection diagram of the 9400 is
as shown in Figure 9-10. The equivalent circuit consists of an integrator, comparators,
a delay network, a divide-by-2 netwotk, and open-collector output transistors. The
input current /b = V1r,/R1n is converted to a charge by the integrating capacitor C1.n,
and shows up as a linearly decreasing voltage VA at the output of the op-amp
integrator, as shown in Figure 9-IO(b). In equation form,
l: i.)t
VA= -(1c..,, (9-3)

+5V
+5 V
,-----------
v 00 1 ---------,
14
I la
6
Ve 3 µs Ve,
GND delay +SV
Comp in
111
RL
I io xn
I 110
I
I v
( F20
-2.5 I
I ----, -:-2
I
I I
I
I I I
I 9
Amp I
I
out 121
I Output
-5 V v.;
v,ef
7
,-- I
_ _J
common
out 51
I
--------"---
s,
I
I
I
-, I
c.; I I
2~ I
c,., I I
Input I 5:i L _________ I
_J
0-10 V I
v: R,n 31
-1 I'"
1 Mn '"
+5 V
Offset I
Rb 21
R•"">-oO>---'oAJv.---,__ _ ___.._ ___, !
!
SOKH I I
___________ _J
-5v 1R0Kn L R---- 4
( I b1u
b,as 100 Kn
Offset adjust
/
-5V
(a)
Figure 9-10 (a) 9400 V/F converter equivalent circuit and connection diagram. (b) Its
waveforms. (Courtesy of Teledyne Semiconductor.)
where J,n = input current (amperes)

C1nt = integrating capacitor (farads)
t = time (seconds) ·
Sec. 9-10 Voltage-to-Frequency and Frequencv-to-Voltaqe Converters 351

v ..,
VA
-1
c.;
Opampoo~::,, ov _ ,~......
~
I
~ ~,
~ .. t
w
I
I .
4
ov0!- -11
r-3µs
Comparator
output
Ve
lI L v~t.
I 1
+J 4--3 µs
I I
3 µs delay ::: 5 v I
circuit -
output ov
Ve1
Pulse frequency
sv
output V .___,_._ __ __, ..... __ ........-.. ~
O
F0 f+T~
Divide-by-2 ;;;. 5
output V .,_
Vl .__ ., t
O
Ve2
t
-----2T---
dl!f 2 : : t. __. __ . ._ .,
Frequency
(b)
Figure 9-10 (cont.)
The output VA of the integrator is sensed by the comparator: The output of the
comparator is then applied via the 3 µs delay network to the output transistor Q1,
the divide-by-2 network, and the C,0c charge/discharge control circuit.' The output
of the divide-by-2 network drives the <>ptput transistor Q2• When the output VA of the
op-amp is positive, the output Ve of the noninverting comparator is high, or - + 5 V,
and the output Vs, of the 3 µs delay network is low or O V. Since Vs, is low, the
transistor Q, is off, and the output F0 is high, or - + 5 V [see Figure 9-IO(b)]. The
divide-by-two network is a negative-edge-triggered flip-flop whose output voltage
Va1 is a complement (inversion) of Vs,; hence the transistor Q2 will be on, and output
F0/2 will be low. Finally, with Vs1 low, the C,.c charge/discharge control circuit is

disabled, and capacitor C,.r remains discharged (is shorted out). However, from
Equation (9-3), the output VA of the op-amp is linearly decreasing. Therefore, when
VA goes slightly below O V, the output Ve of the comparator switches "low" to O V.
Three microseconds after Ve goes low, VB, switches from low to high. This forces
output F0 low and enables the C,.r charge/discharge control circuit which connects
C,.r to the reference voltage v,.r of -5 V. At this instant the negative voltage at the
( - ) input causes the output of the op-amp to step up to a finite amount, as shown in
Figure 9-IO(b). The reference capacitor C,.r remains connected to V,.r for a time
period long enough to virtually charge it to V,.r· The charging path for C,.r is through
the output terminal of the op-amp, through C;nt, through C,.r, and finally through
the negative reference voltage. Now, since the output of the op-amp VA is positive, the
output of the comparator switches from low to high, and 3 µs later VB, goes low.
This disables the c,.r charge/discharge control circuit, and c,.r is shorted out,
dissipating the stroed reference charge. When VB, goes low, the output F0 goes high,
the output of the divide-by-2 circuit goes low, and output F0/2 therefore goes high
[see Figure 9-IO(b)]. The integrating capacitor C1n, a.gain begins converting the input
current /1n to a charge, and in tum the eutput of the op-amp starts decreasing linearly
[see Equation (9-3)]. When the output of the op-amp goes slightly below O V, the
output of the comparator goes from high to low, and hence the cycle repeats. In short,
the continued discharging of C1n1 by· the input current 11.. is balanced out by fixed
charge from V,.r· As the input voltage V; .. is increased, the rate of decrease of output
voltage VA also increases [see Equation (9-3)], causing output frequency F0 to also
increase. Since each positive voltage increment in VA is fixed, the increase in frequency
with voltage is linear.
As shown in Figure 9-lO(a), the 9400 contains a "self-start" circuit that assures
proper V/F operation when power is first applied. If the op-amp output VA is below
the comparator threshold of O V and C,.r is already charged, then when the power is
first applied, a positive voltage step will not occur. In this situation the output VA
of the op-amp continues to decrease until it crosses the -2.5 V threshold of the "self-
start" comparator. When this happens, the self-start comparator connects through
the 20-kn resistor a negative supply voltage Vss to the (-) input of the op-amp,
which in tum causes the output of the op-amp to quickly go positive. As soon as VA
goes positive, the self-start comparator is disabled, and the 9400 resumes its normal
operating mode.
The 9400 is a 14-pin DIP with plastic and ceramic options. The pin diagram is
shown in Figure 9-11. The functions of these pins are as follows:
Pin I I: Cotparator input. This pin is the (+)input of the comparator and is
connected to the output of the op-amp in the V/F mode. In the F/V mode,
the input frequency is applied to the comparator input.
Pin 8: Pulse frequency- output. At this pin a pulse waveform output is avail-
able whose frequency is proportional to the input voltage. Since this is an open-
collector output,' it requires a pull-up resistor and interfaces directly with all
forms of logic.
Pin JO: Frequency divide-by-T output. This pin provides a square-wave output
which is one-half the frequency of the pulse output at pin 8. This output is an
Sec. 9-1 O Voltage-to-Frequency and Frequency-to-Voltage Converters 353

I bios 14 Yoo
Zero adjust 2 13 NC
Iin 3 12 Amplifier output
Vss 4 9400 11 Comparator in

Fo
V,., out 5 10 output
2
GND 6 9 Common
v.: 7 8 Pulse F O output

Figu'"\~-11 Pin diagram for the 9400.
"
open collector and hence requires a pull-up resistor. It is also compatible with
all logic families. ·
Pin 9: Output common. The emitters of both the output transistors are con-
nected to this pin. A unipolar or bipolar output voltage swing can be obtained
by connecting this pin either to ground or to the negative supply Vss, respec-
tively. For high-performance applications, the output ground (pin 9) should be
separated from the input ground (pin 6).
Pin I: h1 ... A resistance Rbiu is connected between pin 1 and pin 4. Specifica-
tions for the 9400 are based on Rbi•• = 100 kQ ± 10%.
Pin 12: Amplifier out. This is the output of the op-amp which is a negative-
going ramp signal in the V /F mode. In the F /V mode, a voltage proprotional
to the frequency input is generated at this pin.
Pin 2: Zero adjust'. The circuit that can be used to reduce the output initially
to zero is connected to this pin. This low-frequency set point is determined by
adjusting the voltage at this pin,
Pin 3: /10• This pin is the ( - ) input of the op-amp, and the input current /10
is applied to it. /10 is 10 µA for nominal full scale with an over-range current
up to 50 µA.
Pin 7: Vr.r· A reference voltage from either a separate negative supply or the
Vss may be applied to this pin.
Pin 5: Vr.r OUT. When Crer is to be charged, the Cr.r charge/discharge
control circuit connects this pin to the reference voltage Vr.r (pin 7).
Pin 13: NC. No connection.
Pin 6: GND. Input ground.
I
9-10.1 (a) V/F design procedure. The output frequency F of the 9400 0
V/F converter is related to the analog input voltage V1a by the equation
F = V lD O
I (9-4)
R1n (V ..rXC..r)
The V/F converter shown in Figure 9-12 can be designed by using the following
steps:
354 Comparatorsand Converters Chap. 9

-5 V +5 V
Vss
Rb;as Voo
14
ioo en i0.1 µF
2 13 NC
3
Vss
4 9400 11
c,., V/F
Fo
5 10
2
GND 6 9
7 8
1 Mil RL
10kfl 10 kfl
v.:
-5 V C int +5 V
1000 pF
Figure 9-12 10 Hz to 10 kHz V/F converter. To increase Fomu to 100 kHz, change c.;
to 27 pF and Ciat to 75 pF. (Courtesy of Teledyne Semiconductor.)
1. Choose VDD and Vss such that

4V < VDD < 7.5 V
- 7.5 V< Vss < -4 V
Generally, VDD = +5 V and Vss = -5 V. For high accuracy, 0.1-µF disk
decoupling capacitors located near the pins 4 and 14 are recommended.
2. The reference voltage V,0r can be a separate precision source or can be the
negative supply voltage Vss· Usually, V,.r = Vss = -5 V.
3. R10 is calculated from the equation
R _ Vin full scale
In - /10 full SCaJe
For the 9400 V/F the specified values of V10 full scale = IO V and Ii,,, full scale
= IO µA.
Hence R1 .. = I Mn. Metal film resistors with < I % tolerance are recommended
for high accuracy.
4. For the 9400 V/F, the specified value of Rb1as = 100 kn.
5. The specified value of pull-up resistors RL is 10 kn each (see Figure 9-12).
6. Although the exact value of C,.r is not critical, it should be <500 pF. This
capacitor should be located as close as possible to pins 3 and 5. Glass film
capacitors are recommended for high accuracy.
Sec. 9-1 O Voltage-to-Frequency and Frequency-to-Voltage Converters 355

--=·===--=
7. Choose the value of C1n, such that

3Cr.r < C,01 < lOCr.r
However, for improved stability and linearity, C101 must be > 4Cr.r· This
capacitor should be located as close as possible to pins 3 and 12.
8. The exact values of offset adjust resistors R0, Rb, and R, are not critical; however,
they are related by the relationship
s, < R 0 < Rb
(See Figure 9-12).
9-10.1 (b) Adjustment/calibration procedure. For a 10-kHz full-scale

output frequency F the adjustment/calibration procedure is as follows:
0,
1. Set Vin to 10 mV and adjust the R potentiometer to obtain a 10-Hz output

0
frequency (see Figure 9-12).

2. Set Vin to 10 V and adjust R, Vre r, or Cr.r to obtain a 10-kHz output frequency.
0,
9-10.1 (c) Single-supply operation. The 9400 V/F converter can also be
operated using a single supply, as shown in Figure 9-13.
10 V to 15 V
14 RL RL
8.2 V 6.2 K 10 kn 10k11
2
10k11
6 8 Fo
i0.001 µF
11 , Fo
620kn 9400 10
2
12 V/F
820 pF
18 ki1
5
R;n
Vin 3
1 MU 7 4 9
100k11
op1 µF
5ki1 Gain adjust
Figure 9-13 9400 V/F converter using single variable supply voltage with offset and gain
adjust. (Courtesy of Teledyne Semiconductor.)

Example 9-3
The V/F converter of Figure 9-12 is initially adjusted for a JO-kHz full-scale output
frequency. Determine the output frequencies F and F /2 if the input signal V; = 2 V.
0 0 0
Solution. The output frequency F of the 9400 is directly proportional to the input
0
voltage V; In addition, it has a guaranteed linearity of 0.05 %. Since the circuit is

0•
initially adjusted for a 10-kHz full-scale output frequency (at Via = 10 V), when the
input V; = 2 V, the output frequency F0 will be (2 kHz ± 0.05 %) and F0/2 will be
0
l kHz ± 0.05 %- The nature of these output waveforms will be as shown in Figure
9-lO(b). I
The V/F converter is used in instrumentation and control, digital, and communi-
cation systems. Typical applications that use V/F converters are in temperature
sensing and control, transducer encoding, analog-to-digital (A/D) converters, micro-
processor data acquisition, digital panel meters, phase-locked loops, and analog
data transmission and recording. For specific application of the V/F converter, refer
to Chapter 11.
9-10.2 F/V Converter
When used as an F/V converter, the 9400 generates an output voltage that is linearly
proportional to the input frequency waveform. The features of the 9400 F/V converter
include de to 100 kHz operation, op-amp output, programmable scale factor, high
input impendance (> 10 MO), and, above all, its capability to accept any voltage wave
shape. Figure 9-14(a) shows an equivalent circuit (inside the dashed box) and connec-
tion diagram of the 9400 when it is used as a F/V converter. The input frequency is
applied to the ( +) input of the comparator (pin I I). Since the comparator hysteresis
voltage is ±200 mV, the input signal amplitude must be greater than ±200 mV
in order to trip the comparator. If only a unipolar input signal is available, it can be
converted into a bipolar waveform by using the offset circuit of Figure 9.:.15.
Each time the input signal crosses zero in the negative direction, the output of
the comparator goes low. Three microseconds later the Cre r charge/discharge control
circuit is enabled, which instantaneously connects the reference capacitor c,.r to the
reference voltage V,.r [see Figure 9-I 4(a)]. This. action charges C101 each time with a
precise amount of voltage until the voltage across it can no longer increase. The
charging path is through the output terminal of the op-amp, through C1110 through
C,.r, and finally through Vr.c· On the other hand, each time the input waveform
crosses zero in the positive direction, the output of the comparator switches high.
This disables the C,.r chargeldischagre control circuit, and C,.r is shorted out. How-
ever, the voltage across C1n, is retained because the only discharge path for C1111 is
through R,110 which is very large (1 M!l). The voltage across C1111 is the output voltage
Vo.
The amount of ripple on V0 is inversely proportional to C1n1 and the frequency
of the input Fm. This means that for low frequencies C1n1 can be increased in the range
1 to 100 µF to reduce the ripple. To eliminate the ripple on V0, an extra op-amp that
is operating in the common-mode configuration shown in Figure 9-16 can be con-
nected to the output of the F/V converter of Figure 9-1~a). Because of the common-
Sec. 9-1 O Voltage-to-frequency and Frequency-to-Voltage Converters 357

+V
Comp
Frequency in
Input,
FIN
51
I
I Output
I
I common
GND I
I
I ---,
I I
I C,.. charge/discharge I
I control circuit I
71 isI
C,.1
56 pF
+6V - c,..,
1000 pf
:>-~~~~ ....... ~~~1,...-~--cvo
R, 112 Output
20kO~~Mr~.----,~~~~~~-~~~~~~~ I
I I
2.2 kn
R0 I
L _ _ _)I
Offwt I- 4 v.
edjult 100k0
(a)
-6V
,,vw LJ
rl
LJ
I
r. - :t1- : :h:
F,n • t
ov
-2.5 V I I I I I
5V
OV I
[ • t
I
I
::l I
'I ..
{b)
Figure 9-14 (a) De to 10 lcHz F/V converter. Fa/2 and Fa are optional if buffer is needed.
When not used, pins 8, 9, and 10 may be connected to ground. (b) F/V digital outputs.
(Courtesy of Teledyne Semiconductor.)
358
v
+2.5V~
ov t
-2.5 V
-5V
I
Figure 9-15 Offset circuit to convert unipolar waveform into bipolar waveform.
1 µF 10kn lOkn
r 4.7 kn
10k11
Figure 9-16 F/V ripple eliminator.
mode configuration, the ac ripple is canceled at the output of an op-amp provided

that both ( +) and ( - ) inputs have the same gain. The 10 kn potentiometer is used
to make the gain of ( +) and ( - ) inputs equal. Besides that, the circuit in Figure
9-16 has a de gain of unity, so that output voltage is equal to input.
In the F/V converter of Figure 9-14(a), outputs F0 and F0/2 are optional because
these outputs are useful in only some applications. The output F0 follows the input
frequency waveform, with a 3-µS delay on the rising edge [see Figure 9-14(b)]. F /2 0
is a square wave with a frequency one half of F0• If F0 and Fof2 outputs are not used,
I pins 8, 9, and 10 may be connected to ground .
. Although the F/V converter accepts any input wave shape, the circuit will work
only if the positive pulse width of the input waveform is at least 5 µsand the negative
pulse width is >0.5 µs. When Fin max is less than 1 kHz, the duty cycle ( = pulse
width/time period x 100) should be greater than 20% to ensure that C,., is fully
charged and discharged.
9-10.2(a) F/V design procedure. The output voltage V0 of the F/V

converter is related to the input frequency F,n by the equation
(9-5)
Sec. 9-10 Voltage-to- Frequency and Frequency-to-Voltage Converters 369

The response time to a change in F1n is equal to R1n1Cint· The F/V converter can be
designed by following these steps:
1. Choose V DD and Vss such that

4V< VDD< 7.5 V
-7.5V < Vss < -4 V
(Usually, VDD = +5 V and Vss = -5 V.)
2. Choose V,.r = Vss = -5 V.
3. Choose R1n1 = 1 MQ for F,n max of 10 kHz. However, for F1n max of 100 kHz,
Rint should be decreased to 100 kQ.
4. Rbiu = 100 kQ is the specified value for the 9400 F/V converter.
5. Choose pull-up resistors RL = 10 kQ.
6. Choose C,.r ~ 56 pF_ for a F;,, max of 10 kHz. However, C,.r should be increased
for a lower Fin max·
7. Choose clnt = 1,000 pF for Fin max of IO kHz. However, for a lower F,n mm
Cint can be increased in the range 1 to 100 µF.
8. Choose offset voltage compensating network resistors R R6, and Re 0,
such that
[See Figure 9-14{a)].
9-10.2{b) Adjustment/calibration procedure. Fora 10-kHzmaximum

input frequency F1nmm the adjustment/calibration procedure is as follows:
1. When no input signal is applied {F1n = 0), adjust the offset null circuit to obtain
a O V de output voltage. 1
2. Set F1n .= 10 kHz and adjust C,.r so that V is approximately 2.5 to 3 V.

0
9-10.2{c) Single-supply operation. The 9400 F/V converter can also be

operated using a single supply, as shown in Figure 9-17. In this figure, Vrer is defined
as the voltage difference between pins ·2 and 7. The comparator's(-) input is refer-
enced to 6.2 V; therefore, the input signal must satisfy the requirement
4 V < input voltage< VDD
The output voltage in turn is also referenced· to 6.2 V. Additionally, if the input
signal is ac-coupled, a 100-kn to 10-MQ resistor must be connected between ( +) and
(-) inputs (pins 11 and 6) of the comparator. ·
The 9400 F/V converter can be, used in applications such as frequency meters/
tachometers, speedometers, rpm (revolutions per minute) indicators, FM demodula-
tion frequency multipliers/dividers, and motor control.
Ex.ample 9-4
The F/V converter of Figure 9-14{a) is initially adjusted for V 0 = 2.8 Vat Fin ma:r. of
10 kHz. Determine the output voltage V if Fi« = l kHz.
0

10 V to 15 V
Offset Abi11
14
R, 100 kn
100 kn 2 13
Bias
10 kn I in
3
Vss Amp out Vo Output
4 9400 12
RC F/V
5 · Fin
11
Ref out Comp in Input
GNO 10
6
9
v.:
7 8
Rint c.;
1 Mn 1000 pF
f:igilre 9-17 9400 F/V converter using single supply. (Courtesy of Teledyne Semiconduc-
tor.)
Solution. The 9400 F/V converter generatesan output voltage that is linearly propor-
tional to the input frequency F1a. Therefore, at Fin = 1 kHz, V0 = 2.8 V/10 = 0.28 V.
S-11 ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG

CONVERTERS
Digital systems are used in ever more applications because of their increasingly
efficient, reliable, and economical operation. With the development of the micro-
processor, data processing has become an integral. part of various systems. Data
processing' involves transfer of data to and from the microcomputer via an input/
output devices. Since digital system's such 'as microcomputers use a binary system
of "ones" and "zeros," the data to be .put in to the microcomputer- have to be con-
verted from-analog form to digital form. The circuit that performs this conversion
is called an analog-to-digital (A/ D) converter. On the other hand, a digital-to-analog
(D/A) converter is used when a binary output from a digital system must be converted
to some equivalent analog voltage or current. The binary output (a sequence of l's
O's and) from a digital system is difficult to interpret; however, a D/A converter
makes the interpretation easier. The function of a D/A converter is exactly opposite
to that of an A/D converter. This section presents both types ·of converters. The
Sec. 9-11 Analog-to-Digital and Digital-to-Analog Converters 361

D/A converter is presented first because (1) it is simpler than the A/D converter and
(2) it canalso be used to form the A/D converter.
9-11.1 DI A Converters
A D/A converter in its simplest form uses an op-amp and either binary-weighted
resistors or R and 2R resistors (see Figures 9-18 and 9-19).
9-11.1 {a) 0/A converter with binary-weighted resistors. Figure 9-18

shows a D/A converter using an op-amp and binary-weighted resistors. Although in
this figure the op-amp is connected in the inverting mode, it can also be connected
in the noninverting mode. Since the number of binary inputs is four, the converter
is called a 4-bit (binary digit) converter. Because there are 16 (24) combinations of
binary inputs for bO through b3, an analog output should have 16 possible cor-
responding values. In Figure 9-18, four switches (bO to b3) are used to simulate the
binary inputs; in practice, a 4-bit binary counter such as the 7493 may be used instead.
When switch bO is closed (connected to +5 V), the voltage across R is 5 V because
V2 = V1 = 0 V. Therefore, the current through R is 5 V/10 kn= 0.5 mA. However,
the input bias current IB is negligible; hence the current through feedback resistor
RF is also 0.5 mA. which, in turn produces an output voltage of -(I kQ)(0.5 mA) =
-0.5 V. Note that the op-amp is working as a current-to-voltage converter. Now
suppose that switch bl is closed and bO is opened. This action connects R/2 to the
positive supply of +s V, causing twice as much current (1 mA) to flow through Rp,
which in turn doubles the output voltage. Thus the output voltage V0 is -1 V when
switch b I is closed. Similarly, if both switches bO and b I are closed, the current through
RF will be 1.5 mA which will be converted to an output voltage of -[(I kO(l.5 mA)] =
-1.5 v.
Thus, depending on whether switches bO to b3 are open or closed, the binary-
weighted currents will be set up in input resistors. The sum of these currents is equal
to the current through Rp, which in turn is converted to a proportional output voltage.
When all the switches are closed, obviously the output will be maximum. The output
voltage equation is given by
bO
Vo= -RP (R
bl b2 ,
+ R/2 + R/4 1
b3)
R/8 (9-6)
where each of the inputs b3, b2, bl, and bO may either be high ( +5 V) or low (0 V).
Figure 9-18(b) shows analog outputs versus possible combinations of inputs.
The output is a negative-going staircase waveform with 15 steps of -0.5 V each.
In practice, however, the steps may not all be the same size because of the variations
in logic high voltage levels. Notice tb,at the size of the steps depends on the value of
RP. Therefore, a desired step can be obtained by selecting a proper value of R,,
provided that the maximum output voltage does not exceed the saturation levels of
an op-amp. For accurate operation of the D/ A converter, precision metal film resis-
tors are recommended.
The problem with the D/A converter of Figure 9-18 is that it requires binary-
weighted resistors, which may not be readily available, especially if the. number of

+5V
bO
R
-
0.5mA
10k51
le ='! 0
V2
i -
RF
0.5 mA +15 V
1 k51
5 kn
V0=-0.5V
2.5 k51
----o b3
R/8
I
1.25 k51
(a)
Decimal equivalent of
binary inputs
0 1 2 3 15
-0.5 V
-lV
-1.5V
-7.5 V
(bl
Figure 9-18 (a) D/A converter with binary-weighted resistors. (b) Graph of
output versus inputs.
inputs is more than four. An attractive alternative is to use R and 2R resistors for the
D/A converter since it requires only two sets of precision resistance values.
9-11.1 (b} 0/A converter with R and 2R resistors. Figure 9-19(a)
shows a D/ A converter with R and 2R resistors. As before, the binary inputs are
simulated by switches bO through b3, and the output is proportional to the binary
inputs. Binary inputs can either be in the high ( +s V) or low (0 V) state. Assume
that the most significant bit (MSB) switch b3 is connected to +s V and other switches
are connected to ground as in Figure 9-19(a). Thevenizing the circuit to the left of
switch b3, Thevenin's equivalent resistance Rm is
RTH = [([(2R II 2R + R) II 2R] + R} II 2R] + R (9-7a)
= 2R = 20k!l
Sec.9-11 Analog-to-Digital and Digital-to-Analog Converters 363
2R
2okn
2R
2okn
R
rnkn
2R
2okn
R
10 kn
2R
20 kn
R
10 kn
--
I
V2
I
RF
2okn
bO Vo
b1 b2
RL \
10kn
V1 =OV
(al
2okn ~ 1 2okn
+15 V
2R
zo xn
b3
+5V
(b)
foput(V)
Decimal equivalent of Output Decimal equivalent of
binary inputs b3 b2 bl bO voltage (V) binary inputs
0 3 6 15
0 0 0 0 0 0
I 0 0 0 5 -0.625 -0.625 V
2 0 0 5 0 -1.25
3 0 0 5 5 -1.875 -1.875 V
4 0 5 0 0 -2.50
5 0 5 0 5 -3.125 -3.125 V
6 0 5 5 0 -3.750
7 0 5 5 5 -4.375
8 5 0 0 0 -5.0
9 5 0 0 5 -,5.625
-8.875 V
10 5 0 5 0 -6.25
-9.375 V
11 5 0 5 5 -6.875
12 5 5 0 0 -7.50
-Vo
13 5 5 0 s -8.125
14 5 5 5 0 -8.875
15 5 5 5 5 -9.3y5
(cl
Figure 9-19 (a) D/A converter with R/2R resistors, (b) Equivalent circuit when b3 is high
and bO, bl, and b2 are low. (c) Output VCl'3US inputs.
364
The resultant circuit is shown in Figure 9-l 9(b). In this figure the ( - ) input is at
virtual ground (V2 ~ o
V); therefore, the current through RTH (= 2R) is zero. How-
ever, the current through 2R connected to +5 Vis 5 V/20 kQ = 0.25 mA. The same
current flows through RP and in turn produces the output voltage
V0 = -(20 kQ)(0.25 mA) = -5 V (9-7b)
Using the same analysis, the output voltage corresponding to all possible cornbina-
tions of binary inputs can be calculated as shown in Figure 9-19(c). The maximum
or full-scale output of -9.375 V is obtained when all the inputs are high. The output
voltage equation can be written as
b3 b2 bl bO) (9-8)
Vo= -RF ( 2R + 4R + 8R + J6R
where each of the inputs b3, b2, b 1, and bO may be either high ( + 5 V) or low {O V).
The great advantage of the D/ A converter of Figure 9-19(a) is that is requires
only two sets of precision resistance values; nevertheless, it requires more resistors
and is also more difficult to analyze than the binary-weighted resistor type. As the
number of binary inputs is increased beyond four, both D/ A converter circuits get
complex and their accuracy degenerates. Therefore, in critical applications an inte-
grated circuit specially designed as a D/ A converter should be used.
9-11.1 (c) Monol_ithic/hybrid D/A converters. At present, 8-, 10-, 12-,

14-, and 16-bit D/ A converters are available with either a current output, a voltage
output, or both current and voltage outputs. The MC1408L is a common 8-bit
monolithic D/A converter with a current output which can be converted to a voltage
type by using an 1-to-V converter op-amp [see Figure 9-20(a)]. On the other hand,
the SE/NE 5018 is a typical 8-bit D/A converter with voltage output. Figure 9-20(b)
shows the SE/NE 5018 configured for unipolar output (0 to 10 V). For 12 bits of
resolution as well as current and voltage outputs, hybrid D/A converters such as the
DATEL DAC-HZ series are an excellent choice. To make an intelligent selection
from a variety of D/A converters to suit a given application, it is necessary to know
the key specifications of D/A converters, such as resolution, nonlinearity, gain error,
and settling time.
Resolution. Resulution is determined by the number of input bits of the D/A

converter. For example, an 8-bit converter has 28 ( = 256) possible output
levels; therefore, its resolution is 1 part in 256. In short, resolution is a value of
the LSB.
Nonlinearity or linearity error. This is the difference between the actual output
of the DAC and its ideal straight-line output. The error is normally expressed
as a percentage of the full-scale range.
Gain error and offset error. Gain error is usually caused by the deviations in
the feedback resistor on the 1-to-V converter. On the other hand, offset error
implies that the output of the DAC is not zero when the binary inputs are all
zero. This error stems from the input offsets (V and /) of the op-amp as well
as the DAC.

+Vcc=+5V
I
MSB 07 5 13 14
06 6 1 kn
05 7 A
15
04 9 MC1408L 1 kn
1
03 8 OAC
2
02 10
01 11
LSB DO 12 4 1------.J\/\Nv--..,......-,
16 3 ..
V0=9.961 Vwith
6 all inputs high
-VEE
-5V
-15 V
(a)
07 + 06+ D5+ 04
{ 2
+ D3+ 02 + _Q! + _Q.Q.}
4 8 16 6 64 128 256
0.1 11F
·f1
Digital data
in
LSB
(Latch enable)
9 8 7 6 5 4 3 2 19 '1
10 Digital ground/
14 V.., In
Full 11:ale Anaolg ground 22
ldjust 13 v.., Out
12 V,., Adj vOAlt 28 Output

I NE/SE•6018 I
60 RL
pF +15V
--<>--lB DAC
comp. +Vee
0.0111F
-VEE"' -15
V ----<>--17 20kn
A:!~~~
I .
-VEE
Bipolar offlet -15 V
15 21
Zero11:ale
adjust
FJaare ,-20 (a) MC1408D/A converter with current output. (Courtesy of Motorola Semi-
conductor.) (b) NE/SE 5018 D/A converter with voltage output. (Courtesy of Signetics
Corporation.)
366
Settling time. This is the time required for the output of the DAC to settle to
within ±t LSB of the final value for a given digital input, that is, zero to full
scale.
Typical applications for D/A converters include microcomputer interfacing,

CRT graphics generation, programmable power supplies, digitally controlled gain
circuits, digital filters, and others.
9-11.2 AID Converters
A/D converters convert an analog voltage to the digital output that best represents
the input. As in the case of D/A converters, analog converters are also specified as
8, 10, 12, or 16 bit. There are many types of A/D converters: single-ramp integrating,
dual-ramp integrating, single counter, tracking, and successive approximation.
This section discusses only the successive-approximation type, which uses a com-
parator, a successive-approximation register, output latches, and a D/A converter.
9-11.2(a) Successive-approximation A/0 converter. Figure 9-21

shows a successive-approximation type of A/D converter. The heart of the circuit is
an 8-bit successive-approximation register (SAR), whose output is applied to an
8-bit D/A converter. The analog output (V of the D/A converter is then compared
0)
_ Seri al data
Clock,
8-bit SAR
DO - out
s o Start
D cc I - Con version
- co mplete
Serial data 07 03 o, Latch
input enable
- E
-
~
~
--
~ Digital
B·bit latch data
.. output
~
Analog voltage
out V1 - Binary inputs
-
L(_
Comparator
b7
B·bit DAC
bO
,, Vin
Analog input
Figure 9-21 Successive-approximation-type A/D converter.

to an analog input signal V1n by the comparator. The output of the comparator is a
serial data input to the SAR. The SAR then adjusts its digital output (8 bits) until
it is equivalent to analog input Vin· The 8-bit latch at the end of conversion holds
onto the resultant digital data output. The 'circuit works as follows. At the start of a
conversion cycle, the SAR is reset by holding the start (S) signal high. On the first
clock pulse LOW-to-HIGH transition, the most significant output bit Q7 of the
SAR is set. The D/A converter then generates an analog equivalent to the Q7 bit,
which is compared with the analog input Vin· If the comparator output is low, the
D/A output> V1n and the SAR will clear its MSB Q7• On the other hand, if the
comparator output is high, the D/A output< Vin and the SAR will keep the MSB
Q7 set. In any case, on the next clock pulse LOW-to-HIGH transition, the SAR will
set the next MSB Q6• Depending on the output of the comparator, the SAR will then
either keep or reset the bit Q6• This process is continued until the SAR tries all the
bits. As soon as the LSB Q0 is tried, the SAR forces the conversion complete (CC)
signal HIGH to indicate. that the parallel output lines contain valid data. The CC
signal in turn enables the latch, and digital data appear at the output of the latch.
Digital data are also available serially as the SAR determines each bit. To cycle the
converter continuously, the CC signal may be connected to the start conversion
input (see Figure 9-21). The advantage of the successive approximation A/D converter
is its high speed and excellent resolution. For example, the B-bit successive approxima-
tion A/D converter of Figure 9-2 l requires only eight clock pulses.
9-11.2(b) Monolithic/hybrid A/0 converters. There are many

monolithic A/D converters, such as the integrating A/D, integrating A/D with three-
state outputs, and the tracking A/D with latched outputs. In addition, the outputs
of A/D are coded in straight binary, binary-coded decimal (BCD), complementary
binary (l's or 2's), or sign-magnitude binary. Figure 9-22 shows the Teledyne 8703,
an 8-bit monolithic CMOS A/D converter with three-state output. The converter is
microprocessor-compatible, exhibits high stability over a full temperature range,
contains all required active elements, and has latched parallel binary outputs with
strobed or free-running conversion, It has an infinite input range since any positive
voltage can be applied via a scaling register R1n.
As in the case of monolithics, there are many hybrid A/D converters, such as
the successive-approximation A/D with input buffer amplifier, low-power CMOS
A/D, the fast A/D with sample-and-hold, and the ultrafast A/D with input buffer
amplifier. Datel-Intersil's hybrid ADC-815MC is a very.high speed 8-bit successive-
approximation A/D converter. It is capable of 8-bit resolution in only 600 ns. It has
a six analog-input voltage range with parallel or serial outputs and requires no
calibration. Datel's ADC-MC8B is an 8-bit monolithic multifunction A/D-D/A
converter which operates on a single +5-V supply. It is a complete D/A converter
which can be configured as an A/D converter by using an external comparator and
a quad two-input Schmitt trigger NANO gate.
As with D/A converters, specifications such as resolution or nonlinearity are
also used for A/D converters. Another important parameter for A/D is conversion
time, the time required to convert an analog input into valid digital outputs.

>
... "'
...
c"' ::,
... a-
:.0
:.0
::,
0
ciJ >
"'
::,
CD
>c c:
..,,
~
0
a: ri.- N
N M M
N N
~I
..."'c
::, >
;;11
~0
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0 I
u
...a. .,"'
::, ]
·5,
m
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::,
s:
0
0-
e
......
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"'c
0
z
0::, 0
N
o
0
o
0
0
>.,._>__ ~-.
ll'l
I
>'a >
+ u. ll'l
I
;4> I
I
L---- -,
I
I
-------
~~
0
N
I
C) 0
....,u
·-ccc ...
::, c O
... c O
a:... 8., >
... "O
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if E
!!!·~ ~
:~"'c ...~c
0
u
369
Typical applications of A/D converters include microprocessor interfacing,
data printing and recording, digital voltmeters, and control of LED or LCD displays.
9-12 CLIPPERS AND CLA/1.IIPERS
Waveshaping circuits are commonly used in digital computers and communications

such as TV and FM receivers. Waveshaping techniques include limiting, clipping,
and .clamping. Voltage limiting was discussed in Section 9-7. The present section
presents typical circuits that use clipping and clamping techniques. In op-amp clipper
circuits a rectifier diode may be used to clip off a certain portion of the input signal
to obtain a desired output waveshape. An op-amp half-wave rectifier and an absolute-
value output circuit use diodes to remove or 'modify certain portions of the input
waveform. In the applications described above the diode works as an ideal diode
(switch) because when on, the voltage drop across the diode is divided by the open-
l(?OP gain of the op-amp. On the other hand, when reverse biased (off), the diode
is an open circuit. In an op-amp clamper circuit, however, a predetermined de level is
deliberately inserted in the output voltage. For this reason, the clamper is sometimes
called a de inserter. ·
9-12.1 Positive and Negative Clippers
A positive clipper, a circuit that removes positive parts of the input signal, can be
formed by using an op-amp with a rectifier diode as shown in Figure 9-23(a). In this
circuit the op-amp is basically used as a voltage follower with a diode in the feedback
path. The clipping level is determined by the reference voltage Vr.r, which should be
less than the input voltage range of the op-amp. Additionally, since Vr.r is derived
from the positive supply voltage (+Vee), the de supply voltages must be well regulated.
As shown in Figure 9-23(b) the output voltage has portions of the positive half cycles·
above vr.r clipped off. .
The circuit works as follows. During the positive half cycle of the input, the
diode DI conducts only until 'Vin = v,.r• This happens because when Vin < vr.r,
the voltage (Vr.r) at the (-) input is higher than that at the (+)input; hence the
output voltage v~ of the op-amp becomes sufficiently negative to drive D1 into conduc-
tion. When D1 conducts, it closes the feedback loop and the op-amp operates as a
voltage follower; that is, output Vo follows input V;n until V;n = vrof· However, when
v1n is slightly higher than Vrcr, the output v~ of the op-amp becomes sufficiently
positive to drive D1 into cutoff. This opens the feedback loop and the op-amp operates
open-loop; therefore, it further drives its output v~ toward positive saturation
(- + Vee). With D1 reverse biased,' the output voltage i•0 = V,.r· Thus when v1o. >
v,.r,v: - + Vee and Vo = vrcf [see Figure 9-23(b)].
When v1n drops below Vr.r, the output of the op-amp v~ again becomes suf-
ficiently negative to drive DI into conduction. This closes the feedback loop; hence
the output follows the input. Thus diode D, is on for Vin < v,.r and off for Via > vr.r·
The output follows the input only when the diode is on. The op-amp alternates between
open-loop and closed-loop operations as the diode D1 is turned off and on, respec-

2V
v,ef = 1 V
-2 V
V0 I
I
I
I 01 off
-VEE
I
-15 V
-2 V
R
lb)
10kU
+Vee
10 kU +
V,01=1V
t 2V
(a)
-v,.1 = -1 v
-2 V
=v.; = -1 V --.....--""'
-2 V 01 on
01 off
(c)
Figure 9-23 (a) Positive clipper circuit. (b) Input and output waveforms with
+ Vref = 1 V. (c) Input and output waveforms with -Vrcr = -1 V.
tively. For this reason the op-amp used must be high-speed, preferably compensated
for unity gain. HA2500, LM310, and µA318 are examples. Besides that, the difference
input voltage vld is high during the time when the feedback loop is open (D1 off);
hence an op-amp with high difference input voltage is necessary to prevent input
breakdown.
In Figure 9-23(a), if pot RP is connected to the negative supply - VEE instead
of+ Vee, the reference voltage Vr.c will be negative. This will cause the entire output
waveform above -Vr.r to be clipped off, as shown in Figure 9-23(c). The output
follows the input only when Vin < - Vref•
Sec. 9-12 Clippers and Clampers 371

The positive clipper of Figure 9-23(a) is converted into a negative clipper by
simply reversing diode D1 and changing the polarity of reference voltage Vr.r· The
resultant circuit is shown in Figure 9-24(a). The negative clipper clips off the negative
parts of the input signal below the reference voltage [see Figure 9-24(b)]. Diode D1
conducts when Vin > - Vr.r, and therefore during this period output v0 follows the
input Vin· However, the negative portion of the output voltage below - Vr.r is clipped
off because DI is off for V;n < - vr.r· In the circuit of Figure 9-24(a), if - vrer is
changed to + Vr.r by connecting the potentiometer RP to the + Vee, the output voltage
below+ Vr.r wi.11 be clipped off, as shown in Figure 9-24(c). The diode D1 must be
on for Vin > + Vref and off for V; < + Vrer·
0
2V
-v,., = -1 V
-2 V
+Vee
2V
+15V
-v,., = -1 V
01 off
R (b)
10 kn·
-15 V
-VEE
10 kn +
-V,01=-1V
t v,., =
2V
1 V
(a)
-2 V
V0 I
I
I
I
I
2V I
v,., = 1 V
(c)
Figure 9-24 {a) Negative clipper circuit. (b) Input and output waveforms with
- Vrer = -1 V. (c) Input and output waveforms with+ V rer =' +1 V.
372 · Comparators and Converters Chap.9

9-12.2 Small-Signal Half-Wave Rectifiers
The circuit of Figure 9-24(a) can be used as a positive small-signal half-wave rectifier
provided that - V,er = 0 V. Shown in Figure 9-25(a), the resultant circuit can rectify
signals with peak values down to a few millivolts, unlike conventional diodes. This is
+100 mV
-100 mV
Vo
Vo
01 On
RL +100 mV
10kS1
(a) (bl
Figure 9-25 (a) Positive small-signal half-wave rectifier circuit. (b) Its input and
output waveforms.
possible because the high open-loop gain of the op-amp automatically adjusts the
voltage drive to the diode D1 so that the rectified output peak is the same as the input
[see Figure 9-25(b)]. In fact, the diode acts as an ideal diode (switch), since the voltage
drop across the on diode is divided by the open-loop gain of the op-amp. As v1n starts
. increasing in the positive direction, the v~ also starts increasing positively until diode
D1 is forward biased. When D1 is forward biased, it closes a feedback loop and the
op-amp works as a voltage follower. Therefore, the output voltage v follows the 0
input voltgae v1n during the positive half-cycle, as shown in Figure 9-25(b).
However, when v1n starts increasing in the negative direction, v~ also increases nega-
tively until it is equal to the negative saturation voltage c~ -
VEE). This reverse
biases diode D1 and opens the feedback loop. Therefore, during the negative half-
cycle of the input signal, Va is O V.
The op-amp in the circuit of Figure 9-25(a) must be a high-speed op-amp since
it alternates between open-loop and closed-loop operations. µA318, HA2500, and
LM3 IO are typical examples of high-speed op-amps.
Figure 9-26(a) shows a negative small-signal half-wave rectifier. This circuit,
in fact, can be obtained from the circuit of Figure 9-23(a) by setting V,er = 0 V.
During the positive alternation of v1n, D1 is reverse biased; therefore, Va= 0 V.
On the other hand, during the negative alternation, D 1 is forward biased; hence
V follows Vio.·
0

Vin
+100 mV
ov
-100 mV
Vo
Vo
RL 01 Off
10 kn
ov
-100 mV
(al (bl
Figure 9-26 (a) Negative small-signal half-wave rectifier circuit. (b) Its input and
output waveforms.
Yet another negative half-wave rectifier is shown in Figure 9-27(a). In this

circuit two diodes are used so that the output v~ of the op-amp does not saturate.
This minimizes the response time and increases the operating frequency range of the
op-amp. However, notice that the op-amp is used in the inverting configuration,
and the output is measured at the anode of diode Di with respect to ground. Besides
that, the output resistance is nonuniform since it depends on the state of diode D1•
In other words, the output impedance is low when Di is on and high Rp) when c~
D1 is off. This problem, however, can be cured by connecting a voltage follower
R1 Vo
10kS1
+
01 1N914
v~
-VEE +
-15 V 02 1N914
01 02
On On
(a) (b)
Figure 9-27 (a) Negative half-wave rectifier. (1;,) Its input and output waveforms.
·--
stage at the output. During the positive half-cycle of vin, output v:
is negative, which
forward biases diode D1 and closes the feedback loop through RP. Since R1 = RP,
v = vin· However, on the negative alternation of Vin• output v: is positive; hence
0
diode D2 is forward biased. In fact, it is this diode which prevents the op-amp
from going into positive saturation. Since diode D1 is off, output v = 0 V. To obtain
0
positive half-wave rectified outputs, diodes D1 and D2 must be reversed.

Example 9-5
In the circuit of Figure 9-25(a), Vin = 200 mV peak-to-peak sine wave at 100 Hz.
Briefly describe the operation c1f the circuit and draw the output waveform.
Solution. During the positive half-cycle of the input, diode D 1 conducts; therefore,
output follows the input; that is, v = 100 mV peak. During the negative half-cycle of
0
Vin, diode D1 is reverse biased; hence ·u = 0 V. The output waveform is shown in

0
Figure 9-25(b).
9-12.3 Positive and Negative C/ampers
In clamper circuits a predetermined de level is added to the output voltage. In other

words, the output is clamped to a desired de level. If the clamped de level is positive,
the clamper is a positive clamper. On the other hand, if the clamped de level is negative,
the clamper is called a negative clamper. Other, equivalent terms used for clamper
are de inserter or restorer.
Recall that op-amps designed to operate from a single power supply, such as
the 124 series, employ a de insertion technique. Inverting and noninverting amplifiers
that use this technique are repeated here for convenience [see Figure 9-28(a) and (b)].
The value of the capacitors in these circuits depends on different input rates and
pulse widths. Notice that in both amplifier circuits the de level added to the output
voltage is approximately equal to Vcc/2. This fixed positive de level is needed to
obtain a maximum undistorted symmetrical sine wave. A clamper with a variable
positive de level is shown in Figure 9-29(a). However, this circuit functions differently
from that of Figure 9-28(a) in that the input waveform peak is clamped at V,.r [see
Figure 9-29(b)]. For this reason the circuit is called the peak clamper.
The output voltage of the clamper is a net result of ac and de input voltages
applied to (-) and (+)input terminals, respectively. Therefore, in order to under-
stand the circuit operation, each input must -be conside red separately. First consider
the input voltage V,.r at the (+)input. Since this voltage is positive, Va is also posi-
tive, which forward biases diode D1• This closes the feedback loop and the op-amp
operates as a voltage follower. This is possible because C1 is an open circuit for de
voltage. Therefore, v, = + V,.r· As far as voltage v10 at the ( - ) input is concerned,
during its negative half-cycle, diode D1 conducts, charging C, to the negative peak
value of VP. However, during the positive half-cycle of v10, diode DI is reverse biased;
hence, the voltage VP across the capacitor acquired during the negative half-cycle is
retained. 'Since this voltage Vp is in series with the positive peak voltage Vp, the output
voltage v0 = 2 Vp. Thus the net' output is V,.r plus 2 Vp, so thatthe negative peak of
2Vp is at v,.r [see Figure 9-29(b)]. For precision clamping,
T
C,Rd«2

v,n
VP
ov
+
-VP
Vo
RL
10kS1 ~ Vee
-I Vee
2
ov
(a)
v,n
r
c, R,
+Vee
R2 ~Vee
c, +Vee
2
f"
O V 1------>......_ __
R3 v.:
t v0: lv,., + (1 + :F, )von]
(b)
Figure 9-28 (a) Inverting amplifier with de level. (b) Noninverting amplifier with de
level.
where Rd = resistance of diode D1 when it is forward biased

= 100 n typically
T = time period of the input waveform
Resistor R is used to protect the op-amp against excessive discharge currents from
capacitor C,, especially when the de supply voltages are switched off. A positive-peak
clamping isI accomplished by reversing D1 and using negative reference voltage
( - v,.r) [see waveform in Figure 9-29(c)].

0.1 µF
c,+
f
+ VP
n
R
4.7 kn 01
-VEE
+ 1N914
-15 V
+15V
+Vee
(a)
v,., -------------
(b) (c)
Figure 9-29 (a) Peak clamper circuit. (b) Input and output waveforms with
+ Vrcr· (c) Input and output waveforms with - Vrer·
9-13 ABSOLUTE-VALUE OUTPUT CIRCUIT
Another important circuit used in waveshaping is the absolute-value output circuit.

This circuit produces an output signal which swings positively only, regardless of the
polarity of the input signal. Figure 9-30 shows an absolute-value output circuit with
Sec.9-13 Absolute-Value Output Circuit 377

R R R V2 R 03
10 kn 10 kn
+Vee
+15 V
-
- 12
+
le= O i
Vo Vo (+)
1N914 R Vo, R
10 kn +
o, -15 V RL
10kn RL
-Vee R -Vee
10 kn
(a) (b)
R = ~
TH 2 R
+
Thevenize
(cl
»;
VP
ov
-VP
Vo
VP
(d)
Figure 9-30 (a) Absolute-value output circuit, equivalent circuit during (b) positive half-
cycle and (c) negative half-cycle. (d) Its input and output waveforms.
378
its input and output waveforms. Because of the nature of its output waveform, the
circuit may be used as a full-wave rectifier if the input is a sine wave. During the posi-
tive half-cycle of Via, diode D 1 is forward biased and D2 is reverse biased; therefore,
the equivalent circuit is as shown in Figure 9-30(b). In this circuit the voltage at the
(+)input is
v - v,. - VD, (9-9a)
,- 2
where VD1, the voltage drop across [J, = 0.7 V. Similarly, voltage v2 at the(-) input
is
_ v.(+) - VDJ
V,-~-~-~
- 2 (9-9b)
where v0( +) = output voltage during the positive half-cycle

VD3 = voltage drop across D3 = 0.7 V
Since v,4 ~ 0 V, v, = v2• Therefore, from Equations
I
(9-9a) and (9-9b),
V,. - VD,_ v.(+) - VD3
2 - 2
or
v.(+) = V,. (9-10)
On the other hand, during the negative half-cycle of v1a, diode D1 is reverse biased
and D1 is forward biased; hence the equivalent circuit is as shown in Figure 9-30(c).
This circuit can further be simplified by Thevenizing to the left of (-) input.
Thevenin's voltage and resistance are
Vrn = -(v,. 2 VD2) (9-lla)
~ R
RTH=2 (9-11b)
[See Figure 9-30(c)]. Now output voltage v 0(-) can be obtained by writing
Kirchhoff's current equation at node v2:
t, = /1 + /Bl
/1 ~ /2 since /B1 ~ 0 A
(v.(-) - VD3) - Vz _ Vz - (VTa)
(9-llc)
R - R/2
However, v,4 = 0 V and v1 = 0. Therefore, v1 = 0 and
v.(-) - VDJ _ -VTB
R - R/2
Substituting for VTB from Equation (9-lla), we get
v.(-) - VDJ = Vp - VD2
(9-12)
v.(-) = Vp
Thus, regardless of the polarity of the input signal, output is always positive going,
hence the name absolute-value output circuit. Note that the gain of the circuit is I ;
Sec. 9-13 Absolute-Value Output Circuit 379

therefore, the positive peak amplitudes are the same as input peak amplitudes.
Besides that, diode D3 compensates for the voltage drop across D1 or D2•
9-14 PEAK DETECTOR
Square, triangular, sawtooth, and pulse waves are typical examples of nonsinusoidal
waveforms. A conventional ac voltmeter cannot be used to measure these nonsinus-
oidal waveforms because it is designed to measure therms value of the pure sine wave.
One possible solution to this problem is to measure the peak values of the nonsinus-
oidal waveforms.
Figure 9-31 shows a peak detector that measures the positive peak values of the
square wave input. During the positive half cycle of Vin, the output of the op-amp
drives D1 on, charging capacitor C to the positive peak value VP of the input voltage
t'in· Thus when DI is forward biased, the op-amp operates as a voltage follower.
On the other hand, during the negative half-cycle of v10, diode D1 is reverse biased,
and voltage across C is retained. The only discharge path for C is through RL since
the input bias current /8 is negligible. For proper operation of the circuit, charging
time constant ( C Rd) and discharging time constant ( C RL) must satisfy the following
conditions:
T
CRd <10 (9-13a)
where Rd = resistance of the forward-biased diode, 100 n, typically

T = time period of the input waveform
and
(9-13b)
where RL is the load resistor.
If RL is very small so that Equation (9-13b) cannot be satisfied, use a buffer
(voltage follower) between capacitor C and load resistor RL. Although a 741-type
op-amp is used in the circuit of Figure 9-31, a high-speed, precision-type op-amp
v.;
iv.,
l Vee ov
115 V
1N914
D1 .
t Is ::-- 0
--VP
-
Vo
+ -
le
~
+ le Vo
+
r
D2 PIL
VP
- 1N914
10 kn
-VEE
ov
r---j
(al (bl
Figure 9-3.1 (a) Peak detector circuit. (b) Its input and output wa veforrns.

such as the µA 771 or µA 714 may be desirable in critical applications. The resistor
R is used to protect the op-amp against excessive discharge currents, especially when
the power supply is switched off. The resistor RoM = R minimizes the offset problems
caused by input currents. In addition, diode D2 conducts during the negative half-
cycle of v10 and hence prevents the op-amp from going into negative saturation.
This in turn helps to reduce the recovery time of the op-amp. Negative peaks of input
signal v1n can be detected simply by reversing diodes D1 and D2•
9-15 SAMPLE-AND-HOLD CIRCUIT
The sample-and-hold circuit, as its name implies, samples an input signal and holds
on to its last sampled value until the input is sampled again. Figure 9-32 shows a
sample-and-hold circuit using an op-amp with an E-MOSFET. In this circuit the
E-MOSFET works as a switch that is controlled by the sample-and-hold control
voltage Vs, and the capacitor C serves as a storage element. The circuit operates as •
follows. The analog signal v1n to be sampled is applied to the drain and sample-and-
hold control voltage Vs is applied to the gate of the E-MOSFET. During the posi-
tive portion of Vs, the E-MOSFET conducts and acts as a closed switch. This allows
input voltage to charge capacitor C. In other words, input voltage appears across C
and in turn at the output, as shown in Figure 9-32(b). On the other band, when Vs
is zero, the E-MOSFET is off (nonconductive) and acts as an open switch.
+Vee
+15V
MOSFETon MOSFETo·
N,ehannel 7
E-MOSFET
5
0 s
Ts I TH I
-Vee
-15V
Input
voltage
10 kn
Sample-and-hold
control voltage
l•l (b)
Figure 9-32 (a) Sample-and-hold circuit. (b) Its input and output waveforms.
Sec. 9-15 Sample-and-Hold Circuit 381

The only discharge path for C is, therefore, through the op-amp. However, the input
resistance of the op-amp voltage follower is also very high; hence the voltage across
C is retained. The time periods Ts of the sample-and-hold control voltage Vs during
which the voltage across the capacitor is equal to the input voltage are called sample
periods. The time periods TH of Vs during which the voltage across the capacitor is
constant are called hold periods [see Figure 9-32(b)]. The output of the op-amp is
usually processed/observed during hold periods. To obtain close approximation
of the input waveform, the frequency of the sample-and-hold control voltage must be
significantly higher than that of the input. In critical applications a precision and/or
high-speed op-amp is helpful. If possible, choose a low-leakage capacitor such as
Teflon or polyethylene. .
A significant reduction in size and an improved performance can beachieved by
using a specially designed sample-and-hold IC such as the LF398. The functional
circuit of the LF398 shown in Figure 9-33 requires only an external storage capacitor.
Off~t
,--- 2
- - --- -- -----------. ---1
'II 30kn
I
I
I 5
I
">-_....._.....a Output
I I
31 I
Input I
I I
I I
I I
I
81 I
Logic
I I
I soo n
I ---' I
Logic 71 I
reference I
I I
I ________ __JI
L----------------- 6
Hold
capacitor
(a)
V+
v-
3
Analog input o----4
5V-r-, I
ov_J L Logic
input
lb)
Figure 9-33 LF398 sample-and-hold. (a) Functional diagram. (b) Typical connection
diagram. (Courtesy of National Semiconductor.)

The sample-and-hold circuit is commonly used in digital interfacing and com-
munications such as analog-to-digital and pulse modulation systems.
SUMMARY
1. Together with such functions as amplifier, filter, and oscillator, the op-amp can also be
used as a.cornparator, limiter, detector, clipper, clamper, and converter.
2. In its simplest form, a comparator is nothing more than an open-loop op-amp with two
analog inputs and a digital output, de~ending on which input is the larger. It is used in
digital interfacing, Schmitt triggers, analog-to-digital converters, oscillators, and others.
3. An immediate application of the comparator is the zero-crossing detector, in which the
reference voltage Vrc1 = 0 V.
4. The Schmitt trigger is a comparator with positive feedback that converts an irregular
waveform to a square or pulse waveform. In the Schmitt trigger the input voltage triggers
the output every time it exceeds certain voltage levels called upper threshold Vut and lower
threshold Va.
S. Switching speeds, accuracy, and compatibility of outputs are the limiting factors to the
use of op-amp comparators in critical applications. The output of an op-amp can be
limited to a predetermined value by using external components such as zeners and diodes.
Such circuits are called voltage limiters.
6. The window detector uses two comparators and two threshold levels to determine when
an unknown input is between these levels. When the input is between two predetermined
limits, the output is high. However, when the input goes above or below the set limits,
the output is low.
7. The Teledyne 9400 can be used as a V/F or F/V converter simply by using two external
capacitors, three resistors, and a reference voltage. The V/F converter is used in such
applications as temperature sensing and control, analog-to-digital converters, digital
panel meters, and phase-locked loops. The F /V converter is used for applications such as
frequency meters, speedometers, frequency multipliers/dividers, and motor controls.
8. The analog-to-digital (A/D) converter changes an analog input into a digital output
while a digital-to-analog (D/A) converter changes a digital input into an analog output.
The D/A converter can be formed by using anop-amp and either binary-weighted resis-
tors or an R and 2R ladder network. Integrated D/A converters are available as 8, 10,
12, 14, and 16 bits with voltage or current outputs, Microcomputer interfacing, CRT
graphics generation, programmable power supplies, and digital filters are typical applica-
tions of D/A converters. On the other hand, the A/D converter can be a single-ramp or
double-ramp integrating type, single-counter type, tracking type, or successive approxi-
mation type. As with D/A converters, there are many monolithic/hybrid A/D converters.
Typical applications of A/D converters include microprocessor interfacing, digital volt-
meters, and LED/LCD displays.
9. A clipper is a circuit that removes certain parts of the input waveform. The clipper can
be formed by using an op-amp with a rectifier diode. On the other hand, in an op-amp
clamper a predetermined de level is deliberately inserted in the output voltage. A half-
wave rectifier is a form of clipper. The outputs of the amplifiers that operate on a single
power supply are clamped to a desired value to avoid output distortion. Yet another
waveshaping circuit is the absolute value output circuit, in which the output swings posi-
tively only. Such a circuit is formed by using an op-amp with rectifier diodes.
Chap. 9. Summary 383

10. The peak detector is generally used to detect the positive peak values of nonsinusoidal
waveforms such as triangular, sawtooth, or pulse.
11. The sample-and-hold circuit samples an input signal and holds on to its last sampled
value until the input is sampled again. It can be constructed by simply using an op-amp
with a E-MOSFET as a switch. However, a monolithic sample-and-hold such as the
LF398 requires only an external capacitor. The sample-and-hold-circuit is used in digital
interfacing and communications.
QUESTIONS
9-1. What is a comparator?

9-2. What is the difference between a basic comparator and the Schmitt trigger?
9-3. List the important characteristics of the comparator.
9-4. What is voltage limiting, and why is it needed?
9-5. What is a window detector?
9-6. Name and then briefly describe one application of V/F and F/V converters.
9-7. Briefly describe the operation of the F/V ripple eliminator shown in Figure 9-16.
9-8. For the 9400 F/V converter, what is the limitation on input pulse widths?
9-9. What is the difference between A/D and D/A converters? Give one application of each.
9-10. What is the major difference between 1408 and 5018 D/A converters?
9-11. Define the following terms: resolution, settling time, conversion time.
9-12. What is the difference between clippers and dampers? Give one application of each.
9-13. What is an absolute-value output circuit? How can it be used as a full-wave rectifier?
9-14. What is the name of the circuit that is used to detect the peak value of the nonsinusoidal
input waveforms? Briefly explain its operation.
9-15. What is a sample-and-hold circuit? Why is it needed?
PROBLEMS
9-1. For the basic comparator of Figure 9-l(a), v1n = 2 V pp sine wave at 1 kHz, V,.c =
500 mV, R = 100 n and supply voltages= ±15 V. Draw the output waveform.
9-2. In the circuit of Figure 9-4(a), R1 = 150 n, R2 = 68 kil, Vin = 500 mV pp sine wave,
and the saturation voltages = ± 14 V.
(a) Determine the threshold voltages Vu, and Vi,.
(b) What is the value of hysteresis voltage Vhy?
9-3. In the circuit of Figure 9-5, v;n y 100 mV peak sine wave at 100 Hz, R = 1 k!l, and
D1 and D2 are 6.2-V zeners. The op-amp is a 741 with supply voltages= ±12 V.
Draw the output voltage waveform.
9-4. Repeat Probem 9-3 for the circuit shown in Figure 9-6(a). Assume that the voltage
drop across the forward-biased diode is 0.7 V.
9-5. In the 9400 Y/F converter shown in Figure 9-lO(a), V10 = 5 V, Rin = 1 Mil, V,.r =
-5 V, and C,.r = 180 pF.
384 Comparators. and Converters Chap. 9

(a) Calculate the value of output frequency F
0:
(b) Draw the F and F0/2 waveforms.

0
(c) In order to obtain bipolar outputs, what modification is required in the output
circuitry?
9-6. Calculate the output voltage V0 for the 9400 F/V converter of Figure 9-14(a) if F10 =
2.5 kHz. What modifications are required in the external components if F14 is changed
to 100 kHz?
9-7. Referring to the D/A converter with binary weighted resistors shown in Figure 9-18(a),
determine the size of each step if RF F 1.2 kn. What is the output voltage when inputs
'bO through b3 are at 5 V?
9-8. For the D/A converter using an R-2R ladder network shown in Figure 9-19(a):
(a) Determine the size of each step if RF = 27 kn.
(b) Calculate the output voltage when the inputs bO, bl, b2, and b3 are at 5 V.
(c) What is the advantage of this type of D/A converter over the one with binary-
weighted resistors?
9-9. For the small-signal half-wave rectifier of Figure 9-25(a), draw the output waveform if
v;0 is a 300-m V peak sine wave at 1 kHz .
.' 9-10. Repeat Problem 9-9 with D1 reversed.
9-11. For the peak clamper shown in Figure 9-29{a), draw the output voltage waveform if
v10 = 500 mV pp sine wave at 100 Hz and Vrer = 50 mV.
9-12. In the peak detector of Figure 9-31, C = O.ol µF, RL = 1 Mn, and v10 = 2 V pp
square wave at I kHz. Draw the approximate output voltage waveform. (Assume that
the resistance of the forward-biased diode Rd = 100 n.)
EXPERIMENT 9-1
COMPARATOR AND SCHMITT TRIGGER
Objectives
In this experiment you will see how an op-amp can be used as a comparator and a
Schmitt trigger. At the end of this experiment you should be able to:
1. Verify that an open-loop op-amp is a basic comparator.

2. V.erify the operation of a zero-crossing detector.
3. Draw the output waveform of a comparator for a given value of reference·
voltage.
4. Explain the difference between the comparator and the Schmitt trigger.
5. Select the appropriate components for desired values of thresholds:
Equipment
2. Audio-signal generaltor
3. Digital voltmeter
Exp. 9-1 Comparator and Schmitt Trigger 385

Materials
1. 741 or 351 op-amp

2. Two l N9 l 4 diodes
3. Two IN3826 (5.l-V) zeners
5. l 0-kn resistor
6. l 00-kn resistor
7. 180-kn resistor
8. IO-kn potentiometer
Procedure
1. Connect the circuit of Figure E9-l.1 (a).
+15V
+15 V
\
1 kn
6
+
R, 1 kn
1N3826,
/
V2 = 5.1 V
-15 V
(a) (b)
Figure E9-1.1 Op-amp as (a) a comparator and (b) the Schmitt trigger. (Pin numbers refer
to the 8-pin mini DIP.)
2. Connect the voltmeter at point R and adjust the IO-kn potentiometer so that
the voltage V,.r at point R is O V. Adjust the signal generator for v1n = 2 V pp
sine wave at I kHz. ,
3. Using the scope, simultaneously observe the input and output waveforms.
Draw the output waveform in Figure E9-1.2(a)..
4. Reconnect the voltmeter to point R and adjust the JO-kn potentiometer so that
voltage V,.r = +0.5 V. Repeat.step 3 [Figure E9-l.2(b)].
5. Connect the voltmeter to point R again and adjust the IO-kn potentiometer
so that V,.r = -0.5 V. Repeat step 3 [Figure E9-1.2(c)].

Vin Vin
1 Vp 1 Vp
ov ov
-1 Vp -1 Vp
1 ms .. I 1 ms •I
Vo Vo
(al (bl
Vin
Vin
1 Vp 0.5Vp
ov ov t
-1 Vp -0.5 Vp
1 ms
"I
Vo Vo
(cl (dl
Vin
\:!
0.5 Vp
ov
-0.5 Vp
Vo
O V ~-----------
(el
Figure E9-1.2 Waveforms for (a) step 3, (b) step 4, (c) step 5, (d) step 7, (e) step 8.
387
6. Connect the circuit of Figure E9-1.l(b). Adjust the signal generator so that
v1a = 1 V pp sine wave at 1 kHz.
7. Repeat step 3 [Figure E9-1.2(d)].
8. Replace the 100-la2resistor with a 180-kn resistor and repeat .step 3 [Figure
E9-1.2(e)].
· Questions
1. What is the function of the rectifier diodes in Figure E9-1.l(a)?

2. What is the function of the zener diodes in Figure E9-1.1(b)?
3 ..
Explain the significanceof the V.. r value in comparator operation.
4. What is the significance of the R1 and R2 values in the operation of the
Schmitt trigger?
5. What parameter is most important in the operation of an op-amp as a com-
parator?
6. Explain the differencesbetween the comparator and the Schmitt trigger.
7. What are the limitations of an op-amp as a comparator?
EXPERIMENT9-2
DIGITAL-TO-ANALOG CONVERTER USING THE R-2R
LADDER NETWORK
ObjtH:tives
In this experiment you will learn how the D/A converter works. At the end of this
experiment you should be able to:
1. •
Apply the concepts learned in this-experiment to construct a D/A converter
with more digital inputs.
2. Determine the size of each step (resolution) for a given D/A converter.
I
3. Select a D/A converter with an appropriate number of digital inputs for a

desired step size (resolution).
4. Discuss the advantages and disadvantages of an op-amp as a D/A:converter.
Equipment
2. + 5-V power supply
3. ±15-V power supply

Materials
1. 741 or 351 op-amp
2. I 00-n resister
3. Four 10-kO,resistors (± 1 % or better tolerance)
4. Six 20-kO resistors (± 1 % or better tolerance)
5. 100-kO resistor
6. 20-kn potentiometer I
7. Miniature four-slide or rocker switch assembly
8. Linear graph paper
Procedure
1. Connect the circuit as shown in Figure E9-2. l. (The op-amp pin numbers
indicated in this figure.refer to the 8-pin mini DIP).
R R R
10kU . 10 kU 10kU 20kU
2R 2R 2R 2R
20 kU 20 kU 20 kU 20kU
6
+15V
bO bl b2 b3 R.
20 kn ;;,,-,111-"l,'IIVI,- -15V
-15V
Figure E9-2.1 Op-amp used as a 4-bit D/A converter.
2. Connect the voltmeter to the output terminal. With all switches (inputs bO to b3)
shorted to ground, adjust the 20-kO potentiometer until the output is reduced
to O V. If you have a problem in reducing output to O V, you may try a different
value for the 100-n resistor.
3. Connect the switch corresponding to input bO to +5 V (logic 1) .and measure
the output voltage. Enter the measured value in Table E9-2.1.
4. Connect the switch corresponding to input bl to +5 V, and short all other
remaining switches to ground. Measure the output voltage and enter the result
in Table E9-2. l.
5. Complete Table E9-2. l for the indicated input conditions.
6. Using the data in Table E9-2. l, plot the graph of decimal equivalents of binary
inputs versus output voltage.
Exp. 9-2 Digital-to-Analog Converter Using the R-2R Ladder Network 389
TABLE E9-2.1
Inputs=
Decimal equivalents of binary Output voltage,
inputs b3 b2 bl bO Vo
0 ov OV ov ov ov
1 ov ov ov 5Y
2 ov ov 5V OY
3 ov ov 5V 5V
4 ov 5V ov ov
5 ov 5V ov 5V
6 ov 5V 5V ov
7 OV 5Y 5V 5V
8 5V OV OV ov .
9 5V ov OV 5V
10 5V ov 5V ov
11 5V ov 5V 5V
12 5V 5V ov ov
13 5V 5V ov 5V
14 5V 5V 5V ov
15 5V 5V 5V 5V
oO V = logic O and 5V = logic 1.
Questions
1. In the D/ A converter of Figure E9-2.1, if the number of inputs is increased

from four to eight, what is the size of each step and what is the output voltage
if all the inputs are logic I ( + 5 V)?
2. In the converter of Figure E9-2. l, what will be the size of each step if RP is
changed to I0-kn?
3. In Figure E9-2. l, if R; = IO kn, what will the output voltage be when all inputs
are logic I?
4. Determine the number of inputs required for a D/A converter if the size gf each
step is equal to 9.766 mV. Assume that R = 10 kO, 2R = 20 kn, and RP=
20kn.
5. Is the graph of decimal equivalents of binary inputs versus output voltage
linear? If not, give the reasons.
6. What are the advantages and disadvantages of an op-amp D/A converter?
,-
,

10
Specialized IC Applications
10-1 INTRODUCTION
Integrated circuits with improved capabilities are appearing in ever-increasing

numbers. Innovative design methods and fabrication procedures have not only helped
produce a large variety of new integrated circuits but have also improved the old ones.
Often the use of specialized !Cs produces a simpler and more accurate circuit, such as
Datel's universal filter FLT-U2, Signetics' phase-locked loop (PLL) SE/NE 565 and
timer SE/NE 555, and others. This chapter presents a sampling of specialized inte-
grated circuits and their applications to such devices as universal filters, timers,
phase-locked loops, power amplifiers, voltage regulators, and voltage references.
10-2 UNIVERSAL ACTIVE FILTER
Various filter networks using general-purpose op-amps are discussed in Chapter 8.

However, in critical applications specially designed filter !Cs are preferred. Besides
being more accurate, the specially designed IC filters are simpler, easier to use, and
more flexible. Datel's FLT-U2 is a typical example of such specialized IC filters.
Datel's FLT-U2 is a universal filter which uses the state-variable active filter principle
to implement second-order low-pass, high-pass, and band-pass output functions.
These output functions are simultaneously available at the output of three committed
op-amps (pins 3, 13, andS) as shown in the FLT-U2 block diagram of Figure 10-l(a).
A fourth uncommitted op-amp can be used as a gain stage, buffer amplifier, or to
raise the order of the low-pass, high-pass, or band-pass functions. The uncommitted
391
HP NC BP NC LP NC +15 V DC
out 3 14 out 13 7 out 5 10 4
100 kn
R,n 10 kn 1000 pF 1000 pF

2
1 11 BUF
Ra o----1 out
100 kn 100kn
.100 kn
9 6 12
GND NC -js voe
(a)
Ra 16
R,n 2 15
HP out 3 14
v+ 4 FLT-U2 l3 SP out
(Top view)
LP out 5 12 v-
6 11 BUF out (cl
7 10
8 9 GND
(bl
Figure 10-1 (a) FLT-U2 universal filter block diagram. (b) Connection diagram. (c)
Ceramic 16-pin DIP. (Courtesy of Datel-Intersil.)
392
op-amp can also be used to realize the notch and all-pass functions. The important
characteristics of the FLT-U2 are the following:
Frequency range 0.001 Hz to 200 kHz

Figure of merit (Q) range 0.1 to 1000
Frequency accuracy ±5%
Voltage gain 0.1 to 1000
Input impedance 5MQ
Operating voltage range I ±5 to ±18 V
Unity gain bandwidth 3MHz
Slew rate 1 V/µs
Frequency tuning is accomplished by using two external resistors and Q tuning

by using a third resistor. In addition, by using the FLT-U2 any of the filter types,
such as Butterworth, Chebyshev, or Bessel, may be designed by proper selection of
external components.
10-2.1 Design Procedure
In the design procedure that follows, it is assumed that the gain of the desired filter
function is unity. For simplicity, Q is assumed to be larger than 1. Figure 10-2 shows
the relative gains of the three simultaneous filter outputs assuming that the band-pass
gain is set to unity (0 dB). From this figure it is clear that the low-pass gain is always
10 dB higher than band-pass gain, and high-pass gain is always 10 dB lower than
band-pass gain.
In following the design steps listed below, refer to Figure 10-3.
Low-pass
+10
aJ
T.l
-10
c
'iii
(!) -20
-30
-40
0.1 0.5 5.0 10.0
Relative frequency
Figure 10-2 Relative gains of simultaneous filter outputs (Q = I).
Sec. 10-2 Universal Active Filter 393

0
a..
....J I
I u.
a.
".l...
UT
I
I
.,
cc
e,
al I (")
I
u.
.l...
u, a.
§
I
1---<t---t---
.
cc
a.. (")
J:
11:, ~
a.
.,, ~
.><
; 8 0
0
M
cc
I r£
> a aa
,;
.s c
-
.: c z ·-
394
1. For a desired function-low-pass, high-pass, or band-pass-use Table 10-1 to
select an appropriate filter configuration for inverted or noninverted output.
TABLE 10·1 FILTER CONFIGURATIONS
Configuration LP HP BP
Inverting input Inverted Inverted Noninverted

Noninverting input ljoninverted Noninverted Inverted
Note that the low-pass, high-pass outputs are in phase.

For an inverting configuration, follow this step; otherwise, go to step 3. Using
the desired value of Q, calculate R1 and R3 from Table 10-2. (R2 is open.)
TABLE 10-2 INVERTING CONFIGURATIONS
R1 R3
Low-pass lOOkn lOOkn

(3.80)(Q) - 1
High-pass lOkn lOOkn
(6.64)(Q) - 1
lOOkQ
Band-pass (Q)(31.6 kn)
(3.48)(Q)
3. Follow this step if a noninverting configuration is to be used; otherwise, go to

step 4. Calculate R2 and R3 values from Table 10-3, using the desired value of
Q. (R1 is open.)
TABLE 10-3 NONINVERTING CONFIGURATIONS
Low-pass 3t6kn lOOkQ

-Q- (3.16)(Q) - 1
High-pass 31.6 icn lOOkO
Q (0.316)(Q) - 1
100k(l
Band-pass lOOkO
(3.48)(Q) - 1
\
4. Using the desired value of resonant frequency /1, which is the center frequency
for band-pass and the cutoff frequency for low-pass or high-pass, calculate R4
and R, values from the equation
R4- = R, = (5.o3)(l0') ohms (10-1)
!1
where /1 is either
.
the center frequency or cutoff frequency. expressed
. in hertz.

For a band-pass filter the center frequency can be varied without affecting
bandwidth by varying Rs, with R4 fixed.
5. If /1 < 50 Hz, the internal 1000-pF capacitors shoulci be shunted with equal
value external capacitors across pins 5 and 7 and 13 and 14 (see Figure 10-3).
R4 and Rs values are then computed from the equation
. ohms (10-2)
where C is the total capacitance in pF, that is, the sum of the external capaci-
tance across pins 5 and 7 or across pins 13 and 14 in pF, and the internal 1000-pF
capacitor. The value /1 is in hertz.
6. The procedure described above is based on unity gain output for the desired
function. However, if additional gain is required, the fourth uncommitted op-
amp should be used as an inverting or' noninverting gain stage following the
selected output (see Figure 10-4). Also, as shown in Figure 10-5, the order of
the filter function can· be raised by adding a capacitor to the gain stage.
The resonant frequency tuning is done by varying R4 or Rs resistors while the

figure of merit Q tuning is done by adjusting input resistors R1, R2, or R3, depending
on the filter configuration desired (see Figure 10-3). When tuning the filter and checking
Rs R1
Vin
10
11 R7
Vout = -R Vin
s
R8 = Rs II R1
l
(a)
Rs R7
10
11
V out =(1 + :: ) V;n
.V;n
(b)
Figure 10-4 Uncommitted op-amp gain configurations. (a) Inverting. (b) Non-
inverting.
396 Specialized IC Applications Chap. 10

11 · R7 /R6
vout = - j2rrfC3 R7 + 1 V;n
(al
(b)
Figure 10-5 Using the uncommitted op-amp to raise the order of low-pass
function. (a) Inverting configuration. (b) Noninverting configuration.
it over its frequency range, care should be exercised so that clipping does not occur in
the filter. If clipping occurs, the input signal level should be reduced. For best perfor-
mance, all external resistors should be 1 % metal film, and capacitors should be a
stable type such as tantalum and Mylar. Higher-order filters can be made by using
cascaded FLT-U2 stages. To construct a notch filter, the simplest method is to use the
FLT-U2 as an inverting band-pass filter and then to sum the output of the band-pass
filter with the input signal by means of the uncommitted op-amp.
The FLT-U2 universal filter may be used in audio tone signaling, data acquisi-
tion, and feedback control systems.
Example 10-1
The FL T-U2 is to be used as a second-order inverting Butterworth low-pass filter
with a de gain of 5, cutoff frequency of 2 kHz, and Q = 10. Determine the values of
the external components.
Solution. The values of external components can be determined by following these
design steps:

1. According to Table 10-1, the inverting configuration would normally be used
to give an inverting low-pass output. However, to obtain a gain of 5, an inverting
uncommitted op-amp has to be used; hence the noninverting filter configuration
must be used.
2. From Table 10-3, using Q = 10,
316 kn
R,. = 10 = 31.6 kn
R3 = (3.1~~1~ _ 1 = 3.27 kn (use 3.3 kn)
R1 = open
3. Substituting jj = 2 kHz in Equation (10-1), we get
(5.03)(107)
R1, = R, = (2)(l03) = 25.15 kn
(Use R4 = R, = 24.9 kn.)
4. The final step is to use the uncommitted op-amp as an inverting amplifier with
a gain of 5 [see Figure 10-4(a)]. Let R6 = 1.8 kn; then R7 = (5)(1.8 kn) =
9.0 kn (use u ro-in potentiometer). R8 = R6 II R1 = 1.5 Idl. The complete
circuit is shown in Figure 10-6. ·
Example 10-2
Using the FLT-U2, design a second-order inverting Butterworth band-pass filter with
center frequency /1 = 5 kHz and Q = 10.
Solution. The values of external components needed to use the FLT-U2 as a band-
pass filter can be determined by following these design steps:
1. According to Table 10-1, the noninverting configuration is chosen to obtain an

inverted band-pass output. ·
2. Using Q = 10, the values of R2 and R3 from Table 10-3 are
R2 = lOOkn
100 kn
R3 = (3.48)(10) -. 1 = 2.96 kn
(use R3 = 2.7 kn). However,
Ri = open
3. Since j] = 5 kHz, from Equation 10-1,
(5.03Xl07) ,...,
R4 = R, = (5)(10l) = 10 kn
For accurate circuit operation, Ri, may be a fixed io.sn resistor while R, may
be a 10-kn potentiometer, so that R, can be adjusted for the exact center fre-
quency of 5 kHz. I
The complete circuit is shown in Figure 10-7.
Example 10·3
Using the FLT-U2, design a notch filter with 5-kHz notch-out frequency and Q-= 10.
Solution. As mentioned earlier, the FLT-U2 can be used as a notch filter by summing
the inverted output of the band-pass filter designed in Example 10-2 with the input

>
&
> >
It) ~
~
Cl)
...... ...I
It)
u,
c.
§...
N
::,
~
u..
u..
c.
s
...
8
.
a:
399
·,
R4
10 kn
Rs
10 kn
3 14 7
13 vou,
(Band-pass
R2 FLT·U2 output)
too kn
9 4 12
R3 2.1 kn
+15 V -15 V
Figure 10-7 Band-pass filter of Example 10-2.
signal by means of the uncommitted op-amp (see Figure 10-8). The use of the band-
pass filter of Example 10-2 is possible here because its 5-kHz center frequency and Q
value are equal to the 5-kHz notch-out frequency and the Q value of the notch filter.
Since no extra gain is required, the feedback resistance and the input resistances of the
uncommitted op-amp used as the summing amplifier must be equal in value. Therefore,
let
R6 = R7 = R8 = 10 k!l
Then
R9,..., R6 IIR7 IIR8 = 3.3 k!l
Figure 10-8 shows the complete diagram of the notch filter.
Ra
10 kn
Rs
R4
10 kn
Ra
10 kn
3 14 7 13 10
11 Vout
(Notch
FLT-U2 output)
R2
6
rnokn
s, 4 12
+
R3 R9
2.1 kn 3.Jkn
+15V -15V
Figure 10-8 Notch filter of Example 10-3.

10-3 TIIE 555 TIIIIIER
One of the most versatile linear integrated circuits is the 555 timer. Signetics Corpora-
tion first introduced this device as the SE/NE 555 in early 1970. Since its debut, the
device has been used in a number of novel and useful applications. A sample of these
applications includes monostable and astable multivibrators, de-de converters, digital
logic probes, waveform generators, analog frequency meters and tachometers,
temperature measurement and control, infrared transmitters, burglar and toxic gas
alarms, voltage regulators, electric eye~, and many others. The 555 is' a monolithic
timing circuit that can produce accurate and highly stable time delays or oscillation.
In other words, the timer basically operates in one of the two modes: either as a
monostable (one-shot) multivibrator or as an astable (free-running) multivibrator. The
device is available as an 8-pin metal can, as an 8-pin mini DIP, or a 14-pin DIP.
Figure 10-9 shows the connection diagram and the block diagram of the SE/NE 555
timer. The SE555 is designed for the operating temperature range -55 to +125°C,
while the NE555 operates over a temperature range of O to + 70°C. The important
features of the 555 timer are these: it operates on + 5 to + 18 V supply voltage in both
free-running (astable) and one-shot (monostable) modes; it has an adjustable duty
cycle; timing is from microseconds through hours; it has a high current output; it can
source or sink 200 mA; the output can drive TTL and has a temperature stability of
50 parts per milJion (ppm) per degree Celsius change in temperature, or equivalently
0.005 %/°C. Like general-purpose op-amps, the 555 timer is reliable, easy to use, and
low cost.
The next several sections explain the operation of the 555 timer as a monostable
and astable multivibrator; a few simple applications using these two modes are then
presented.
·10-3.1 The 555 as a Monostable Multivibrator
A monostable multi vibrator, often called a one-shot multivibrator, is a pulse-generating

circuit in which the duration of the pulse is determined by the RC network connected
externally to the 555 timer. In. a stable or standby state the output of the circuit is
approximately zero or at logic-low level. When an external trigger pulse is applied,
the output is forced to go high (~ Vee). The time the output remains high is deter-
mined by the external RC network connected to the timer. At the end of the timing
interval, the output automatically reverts back to its logic-low stable state. The output
stays low until the trigger pulse is again applied. Then the cycle repeats. The mono-
stable circuit has only one stable state (output low), hence the name monostable.
Normally, the output. of the monostable multivibrator is low.
Figure 10-lO(a) shows the 555 configured for monostable operation. To better
explain the circuit's operation, the internal block diagram is included in Figure
10-lO(b).
Before proceeding with the operation of the 555 timer as a monostable multi-
vibrator, it is important to examine its pin functions. The pin numbers used in the
following discussion refer to the 8-pin mini DIP and 8-pin metal can packages [see
Figure 10-9(a)].
Sec. 10-3 The 555 Timer 401

Ground , • 8 +Vee
Trigger 2 7 Discharge
555
Output 3 6 Threshol(I
Reset 4 5 Control voltage
(al
Vee Control
voltage
8 5
v:
R
4
Threshold
6
,
Comparator
lVcc
Reset
R
'iVcc
Comparator
2 Trigger
R
7
Discharge
Flip-
flop
Output
stage
3
Output Ground
(bl
Figure 10-9 (a) 555 timer connection diagram, (b) Block diagram. (Courtesy of
Signetics Corp.)
Pin 1: Ground. All voltages are measured with respect to this terminal.
Pin 2: Trigger. The output of the timer depends on the amplitude of the external
trigger pulse applied to this efin. The output is low if the voltage at this pin is
greater than i Vee· However, when a negative-going pulse of amplitude larger
~an-! Vee is applied to this pin, the comparator 2 output goes low, which in tum
switches the output of the timer high [see Figure 10-9(b)]. The output remains
high as long as the trigger terminal is held at a low voltage.
Pin 3: Output. There are two ways a load can be connected to the output

+Vee
8 4 Reset RA
+ l_[ Trigger 7
Input 2 c
O 555 6
Output 3
5
0.01 µF
(a)
+Vee
10µF
i + I ',I
I I
Decoupling C3 I
I
RA capacitor I
R 5kf2 v ••, I I
I
6 I
4 J
Threshold
Control 5 iVcc Reset
voltage
R 5kf2
Flip-
flop I
Normally~ R
~ Vee "on" load L
2
Trigger I
:ulnput I
7 I
Discharge I
Output 3 I
R 5kf2 stage
a, Output ~
c Normally RL
1 Ground "off" load
'O
lb)
Trigger input ---u T==w tJ :~cc
I I
I I I
Output waveform ---'
~tp~
Capacitor voltage I
I
I
I
(c)
Figure 10-10 (a, b) 555 connected as a monostable multivibrator. (c) Input and output wave-
forms.
403
terminal; either between pin 3. and ground (pin l) or between pin 3 and supply
voltage + Vcc (pin 8) [see Figure 10-lO(b)]. When the output is low, the load
i current flows through the load connected between pin 3 and + Vee into the
output terminal andis called the sink current. However, the current through the
grounded load is zero when the output is low. For this reason, the load con-
nected between pin 3 and + Vcc is called the normally-on load and that connected
between pin 3 and ground is called the normally-off load. On the other hand,
when the output is high, the current through the load connected between pin 3
and + Vee (normally-on load) is zero. However, the output terminal supplies
current to the normally-off load. This current is called the source current. The
maximum value of sink and source current is 200 mA.
Pin 4: Reset. The 555 timer can be reset (disabled) by applying a negative pulse
to this pin. When the reset function is not in use, the reset terminal should be
connected to + Vee to avoid any possibility of false triggering.
Pin 5: Control voltage. An external voltage applied to this terminal changes the
threshold as well as the trigger voltage [see Figure 10-lO(b)]. In other words, by
imposing a voltage on this pin or by connecting a pot between this pin and
ground, the pulse width of the output waveform can be varied. When not used,
the control pin should be bypassed to ground with J 0.01-µF capacitor to
prevent any noise problems.
Pin 6: Threshold .. This is the noninverting input terminal of comparator 1,
which monitors the voltage across the external capacitor [see Figure 10-lO(b)].
When the voltage at this pin is ;;::::: threshold voltage i Vee, the output of com-
parator 1 goes high, which in turn switches the output of the timer low.
Pin 7: Discharge. Thispin is connected internally to the collector of transistor
Q1, as shown in Figure 10-lO(b). When the output is high, Q1 is off and acts as
an open circuit to the external capacitor connected across it. On the other hand,
when the output is low, Q1 is saturated and acts as a short circuit, shorting out
the external capacitor to ground.
Pin 8: + Vee· The supply voltage of + 5 V to + 18 is applied to this pin with
respect to ground (pin 1).
10:-3,1 (a) Monostable operation. According to Figure 10-lO(b), initially

when the outputis low, that is, the circuit is in a stable state, transistor Q1 is on and
capacitor C is shorted out to ground. However, upon application of a negative trigger
pulse.to pin 2, transistor Q1 is turned off, which releases the short circuit across the
external capacitor C and drives the output high. The capacitor C now starts charging
up toward Vee through R,4. However, when the voltage across the capacitor equals
i Vee,. comparator l's output switches from low to high, which in turn drives the
output to its low state via the output of the flip-flop, At the same time, the output of
the flip-flop turns transistor Q 1 on, and hence capacitor C rapidly discharges through
the transistor. The output of the monostable remains low until a trigger pulse is again
applied. Then the cycle repeats. Figure 10-lO(c) shows the input trigger, output
voltage, and capacitor voltage waveforms. As shown here, the pulse width of the
input trigger must be smaller than the expected pulse width of the output waveform.

Also, the trigger pulse must be a negative-going input signal with an amplitude larger
than !Vee•
The time during which the output remains high is given by
tp = 1.1R,4C seconds (10-3)
where RA is in ohms and C is in farads. Figure 10-11 shows a graph of the various
combinations of RA and C necessary to produce desired time delays. Note that this
graph can only be used as a guideline and gives only the approximate value of R,4
and C for a given time delay. ,
Once triggered, the circuit's output will remain in the high state until the set
time tp elapses. The output will not change its state even if an input trigger is applied
again during this time interval tP. However, the circuit can be reset during the timing
cycle by applying a negative pulse to the reset terminal. The output will then remain
in the low state until a trigger is again applied.
Often in practice a decoupling capacitor (10 µF) is used between 1-~e {pin 8) +
and ground (pin I) to eliminate unwanted voltage spikes in the output waveform.
Sometimes, to prevent any possibility of mistriggering the monostable multivibrator on
positive pulse edges, a waveshaping circuit consisting of R, C,., and diode D is con-
nected between the trigger input pin 2 and Vee pin 8, as shown in Figure 10-12. The
100.--------------.------------~-------------.-------------------------------------~
10
LL
3-
o
Cl>
o
c:
a
-~
Q.
c:3 0. 1
0.01
0.001..._ ....._. ~------------------------~------------------------'

10 IJS 100 µs 1 ms 10 ms 100 ms 1 s 10 s
Time
delay-
tp: 1.1 RAC
Figure 10-11 Determining R,4 and C values for various time delays.

+Vee
r--- -., C + 10 µF
R O
I
I 8 4
3
.T Decou~ling
I ~ capacitor
6
I r I : 2
555 7
lJ lnp~
1 c2 Waveshaping
I
--+---- .....
•
triggar I
L
network J1I --....------_:-3 - 0utput
5
c
0.01 µF
Figure 10-12 Monostable multivibrator with waveshaping network to prevent

positive pulse edge triggering.
values of R and C2 should be selected so that the time constant RC2 is smaller than
the output pulse width t P"
Example 10-4
In the circuit of Figure 10-lO(a), RA = 10 ill, and the output pulse width t P = 10 ms.
Determine the value of C.
Solution. Rearranging.Equation (10-3), we get
- (10)(10-3) - -
C - (1.l)(l04) - 0.909µF = 1 µF
(Notice that approximately the same value can be obtained for C from the time delay
graph of Figure 10-11.)
10-3.2 Monostable Multivibrator Applications
10-3.2(a} Frequency divider. The monostable multivibrator of Figure 10-

lO(a) can be used as a frequency divider by adjusting the length of the timing cycle
tP with respect to the time period T of the input trigger signal applied to pin 2. In
order to use the monostable multivibrator as a divide-by-2 circuit, the timing interval
tP must be slightly larger than the time period T of the input trigger signal, as shown
in Figure 10-13. By the same concept, in order to use the monostable multivibrator as
a divide-by-J circuit, tP· must be slightly larger than twice the period of the input
trigger signal, and so on.
The frequency-divider application is possible because the monostable multi-
vibrator cannot be retriggered during the timing cycle.
I
Example 10-5 .
The circuit of Figure 10-lO(a) is to be used as a divide-by-Z network. The frequency of
the input trigger signal is 2 kHz. If the value of C = O.Ql µF, what should be the value
of R,4?
Solution. For a divide-by-2 network, t P should be slightly larger than T. Let
tp = 1.2T

Therefore,
1
t" = (1.2) 2 kHz= 0.6 ms
Rearranging Equation (10-3) yields
(0.6)(10-3)
R,. = (1.l)(lO-a) = 54.5 k!l
A combination of a 10-k!l fixed resistor and a 50-ill potentiometer may be used for
R,.. The input and output waveforms are shown in Figure 10-13.
Input Output 1No

Output
trigger triggered change triggered
Vpi------.ur
OV -------
T = 0.5 ms-t-1
2 cycles ---+J
1
0 0.5 1.0 1.5 :t (ms)
I
Output I
I
voltage I
I
ovi------4 tp = 0.6 ms
1 cycle
0 1.0 1.5 t (ms)
I· 1.0ms -1
Figure 10-13 Input and output waveforms of the monostable multivibrator as a
divide-by-Znetwork.
10-3.2(b) Pulse stretcher.. This application makes use of the fact that the
output pulse width (timing interval) of the monostable multivibrator is of longer
duration than the negative pulse width of the input trigger. As such, the output pulse
width of the monostable multivibrator can be viewed as a stretched version of the
narrow input pulse, hence the name pulse stretcher. Often, narrow-pulse-width signals
are not suitable for driving an LED display, mainly because of their very narrow pulse
widths. In other words, the LED may be flashing but is not visible to the eye because
its on time is infinitesimally small compared to its off time. The 555 pulse stretcher can
be used to remedy this problem.
Figure 10-14 shows a basic monostable used as a pulse stretcher with an LED
indicator at the output. The .LED will be on during the timing interval t" = 1.lR,.C,
which can be varied by changing the value of R,. and/or C. ·
10-3.3 The 555 as an Astable Multivibrator

An astable multivibrator, often called a free-running multivibrator, is a rectangular-
wave generating circuit. Unlike the monostable multivibrator, this circuit does not
require an external trigger to change the state of the output, hence the name free-
running. However, the time during which the output is either high or low is determined
by the two resistors and a capacitor, which are externally connected to the 555 timer.
10-3.3(a) Astable operation. Figure I0-15(a) shows the 555 timer
connected as an astable rnultivibrator. Initially, when the output is high, capacitor

RA
8 4
2
7
~rigger input
555 6
3
nnOutput
5
c 1.0 µF
c,
LED 0.01 µF
FLV117
Figure 10-14 Monostable multivibrator
as a pulse stretcher.
+Vcc=+5V
RA 2.2 k.11
8 4
7
3
555 Output
6
Ra 3.9 k.11
2 5
c,
C i0.1 µF
(al
... ., ;;;: v cc 1------,

......-
:,
0. "'
:,
Cl
0 !;
ov ----------
Charging Discharging
(bl
Figure 10-15. 555 as an astable multivibrator. (a) Circuit. (b) Voltage across
capacitor and output voltage waveforms.
408
C starts charging toward Vee through RA and RB. However, as soon as voltage across
the capacitor equals f Vee, comparator 1 triggers the flip-flop, and the output switches
low [see Figure 10-15(b)]. Now capacitor C starts discharging through RB and transistor
Q 1• When the voltage across C equals t Vee, comparator 2's output triggers the flip-
flop, and the output goes high. Then the cycle repeats. The output voltage and
capacitor voltage waveforms are shown in Figure 10-15(b).
As shown in this figure, the capacitor is periodically charged and discharged
between lVee and {Vee, respectively. The time during which the capacitor charges
from { Vee to i Vee is equal to the time the output is high and is given by
t, = 0.69(R,. + RB)C (10-4a)
where R,. and RB are in ohms and C is in farads. Similarly, the time during which the
capacitor discharges from j Vee· to { Vee is equal to the time the output is low and is
given by
(10-4b)
where RB is in ohms and C is in farads. Thus the total period of the output waveform is
T = le + td = 0.69(R,. + 2RB)C (10-5)
This, in turn, gives the frequency of oscillation as
1 1.45
I, = T = (RA + 2RB)C (10-6)
Equation (10-6) indicates that the frequencylo is independent of the supply voltage·
Vee· The frequency of oscillation (free-running frequency) lo can also be found by
Figure 10-16. ;
Often the term duty cycle is used iu conjunction with the astable multivibrator.
The duty cycle is the ratio of the time td during which the output is low to the total
time period T. It is generally expressed as a percentage. In equation form,
% duty cycle = f x 100

- R,. ~B 2RB (lOO) (10-7)
The duty- cycle of the square wave is 50 %. This means that, according to Equation
(I 0-7), the as table multivibrator shown in Figure 10-15(a) will not produce square-
wave output unless the resistance R,. = 0 n. However, there is a danger in shorting
resistance Rj to zero. With R,. = 0 n, terminal 7 is connected directly to+ Vee· When
the capacitor discharges through RB and Q1 (pin 7), an extra current is supplied to
Q1 by Vee through a short between terminal 7 and+ Vee, which may damage Q1 and
hence the timer. Fortunately, an alternative is available which is explained in the
section on astable multivibrator applications.
Example 10-6
In the astable multivibrator of Figure 10-15(a), R,. = 2.2 k!l, RB= 3.9 k!l, and C =
0.1 µF. Determine the positive pulse width tc, negative pulse width td, and free-running
frequency f..
Sec. 1 0-3 The 555 Timer 409

Solution. From Equations (10-4a) and (10-41:>),
,. = (0.69)(2.2Jdl + 3.9 Jdl)(0.1)(10-6)
= 0.421 ms
Id = (0.69)(3.9 Jdl)(0.1)(10-6)
= 0.269ms
Therefore,
1
lo = (0.421 + 0.269)(10-3) = 1.45 kHz
Using C = 0.1 µF and RA+ 2RB = 10 Jen, the free-running frequency can also be
found from the graph in Figure 10-16, as indicated by point A. Note that the graph
uses the log-log scale; that is, vertical and horizontal axes are marked in logarithmic
scales.
0:'1 10 100 1 k 10 k 100 k

Free-running frequency (Hz)
Figure 10-16 Free-running frequency versus R,4, RB, and C.

I
10-3.4 Astable Multivibrator Applications
10·3.4(a) Square·wave oscillator. Without reducing RA= on, the

astab1e multivibrator can be used to produce a square-wave output simply by con-
necting diode D across resistor RB, as shown in Figure 10-17. The capacitor C charges
through RA and diode D to approximately j Vee and discharges through R8 and
410 SpecializedIC Applications Chap. 10

+Vcc=+5V
+
10-µF
C3
f
~
'
Decouplinq
capacitor
8 4
I 555 3 ~5V
Output OV
2 5
Figure 10-17 Astable multivibrator as a square-wave oscillator.
terminal 7 (transistor Q 1) until the capacitor voltage equals approximately j Vee; then
the cycle repeats. To obtain a square-wave output (50% duty cycle), RA must be a
combination of a fixed resistor and potentiometer, so that the potentiometer can be
adjusted for the exact square wave.
10-3.4(b) Free-running ramp generator. The astable multivibrator can

be used as a free-running ramp generator when resistors RA and RB are replaced by
a current mirror. Figure 10-18(a) shows an astable .multivibrator configured to
perform this function. The current mirror starts charging capacitor C toward
Vee at a constant rate. When voltage across C equals j Vee, comparator 1 turns
transistor Q, on and C rapidly discharges through transistor QI' Refer to Figure
10-9(b). However, when the discharge voltage across C is approximately equal to
f Vee, comparator 2 switches transistor Q, off, and then capacitor C starts charging
up again. Thus the charge-discharge cycle keeps repeating. The discharging time of
the capacitor is relatively negligible compared to its charging time; hence, for all
practical purposes, the time period of the ramp waveform is equal to the charging
time and is approximately given by
T = (Vee)(C) (10-8a)
3Ie
where le = (Vee - VBE)I R = constant current in amperes and C is in farads. There-
fore, the free-running frequency of the ramp generator is
fo = (V:~(C) (10-8b)
Figure 10-18(b) shows the generator's output waveform. For the analysis and design
of the current mirror, the reader may refer to Section 1-11.
Example 10-7
Referring to the circuit of Figure 10-18(a), determine the frequency of the free-
running ramp generator if R is set at 10 ill. Assume that the VBE = VD1 = 0.7 V.
Sec. 1 o-s The 555 Timer 411

+Vcc'"+SV
R Vo,,-----,.------+--------+ .... 10-µF

-----.
2.7 kn 1 Mn
Dl
Ve
I le
T 8 4
c
3 i
-
D r
ecou? mg
capacitor
4.3 V- le 7
555
Output._ 6....
Ve
(a)
V3
~ s vi----------- .... --- -
Vee
Voltage
at pin 3
ov....._ __ ~,._ __ _..,.. ,..____ ~.~----
11 t
,1
11
II
11
11
11
,,
'1
Ve --~3.3 V
Output
voltage
-- • 1.67 V
t.~ 1-<f-(d
1
r--1
(b)
Figure 10-18 (a) Free-running ramp generator circuit. (b) Output waveform.
Solution: By Equation (10-Sb),.

(3)[5 - 0.7]
lOk
lo =. (5)(5)(10_8) = 5.16 kHz
10-4 PHASE-LOCKED LOOPS

Although the evolution of the phase-locked loop began in the early 1930s, its cost
outweighed its advantages at first. With the rapid development of integrated-circuit
technology, however, the phase-locked loop has emerged as one of the fundamental
building blocks in electronics technology. The phase-locked-loop principle has been
used in applications such as FM (frequency modulation) stereo decoders, motor speed

controls, tracking filters, frequency synthesized transmitters and receivers, FM
demodulators, frequency shift keying (FSK) decoders, and a gen1..!~1tion of local
oscillator frequencies in TV and in FM tuners. Today the phase-locked loop is even
available as a single package, typical examples of which include the Signetics' SE/NE
560 series (the ~60, 561, 562, 564, 565, and 567). However, (or more economical
operation, discrete !Cs can be used to construct a phase-locked loop.
10-4.1 OperatingPrinciples
I
Figure 10-19 shows the phase-locked loop in its basic form.· As illustrated in this
figure, the phase-locked loop consists of:
1. A phase detector
2. A low-pass filter
3. A voltage-controlled oscillator
Forward path
Phase Low-pass Voltage-

flN
detector filter controlled ----fOllT
Input oscillator Output
frequency frequency
Feedback path
Figure 10-19 Block diagram of a phase-locked loop.
The phase detector, or comparator, compares the input frequency.fiN with the
feedback frequency /ouT· The output of the phase detectoris proportional to the phase
difference betweenfiN and/ouT· The output voltage of a phase detector is a de voltage
and therefore is often referred to as the error voltage. The output of the phase detector
is then applied to the low-pass filter, which .removes the high-frequency noise and
produces a de level. This de level, in turn, is the input to the voltage-controlled oscil-
lator (VCO). The filter also helps in establishing the dynamic characteristics of the
PLL circuit. The output frequency of the VCO is directly proportional to the input
de level. The VCO frequency is compared with the input frequencies and adjusted
until it is equal to the input frequencies. In short, the phase-locked loop goes through
three states: free-running, capture, and phase lock.
Before the input is applied, the phase-locked loop is in the free-running state.
Once the input frequency is applied, the VCO frequency starts to change and the
phase-locked loop is said to be in the capture mode. The VGO frequency continues
to change until it equals the input frequency, and the phase-locked loop is then in
the phase-locked state. When phase locked, the loop tracks any change in the input
frequency through its repetitive action.
Sec. 10-4 Phase-Locked Loops 413

Before studying the specialized phase-locked-loop IC, we shall consider the
discrete phase-locked loop, which may be assembled by combining a phase detector, a
low-pass filter, and a voltage-controlled oscillator (see Figure 10-19).
10-4.1(a) Phase detector. The phase detector compares the input fre-
quency and the VCO frequency and generates a de voltage that is proportional to the
phase difference between the two frequencies. Depending on the analog or digital
type of phase detector used, the PLL is either called an analog or digital type, respec-
.
tively. Even though most of the monolithic PLL integrated circuits use analog phase
detectors, the majority of discrete phase detectors in use are of the digital type mainly
because of its simplicity. For this reason, we shall consider only digital-type phase
detectors here.
A double-balanced mixer is a classic example of an analog phase detector. On
the other hand, examples of digital phase detectors are these:
1. An exclusive-OR phase detector

2. An edge-triggered phase detector
3. A monolithic phase detector (such as type 4044)
Figure 10-20(a) shows the exclusive-OR phase detector that uses an exclusive-
OR gate usch as CMOS type 4070. The output of the exclusive-OR gate is high only
when.fiN or fouT is high, as shown iri· Figure 10-20(b).
In this figure, fs« is leading/ otrr by ¢, (phi) degrees; that is, the phase difference
between frn and fouT is¢, degrees. The de output voltage of the exclusive-OR phase
detector is a function of the phase difference between its two inputs. ·Figure 10-20(c)
shows de output voltage as a function of the phase difference between hN and fouT·
This graph indicates that the maximum de output voltage occurs when the phase
difference is 1t radians or 180°. The slope of the curve between O and n radians is the
conversion gain k , of the phase detector. For example, if the exclusive-OR gate uses
a supply voltage Vee= 5 V, the conversion gain k, is
5V
k , . = -n = 1.59 V/rad
The exclusive-OR type ofphase detector is generally used if the hN and fouT are
square waves. The edge-triggered phase detector, on the other hand, is preferred if
thefrn andfouT are pulse waveforms with less than 50% duty cycles.
Figure 10-2I(a) shows the edge-triggered type of phase detector using an R-S
(reset-set) flip-flop. The R-S flip-flop, in turn, is formed from a pait of cross-coupled
NOR gates, such as the CD400l. The Jl-S flip-flop is triggered; that is, the output of
the detector changes its logic state on the positive (leading) edge of the inputs hN and
fouT [see Figure 10-2l(b)]. The graph of de output voltage versus phase difference
betweenfrn andfouT is shown in Figure 10-21(c).
The advantages of the edge-triggered type phase detector over the exclusive-OR
type of detector are: ( l) the de output voltage is linear over 2tt radians or 360°, as
opposed to tt radians or 180° in the case of the exclusive-OR detector; and (2) the

~:,
s-:, >- ..J J: J: ..J ::.:
Cl.
~~ c:
0
o·-
..J J: 'i
c:
II II 0
~:, al ..J J: ..J J:
..J J: ·e
QI N~
0. >
c:
-c: < ..J ..J J: J:
...II
0
s
QI
g. J;IN tl 5
(ii "'.,_
c: c: 0
t Cl) -0
~! c:
~ ~ 1l "'z
~
..
-e
51
s:"'
Cl.
--
>
~IN
M
..
>"' ... ~"' ...~ 0
:,
(.)
O S-.t:
}IN
:, 0 >
0 > Ill
8
>
>
0
0
al • -c• >-• >-
.. .. <. al
>
Lt> 'tJ
c:
:,
------- ~
Lt>
... oe
0
-
M
• M N 0
en co II
0
II
0 !il
> >
-----------cl;
...
5.~
c: "'
·-:- en
NO:
'i o
"'> .,----.. . -~T
:,
-C'
,...
o'iii
:,
----~ .....
~]
0"'
o
-_J_
N .,. ,...
-~ ~
8
...
:,
s-:,
M Lt> co 0
II
5 u
_o -e
>
.£ al > >-"' <:"' al "' >
!il
415
A,
14
2 Voe "S" input
81 13 f IN Output
3 84 V de
v, 12
4 A4
Y2 11
5 Y4
A2 10
6 Y3
82 "R" input
9
7 83 fOVT
Vss 8
A3
CD4001 Quad 2-input NOR gate
V 00 = 3 V to 1 5 V
V 55 = Ground
.(a)
____.n Fl.L
Output
I I
0 21r
(b)
DC output
voltage
V CC :!! V sat
.,...... .__, -Slope= conversion gain Ku
.._ _ __._ __ _._ ...__ Phase difference between

0 41r f1N and i0VT
(c)
Figure 10-21 Edge-triggered type phase detector. (a) NOR gate R-S flip-flop connection
diagram. (b) Input and output waveforms. (c.) De output voltage versus phase difference
betweerv/rn and I our.
416
edge-triggered detector also exhibits better capture, tracking, and locking characteris-
tics than the exclusive-OR detector. However, both types of detectors are sensitive
to hormonics of the input signal and changes in the duty cycles offrn and/our·
In a monolithic phase detector IC such as CMOS type 4044, the harmonic
sensitivity and duty cycle problems are absent, since the circuit responds only to
transitions in the input signals. In other words, the phase error and hence the output
error voltage of the monolithic phase detector is independent of the variations in the
amplitude and duty cycle of the input waveforms. Therefore, in critical applications
the monolithic phase detector is prsferred over both the exclusive-OR and edge-
triggered types of phase detectors.
Figure 10-22(a) shows the block diagram of the MC4344/4044 phase detector.
As shown in this figure, the MC4344/4044 consists of two digital phase detectors, a
charge pump, and an amplifier. Phase detector 1 is used in applications that require
zero frequency and phase difference at lock. On the other hand, if quadrature lock is
desired, phase detector 2 can be used. When detector 1 is used in the main loop,
detector 2 can also be used to indicate whether the main loop is in lock or out of lock.
The input/output transfer characteristic curve of phase detector 1 is shown in
Figure 10-22(b). As shown here, the curve is linear over 4n radians or 720° and has a
conversion gain k, of 1.5 V/4n = 0.12 V/rad.
10-4.1 (b) Low-Pass filter. The function of the low-pass filter in the
phase-locked loop is to remove the high-frequency components in the output of the
phase detector and to remove high-frequency noise. More important, the low-pass
filter controls the dynamic characteristics of the phase-locked loop. These charac-
teristics include capture and lock ranges, bandwidth, and transient response. The lock
range is defined as the range of frequencies over which the PLL system follows the
changes in the input frequency frn· An equivalent term for lock range is tracking
range. On the other hand, the capture range is the frequency range in which the PLL
acquires. phase lock. Obviously, the capture range is always smaller than the lock
range.
As the filter bandwidth is reduced, its response time increases. However,
reduced bandwidth reduces the capture range of the PLL. Nevertheless, reduced
bandwidth helps to keep the loop in lock through momentary losses of signal and also
minimizes noise.
The loop filter used in the PLL may be one of the three types shown in Figure
10-23. With the passive filters of Figure 10-23(a) and (b), an amplifier is generally
used for gain._ On the other hand, the active filter of Figure 10-23(c) includes the gain.
10-4.1 (c) Voltage-controlled oscillator. A third section of PLL is the

voltage-controlled oscillator. The VCO generates an output frequency which is
directly proportional to its input voltage. The block diagram of the VCO is shown in
Figure 10-24.
While the SE/NE 566 VCO is discussed in Section 8-18, a typical connection
diagram is repeated in.Figure 10-25 for convenience. The maximum output frequency
of the NE/SE 566 is 500 kHz. For higher output frequency, therefore, integrated
circuits such as Motorola's MC4324/4024 and MC1648 may be used.
Sec. 10-4 Pha5e-Locked Loops 417

Outputs
Input Output
I
U1 01' PU UF A Amplifier input
13 2 4 5 9
Phase-freq
Inputs{: 3 detector
1
Charge 8
Output
pump
Phase-freq
detector
2
6 12 11 10 14
,02 U2, PD OF Yee

GND
'
Outputs Input Output
(a)
2.25
2.00
u
't:J
> 1.75
8,
5 1.50
0
...
>
:, 1.25 Slope = conversion gain KP
...c.
:,
0 1.00
0.75
-271"· 0 +271"
~ Phase difference ( Rad)
lb)
Figure 10-22 (a) MC4344/4044 phase detector block diagram. R, reference

input; V, variable or feedback input; PU, pump-up signal; PD, pump-down
signal; UF, up-frequency output signal; OF, down-frequency output signal. (b)
Its input/output transfer characteristic curve. (Courtesy of Motorola Semicon-
ductor.)
10-4.2 MonolithicPhase-Locke</ Loops
Signetics' SE/NE 560 series are monolithic phase-locked loops. The SE/NE 560, 561,
562, 564, 565, and 567 differ mainly in operating frequency range, power supply
requirements, and frequency and bandwidth adjustment ranges. Only the SE/NE 565
phase-locked loop is discussed here because it is one of the most commonly used
devices of the 560 series.
Figure-10-26 shows the block diagram and connection diagram of the 565 PLL.

R,
Input from Output

phase detector to VCO
(al I (bl
Input from
phase detector
(cl
Figure 10-23 Low-pass filters. (a, b) Passive filters. (c) Active filter.
vco
Input from SE/NE 566 or ---~fOUT
low-pass filter equivalent Output
frequency Figure 10-24 VCO block diagram.
+V
2 R, R2
NE/SE566
~c,
0.01 µF
3 6
C2
~ tp ~{:
Modulating
5
4
Ve le input
R3
Figure 10-25 SE566 VCO connection diagram.
419
+V
10
Low-pass filter
//\
1 C2
lnputo----1---4
2
Phase 1-----t Amplifier
3.6 k.n 7
·.-----,1--__..,___
i---'11· •111··"'
T
Demodulated
output
detector 6
I nputo- --3-+----t ._____, ~ .__
__ __,1------+--1o--- Reference output
Phase comparator _ 5
VCO input <>----te------'
.riri, 0-~ _4+-----.1

vco ini,ut
iC1J..t~~\ \/CO
8 9 /\IV\. 1
R 1 :~ ,T
c --
+V -v
(al
-v
• 14 NC
Input 2 13 NC
Input 3 12 NC
VCO output NE/SE

4 11 NC
565
Phase comparator
5 10 +V
VCO input
Reference output External capacitor

6 9
for VCO.
Demodulated External resistor
output 7 8 forVCO
14-pin DIP package
(b)
Figure 10-26 (a) NE/SE 565 PLL block diagram. (b) Connections diagram.
(Courtesy of Signetics-Corp.)
420
The device is available as a 14-pin DIP package and as 10-pin metal can package. The
important electrical characteristics of the 565 PLL are
Operating frequency range: 0.001 Hz to 500 kHz
Operating voltage range: ± 6 to ± 12 V
Input level required for tracking: 10 mV rms minimum to 3 V peak-to-peak
maximum
Input impedance: 10 kn typically
Output sink current: 1 mA, ty~ically
Output source current: 10 mA, typically
Drift in VCO center frequency CJouT) with temperature: 300 ppmj°C, typically
Drift in VCO center frequency with supply voltage: 1.5 %/V maximum
Triangle-wave amplitude: typically 2.4 V pp at ± 6 V (see block diagram, pin 9)
Square-wave amplitude: typically 5.4 V pp at ±6 V (see block diagram, pin 4)
Bandwidth adjustment range: <±1 to) ±60%
The center frequency of the PLL is determined by the free-running frequency of
the VCO, which is given by the equation
r ~ 1.2 Hz
)OUT= 4R c (10-9)
I I
where R1 and C1 are an external resistor and a capacitor connected to pins 8 and 9,
respectively [see block diagram of Figure 10-26(a).] The VCO free-running frequency
fouT is adjusted externally with R1 and C1 to be at the center of the input frequency
range. Although C1 can be any value, R1 must have a value between 2 and 20 kn. A
capacitor C2 connected between pin 7 and the positive supply (pin 10) forms a first-
order low-pass filter with an internal resistance of 3.6 kn. The filter capacitor c,
should be large enough to eliminate variations in the demodulated output voltage at
pin 7 in order to stabilize the VCO frequency.
The 565 PLL can lock to and track an input signal over typically ± 60 % band-
width with respect to louT as the center frequency. The lock-range IL and capture
range le of the PLL is given by the following equations:
. JL = ± 8fouT Hz (10-10)
v
wherefouT = free-running frequency of VCO (hertz)
+
V = ( V) - (- V) (volts)
and
le=
r
± [ (2n)(3.6)(103){C2)
Jl/2 (10-11)
where C2 is in farads.
The Jock range usually increases with an increase in input voltage but decreases
with an increase in supply voltages. Pins 2 and 3 are the input terminals of the 565
PLL, and an input signal can be direct-coupled, provided that there is no de voltage
difference between the pins and de resistances seen from pins 2·and 3 are equal. A
short between pins 4 and 5 connects the VCO output CJouT) to the phase comparator
and enables the comparator to comparelouT with the input signalf1N.
Sec. 10-4 Phase-locked loops 421

In frequency multiplication applications a digital frequency divider is inserted
between pins 4 and 5, as will be shown below. A de reference voltage at pin 6 is
approximately equal to the de potential of the demodulated output at pin 7. In
applications such as frequency shift keying (FSK), the de reference voltage at pin 6
is used as an input to the comparator. [Refer to Section 10-4.3(b) for an example.]
The lock range of PLL can be decreased with little change in the free-running frequency
of the VCO by connecting a resistance between pins 6 and 7.
Example 10-8
.Referring to the circuit of Figure 10-27(a), determine the free-running frequency
fouT, the lock range fL, and the capture range fc-
+v = +10 v
R, + C2
12 k.n 10µF
C3
10 a 0.001 µF-
7 Demodulated
2
Input output
6 Reference
output
NE565
4
VCO output
3
5
J'l.Il..
-v =-10 V
(al
--------Lock range fl _,
Capture range
----fc---+-1
1.5 k 2.433 k 2.5 k 2.566 k 3.5 k

Frequency (Hz)
(bl
Figure 10-27 (a) Circuit of Example 10-8. (b) Relationship betwecn/ouT.!L, and/c,

Solution. From Equations (10-9) through (10-11),
/ouT = (4)(12)do\oo-a) = 2.5 kHz

• - ±8(2.5)(103) - ±1 kH
JL - (20) - z
(103)
le = ± [ (2n)(3.6)(103)(10)(10-6)
Jl/2 = ±66.49 Hz
The relationship between/ouT,11, and/c is depicted in Figure 10-27(b).
10-4.3 565 PLL Applications
10-4.3(a) Frequency multiplier. Figure 10-28(a) is a block diagram of a

frequency multiplier using the 565 PLL. As shown in this diagram, the frequency
divider is inserted between the VCO and the phase comparator. Since the output of
the divider is locked to the input frequency hN, the VCO is actually running at a
multiple of the input frequency. The desired amount of multiplication can be obtained
by selecting a proper divide-by-N network, where N is an integer. For example, in
order to obtain the output frequency fouT = 5frN, a divide-by-N = 5 network is
needed. Figure 10-28(b) shows this function performed by a 7490 (4-bit binary
counter) configured as a divide-by-5 circuit. In this figure, transistor Q 1 is used as a
driver stage to increase the driving capability of the NE565.
To verify the operation of the circuit, one must determine the input frequency
range and then adjust the free-running frequency fouT of the VCO by means of R1
and C1 so that the output frequency of the 7490 divider is midway within the pre-
determined input frequency range. The output of the VCO now should be 5fm· In
Figure 10-28(b), the output frequency fouT can be adjusted from 1.5 kHz to 15 kHz
by varying potentiometer R1 [see Equation (10-9)]. This means that the input frequency
frn range has to be within 300 Hz to 3 kHz. In addition, the input waveform can either
be sine orsquare and maybe applied to input pins 2 or 3. Figure 10-28(c) shows the
input-output waveforms forfoUT = 5fm· .
Even though supply voltages of ±10 V are used in Figure J0-28(b), the NE565
can be operated on ±5-V supply voltages instead. A small capacitor, typically 1000 pF,
is connected between pins.? and 8 to eliminate possible oscillations. Also, capacitor
C2 should be large enough to stabilize the VCO frequency.
10-4.3(b) Frequency shift_ keying (FSK) demodulator. In computer

peripheral arid. radio (wireless) communications, the binary data or code is trans-
mitted by means of a carrier frequency which is shifted between two preset fre-
quencies. Since a carrier frequency is shifted between two preset frequencies, the
data transmission is said to use a frequency shift keying (FSK) technique.
A very useful application of the 565 PLL is as a FSK demodulator. In the 565
PLL the frequency shift is usually accomplished by driving a VCO with the binary
data signal so that the two resulting frequencies correspond to the logic O and logic 1
states of the binary data signal. The frequencies corresponding to logic 1 and logic O
states are commonly called the mark and space frequencies. Several standards are
used to set the mark and space frequencies. For example, when transmitting teletype-

r-------------------------------------,
I I
I
t1N --1-11~
I Phase Amplifier Low-pass VCO
I
f N f
I comparator filter --, --~ QUT "' .'._ IN
I 565 PLL I
IL---- ----------------------------------J I
+N Network
t0UT (frequency
f IN = N divider) When N = 5,.f0UT = 5 flN
(a)
+V = +10 v----------. 2okn} R,

+ C2
10µF
0.001 µF
Zkn
10 7
2 4 VCO output
NE565
3 Vee= +5 V ---------.
5
5
11 7490
(+5 Network)
-v = -10 v--------'
2 3 6 7 10
(b) -
flN
~---1Cycle--c
• t
four
~-D-D scjj D rl [ • t
(e)
Figure 10-28 Frequency multiplier using the 565. (a) Block diagram. (b) Connection
diagram for multiply-by-5. (c) Input-output waveforms.
424
J
writer information using a modulator-demodulator system (modem for short), a
1070 Hz-1270 Hz (mark-space) pair represents the originate signal, while a 2025 Hz-
2225 Hz (mark-space) pair represents the answer signal.
Figure 10-29 shows a typical block diagram of the AM (amplitude modulation)
and FM (frequency modulation) transmitters and receivers. A simplified diagram
using only an FSK generator and FSK demodulator is shown in Figure 10-30. The
FSK generator is formed by using a 555 as an astable multivibrator whose frequency
is controlled by the state of transistor Q 1• In other words, the output frequency of the
FSK generator depends on the logit state of the digital data input. 150 Hz is one of
the standard frequencies at which the data are commonly transmitted. When the
input is logic 1, transistor Q 1 is off. Under these conditions, the 555 works in its normal
mode as an astable multivibrator; that is, capacitor C charges through RA and Ra
to j Vee and discharges through Ra to -! Vee· Thus capacitor C charges and discharges
alternately between j Vee and 1 Vcc as long as the input is at a logic 1 state. The fre-
quency of the output waveform is given by Equation (10-6):
1 = (RA
0 ~4iRa)C = 1070 Hz
The values of RA, RB, and C are selected so that l represents a mark frequency
0
(1070 Hz). On the other hand, when the input is logic 0, Q1 is on (saturated), which in
turn connects the resistance Re across RA. This action reduces the charging time of
the capacitor and increases the output frequency which is given by Equation (10-6):
lo = (RA 11 R~·~ 2Ra)C = 1270 Hz

By proper selection of resistance Re, this frequency is adjusted to equal the space
frequency.of 1270 Hz. The difference between FSK signals of 1070 Hz and 1270 Hz
is 200 Hz; this difference is called thelrequency shift.
~s shown in Figure 10-30, the output of the 555 FSK generator is then applied
to the 565 FSK demodulator. Capacitive coupling is used at the input to remove a de
Antenna
Input FSK 1070 - 1270.Hz AM or FM

digital serial data -----M generator transmitter
at 150 Hz
(a)
Antenna
Output
ft.Mor FM . FSK ,__ _ __.~ digital serial data
reciever 1070 - 1270 Hz demodulator at 150 Hz
(b)
Figure 10-29 (a) Block diagram of AM/FM transmitter. (b) Receiver,

r------ ... -----i >~ .,,
>
I
tY:! I~ >I
•
~ I +
I
l I
~ ... s I
-5 .s sci"' !: =: I
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cc I ~
........"'
I !i:::,
cc I
I
I
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ci
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I
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)
I I
n ~
L -------,
"- . I C: I ... >I ...
en
t5'.,,
:i. I .,.
0
cc I
I
cS ~"'
ci
-
ci IL-
- _J
..... CII
III N M
s
0 'a c:
'": i
..
-~-
:z:
--------------
t~ Q
.....
M !:
.,, ...
.,,18 cS E"'
d
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..... N
cc< '°
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s
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426
level. As the signal appears at the input of the 565, the loop locks to the input frequency
and tracks it between the two frequencies with a corresponding de shift at the output.
Resistor R1 and capacitor C1 determine the free-running frequency of the VCO,
while C2 is a loop filter capacitor that establishes the dynamic characteristics of the
demodulator. Here C2 must be chosen smaller than usual to eliminate overshoot on
the output pulse. A three-stage RC ladder (low-pass) filter is used to remove the carrier
component from the output. The high cutoff frequency (/8 = 1/2nRC) of the ladder
filter is chosen to be approximately halfway between the maximum keying rate of
150 Hz and twice the input frequency, that is, approximately 2200 Hz. The output
signal of 150 Hz can be made logic compatible by connecting a voltage comparator
between the output of the ladder filter and pin 6 of the PLL. The VCO frequency is
adjusted with R1 so that atfiN = 1070 Hz a slightly positive voltage is obtained at the
output.
10-5 POWER AMPLIFIERS
Small-signal amplifiers are essentially voltage amplifiers that supply their loads with
larger amplified signal voltages. On the other hand, large signal or power amplifiers
supply a large-signal current to current-operated Ioads such as speakers and motors.
In previous discussion the general-purpose op-amp has been emphasized as a
voltage amplifier because it is essentially a small-signal amplifier with a limited output
current capability. For instance, the maximum output current supplied by the 741-
type op-amp is equal to its short-circuit (RL = 0 !l} current, namely 25 mA ideally.
· Obviously, the current supplied by the 741 will decrease with an increase in load. In
audio applications, however, the amplifier is called upon to deliver much higher
current than that supplied by general-purpose op-amps. This means that loads such as
speakers and motors requiring substantial currents cannot be driven directly by the
output of general-purpose op-amps. However, there are two possible solutions avail-
able. One method is to use discrete or monolithic power transistors called power
boosters at the output of the op-amp; a second method is to use specialized ICs
designed as power amplifiers.
10-5.1 Power Amplifiers Using Power Boosters
A simple method of increasing the output current of a general-purpose op-amp is to

connect a power booster in series with the op-amp. Obviously, the output charac-
teristics of this arrangement, such as output current and output impendance, are then
controlled by the choice of the power booster and the configuration in which it is
used. Usually, a discrete power booster is an emitter-follower stage formed QY using a
power transistor, as in Figure 10-31 (a). (Transistors with power dissipation larger
than t W are called power transistors.) Because of its unity gain, the emitter fol-
lower helps to retain the voltage-gain characteristics of the general-purpose op-amp.
In addition, the emitter follower offers a relatively high input impedance; therefore,
it also works as an isolation stage (buffer) between the op-amp and the load. The
input impedance and output current of the emitter follower may be further increased
Sec. 10-5 Power Amplifiers 427

+Vee
RF
+Vee
R1 2
6
3 V'0
RoM = R1
-Vee
8 n load
' ,.
(a)
"
RF
+Vee +15 V
R1
2
6 5 10
3 v· Input
r
0
Output
RL
-Vee -15 V
4
BB
3329/03
Input 5 10 Output
-VEE 7
14-pin DIP , 3329/0'J

package , connect-vn
diagram
(b)
Figure 10-31 Power amplifiers using general-purpose op-amp input stage and
(a) discrete power booster. (b) 3329/03 IC power booster. (Courtesy of Burr-Brown
Research Corporation.)
428
by the use of Darlington power transistors. For increased efficiency, the power booster
is often configured as a push-pull Class B amplifier.
Figure 10-3l(b) shows a typical connection-diagram for the power amplifier
using a general-purpose op-amp and the Burr-Brown 3329/03 monolithic power
booster. The 3329/03, a unity-gain power booster amplifier which does not require
any external components, is designed to be used inside the feedback loop of an
op-amp. It operates over a power supply range of± 12 to ± 18 V. The device has a
Class B output stage which provides output current of± 100 mA at 20 V peak-to-peak
output voltage swing when operated onrsupplies of ± 15 V. In addition, the device
will operate over the temperature range -40 to +85°C without a heat sink. Above
all when the 3329/03 power booster is used with an op-amp, it does not degrade the
frequency response and output characteristics of the op-amp, mainly because of the ·
following electrical characteristics:
Full power frequency = 1 MHz

Small-signal bandwidth = 5 MHz
Input impedance = 10 kn
Open-loop output impedance= 10 n
Another power booster with increased output current, slew rate, and bandwidth
is the Burr-Brown 3553. It has an output current of ±200 mA with a 300-MHz
bandwidth and a slew rate of 2000 VIµs. The 3553 is therefore ideally suited for line
driving applications (50-0 load) in which fast pulses or wideband signals are involved.
For applications such as stepper motor drivers, servomotor drivers, power supplies,
and power DA Cs requiring output voltage up to ±30 V and full output current ±2 A,
the Intersil ICL8063 (16-pin DIP) monolithic power transistor driver and amplifier
is most suitable. The ICL8063 will operate from the outputs of most of op-amps and
devices such as timers and comparators. When used in conjunction with general-
purpose op-amps, external complementary power transistors, and 8 to 10 passive
components (resistors and capacitors), the ICL8063 can deliver more than 50 W to
external loads. It has built-in safe area protection, short-circuit proof protection, and
built-in ± 13-V regulators.
',
10-5.2 Monolithic Power Amplifiers
.,
A variety of monolithic as well as hybrid power amplifiers are commercially available.
Although power amplifiers differ from general-purpose op-amps in delivering various
amounts of power, they are nearly as compact. Because of its wide acceptance,
National Semiconductor's LM380 audio power amplifier is introduced here and
followed by a brief discussion of hybrid power amplifiers with output power up to
IOOW.
10-5.2(a) LM380 power audio amplifier. The National Semiconductor's

LM380 is a power audio amplifier designed to deliver a minimum of 2.5 w· (rms) to
an 8-0 load and hence is ideal for consumer applications. Because of the following
features, the LM380 requires a minimum number of external components:

An internally fixed gain of 50 (34 dB)
Output automatically self-centering to one half of the supply voltage
Output short-circuit proof with internal thermal limiting
A unique input stage allowing inputs to be ground referenced or ac coupled /
In addition, the LM380 has a wide supply voltage range (5 to 22 V), high peak
current capability (1.3 A maximum), high impedance (150 kn), low (0.2 %) total
harmonic distortion (THO), and is available in a standard DIP package. Also, the
LM380 has a bandwidth of 100 kHz typically at PouT = 2 Wand RL = 8 n.
Figure 10-32 shows the connection diagram, block diagram, and schematic
diagram of the LM380. A copper lead frame used with the center three pins (3, 4, 5,
10, 11, and 12) on either side of the DIP package comprises a heat sink [see Figure
10-32(a)]. Therefore, there is no need to use a separate heat sink for the audio amplifier.
LM380 Circuit Description. The schematic diagram of the LM380 shown in
Figure 10-32( c) is composed of four stages: PNP emitter follower, differential amplifier,
common emitter, and quasi-complementary emitter follower. The input stage is an
emitter follower composed of PNP transistors Q 1 and Q2, which drives the PNP
Q3-Q4 differential pair. The choice of PNP input transistors Q1 and Q2 allows the
input to be referenced to ground; that is, input can be direct coupled to either the
inverting (pin 6) or the noninverting (pin 2) terminals of the amplifier.
The current in the PNP differential pair Q3-Q4 is established by Q7, R3, and+ V.
The current mirror formed by transistors Q7, Q8, and associated resistors then estab-
lishes the collector current of Q9• Transistors Q5 and Q6 constitute collector loads for ,
the PNP differential pair. The output of the differential amplifier is taken at the
junction of Q4 and Q6 transistors and is applied as an input to the common-emitter
voltage gain stage.
The common-emitter amplifier stage is formed by transistor Q9 with D1, D2,
and Q8 as a current source load. The capacitor C between the base and collector of
Q9 provides internal compensation and helps to establish the upper cutoff frequency
of 100 kHz at 2 W for 8-n loads. Since Q7 and-Q8 form a current mirror, the current
through D 1 and D2 is approximately the same as the current through R3• In addition,
D 1 and D2 are temperature-compensating diodes for transistors Q 1 0 and Q 11 in that
D1 and D2 have the same characteristics as the base-emitter junctions of Q10 and Q11•
Therefore, the current through Q10 and (Q11-Q12) is approximately equal to the
current through diodes D1 and D2•
The output stage is a quasi (false)-complementary pair emitter follower formed
by NPN transistors Q10 and Q12• In fact, the combination of PNP transistor Q11
and NPN transistor _Q 12 has the power capability of an NPN transistor but the
characteristics of a PNP transistor.
Because of the arrangement of the output stage, the quiescent output voltage is
half the supply voltage ( + V). Furthermore, the negative de feedback applied through
R5 balances the differential amplifier so that the de output voltage is stabilized at
+ V/2. To decouple the input stage from the supply voltage + V, a bypass capacitor
on the order of microfarads should be connected between the bypass terminal (pin I)
and ground (pin 7). The overall internal voltage gain of the amplifier is fixed at 50.

Bypass
Bypass +V
Noninv
2
input
3 Noninv ,..___ 2_.

input
GNt{ 4 LM 380
Inv o---6--4
5 input
Inv
..., input
6 9 NC Ground *Ground
Ground 7 8 VOUI
(b)
14-pin DIP packet

(al
+v
r--------------------------------------
1 .. Current mirror ( 14)
I
.
o.,
0.5 !2 R5
Bypass Rs Output
R3 (8)
(1) 25 K
0.5 !2 R7
c
1 k!2
10 pF
Inv
"-" input
Noninv.
01 (~) .. +"input
(6)
r---- ----,
I
L _
- -,'
I
I
150 k!2 R1 I
I.
Slave
Ground
current (3, 4, 5, 10, 11, 12)
mirror
heat-sink pins
I (7)
L-----------------~
Ground
(c)
Figure 11-32 (a) LM380 power audio amplifier connection diagram. An asterisk indicates
ground-heat sink pins. (b) Block diagram. (c) Schematic diagram. (Numbers in parentheses
are pin numbers.) (Courtesy of National Semiconductor.)
431
However, gain can be increased by using positive feedback, as illustrated in the
applications discussed in the next section.
Another commonly used audio amplifier is the LM384. The schematic diagram
of the LM384 is the same as that of the LM380, which is shown in Figure 10-32,
except that the former is designed to deliver 5 W.
Applications
Audio Power Amplifier. Figure 10-33 shows the simplest and most basic appli-
cation of the LM380-as an audio power amplifier. As shown in this figure, the
amplifier requires very few external components because of the internal biasing,
compensation, and the fixed gain. When the power amplifier is used in the non-
inverting configuration, the inverting terminal may be either shorted to. ground,
connected to ground through a resistor or capacitor, or left open as shown in Figure
10-33. Similarly, when the power amplifier is used in the inverting mode, the non-
inverting terminal may be either shorted to ground or returned to ground through a
resistor or capacitor. Usually, a capacitor is connected between the inverting terminal
and ground if the input has a high internal impedance. Nevertheless, in either configu-
ration the supply voltage + V should be decoupled by connecting a capacitor between
the+ Vterminal (pin 14) and ground. As a precautionary measure, an RC combination
should be used at the output terminal (pin 8) to eliminate 5- to 10-MHz oscillation,
especially in an RF-sensitive envirorrnent,
Decoupling
+V = +15 V capacitor
ck
14 O.l 0µF ~
8 : :,:~ ,,:;~.,
2.7ntR . ~ ~
:\
O.l µFTC~ "R" and "C" added
• for stability with high
'.!: current loads
Figure 10-33 LM380 audio power amplifier. (Courtesy of National Sernicon-

ductor.)
Although the gain of the LM380 is internally fixed at 50, it can be changed with
the use of external components. Specifically, gains up to 300 are possible when
positive feedback is used. Figure 10-34(a) 1hows the LM380 configured for a gain of
200 using positive feedback. On the other hand, variable gains up to 50 are obtained
with the use of a potentiometer across the two input terminals, as shown in Figure
10-34(b).
Bridge Power Audio Amplifier. For applications requiring more power than is
provided by the single LM380 amplifier, two LM380s can be used in the bridge
configuration show.n in Figure 10-35. In this arrangement the maximum output voltage

+v
s-n
8 I 500µF speaker
6
2.7n;~R
0.1 µF:i:c
1 Mn
(a)
+v
C2
2 14
0.2~
µr ¢
8
Rv s-n
2 Mn I 500 µF speaker
6 >
2.7 n:!R
3, 7
"I
0.1 µF:{:c
,.I .
v
(b)
Figure 10-34 (a) LM380 configured for a gain of 200 using positive feedback.
(b) LM380 with a variable gain (volume control) up to 50 using a potentiometer
across the two input terminals. (Courtesy of National Semiconductor.)
swing will be twice that of a single LM380 amplifier; therefore, the power delivered to
the load will be four times as much. For improved performances, potentiometer R4
should be used to balance the output offset voltages of the LM380s.
Intercom System. A simple and inexpensive intercom system can be formed by
using the LM380 as shown in Figure 10-36. The speakers used in this figure are
permanent-magnet types and hence act as microphones as well. The talk and listen
modes are defined with reference to a master station. When the switch is in the talk

+V +V
51 pF
6
Figure 10-35 LM380s used in bridge configuration to provide more power. (Rand C for
stability with high current loads.) (Courtesy of National Semiconductor.)
+V•+15V
Listen
SW 2
Voice
in Listen
T1lk:
I Av SW
I
I N, N, 2Mn T1lk
I
I 6
, I
I spuker
I
I
I I
L---------------------------------------J
(1)
+V • +15 V
2
I Listen
Talk I
c,
I
Av a SW
Voic8
: N, 2Mn Talk in
I
50i,F
I 6
I
I
I
I
I I
L--------------------------------------~
(b)
Figure 10-36 Intercom system using the LM380. (a) Talk mode. (b) Listen mode. (Cour-
tesy of National Semiconductor.) ·
434
position, the master speaker acts as the microphone [see Figure 10-36(a)]. On the
other hand, when the switch is in the listen mode, the remote speaker acts as the
microphone [see Figure l 0-36(b )]. In either position the overall gain of the circuit is
the same and depends on the turns ratio of the transformer T as well as the internal
gain of the LM380. For example, if the turns ratio N1/N2 = 20, the overall gain of
the circuit will be 50 x 20 = 1000. However, the internal gain of the LM380 can be
controlled with the use of potentiometer Ri:
A sample of monolithic power audio amplifiers with their output power ratings
is listed in Table 10-4. In these pO\~er I Cs, the heat-sink requirements are met without
the use of separate heatsinks. Because of their compact size, power audio amplifiers
are more convenient than any of the discrete forms of audio amplifiers. Duel power
amplifiers such as the LM377, which delivers 2 W/channel, are used for stereo phono-
graphs, tape players and recorders, and AM-FM stereo receivers.
TABLE 10-4 TYPICAL MONOLITHIC POWER

AUDIO AMPLIFIERS
Output power (W) IC type
MC1454
2 LM377 (dual)
4 LM378 (dual)
5 µA706
6 LM379 (dual)
8 TDA2002
For applications requinng more output power than that supplied by the
monolithic power !Cs, hybrid power amplifiers are commonly used. For example,
the Intersil's ICH8510/8520/8530 is a family of hybrid power amplifiers designed to
deliver I, 2, and 2.8 A, respectively, at 24-V output levels. All amplifiers are protected
against inductive kickback with internal power limiting, and against shorts to ground.
Each device has a de gain of 105 (100 dB), internal frequency compensation, and an
electrically isolated package style that allows easy heat sinking. These devices are
used to drive electronic values, push-pull solenoids, and de and ac motors.
Another classic example of a hybrid power amplifier is the Burr-Brown's 3573,
which is designed to deliver 100 W peak or 40 W continuous output power. When
operated from ±28-V power supplies, the device delivers ±5 A peak minimum at
±20 V (40 V peak to peak) to the load. The 3573 is internally frequency compensated
with good input and distortion characteristics and is low in cost. It can be used to
drive de and ac motors, electronic valves, and push-pull solenoids.
10-6 VOLTAGE REGULATORS
A voltage regulator is a circuit that supplies a constant voltage regardless of changes

in load currents. Although voltage regulators can be designed using op-amps, it is
quicker and easier to use IC voltage regulators. Furthermore, IC voltage regulators
Sec. 10-6 Voltage Regulators 435

are versatile, relatively inexpensive, and are available with features such as a pro-
grammable output, current/voltage boosting, internal short-circuit current limiting,
thermal shutdown, and floating operation for high-voltage applications. IC voltage
regulators are of the following types:
Fixed output voltage regulators: positive and/or negative output voltage

Variable output voltage regulators: positive or negative output voltage
Switching regulators
Special regulators
Except for the switching regulators, all other types of regulators are called linear
regulators. The impedance of a linear regulator's active element may be continuously
varied to supply a desired current to the load. On the other hand, in the switching
regulator a switch is turned on and off at a rate such that the regulator delivers
the desired average current in periodic pulses to the load. Because the switching
element dissipates negligible power in either the on or off state, the switching regulator
is more efficient than the linear regulator. Nevertheless, in switching regulators the
power dissipation is substantial during the switching intervals (on to off or off to on).
In addition, most loads cannot accept the average current in periodic pulses. There-
fore, most practical regulators are of the linear type.
Voltage regulators are commonly used for on-card regulation and laboratory-
type power supplies. Voltage regulators, especially the switching type, are used as
control circuits in pulse width modulation (PWD), push-pull bridges, and series-type
switchmode supplies. Almost all power supplies use some type of voltage regulator IC
because voltage regulators are simple to use, reliable, low in cost, and above all,
available in a variety of voltage/current ratings. A vast number of voltage regulators
is available: data sheets and application notes provided by the manufacturers contain
information on the design/use of these devices. The next section presents a selection
of voltage regulators to illustrate design and construction features of these devices.
10-6.1 Positive Voltage Regulator Series with Seven

Voltage Options
The 7800 series consists of three-terminal positive voltage regulators with seven
voltage options [see Figure 10-37(a)]. These !Cs are designed as fixed-voltage regula-
tors and with adequate heat sinking can deliver output currents in excess of I A.
Although these devices do not require external components, such components can
be used to obtain adjustable voltages and currents. These !Cs also have internal
thermal overload protection and internal short-circuit current limiting. As shown in
Figure 10-37(c), proper operation requires a common ground between input and
output voltages. In addition, the difference between input and output voltages
(Vin - V called dropout voltage, must be typically 2.0 V even during the low point
0),
on the input ripple voltage. Further, the capacitor C, is required if the regulator is
located an appreciable distance from a power supply filter. Even though C is not 0
needed, it may be used to improve the transient response of the regulator.

Typical performance parameters for voltage regulators are line regulation, load

Maximum
Device Output
input voltage
type voltage (V) (V)
7805 5.0
7806 6.0
7808 8.0
7812 12.0 } 35
7815 15.0
7818 18.0
78"24 I :!4.0 40
(a)
I ..
Metal package
(T0-3 type)
Input Output
3
V;n---r 78XX' t----C>------- v O
Pin 2.
1. Input __./e,
~---
Case
Output
Ground
c;.l co
0.33 µF 2 0.1 µF
•XX: These two numbers

of the type number
Plastic package indicate output
voltage
T0-220 type
(c)
Pin1. Input
2. Ground
3. Output
(b)
Figure 10-37 7800 series regulators. (a) Voltage options. (b) Package types. (c) Standard
application. (Courtesy of Motorola Semiconductor.)
regulation, temperature stability, and ripple rejection. Line or input regulation is

defined as the change in output voltage for a change in the input voltage and is usually
expressed in millivolts or as a percentage of output voltage V0• Load regulation is the
change in output voltage for a change in load current and is also expressed in millivolts
or as a percentage of V Temperature stability or average temperature coefficient of
0•
output voltage (TCV 0) is the change in output voltage per unit change in temperature
and is expressed in either millivolts/°C or parts per million (ppm)/°C. Rippierejection
is the measure of a regulator's ability to reject ripple voltages. It is usually expressed
in dB. The smaller the values of line regulation, load regulation, and temperature
stability, the better the regulator.

The 7800 regulators can also be used as current sources. Figure 10-38 shows a
typical connection· diagram of the 7805C as a 0.5-A current source. The current
supplied to the load is given by the equation
i, = l + Io
V'
(10-12a)
where I0 = quiscent current (amperes)
= 4.3 mA typically for the 7805C
Dropout voltage
Vin - V0 = 2 V
Input
V;n --....---<>--t 7805 C
----.---'
2
------------..--0----vL
Ia RL
10 n.
,ow
Figure 10-38 7805C as a 0.5-A current
source.
Referring to Figure 10-38, VR = V23 = 5 V and R = 10 n; therefore,

h ~ 0.5 A
The output voltage V0 with respect to ground is
Vo= VR + VL (10-12b)
where VL = ILRL. The load resistance RL = 10 n; 'hence VL = 5 V. Therefore, V = 0
10 V. Since the dropout voltage for the 7805C is 2 V, the minimum input voltage
required is given by the equation
Vin = V0 + (dropout voltage) (10-12c)
=12V
In short, a current source circuit using a voltage regulator can be designed for a desired
value of load current (IL) simply by selecting an appropriate value for R. Note,
however, that Vin depends on the size of RL and also the dropout voltage of the
regulator [see Equation (l0-12c)].
Example 10-9
Using the 7805C voltage regulator, design a current source that will deliver 0.25 A
current to the 48-0.10-W load.
Solution. Determine the value of R and find the minimum value of Vi needed by 0
using Equations (10-12a) throu~h (10-12c):

R- 0 _;f A= zo n
Vo= 5.0 + (48)(0.25) = 17 V
Vio = 17 + 2 = 19 V
The 7900 series of fixed output negative voltage regulators are complements to

the 7800 series devices. These negative regulators are available in the same seven-
voltage options as the 7800 devices. In addition, two extra voltage options, - 2 V,
and -5.2 V, are also available in the negative 7900 series, as shown in Figure 10-39(a).
Figure 10-39(b) shows the package types in which the 7900 series woltage regulators
are available.
Maximum
Device Output
input Metal package
type voltage (V)
voltage (V)
7902 -2.0 - (T0-3 type)
7905 -5.0 (Bottom view)

7905.2 -5.2
7906 -6.0
-35
7908 -8.0
7912 -12.0 Plastic package
7915 -15.0
7918 -18.0
7924 -24.0 -40
Pin 1. Ground
2. Input
(a) 3. Output
(Heat-sink surface
connected to pin 2)
(b)
,.
Figure 10-39 7900 series voltage regulators. (a) Voltage options. (b) Package
types. (Courtesy of Motorola Semiconductor.)
10-6.2 Switching Regulators
An example of a general-purpose regulator is Motorola's MCI 723; It can be used

in many different ways, for example, as a fixed positive or negative output voltage
regulator, variable output voltage regulator, or switching regulator. Because of its
'flexibility, it has become a standard type in the electronics industry. Although it is
designed to deliver load current to 150 mA, the current capability can be increased to
several amperes through the use of one or more external pass transistors. Figure
10-40 shows the connections for switching-regulator action of the 723 type regulator
for positive output. The regulator requires an external transistor and a 1-mH choke.
To minimize its power dissipation during switching, the external transistor used must
be a switching power transistor. The 1-mH choke smooths out the current pulses
delivered to the load while capacitor C holds output voltage at a constant de level.
10-6.3 Voltage References
Voltage references are a special type of voltage regulators that are used for reference
purposes as reference voltages. Typical applications of voltage references include D/ A
and A/D converters that do not have internal references, amplifier biasing, low-

2N4918 or equiv.
ioo n (11) 7
v: (12) 8 6 (10) to n
+lOV
(6) 4 10 (2)
MC1723
(MC1723C)
1 (3)
2.2 kn 1 Mn +
C 100 µF
1 kn (5) 3 2 (4)
5 (7)
Figure 10-40 Motorola MC1723 as a 5-V 1-A switching regulator. (Pin numbers
adjacent to terminals are for the metal packages and those in parentheses are for
the DIP packages.) (Courtesy of Motorola Semiconductor.)
temperature-coefficient zener replacements, high-stability current references, compa-

rator circuits, and voltmeter system references. Typical examples of voltage references
include the following: The ICL8069 is a 1.2-V temperature-compensated voltage
reference; the 9495 is a Teledyne's 5-V reference; and the MC1403 is a Motorola's
2.5-V reference.
10-6.3(a) MC1403 used as a voltage reference for DAC MC1408.
Figure 10-41 shows a· D/A converter using the MC1403 voltage reference. A stable
current reference of nominally 2.0 mA required for the MC1408 is obtained from
the MC1403 with the addition of series resistors R1 and R2• Besides that, resistor R3
improves temperature performance and capacitor C decouples any noise present OIJ...
0
the reference line. A single MC1403 can provide the required current input for up to
five of the D/A converters. For complete connection diagram of MC1408, refer to
Figure 9-20(a).
10-1 VOLTAGE INVERTER

-
Datel's VI-7660 is a monolithic CMOS voltage inverter that provides -1.5 to
-10 V from + 1.5 to + 10 V sypplies with the addition of only two noncritical
external capacitors. The block diagram of the VI-7660 is shown in Figure 10-42(a),
which contains a de voltage regulator, RC oscillator, voltage-level translator, four
output-power MOS switches, and a logic network. The logic network senses the most
negative voltage in the device and ensures that the output N-channel switches are not
forward biased. This assures latch-up-free operation. When unloaded, the oscillator
oscillates at a nominal frequency of 10 kHz for an input supply voltage of 5 V.
Because of noise or other considerations, it may be desirable to increase the oscillator

Full-scale
adjustment
2 2.5 V 14
+sv---0--1 MC1408
soon DIA
3 ......--0-1-5-1converter
(b)
V;n 1 8 NC
VOUt 2 7 NC
MC1403
GND 3 6 NC
NC 4 5 NC
8-pin DIP
package
(a)
Figure 10-41 (a) MC1403 voltage reference pin diagram. (b) MCl403 providing
the reference current for the MC1408. (Courtesy of Motorola Semiconductor.)
frequency in some applications. This may be done by overdriving the oscillator from
an external clock. On the other hand, to maximize the conversion efficiency it may be
necessary to lower the oscillator frequency. This is achieved by connecting an addi-
tional capacitor (typically 100 pF) between pins 7 and 8 [see Figure 10-42(b)].
Typical applications for the Yl-7660 include data acquisition and micro-
processor-based systems in which a positive supply is available and an additional
negative supply is required. The YI-7660 is also ideally suited as on-board negative
supply for up to 64 dynamic RAMs (random-access-memory ICs).
10-7.1 Vl-7660 Applications
10-7.1.(a) Simple negative converter. Figure 10-43 shows typical con-

nections when the YI-7660 is used as a simple negative converter. To improve the
low-voltage (LY) operation, that is, when supply voltage ( + V) < 3.5 Y, the LY pin
+
may be grounded. However, for ( V) > 3.5 Y, the LY pin is left open to prevent
device latch-up. Also, an additional diode D1 must be included for proper operation
at higher supply voltages ( + V > 6.S Y) and/or elevated temperatures. When capacitor
C ,c is used to maximize the conversion efficiency of the device, the oscillator frequency
0
decreases and hence the reactances of C1 and C2 will increase (see Figure 10-43).
Therefore, to overcome the increase in their reactances, the values of C, and C2 must
be increased by the same factor that the frequency has been reduced. For example,
Sec. 10-7 Voltage Inverter 441
\
8
+v
Voltage 2
RC
level CAP+
oscillator translator
4
CAP-
7 6
osc LV
5
(Oscillator) (Low voltage)
VoUT
Voltage
regulator
Logic
network
(a)
NC 1 8 +V
CAP+ 2 7 osc
VI-7660PC
GND 3 6 LV
CAP- 4 5 VoUT
8-pin DIP
packag~
(b)
Figure 10-42 VI-7660 voltage inverter. (a) Block diagram. (b) Connectiondiqram. (Cour-
tesy of Datel-Intersil Inc.)
the addition of Cose · 100 pF between pins 7 and 8 will lower the oscillator frequency
from 19 kHz to 1 kHz and will thereby call for an increase in the values of C1 and
C2 from 10 µF to 100 µF. The output voltage equation is
VouT = -( + V) for 1.5 < + V < 6.5 V (10-13a)
I
VouT = -(+ V- VD1) for 6.5 < + V < 10 V (10-13b)
where VD1 =-forward voltage drop of diode D1
= 0. 7 V typically
10-7.1 (b) Negative-voltage multiplier. To produce larger negative mul-
tiplication of the initial supply voltage, the VI-7660's may be cascaded as shown
in Figure 10-44. The practical limit to the number of devices that can be cascaded is
442 Specialized IC Applications .Chap. 10

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443
10 for light loads. The output voltage is given by the equation ·
VouT = -(n)( + V) (10-14)
where n = number of devices cascaded and must be< 10
+ V = input supply voltage
SUMMARY
1. Although a general-purpose op-amp may work satisfactorily in certain applications, the

use of specialized !Cs results in simpler, easier, more economical, as well as more accurate
circuits. In some other applications general-purpose op-amps will not work at all. Under ·
such circumstances, the designer is forced to use specialized ICs. The best source of such
specialized ICs are the manufacturers, data books.
2. Datel's FLT-U2 is a universal filter which provides second-order low-pass, high-pass,
and band-pass output functionssimultaneously, It can also be used as a notch or alt-pass
filter. An uncommitted op-amp available in the FLT-U2 can be used to either increase the
overall gain of the filter or to raise the order of the low-pass or high-pass filter to the
third order.
3. Signetics' NE/SE 555 is a monolithic timing circuit that can produce accurate and
highly stable time delays or oscillation. Thus the 555 may be used as either a monostable
or an astable multivibrator. This device can be used in such applications as waveform gen-
erators, digitai logic probes, infrared transmitters, burglar alarms, toxic gas alarms, and
electric eyes.
4. The phase-locked loop (PLL) basically consists of a phase detector, an amplifier/low-pass
filter, and a VCO. The output/ouT of the VCO is fed back to the phase detector, where it
is compared with the input frequency /rn. WhenfiN = /ouT, the loop is said to be locked.
Signetics' SE/NE 560 series-560, 561, 562, 564, 565, and 567-are monolithic PLLs.
The PLLs are used in such applications as FM stereo decoders, motor speed controls,
FSK decoders, and FM demodulators.
5. Power amplifiers are intended to supply a large-signal current to current-operated loads
such as. speakers and motors. The output current capability of general-purpose op-amps
can be increased by using a power transistor called a power booster in series with it. !n
some applications, however, monolithic/hybrid power amplifiers are preferred, mainly
because of their compact size and simpler. and more reliable operation. National Semi-
conductor's LM380 is a monolithic power audio amplifier designed to deliver minimum a
of 2.5 W (rms) to an 8-Q load, while Burr-Brown's 3573 hybrid power amplifier is
capable of delivering 100 W peak or 40 W continuous output power. Power audio ampli-
fiers can be used for such applications as simple phonograph amplifiers, alarms, TV sound
systems, and intercoms.
6. A voltage regulator is a circuit that supplies a constant voltage regardless of changes in
load currents. Monolithic voltage regulators are available in a variety of different output
voltage ratings and are also quicker and easier to use. The 7800 is a fixed-positive-voltage
regulator series with seven voltage options, while the 7900 is a fixed-negative-voltage regu-
lator series with nine voltage options. Voltage references are special regulators designed
for reference. voltage purposes. A voltage inverter such as Datel's VI-7660 converts
positive voltages from +1.5 to +10 V to -1.5 to -10V. Voltage regulators are mainly
used in power supplies, while voltage references are used with comparators, amplifiers,
and D/A converters.

QUESTIONS
10-1. What is the function of the FLT-U2? List important features of this device.
10-2. What maximum-order low-pass (or high-pass) filter can be realized using just one
FLT-U2?
10-3. What is the function of the uncommitted op-amp of the FLT-U2?
10-4. Can a notch filter be realized using FLT-U2? Explain how.
10-5. To form a fourth-order low-passi high-pass, or band-pass filter, how many FLT-U2s
are needed? Explain the connection procedures required to form a 'fourth-order low-
pass filter.
10-6. List one application in which you will use the FLT-U2.
10-7. List important features of the 555 timer.
10-8. What are the two basic modes in which the 555 timer operates?
10-9. Briefly explain the differences between the two operating modes of the 555 timer.
10-10. What must the relationship be between the pulse width Ip and the period T of the
input trigger signal if the )55 is to be used as a divide-by-4 network?
10-11. List one application each in which the 555 can be used as a monostable and astable
multivibrator.
10-12. What is a phase-locked loop?
10-13. List the basic building blocks of the discrete PLL.
10-14. What is the major difference between digital and analog PLLs?
10-15. What is the major advantage of a monolithic phase detector such as the MC4344 over
an exclusive-OR and an edge-triggered phase detector?
10-16. Briefly explain the roles of a low-pass filter and VCO in PLLs.
10-17. What are the advantages and disadvantages of monolithic PLLs over discrete PLLs?
10-18. List one application of the PLL and then briefly describe the role of the PLL in that
application.
10-19. What is the major difference between small-signal and power amplifiers?
10-20. What is a power booster? Why is it needed?
10-21. List the differences between the monolithic power amplifiers and the power amplifiers
using power boosters.
10-22. List important features of the LM380 poweraudio amplifier.
10-23. What is the major difference between monolithic and hybrid power amplifiers?
.10-24. What is a voltage regulator? List four different types of voltage regulators.
10-25. How many voltage options are available with each of the 7800 and 7900 voltage
regulators?
*
10-26. What is a voltage reference? Why is it needed?
10-27. List two important features of VI-7660 voltage inverter.
PROBLEMS
10-1. Using the FLT-U2, design a second-order noninverting Butterworth low-pass filter
with 10 kHz cutoff frequency, a gain of 10, Q = 5, and Vs= ±15 V.
10-2. Repeat Problem 10-1 for a high-pass filter.

10-3. Design a band-pass filter with 2.kHz center frequency, Q = 20, and noninverted out-
put. Use FLT-U2 with supply voltages= ±15 V.
10-4. Repeat Problem 10-3 for inverted output.
10-5. Using the FLT-U2, design a notch filter with 2 kHz notch-out frequency and Q = 20.
10-6. Using the 555 timer, design a monostable multivibrator having an output pulse width
of 100 ms. Verify the designed values of R,. and C with the graph of Figure 10-11.
10-7. In the circuit of Figure 10-lO(a), C = 0.1 µF and the output pulse width is 1 ms.
Determine the. value of R,..
10-8. The monostable multivibrator of Figure 10-lO(a) is to be used as a divide-by-J net-
work. The frequency of the input trigger is 12 kHz. If the value of C = 0.05 µF,
what should be the value of R,.?
10-9. For the astable multivibrator of Figure 10-15(a), RA ~ 4.7 kQ, RB= 1 kn, and
C = 1 µF. Determine the positive pulse width, the negative pulse width, and the
free-running frequency. What is the duty cycle of the output waveform?
10-10. Design an astable rnultivibrator having an output frequency of 10 kHz with a duty
cycle of 25 %.
10-11. In the ramp generator of Figure 10-18(a), R is set at 100 k!l, keeping all the other
values the same. What is the approximate frequency of the output ramp?
10-12. Design a ramp generator having an output frequency of approximately 5 kHz.
10-13. Referring to Figure 10-27(a), determine fouTJL, and fc if C 1 = 0.001 µF.
10-14. Repeat Problem 10-13 with C1 = 470 pF.
10-15. Referring to the 565 PLL frequency multiplier of Figure 10-28(b), determine the
range for the output frequency fouT if R1 is varied from 2 to 20 kO.
10-16. In the circuit of Figure 10-28(b), if JIN = 500 Hz, what is the value of R1 needed?
10-17. In the intercom system of Figure 10-36, an overall gain of 200 is needed. What must
be the turns ratio Ni/N2 of the transformer if potentiometer Rv is open?
10-18. Using the 7805C voltage regulator, design a current source that will deliver 150 mA
current to the 8-0; 10-W load.
10-19. The VI-7660 is used as a simple negative converter, as shown in Figure 10-43. Deter-
mine the output voltage VouT if (a) + V = 5 V and (b) + V = 9 V.
10-20. The VI-7660 voltageinverters are to be used to obtain an output voltage of -15 V.
How many VI- 7660s are needed if the supply voltage + V = 5 V? Draw the complete
connection diagram.
EXPERIMENT 10~1
THE 555 TIMER AS A MONOSTABLE AND ASTABLE
MULTIVIBRATOR
Objectives
In this experiment you will learn the operation of a 555 timer as a monostable and
astable multivibrator. At the end of this experiment you should be able. to:
1. Select appropriate timing components for a desired output pulse width when
the 555 is used as a monostable multivibrator.

2. Verify that for proper operation of the monostable multivibrator, the width of
the negative-going trigger pulse must be smaller than the desired output pulse
width.
3. Understand the operation of reset and control pins when the 555 is used as a
monostable multivibrator.
4. Select a proper combination of external components for a desired output
frequency using the 555 as an astable multivibrator.
5. Determine the duty cycle of a given waveform.
Equipment
2. Audio square-wave generato
· 3. +5 V power supply
Materials
1. NE555
2. 1N914 ·
3. I-kn resistor
4. 2.2-kn resistor
5. Two 3.3-kQ resistors
6. 4.7-kQ resistor
7. 6.8-kQ resistor
8. 10-kQ resistor
9. 12-kQ resistor
10. 20-kQ resistor
11. 100-kQ resistor
12. 10-kQ potentiometer
13. 2.5-MQ potentiometer
17. SPDT switch
All resistors should be with ±1% tolerance and all capacitors should be Mylar.
Procedure
1. Connect the monostable multivibrator as shown in Figure EI0-1.1.
2. Set the square-wave generator for 5 V pp output at 50 Hz. Connect channels 1
and 2 of the scope to the input and output terminals, respectively, of the mono-
stable multi vibrator. Make sure that switch SW 1 is in position A. (Pin 4 con-
nected to +5 V.)
Exp. 10-1 The 555 Timer as a Monostable and Astable Multivibrator 447
+5V
A sw,
RA
,----------- ---,
12 kn
~
8 4 Reset
6
Waveshaping 7
network -----,~ 1N914 +
Vo
CJ1µ,F 555 3 Output
2
0.01·µ,F 5
L--------------~ Control voltage

+ 5 V pp at 50 Hz
Square-wave generator
used as a source of
i C2
0.01 µF.
input trigger
Figure El0-1.1 555 used as a monostable multivibrator.
3. Measure the pulse width of the output waveform and enter the measured value
in Table El0-1.l{a).
TABLE E10-1.1
(a)
Output pulse width (s)
c R,4 Calculated
(µF) (k!l) Measured (tp = l.1R..4C)
1 12
1 6.8
1 4.7
1 2.2
,
4. Momentarily switch off the generator and ·the power supply, and replace the
12-kn resistor by the 6.8-kn resistor.
5. Tum the generator and the power supply back on and repeat step 3.
6. Complete Table El0-1.l(a) for the remaining values of R,1..
7. With R,1. = 2.2 kn, C = 1 µF, and the dual-trace scope connected to the input
and output terminals of the multivibrator, place switch SW 1 in position B.
448 Specialized IC Appications Chap. 10

Observe the output waveform. Enter the amplitude and frequency of the output
waveform in Table El0-1. l(b).
TABLE E10-1.1
fb)
Output waveform
Amplitude M Frequency (Hz)
8. Return switch SW1 to its original position, A. Connect the series combination
of the 10-kQ resistor and the 2.5-MQ potentiometer between the control voltage
pin 5 and ground (across C2). Vary the 2.5 MQ potentiometer and simultane-
ously observe the output waveform. In Table El0-1.l(c), enter the amplitude
and pulse-width of the output waveform for the minimum and maximum values
of the potentiometer. Remove the 10-kn resistor and 2.5-MQ potentiometer
connected across C2•
TABLE E10-1.1
(c)
Output waveform
2.5-Mn potentiometer
setting Amplitude (V) Pulse-width (ms)
Minimum (0 il)
Maximum (2.5 Mn)
9. Remove the waveshaping components C1, Ri, and D1 from the circuit of Figure
EI0-1.1 and apply the 50-Hz square wave directly to the trigger pin 2. Using
the scope, simultaneously observe the input and output waveforms. Enter the
amplitude and pulse-width. of the output waveform in Table El0-1.l(d).
TABLE E10-1.1
(d)
Input waveform Output waveform
Amplitude (V) Time period (ms) Amplitude (V) Pulse-width (ms)
Exp. 10-1 The 555 Timer as a Monostable and Astable Multivibrator 449
10. Connect the astable multivibrator of Figure El0-1.2.
11. Connect the scope to the output terminal and measure the frequency and duty
cycle of the output waveform. Enter the measured values in Table E10-1.2(a).
+5 V
8 4
7
Vo
555 .3 Output
2
c 5
0.0, µF
c, 0.01 µF
Figure El0.1.2 555 as an astable

multivibrator.
TABLE E10-1.2
(a)
% Duty cycle Output frequency
Calculated Calculated
c RA RB lOORB I 1.45
(µF) (kn) (kQ) Measured RA.+ 2RB Measured =(RA+ 2RB)C
0.01 3.3 1
0.01 3.3 10
o.oi 3.3 .100
o.oi 3.3 3.3
12. Momentarily switch off the power supply and replace RB of 1 k!l by 10 kn.
Tum the power supply back on and repeat step 11.
13. Complete the table for the reziaining values of RB.
14. Switch off the power supply again, and replace the 3.3-kQ value of RA by a series
combination of a I-kn resistor and a 10-kQ potentiometer. Also, connect a
1N914 diode across RB such that the anode of the diode is connected to the
junction of RB and R ... and the cathode to the junction of RB and C. Connect the
scope to the output terminal of the astable multi vibrator and turn on the power
- -<
450. Specialized IC Applications Chap. 10

supply. Adjust the 10-kn potentiometer until the output is a square wave.
Measure the frequency and the duty cycle of the output waveform. Enter the
total value of R" in Table El0-1.2(b).
(b)
% Duty cycle
c RB R" = 100/p
(µF) (kQ) (kn) T Output frequency
I
O.Ql 3.3
Questions
I. Are the measured pulse widths within ± 10 % of calculated pulse widths? If

not, give the reasons.
2. Explain the result of step 7.
3. Explain the result of step 8.
4. What is the function of the waveshaping circuit in Figure EI0-1.1?
5. Why did the monostable multivibrator not work in step 9?
6. For the astable multivibrator, is the percent duty cycle the same at different
output frequencies? Explain your answer.
7. In order to produce a square-wave output (50% duty cycle), a diode is used
across R8 in the astable multivibrator of Figure El0-1.2. Explain briefly how
the circuit works.
8. For a square-wave output, what is the relationship between R" and RB? Explain
your answer.
EXPERIMENT 10-2
NE565 PHASE-LOCKED LOOP AS A FREQUENCY MULTIPLIER
Objectives
In this experiment you will learn the operation of the NE565 phase-locked loop,
You will also use the NE565 as a multiplier. At the end of this experiment you should
be able to:
1. Understand the relationship between the free-running frequency, lock range,

and capture range of the PLL.
2. Verify that the capture range depends on the value of the low-pass filter capacitor.
3. Select an appropriate resistor-capacitor combination for a desired VCO
free-running frequency.
4. Use a PLL as a frequency multiplier for a desired output frequency.
Exp. 10-2 NE565 Phase-Locked Loop as a Frequency Multiplier 451

Equipment
2. Audio-square-wave generator
3. ±6-V power supply
Material•
1. NE565 PLL
2. 74LS90 decade counter
3. 2N2222 switching transistor
4. 2-kn resistor
5. 4.7-kn resistor
6. 6.8-kn resistor
7. 10-kn resistor
8. 12-kn resistor
9. zo-sn potentiometer
11. 5-µF capacitor
12. 10-µF capacitor
AJI resistors are with 1 % tolerance and all capacitors are Mylar.
Prot:edure
1. Connect the 565 PLL as shown in Figure El0-2.1. Do not apply the input voltage
Vin yet. The numbers indicated in the figure represent the pins.
2. Connect one channel of the scope to the VCO output pin 4, and measure the
free-running frequency of the VCO. Enter the measured value in Table El0-2.1.
3. Turn on the audio generator and set it for 1 V pp square wave at 1 kHz. Connect
another channel of the. scope to the input terminal pin 2 of the PLL. Make sure
that the scope is properly triggered.
4. Observe the scope display and gradually increase the input frequency until the
loop is phase-locked onto the input frequency. This frequency is the lower
end of the capture range. Enter it in Table El0-2.1. As the input frequency is
increased further, the loop tracks the input until f2, the upper end of the lock
range. For input frequencies greater than f2, the loop is unlocked. Enter the
frequency f2 at which the ioop unlocks in Table El0-2.1.
5. Gradually decrease the frequency until the loop is again phase-locked onto the
input frequency. This is the frequency f3, the upper end of the capture range.
Enter the value of f3 in Table El0-2.1. Keep on decreasing the input frequency
until the loop is unlocked. The frequency f4 at which this
happens is the lower
end of the lock range. Enter the value oi f; in Table El0-2.1.
6. Momentarily switch the generator and the power supply off and replace 6.8 kn

+6 V
0.001 µF
10 8
Input 7 -------Q Demodulatedoutput
2
6 ------u Referenceoutput
NE565
4 -----~ VCO output (f0)
3
9
s-----
c,
0.001 µF
-6V
Figure El0-2.1 NE565 PLL.
TABLE E10-2.1
VCO free-running
frequency, /ouT Lower end Upper end Upper end Lower end
of the of the of the of the
Calculated capture lock capture lock
R1 C1 C2 J; 0.3 range, range, range, range,
(kn) (µF) (µF) Measured OUT= R1C1 /1 (Hz) fz (Hz) /3 (Hz) J, (Hz)
1. 6.8 0.001 1
2. 12 0.001 1
3. 12 0.001 5
Lock range IL Capture range Jc
Calculated Calculated
Measured
(/2 -/.)
±8/ouT
12
Measured
(/3 -/1)
[ IL
± (2n)(3.6)C2
]112
1.
2.
3.
463
(R1) by 12 kn. Switch the generator and the power supply back on and repeat
steps 4 and 5.
7. Repeat step 6, but this time change the value of C2 from 1 µFtp 5 µF instead
of changing the value of R1•
8. Complete Table El0-2.1.
9. Connect the 565.PLL as shown in Figure El0-2.2. Connect channels 1 and 2 of
the scope to the input and output terminals.
+6 v
20 kn
0.001 µF -
2k.n
10 8
71--------'
,------l2
VCO output
NE565 41-----------------------.---o
.-----13
5 t----. +6 V
9
5
...___-111 74LS90
2 3 6 7 10
-5V
Divide by 5
Figure El0-2.2 NE565 as a frequency multiplier.
TABLE t:10-2.2
Input frequency, Output frequency,

/rn (Hz) /ouT (Hz)
500
1000
1500
10. Set the generator for 1 V pp square wave at 500 Hz. Adjust the 20-kn potentiom-
eter slowly until the loop is phase locked. Measure t1ie output frequency and
enter it in Table El0-2.2.

11. Change the input frequency to 1 kHz and again adjust the 20-kQ potentiometer
until the loop is phase-locked. Measure/oUT and enter it in Table El0-2.2 Repeat
the same procedure for an input frequency of 1.5 kHz.
Questions
1. Are the measured values of fouT within 10 % of its.calculated values? If not, give
the reasons.
2. How does the value of R1 atfect the VCO free-running frequency /ouT?
3. What effect does C2 have on the capture range?
4. Is there any relationship between/ouT,/L, and/c? Explain.
5. In the frequency multiplier of Figure El0-2.2, what would the minimum and
maximum values of input frequency be? Explain.
6. What modifications are required in the frequency multiplier of Figure El0-2.2
if the input frequency is 10 kHz?
Exp. 10-2 NE565 Phase-Locked Loop as a Frequency Multiplier 465

··--·--· ..---··- ..,, . .-. .. ._......._,_,_,,, ,
11
Selected IC System Projects
11-1 INTRODUCTION
The preceding chapters have emphasized the analysis and use of individual !Cs.
The next logical step would be to consider how some of these discrete !Cs might be
combined to form a system that serves some useful purpose. The aim of this chapter
is to demonstrate some of the interesting and challenging projects devoted to con-
structing IC systems that serve a number of useful purposes.
To most people the word system means a very complex, cumbersome, and
expensive combination of networks. On the contrary, a system may be simply a
combination of a few I'Cs together with some discrete components, the effect of which
is to perform a specific useful service. A system may even be built from a single IC
and a few discrete components .. The simpler system is increasingly .more common
today because of the increasing pace of refinement and advancement in IC technologies.
Even though innumerable systems could -be formed from combinations of the- many
ICs presented thus far, this chapter focuses on a limited number of systems only.
These are simple enough to be discussed meaningfully at this level, and they are
illustrative ofIC systems designed for specific uses. In addition, this chapter introduces
a function generator system using a specially designed IC that requires very few
external components.
45~
11-2 POWER SUPPLY: APPLICATION OF VOLTAGE
REGULATORS
Since a power supply is a vital part of all electronic system, it will be discussed first.
Most digital ICs, including microprocessors and memory ICs, operate on a ±5-V
supply, while almost all linear I Cs (op-amps and special-purpose I Cs) require± 15-
or ± 12-V supplies. Therefore, the power supply presented in this section will have
±5 and ±15 V.
Figure 11-1 shows the blockt diagram of a typical power supply. The schematic
diagram of the power supply that provides output voltages of ± 5 V at 1.0 A and
Fuse
Filter Regulator
Transformer Rectifier Regulator
output
Figure 11-1 Block diagram of a power supply.
± 15 V at 0.500 A is shown in Figure 11-2. In this figure two separate transformers

are used because they are readily available; however, it is possible to custom design
a single transformer with the same specifications to replace the two. The ±15 V
supply voltages are obtained from a 26.8-V center-tapped (CT) transformer, and the
±5-V supply voltages are obtained from the 12.6-V CT transformer. The output of
these secondaries is then applied to the bridge rectifiers, which convert the sinusoidal
inputs into full-wave rectified outputs. The filter capacitors at the output of the bridge
rectifiers are charged to the peak value of the rectified output voltage whenever the
diodes are forward biased. Since the diodes are not forward biased during the entire
positive and negative half-cycles of the input waveform, the voltage across the filter
capacitors is a pulsating de that is a combination of de and a ripple voltage. From the
pulsating de voltage, a regulated de voltage is extracted by a regulator IC.
Consider first how the ± 15-V · supply voltages are obtained in the circuit of
Figure 11-2. As shown in Section 10-6, the 7815 is a +15-V regulator, the 7915 is a
-15-V regulator, and both can deliver output .current in excess of 1.0 A. They will
hence perform satisfactorily in the circuit of Figure 11-2 by providing ± 15 V at
0.500 A. However, since the drop-out voltage (Vin - V0) is 2 V, the input voltage for
the 7815 must be at least + 17 V and that for the 7915 must be at least -17 V. This
means that the rectified peak voltage must be greater than + I7 V and -17 V, which
in turn implies that the secondary voltage must be larger than 34 V peak or 24 V
rms. The voltage across the center-tapped secondary in Figure 11-2 is 26.8 V rms,
thus satisfying the minimum voltage requirement of 24 V rms. Besides that, the peak
voltage between either of the secondary terminals and the center-tap (ground terminal)
is 13.4(../2) = 18.95 V peak, which is less than the maximum peak voltages of +35 V
and -35 V for the 7815 and 7915, respectively.
Note that the voltages across the two halves of the center-tapped secondary
are equal in amplitude but opposite in phase. During the positive half-cycle of the
input voltage, diode D1 conducts and capacitor C1 charges toward a positive peak
Sec. 11-2 Power Supply: Application of Voltage Regulators 457

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value cs 18.95 Y. At the same time, diode D3 is also conducting, hence capacitor
C3 charges toward a negative peak value cs -18.95 Y. This means that the voltage
'across nonconducting diodes D2 and D4 is 37.90 Y peak, which implies that the peak-
reverse-voltage (PRY) rating of the bridge rectifiers must be larger than 37.90 v
peak or 26.8 Y rms. The PRY rating of the bridge rectifier diodes, also known-as a
working inverse voltage (WIY), is specified on the data sheets.
The bridge rectifier, MDA200 (Motorola's rectifier) in Figure 11-2, has a PRV
rating of 50 Y, which is higher than needed. This bridge rectifier is, in fact, used here
because it is readily available and -J.iore commonly used. On the other hand, during
the negative half cycle of the input waveform, diodes D2 and D4 conduct and charge
capacitors C1 and C3 toward the peak voltage of 18.95 Y with indicated polarities.
Note, however, that the diode pair that conducts during either the positive or nega-
tive half-cycle does not do so for the entire half-cycle. The diodes conduct only during
the time when the anode is positive with respect to the cathode. In other words,
when the diode is forward biased, the capacitor is charged by current pulses. Data
sheets give the maximum average rectified current / mu which the diode can safely
0
handle, For the MDA200, /0 max is 2.0 A. In addition, when the power supply is first
turned on, the initial charging of the capacitor causes a large transient current called
the surge current to pass through the diodes. The surge current lps flows only briefly
and is therefore much larger than the maximum average current / niax· The maximum
0
. surge-current I PsM is normally included on the data sheets; it is 60 A for the MDA200.
Finally, the size of the filter capacitor depends on the secondary current rating
of the transformer. As a rule of thumb, a 1500-µF capacitor should be used for each
ampere of current. The working voltage rating (WVDC) of the capacitor, on the other
hand, depends on the peak rectified output voltage and must be at least 20 % higher
than the peak value of the voltage it is expected to charge to. Capacitors C1 and C3
satisfy these requirements (see Figure 11-2). Capacitors C2 and C4 at the output of
the 7815 and 7915 regulators, respectively, help to improve the transient response
and should be in the range of 1 µF.
Next consider the ±5-Y supply. _The circuit arrangement of the ±5-V supply
is identical to that of the ± 15-Y supply except that here the specifications for the
transformer T2 secondary are different. Therefore, the operation and design considera-
tions for the ± 5-Y supply are the same as - those presented above for the ± 15-V
supply.
The voltage regulators in Figure 11-2 will require heat sinks. The power
dissipated by the 15-Y regulators is as follows:
Power dissipated = (dropout voltage)(current)
= (18.95 - 15)(0.5) = 1.98 W
Similarly, the. power dissipated by the 5-Y regulators is ../
(8.91 - 5)(1.0) ~ 3.91 W
Therefore, for the proper operation the regulators must be heat-sinked in order
to keep their temperature down. If a regulator is a metal package (T0-3 type), the
appropriate heat sink is mounted on the case of the package. However, if the regulator
is an epoxy package, a silicon grease may be used on the back of the package and then
Sec. 11-2 Power Supply: Application of Voltage Regulators 459

the package can be bolted to the chassis of the power supply cabinet with insulating
hardware.
Besides the ± 15-V and ± 5-V regulated supply voltages, there is often a need
for a 60-Hz square-wave signal which is used as a time base in scanning the digital
displays and as a trigger for sequential and timing circuits. If needed, a 1-Hz (1-s)
signal for the real-time clock can be readily obtained from the 60-Hz signal by using
a divide-by-60 network. Although not commonly done, a higher-frequency signal
can also be obtained from the 60-Hz signal by using a multiplier. For these reasons,
in Figure 11-2 a 60-Hz square-wave signal is produced by using two small-signal
diodes and a 555 timer as the Schmitt trigger.
Parts List
Transformer T1 Primary: 117 V, 60 Hz Hobart P-300
Secondary: 26.8 V CT, 1.0 A
Transformer T2 ·Primary: 117 V, 60 Hz Hobart P-305
Secondary: 12,6 V CT, 2.0 A
Bridge rectifiers MDA200 PRY = 50 v, I.max = 2.0 A,
IPSM = 60A
MDA970Al: PRY = 50 V, I.max = 4.0 A,
/FSM = 100 A
NE555 timer
Two 1N914 signal diodes
io-sn resistor
Capacitors 3000 µFat 16 V (2): Sprague TVA1175
1500 µFat 50 V (2): Sprague TVA1318
1.0 µF at 50 V (4): Sprague TV A 1300
Regulators + 15 V: MC7815
-15V: MC7915
+ 5V: MC7805
- 5V: MC7905
Fuse 0.750 A slow blow
Switch On-off toggle type
Silicon grease with insuiating hardware or four heat sinks.
11-3 AUDIO FUNCTION GENERATOR: APPUCATION

OF THE FUNCTION GENERATOR IC
A sine-wave signal is generally used iti testing linear circuits such as amplifiers and
filters; 'on the other hand, a square-wave input is often essential for testing digital
circuits such as flip-flops, counters, and registers. In this section an audio function
generator using a specially designed integrated circuit ICL8038 will be _presented.
This IC produces not only sine and square waves but also the triangular wave.
As a first step, let us briefly consider the internal structure. operation, and
electrical characteristics of the ICL8038. Figure 11-3 shows the functional diagram
460 Selected IC System Projects Chap. 11

Current
source
1 <r-:
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14 NC
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2 13 NC
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-Vee
4 8038 11
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cycle GND
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capacitor
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+Vee 6 9 out
.
FM FM sweep
bias
7 B
input
(b)
Figure 11~3 ICL8038 waveform generator. (a) Block diagram. (b) Connection
diagram. (Courtesy of Intersil Inc.)
.461
and connection diagram of the ICL8038. The 8038 function generator is a monolithic
integrated circuit that utilizes advanced monolithic technology, such as thin-film
resistors and Schottky-barrier diodes. As shown in Figure l l-3(d), it consists of two
current sources, two comparators, two buffers, a flip-flop; and a sine converter.
The triangular wave is generated by alternately charging the external capacitor
from one current source and then linearly discharging it with another. The triangular
wave is then applied to comparators 1 and 2 and also simultaneously buffered to the
sine converter. The comparators and the flip-flop together convert the triangular
wave into a square wave, whereas the sine converter converts the triangular wave
into a sine wave. The sine converter is composed of 16 transistors. These transistors
function in a nonlinear manner by providing a decreasing shunt impedance as the
triangular wave potential moves toward the positive and negative peaks. Figure 11-4
indicates the relationship between the sine, square, and triangular waveforms gener-
ated by the ICL8031?.
Triangle wave
Sine wave
Square wave
Figure 11-4 Output waveforms of the
ICL8038. (Courtesy of Intersil Inc.)
As shown in the functional block diagram, both triangular and square-wave

outputs are buffered so that the output impedance of each is 200 n. However, the
sine-wave output has a relatively· high output impedance of l kn. For this reason
the sine-wave output is often fed into a separate noninverting amplifier which provides
buffering, gain, and amplitude adjustment, as will be seen shortly.
Figure ll-3(b) shows that the 8083 function generator is a 14-pin DfP; it is
available as a plastic.or ceramic package. The pin functions are as follows:
Pins I and 12: Sine-wave adjust. By adjusting a 100-kQ potentiometer connected

between pins 12 and 11 (negative supply or ground), sine-wave distortion of
less than 1 % is achievable. However, to obtain a distortion close to 0.5 %,
two 100-kQ potentiometers may be connected between pins 6 (+Vee) and ll
(-- VEE or ground) with the, wiper of one potentiometer connected .o pin 1
and that of the other to pin 12. ·
Pin 2: Sine-wave out. The sine-wave output is available at this pin, the ampli-
tude of which is 0.22Vs, where ±5 V <Vs< ±15 V.
Pin 3: Triangle out. The triangular output is taken out at this pin. Like the
sine-wave, the output amplitude of the triangular wave is also a function of
supply voltage Vs and is equal to 0.33 Vs, where ± 5 V < Vs < ± 15 V.
462 SH;.-.,1,.;d IC svstern Projects Chap. i1

Pins 4 and 5: Duty cycle/frequency adjust. The symmetry (50% duty cycle for
square wave) of all waveforms can be adjusted by connecting two external
resistors (generally equal in value) between+ Vee and pins 4 and 5 (see the
connection diagram shown in Figure. 11-5). These external resistors, together
with the external capacitor connected to pin 10, determine the frequency of the
output waveforms. The recommended value of external timing resistors · is
between I kn and 1 Mn so that the resultant charging current is between 10.'µA
and IO mA. The optimum performance is obtained for these charging currents.
Pin 6: + Vee· Positive supply veltage is applied to this pin so that {0 V < Vee~
30 V with respect to voltage at pin 11 ( - VEE or ground).
Pin 7: FM hias. This pin is a junction of two resistors (10 kn· and 40 kQ)
which form a voltage divider with the supply voltage(s). When this pin is shorted
to pin 8, a high output frequency is obtained, as opposed to connecting pin ~
to the + Vee for the given values of external timing resistors and capacitor.
This is because the output frequency of the waveform generator is a direct
function of the de voltage at pin 8 with respect to + Vee· This procedure is
generally used to test the ICL8038. ·
Pin 8: FM sweep input, For frequency sweeping or for larger FM deviations,
the modulating (sweep) signal is applied between the+ Vee and pin 8. In this
way a very large sweep range is created. The sweep FM range is the ratio of
• maximum frequency to minimum frequency, which can be extended to 1000:1
for the 8038. However, for proper operation the sweep voltage should be within
the range
( ~ Vee+ 2V) < V,weep < Vee
where Vee is the total supply voltage. The sweep .frequency of FM is typically
10 kHz for the 8038.
On the other hand, for small deviations (±10% typically) the FM signal
can be applied directly to pin 8.
Pin 9: Square-wave output. The square-wave output is available at this pin.
The square-wave output is in fact open collector, in that this pin can be con-
nected through a load resistor to a different power supply than that used for the
function generator itself. However, the maximum value of the power supply
used must be less than 30 V. This means that to obtain a TTL-compatible square-
wave output, a load resistor (10 kn typically) simply needs to be connected to
the +5-V supply.
In addition, the duty cycle of the square wave can be varied from 2 to
98 % by external components connected to pins 4, 5, and + Vee·
Pin 10: Timing capacitor. An external capacitor connected to this pin, together
with the timing resistors connected to pins 4 and 5, determines the frequency of
output waveforms. Oscillations can behalted by connecting pin 10 to ground.
Pin 11: - Vu/ground. If(±) supply voltages are used, a negative supply
- VEE. is connected to this pin. On the other hand, if a single supply is used,
this pin is connected to ground. With(±) supply voltages, all output waveforms
are symmetrical (bipolar) about the O.V. Obviously, if a single supply is used,
'. Sec.11-3 Audio Fun~tionGenerator: Application of the Function GeneratorIC 463

the output waveforms are unipolar; that is, their average voltage is equal to
+Vcc/2.
Pins 13 and 14: NC. No connections.
The important features of the 8038 are these:
Simultaneous outputs: sine wave, square wave, and triangle wave.

Frequency range of operation: 0.001 Hz to 500 kHz.
Low distortion: 1 %.
Low frequency drift with temperature: 50 ppm/°C maximum.
Easy to use: Requires very few external components.
Now let us see how the 8038 can be used as an audio function generator. Figure
11-5 shows a function generator that produces the sine wave, square wave, and
triangular wave and has a frequency range of less than 20 Hz to above 100 kHz.
However, around 100 kHz the quality of output waveforms starts deteriorating,
in that the sine and triangular waves distort and the square wave becomes a pulse
waveform with < 50 % duty cycle.
Although the function generation of Figure 11-5 is not of a high laboratory
standard and may not be used for calibration purposes or in critical design applica-
tions, it is nevertheless useful for beginning designers and hobbyists. Besides that,
it is simple and low in cost.
In the circuit of Figure 11-5, switch SW 2 helps to select the desired output
waveform. For the output waveform chosen, the frequency select switch SW 1 is then
used to select an appropriate frequency range; a specific value of frequency is then
obtained by adjusting potentiometer R4• R,. allows the potential at pin 8 to be varied
from + Vee to + Vcci3 with respect to ground, which in turn varies the frequency of
the output waveform. .
Potentiometer R3 is used to vary the duty cycle of the square-wave output and
hence may be used to adjust the duty cycle of the square wave to 50 %, especially
at higher frequencies. Besides that, potentiometers R1 and R9, whose· wipers are
connected to pins 1 and 12, respectively, are adjusted to minimize sine-wave
distortion.
As mentioned earlier, the square-wave output is uncommitted and is available
at pin 9. Therefore.iin order to obtain a TIL-compatible square-wave output, pin 9
may be connected through a pull-up resistor to a +s-V supply if desired. However,
in Figure 11-5, pin 9 js connected through resistor R10 and potentiometer R11 to
+ 12 V. The output amplitude of the square wave can be adjusted to a desired value by
varying R 11• Resistor R 1 0 is used i11 series with potentiometer R 11 so that the + V cc
of 12V is not directly applied to the(+) input of the op-amp (see Figure 11-5).
The triangular-wave output is available at pin 3, the amplitude of which is
(0.33)(± 12 V) = ±3.96 V. However, potentiometer R12 is used to vary the amplitude
of the triangular wave. Finally, the sine-wave output is available at pin 2. Although
the amplitude of the sine wave is (0.22)(± 12 V) = +2.64 V, it can be adjusted to a
desired value with the help of potentiometer R 1 3•

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Switch SW2 helps to select one of the three output waveforms, which is then
applied to the output stage composed of the op-amp and a power booster. The output
stage serves two functions: (1) it provides a low output impedance and (2) it in9leases
the output power drive capability of the 8038. Recall that without the output stage
the. output resistance· of the triangular and square waves is 200 n, while that of the
sine wave is 1 kn. Because the output stage is configured as a noninverting amplifier,
however, the output resistance is reduced to a negligibly small value. In addition,
the use of the power booster MC1438R (or BB3553) inside the op-amp's feedback
loop improves the output drive capability of the 8038 without degrading op-amp
characteristics. The op-amp used here is a LF351 with a slew rate of 13 V/ µs and a
unity gain bandwidth of 4 MHz. It is used as a noninverting amplifier with a gain
of 11 (see Figure 11-5). ·
For smaller-amplitude output ac signals, it may be necessary to reduce the
output offset voltage to zero initially. This is accomplished by adjusting the offset
null circuitry, namely potentiometer RP of the LF351 op-amp.
Parts List
ICL8038 function generator
LF351 op-amp
MC1438R power booster
Two 1-kn resistors
1-kn potentiometer
Two 3.9-kn resistors
Four io-xn resistors
Three io-in potentiometers
20-kn resistor ·
Two zo-in potentiometers
Two 100-kn potentiometers
470-pF capacitor
0.001-µF capacitor
0.01-µF capacitor
0.1-µF capacitor
Three 1.0-µF capacitors
10.0-µF capacitor
Five-position switch
· Three-position switch
11-4 LED TEMPERATURE INDICATOR: APPLICATION

OF THE V/F CONVERTER AND THE 555 TIMER
This, project illustrates the use of a V/F converter in monitoring temperature in
degrees Fahrenheit (°F). The block diagram of the temperature indicator is shown in
Figure l 1-6(a). The indicator is composed of a temperature sensor, amplifier, V/F
Selected IC System Projects Chap. 11

converter, three-digit binary-coded-decimal (BCD) counter, time base, and LED
display. In addition to the 9400 V/F converter, other ICs needed for this project
include the LM334 temperature sensor, LF353 dual op-amp, NE555 timers, 74LSOO
NAND gate, MC14553 three-digit BCD counter, MCI4543 BCD-to-seven segment
decoder/driver/latch, and three seven-segment (common anode or common cathode)
LED displays with three PNP switching transistors.
Figure 1 l-6(b) shows the schematic diagram, which is designed to display
temperatures from O to l00°F. Operation of the circuit is as follows. The output
of the temperature sensor changes linearly as a function of temperature (IO mV/°K).
This output is an input to the summing amplifier, which is used to calibrate the output
of the temperature sensor for a desired temperature type (°K, °C, or °F) and an
intended range. That is, in order to display the temperature in either "K, °C, or °F,
potentiometer R4 is adjusted accordingly so that a suitable voltage appears at the
output of the summing amplifier. Since the output of the temperature sensor is
directly proportional to temperature changes, R4 needs to be adjusted at only one
temperature. The output of the summing amplifier then drives the inverting amplifier.
The purpose of the inverting amplifier is twofold: (1) to invert the input so that its
output voltage is positive, which is necessary for the V/F converter, and (2) to provide
a suitable gain, which depends on the voltage-to-frequency scaling used for the V/F
converter.
· The output of the inverting amplifier is the input to the V/F converter; therefore,
the output frequency of the converter is directly proportional to the output voltage
of the inverting amplifier. For example, as the temperature goes up the output voltage
of the summing amplifier increases in the negative direction, whereas that of the
inverting amplifier increases in the positive direction, which in turn causes the
frequency of the V/F to increase in the positive direction.
The output frequency of the converter is then ANDed with the gating signal to
produce the clock signal for the three-digit BCD counter. The BCD output of the
counter then drives the three LED displays sequentially via the BCD-to-seven segment:
decoder/latch/driver stage, and the temperature is displayed on the LEDs, depending
on the relationship between the frequency of the V/F converter and the gate signal.
The gate, latch, and reset signals are generated by the time-base circuit, which consists
of a free-running multivibrator and two one-shot multivibrators.
LED
displays
Temperature V/F Three-digit

sensor Amplifier converter counters
Time base
(a)
Figure 11-6 LED temperature indicator. (a) Block diagram.
Sec.11-4 LED Temperature Indicator: Application of the V/F Converter 4$7

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enable
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~,vt--~n
I I
+-l I-+- 0.5 I I
Master
reset
av
I I
n
I I
t(ms)
(cl
Figure 11-6 (c) Timing diagram.
Next let us examine the design considerations and procedures for each of the
sections in the temperature indicator of Figure ll-6(b). The temperature sensor
LM334 is a three-terminal adjustable current source whose current can be pro-
grammed from 1 µA to 10 mA with one external resistor R,.t· The three terminals
are labeled + V, R, and - V. The pin diagram and the connection diagram of the
LM334 are shown separately in Figure 11-7.
The LM334 has a wide operating voltage range of 1 to 40 V. It can also withstand
reverse voltage of up to 20 V (terminal+ Vis negative with respect to -V). It is
designed to operate over a temperature range of Oto 70°C. For a wider temperature
range, such as -55 to 150°C, Intersil's AD590 temperature sensor is recommended.
For the values indicated in Figure 11-6(b), the output of the LM334 changes
10 mV/°K. This means that at 0°F = 255.22°K, the output of the sensor will be
2552.2 mV, which must be scaled down to O V so that the temperature displayed will
bein degrees Fahrenheit. This is accomplished by the use of the summing amplifier.
Specifically, potentiometer R4 of the summing amplifier is adjusted so that the output
is O V. The same procedure is used to calibrate the output of the summing amplifier
at any other value of °F. Table 11-1 shows the relationship between °K, °C, °F and
the output of the temperature sensor and the summing amplifier at corresponding
values of temperature. Because the output of the sensor is directly proportional to
the temperature, the output of the summing amplifier needs to be calibrated at the
temperature at which the circuit is initially started up (referto Table 11-1).
Note that the output of the summing amplifier is a negative de voltage since
the net input voltage is always positive for temperatures > 0°F (see Table 11-1).
Sec. 11-4 LED Temperature Indicator: Application of the V/F Converter 469
+v
I,., i +V
Roe,
-v
V0=RLI..,
+V -v
R RL.
(a) (bl
Figure 11-7 LM334 as a temperature sensor. (a) Pin diagram. (b) Connection
diagram; (Courtesy of National Semiconductor.)
TABLE 11-1 RELATIONSHIP BETWEEN DIFFERENT TEMPERATURE UNITS

AND OUTPUTS OF THE SENSOR AND SUMMING AMPLIFIER
Output of the
Degrees Degrees Degrees Output of the summing amplifier
Kelvin Celsius Fahrenheit temperature (mV) to be
(OK) (QC) (°F) sensor (mV) adjusted to
1. 255.22 -17.78 o· 2552.2 0

2. 273 0 32 2730 -177.8
3. 298. 25 77 2980 -427.8
4. 3_10.78 37.78 100 3107.8 -555.6
However, the 9400 V/F requires a positive input voltage. The summing amplifier
must therefore be followed by an inverting amplifier. The gain of the inverting
amplifier, however, depends on the voltage-to-frequency scaling of the converter.
The V/F converter of Figure 1 l-6{b) is calibrated for a maximum frequency of 50 kHz, .
which represents a temperature of 100°F when the input voltage is 10 V maximum.
For 9400 V/F calibration procedure refer to Section 9-10.l(b). Since the output
of the summing amplifier is -555.6 mYat 100°F, the gain of the inverting amplifier
must be equal to
IOV ....., 18
555.6mv=
The output frequency of the V/F converter is then ANDed with the output
frequency (called the gate signal) of the 555 free running multivibrator to produce the
470 SelectedIC SystemProjects Chap. 11

clock signal for the three-digit BCD counter. Since the maximum 50 KHz output
frequency of the converter represents I00°F, the three-digit BCD counter must be
clocked 100 times in order to display l00°F. To accomplish this, the pulse-width of
the free running multivibrator must be 100/50 K = 2 ms so that 100 pulses will be
produced in 2 ms. At the end of 2 ms, the count of the counter is latched and dis-
played on the LED display. After the count is displayed as a temperature on the
LEDs (50 KHz V/F output frequency represents 100°F), 'the BCD counter is reset .
and the cycle repeats. In other words, the counter continuously cycles through three
states: count, latch, and reset. Therefore, the free running multivibrator (gate signal)
must provide for the time period required to count, latch, and reset the BCD counter.
The latch enable and master reset pulses for the BCD counter MC14553 are produced
by using two 555 one-shot multivibrators. Figure 1 l-6(c) indicates the timing diagram
for the BCD. counter MC14553, where the time period of the free runningmultivibrator
is approximately 12.5 ms with a pulse width of 2 ms. The pulse width of the latch
enable pulse is approximately l O ms, and the master reset pulse width is approximately
0.5 ms. To accomplish 2 ms, 10 ms, and 0.5 ms pulse width, adjust potentiometers
R,1., R,1.1, and R,1.2, respectively. (Figure l 1-6b).
The three-digit BCD counter used in Figure l l-6(b) is the MC14553. The block
diagram and pin diagram of the MC14553 is shown in Figure 11-8. As shown in the
block diagram, the MC14553 consists of three negative-edge-triggered BCD counters
with a quad latch at the output of each counter, which enables the storage .of.any
given count. The outputs of the latches are time multiplexed so that one BCD digit
at a time is produced. The operation of the multiplexer output selector is controlled
by the on-chip oscillator, whose frequency depends on the external capacitor.
The pin functions are asfollows:
Pins 2, 1, and 15: DSJ, DS2, and DS3. These are the active-low digit-select
outputs which sequentially control the three LED/LCD displays.
Pins 4 and 3: CJA and CJB. An external capacitor C1 between these pins controls
. the frequency of the on-chip oscillator, which in turn drives the multiplexer
output selector. If an external clock is to be used instead of the capacitor, the
clock must be applied to pin 4.
Pins 9, 7, 6, and 5: Q0, Q1, Q,., and Q3• The BCD outputs are available at
these pins and are active-high.
Pin 8: Vss· This pin is connected to ground potential. The (+)supply voltage
is also measured with respect to this pin.
Pin JO: LE. This is a latch-enable input pin. When the latch-enable input goes
high, the information in the BCD counters is stored in the quad latches and is
retained as long as the latch is high.
Pin 11 :· Dis. When an external input pulse applied to this pin goes high, the
input clock is disabled, which in turn freezes the counters. However, the last
count in the counters is retained. When not used, this pin should be connected
to ground.
Pin 12: Clock. The input trigger source for the counters is connected to this
Sec. 11-4 LED TemperatureIndicator: Application of the V/F Converter 471

!Digit select 2) 052 1 • 16 I supply
Voo
(Digit select 1 J 051 15 053 !Digit select 3)
External { C1B 3 14 OF (Overflow)
oscillator
ceoacuor C1A 4 13 MR (Master reset)
MC14553
a, 5 12 Clock
aco { o, 6 11 D,s !Oisoblo)
outputs
a, 10 LE ( Latch enable)
IG•our.dJ v ss 9 00 (BCD output)
lo)
Scan Pulse
oscillator generator
Scanner
00
c
Pulse 01 Quad
shaper latch
02
A +10
Tens 03
00
11
Disable
(active
high)
01
00
c BCD
01 outputs
Quad Multiplexer (active
02 latch
high)
A + 10
Units 03
02
03
00 1--.---1
c
011--1----<
Quad
02 1--1---l latch
13
MA Overflow
lacuve high)
I LSD) Di91t select IMSDI
(active low}
Figure 11-8 MC14553 three-digit BCD counter. (a) Pin diagram. (b) Block
diagram. (Courtesy of Motorola Semiconductor.)
472
pin. The counters are advanced on each high-to-low (logic 1 to 0) transition
of the input trigger.
Pin 13: MR. When an input pulse applied to this pin goes high, the three BCD
counters and the multiplexer scanning circuit are initialized (reset). In addition,
the scan oscillator is inhibited, and digit-select outputs OS 1, DS2, and DS3
are disabled. For that reason, this pin is called master reset (MR).
Pin 14: OF. This pin indicates the overflow condition of the counters. The
voltage at pin 14 goes high for every 1000 counts and hence can be used to
1
cascade multiple MC14553s.
Pin 16: VnD· A (+)supply voltage up to+ 18 V de can be applied to this pin
with respect to pin 8 (Vss).
As shown in Figure 11-6(b ), the master reset (MR) and latch enable (LE) pulses
for the MC14553 are produced by using two 555 one-shot multivibrators. In addition,
the clock signal for the MC14553 is produced by ANDing the output of the V/F con-
verter with the gating signal, which is obtained by using the 555 free-running· mul-
tivibrator. (For more information on the 555 timer, refer to Section 10-3.) The digit
select outputs DS 1, DS2, and DS3 sequentially drive the 2N 1305 PNP transistors
T1, T2, and T3, which in turn control the three LED displays. The BCD outputs of
the MC.14553 are connected to the -BCD inputs of the MC14543, which is a BCD-to-
seven segment latch/decoder/driver [see Figure l l-6(b)]. The seven-segment outputs
of the MCJ4543 then drive the seven segments of the LED selected by the digit-select
of the MC14553. .
The MC14543 is designed to provide three functions: a 4-bit storage latch,
an 8421 BCD-to-seven segment decoder, and a driver. The device is capable of driving
· LCD and LED displays. Figure 11-9(a) shows the pin diagram, with pin functions
as· follows : ·
Pin 1: LD. Since this pin is used to enable and disable the latches of the device,
it is called .latch disable (LO). When this pin is high (connected to Vnn), the
BCD at the input is latched into the device. On the other hand, when this pin
is low (connected to Vss), the latches are disabled.
Pins 5, 3, 2, and 4: A, B, C, and D. These pins are the input pins to which the
BCD inputs are applied.
Pin 6: Ph. This pin is called a phase invert (Ph) pin because it is used to invert
the logic levels of the seven-segment output combinations. That is, when this
pin is logic O (connected to Vss), the MC14543 can drive common cathode
LED readouts. On the other hand, for common anode LED readouts, this pin
must be logic 1 (connected to VnD).
Pin 7: BI. When this pin is logic 1, the display is blanked; hence it is called
blanking input (Bl). However, if this pin is logic 0, the display reads the BCD
number corresponding to the code at pins 2, 3, 4, ~id 5.
Pin 8: Vss· This is a ground pin, and (+)supply 11nD is measured with respect
to it.
Pins 9, JO, 11, 12, 13, 15, and 14: a, b, c, d, e, f, g. These pins represent the
Sec. 11-4 LED Temperature Indicator: Application of the V /F Converter 473

-- 1 • 16 --
-
- 2 15 -
-
-
- 3 14
-- g
- 4
MC14543
13 -- e
- 5 12
- d
Seven-segment
outputs
-- 6 11 -- c
-- 7 10 -- b
-- 8 9 -- a
(a)
dp e
/b)
Figure 11-9 . (a)· MC14543 BCD-to-seven segment latch/decoder/driver pin
diagram. (Courtesy of Motorola Semiconductor.) (b) LED segments.
seven-segment outputs corresponding to the BCD code at the inputs A, B, C,

and D [see the LED segment assignment shown in Figure 11-9(b)].
Pin 16: VDD· A (+)voltage of 3.0 to 18 V de can be applied to this pin with
respect to pin 8 (Vss),
As shown in Figure 11-6(b), the Ph pin 6 of the MC14543 is connected to VDD

(logic 1) because the LED displays are the common anode type. In order to limit
the current through each of the LED segments, a separate resistor is used in series
with each segment. Note, however, that only seven resistors are required for all the
segments of the LEDs. This is possible because the digit-select outputs of the MC14553
function sequentially. In addition, the BCD outputs are also multiplexed, one BCD
digit at a time.
Finally, since the accuracy· of the temperature displayed depends mainly on
the frequency stability of the free-running multivibrator, all resistors must be of
1 % or better tolerance, and capacitors must be either Mylar or tantalum types.
474 Selected IC .svstern Projects Chap. 11

Also, remember that the temperature indicator must be calibrated 'at the temperature
at which it is initially turned on.
Parts List
Teledyne 9400 V /F converter
1~ LM334 temperature sensor
LF353 dual op-amp
Three NE/SE 555 timers
74LSOO NAND gate
MC14553 three-digit BCD counter
MC14543 BCD-to-seven segment decoder/driver/latch
Three seven-segment common anode LEDs: MAN72A or equivalent
Three 2Nl 305 switching transistors
Two 1N914 signal diodes
Seven 220 n resistors
Three 1-kO resistors
Two 1-kO potentiometers
3-kn potentiometer
Five io-sn resistors
Two 10-kO potentiometers
15-kQ resistor
20-kQ resistor
Two 50-kQ potentiometers
. Four 100-k!l resistors
180-kQ resistor
510-kQ resistor
I-Mn potentiometer
100-pF capacitor
Two 0.001-µF capacitors
Five 0.01-µF capacitors
Three 1-µF capacitors
10-µF capacitor
All resistors with ± I % tolerance and all capacitors either Mylar or tantalum.
11-5 DIGITAL DC MOTOR SPEED CONTROL: APPLICATION

OF THE DIA AND F/V CONVERTERS
Various techniques can be used to control the speed of a de motor, such as using
the phase-locked-loop principles, digital inputs, or analog inputs. If desired, the
speed of the motor may also be monitored with LED or LCD displays. This project
illustrates the use of digital inputs to control the speed of a de motor. To process
Sec. 11-5 Digital de Motor Speed Control: Application of the D/A and F/V 475
the digital inputs, aD/ A converter will be used, while a combination of a speed sensor
and F/V converter will be used to sense and convert the speed into an appropriate
voltage.
Figure 11-10 shows the block diagram of a digitally controlled de motor. The
output of the D/A converter is proportional to the binary equivalent of its digital
inputs. The differential amplifier compares the D/A converter output with the output
voltage of the F/V converter. The resulting difference voltage is an input to the power
amplifier/driver stage. The output of the power amplifier/driver then drives the de
motor. The speed sensor converts the motor's speed into a pulse waveform, which
is in turn converted into a proportional voltage by the F/V converter. Since the output
o(Jhe F/V converter is processed using a negative feedback for~ed with the differ-
ential amplifier, the motor is kept at a constant speed corresponding to the setting
of the digital inputs. In fact, the key to the operation of the circuit is that the dif-
ferential amplifier maintains a specific difference between two input voltages so that
motor speed is constant at the selected digital input setting.
MSB
Motor
Digital
inputs
{ LSB
D/A
converter
Differential
amplifier
Power
amplifier/
driver
I
I
Analog I
voltage I
I
F/V Speed
converter sensor
Figure U-10 Block diagram of a digitally controlled de motor.
Since the output of the D/A converter is directiy proportional to the binary
equivalent of its digital inputs, the output voltage of the D/ A converter will be
maximum positive when all the inputs are logic 1. This means that when all inputs
are logic "1," the motor will run at a maximum speed.
Now suppose that the motor is initially running at a certain speed, and digital
inputs have just been set to lower the speed. This action will reduce the output voltage
of the D/ A converter, which in turn reduces the difference between the two input
voltages of the differential amplifier, resulting in a reduced drive for the motor.
Therefore, the speed of the motor will be lowered until the output of the F/V converter
is such that a specific input difference voltage for the differential amplifier, which is
required to keep the motor running at a constant speed, is reached. The difference
voltage necessary to maintain the constant motor speed is a function of the physical
dimensions and electrical characteristics of the motor. These include torque, speed,
inertia, current and voltage ratings, and gain of the differential amplifier. Thus the
constant difference voltage and, in turn, a constant motor speed are maintained
through the use of negative feedback.
The digital inputs may be calibrated in terms of revolutions per minute

(RPM). In addition, the output of the speed sensor may be applied to the frequency
meter/RPM indicator in order to monitor the motor's speed.
Figure 11-11 shows the schematic diagram of a digitally controlled de motor.
As shown in the figure, the following I Cs are used: SN74LS241 octal tri-state buffer,
MCI408 8-bit D/A converter, MCI403 2.5-V voltage reference, L.F353 dual op-amp,
9400 F/V converter, and the Hall effect transducer. The desired .digital inputs are
selected by the use of a switch assembly. The eight LEDs indicate the state of the
digital inputs applied to the D/A converter. When a switch is open, the corresponding
LED lights up. The 74LS241 octal tri-slate buffer is used here because it isolates the
LEDs from switches and also provides a current drive for the LEDs.
· In Figure 11-11 the only device that is not discussed so far is the Hall effect
transducer. A number of materials exhibit the Hall effect in that when a current-
carrying semiconductor strip (usually silicon) is placed in the transverse (perpendicular)
magnetic field, the combination produces an EMF between the opposite edges of the
strip. This EMF is proportional to the product of the current and field strength.
On the other hand, when the magnetic field is zero, or of specific polarity, an EMF
between the opposite edges of the strip is also zero. Thus the Hall effect transducer
is a magnetically activated electronic switch that can be used for sensing a magnetic
field. ·
Figure 11-12 shows the equivalent circuit, operating arrangement, and an
electrical switching characteristic with hysteresis of Texas Instrument's TLl 70 bipolar
Hall effect switch. The TLl 70 is a three-terminal plastic package which consists of
a silicon sensor, signal conditioning and hysteresis function, and an open-collector
output stage integrated onto a monolithic chip [see Figure l l-12{a)]. The output of
the device is compatible with bipolar or MOS logic circuits. Figure 1 l-12(b) shows
the practical setup for the on state. The sensor is "on" (output voltage< 0.04 V)
when the magnetic field (BoN) associated with the permanent-magnet north pole is
perpendicular to the surface of the sensor and below a certain level, called the operate
point or the threshold. On the other hand, the sensor is "off' when the magnetic field
(BoFF) emitted from the south pole of a permanent magnet is perpendicular to the
surface of the sensor and above a certain level,. called the release point. The TLl 70
has a typical operate point of< -3,60 gauss and a release point of> 350 gauss with
a magnetic switching hysteresis '(BoN - Bopp) of 200 gauss typically. Obviously,
the negative and positive magnetic fields are defined as those fields that are emitted
from the north and south poles, respectively, of a permanent magnet. The magnetic
switching hysteresis curve of the TL170 is shown in Figure ll-12(c). The sensor is
designed so that its output stage can withstand up to 20 V in the off state and can
sink up to 16 mA in the on state.
To operate, the TLI 70 sensor is positioned so that the plain surface of the
sensor faces the permanent magnet. In addition, to obtain two samples per revolution
and hence help to control the motor speed more accurately, four permanent magnets
are used in Figure 11-11. These magnets are glued to the 4-in.-diameter disk with
alternately south and north poles up, as shown in Figure 11-12(d). The disk is then
mounted oh the motor's shaft. When the motor is running, the TLI 70 is turned on
due to the magnetic field strength of the north pole and turned off due to the magnetic
Sec. 11-5 Digital de Motor Speed Control: Application of the D/A and F/V 477
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478
r----------------1
I I
I I
- I Integrated Signal ~--,---Q Output
Magnetic - I silicon conditioning I
field I Hall and I
- I sensor 1hysteresis I
I I
L --~
GND
(a)
v.:
On state Off state

(operate) (release)
Output
-350 0 +350
(North (south
GND pole) pole)
(b)
-, Field strength, B
(c)
On
Non-magnetic disk
On
(d)
Figure 11-12 TLI 70 bipolar Hall effect switch. (a) Equivalent circuit. (b) On-
state arrangement. (c) Electrical switching characteristic. (d) Practical setup.
(Courtesy of Texas Instruments.)
479
field strength of the south pole. Therefore, because of four permanent magnets the
sensor will generate two cycles per revolution. The distance between the magnets
and the sensor, however, depends on the field strength of the magnets. For the TLl 70
used in Figure 11-11, a magnetic field strength magnitude of > 350 gauss is necessary.
· When the motor is running, the distance between the disk and sensor can be adjusted
· so that the output of the sensor is a pulse waveform. Remember that the output ampli-
tude of the sensor depends on the supply voltage and is independent of the RPM of
the motor.
Now let us reconsider the circuit of Figure 11-11. The D/A and F/V converters
in this figure should be adjusted initially as follows:
1. With all the inputs high (logic I), adjust R17 so that the output voltage of the
1-to-V converter is 3.0 V.
2. Disconnect pin 11 of the F/V converter from the junction of R27 and R26•
First, use the zero-adjust circuit connected to pin 2 to reduce the output voltage
to zero. Second, apply 160 Hz 5 V pp symmetrical square wave to pin 11 and
adjust R10t until the output voltage is equal to 3.0 V.
Once the adjustments are performed in this order, they should not have to be
repeated. Note that the F/V is calibrated for maximum expected speed of the motor.
InFigure 11-11, the motor speed is
4800 RPM = ( 4800X2) = 160 Hz
60
The motor in Figure 11-11 initially starts running when the input binary code is
(00000110)2• Thereafter, the motor speed increases with the digital input until the
motor attains a maximum speed at (00111111)2• After (00111111)2 however, the motor
speed does not increase further even though the digital input is increased. In other
words, we get 6-bit resolution instead of 8-bit. To obtain 8-bit resolution, an appro-
priate DAC with better resolution, a motor having favorable electromechanical spe-
cifications, and a differential amplifier with proper gain must be selected. The principles
illustrated in the digital de motor speed control of Figure 11-11 are used in the cruise
control of automobiles.
Parts List
SN74LS241: tri-state buffer

MC1408: 8-bit D/A converter
MC1403: 2.5-V voltage reference
LF353: dual op-amp
Teledyne 9400: F/V converter
TRW 405A100-1: de motor
2N6569 and 2N6594: complementary power transistors
TLl 70: bipolar Hall effect switch
FLY 117: light-emitting diodes (8)
Miniature 8-slide or rocker DIP switch

Heat sinks for power transistors
Four small magnets with field strength magnitude> 350 gauss
Nonmagnetic disk 4 in. in diameter
Eight ,220-n resistors
Three 1-kn resistors
1.5-kn resistor
2.2-kn resistor
Eight 4.7-kn resistors
Six 100-kn resistors
1-kn potentiometer
20-kn potentiometer
I-Mn potentiometer
Two 2.5-Mn potentiometers
15-pF capacitor
75-pF capacitor
0.001-µF capacitor
_0.1-µF capacitor
1.0-µF capacitor
11-6 APPLIANCE TIMER: APPLICATION OF THE 555 TIMERS
The previous project showed how the Hall effect transducer works as a magnetic
sensor. This project introduces another important type of transducer, an optical
coupler. An optical coupler together with a square-wave generator and counters
can be, used to construct a timer for appliances. That is, an appliance can be turned
on at a desired time for a specific time internal. Figure 11-13 shows a block diagram
of such a timer.
As shown in Figure 11-13, the output of the square-wave generator is used as
a clock (trigger signal) for the divide-by-N counters. A divide-by-N counter is a
digital IC that produces a single output pulse for every N input pulses, where N is an
integer. The integer N is commonly called the modulus of the counter. There are
Square-wave Divide-by- One-shot Optical

N Appliance
generator multivibrator coupler
cgunters
Reset
control
circuit
117 V
60 Hz
Figure 11-13 Block diagram of an appliance timer.
Sec. 11-6 ApplianceTimer: Application of the 555 Timers 481

basically two types of divide-by-N counters: fixed and programmable. For example,
the 7490 is the fixed modulus type and can be used as a divide-by-5 or divide-by-10
counter. On the other hand, the 74192 is a programmable counter which can be
programmed to divide from 1 to 15. Often, in order to increase the resultant output
count, the fixed-modulus type counters are connected in series (cascaded). In this
arrangement the output of the first counter is the input to the second, the output of
the second counter is the input to the third, and so on. Using the cascading technique,
time delays of hours, days, or even weeks can be achieved.
In Figure 11-13, the output of the divide-by-N counters is then applied to a
one-shot (monostable) multivibrator, the output of which in turn drives the optical
coupler. The output pulse width of the one-shot controls the time an optical coupler
is on. The output of the monostable multivibrator is also applied to the reset control
circuit, which halts the square-wave generator and also resets the circuit for restart
operation.
The resistor-capacitor combination used for the monostable determines its
output pulse width. When the output pulse goes high (logic Oto 1), the optical coupler
is triggered and the appliance turns on. On the other hand, when the output pulse
width of the monostable goes low (logic 1 to 0), the optical coupler is disabled and
the appliance turns off. At the same time, the negative transition of the pulse also
triggers the reset control circuit, which in turn shuts off the square-wave generator.
Thus the circuit is ready for the next cycle.
Before considering the schematic diagram of the appliance time~xamine
the operation of Motorola's MOC301 l, an optically isolated triac driver. Figure
11-14 shows the internal construction and the pin diagram of the MOC301 l. The
• Main terminal
Triac driver substrate

DO NOT CONNECT
Figure 11-14 MOC3011 internal

Main terminal
structure and pin diagram. (Courtesy
MOC3011 of Motorola Inc.)
3011 consists of an infrared emitting diode, optically coupled to a silicon bilateral

switch, and is available as a 6-pin DIP. The bilateral switch, commonly known as a
diac, is a member of the thyristor family. Other members of the thyristor family are
the silicon-controlled rectifier (SCR) and the triac. A peculiarity of the thyristor is
that it consists of four layers-P, N, P, and N-and is primarily designed for high-
voltage and high-current switching 'applications. The diac consists of ~gh-voltage/
current diodes connected in opposite directions. On the other hand, the major dif-
ference between the SCR and triac is that the SCR conducts in only one direction,
while the triac conducts in both the directions. In fact, the triac.is two SCRs connected
in opposite directions. Both the SCR and triac are three-terminal devices (anode,
cathode, and gate), whereas a diac is a two-terminal device (anode and cathode).
In the internal structure of the 3011, even though a symbolic notation for the
482 Selected IC System .Projects Chap. 11

diac is shown between output pins 4 and 6, this component actually works as a tirac
since its operation is controlled by the infrared emitting diode. The maximum electrical
ratings of an.infrared emitting diode are as follows:
1. Reverse voltage (VR) = 3.0 V.

2. Continous forward current (Ip) = 50 mA at forward voltage (Vp) of 1.5 V.
On the other hand, _the output driver maximum electrical ratings are:
1. On-state output terminal voltage (VnRM) = 250 V.

2. On-state rms current Ur) = 100 mA.
3. Peak nonrepetitive surge current (/ISM) = 1.2 A.
4. Isolation surge voltage (an internal device dielectric breakdown rating) (V150) =
7500 V peak.
In addition, the total device power dissipation is 330 mW, and the LED trigger
current-the current required to latch output-is 5 mA typically.
Now let us see how the 3011 is used in the appliance timer. Figure 11-15 shows
the schematic diagram of the timer, which is designed to switch an appliance on 23
min after the initial startup time. The appliance remains on for approximately 12
min. The 556, a dual 555 timer, is used to form the astable and monostable multi-
vibrators. The time between the pulses as well as the output pulse width of the timers
is limited by the size and cost of the timing components. In the circuit of Figure 11-15,
the time period of the pulse output waveform of the astable multivibrator is
/T = 0.69(RA + 2RB) C ~ 11.5 min, even though a maximum time period of approxi-
mately 20 min is possible. The output pulse waveform of the astable multivibrator
works as a clock for the SN74177 4-bit binary counters/latches.
The SN74177, a 14-pin DIP, consists of four de-coupled master-slave flip-flops,
which accept frequencies of O to 35 MHz at the clock 1 input and O to 17 .5 MHz
at the clock 2 input (see Figure 11-15). It is fully programmable and triggers on the·
negative-going edge of the clock pulse. A, B, C, and D are the data inputs and
QA, QB, Qc, and Qn are the outputs. When the count/load (pin 1) is low, the outputs
directly follow the inputs. However, when the count/load is high (logic l)' and the
clock inputs are inactive, the outputs remain unchanged. The clear terminal (pin 13),
when taken low (logic 0), sets all outputs low regardless of the states of the clocks.
In Figure 11-15, the SN74177 is used as a 4-bit ripple-through counter in which
output QA must be externally connected to the clock 2 input. The output of the astable
multivibrator is applied to the. clock 1 input. In addition, the count/load is connected
to +5 V and clear is taken low each time the timer is used. In fact, this arrangement
enables the 74177 to perform simultaneous divisions by 2, 4, 8, and 16 at the QA,
QB, Qc, and Qn outputs, respectively. That is, the outputs at QA, QB, Qc, and Qn
will have time periods of 23, 46, 92, and 184 min. However, only the QA output is
used in Figure.l l-l S. To achieve longer time periods, output Qn of the 74177 can be
used to clock the next SN74177, and so on. In addition, by using all four outputs
of the 74177, three more appliances can be controlled, although at different times.
Sec. 11 -6 Appliance Timer: Application of the 555 Timers 483

.,c., ;:
c > ...
.!!! o::c
LL
::i. a.
a.
v -o
- cc
0 ~ 0
c..
+
~
o"'
cc
--
(')
'<t
0
N
o
0
.., ::;E
a:
cc
<t'l
-,.-.
<t'l
M N
CXl
a:"' o.ri
..:
u..
r-,
.....
~
e
··,;:
::i. '<t
8i::
0 ...
r-;
.2!
0 ..:,/.
o
~c p.
f--
ac.. a: c: ..:,/.
I 2.
Uf--
0
<
c..
(/) 0
c
~ a ......
Ill
~
'<t
CXl
z
o r-,
...I
N~
..J f
(/)
N
u
u u =
>
c
0 >
u
u
'<t
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-c
a a"' a
u
>
(')
'<t
l
~---0 ~
a
"'u
[I] ..J ON
o-
CD ..... 0
~ .....
~ N
.....
-.....
'<t a,
'<t ..... 0
u a ::c
M z <t'l '<t
o
~
.,
u"'
'<t
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CXl "'
"'
0 o
:;;
~
<;
c:, ,~u UltOL
(')
0
u
a:
.. ..>..
r-, <t'l
~
'<t
cc
<t'l
s,
0 ::i.
_, ...
<t'l (') c
.....
0
:::~
:, u + f-i-t>
c:
N cc
LL
::i.
-,--
-i'
(/)
..
.o.~
~~
:,
c..
..:,f.
.,:- u§
a: o.ri
+ 00
484
The Q.. output of the 74177 with a time period of 23.0 min is applied to the
monostable multivibrator, which bas a pulse width of approximately 12 min. Note
that the waveshaping network composed of R1, C1, and D1 is used between trigger
pin 8 and the Vee pin 14. This arrangement assures proper operation of the monostable
multivibrator, since the negative pulse width of the input trigger will be shorter than
that of the output pulse width of the monostable multivibrator. Thus in Figure 11-15,
23 min after the timer is initially set the appliance will come on and will remain on
for approximately 12 min. At the epd of 12 min, the output pulse width of the mono-
stable goes low (logic 1 to 0), which disables the 3011 and the appliance turns off.
At the same time, the negative transition in the output pulse of the monostable
multivibratoralso triggers the reset control circuit and shuts the astable multivibrator
off.
The reset control circuit is composed of a single J-K negative-edge-triggered
flip-flop with preset and clear. The Q output of the flip-flop is connected to reset
pin 4 of the astable multivibrator and is normally high (logic 1). However, when the
output pulse of the monostable goes low, it switches the Q output low (logic 0),
which in turn shorts out the reset terminal. This halts the astable operation and
prevents further clocking of the 74177 counters. -The end result is that the appliance
goes through one cycle (off-on-off) and then stops. Initially, to start the timer first
apply the power to the timer by placing switch SW 1 in the ON position, Second,
depress the START switch SW2• With SW2 depressed, the J-K flip-flop is preset
(Q = 1) and the reset terminal of the astable multivibrator is pulled high (logic 1).
The switch SW2 also clears the Q .. , QB, Qc, and QD outputs of the 74177 counters.
Now the timer is on and the appliance will come on in approximately 23 min and
will remain on for approximately 12 min. At the end of 12 min the appliance turns
off and the Q output of the J-K flip-flop switches low. This action shuts off the astable
multivibrator and hence the timer. To restart the timer, simply depress the START
, switch SW 1• When the timer is not in use, switch SW 1 should be in the off position.
The timing diagram for the circuit in Figure 11-15 is shown in Figure 11-16. In the
appliance timer of Figure 11-15 since the maximum on state rrns current applied by
the MOC3011 is 100 mA, the power rating of an appliance whose operation is to be
controlled must be < 11 W = (110 V)(l 00 niA):However, for appliances with higher
power ratings .(>11 W), a triac with appropriate electrical specifications (V and/)
may be used between the MOC3011 and an appliance. For more information on using
the triacs with the MOC301 l, refer to the MOC301 l data sheets. Finally, to verify the
operation of the appliance timer, a 5-W light bulb may be used as the appliance.
The timer concepts discussed above can be used to control the operation of
a furnace or central air conditioning unit so that it comes on at a desired time. For
example, a timer may be used to shut off the furnace in the house after 10 P .M. and
turn it back on at 5 A.M. This arrangement will help to save energy and money,
especially in winter.
The ~ncepts of appliance timers can also be used in switching house lights
on and off ll regular intervals, especially when the owner is on vacation. This provi-
sion should discourage burglars. In fact, when cyclic operation of the timer is desired,
the reset control circuit shown in Figure 11-15 is not needed.
Sec. 11 -6 Appliance Timer: Application of the 555 Timers 485

a! 5V
Astable
output
'
O V ...__....__.___....__.__ t (min)
11.5 min
a! 5 V ~--------
Counter
QA output
O V ---------------
---23 min---•...il
Appliance on
e!5V
Monostable Appliance off
output
OV 1---------L--_._ __
11·2 mi~I
I
I
I
I
I
e! 5 V !
J-K flip-flop
Q output
av 1-----------_._ ._. Figure 11-16 Timing diagram for the
,_,_---35min---- appliance timer.
Parts List
NE556 timer
SN74177 4-bit binary counters/latches
MOC30Yl optically isolated triac driver
SN74H102 single J-K flip-flop or 7476 dual J-K
1N914 signal diode
390-0 resistor
4.7-kQ resistor
5.1-kQ resistor
Two ro-xn resistors
Two 5.1-MQ resistors

Three 0.01-µF capacitors
1.0-µF capacitor
10-µF capacitor
100-µF capacitor
130-µF capacitor
SPDT switch
Pushbutton switch (normally open)
11-7 SIREN/ALARM: APPLICATION OF THE LM380 POWER

AMPLIFIER
Devices such as burglar alarms and sirens, whose basic purpose is to monitor certain
conditions, make enjoyable projects because of the variety of sounds they can generate.
Figure 11-17 shows a simple siren/alarm circuit using a dual op-amp MC1458, audio
amplifier LM380, and a 1-W speaker. The dual op-amp is used as a signal generator
which produces square, pulse, and triangular or sawtooth waveforms as discussed in
Section 8-17, while the operation of the audio power amplifier LM380 is explained
in Section 10-5.
The operation of the circuit is as follows. The A 1 and A2 op-amps make up a
waveform generator in which the output of A1 is a square wave or pulse waveform
and that of A2 is either a triangular or sawtooth waveform. The potentiometer R2
controls the frequency as well as the type of output waveform of op-amps A1 and A2•
The switch SW 1 then connects the output of A 1 or A2 to the audio power" amplifier
LM380, which in tum drives the speaker.
Although not used in the circuit of Figure 11-17, a potentiometer may be con-
nected between (+)and·(-) inputs of the power amplifier to control its voltage
gain, which in turn controls the sound volume. The sound level produced depends
on the position of switch SW i, the wiper setting of potentiometer R2, and the value
of capacitor Cp, Therefore, sounds of varying intensities can be obtained by adjusting
SWi, R2, and c-
Recall that pulse and sawtooth waveforms can be generated by using the 555
timer, as shown in Section 10-3.4. Similarly, the VCO 556 persented in Section 8-18
also generates a squa~e wave and a triangular wave. These circuits may therefore be
used as the signal generator in the circuit of Figure 11-17, instead of an op-amp
signal generator.
For higher outputpower that is sound intensities, audio power amplifiers may
be used in the· bridge form shown in Figure 10-35. In fact, this corifiguration will
also require a higher wattage speaker.
Parts List
MC1458 dual op-amp

LM380 audio power amplifier
Three-position switch
!
Sec.11-7 Siren/Alarm: App!ication of the LM380 Power Amplifier 487
r-
t;
::,
]'
>
u
c:
.g"'
::,
u.
>
LO
>
...
LO
I ...
c
a,
M
...
c::
0
488
1-W speaker
Two io-in resistors
39-kn resistor
20-kn potentiometer
0.05-µF capacitor
:Two 0.1-µF capacitors
1000-µF capacitor
11-8 SUGGESTED IC PROJECTS

The IC systems presented above are a fair sample of practical applications of ICs
discussed in the previous chapters. ·These IC projects demonstrate th,lt a practical
and useful system does not have to be complex or expensive. In addition, the projects
illustrated here should give you enough experience and confidence so that you might
try your hand at a project of your own.
Although numerous practical IC systems can be formed with appropriate com-
binations of linear and/or digital ICs, block diagrams for suggested IC projects that
should prove to be simple, interesting, practical, yet challenging to you are shown in
Figure 11-18. These are:
(a) Rpm speed indicator

(b) Frequency meter
(c) Motor speed control using phase-locked-loop principles
(d) Digital light meter
(e) Digital voltemeter
(f) Shaeen-LEO sequencer or roulette wheel
(g) Sound generator
(h) Amplifier with digitally controlled gain
(i) Logic probe using window comparator
Motor/fan
\
I LED/LCD
\
,-, n ;-; n ,, ,,
'o Speed
sensor
6-digit
BCD
counters
Decoders/
drivers/
latches u ,-; ,-; 0 u ,-,
Display
Latch Reset
Time base
Figure 11-18 Block diagrams for IC projects. (a) RPM speed indicator.
Sec. 1.1 -8 SuggestedIC Projects 489

LED/LCD
display
Square wave
. Switch 6-digit Decoders/ nnnnnn
I?
''
BCD
counters
drivers/
latches oooooo
Schmitt
trigger_
L R
Timebnl
Sine wave
(b) Frequency meter.
Motor
.nn.. Phase Filter/power
Oscillator ----i .detector amplifier
I
I
Speed _____ .)
I
sensor
(c) Motor speed control using phase-locked loop principles.
3-digit Decoders/
Photocell
IN V/F.
BCD
converter converter drivers/
counters latches
....
nnn
LJI II I
LED display
(d) Digital light meter.
Decoders/
Attenuator 3~ -digit
network drivers/latches
Input AID converter (optional)
voltage .__ __,
I I I In
uuu
LED display
(e) Digital voltmeter.
490
\4-bit
One-of-16
Oscillator
decoder 16
(VCO) counters LEDs
(74154)
(0 Sixteen LED sequencer or roulette wheel.
4-bit D/A Power

Oscillator
counten converter amplifier
(g) Sound generator.
Input:!:
Op-amp t--- .... -~ Output
Digitally
selectable
resistors
(h) Amplifierwith digitally controlled gain,
Upper
th reshold
High ..... /
Input Window Go ::/
Lower
comparator
Low :. ./
tht:eshold -
(i) Logic probe using window comparator. "
491
Appendix A
492
RESISTANCE" CHART (10 0 to 22 M0)0
Resistance Resistance Resistance Resistance

(0) · (kO) (kQ) (MO)
• 10 • 1.0 -ioo • 1.0

11 1.1 110 ·~rl
• 12 • 1.2 •120 • 1.2
13 1.3 130 1.3
• 15 • 1.51 -iso • 1.5
16 1.6 160 1.6
• 18 • 1.8 *180 • 1.8
20 2.0 200 2.0
• 22 • 2.2 •220 • 2.2
24 2.4. 240 2.4
• 27 • 2.7 •210 .• 2.7
30 3.0 300 3.0
• 33 .• 3.3 *330 • 3.3
36 3.6 360 3.6
• 39 • 3.9. •390 • 3.9
43 4.3 430 4.3
• 47 • 4.7 *470 • 4.7
51 5.1 510 5.1
• 56 • 5.6 *560 • 5.6
62 6.2 620 6.2
• 68 • 6.8 *680 • 6.8
15 1.S 750 1.5
• 82 • 8.2 *820 • 8.2
\ 91 9.1. 910 9_.1
•100 •10.0· •10
110 11 ~ 11
•120 •12 •12
130 13 13
-iso •ts •1s
160 16 16
*180 •ts *18
200 20 20
•220 •22 •22
240 24
•210 "27
300 30
*330 *33
360 36
•390 •39
430 43
*470 •47
510 Sl
*560 •s6
620 62
*680 *68
750 · 1S
*820 *82
~10 91
-"I'olerancc o( ±10% available.only in values with•; ±S% available for all.

483
I
Appendix B
:-·
CAPACITA~CE CHART (1 pf to 1000 µF)•

I
Capacitance Capacitance Capacitance Capacitance \ Capacitance Capacitance
(pF) (pF) (µF) (µF) (µF) (µF)
1 47 0.001 0.025 0.82 300

1.2 so 0.0012 0.027 1.0 400
LS 56 0.0015 0.03 2 500
1.8 68 0.0018 0.033 3 600
2.2 75 0.002 0.035 4 750
2.7 82 0.0022 0.039 s 800
3.0 100 0.0025 0.04 6 900
3.3 120 0.0027 0.047 8 1000
3.9 150 0.003 0.05 10
4.7 180 0.0033 0.056 12
5.0 200 0.0039 0.06 15
5.6 220 0.004 0.068 16
6.8 270 0.0047 0.075 20
8.2 300 0.005 0.082 2S
10 330 0.0056 0.1 30
12 390 0.006 0.12 40
15 430 0.0068 0.15 so
18 470 0.0075 0.18 60
20 soo 0.008 0.22 75
22 510 0.0082 0.25 80
25 560 0.01 0.27 85
27 620 0.012 0.33 100
30 680 0.015 0.39 150
33 750 0.018 0.47 160
39 820 0.02 0.56 200
910 0.022 0.68 2SO
-The standard WVDC ratings for the capacitors are: 1 V, 3 v, 6 V,.10 V, 12 V, 16 V, 20 V, 25 V,

SO v, 60 v, 15 v, 90 v, 100 v, 150 v, 175 v. 200 v, 2SO v, 300 v, 350 v, 400 v, 450 v, 47' v,
SOO v, 525 v, sso v, 600 v, 1000 v.
494
_____ ... ...,_ . . .------··-..·--·--"- .....--·-·-·---~-·--·- ..-··-------
•• 't_,
Appendix C I
Answers to Selected Problems
Chapter 1 12. A0 = 15.6

R1 = 1 Mn
2. (a) ls1 = h.2 = 1.19 mA 14. Q1, Q2, Q3, Q_.; CA3086
VB1 = VB2 B1 + B2
= 0 V (assuming R2 =.4.6k!l
are connected to ground) Re= 1 kn
Vs1 = Vs2 = -0.715 V 16. hJ = 0.988'mA
.I (b)
Vc1 = Vc2 = 6.79 V
Ad= 64.26
18. (a) lco1 = lco2 = ·1.15 mA
VcEQI = VcEQ2 = 5.31 V
(c) R11 = R12 = 4.2 k!l (b) Ad = 216.2
4. (a) ls1 = ls2 = 1.19 mA (c) R1 = 4.35 xn
VB1 = VB2 = 0 V (assuming B1 and B2 (d) V0 max = 20 V
are connected to ground) 20. (a) IE1 = ls2 = 0.988 mA
Vs1 = Vs2 = -0.715 V JE3 = 1.95 mA
Vc1 = Vc2 = 3.34 V Is« = les = 0.975 mA
(b) Ad= 266.56 . les = ls1 = 9.75 µA
(c) R11 = R12 = 4.2 k!l VB1 = VB2 = 0 V (assuming B1 and B2
6. (a) IE1 = IE2 = 1.19 mA are connected to ground)
V Bl= VB2.,,; 0 V (assuming B1 and B2 VE1 = Vs2 = -0.715 V
are connected to ground) Vc1 = Vc2 = VB5 = VB7 = 7.33 V
VEI = VE2 = -0.715 v VE, ""." Vs6 = Vc3 = 5.9 V
Vc1 =.Vc2 = 3.34 V Ve•= Vc5 = 10 V
(b) Ad = 133.28 Vc6 = Vc1 = 8.25 V
(c) R11 ;= R,2 = 4.2 k!l VBJ = -5 V, and Vs3 = -5.715 V
8. (a) v0 = 385.5 mV pp (b) AdT = 1865.2
(b) V0 max= 12.85 V pp (c) t10 max = 3.5 V pp
10. (a) v0 = 40.2 mV PP 22. (a) ls3 = 1£5 = 2.1 i' mA
(b) t10 max = 12.53 V PP. /El = /£2 = /£6 = fs1 = 1.055 mA
496
\
Vsi \= Vs2 = 0 V with Bi and B2 con- 4. V0,..., -14 V
nected to ground. 6. 'IJ0 = 3 V
VE1 = VE:1. = Vc3 = -0.715 V
Vc1 = Vc2 = Vs6 = Vs, = 4.04 V
VB6 = VE, = Vcs = 3.325 V
Chapter 4
Vc6 = Ve, = 5.52 V
VE3 = VEs = -9V
(b) AdT = 6,932.2 2. (a) AF = 10.99
(c) V max = 4.39 V pp
0
(b) AF= 11
24. (a) IE1 = IE2 = 0.368 mA (c) Results in a and bare the same because
l1n = IE4 = 3.8 mA AB»l.
·1~,-=-0.736 mA 4. AF= 10.99
R,F = (1.2)(1012) Q
Vs1 = Vs2 = VcM = 3.5 V
VB1 = VE2 = Vcs = 2.785 V RaF = (1.8)(10-3) n
Vc1 = Vc2 = V93 = V84 = 8.32 V fy = 54.55 KHz
Vss = 2.26 V VaaT = +0.358 mV or -0.358 mV
6. V0 = 1.1 V pp
VEs = 1.545 V
Vc3 = Vc4 = 12V 8. (a) AF = -9.99
VB3 = VE4 = 7.61 v (b) AF= -10
(b) AdT = 143.63 (c) Results in a and bare the same because
(c) Va max,..., 7.36 V pp (unbalanced output AB» 1.
riding on 7.61 V de.) 10. Ap = -4.7
26. Di, D2, Qs, Q6: CA3086 transistor array RIP,..., 1 ill
R2 = 5.6 ill RaF = 0. 705 m!2
RE= 680k!l IF·= 127.66 kHz
R = 4.18 ill (5 ill pot) VaaT = +152.8 µV or. -152.8 µV
28. Q6, Q,, Q,: CA3086 transistor array 12. (a) v0 = -4.7 V pp
R2 = 5.6 ill 14. (a) AD = -39
R = 3.51 ill (5 ill pot) (b) RtP = 4 ill
30. (a) IB1 = IB2 = 1.02 mA 16. (a) AD = -44
Vsi = 2.87 V, V82 = 7.01 Y· (b) AD= -66
VEI = 2.24 V
18. (a) AD = 14
VE2 = Vc1 = 6.38 V (b) R,F, = R,F, = 342.86 on
Vc2 = 10.16 V (c) RaF = 5.25 m!2
(b) A.,= -73.44 (d) fp = 71.43 kHz
(c) A1 = 104.86
(d) R1 = 2.57 ill
Chapter 5
Chapter 2
;
2. Vaa = +240 mV or -240 mV
4. Va ,..., 1 V pp .
2. (a) Adr = 4,812.8 (exact) 6. V0, .. = 7 mV
Adr = 5,013.4 (ideal) 18. Vaar = 71 mV
(b) R, = 2.79 M!l VaaT = 68 mV
(c) v0 max = 16.96 V pp 10. (a) E., = ±30.6 mV
Va= 101 mV ± 30.6 mV
(b) E., = ±30.6 mV
Chapter 3 Va = 1.01 V ±· 30.6 mV
12. (a) E., = ±51.44 mV
2. A,m = 1 Va = 1.66 V peak ± 51.44 mV
496 App. C Answers to Selected Problems

14. (a) AV00 = ±60 .. 6 mV Cbapter 8
(b) V0 = -1.01 V peak± 60.6 mV
16. AV00 = 7.61 µV r.m.s. 2. R = 5.3 kO (10 ill pot)
18. AV00 = 12.51.4 mV C = o.or µF
20. (a) Vo = 470 mV sinewave at 1 kHz · Use a voltage follower.
(b) Vno = 4.7 µV at 60 Hz 4. R = 13.25 k!l (use 20 k!l pot)
22. v.m = 10.64 V r.m.s. C = 0.01 µF
R1 = 4.7 kO and Rp = 2.7 ill
I 8. For fH = 2 kHz: R' = 7.95 ill (use 10 kO
pot)
Chapter 6
C' = O.ot µF
For fL=400Hz: R,...,39k0 and. C=
2. BW,..., 80kHz
0.01 µF
4. BW,..., 5kHz
For APT = 4: R1 = R'1 = Rp = R'i, = 10
104
kO
6. AoL = ( . f )( f )( .. f )
l + 10.7 M l + J 3M l + J 18 M lO. For !L = 2 kHz: R = 7.95 kO (use 10 kO
8. UBW = 72 MHz pot), C = O.ot µF
10. (a) -97.46° . For !H = 400 Hz: R'- 39 k!l, and C' =
(b) -260.92° 0.01 µF
12. C1 = 10 pF, R1 = 0 0, C2 = 3 pF For APT = 2: · R, = Rp = R'1 = R'i, = R2
14. fmax = 79.5 MHz = R3 = R• = 10 ill
16. Vtn max = 0.8 V pp 12. "' =;= -126.83°
. 18. SR= 36.01 V/µS To obtain positive phase shift interchange
20. V0 max = 3.02 V resistor R and capacitor C.
14. Rs = 7.95 kO (use 10 ill pot)
C, = O.ot µF
R1 = 10 ill
Chapter 7 Rp = 20ill
16. lo = 1 kHz .
2. V0 = 5.7V 18 .. (a) Va = 4.94 V pp
4. (a) BW = 99.84 kHz (b) lo = 1.18 kHz
(b) V0 max = 15 V 20. · lo changes from 9.8 kHz to 2.18 kHz if R1
(c) '!/,, = 7.5 V de - 2 V peak sinewave is varied from 4 ill to 18 kO.
· v0 = - 2 V peak sinewave
6. (a) Va= -1..14 V
(b) Scaling amplifier or weighted amplifier Chapter 9
8. RP= 2.4k!2
10. (a) Vab varies from --1 V to 4.09 V 2. (a) Vur = 30.8 mV
(b) Va varies from -2.61 V .to 10.68 V Vir = -30.8 mV
14. Vin= 11.34 mV (b) V...,. = 61.6 mV
16. Vtn,..., 0.52 V r.m.s, 4. The output voltage swings between -12 V
18. (a) 10 = 3.33 mA and +6.9 V
(b) Va = 10.1 V 6. Va= 700mV
20. Va = 316.4 mV Change s.; from 1 MO to 100 kO if
22. Va = 3.98 coswt - 3.98 Fi« is changed from 10 kHz to 100 kHz.
24. R1 = 7.9 ill (10 kO pot) 8/ (a) Size of each step = 0.84375 V
C1 = 0.01 µF (b) Va= -12.66 V
C» = 500 pF (c) The advantage of R/2R DAC is that it
RP= 159 ill (200 ill pot) requires only two sets of resistance
RoM = s.a sn values,
App. C Answers to Selected Problems 497

10. The output voltage is a negative going half C = 0.1 µF, and NE555 timer
wave rectified waveform' having a peak value 8. RA = 3.33 kQ (use 3.3 ill)
of -300mV. 10. RA = 3.6 ill (use 5 ill pot)
12. ve ......, 1 V Rs= 1.8 kQ \
C = 0.02 µF, and NE555 timer
12. 1N914 small signal diode
Chapter 10 2N404 PNP transistor
NE555 timer
2. .R2 = 6.32 ill (use 10 kQ pot) R = 516.2 Q (use 1 ~Q pot)
R3 ,,,. 124.2 kQ (use 200 ill pot) C= lµF
R4 = Rs = 5.03 kQ (use 5.1 kQ) C1 = 0.01 µF, and C3 = 10 µF
R6 = 1 ill 14. louT= 53.19 kHz
R7 = 9 kQ (use 10 k!l pot) IL= ± 21.28 kHz
R8 = 900 Q (use 820 Q) le=± 306.7 Hz
4. R2 = lOOkQ 16. R1 = 12 kQ
R3 = 1.46 k!l (use 1.5 ill) 18. R = 34.3 Q, and Vin :2: 8.2 V
R4 = Rs = 25.15 kO (use 50 ill pots) 20. n=3
6. RA = 909.09 ill (use 1 MO pot)
498 App. C Answers to Selected Problems

---~
'
Bibliography
Burr-Brown General Catalog. Tucson, Ariz.: Burr-Brown, 1979.

Datal-Intersil Data Acquisition Component Handbook. Mansfield, Mass.: Datel-Intersil,
Inc., 1980.
Fairchlld Linear Op-Amp Data Book. Mountain View, Calif.: Fairchild Camera and Instru-
ment Corporation, 1979.
Intersil Data Book. Cupertino, Calif.: Intersil' Inc., 1979.
Motorola Linear Integrated Circuit. Motor~la CMOS Data. Phoenix, Ariz.: Motorola
Semiconductor Products, 1979. :
National Linear Data Book. Santa Clara, Calrf.: National Semiconductor Corporation, 1978.
RCA Linear Integrated Circuits. Somerville, N.J.: RCA Solid State, 1978.
Signetics Analog Data Manual. Sunnyvale, Calif.: Signetics Corporation, 1979.
Teledyne Data Conversion Design Manual. Mountain View, Calif.: Teledyne Semiconductor,
"1980.
The TTL Data Book for Design Engineers. Texas Instruments, 1976.
BERLIN, H. M., The Design of Active Filters with Experiments. Derby, Conn.: E and L Instru-
ments, Inc., 1977.
BYLEu.v, J .. E., and M. VANDER Koor, LM380 Power Audio Amplifier. National Semiconduc-
tor Linear Applications, Vol. 1, 1976.
KAHN, M., The Versatile Op-Amp. New York: Holt, Rinehart and Winston, Inc., 1970.
MALVINO, A. P., Electronic Principles. New York:, McGraw'-Hill.Book Company, 1979.
Phase-Locked Loops. Benton Harbor, Mich.: Heathkit Continuing Education, 1980.
PRENsK.Y, S. D., Manual of Linear Integrated Circuits: Operational Amplifiers and Analog ]Cs.
Reston, Va.: Reston Publishing Company, Inc., 1974.
RUTKowsJC.I, G. B., Handbook of Integrated Circuit Operational Amplifier. Englewood Cliffs,
NJ.: Prentice-Hall, 1~1975.
489
-~---------------· ----·--·--··------·--·-·- .. _ .. , _
'
Index
~----------------------------------·------~----------------~--------------
A Bandwidth:
definition, 121
Absolute-value output circuit, 377-80 difference between transient response, slew rate
AC amplifiers, 234-40 and,224
with a single supply voltage, 238-40 of differential amplifiers with negative feed-
Active filters (see Filters) back, 14()-41
AC voltmeter, low-voltage, 259-60 with feedblflc, of voltage-shunt feedback
All-pass filters, 286,.307-8 amplifier, 121-22, 129-30
Amplifier-to-amplifier coupling (see Channel unity gain (see Gain-bandwidth product)
separation) BI-FET technology, 77
Analog circuits, 73 Binary-weighted resistors, digital-to-analog
Analog-to-digital (A/D) converters,-361, 367-70 converters with, 362-63
Analog weight scale, 254-55 · Bode plot, 206
Appliancetimers, 481-87 Bridge power audio amplifier, 432-33
Astable multivibrator, 555 timer as, 407-12 Butterworth filter, 286-97
Audio function generator, 460-66 first-order high-pass, 293-95
Audio power amplifiers, 429-35 first-order low-pass, 286-90
Average temperature coefficient of input offset second-order high-pass, 295-97
voltage (and current), 103 second-order low-pass, 290-93
Averaging amplifier:
inverting, 244
noninverting; 245 c
Cascaded differential amplifiers, 35-41
B with level translator circuit, 37-41
experiment, 57-60
Band-pass filters, 286, 299-304 Cascode amplifier (CE-CB configuration), 42-47
narrow, 302-4 AC analysis, 44-47
wide, 299-30? DC analysis, 43-44
Band-reject filters (band-stop or band-elimination experiment, 60-63
filters), 286, 304- 7 Cauer filters, 286
narrow, 305-7 CE-CB configuration (.see Cascode amplifier)
wide, ~04-5 Channel separation, I 04-5
501
Chebyshev filters, 286 channel separation, 104-5
Circuit stability, 217-18 common-mode rejection ratio, 100-101
Clampers, 370, 375- 77 differential input resistance, 99
Clippers, positive and negative, 370, 372 equivalent input noise voltage and current, 104
Closed-loop bandwidth (See Gain-bandwidth gain-bandwidth product, 103
product) input bias current, 99
Closed-loop frequency response, 216-17 input capacitance, 99
Closed-loop voltage gain: input offset current, 98-99
of voltage-series feedback amplifier, 117-18 input offset voltage, 98
of voltage-shunt feedback amplifier, 126 input voltage range, 100
Common-mode configuration, 192-93 large-signal voltage gain, 101
Common-mode rejection ratio (CMRR), long-term input offset voltage (and current)
100-101, 193-95 stability, I o·~-4
of dual-input, balanced-output differential offset voltage adjustment range, 99.,.\00
ampltfter, 10-11 output resistance, 102
Common-mode voltage range (CMVR), 189-90 output short-circuit current, 102
Comparators (phase detectors), 336-50 output voltage swing, 101-2
basic, 336-38 power consumption; 102
characteristics, 343 slew rate, 103, 218
high-speed and precision-type, 347-48 supply current, 102
inverting, 338 supply voltage rejection ratio, 101
limitations of op-amps as, 343 transient response, 100.-3
noninverting, 336-38 types of information found on, 97-98
in phase-locked loop, 413-17 Datel VI-7660 voltage inverter, 440-44
as Schmitt trigger, 340-42 DC amplifiers, 234
as voltage limiters, 344-46 DC voltmeter, low-voltage, 258-259
as window detector, 348-50 , Degenerative feedback (see Negative feedback)
as zero-crossing detector, 338-40 Delay equalizers (see All-pass filt!1_rs)
Compensating networks: Differential amplifiers, 1-41
frequency response and, 206-7 cascaded, 35-41
offset-voltage, 155-64 with level translator, 37-41, 57-60
Constant current bias, differential amplifier with, circuit configuration, 3-4
25-29. , with constant current bias, 25-29
experiment. 54-5i· experiment, 54-57
Converters: with current mirror, 29-35
analog-to-digital (A/ D), 361, 367-70 dual-input, balanced-output, 4-11
current-to-voltage. (see Current-to-voltage AC analysis, 5-9
converter) common-mode rejection ratio, 10-11
digital-to-analog (D / A). (see Digital-to-analog DC analysis, 4-5
(D / A) converters) inverting and noninverting inputs, 9-10
frequency-to-voltage (F /V), 357-61 _dual-input, unbalanced-output, J 1-13
voltage-to-current. (see Voltage-to-current with FETs, 21
converter) instrumentation amplifiers, 249-55
voltage-to-frequency. (see Voltage-to- analog weight scale, 254-55
frequency converter) flow meter and thermal conductivity meter,
Corner frequency, 211 253-54
Current drift (see Average temperature coefficient light-intensity meter, 253
of input offset voltage (and current)] resistive transducers, 249-52
Current gain of·CE-CB configuration, 45 temperature controller, 253
Current.mirror, 29-35 temperature indicator, 252-53
Current-to-voltage converter, 264-66 with negative feedback, 133-41
detecting current through photosensitive with one op-amp, 133-35
devices and, 265-66 output resistance and bandwidth, 140-41
in voltage-shunt feedback amplifier, 130-31 with three op-amps, 137-40
with two op-amps, 135-37
open-loop, 108
D single-input, balanced-output, 14-17
single-input, unbalanced-output, 17-21
as subtractor or summing amplifiers, 246-48
Data sheets for op-amps, 87-105 with swamping resistors, 21-25
average temperature coefficient of input offset Differential input and differential output
voltage (and current), 103 amplifiers, 255-57
502 Index
Diff~r~ntial input resistance, 99 band-reject (band-stop or band-elimination)
in ipual-input, balanced-output differential (see Band-reject filters)
i amplifier, 8-9 Butterworth (see Butterworth filters)
in d1Ji3l-input, unbalanced-output differential higher-order, 297-99
l amplifier, 13 high-pass (see High-pass filters)
in single-input, balanced-output differential low-pass (see Low-pass filters)
amplifier, 17 passive, 284
in single-input, unbalanced-output differential universal, 308, 391-400
amplifier, 19, 21 555 timer, 401-12
Differentiator (differentiation amplifier), 271-74 as appliance timer, 481-87
Digital DC motor speed control, 475-81 as an astable multivibrator, 407-12
1
Digital ICs, 73 in LED temperature indicator, 466-75
develipment,77-78 as a monostable multivibrator, 401-6
Digital- -analog circuits (DACs), 264 Flat-flat filter (see Butterworth filter)
with c rrent-to-voltage converter, 264-65 Flat pack IC package, 78, 80
Oigital-t -analog (D/A) converters, 361-67 Flow meter, 253
-- .with binary-weighted resistors, 362-63 Free-running multivibrator (see Astable rnul-
digital oc motor speed control using, 475-81 tivibrator; Monostable multivibrator)
monolithic/hybrid, 365-61 . Free-running ramp generator, astable mul-
with R and 2R resistors, 363-65 tivibrator as, 411
Diode match finder, 261-62 Frequency:
DIP (dual-in-line package), 79 corner (-3dB), 211
Dual-input, balanced-output differential open-loop voltage gain as a function of, 210-16
amplifier, 4-11 Frequency divider, monostable multivibrator as,
AC analysis, 5-9 406-7
common-mode rejection ratio (CMRA), 10-11 Frequency multiplier, phase-locked loop as, 423
DC analysis, 4-5 Frequency response, 205-32
inverting and noninverting inputs, 9-10 circuit stability and, 217-18
Dual-input, unbalanced-output differential closed-loop, 216-17
amplifier, 11-13 compensating networks and, 206- 7
Duty cycle, 409 high-frequency op-amp equivalent circuit and,
209-10
of internally compensated op-amps, 208
E of noncompensated op-amps, 208
of a peaking amplifier, 240-42
Equivalent circuit(s): slew rate and, 218-24
high-frequency, 209-10 Frequency response plot, 205-6
of-op-amps, 65-72, 106-7 Frequency scaling in low-pass filters, 288-90
of 741 op-amp, 69-72 Frequency shift keying (FSK) demodulator,
Equivalent input noise voltage and current, 104
phase-locked loop as, 423-27
Error voltage, 177-81 Frequency stability of oscillators, 310
Frequency-to-voltage (F/V) converters, 357-61
F digital DC motor speed control using, 4?5-81
Fairchild:
device identification method, 82 G
µ A709 op-amp, 76 ·
741 op-amp (see 741 op-amp) Gain-bandwidth product (unity gain-bandwidth),
Feedback, 114 (see also Negative feedback; 103, 121, 212
Positive feedback) General-purpose op-amps, 73
Feedback amplifier(s):
block diagram representation of, 114-15
voltage-series (see Voltage-series feedback H
amplifier)
voltage-shunt (see .Voltage-shunt feedback Hall effect transducer, 477
amplifier) Higher-order filters, 297-99
Feedforward compensation, 218 High-frequency op-amp equivalent circuit,
FETs, differential amplifiers with, 21 209-10
Filters, 283-308 High-pass filters, 286
all-pass, 286, 307-8 first-order Butterworth, 293-95
analog or digital, 283.-84· . second-order Butterworth, 295-97
band-pass (see Band-pass filters) Hybrid ICs, 74
Index 503
LED temperature indicator, 466-75
Level translator, cascaded differential amplifier
Ideal voltage transfercurve, 107 with, 37-41
Input bias current, 99, 164-70 Light-emitting diode tester, 262
Input capacitance, 99 Light-intensity meter, 253, 266
Input offset current, 98-99, 170-72 Limiters, voltage, 343-46
changes (drifts) with time, 186-87 Linear ICs, 73
Input offset voltage, 98, 153-64 development, '76-78
changes (drifts) with time, 186-87 manufacturers' designations, 74-76
Input resistance: ·· monolithic, 73-74
of cascode amplifier, 45-47 LM380 power audio amplifier, 429-35
differential (see Differential input resistance) as siren/alarm, 487-89
~ential amplifiers with negative feed- Long-term-input offsei voltage (and current)
back, 134-37, 139-40 stability, 103-4
with feedback: , Low-pass filters, 284-93
of voltage-series feedback amplifier, 119-20 first-order Butterworth, 286-90
of voltage-shuntfeedback amplifier, 128-29 in phase-locked, loop, ·417
Input voltage range, 100 second-order Butterworth, 290-93
Instrumentatiorr'amplifiers, 248-55 LSI (large-scale integration),-18 .
with transducer bridge, 249-55
analog weight scale, 254-55
flow meter and thermal conductivity __ meter,
253-54 M
light-intensity meter,-253
temperature controller, 253 Medium-scale integration (MSI), 78
temperature indicator, 252-53 Metal can IC package, 78-80
Integrated circuits (ICs), 72-84 (see also -3d8 frequency, 211
Operational amplifiers) Monolithic ICs, 73-74
development, 76-78 Monostable multivibrators, 401-7
device identification; 82 Motorola op-amp MC 1435, equivalent circuit,
digital, 73 66-69
hybrid, 74 Motorola, ordering information for-mat for ICs,
linear (see Linear ICs) 82
manufacturer's designations, 74-76 MSI (medium-scale integration), 78
monolithic, 73-74 Multiple-feedback filter, 302-4
ordering information, 81-82 Multivibrators (see Astable multivibrators;
package types, 78-80 Monostable multivibrators)
pin designations, 80
power supplies, 83
SSI, MSI, LSI, and VLSI packages, 78
temperature ranges, 80-81 N
types, 73-74 .II
Integrator (integration amplifier), 268-69
National Semiconductor:
Intercom system, 433-35
LM380 power audio amplifier, 429-35
Internally compensated op-amps, frequency
response, 208 ordering information format for ICs, 82
Inverter of voltage-shunt feedback amplifier, Negative clampers, 375
131-32 Negative clipper, 372
Inverting amplifiers: Negative feedback, op-amps with, I 14-52(seealso
open-loop, 108-9 Differential amplifiers-with negative
feedback; Feedback amplifiers)
as summing, scaling, and averaging amplifiers,
Noise, 190-92
242-44
Noncompensated op-amps, frequency response
Inverting comparator, 338
I of, 208
lnvertingtjnputs of dual-input, balanced-output
Noninverting amplifier:
differential amplifiers, 9-10
Inverting input terminal at virtual ground in with feedback (closed-loop) (see Voltage-series
feedback amplifiers)
voltage-shunt feedback amplifier, 127-28
open-loop, 109-11
as summing or averaging amplifiers, 244-46
L Noninverting comparator, 336-38
Noninverting inputs of dual-input, balanced-
Large-scale integration (LSI), 78 output differential amplifier, 9-10
Large-signal voltage gain, 101 Notch filter, 305-7
604 Index
0 offset-voltage compensating network design,
155-6~
thermal drift and, 174-81
error voltage, 177-!i I
Offset voltage (see Input offset voltage; Output
total, 172-74
offset voltage) .
variation in power supply voltages and, 182-86
Offset vorfage adjustment range, 99-100
Output resistance, 102
Offset-voltage compensating network design,
of differential amplifiers with negative feed-
155-64 back, 140-41
!//noise, 190
One-shot multivibrator (see Monostable mul- in dual-input, balanced-output differential
amplifier, 9
tivibrator)
in dual-input, unbalanced-output differential
Open-loop gain, 108
amplifier, 13
Open-loop op-amp configuration, 107-14
with feedback:
Open-loop voltage gain, frequency and, 210-16
of voltage-series feedback amplifier, 120-21
Operational amplifier(s): of voltage-shunt feedback amplifier, 129
block diagram of a typical, 65 in single-input, balanced-output differential.
equivalent circuits, 65-72, 106-7 amplifier, 17
first-generation, 76 in single-input, unbalanced-output differential
general linear applications, 233-82 amplifier, 21
AC amplifiers, 2~4-40 Output short-circuit current." 102
current-to-voltage converter, 264-66 Output voltage swing, 101-2, 123
DC amplifiers, 234 Overshoot, I 02
differential input and differential output
amplifier, 25$-57
differentiator, 271-74 p
instrumentation amplifiers, 248-~5 .
integrator, 268-69 Peak clamper, 375
peaking amplifiers, 240-42 Peak detectors, 380-81
summing, scaling, and averaging amplifiers, Peaking amplifiers, 240-42
242-44 Phase correctors (see All-pass filters)
very high input impedance circuit, 266-67 Phase detectors (see Comparators)
voltage-to-current converter with floating Phase-locked loops, 412-27
load, 257-62 comparator in, 413-17
voltage-to-current converter with grounded as frequency multiplier, 423
load, 262-63 as frequency shift keying (FSK) demodulator,
general-purpose, 73, 234 423-27
ideal, 105-6 low-pass filter in, 417
integrated circuits (see Integrated circuits) monolithic, 418-23
with negative feedback, 114-52 (see also operating principles, 413-17 -;
Differential amplifiers-with negative voltage-controlled oscillator in, 4,~7
feedback) Phase shift oscillator, 310-12
open-loop, 107-14 Photocells, 265-66
schematic symbol, 72 Photoconductive cells in instrumentation
second-generation,76-77 . amplifiers, 252 .
special-purpose, 73 Photosensitive devices, detecting current through,
Oscillator(s), 308-25 265-66.
frequency stability, 310 Photovoltaic cells, 265
phase shift, 310-12 Positive clampers, 375-76
principles, 309-10 Positive clipper, 370-72
quadrature; 3_13-15 Positive feedback, 114
as sawtooth-wave generator, 321-22 Power amplifiers, 427-35
as square-wave generator, 315-17 monolithic, 429-35
astable multivibrator, 410-11 with power boosters, 427-29
-;
•j. as triangular-wave generator, 317-21 siren/alarm as application, 487-89
types, "310 P.ower consumption, 102
voltage-controlled, 322-25 Power supplies:
on phase-locked loop, 417 for ICs, 83
Wien bridge, 312-13 voltage regulators as, 457-60
Output offset voltage, 153-74 Power supply rejection ratio (PSRR) (see Supply
input bias current and, 164-70 voltage rejection .ratio)
input offset current and, 170- 72 Power supply sensitivity (PSS) (see Supply voltage
input offset voltage and, 153-64 rejection ratio)
Index 605
Power supply voltages, output offset voltage and Summing amplifier:
variation in, 182~86 differential amplifier as, 247-48
Pulse stretcher, monostable multivibrator as, 407 inverting, 243
noninverting, 245-46
Q
Supply current, 102
Supply voltage rejection ratio, IOI
Swamping resistors, differential amplifiers with,
Quadrature oscillator, 313-15
21-25
Switching regulators, 436, 439
R
Rectifiers, small-signal half-wave, 373-75 T

B.esistive transducers in instrumentation
amplifiers, 249-52 Temperature (see Thermal drift)
Restorers. (see Clampers) Temperature controller, 253
Rise time, 102 Temperature indicator, 252-53
Temperature ranges of ICs, 80-81
Temperature-sensitive parameters, 187-88
s Thermal conductivity meter, 253-54
Thermal drift, 174-81
Sample-and-hold circuit, 381-83 Thermal noise, 190
Sawtooth-wave generator, 321-22 Thermistors, 251
. Scaling (or weighted) amplifier: Total output offset voltage, 172-74 (see also Out-
differential amplifier as, 246 put offset voltage) ·
inverting, 243 with feedback, 122-23
Schmitt trigger, 340-42 of voltage-shunt feedback amplifier, 130
Schottky noise, 190 Transducer:
SE/NE 555 timer (see 555 timer) Hall effect, 477
741 op-amp, 76-77 in instrumentation amplifiers, 248-52
data sheets (see Data sheets for op-amps) Transient response, 102-3
. equivalent circuit, 69-72 difference between bandwidth, slew rate, and,
manufacturers' designations, 74-76 224
ordering information, 82 Transistor pack, 78-79
Shifter stage (see Level translator) Triangular-wave generator, 317-21
Sine wave-to-square wave converter (zero-
crossing detector), 338-40
Single-input, balanced-output differential u
amplifier, 14-17
Single-input, unbalanced-output differential Unity gain bandwidth (see Gain-bandwidth
amplifier, 17-21 product)
Siren/alarm, 487-88 Universal active filters, 308, 391-400
Slew rate (SR);" 103, 218-24
causes, 220-21
in data sheets, 218 v
difference between bandwidth, transient
response, and, 224 Very high input impedance circuit, 266-67
effect in applications, 222-24 Very large scale integration (VLSI), 78
equation, 221-22 Vl-7660 voltage inverter, 440'-44
Small-scale integration (SSI), 78 Voltage-controlled oscillator, 322-25 (see also
Small-signal bandwidth (see Gain-bandwidth Voltage-to-frequency converter)
product) in phase-locked loop, 417
Small-signal half-wave rectifiers, 37':J-75 Voltage follower, 123-25
Speciai-purpose op-amps, 73 Voltage gain:
Square-wave generator, 315-17
astable rnultivibrator as, 410-11
of cascode amplifier, 44-45
closed-loop (see Closed-loop voltage gain) ,·..
SS! (small-scale integration), 78
State-variable filters (see Universal filters)
of differential amplifiers with negative feed-
back, 133-39
.r
Steady-state response, 102 in dual-input, balanced-output differential
Strain gages, 252 amplifier, 6-8
Subtractor, differential amplifier as, 246 in dual-input, unbalanced-output differential
Successive-approximation analog-to-digital amplifier, 12-13
converter, 367-68 large-signal, IOI
506 Index
open-loop, 210-16 total output offset voltage with feedback, 130
in single-input, balanced-output differential Voltage-to-current converter (see also Voltage-
amplifier, 14-17 controlled oscillator)
in single-input, unbalanced-output differential with floating load, 257-62
amplifier, 18-19 diode match finder, 261-62
Voltage inverters, 440-44 light-emitting diode tester, 262
Voltage-level detector (see Comparator) low-voltage AC voltmeter, 259-60
Voltage limiters, 343-46 low-voltage DC voltmeter, 258-59
Voltage references, 439-40 zener diode tester, 262
Voltage regulators, 435-44 with grounded load, 262-63
positive, .with seven voltage options, 436-39 Voltage-to-frequency converters 350-57
as power supply, 457-60 I adj~stment/calibration procedure, 356
switching, 436, 439 design procedure, 354-56
. voltage references, 439-40 as LED temperature indicator, 466-75
'l(Qltage-sensitiveparameters, 188-90 single-supply operation, 356-57
Voltage-series feedback amplifiers, 116-25 Voltage transfer curve, ideal, 107
.bandwidth with feedback, 121-22 Voltmeter:
closed-loop voltage gain, 117-18 ac, low-voltage, 259-60
difference input voltage ideally zero in, 118-19 de, low-voltage, 258-59
input resistance with feedback, 119-20
negative feedback, 116-17 _
· output resistance with feedback, 120-21 w
total output offset voltage with feedback,
122-2j
Weighted amplifier (see Scaling amplifier)
voltage follower, 123-25 Weight scale, analog, 2S4-55
Voltage-shunt feedback amplifiers, 125-33 Wien bridge oscillator, 312-13
bandwidth with feedback, 129-30 Window detector, 348-50
closed-loop voltage gain, 126-27
current-to-voltage converter in, 130-31
input resistance with feedback, 128-29
inverter, 131-32 z
inverting input terminal at virtual ground,
127-28 Zener diode tester, 262
output resistance with feedback, 129 Zero-crossing detector, 338-40
Index 607

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I

Missouri Institute of Technology

Prentice,Hall of India l?ir~® loma'ft®~

This Indian Reprint-Rs. 65.00

PRENTICE-HALL INTERNATIONAL, INC., Englewood Cliffs.

© 1983 by Prentice-Hall, lnc., Englewood Cliffs, N.J., U.S.A. All rights

This Eastern Economy Edition is the only authorised, complete and

Reprinted in India by special arrangement with Prentice-Hall, Inc.,

Printed by Jay Print Pack Private Limited, Mew Delhi-110015 and

1 DIFFERENTIAL A/VD CASCODE AMPLIFIERS 1

2 INTRODUCTION TO OPERATIONAL AMPLIFIERS 64 I'

3 1/t!TERPRETATION OF DATA SHEETS AND CHARACTERISTICS

3-6.3 The Noninverting Amplifier 109

4 AN OP-AMP WITH N.EGATIVE FEEDBACJ<

4-1 Introduction 113

THE PRACTICAL OP-AMP 153

5-1 Introduction 153

6-1 Introduction 205

8-1 Introduction 283

8-9 Band-Reject Filters 304

(!_j COMPARATORSAND CONVERTERS 336

9-1 Introduction 336

10 SPECIALIZED IC APPLICATIONS 391

10-1 Introduction 391

11-1 Introduction 456

APPENDIX C ANSWERS TO SELECTED PROBLEMS 496

-·---·-------·-· ...- . ..... --·· ·-··--·· -··-----------·- .. ....-.... ,

Diflerential and Cascode Amplifiers

Flpre 1-1 Two identical emitter-

Flpre 1-2 Dual-input, balanced-

2 Differential and Cascode Amplifiers Chap. 1

1-3 DIFFERENTIAL AMPLIFIER CIRCUIT CONFIGURATIONS

The four differential amplifier configurations are the following:

1. Dual-input, balanced-output differential amplifier

1. Because of the nature of r-parameters, ac analysis of differential amplifiers with

Sec. 1-3 Differential Amplifier Circuit Configurations 3

1-4 DUAL-INPUT, BALANCED-OUTPUT DIFFERENTIAL

The circuit shown in Figure 1-2 is a dual-input, balanced-output differential amplifier.

4 Differentialand CascodeAmplifiers Chap.1

Figure 1-3 De equivalent circuit of

Notice that the emitter current in transistors Q1 and Q2 is independent of collector

we can obtain the voltage at the collector Ve, as follows:

Sec. 1-4 Dual-Input, Balanced-Output Differential Amplifier "5

1-4.2(a) Voltage gain. Before we proceed in deriving the expression for

Figure 1-4 Dual-input, balanced-output differential amplifier. (a) Ac equivalent

6 Differential and Cascode Amplifiers Chatr.-1

Sec. 1-4 Dual-Input, Balanced-OutputDifferentialAmplifier 7

Notice that the voltage-gain equation of the differential amplifier is independent of

i,.f Pac .,,,aO

8 Differentialand CascodeAmplifiers Chap. 1

1-4.2( c) Output resistance. Output resistance is defined as the equivalent

1-4.3 lnflerting and Noninflerting Inputs

noninverting input because a positive voltage v1 I acting alone produces a positive

Sec. 1-4 Dual-Input, Balanced-Output DifferentialAmplifier 9

1-4.4 Common-Mode Rejection Ratio

An important characteristic of the dual-input, balanced-output differential amplifier

Figure 1-S Differential amplifier in common-mode configuration.

10 Differentialand CascodeAmplifiers Chap. 1

1-S DUAL-INPUT, UNBALANCED-OUTPUT DIFFERENT/AL

The de analysis procedure for the dual-input, unbalanced-output differential amplifier