v4.

Cyclic Redundancy Code Generator Macro

Fe a t ur es Fu n ct i o n al D e sc r i p t i on
The highlights of the Cyclic Redundancy Codes (CRC) Many designers use the CRC as an alternative to parity and
Generator are as follow: checksum calculation for checking (and sometimes
correcting) data transmission errors. A 16-bit CRC detects
• CRC Calculation all single and double-burst errors and ensures detection of
• Multiple Algorithm Support 99.998% of all possible errors. This level of error protection
– CRC8 ATM (HEC) is considered sufficient for data transmission blocks of 4
kilobytes or less. For larger transmissions, a 32-bit CRC is
– CRC10 ATM (OAM) often employed.
– CANbus Gigabit Ethernet, ATM, and other higher-speed protocols
– X25 (SDLC, HDLC, CRC-CCITT) require the use of CRC, although the exact CRC polynomial
– CRC16 changes depend upon the transmission protocol (Figure 1).
In ATM, an 8-bit CRC is used for the header error check,
– CRC16 inverted
and in addition (optional) CRC error checking is often done
– CRC32 for data. For larger transmissions, a 32-bit CRC is often
– User defined polynomial used.
• A Win32 console application that generates VHDL code The CRC method treats the data frame as a large binary
number. This number is then divided (at the generator end)
• Performance (CRC32, 54SXA –2)
by a fixed binary number (the generator polynomial) and
– Serial → 200 MHz the resulting CRC value is appended to the end of the data
– 32-bit Parallel, 8-bit Data—130 MHz frame. The receiver then repeats the calculation and
compares its CRC value with the generated CRC value. The
The CRC Generator application generates VHDL code
classic serial implementation method uses a shift register
specifically for use in the SX-A, ProASIC, and ProASICPLUS
with XOR gates and feedback taps as shown in Figure 1 for
families. The RTL VHDL code generated is simply designed
the X25 polynomial (G(x)=x16+x12+x5=1).
to take advantage of the SX-A silicon features. This is
necessary to meet the timing requirement of greater than A serial CRC implementation is suitable up to about 100
125 MHz—oriented toward telecommunications Mb/s using FPGAs. The blocks described here can be used
applications. for higher rates including Gigabit Ethernet (1 Gb/sec serial
rate stepped down to 125 MHz and ATM (620 Mb/sec serial
rate stepped down to 77.5 MHz).

CCITT Generator Polynomial

16 12 5
G(x) = x + x + x + 1

D Q D Q D Q D Q CRC
Data D Q D Q D Q D Q D Q D Q D Q
out
in D Q D Q D Q D Q D Q

Figure 1 • Serial CRC Calculation

J an u a r y 2 0 0 2 1
© 2002 Actel Corporation
 C y c lic R e d u n d a n c y C o d e Ge n e r a t o r M a c r o

The CRC Shift Sequence

The initial contents of the feedback shift register are shown contents. We continue to shift until eight shifts have been
in the top row; namely, C15 through C0. After the first data made, as shown in the diagram. The new shift register
bit D0 is shifted into the shift register, the new contents of contents are now functions of both the original contents and
the shift register are functions of D0 and the previous the 8 data bits after 8 clocks, as shown in Figure 2.

Initial: Bit shifted in 0: Bit shifted in 1: Bit shifted in 7:

15: C15 15: C14 15: C13 15: C7 ^ D4 ^ C11 ^ D0 ^ C15
14: C14 14: C13 14: C12 14: C6 ^ D5 ^ C10 ^ D1 ^ C14
13: C13 13: C12 13: C11 ^ D0 ^ C15 13: C5 ^ D6 ^ C9 ^ D2 ^ C13
12: C12 12: C11 ^ D0 ^ C15 12: C10 ^ D1 ^ C14 12: C4 ^ D0 ^ C15 ^ D7 ^ C8 ^ D3 ^ C12
11: C11 11: C10 11: C9 11: C3 ^ D1 ^ C14
10: C10 10: C9 10: C8 10: C2 ^ D2 ^ C13
9: C9 9: C8 9: C7 9: C1 ^ D3 ^ C12
8: C8 8: C7 8: C6 8: C0 ^ D4 ^ C11 ^ D0 ^ C15
7: C7 7: C6 7: C5 7: D0 ^ C15 ^ D5 ^ C10 ^ D1 ^ C14
6: C6 6: C5 6: C4 ^ D0 ^ C15 6: D1 ^ C14 ^ D6 ^ C9 ^ D2 ^ C13
5: C5 5: C4 ^ D0 ^ C15 5: C3 ^ D1 ^ C14 5: D2 ^ C13 ^ D7 ^ C8 ^ D3 ^ C12
4: C4 4: C3 4: C2 4: D3 ^ C12
3: C3 3: C2 3: C1 3: D4 ^ C11 ^ D0 ^ C15
2: C2 2: C1 2: C0 2: D5 ^ C10 ^ D1 ^ C14
1: C1 1: C0 1: D0 ^ C15 1: D6 ^ C9 ^ D2 ^ C13
0: C0 0: D0 ^ C15 0: D1 ^ C14 0: D7 ^ C8 ^ D3 ^ C12

Figure 2 • Serial to Parallel CRC Sequence

If input data bits are available in parallel, the number of available in parallel on cycle N/M+1, the next M bits on
steps to generate the CRC can be reduced. In our example, cycle N/M+2, etc.
the 16-bit CRC generation would be a two-step process- one This widely used method is slow for Gigabit Ethernet and
for each set of eight input data bits. The same technique high-speed ATM, where bit rates can top 100 Mbps. An
extends to 32-bit CRCs. Alternatively, we can expand the alternative method is parallel computation of the CRC.
equations to do a full 16- or 32-bit CRC in one step. Serial-to-parallel conversion of the data effectively divides
There is no pipelining other than the CRC register itself. In the input clock frequency by 8, 16, or 32. We can now
an N-bit serial CRC, the data becomes available on the Nth calculate an N-bit CRC M-bits at a time. A typical
clock edge after the first one (which clocks the first bit into implementation is shown in Figure 3 for an 8-bit parallel
the shift register). This is actually cycle N+1. For an N-bit 16-bit CRC.
parallel CRC, with M data bits available, N/M should be an
integer. Again, if cycle 1 is the cycle on which data is
clocked into the N/M bit shift register, the first M bits are

PAD [7:0]
DI[7:0] D Q PARCRC8

E DFE
PAD [15:0]
D Q CRC [15:0
>CLK
E DFE

D Q >CLK
ENABLE
DF1

>CLK

D Q
INIT
DF1

>CLK

CLK

Figure 3 • 8-Bit Parallel CCITT-16 CRC

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Top-Level Interface

Top-Level Block Diagrams

Figure 4 illustrates the serial and parallel cases for the CRC
CLK
block. In addition, Table 1 describes the signals for the
serial and parallel CRC.
RSTn

INITn CRC (N:0)

LOAD

D (M:0)

Figure 4 • CRC Block

Table 1 • Top-Level Signal Description
CLK Input This is the master clock signal.
RSTn Input Asynchronous system reset (initialization) signal.
INITn Input Synchronous reset (initialization) signal.
LOAD Input In parallel mode, when this signal is high the macro is enabled allowing the CRC to be calculated on
incoming data. When this signal is low the previous CRC value is retained on the CRC output. In serial
mode, when this signal is high the macro is enabled allowing the CRC to be calculated on incoming
data. When this signal is low the calculated CRC is shifted out unaltered by incoming data.
D(M:0) Input CRC input data – 8, 16, or 32 bits. For serial CRC computation, this is a single bit.
CRC(N:) Output CRC output data – 8, 16, or 32 bits. For serial CRC computation, this is a single bit.

D e l i ve r ab l e s
A Win32 console application (NT/Win95/Win98/Win2000 If the user wants a different polynomial, an "Enter your
compatible) allows choosing the desired polynomial from polynomial" option is available. For example, the X25
the menu. There are several common generator polynomials polynomial would be entered as 10001000000100001.
supported with the Actel CRC Macro as follow: User-defined polynomials up to 32nd order (comparable to
sCRC8, ATM (HEC) CRC32, for example) are supported.
x8+x2+x+1 In addition, the number of input data bits to be calculated
CRC10, ATM (OAM Cell) in parallel (up to 32) can be selected. The program will
generate a fully synthesizable, completely behavioral VHDL
x10+x9+x5+x4+x+1
description.
CANbus
A simple test bench has been implemented illustrating CRC
x15+x14+x10+x8+x7+x4+x3+1
generation using the X25 polynomial and is supplied with
CRC16 the macro. The test bench reads in random data and
x16+x12+x2+1 calculates the CRC both serially and with 8-bit parallel data.
CRC16 inverted At the end of the simulation, the two CRCs are compared to
x16+x14+x+1 verify that the parallel CRC was implemented correctly
(serial CRCs are correct by inspection). The test bench can
X25 (SDLC, HDLC, CRC-CCITT) be easily modified to accommodate different polynomials.
x16+x12+x5+1
CRC32 (Ethernet, FDDI)
x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1

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Estimated Performance and Device Utilization

The expected performance and utilization statistics are clocked. The serial data rate is the effective system clock
given in Table 2 and Table 3 for serial and parallel CRC rate assuming serialization and deserialization of the data
implementations using the SX-A –3 and ProASICPLUS for the parallel CRC cases.
devices. The clock frequency is the rate at which the CRC is
Table 2 • 54SX-A Utilization and Performance Statistics
CRC Configuration with an SXA08 Sequential/Total Percent (%) Maximum Clock Maximum System
Device Used Modules 54SXA08 Frequency (MHz)1 Frequency

CRC-32 32-bit wide input 32/392 50 114 3.6 GHz

Generator 8-bit wide input 32/36 19 149 1.2 GHz
Polynomial 1-bit wide input 32/115 9 255 255MHz
CRC-16/CCITT 16-bit wide input 16/106 11 166 2.6 GHz
Generator 8-bit wide input 16/57 7 240 1.9 GHz
Polynomial 1-bit wide input 16/35 6.5 297 297 MHz
1. TDPR was used to obtain the timing results. Pipelining the “d” inputs to the macro were also used to obtain parallel timing results.

Table 3 • ProASICPLUS Utilization and Performance Statistics

CRC Configuration with an APA750 Sequential/Total Percent (%) Maximum Clock Maximum System
Device Used Tiles APA750 Frequency (MHz)1 Frequency

CRC-32 32-bit wide input 177/32768 0.5 82 2.4 GHz

Generator 8-bit wide input 177/32768 0.5 82 656 MHz
Polynomial 1-bit wide input 105/32768 0.3 130 130 MHz
CRC-16/CCITT 16-bit wide input 128/32768 0.4 102 1.6 GHz
Generator 8-bit wide input 80/32768 0.2 106 848 MHz
Polynomial 1-bit wide input 38/32768 0.1 169 160 MHz
1. TDPR was used to obtain the timing results. Pipelining the “d” inputs to the macro were also used to obtain parallel timing results.

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