Datasheet A4927

A4927
Automotive Half-Bridge MOSFET Driver
FEATURES AND BENEFITS DESCRIPTION

• Half-bridge MOSFET driver The A4927 is an N-channel power MOSFET driver capable of
• Bootstrap gate drive for N-channel MOSFET bridge controlling MOSFETs connected in a half-bridge arrangement
• Cross-conduction protection with adjustable dead time and is specifically designed for automotive applications with
• Charge pump regulator for low supply voltage operation high-power inductive loads, such as brush DC motors solenoids
• 5.5 to 50 V supply voltage operating range and actuators.
• SPI-compatible serial interface
The A4927 is intended for automotive systems that must meet
• Bridge control by direct logic inputs or serial interface
ASIL requirements. In common with other Allegro A2SIL™
• Programmable gate drive
products, this device incorporates features to complement
• Current sense amplifier 2
proper system design, allowing users to achieve the required
• Programmable diagnostics - ASIL level.
• A2SIL™ product—device features for
safety-critical systems A unique charge pump regulator provides full gate drive for
battery voltages down to 5.5 V for most applications. A bootstrap
capacitor is used to provide the above-battery supply voltage
APPLICATIONS required for N-channel MOSFETs.
• Anti-lock braking systems (ABS)
The half bridge can be controlled by independent logic-level
• HVAC (blower fan)
inputs or through the SPI-compatible serial interface. The
• DC pumps (fuel, oil, water)
external power MOSFETs are protected from shoot-through
• Solenoids and actuators
by a programmable dead time.
• Similar industrial applications
Integrated diagnostics provide indication of multiple internal
PACKAGE: faults, system faults, and power bridge faults, and can be
configured to protect the power MOSFETs under most short-
24-lead TSSOP with
exposed pad (suffix LP)
circuit conditions.
In addition to providing full access to the bridge control, the
serial interface is also used to alter programmable settings such
as dead time, VDS threshold, and fault blank time. Detailed
diagnostic information can be read through the serial interface.
The A4927 is supplied in a 24-lead eTSSOP (suffix LP). This
Not to scale package is lead (Pb) free, with 100% matte-tin leadframe
plating (suffix –T).
VBAT
ECU A4927 Load
SPI
GND
Figure 1: Typical Application
A4927-DS, Rev. 2 February 11, 2019

MCO-0000166
A4927 Automotive Half-Bridge MOSFET Driver
SPECIFICATIONS
SELECTION GUIDE
Part Number Packing Package
7.8 mm × 4.4 mm, 1.2 mm max height
A4927KLPTR-T 4000 pieces per reel
24-lead TSSOP with exposed thermal pad
ABSOLUTE MAXIMUM RATINGS [1]

Characteristic Symbol Notes Rating Unit
Load Supply Voltage VBB –0.3 to 50 V
Regulator Output VREG VREG –0.3 to 16 V
Charge Pump Capacitor Terminal VCP1 CP1 –0.3 to 16 V
VCP1 – 0.3 to
Charge Pump Capacitor Terminal VCP2 CP2 V
VREG + 0.3
Battery-Compliant Logic Input Terminals VIB HS, LSn, RESETn, ENABLE –0.3 to 50 V
Logic Input Terminals VI STRn, SCK, SDI –0.3 to 6 V
Logic Output Terminal VO SDO –0.3 to 6 V
Diagnostics Output VDIAG DIAG –0.3 to 50 V
Sense Amplifier Inputs VCSI CSP, CSM –4 to 6.5 V
Sense Amplifier Output VCSO CSO, OOS –0.3 to 6 V
Bridge Drain Monitor Terminal VBRG VBRG –5 to 55 V
Bootstrap Supply Terminal VC C –0.3 to VREG + 50 V
GH VC – 16 to VC + 0.3 V
High-Side Gate Drive Output Terminal VGH
GH (transient) –18 to VC + 0.3 V
S VC – 16 to VC + 0.3 V
High-Side Source (Load) Terminal VS
S (transient) –18 to VC + 0.3 V
GL VREG – 16 to 18 V
Low-Side Gate Drive Output Terminal VGL
GL (transient) –8 to 18 V
LSS VREG – 16 to 18 V
Bridge Low-Side Source Terminal VLSS
LSS (transient) –8 to 18 V
Ambient Operating Temperature Range TA Limited by power dissipation –40 to 150 °C
Maximum Continuous Junction Temperature TJ(max) 165 °C
Overtemperature event not exceeding 10 seconds,
Transient Junction Temperature TJt lifetime duration not exceeding 10 hours, 180 °C
guaranteed by design characterization.
Storage Temperature Range Tstg –55 to 150 °C
1 With respect to GND. Ratings apply when no other circuit operating constraints are present.
THERMAL CHARACTERISTICS: May require derating at maximum conditions

Characteristic Symbol Test Conditions [2] Value Unit
4-layer PCB based on JEDEC standard 28 °C/W
RθJA
Package Thermal Resistance 2-layer PCB with 3.8 in.2 copper each side 38 °C/W
RθJP 2 °C/W
2 Additional thermal information available on the Allegro website.
Allegro MicroSystems, LLC 2

955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Table of Contents
Features and Benefits 1 Gate Drive Control 17
Description 1 Logic Control Inputs 18
Package 1 Output Disable 18
Typical Application 1 Sleep Mode 19
Selection Guide 2 Current Sense Amplifier 19
Absolute Maximum Ratings 2 Diagnostic Monitors 19
Thermal Characteristics 2 Status and Diagnostic Registers 19
Pinout Diagram and Terminal List Table 4 Chip-Level Protection 19
Functional Block Diagram 5 Operational Monitors 20
Electrical Characteristics 6 Power Bridge and Load Faults 21
Supply and Reference 6 Fault Action 23
Gate Output Drive 7 Fault Masks 23
Logic Inputs and Outputs 8 Serial Interface 25
Logic I/O – Dynamic Parameters 8 Configuration Registers 27
Current Sense Amplifier 9 Diagnostic Registers 27
Diagnostics and Protection 10 Control Register 27
Timing Diagrams 11 Status Register 28
Logic Truth Tables 13 Serial Register Reference 29
Functional Description 14 Application Information 35
Input and Output Terminal Functions 14 Dead-Time Selection 35
Power Supplies 15 Bootstrap Capacitor Selection 35
Pump Regulator 15 Bootstrap Charging 35
Gate Drives 15 VREG Capacitor Selection 36
Bootstrap Supply 15 Current Sense Amplifier Configuration 36
Bootstrap Charge Management 15 Current Sense Amplifier Output Signals 36
Top-Off Charge Pump 16 Input/Output Structures 37
High-Side Gate Drive 16 Layout Recommendations 38
Low-Side Gate Drive 16 Package Outline Drawing 39
Gate Drive Passive Pull-Down 17
Dead Time 17

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PINOUT DIAGRAM AND TERMINAL LIST TABLE
GND 1 24 VBRG
DIAG 2 23 VBB
ENABLE 3 22 CP1
RESETn 4 21 CP2
HS 5 20 VREG
LSn 6 PAD 19 C
SDI 7 18 S
SCK 8 17 GH
SDO 9 16 GL
STRn 10 15 LSS
OOS 11 14 CSP
CSO 12 13 CMS
24-Lead eTSSOP (suffix LP)

Pinout Diagram
Terminal List Table

Name Number Function
C 19 Bootstrap capacitor
CP1 22 Pump capacitor CCP connection
CP2 21 Pump capacitor CCP connection
CSM 13 Current sense amplifier (–) input
CSO 12 Current sense amplifier output
CSP 14 Current sense amplifier (+) input
DIAG 2 Diagnostic output
ENABLE 3 Gate drive output control input
GH 17 High-side gate drive output
GL 16 Low-side gate drive output
GND 1 Power ground
HS 5 HS control input
LSn 6 LS control input
LSS 15 Low-side source
OOS 11 Sense amplifier offset output
RESETn 4 Standby mode control input
S 18 Load connection
SCK 8 Serial clock input
SDI 7 Serial data input
SDO 9 Serial data output
STRn 10 Serial strobe (chip select) input
VBB 23 Main power supply
VBRG 24 High-side drain voltage sense
VREG 20 Regulated gate drive supply
PAD – Thermal pad; connect to GND

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CCP
CP1
CP2
VBB
VREG
VBAT
Logic Charge
Supply Pump CREG
Regulator Regulator
VBRG
Charge
Pump
C
ENABLE
HS GH
Drive
VDS
HS Monitor
Control Bootstrap S
LSn Logic Monitor
VDS
Monitor
LS GL
RESETn Drive
Timers
LSS
OOS
STRn V OOS
SCK DAC CSP
Serial
SDI Interface
SDO DAC
CSM
DIAG CSO
Diagnostics &
Protection
PAD GND
Figure 2: Functional Block Diagram

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ELECTRICAL CHARACTERISTICS: Valid for TJ = –40 to 150°C, VBB = 5.5 to 50 V, unless otherwise specified
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
SUPPLY AND REFERENCE
Operating; outputs active 5.5 – 50 V
VBB Functional Operating Range VBB Operating; outputs disabled 5 – 50 V
No unsafe states 0 – 50 V
RESETn = high, VBB = 12 V,
IBBQ – 8 20 mA
VBB Quiescent Current All gate drive outputs low
IBBS RESETn ≤ 300 mV, sleep mode, VBB < 35 V – – 20 µA
Internal Logic Supply Regulator
VDL 3.1 3.3 3.5 V
Voltage [3][4]
VBB > 7.5 V, IVREG = 0 to 30 mA 7.5 8 8.5 V
VREG Output Voltage, VRG = 0 VREG 6 V < VBB ≤ 7.5 V, IVREG = 0 to 13 mA 7.5 8 8.5 V
5.5 V < VBB ≤ 6 V, IVREG < 8 mA 7.5 8 8.5 V
VBB > 9 V, IVREG = 0 to 30 mA 9 11 11.7 V
7.5 V < VBB ≤ 9 V, IVREG = 0 to 20 mA 9 11 11.7 V
VREG Output Voltage, VRG = 1 VREG
6 V < VBB ≤ 7.5V, IVREG ≤ 0 to 13mA 7.9 – – V
5.5 V < VBB ≤ 6 V, IVREG < 8 mA 7.9 9.5 – V
ID = 10 mA 0.4 0.7 1.0 V
Bootstrap Diode Forward Voltage VfBOOT
ID = 100 mA 1.2 1.9 2.5 V
Bootstrap Diode Current Limit IDBOOT 250 500 750 mA
Top-Off Charge Pump Current Limit ITOCPM 50 100 – µA
High-Side Gate Drive Static Load
RGSH 250 – – kΩ
Resistance
System Clock Period tOSC 42.5 50 57.5 ns
Continued on the next page…

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ELECTRICAL CHARACTERISTICS (continued): Valid for TJ = –40 to 150°C, VBB = 5.5 to 50 V, unless otherwise specified
GATE OUTPUT DRIVE
Turn-On Time tr CLOAD = 10 nF, 20% to 80% – 190 – ns
Turn-Off Time tf CLOAD = 10 nF, 80% to 20% – 120 – ns
Pull-Up Peak Source Current IPUPK – 400 – mA
IR1 = IR2 = 0, TJ = 25°C, IGH = –150 mA [1] 4 6 10.5 Ω
Pull-Up On Resistance RDS(on)UP
IR1 = IR2 = 0, TJ = 150°C, IGH = –150 mA [1] 9.5 12 19 Ω
Pull-Down Peak Sink Current IPDPK – 800 – mA
IF1 = IF2 = 0, TJ = 25°C, IGL = 150 mA 1.5 2.4 3.1 Ω
Pull-Down On Resistance RDS(on)DN
IF1 = IF2 = 0, TJ = 150°C, IGL = 150 mA 2.9 4 5.5 Ω
GH Output Voltage High VGHH VC – 0.2 – – V
GH Output Voltage Low VGHL –10 µA < IGH < 10 µA – – VS + 0.3 V
VREG –
GL Output Voltage High VGLH – – V
0.2
VLSS +
GL Output Voltage Low VGLL –10 µA < IGL < 10 µA – – V
0.3
VBB = 0 V, VGH – VS < 0.3 V – 950 – kΩ
GH Passive Pull-Down RGHPD
VBB = 0 V, VGL – VLSS < 0.3 V – 950 – kΩ
Input Change to unloaded Gate output change,
60 90 140 ns
(Figure 5) DT[5:0] = 0
Turn-Off Propagation Delay tP(off)
135 165 215 ns
(Figure 5) DT[5:0] > 0
50 80 130 ns
(Figure 5) DT[5:0] = 0
Turn-On Propagation Delay tP(on)
125 155 205 ns
(Figure 5) DT[5:0] > 0
Propagation Delay Matching
ΔtOO DT[5:0]=0 – 15 30 ns
(On-to-Off)
Propagation Delay Matching
ΔtHL Same state change, DT[5:0] = 0 – – 20 ns
(GH-to-GL)
Default power-up state (Figure 5) 1.36 1.6 1.84 µs
Dead Time (Turn-Off To Turn-On Delay) tDEAD
Programmable range DT[5:0], nominal 0.1 – 3.15 µs

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LOGIC INPUT AND OUTPUTS
Input Low Voltage VIL – – 0.8 V
Input High Voltage VIH All logic inputs 2.0 – – V
Input Hysteresis VIhys RESETn inputs 200 400 – mV
Input Hysteresis VIhys All other logic inputs 250 550 – mV
Input Pull-Down HS, ENABLE, RPD 0 < VIN < 3 V – 50 – kΩ
RESETn IPD 3 V < VIN < 50 V – 70 – µA
Input Pull-Down SDI, SCK RPDS 0 < VIN < 3 V – 50 – kΩ
Input Pull-Up Current to VDL IPU STRn – 70 – µA
Input Pull-Up to VDL RPU LSn – 170 – kΩ
Output Low Voltage SDO, DIAG VOL IOL = 1 mA – 0.1 0.4 V
IOS = –200 µA [1] VDL – 0.1 – – V
Output High Voltage SDO VOHS
IOS = –1 mA [1] VDL – 0.4 – – V
Output Leakage SDO [1] IOS 0 V < VOS < VDL, STRn = 1 –1 – 1 µA
0 V < VOD < 12 V, DIAG active – 10 17 mA
Output Current Limit (DIAG) IOLDLIM
18 V ≤ VOD < 50 V, DIAG active – – 2.5 mA
0 V < VOD < 12 V, DIAG inactive –1 – 1 µA
Output Leakage [1] (DIAG) IOD
18 V ≤ VOD < 50 V, DIAG inactive – – 2.5 mA
LOGIC I/O – DYNAMIC PARAMETERS
Reset Pulse Width tRST 0.5 – 4.5 µs
Reset Shutdown Time tRSD 30 – – µs
Input Pulse Filter Time tPIN HS, LSn – 35 – ns
Clock High Time tSCKH A in Figure 4 50 – – ns
Clock Low Time tSCKL B in Figure 4 50 – – ns
Strobe Lead Time tSTLD C in Figure 4 30 – – ns
Strobe Lag Time tSTLG D in Figure 4 30 – – ns
Strobe High Time tSTRH E in Figure 4 300 – – ns
Data Out Enable Time tSDOE F in Figure 4 – – 40 ns
Data Out Disable Time tSDOD G in Figure 4 – – 30 ns
Data Out Valid Time From Clock
tSDOV H in Figure 4 – – 40 ns
Falling
Data Out Hold Time From Clock
tSDOH I in Figure 4 5 – – ns
Falling
Data In Set-Up Time To Clock Rising tSDIS J in Figure 4 15 – – ns
Data In Hold Time From Clock Rising tSDIH K in Figure 4 10 – – ns
Wake Up From Sleep tEN – – 2 ms

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CURRENT SENSE AMPLIFIER
Input Offset Voltage VIOS –4 – +4 mV
Input Offset Voltage Drift ΔVIOS – ±4 – µV/°C
Input Bias Current [1] IBIAS 0 V < VCSP < VDL, 0 V < VCSM < VDL –16 – 31 µA
Input Offset Current [1] IOS VID = 0 V, VCM in range –10 – +10 µA
Input Common-Mode Range (DC) VCM VID = 0 V –1.8 – +2 V
Default power-up value – 35 – V/V
Gain AV
Programmable range, SAG[2:0], nominal 10 – 50 V/V
Gain Error EA VCM in range –5 ±2 +5 %
Default power-up value – 2.5 – V
Output Offset VOOS
Programmable range, SAO[3:0], nominal 0 – 2.5 V
Output Offset Error EVO VCM in range, VOOS > 0 V –10 ±2 +10 %
Small Signal –3 dB Bandwidth
BW VIN = 10 mVpp 500 – – kHz
at Gain = 25
VCSO = 1 Vpp square wave
Output Settling Time (to within 40 mV) tSET – 1 1.8 µs
Gain = 25, COUT = 200 pF
Output Dynamic Range VCSOUT –100 µA < ICSO < 100 µA 0.3 – 4.8 V
Output Voltage Clamp VCSC ICSO = –2 mA 4.85 5.2 5.6 V
Output Current Sink [1] ICSsink VID = 0 V, VCSO = 1.5 V, Gain = 25 0.275 – – mA
VOOS = 0 V, VID = –50 mV, VCSO = 1.5 V,
Output Current Sink (Boosted) [1][5] ICSsinkb 1 – – mA
Gain = 25
VID = 200 mV, VCSO = 1.5 V
Output Current Source [1] ICSsource – – –1 mA
Gain = 25, Offset = 0 V
VID = 0 V, 100 kHz, Gain = 25 – 75 – dB
VBB Supply Ripple Rejection Ratio PSRR
VCSP = VCSM = 0 V, DC, Gain = 25 75 – – dB
VCM step from 0 to 200 mV
DC Common-Mode Rejection Ratio CMRR 55 – – dB
Gain = 25
VCM = 200 mVpp, 100 kHz, Gain = 25 – 62 – dB
AC Common-Mode Rejection Ratio CMRR VCM = 200 mVpp, 1 MHz, Gain = 25 – 43 – dB
VCM = 200 mVpp, 10 MHz, Gain = 25 – 25 – dB
Common Mode Recovery Time VCM step from –4 V to +1 V
tCMrec – 1 – µs
(to within 100 mV) Gain = 25, COUT = 200 pF
VID step from 0 to 175 mV
Output Slew Rate 10% to 90% SR – 10 – V/µs
Gain = 25, COUT = 200 pF
Input Overload Recovery VID step from 250 mV to 0 V
tIDrec – 1 – µs
(to within 100 mV) Gain = 25, COUT = 200 pF

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DIAGNOSTICS AND PROTECTION
VRON VREG rising 6.4 6.6 6.7 V
VREG Undervoltage VRG = 0
VROFF VREG falling 5.5 5.7 5.9 V
VRON VREG rising 7.6 7.95 8.2 V
VREG Undervoltage VRG = 1
VROFF VREG falling 6.9 7.15 7.4 V
VREG Overvoltage Warning VROV VREG rising 15.5 15.9 16.5 V
VREG Overvoltage Hysteresis VROVHys 1200 1500 – mV
VBB Overvoltage Warning VBBOV VBB rising 32 – 36 V
VBB Overvoltage Hysteresis VBBOVHys 1 – – V
VBB POR Voltage VBBR VBB – 3.5 – V
Bootstrap Undervoltage VBCUV VBOOT falling, VBOOT = VC – VS 56 – 64 %VREG
Bootstrap Undervoltage Hysteresis VBCUVHys – 13 – %VREG
VBOOT VBOOT VBOOT
Gate Drive Undervoltage Warning HS VGSHUV VGSH V
– 1.25 –1 – 0.8
VREG VREG VREG
Gate Drive Undervoltage Warning LS VGSLUV VGSL V
– 1.25 –1 – 0.8
VBRG Input Voltage VBRG When VDS monitor is active 5.5 VBB 50 V
VDSTH = default, VBB = 12 V
IVBRG – – 500 µA
VBRG Input Current 0 V < VBRG < VBB
IVBRGQ Sleep mode VBB < 35 V – – 5 µA
Default power-up value 1.1 1.2 1.3 V
Programmable range VT[5:0], nominal
0 – 3.15 V
VDS Threshold – High Side VDSTH VBRG ≥ 7 V
Programmable range VT[5:0]
0 – 1.5 V
5.5 V ≤ VBRG < 7 V [6]
High-side on, VDSTH ≥1 V, VBRG > 7 V –200 ±100 200 mV
High-Side VDS Threshold Offset [2] VDSTHO
High-side on, VDSTH < 1 V –150 ±50 150 mV
VDS Threshold – Low Side VDSTL
Programmable range, VBB ≥ 5.5 V [6] 0 – 3.15 V
Low-side on, VDSTL ≥ 1 V, VBRG > 7 V –200 ±100 200 mV
Low-Side VDS Threshold Offset [2] VDSTLO
Low-side on, VDSTL < 1 V –150 ±50 150 mV
Default power-up value (Figure 6) 1.36 1.6 1.84 µs
VDS Qualify Time tVDQ
Programmable range TVD[5:0], nominal 0 – 6.3 µs
Overcurrent Voltage VOCT
Programmable range, OCT[3:0], nominal 0.3 – 4.8 V
Overcurrent Qualify Time tOCQ 6.75 7.5 8.25 µs
Temperature Warning Threshold TJWH Temperature increasing 125 135 145 °C
Temperature Warning Hysteresis TJWHhys Recovery = TJWH – TJWHhys – 15 – °C
Overtemperature Threshold TJF Temperature increasing 170 175 180 °C
Overtemperature Hysteresis TJHys Recovery = TJF – TJHys – 15 – °C
1 For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device terminal.
2 VDS offset is the difference between the programmed threshold, V
DSTH or VDSTL and the actual trip voltage.
3 VDL derived from VBB for internal use only. Not accessible on any device terminal.
4 Verified by design and characterization.
5 If the amplifier output voltage (V
CSO) is more positive than the value demanded by the applied differential input (VID) and output offset (VOOS)
conditions, then output current sink capability is boosted to enhance negative-going transient response.
6 Maximum value of VDS threshold that should be set in the configuration registers for correct operation when V
BRG is within the stated range.

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VCSO = [(VCSP + VCSM) × AV] + VOOS

CSP
CSO
VCM = (VCSP + VCSM) / 2 RS VID AV
VCSD
OOS
CSM
VCSP AV set by VOOS set by
SAG[2:0] VOOS VCSO
SAO[3:0]
VCSM
IPH A4927
GND
Figure 3: Sense Amplifier Voltage Definitions
STRn
C A B D E
SCK
J K
SDI X D15 X D14 X X D0 X

F
I G
SDO Z D15’ D14’ D0’ Z
Figure 4: Serial Interface Timing (X = don’t care, Z = high impedance (tri-state))
HS
LSn
tDEAD tP(off) tP(on) tP(off)

GH
GL
tP(off) tDEAD tP(on) tP(off)

Synchronous Rectification High-side pwm Low-side pwm
Figure 5: Gate Drive Timing – Control Inputs

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MOSFET turn on MOSFET turn on MOSFET on MOSFET on

No fault present Fault present Transient disturbance Fault occurs
No fault present
Gx
VDS
tVDQ tVDQ
Fault Bit
Figure 6a: VDS Fault Monitor – Blank Mode Timing (VDQ = 1)
MOSFET turn on MOSFET turn on MOSFET on MOSFET on

No fault present Fault present Transient disturbance Fault occurs
No fault present
Gx
VDS
tVDQ tVDQ tVDQ tVDQ

Fault Bit
Figure 6b: VDS Fault Monitor – Debounce Mode Timing (VDQ = 0)

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LOGIC TRUTH TABLES

Table 1: Control Logic (Control by Logic Inputs)
HS LSn GH GL S
0 1 LO LO Z
0 0 LO HI LO
1 1 HI LO HI
1 0 LO LO Z
HI = high-side FET active, LO = low-side FET active
Z = high impedance, both FETs off
All control register bits set to 0, RESETn = 1, ENABLE = 1
Table 2: Control Logic (Control by Serial Register)

HSR LSR GH GL S
0 0 LO LO Z
0 1 LO HI LO
1 0 HI LO HI
1 1 LO LO Z
HI = high-side FET active, LO = low-side FET active
Z = high impedance, both FETs off
HS = 0, LSN = 1, RESETn = 1, ENABLE = 1
Table 3: Control combination logic table – Logic Inputs and Serial Register
Terminal Register Internal Terminal Register Internal
HS HSR HI LSn LSR LO Internal control signals (HI, LO) are derived by combining
the logic states applied to the control input terminals (HS,
0 0 0 0 0 1
LS) with the bit patterns held in the Control register (HSR,
0 1 1 0 1 1 LSR).
1 0 1 1 0 0
Normally the input terminals or the Control register method
1 1 1 1 1 1 is used for control with the other being held inactive (all
termials or bits at logic 0).
ENABLE HI LO GH GL S Comment
1 0 0 L L Z Bridge disabled
1 0 1 L H LO Bridge sinking
1 1 0 H L HI Bridge sourcing
1 1 1 L L Z Bridge disabled
0 X X L L Z Bridge disabled
X = don’t care

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FUNCTIONAL DESCRIPTION
The A4927 is a half-bridge (H-bridge) MOSFET driver (pre- Input and Output Terminal Functions
driver) requiring a single unregulated supply of 5.5 to 50 V. It
includes an integrated linear regulator to supply the internal logic. VBB: Main power supply for internal regulators and charge
All logic inputs are TTL compatible and can be driven by 3.3 or pump. The main power supply should be connected to VBB
5 V logic. through a reverse voltage protection circuit and should be
decoupled with ceramic capacitors connected close to the supply
The two high-current gate drives are capable of driving a wide and ground terminals.
range of N-channel power MOSFETs, and are configured as a
half-bridge driver with one high-side drive and one low-side VBRG: Sense input to the top of the external MOSFET bridge.
drive. The A4927 provides all necessary circuits to ensure that the Allows accurate measurement of the voltage at the drain of the
gate-source voltage of both high-side and low-side external FETs high-side MOSFET in the bridge.
are above 10 V, at supply voltages down to 7 V. For extreme CP1, CP2: Pump capacitor connection for charge pump. Con-
battery voltage drop conditions, correct functional operation is nect a minimum 220 nF, typically 470 nF, ceramic capacitor
guaranteed at supply voltages down to 5.5 V, but with a reduced between CP1 and CP2.
gate drive voltage.
VREG: programmable regulated voltage, 8 or 11 V, used to sup-
Gate drives can be controlled directly through the logic input ter- ply the low-side gate drivers and to provide current for the above
minals or through an SPI-compatible serial interface. The sense supply charge pump. A sufficiently large storage capacitor must
of the logic inputs are arranged to allow the bridge to be driven be connected to this terminal to provide the required transient
by a single PWM input if required. The bridge can also be driven charging current.
by direct logic inputs or by two PWM signals depending on the
required complexity. The logic inputs are battery voltage compli- GND: Analog, digital, and power ground. Connect to supply
ant, meaning they can be shorted to ground or supply without ground–see Layout Recommendations.
damage, up to the maximum battery voltage of 50 V. C: High-side connection for the bootstrap capacitor and positive
Bridge efficiency can be enhanced by using the synchronous supply for the high-side gate driver.
rectification ability of the drives. When synchronous rectification GH: High-side, gate-drive output for an external N-channel
is used, cross-conduction (shoot through) in the external bridge MOSFET.
is avoided by an adjustable dead time. A hardwired logic lockout
ensures that the high-side and the low-side cannot be permanently S: Source connection for high-side MOSFET providing the nega-
active at the same time. tive supply connections for the floating high-side driver.
A low-power sleep mode allows the A4927, the power bridge, GL: Low-side gate-drive output for an external N-channel MOS-
and the load to remain connected to a vehicle battery supply with- FET.
out the need for an additional supply switch. LSS: Low-side return path for discharge of the capacitance on
The A4927 includes a number of diagnostic features to provide the low-side MOSFET gate, connected to the source of the low-
indication and/or protection against undervoltage, overtempera- side external MOSFET independently through a low-impedance
ture, and power bridge faults. A single diagnostic output provides track.
basic fault indication and detailed diagnostic information is HS: Logic inputs with pull-down to control the high-side gate
available through the serial interface. The serial interface also drive. Battery voltage compliant terminal.
provides access to programmable dead time, fault blanking time
and programmable VDS threshold for short detection. LSn: Logic input with pull-up to control the low-side gate drive.
This is an active-low input. Battery voltage compliant terminal.
The A4927 includes a low-side current sense amplifier with pro-
grammable gain and offset. The amplifier is specifically designed ENABLE: Logic input to enable the gate drive outputs. Battery
for current sensing in the presence of high voltage and current voltage compliant terminal.
transients.

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RESETn: Clears latched faults that may have disabled the out- requires a pump capacitor, typically 470 nF, connected between
puts when taken low for the reset pulse width, tRST. Forces low- the CP1 and CP2 terminals.
power shutdown (sleep) when held low for more than the RESET
The regulated voltage, VREG, can be programmed to 8 or 11 V
shutdown time, tRSD. Battery voltage compliant terminal.
and is available on the VREG terminal. The voltage level is
SDI: Serial data logic input with pull-down. 16-bit serial word selected by the value of the VRG bit. When VRG = 1, the voltage
input msb first. is set to 11 V; when VRG = 0 the voltage is set to 8 V. A suf-
ficiently large storage capacitor (see Application Information
SDO: Serial data output. High impedance when STRn is high.
section) must be connected to this terminal to provide the tran-
Outputs bit 15 of the diagnostic register, the fault flag, as soon as
sient charging current to the low-side drivers and the bootstrap
STRn goes low.
capacitors.
SCK: Serial clock logic input with pull-down. Data is latched
in from SDI on the rising edge of SCK. There must be 16 rising Gate Drives
edges per write and SCK must be held high when STRn changes. The A4927 is designed to drive external, low on-resistance,
STRn: Serial data strobe and serial access enable logic input power N-channel MOSFETs. It will supply the large transient
with pull-up. When STRn is high, any activity on SCK or SDI currents necessary to quickly charge and discharge the external
is ignored and SDO is high impedance, allowing multiple SDI MOSFET gate capacitance in order to reduce dissipation in the
slaves to have common SDI, SCK, and SDO connections. external MOSFET during switching. The charge current for the
low-side drive is provided by the capacitor on the VREG termi-
CSP, CSM: Current sense amplifier inputs. nal. The charge current for the high-side drives is provided by
CSO: Current sense amplifier output. the bootstrap capacitor connected between the C and S terminals.
MOSFET gate charge and discharge rates may be controlled by
OOS: Monitor point for programmable analogue output offset setting a group of parameters via the serial interface or by using
voltage applied to current sense amplifiers. an external gate resistor between the gate drive output and the
DIAG: Diagnostic output. Provides general fault flag output. gate terminal of the MOSFET.
Power Supplies Bootstrap Supply

A single power supply voltage is required. The main power sup- When the high-side drivers are active, the reference voltage for
ply, VBB, should be connected to VBB through a reverse voltage the driver will rise to close to the bridge supply voltage. The
protection circuit. A 100 nF ceramic decoupling capacitor must supply to the driver will then have to be above the bridge supply
be connected close to the supply and ground terminals. voltage to ensure that the driver remains active. This temporary
high-side supply is provided by a bootstrap capacitor connected
An internal regulator provides the supply to the internal logic. between the bootstrap supply terminal, C, and the high-side refer-
All logic is guaranteed to operate correctly to below the regula- ence terminal, S.
tor undervoltage levels ensuring that the A4927 will continue to
operate safely until all logic is reset when a power-on-reset state The bootstrap capacitor is independently charged to approxi-
is present. mately VREG when the associated reference S terminal is low.
When the output swings high, the voltage on the bootstrap supply
The A4927 will operate within specified parameters with VBB terminal rises with the output to provide the boosted gate voltage
from 7 to 50 V and will function correctly with a supply down to needed for the high-side N-channel power MOSFETs.
5.5 V. This provides a rugged solution for use in the harsh auto-
motive environment. Bootstrap Charge Management
Pump Regulator The A4927 monitors the bootstrap capacitor charge voltage to
ensure sufficient high-side drive. It also includes an optional
The gate drivers are powered by a programmable voltage internal bootstrap capacitor charge management system (bootstrap man-
regulator which limits the supply to the drivers and therefore ager) to ensure that the bootstrap capacitor remains sufficiently
the maximum gate voltage. At low supply voltage, the regulated charged under all conditions. The bootstrap manager is enabled
supply is maintained by a charge pump boost converter which by default but may be disabled by setting the DBM bit to 1. This

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may be required in systems where the output MOSFET switching high-side driver and therefore appears as a static resistive load on
must only be allowed by the controlling processor. the top-off charge pump. The minimum value of RGSH for which
the top-off charge pump can provide current, without dropping
Before a high-side drive can be turned on, the bootstrap capacitor
below the bootstrap undervoltage threshold, is defined in the
voltage must be higher than the turn-on voltage threshold, VBCUV
Electrical Characteristics table.
+ VBCUVHys. If this is not the case, then the A4927 will attempt
to charge the bootstrap capacitor by activating the low-side drive. In all cases, the charge required for initial turn-on of the high-side
Under normal circumstances this will charge the capacitor above gate is always supplied by the bootstrap capacitor. If the bootstrap
the turn-on voltage in a few microseconds and the high-side drive capacitor becomes discharged, the top-off charge pump alone will
will then be enabled. The bootstrap voltage monitor remains not provide sufficient current to allow the MOSFET to turn on.
active while the high-side drive is active and if the voltage drops
below the turn-off voltage threshold, VBCUV, a charge cycle is High-Side Gate Drive
also initiated. A high-side gate-drive output for an external N-channel MOS-
The bootstrap charge management circuit may actively charge the FETs is provided on the GH terminal. GH = 1 (or “high”) means
bootstrap capacitor regularly when the PWM duty cycle is very that the upper-half of the driver is turned on and its drain will
high, particularly when the PWM off-time is too short to permit source current to the gate of the high-side MOSFET in the exter-
the bootstrap capacitor to become sufficiently charged. nal load-driving bridge, turning it on. GH = 0 (or “low”) means
that the lower-half of the driver is turned on and its drain will
In some systems, it may not be desirable to permit this feature. sink current from the external MOSFET’s gate circuit to the S
In this case the bootstrap manager may be disabled by setting terminal, turning it off.
the DBM bit to 1. If the bootstrap manager is disabled, then the
user must ensure that the bootstrap capacitor does not become The reference point for the high-side drive is the load connec-
discharged below the bootstrap undervoltage threshold, VBCUV, tions, S. This terminal senses the voltage at the load connections.
or a bootstrap fault will be indicated and the outputs disabled. This terminal is also connected to the negative side of the boot-
This can happen with very high PWM duty cycles when the strap capacitor and is the negative supply reference connections
charge time for the bootstrap capacitor is insufficient to ensure for the floating high-side driver. The discharge current from the
a sufficient recharge to match the MOSFET gate charge transfer high-side MOSFET gate capacitance flows through these connec-
during turn on. tions which should have low-impedance traces to the MOSFET
bridge.
If, for any reason, the bootstrap capacitor cannot be sufficiently
charged a bootstrap fault will occur—see diagnostics section for Low-Side Gate Drive
further details. The low-side gate-drive output on GL is referenced to the LSS
Top-Off Charge Pump terminal. This output is designed to drive an external N-channel
power MOSFET. GL = 1 (or “high”) means that the upper-half of
An additional “top-off” charge pump is provided, which will the driver is turned on and its drain will source current to the gate
allow the high-side drive to maintain the gate voltage on the of the low-side MOSFET in the external power bridge, turning it
external MOSFET indefinitely, ensuring so-called 100% PWM on. GL = 0 (or “low”) means that the lower-half of the driver is
if required. This is a low-current trickle charge pump and is only turned on and its drain will sink current from the external MOS-
operated after a high side has been signaled to turn on. There is a FET’s gate circuit to the LSS terminal, turning it off.
small amount of bias current drawn from the C terminal to oper-
ate the floating high side circuit (<40 µA) and the charge pump The LSS terminal provides the return path for discharge of the
simply provides enough drive to ensure the bootstrap voltage, and capacitance on the low-side MOSFET gate. This terminal is
hence the gate voltage, will not droop due to this bias current. connected independently to the source of the low-side external
MOSFETs through a low-impedance track.
In some applications, a safety resistor is added between the gate
and source of each MOSFET in the bridge. When a high-side An integrated slew control feature allows the MOSFET gate
MOSFET is held in the on state, the current through the associ- charge and discharge rates to be controlled via the serial interface
ated high-side gate-source resistor (RGSH) is provided by the as detailed in the Gate Drive Control section.

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Either the internal slew control or an external resistor between Gate Drive Control
the gate drive output and the gate connection to the MOSFET (as
close as possible to the MOSFET) can be used to control the slew MOSFET gate drives are controlled according to the values set in
rate seen at the gate, thereby controlling the di/dt and dv/dt of the Config 6, 7, and 8 registers.
voltage at the S terminal.
Gate Drive
Gate Drive Passive Pull-Down Command
State OFF I1 I2 ON
Each gate drive output includes a discharge circuit to ensure
that any external MOSFET connected to the gate drive output VGS Miller Region
is held off when the power is removed. This discharge circuit
appears as 950 kΩ between the gate drive and the source connec-
tions for each MOSFET. It is only active when the A4927 is not VDS
t1
driving the output to ensure that any charge accumulated on the
MOSFET gate has a discharge path even when the power is not Figure 7a: Off-to-On Transition (Gate Drive)
connected.
Dead Time Gate Drive

Command
To prevent cross-conduction (shoot through) of the power MOS- State OFF ON
FET bridge, it is necessary to have a dead-time delay between a
high- or low-side turn-off and the next turn-on event. The poten-
VGS
tial for cross-conduction occurs when the high-side and low-side Miller Region
pair of MOSFETs is switched at the same time, for example, at

the PWM switchpoint. In the A4927, the dead time is set by the VDS
contents of the DT[5:0] bits in configuration register 0. These six
bits contain a positive integer that determines the dead time by
Figure 7b: Off-to-On Transition (Switched)
division from the system clock.
The dead time is defined as:
Gate Drive
Command
tDEAD = n × 50 ns I1 I2
State ON OFF
where n is a positive integer defined by DT[5:0] and
Miller Region
tDEAD has a minimum active value of 100 ns. VGS
The accuracy of tDEAD is determined by the accuracy of the

system clock as defined in the electrical characteristics table. The VDS t1
range of it is 100 ns to 3.15 µs. A value of 1 or 2 in DT[5:0] will
set the minimum active dead time of 100 ns. Figure 7c: On-to-Off Transition (Gate Drive)
If DT[5:0] is left at the default value of zero, the dead timer is
disabled and no minimum dead time is generated by the A4927. Gate Drive
The logic that prevents permanent cross-conduction is, however, Command
still active. Adequate dead time must be generated externally State ON OFF
by, for example, the microcontroller producing the drive signals

applied to the A4927 logic inputs or Control register. VGS Miller Region
The internally generated dead time is only present if the on com-

mand for one MOSFET occurs within one dead time after the off VDS
command for the complimentary MOSFET. In the case where
one side of the drive is permanently off the dead time will not Figure 7d: On-to-Off Transition (Switched)
occur. In this case the gate drive will turn on within the specified
propagation delay after the input goes high. (see Figure 5).

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MOSFET off-to-on transitions are controlled as detailed in Figure Logic Control Inputs
7a. When a gate drive is commanded to turn on a current, I1 (as
defined by IR1[3:0]), is sourced on the GH or GL terminal for a Two logic level digital inputs provide direct control for the gate
duration, t1 (defined by TR[3:0]). These parameters should typi- drives, one for each drive. These TTL threshold logic inputs can
cally be set so as to quickly charge the MOSFET input capaci- be driven from 3.3 or 5 V logic and all have a typical hysteresis
tance to the start of the Miller region as drain-source voltage does of 500 mV to improve noise performance. Each input can be
not change during this period. Thereafter, the current sourced shorted to the VBB supply, up to the absolute maximum supply
on GH or GL is set to a value of I2 (as defined by IR2[3:0]) and voltage, without damage to the input.
remains at this value while the MOSFET transitions through the Input HS is active high and controls the high-side drive. LSn is
Miller region, and reaches the fully on state. For the high-side active low and controls the low-side drive. The logical relation-
MOSFET, fully on is assumed when the drain-source voltage, ship between the inputs and the gate drive outputs is defined in
VDS = VBRG – VS, < VDSTH. For the low-side MOSFET, fully on Table 1.
is assumed when VDS = VS – VLSS, < VDSTL.
The logic sense of the inputs (active high or active low) are
I2 should be set to achieve the required input capacitance charge arranged to permit the bridge to be controlled with 1 or 2 inputs.
time. Once in the fully on state, the GH or GL output switches The control inputs can be driven together to control both high-
from current to voltage drive to hold the MOSFET in the on state. side and low-side drives with a single PWM input to provide
If the values of IR1[3:0] and IR2[3:0] are set to 0, GH or GL synchronous rectification.
produces maximum drive to turn on the MOSFET as quickly as The gate drive outputs can also be controlled through the serial
possible without attempting to control the MOSFET input capaci- interface by setting the appropriate bit in the control register. In
tance charge time (Figure 7b). The value of TR[3:0] has no effect the control register all bits are active high. The logical relation-
on switching speed. ship between the register bit setting and the gate drive outputs is
MOSFET on-to-off transitions are controlled as detailed in Figure defined in Table 2.
7c. When a gate drive is commanded to turn off, a current, I1 The logic inputs are combined, using logical OR, with the cor-
(as defined by IF1[3:0]), is sunk by the GH or GL terminal for responding bits in the serial interface control register to deter-
a duration, t1 (defined by TF[3:0]). These parameters should mine the state of the gate drive. The logical relationship between
typically be set so as to quickly discharge the MOSFET input the combination of logic input and register bit setting and the
capacitance to the start of the Miller region as drain-source volt- gate drive outputs is defined in Table 3. In most applications,
age does not change during this period. Thereafter, the current either the logic inputs or the serial control will be used. When
sunk by GH or GL is set to a value of I2 (as defined by IF2[3:0]) using only the logic inputs to control the bridge the serial register
and remains at this value while the MOSFET transitions through should be left in the reset condition with all control bits set to 0.
the Miller region and reaches the fully off state. For the high-side When using only the serial interface to control the bridge, the
MOSFET, fully off is assumed when VDS(low side) = VS – VLSS inputs should be tied such that the active-low inputs are pulled
< VDSTH. For the low-side MOSFET, fully off is assumed when high and the active-high inputs connected to GND—that is, HS
VDS(high side) = VBRG – VS < VDSTH. I2 should be set to achieve tied to GND and LSn tied high. The internal pull-up and pull-
the required MOSFET input capacitance discharge time. Once in down resistors on these inputs ensure that they go to the inactive
the fully off condition, the GH or GL output switches from cur- state should they become disconnected from the control signal
rent to voltage drive to hold the MOSFET in the off state. level.
If the values of IF1[3:0] and IF2[3:0] are set to 0, GH or GL Internal lockout logic ensures that the high-side output drive and
produces maximum drive to turn off the MOSFET as quickly low-side output drive cannot be active simultaneously. When the
as possible without attempting to control the MOSFET input control inputs request active high-side and low-side at the same
capacitance discharge time (Figure 7d). The value of TF[3:0] has time, then both high-side and low side gate drives will be forced
no effect on switching speed. low.
Dead time, DT[5:0] in the Config 0 register, must be set to a non- Output Disable
zero value for gate drive control to be operational. Otherwise,
maximum drive will be produced on all switching transitions to The ENABLE input is connected directly to the gate drive output
minimize MOSFET switching times. command signal, bypassing all gate drive control logic. This can
be used to provide a fast output disable (emergency cutoff).

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Sleep Mode The output offset, VOOS, of the sense amplifier is defined by the
contents of the SAO[3:0] variable as:
RESETn is an active-low input which allows the A4927 to enter
sleep mode, in which the current consumption from the VBB sup- SAO VOOS SAO VOOS
ply and internal logic regulator is reduced to its minimum level. 0 0 8 750 mV
When RESETn is held low for longer than the reset shutdown 1 0 9 1V
time, tRSD, the regulator and all internal circuitry is disabled and
2 100 mV 10 1.25 V
the A4927 enters sleep mode. In sleep mode, the latched faults
3 100 mV 11 1.5 V
and corresponding fault flags are cleared. When coming out
of sleep mode, the protection logic ensures that the gate drive 4 200 mV 12 1.75 V
outputs are off until the charge pump reaches its correct operating 5 300 mV 13 2V
condition. The charge pump will stabilize in approximately 2 ms 6 400 mV 14 2.25 V
under nominal conditions. 7 500 mV 15 2.5 V
To allow the A4927 to start up without the need for an external
logic input, the RESETn terminal can be pulled to VBB with an
Diagnostic Monitors
external pull-up resistor. Multiple diagnostic features provide three levels of fault monitor-
ing. These include critical protection for the A4927, monitors for
RESETn can also be used to clear any fault conditions without
operational voltages and states, and detection of the power bridge
entering sleep mode by taking it low for the reset pulse width,
and load fault conditions. All diagnostics, except for POR, serial
tRST. Any latched short detection fault, which disables the out-
transfer error and overtemperature, can be masked by setting the
puts, will be cleared, as will the serial fault register.
appropriate bit in the mask registers.
Current Sense Amplifier
Table 4: Diagnostic Functions
A programmable gain, differential sense amplifier is provided Name Diagnostic Level
to allow the use of low-value sense resistors or current shunt as POR Internal logic supply undervoltage causing Chip
a low-side current sensing element. The input common mode power-on reset
range of the CSP and CSM inputs and programmable output SE Serial transmission error Chip
offset allow below ground current sensing typically required for
OT Chip junction overtemperature Chip
low-side current sense in PWM control of motors, or other induc-
TW High chip junction temperature warning Monitor
tive loads, during switching transients. The output of the sense
amplifier is available at the CSO output and can be used in peak VSO VBB supply overvoltage Monitor
(Load dump detection)
or average current control systems. The output can drive up to
4.8 V to permit maximum dynamic range with higher input volt- VRO VREG output overvoltage Monitor
age A-to-D converters. VRU VREG output undervoltage Monitor
OC Overcurrent Bridge
The gain of the sense amplifier is defined by the contents of the
VBS Bootstrap undervoltage Bridge
SAG[2:0] variable as:
HU High-side VGS undervoltage Bridge
SAG Gain SAG Gain LU Low-side VGS undervoltage Bridge
0 10 4 30 HO High-side VDS overvoltage Bridge
1 15 5 35 LO Low-side VDS overvoltage Bridge
2 20 6 40
The fault status is available from the status and diagnostic regis-
3 25 7 50
ters accessed through the serial interface.

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DIAG Output low supply circumstances, or during power-up or power-down, an

undervoltage detector ensures that the A4927 operates correctly.
The DIAG terminal provides a single diagnostic signal that
The logic supply undervoltage lockout cannot be masked as it
outputs a general logic-level active-low fault flag. DIAG remains
low while any fault except SE or OC is present or if one of the is essential to guarantee correct operation over the full supply
latched faults has been detected and the outputs disabled. When range.
the general fault flag is reset the DIAG output will be high. When power is first applied to the A4927, the internal logic is
Status and Diagnostic Registers prevented from operating, and all gate drive outputs held in the
off state until the internal regulator voltage, VDL, exceeds the
The serial interface allows detailed diagnostic information to be logic supply undervoltage lockout rising (turn-on) threshold,
read from the diagnostic registers on the SDO output terminal at
VDLON. At this point, all serial control registers will be reset to
any time.
their power-on state and all fault states will be reset. The FF bit
A system status register provides a summary of all faults in a and the POR bit in the status register will be set to one to indicate
single read transaction. The status register is always output on that a power-on-reset has taken place. The A4927 then goes into
SDO when any register is written. its fully operational state and begins operating as specified.
The first bit (bit 15) of the status register contains a common fault
Once the A4927 is operational, the internal logic supply continues
flag, FF, which will be high if any of the fault bits in the status
to be monitored. If, during the operational state, VDL drops below
register have been set. This allows fault condition to be detected
using the serial interface by simply taking STRn low. As soon as logic supply undervoltage lockout falling (turn-off) threshold,
STRn goes low the first bit in the status register can be read on VDLOFF, then the logical function of the A4927 cannot be guar-
SDO to determine if a fault has been detected at any time since anteed and the outputs will be immediately disabled. The A4927
the last fault register reset. In all cases the fault bits in the diag- will enter a power-down state and all internal activity, other than
nostic registers are latched and only cleared after a fault register the logic regulator voltage monitor will be suspended. If the logic
reset. supply undervoltage is a transient event, then the A4927 will fol-
FF provides an indication that a fault has occurred since the last low the power-up sequence above as the voltage rises.
fault reset and one or more fault bits have been set.
CHIP FAULT STATE: OVERTEMPERATURE (OT)
Note that FF (bit 15) does not provide the same function as the
If the chip temperature rises above the overtemperature thresh-
general fault flag output on the DIAG terminal. The fault flag
output on the DIAG terminal provides an indication that either a old, TJF, the overtemperature bit, OT, will be set in the status
fault is present or the outputs have been disabled due to a latched register. If ESF = 1 when an overtemperature is detected, all gate
fault state. FF provides an indication that a fault has occurred drive outputs will be disabled automatically. If ESF = 0, then no
since the last fault reset and one or more fault bits have been set. circuitry will be disabled and action must be taken by the user to
limit the power dissipation in some way so as to prevent overtem-
Chip-Level Protection perature damage to the chip and unpredictable device operation.
Chip-wide parameters critical for correct operation of the A4927 When the temperature drops below TJF by more than the hyster-
are monitored. These include maximum chip temperature, esis value, TJFHys, the fault state is cleared, and when ESF = 1,
minimum internal logic supply voltage and the serial interface the outputs are re-enabled. The overtemperature bit remains in
transmission. These three monitors are necessary to ensure that the status register until reset.
the A4927 is able to respond as specified.
CHIP FAULT STATE: SERIAL ERROR (SE)
CHIP FAULT STATE: INTERNAL LOGIC UNDERVOLT-
AGE (POR) If there are more than 16 rising edges on SCK or if STRn goes
high and there are fewer than 16 rising edges on SCK or the
The A4927 has an independent internal logic regulator to supply
the internal logic. This is to ensure that external events, other than parity is not odd, then the write will be cancelled without writing
loss of supply, do not prevent the A4927 from operating correctly. data to the registers and the SE bit will be set to indicate a data
The internal logic supply regulator will continue to operate with a transfer error. If the transfer is a write, then the status register will
low supply voltage, for example, if the main supply voltage drops not be reset. If the transfer is a diagnostic register read, then the
to a very low value during a severe cold crank event. In extreme addressed register will not be reset.

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Operational Monitors MONITOR: TEMPERATURE WARNING (TW)

Parameters related to the safe operation of the A4927 in a system If the chip temperature rises above the temperature warning
are monitored. These include parameters associated with external threshold, TJW, the hot warning bit, TW, will be set in the status
active and passive components, power supplies, and interaction register. No action will be taken by the A4927. When the temper-
with external controllers. ature drops below TJW by more than the hysteresis value, TJWHys,
the fault state is cleared and the TW bit remains in the status
Voltages relating to driving the external power MOSFETs are register until reset.
monitored, specifically VREG, the bootstrap capacitor voltage, and
the VGS of each gate drive output. The main supply voltage, VBB, MONITOR: VBB SUPPLY OVERVOLTAGE (VSO)
is only monitored for overvoltage events. It is not monitored for
If VBB rises above the VBB overvoltage warning threshold,
minimum voltage since the critical minimum voltage is generated
VBBOV, then the VSO bit will be set in the Diagnostic 2 register
by the VREG charge pump regulator provided by the A4927.
and the VS bit will be set in the Status register. The general fault
MONITOR: VREG VOLTAGE (VR: VRO, VRU) flag will be set but all gate drive outputs will continue to func-
tion. When VBB drops below the falling VBB overvoltage warn-
The internal charge-pump regulator supplies the low-side gate ing threshold, VBBOV – VBBOVHys, the general fault flag will be
driver and the bootstrap charge current. It is critical to ensure that cleared but the VSO and VS bits will remain set. The fault state
the regulated voltage, VREG, at the VREG terminal is sufficiently will only be reset by a low pulse on the RESETn input, by a serial
high before enabling any of the outputs. read of the diagnostic or status register or by a power-on reset.
If VREG goes below the VREG undervoltage threshold, VROFF,
the VREG undervoltage bit, VRU, will be set in the diagnostic Power Bridge and Load Faults
register. All gate drive outputs will go low, the motor drive will
BRIDGE: OVERCURRENT DETECT (OC)
be disabled, and the motor will coast. When VREG rises above the
rising threshold, VRUON, the gate drive outputs are re-enabled and The output from the sense amplifier can be compared to an over-
the fault state is cleared. The VRU bit remains in the diagnostic current threshold voltage, VOCT, to provide indication of overcur-
register until cleared. rent events. VOCT, is generated by a 4-bit DAC with a resolution
of 300 mV and defined by the contents of the OC[3:0] variable
The VREG undervoltage monitor circuit is active during power and the contents of the SAO[3:0] variable. VOCT is approximately
up and all gate drives will be low until VREG is greater than defined as:
approximately 8 V(with VRG = 1). Note that this is sufficient to VOCT = [(n + 1) × 300 mV]
turn on standard threshold external power MOSFETs at a battery
voltage as low as 5.5 V, but the on-resistance of the MOSFET where n is a positive integer defined by OCT[3:0]
may be higher than its specified maximum. Any offset programmed on SAO[3:0] is applied to both the cur-
The VREG undervoltage monitor can be disabled by setting the rent sense amplifier output, VCSO, and the Overcurrent threshold,
VRU bit in the mask register. Although not recommended, this VOCT, and has no effect on the overcurrent threshold, IOCT. The
can allow the A4927 to operate below its minimum specified sup- relationship between the threshold voltage and the threshold cur-
ply voltage level with a severely impaired gate drive. The speci- rent is approximately defined as:
fied electrical parameters will not be valid in this condition.
IOCT = VOCT / (RS × AV)
The output of the VREG regulator is also monitored to detect any
where VOCT is the overcurrent threshold voltage programmed by
overvoltage applied to the VREG terminal. If VREG goes above
OCT[3:0], RS is the sense resistor value in Ω and AV is the sense
the VREG overvoltage threshold, VROV, the VREG overvoltage
amp gain defined by SAG[2:0].
bit, VRO, will be set in the diagnostic register. No action will
be taken as the gate drive outputs are protected from overvolt- The output from the overcurrent comparator is filtered by an
age by independent Zener clamps. When VREG falls below VROV overcurrent qualifier circuit. This circuit uses a timer to verify
by more than the hysteresis voltage, VROVHys, the fault state that the output from the comparator is indicating a valid over-
is cleared but VRO bit remains in the diagnostic register until current event. The qualifier can operate in one of two ways,
cleared. debounce or blanking, selected by the OCQ bit.

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In the default debounce mode, a timer is started each time the If there is a fault that prevents the bootstrap capacitor charg-
comparator output indicates an overcurrent. This timer is reset ing during the managed recharge cycle, then the charge cycle
when the comparator changes back to indicate normal operation. will timeout after typically 200 µs and the bootstrap undervolt-
If the debounce timer reaches the end of the timeout period, set age fault is considered to be valid. If the bootstrap manager is
by tOCQ, then the overcurrent event is considered valid and the disabled and a bootstrap undervoltage is detected when a high-
overcurrent bit, OC, will be set in the Diag 2 register. side MOSFET is active or being switched on, then the bootstrap
undervoltage is immediately valid.
In the optional blanking mode, a timer is started when a low-
side gate drive is turned on. The output from the comparator The action taken when a valid bootstrap undervoltage fault is
is ignored (blanked) for the duration of the timeout period, set detected and the fault reset conditions depend on the state of the
by tOCQ. If a comparator output indicates an overcurrent event ESF bit.
when the blanking timer is not active then the overcurrent event
If ESF = 0, the fault state will be latched, the bootstrap under-
is considered valid and the overcurrent bit, OC, will be set in the
voltage fault bit in the status register, VBS, will be set, and the
Diag 2 register.
high-side MOSFET will be disabled. The fault state, but not the
When a valid overcurrent is detected, no action is taken and only bootstrap undervoltage fault bit, will be reset by a low pulse on
the OC bit is set. The fault state will be reset by a low pulse on the RESETn input or the next time the MOSFET is commanded
the RESETn input, by a serial read of the diagnostic or status to switch on. If the MOSFET is being driven with a PWM signal,
register or by a power-on reset. then this will usually mean that the MOSFET will be turned on
again each PWM cycle. If this is the case, and the fault condition
BRIDGE: BOOTSTRAP CAPACITOR UNDERVOLTAGE remains, then a valid fault will again be detected after the timeout
FAULT (VBS) period and the sequence will repeat. The fault state will be reset
The A4927 monitors the bootstrap capacitor charge voltage to by a low pulse on the RESETn input, by a serial read of the diag-
ensure sufficient high-side drive. It also includes an optional nostic or status register or by a power-on reset.
bootstrap capacitor charge management system (bootstrap man- If ESF = 1, the fault will be latched, the associated bootstrap
ager) to ensure that the bootstrap capacitor remains sufficiently undervoltage fault bit will be set, and all MOSFETs will be dis-
charged under all conditions. The bootstrap manager is enabled abled. The fault state will be reset by a low pulse on the RESETn
by default but may be disabled by setting the DBM bit to 1. This input, by a serial read of the diagnostic or status register or by a
may be required in systems where the output MOSFET switching power-on reset.
must only be allowed by the controlling processor.
The bootstrap undervoltage monitor can be disabled by setting
If the bootstrap manager is disabled, then the user must ensure the VBS bit in the mask register. Although not recommended,
that the bootstrap capacitor does not become discharged below this can allow the A4927 to operate below its minimum speci-
the bootstrap undervoltage threshold, VBCUV, or a bootstrap fault fied supply voltage level with a severely impaired gate drive. The
will be indicated and the outputs disabled. This can happen with specified electrical parameters may not be valid in this condition.
very high PWM duty cycles when the charge time for the boot-
strap capacitor is insufficient to ensure a sufficient recharge to BRIDGE: MOSFET VDS OVERVOLTAGE FAULT (DSO:
match the MOSFET gate charge transfer during turn on. HO, LO)
When the bootstrap manager is active, the bootstrap capacitor Faults on the external MOSFETs are determined by monitoring
voltage must be higher than the turn-on voltage limit before a the drain-source voltage of the MOSFET and comparing it to a
high-side drive can be turned on. If this is not the case, then the drain-source overvoltage threshold, VDST. VDST is generated by
A4927 will attempt to charge the bootstrap capacitor by activat- an internal DAC and is defined by the values in the VT[5:0] vari-
ing the low-side drive. Under normal circumstances, this will able. This variable provides the input to a 6-bit DAC with a least
charge the capacitor above the turn-on voltage in a few microsec- significant bit value of typically 50 mV. The output of the DAC
onds and the high-side drive will then be enabled. The boot- produces the threshold voltage approximately defined as:
strap voltage monitor remains active while the high-side drive
is active, and if the voltage drops below the turn-off voltage, a VDST = n × 50 mV
charge cycle is also initiated. where n is a positive integer defined by VT[5:0]

955 Perimeter Road
The drain-source voltage for the low-side MOSFET is measured In the optional blanking mode, a timer is started when a gate
between the S terminal and the LSS terminal. Using the LSS drive is turned on. The output from the VDS overvoltage com-
terminal rather than the ground connection avoids adding any parator for the MOSFET being switched on is ignored (blanked)
low-side current sense voltage to the real low-side drain-source for the duration of the timeout period, set by tVDQ. If the com-
voltage and avoids false VDS fault detection. parator output indicates an overvoltage event when the MOSFET
is switched on and the blanking timer is not active then the VDS
The drain-source voltage for the high-side MOSFET is measured
fault is considered valid and the corresponding VDS fault bit, LO
between the S terminal and the VBRG terminal. Using the VBRG
or HO will be set in the diagnostic register.
terminal rather than VBB avoids adding any reverse diode volt-
age or high-side current sense voltage to the real high-side drain- If a valid VDS fault is detected, the fault will be latched and the
source voltage and avoids false VDS fault detection. associated MOSFET will be disabled. This state will remain until
reset depending on the value set in the ESF bit.
The VBRG terminal is an independent low-current sense input to
the top of the MOSFET bridge. It should be connected indepen- If ESF = 1, the fault state will only be reset by a low pulse on the
dently and directly to the common connection point for the drain RESETn input, by a serial read of the diagnostic register, or by a
of the power bridge MOSFET at the positive supply connection power-on reset.
point in the bridge. The input current to the VBRG terminal is
If ESF = 0, the fault state, but not the VDS fault bit, will be reset
proportional to the drain-source threshold voltage, VDST, and is
the next time the MOSFET is commanded to switch on. If the
approximately:
MOSFET is being driven with a PWM signal, then this will usu-
IVBRG = 72 × VDST + 52 ally mean that the MOSFET will be turned on again each PWM
where IVBRG is the current into the VBRG terminal in µA and cycle. If this is the case, and the fault conditions remains, then a
VDST is the drain-source threshold voltage described above. valid fault will again be detected after the timeout period and the
sequence will repeat. The fault state will be reset by a low pulse
Note that the VBRG terminal can withstand a negative voltage on the RESETn input, by a serial read of the diagnostic register,
up to –5 V. This allows the terminal to remain connected directly or by a power-on reset.
to the top of the power bridge during reverse battery conditions
where the body diodes of the power MOSFETs are used to clamp If ESF = 0, care must be taken to avoid damage to the MOSFET
the negative voltage. where the VDS fault is detected. Although the MOSFET will be
switched off as soon as the fault is detected at the end of the fault
The output from each VDS overvoltage comparator is filtered by validation timeout, it is possible that it could still be damaged by
a VDS fault qualifier circuit. This circuit uses a timer to verify excessive power dissipation and heating. To limit any damage to
that the output from the comparator is indicating a valid VDS the external MOSFETs or the load, the MOSFET should be fully
fault. The duration of the VDS fault qualifying timer, tVDQ, is disabled by logic inputs from the external controller.
determined by the contents of the TVD[5:0] variable. tVDQ is
approximately defined as: BRIDGE: VGS UNDERVOLTAGE (GSU: HU, LU)
tVDQ = n × 100 ns To ensure that the gate drive output is operating correctly, each
where n is a positive integer defined by TVD[5:0]. gate drive output voltage is independently monitored, when
active, to ensure the drive voltage, VGS, is sufficient to fully
The qualifier can operate in one of two ways: debounce mode or enhance the power MOSFET in the external bridge.
blanking mode, selected by the VDQ bit.
If VGS, on any active gate drive output, goes below the gate
In the default debounce mode, a timer is started each time the drive undervoltage warning, VGSUV, the general fault flag will be
comparator output indicates a VDS fault detection when the active and the corresponding gate drive undervoltage bit, HU or
corresponding MOSFET is active. This timer is reset when the LU, will be set in the diagnostic register. No other action will be
comparator changes back to indicate normal operation. If the taken. When VGS rises above VGSUV by more than the hysteresis
debounce timer reaches the end of the timeout period set by tVDQ, voltage, VGSUVHys, the general fault flags go inactive. The fault
then the VDS fault is considered valid and the corresponding bits remain in the diagnostic register until cleared.
VDS fault bit, LO or HO, will be set in the diagnostic register.

955 Perimeter Road
MOSFET FAULT STATE: SHORT TO SUPPLY until the fault is removed. If ESF = 0, then the gate drive outputs
A short from the load connections to the battery or VBB connec- will not be affected.
tion is detected by monitoring the voltage across the low-side If a VDS fault or bootstrap undervoltage fault is detected, then the
MOSFET using the S terminal and the LSS terminal. This drain- action taken will also depend on the status of the ESF bit, but these
source voltage is then compared to the low-side Drain-Source faults are handled as a special case. If a fault is detected on any of
Threshold Voltage, VDSTL. If the blanking timer is active, the these two diagnostics and ESF = 1, then both gate drive outputs
output from the VDS overvoltage comparator will be ignored for will be driven low and both MOSFETs in the bridge will be held
tVDQ. While the low-side VDS fault is detected, the VDS fault in the off state. When ESF = 1, this fault state will be latched and
bit, LO, will be set in the diagnostic register and the low-side remain until reset. If a VDS fault or bootstrap undervoltage fault
MOSFET will be disabled. When ESF is set to 1, both MOSFETs is detected and ESF = 0, then only the gate drive output to the
will be disabled. MOSFET where the fault was detected will be driven low and the
MOSFET will be held in the off state. When ESF = 0, the VDS
MOSFET FAULT STATE: SHORT TO GROUND fault or bootstrap undervoltage fault state will be latched but will
A short from the load connection to ground is detected by be reset the next time the MOSFET is commanded to switch on.
monitoring the voltage across the low-side MOSFET using the S For all other faults, the gate drive outputs will remain enabled.
terminal and the voltage at VBRG. This drain-source voltage is
then compared to the high-side Drain-Source Threshold Volt-
Fault Masks
age, VDSTH. If the blanking timer is active, the output from the Individual diagnostics—except power-on reset, serial transmis-
VDS overvoltage comparator will be ignored for tVDQ. While the sion error, and overtemperature—can be disabled by setting the
low-side VDS fault is detected, the VDS fault bit, HO, will be corresponding bit in the mask register. Power-on-reset cannot be
set in the diagnostic register and the high-side MOSFET will be disabled because the diagnostics and the output control depend
disabled. When ESF is set to 1, both MOSFETs will be disabled. on the logic regulator to operate correctly. If a bit is set to one
in the mask register, then the corresponding diagnostic will be
Fault Action completely disabled. No fault states for the disabled diagnostic
The action taken when one of the diagnostic functions indicates a will be generated and no fault flags or diagnostic bits will be set.
fault is listed in Table 5. See Mask Register definition for bit allocation. Care must be
taken when diagnostics are disabled to avoid potentially damag-
When a fault is detected, a corresponding fault state is consid- ing conditions.
ered to exist. In some cases, the fault state only exists during the
time the fault is detected. In other cases, when the fault is only Table 5: Fault Actions
detected for a short time, the fault state is latched (stored) until Fault Disable Outputs Fault State
reset. The faults that are latched are indicated in Table 5. Latched Description ESF = 0 ESF = 1 Latched
fault states are always reset when RESETn is taken low, a power-
No Fault No No -
on-reset state is present or when the associated fault bit is read
Power-on-Reset Yes [1] Yes [1] No
through the serial interface. Any fault bits that have been set in
the status or diagnostic register are only reset when a power- VREG undervoltage Yes [1] Yes [1] No
on-reset state is present or when the associated fault bit is read VREG overvoltage No No No
through the serial interface. RESETn low will not reset the fault VBB overvoltage No No No
bits in the status or diagnostic registers. Overtemperature No Yes [1] No
The fault conditions power-on-reset and VREG undervoltage Temperature warning No No No
are considered critical to the safe operation of the A4927 and the Serial transmission error No No No
system. If these faults are detected, then the gate drive outputs are Bootstrap undervoltage Yes [2] Yes [1] Yes
automatically driven low and both MOSFETs in the bridge held Overcurrent No No No
in the off state. This state will remain until the fault is removed.
VDS overvoltage Yes [2] Yes [1] Yes
For the logic terminal overvoltage and overtemperature fault VGS undervoltage No No No
conditions, the action taken depends on the status of the ESF bit.
1 Both gate drives low, both MOSFETs off.
If a fault is detected on any of these two diagnostics and ESF = 1, 2 Gate drive to the affected MOSFET low, only the affected MOSFET off.
then all the gate drive outputs will be driven low and all MOS-
FETs in the bridge held in the off state. This state will remain

955 Perimeter Road
SERIAL INTERFACE
Table 6: Serial Register Definition*
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DT5 DT4 DT3 DT2 DT1 DT0

0: Config 0 0 0 0 0 WR P
0 0 0 0 1 0 0 0 0 0
OCT3 OCT2 OCT1 OCT0 VT5 VT4 VT3 VT2 VT1 VT0
1: Config 1 0 0 0 1 WR P
1 0 0 1 0 1 1 0 0 0
VDQ
2: Config 2 0 0 1 0 WR P
0 0 0 0 0 0 0 0 0 0
TVD5 TVD4 TVD3 TVD2 TVD1 TVD0

3: Config 3 0 0 1 1 WR P
0 0 0 0 0 1 0 0 0 0
VRG
4: Config 4 0 1 0 0 WR P
0 0 0 1 0 0 0 0 0 0
SAO3 SAO2 SAO1 SAO0 SAG2 SAG1 SAG0

5: Config 5 0 1 0 1 WR P
0 0 1 1 1 1 0 1 0 1
TR3 TR2 TR1 TR0 TF3 TF2 TF1 TF0

6: Config 6 0 1 1 0 WR P
0 0 0 0 0 1 0 0 0 1
IR13 IR12 IR11 IR10 IF13 IF12 IF11 IF10

7: Config 7 0 1 1 1 WR P
0 0 0 0 0 0 0 0 0 0

8: Config 8 1 0 0 0 WR P
0 0 0 0 0 0 0 0 0 0
VBS TW HU LU
10: Mask 0 1 0 1 0 WR P
0 0 0 0 0 0 0 0 0 0
VRO VRU VSO HO LO

11: Mask 1 1 0 1 1 WR P
0 0 0 0 0 0 0 0 0 0
HU LU
12: Diag 0 1 1 0 0 0 P
0 0 0 0 0 0 0 0 0 0
VRO VRU HO LO
13: Diag 1 1 1 0 1 0 P
0 0 0 0 0 0 0 0 0 0
VSO VBS OC
14: Diag 2 1 1 1 0 0 P
0 0 0 0 0 0 0 0 0 0
*Power-on reset value shown below each input register bit.
Continued on the next page...

955 Perimeter Road
Table 6:Serial Register Definition (continued)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM ESF HSR LSR

15: Control 1 1 1 1 WR P
0 0 0 1 0 0 0 0 0 0
FF POR SE OT TW VS VR OC VBS GSU DSO

Status P
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
*Power-on reset value shown below each input register bit.
A three-wire synchronous serial interface, compatible with SPI, is fifth bit, WR (D[11]), is the write/read bit. When WR is 1, the
used to control the features of the A4927. The SDO terminal can following 10 bits, D[10:1], clocked in from the SDI terminal, are
be used, during a serial transfer, to provide diagnostic feedback written to the addressed register. When WR is 0, then no data is
and readback of the register contents. written to the serial registers and the contents of the addressed
register are clocked out on the SDO terminal.
The A4927 can be operated without the serial interface using the
default settings and the logic control inputs; however, application The last bit in any serial transfer, D[0], is a parity bit (P) that is
specific configurations are only possible by setting the appropri- set to ensure odd parity in the complete 16-bit word. Odd parity
ate register bits through the serial interface. In addition to setting means that the total number of 1s in any transfer should always
the configuration bits, the serial interface can also be used to be an odd number. This ensures that there is always at least one
control the bridge MOSFETs directly. bit set to 1 and one bit set to 0 and allows detection of stuck-at
The serial interface timing requirements are specified in the faults on the serial input and output data connections. The parity
Electrical Characteristics table, and illustrated in Figure 4. Data is bit is not stored but generated on each transfer.
received on the SDI terminal and clocked through a shift register In addition to the addressable registers, a read-only status register
on the rising edge of the clock signal input on the SCK terminal. is output on SDO for all register addresses when WR is set to 1.
STRn is normally held high, and is only brought low to initiate a For all serial transfers, the five bits output on SDO will always be
serial transfer. No data is clocked through the shift register when the first five bits from the status register. Register data is output
STRn is high, allowing multiple slave units to use common SDI on the SDO terminal msb first while STRn is low and changes
and SCK connections. Each slave then requires an independent to the next bit on each falling edge of SCK. The first bit, which
STRn connection. The SDO output assumes a high-impedance is always the FF bit from the status register, is output as soon as
state when STRn is high, allowing a common data readback con- STRn goes low.
nection.
Registers 12, 13, and 14 contain diagnostic fault indicators and
When 16 data bits have been clocked into the shift register, STRn are read only. If the WR bit for these registers is set to 1, then the
must be taken high to latch the data into the selected register. data input through SDI is ignored and the contents of the status
When this occurs, the internal control circuits act on the new data register is clocked out on the SDO terminal then reset as for a
and the registers are reset depending on the type of transfer. normal write. No other action is taken. If the WR bit for these
If there are more than 16 rising edges on SCK or if STRn goes registers is set to 0, then the data input through SDI is ignored
high and there are fewer than 16 rising edges on SCK—either and the contents of the addressed register is clocked out on the
being described as a framing error—the write will be cancelled SDO terminal and the addressed register is reset.
without latching data to the register. The Status register will not
If a framing or parity error is detected, the SE bit is set in the
be reset.
Status register to indicate a data transfer error. This fault condi-
The first four bits, D[15:12], in a serial word, are the register tion can be cleared by a subsequent valid serial write or by a
address bits giving the possibility of 16 register addresses. The power-on-reset.

955 Perimeter Road
Configuration Registers Config 8: Gate drive current setting:
Nine registers are used to configure the operating parameters of • IR2[3:0] , a 4-bit integer to set the MOSFET turn-on I2 Current
the A4927. in 4.5 mA increments.
Config 0: Bridge timing settings: • IF2[3:0] , a 4-bit integer to set the MOSFET turn-off I2 Current
• DT[5:0], a 6-bit integer to set the dead time, tDEAD, in 50 ns in 5.3 mA increments.
increments.
Diagnostic Registers
Config 1: Bridge monitor setting: In addition to the read-only status register, five registers provide
• OCT[3:0], a 4-bit integer to set the overcurrent threshold volt- detailed diagnostic management and reporting. Two mask register
age, VOCT, in 300 mV increments. allow individual diagnostics to be disabled and three read-only
diagnostic registers provide fault bits for individual diagnostic tests
• VT[5:0], a 6-bit integer to set the drain-source threshold volt- and monitors. If a bit is set to one in the mask register, then the cor-
age, VDST, in 50 mV increments. responding diagnostic will be completely disabled. No fault states
for the disabled diagnostic will be generated and no fault flags or
Config 2: Bridge monitor setting: diagnostic bits will be set. These bits in the diagnostic registers are
• OCQ, selects the overcurrent qualifier mode, blank or debounce. reset on completion of a successful read of the register.
Mask 0:
• VDQ, selects the VDS qualifier mode, blank or debounce.
Individual bits to disable bootstrap (VBS), temperature warning
Config 3: Bridge monitor setting: (TW), and the VGS undervoltage diagnostic monitors (HU and
• TVD[5:0], a 6-bit integer to set the VDS fault verification time, LU).
tVDQ, in 100 ns increments. Mask 1:
Config 4: Regulator configuration: Individual bits to disable the voltage regulator (VRO, VRU and
VSO) and the VDS overvoltage diagnostic monitors (HO and
• VRG, selects the regulator and gate drive voltage. LO).
Config 5: Sense amplifier setting: Diagnostic 0 (read only):
• SAO[3:0], a 4-bit integer to set the sense amplifier offset up Individual bits indicating faults detected in VGS diagnostic moni-
between 0 and 2.5 V. tors (HU and LU).
• SAG[2:0], a 3-bit integer to set the sense amplifier gain between Diagnostic 1 (read only):
10 and 50 V/V. Individual bits indicating faults detected in voltage regulator
(VRO and VRU) and VDS overvoltage diagnostic monitors (HO
Config 6: Gate drive time setting:
and LO).
• TR[3:0], a 4-bit integer to set the high-side and low-side I1 time Diagnostic 2 (read only):
in 50 ns increments.
Individual bits indicating faults detected in the VBB supply volt-
• TF[3:0], a 4-bit integer to set the high-side and low-side I1 time age and overcurrent (VBS and OC).
in 50 ns increments.
Control Register
Config 7: Gate drive current setting:
The Control register contains one control bit for each MOSFET
• IR1[3:0] , a 4-bit integer to set the MOSFET turn-on I1 Current and some system function settings:
in 4.5 mA increments.
• DBM, disabled bootstrap management function.
• IF1[3:0] , a 4-bit integer to set the MOSFET turn-off I1 Current • ESF, defines the action taken when a short is detected. See
in 5.3 mA increments. diagnostics section for details of fault actions.
• HSR and LSR, MOSFET Control bits.

955 Perimeter Road
Status Register provide indicators for specific individual monitors and the
remaining bits are derived from the contents of the three diagnos-
There is one status register in addition to the 16 addressable tic registers. The contents and mapping to the diagnostic registers
registers. When any register transfer takes place, the first five is listed in Table 7.
bits output on SDO are always the most significant five bits of
the status register regardless of whether the addressed register is The first most significant bit in the register is the diagnostic status
being read or written. (see serial timing diagram). flag, FF. This is high if any bits in the status register are set.
When STRn goes low to start a serial write, the SDO outputs the
The content of the remaining eleven bits will depend on the state
diagnostic status flag. This allows the main controller to poll the
of the WR bit input on SDI. When WR is 1, the addressed register
A4927 through the serial interface to determine if a fault has been
will be written and the remaining eleven bits output on SDO will
detected. If no faults have been detected, then the serial transfer
be the least significant ten bits of the status register followed by a
may be terminated without generating a serial read fault by ensur-
parity bit. When WR is 0, the addressed register will be read and
the remaining eleven bits will be the contents of the addressed ing that SCK remains high while STRn is low. When STRn goes
register followed by a parity bit. high, the transfer will be terminated and SDO will go into its high-
impedance state.
The read-only status register provides a summary of the chip sta-
tus by indicating if any diagnostic monitors have detected a fault. The second most significant bit is the POR bit. At power-up or
The most significant three bits of the status register (FF, POR, after a power-on-reset, the FF bit and the POR bit are set, indi-
and SE) indicate critical system faults. Bits OT and TW provide cating to the external controller that a power-on-reset has taken
indicators for specific individual monitors and the remaining bits place. All other diagnostic bits are reset and all other registers are
are derived from the contents of the three diagnostic registers. returned to their default state. Note that a power-on-reset only
The contents and mapping to the diagnostic registers are listed in occurs when the output of the internal logic regulator rises above
Table 7. its undervoltage threshold. Power-on-reset is not affected by the
state of the VBB supply or the VREG regulator output. In general,
Table 7: Status Register Mapping the VR and VRU bits will also be set following a power-on-reset
Status as the regulators will not have reached their respective rising
Register Related Diagnostic undervoltage thresholds until after the register reset is completed.
Bit Diagnostic Register Bits
FF Status Flag None The third bit in the status register is the SE bit, which indicates
that the previous serial transfer was not completed successfully.
POR Power-on-reset None
SE Serial Error None Bits OT and TW are the fault bits for the two temperature moni-
OT Overtemperature None tors. If one or more of these faults are no longer present, then the
TW Temperature warning None
corresponding fault bits will be reset following a successful read
of the status register. Resetting only affects latched fault bits for
VS VBB Monitor VSO
faults that are no longer present. For any static faults that are still
VR VREG monitor VRU, VRO
present, for example overtemperature, the fault flag will remain
OC Overcurrent OC set after the reset.
VBS Bootstrap UV VBS
The remaining bits, VS, VR, OC, VBS, GSU, and DSO are all
GSU VGS UV HU, LU
derived from the contents of the diagnostic registers. These bits
DSO VDS OV HO, LO
are only cleared when the corresponding contents of the diagnos-
UV = Undervoltage, OV = Overvoltage tic are read and reset, they cannot be reset by reading the status
The read-only status register provides a summary of the chip register. A fault indicated on any of the related diagnostic register
status by indicating if any diagnostic monitors have detected a bits will set the corresponding status bit to 1. The related diagnos-
fault. The most significant three bits of the status register (FF, tic register must then be read to determine the exact fault and clear
POR, and SE) indicate critical system faults. Bits OT and TW the fault state if the fault condition has cleared.

955 Perimeter Road
SERIAL REGISTER REFERENCE

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DT5 DT4 DT3 DT2 DT1 DT0

0: Config 0 0 0 0 0 WR P
0 0 0 0 1 0 0 0 0 0
OCT3 OCT2 OCT1 OCT0 VT5 VT4 VT3 VT2 VT1 VT0
1: Config 1 0 0 0 1 WR P
1 0 0 1 0 1 1 0 0 0
OCQ VDQ
2: Config 2 0 0 1 0 WR P
0 0 0 0 0 0 0 0 0 0
TVD5 TVD4 TVD3 TVD2 TVD1 TVD0

3: Config 3 0 0 1 1 WR P
0 0 0 0 0 1 0 0 0 0
VRG
4: Config 4 0 1 0 0 WR P
0 0 0 1 0 0 0 0 0 0
Config 0 Config 2
DT[5:0] Dead time. OCQ Overcurrent time qualifier mode.

tDEAD = n × 50 ns OCQ Qualifier Default
0 Debounce D
where n is a positive integer defined by 1 Blank
DT[5:0],
e.g. for the power-on-reset condition
VDQ VDS Fault qualifier mode.
DT[5:0] = [10 0000] then tDEAD = 1.6 µs.
VDQ VDS Fault Qualifier Default
The range of tDEAD is 100 ns to 3.15 µs.
0 Debounce D
Selecting a value of 1 or 2 will set the
1 Blank
dead time to 100 ns. A value of zero
disables the dead time.
Config 3
Config 1
TVD[5:0] VDS verification time.
OCT[3:0] Overcurrent threshold.
tVDQ = n × 100 ns
VOCT = (n + 1) × 300 mV where n is a positive integer defined by TVD[5:0],
where n is a positive integer defined by OCT[3:0] e.g. for the power-on-reset condition.
e.g. for the power-on-reset condition TVD[5:0] = [01 0000] then tVDQ = 1.6 µs.
OCT[3:0] = [1001] then VOCT = 3 V. The range of tVDQ is 0 to 6.3 µs.
The range of VOCT is 0.3 to 4.8 V.
Config 4
VT[5:0] VDS overvoltage threshold.
VRG VREG Voltage Level.
VDST = n × 50 mV VRG VREG Voltage Default
where n is a positive integer defined by VT[5:0], 0 8V
e.g. for the power-on-reset condition 1 11 V D
VT[5:0] = [01 1000] then VDST = 1.2 V.
The range of VDST is 0 to 3.15 V.

955 Perimeter Road
SERIAL REGISTER REFERENCE (continued)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAO3 SAO2 SAO1 SAO0 SAG2 SAG1 SAG0

5:Config 5 0 1 0 1 WR P
0 0 1 1 1 1 0 1 0 1
Config 2
SAO[3:0] Sense Amp Offset. SAG[2:0] Sense Amp Offset.

Where SAO is a positive integer defined by SAO[3:0]. Where SAG is a positive integer defined by SAG[2:0].
SAO Offset Default SAG Gain Default
0 0 mV 0 10
1 0 mV 1 15
2 100 mV 2 20
3 100 mV 3 25
4 200 mV 4 30
5 300 mV 5 35 D
6 400 mV 6 40
7 500 mV 7 50
8 750 mV
9 1.0 V
10 1.25 V
11 1.5 V
12 1.75 V
13 2.0 V
14 2.25 V
15 2.5 V D

955 Perimeter Road

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TR3 TR2 TR1 TR0 TF3 TF2 TF1 TF0

6: Config 6 0 1 1 0 WR P
0 0 0 0 0 1 0 0 0 1

7: Config 7 0 1 1 1 WR P
0 0 0 0 0 0 0 0 0 0

8: Config 8 1 0 0 0 WR P
0 0 0 0 0 0 0 0 0 0
Config 6 Config 8
TR[3:0] MOSFET turn-on t1 time. IR2[3:0] MOSFET turn-on I2 Current.
t1 = (n + 1) × 50 ns I2 = n × –4.5 mA
where n is a positive integer defined by TR[3:0], where n is a positive integer defined by IR2[3:0],
e.g. if TR[3:0] = [0001] then t1 = 100 ns. e.g. if IR2[3:0] = [1000] then I2 = –36 mA.
The range of t1 is 50 to 800 ns. The range of I2 is –4.5 to –67.5 mA.
Selecting a value of 0 will set maximum gate drive to
turn on the MOSFET as quickly as possible.
TF[3:0] MOSFET turn-off t1 time.
t1 = (n + 1) × 50 ns
IF2[3:0] MOSFET turn-off I2 Current.
where n is a positive integer defined by TF[3:0],
e.g. for the power-on-reset condition I2 = n × 5.3 mA
TF[3:0] = [0001] then t1 = 100 ns. where n is a positive integer defined by IF2[3:0],
The range of t1 is 50 to 800 ns. e.g. if IF2[3:0] = [1000] then I2 = 42.4 mA.
The range of I2 is 5.3 to 79.5 mA.
Config 7 Selecting a value of 0 will set maximum gate drive to
IR1[3:0] MOSFET turn-on I1 Current.
I1 = n × –4.5 mA
where n is a positive integer defined by IR1[3:0],
e.g. if IR1[3:0] = [1000] then I1 = –36 mA
The range of I1 is –4.5 mA to –67.5 mA.
IF1[3:0] MOSFET turn-off I1 Current.

I1 = n × 5.3 mA
where n is a positive integer defined by IF1[3:0],
e.g. if IF1[3:0] = [1000] then I1 = 42.4 mA.
The range of I1 is 5.3 to 79.5 mA.

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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VBS TW HU LU
10: Mask 0 1 0 1 0 WR P
0 0 0 0 0 0 0 0 0 0
VRO VRU VSO HO LO

11: Mask 1 1 0 1 1 WR P
0 0 0 0 0 0 0 0 0 0
Mask 0 Mask 1
VBS Bootstrap Undervoltage VRO VREG Overvoltage

TW Temperature Warning VRU VREG Undervoltage
HU High-Side VGS Undervoltage VSO VBB Overvoltage
LU Low-Side VGS Undervoltage HO High-Side VDS Overvoltage
LO Low-Side VDS Overvoltage
xxx Fault Mask Default
0 Fault detection permitted D
1 Fault detection disabled

955 Perimeter Road

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HU LU
12: Diag 0 1 1 0 0 0 P
0 0 0 0 0 0 0 0 0 0
VRO VRU HO LO
13: Diag 1 1 1 0 1 0 P
0 0 0 0 0 0 0 0 0 0
VSO VBS OC
14: Diag 2 1 1 1 0 0 P
0 0 0 0 0 0 0 0 0 0
FF POR SE OT TW VS VR OC VBS GSU DSO

Status P
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Diag 0 (read only) Status (read only)
HU High-Side VGS Undervoltage FF Diagnostic Register Flag

LU Low-Side VGS Undervoltage POR Power-On-Reset
Diag 1 (read only)

SE Serial Error
OT Overtemperature
VRO VREG Overvoltage
TW High Temperature Warning
VRU VREG Undervoltage
VS VBB Fault
HO High-Side VDS Overvoltage
VR VREG Out of Range
LO Low-Side VDS Overvoltage
OC Overcurrent
Diag 2 (read only) VBS Bootstrap Undervoltage
VSO VBB Overvoltage GSU VGS Undervoltage
VBS Bootstrap Undervoltage DSO VDS Overvoltage
OC Overcurrent on sense amp
xxx Status
0 No fault detected
xxx Status 1 Fault detected
0 No fault detected
1 Fault detected Status Register Bit Mapping
Status Related Diagnostic
Register Bit Register Bits
FF None
POR None
SE None
OT None
TW None
VS VSO
VR VRU, VRO
OC OC
VBS VBS
GSU HU, LU
DSO HO, LO
U = Undervoltage, O = Overvoltage

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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM ESF HSR LSR

15: Control 1 1 1 1 WR P
0 0 0 1 0 0 0 0 0 0
Control
DBM
DBM Bootstrap manager Default
0 Active D
1 Disabled
ESF Enable Stop on Fail.

ESF Recirculation Default
0 No stop on fail. Report fault.
1 Stop on fail. Report fault. D
HSR High-side gate drive

LSR Low-side gate drive
See Table 2 and Table 3 for control logic operation.

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APPLICATION INFORMATION
Dead-Time Selection in the bootstrap capacitor, QBOOT, should be much larger than
QGATE, the charge required by the gate:
The choice of power MOSFET and external series gate resistance
determines the selection of the dead time. The dead time, tDEAD, QBOOT >> QGATE
should be made long enough to ensure that one MOSFET has A factor of 20 is a reasonable value, so
stopped conducting before the complementary MOSFET starts
conducting. This should also account for the tolerance and varia- QBOOT = CBOOT × VBOOT = QGATE × 20
tion of the MOSFET gate capacitance, the series gate resistance or
and the on-resistance of the driver in the A4927.
CBOOT = QGATE × 20
VGHA-VSA VBOOT
VGLA

where VBOOT is the voltage across the bootstrap capacitor.
tDEAD
VGSL The voltage drop, ∆V, across the bootstrap capacitor as the MOS-
FET is being turned on, can be approximated by:
QGATE
∆V =
CBOOT
Vt0
VGSH so for a factor of 20, ∆V will be 5% of VBOOT.
Figure 8: Minimum Dead Time The maximum voltage across the bootstrap capacitor under
normal operating conditions is VREG (max). However in some
Figure 8 shows the typical switching characteristics of a pair of circumstances the voltage may transiently reach a maximum of
complementary MOSFETs. Ideally, one MOSFET should start to 18 V, which is the clamp voltage of the Zener diode between the
turn on just after the other has completely turned off. The point at C terminal and the S terminal. In most applications with a good
which a MOSFET starts to conduct is the threshold voltage Vt0. ceramic capacitor, the working voltage can be limited to 16 V.
The dead time should be long enough to ensure that the gate-
source voltage of the MOSFET that is switching off is just below
Vt0 before the gate-source voltage of the MOSFET that is switch- Bootstrap Charging
ing on rises to Vt0. This will be the minimum theoretical dead
It is good practice to ensure the high-side bootstrap capacitor is
time, but in practice the dead time will have to be longer than this
completely charged before a high-side PWM cycle is requested.
to accommodate variations in MOSFET and driver parameters for
The time required to charge the capacitor, tCHARGE , in µs, is
process variations and overtemperature.
approximated by:
Bootstrap Capacitor Selection tCHARGE =

CBOOT × ∆V
100
The A4927 requires a bootstrap capacitor C. To simplify this
description of the bootstrap capacitor selection criteria, generic
where CBOOT is the value of the bootstrap capacitor in nF and ∆V
naming is used here. So, for example, CBOOT, QBOOT, and VBOOT
is the required voltage of the bootstrap capacitor. At power up and
refer to the bootstrap capacitor, and QGATE refers to any of the
when the drivers have been disabled for a long time, the bootstrap
two associated MOSFETs. CBOOT must be correctly selected to
capacitor can be completely discharged. In this case, ∆V can be
ensure proper operation of the device—too large and time will be
considered to be the full high-side drive voltage, 12 V. Otherwise,
wasted charging the capacitor, resulting in a limit on the maxi-
∆V is the amount of voltage dropped during the charge transfer,
mum duty cycle and PWM frequency; too small and there can
which should be 400 mV or less. The capacitor is charged when-
be a large voltage drop at the time the charge is transferred from
ever the S terminal is pulled low and current flows from the capaci-
CBOOT to the MOSFET gate.
tor connected to the VREG terminal through the internal bootstrap
To keep the voltage drop due to charge sharing small, the charge diode circuit to CBOOT.

955 Perimeter Road
VREG Capacitor Selection voltage, VID is given by:

The internal reference, VREG, supplies current for the low-side VID = VCSP – VCSM = IPH × RS
gate-drive circuits and the charging current for the bootstrap The current sense amplifier’s output voltage on CSxO with
capacitors. When a low-side MOSFET is turned on, the gate- respect to the programmed value of output offset on OOS is:
drive circuit will provide the high transient current to the gate that
is necessary to turn the MOSFET on quickly. This current, which VCSD = (VCSP – VCSM) × AV
can be several hundred milliamperes, cannot be provided directly The absolute voltage on CSxO with respect to ground is there-
by the limited output of the VREG regulator but must be supplied fore:
by an external capacitor, CREG, connected between the VREG VCSO = [(VCSP – VCSM) × AV] + VOOS
terminal and GND
If, for example, the following parameter values are assumed:
The turn-on current for the high-side MOSFET is similar in value
but is mainly supplied by the bootstrap capacitor. However, the • RS = 1 mΩ
bootstrap capacitor must then be recharged from CREG through • IPH = –20A to +40A
the VREG terminal. Unfortunately, the bootstrap recharge can
occur a very short time after the low-side turn on occurs. This • AV = 20 (SAG[2:0] = 0b010)
means that the value of CREG between VREG and GND should • VOOS = 1 V (SAO[3:0] = 0b1001)
be high enough to minimize the transient voltage drop on VID ranges between –20 mV and +40 mV and VCSO between
VREG for the combination of a low-side MOSFET turn on and 0.6 V and 1.8 V. VCSO remains within the amplifier dynamic
a bootstrap capacitor recharge. For block commutation control range, VCSOUT, of 0.3 V to 4.8 V. However, if AV is increased
(trapezoidal drive), where only one high side and one low side to 50, VCSO attempts to drive to 0 V and 3.0 V, the amplifier
are switching during each PWM period, a minimum value of 20 × dynamic range limits are not complied with, and the amplifier
CBOOT is reasonable. For sinusoidal control schemes, a minimum output saturates at its negative limit. This situation could be rem-
value of 40 × CBOOT is recommended. As the maximum work- edied by reducing AV to 30 (0.4 V < VCSO < 2.2 V) or increasing
ing voltage of CREG will never exceed VREG, the part’s voltage VOOS to 1.5 V (0.5 V < VCSO < 3.5 V).
rating can be as low as 15 V. However, it is recommended that
a capacitor rated to at least twice the maximum working volt- Current Sense Amplifier Output Signals
age should be used to reduce any impact operating voltage may
As defined in Figure 1, the current sense amplifier output signals
have on capacitance value. For best performance, CREG should be
on the CSO pins are internally referenced to the voltage on the
ceramic rather than electrolytic. CREG should be mounted as close
OOS pin. Consequently, the signal voltages on CSO should be
to the VREG terminal as possible.
measured differentially with respect to OOS (VCSD). Alterna-
Current Sense Amplifier Configuration tively, the voltages on both CSO (VCSO) and OOS (VOOS) may
be measured consecutively with respect to ground and the values
Amplifier gain, AV, and output offset zero point voltage, VOOS, subtracted to give the required output signal voltages as VCSD =
may be set to a range of values by the SAG[2:0] and SAO[3:0] VCSO – VOOS.
variables respectively as defined in the Current Sense Ampli-
fiers section above. It is important that both values are selected The Input Offset Voltage, VIOS, and the associated drift, ΔVIOS,
to ensure the absolute voltage at the CSO output, VCSO, remains multiplied by the selected amplifier gain, AV, represent the offset
within the amplifier’s dynamic range, VCSOUT, and the dynamic and offset drift limits that apply to VCSD. The Output Offset
range of any downstream signal processing circuitry. Allowance Error, EVO, and Output Offset Drift, VOOSD, limits apply directly
must be made for both positive and negative current flows within to VOOS. EVO and VOOSD do not affect current sense output
the sense resistor. accuracy.
With reference to Figure 1, the relationship between phase cur-
rent IPH, sense resistor value, RS, and differential amplifier input

955 Perimeter Road
INPUT/OUTPUT STRUCTURES
16 V
GH
56 V
VBRG
VBB CP1 CP2 VREG DL
S
6V
VREG
7.5 V
16 V 16 V 56 V 6V
56 V 20 V
GL
16 V
LSS
Figure 9a: Gate Drive Outputs Figure 9b: Supplies
VDL VDL VDL
50 kΩ BIAS
2 kΩ 2 kΩ RESETn 2 kΩ
SDI ENABLE
STRn
SCK HS
50 kΩ
50 kΩ
7.5 V 6V 7.5 V 6V 56 V
Figure 9c: SDI, SCK Inputs Figure 9d: STRn Inputs Figure 9e: RESETn, ENABLE, HS Inputs
VDL VDL
BIAS
170 kΩ
50 Ω 25 Ω LSn 2 kΩ
SDO DIAG
7.5 V 56 V 56 V
Figure 9f: SDO Output Figure 9g: DIAG Output Figure 9h: LSn Input
6V
CSM CSO
OOS
CSP
6V
7.5 V 7.5 V
Figure 9i: CSM, CSP Inputs Figure 9j: CSO, OOS Outputs

955 Perimeter Road
LAYOUT RECOMMENDATIONS
Careful consideration must be given to PCB layout when design- GND as close to the A4927 terminals as possible.
ing high-frequency, fast-switching, high-current circuits: • Check the peak voltage excursion of the transients on the
• The exposed thermal pad should be connected to the GND LSS terminals with reference to the GND terminal using a
terminal. close-grounded (“tip & barrel”) probe. If the voltage at any
• Minimize stray inductance by using short, wide copper tracks LSS terminal exceeds the absolute maximum in the datasheet,
at the drain and source terminals of all power MOSFETs. This add additional clamping and/or capacitance between the LSS
includes load lead connections, the input power bus.This will terminal and the GND terminal.
minimize voltages induced by fast switching of large load • Gate charge drive paths and gate discharge return paths may
currents. carry a large transient current pulse. Therefore, the traces from
• Consider the addition of small (100 nF) ceramic decoupling GH, GL, S, and LSS should be as short as possible to reduce
capacitor across the source and drain of the power MOSFETs the trace inductance.
to limit fast transient voltage spikes caused by track • Provide an independent connection between the LSS terminal
inductance. to the source of the low-side MOSFET in the power bridge.
• Keep the gate discharge return connections S and LSS as short Connection of the LSS terminal directly to the GND terminal
as possible. Any inductance on these tracks will cause negative is not recommended as this may inject noise into sensitive
transitions on the corresponding A4927 terminals, which may functions such as the various voltage monitors.
exceed the absolute maximum ratings. If this is likely, consider • A low-cost diode can be placed in the connection to VBB
the use of clamping diodes to limit the negative excursion on to provide reverse battery protection. In reverse battery
these terminals with respect to the GND terminal. conditions, it is possible to use the body diodes of the power
• Supply decoupling, typically a 100 nF ceramic capacitor, MOSFETs to clamp the reverse voltage to approximately
should be connected between VBB and GND as close to the 4 V. In this case, the additional diode in the VBB connection
A4927 terminals as possible. will prevent damage to the A4927 and the VBRG input will
survive the reverse voltage.
• Supply decoupling should be connected between VREG and
Optional reverse
battery protection
VBB VBRG
+ Supply
VREG
GH
S Load
A4927
GL
LSS
Supply
GND PAD Common
Controller Supply Ground

Power Ground
Figure 10: Supply Routing Suggestions

955 Perimeter Road
PACKAGE OUTLINE DRAWING
For Reference Only – Not for Tooling Use

(Reference MO-153 ADT)
NOT TO SCALE
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
7.80 ±0.10
4.32 NOM 8º
0º
24
0.20
0.09
B
3 NOM 4.40±0.10 6.40±0.20
0.60 ±0.15 1.00 REF

1 2
0.25 BSC
24X C SEATING PLANE

1.20 MAX GAUGE PLANE
0.10 C SEATING
PLANE
0.30
0.65 BSC
0.19 0.15
0.00
0.45 0.65
1.65
A Terminal #1 mark area
B Exposed thermal pad (bottom surface); dimensions may vary with device
C Reference land pattern layout (reference IPC7351 TSOP65P640X120-25M);
all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
3.00 6.10 mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
4.32
C PCB Layout Reference View
Figure 11: Package LP, 24-Lead TSSOP with Exposed Pad

955 Perimeter Road
Revision History
Number Date Description
– April 11, 2017 Initial release
1 April 24, 2017 Added DIAG Output section and updated Status and Diagnostic Registers section (page 20).
2 February 11, 2019 Minor editorial updates
Copyright ©2019, Allegro MicroSystems, LLC

Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:


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Datasheet A4927

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A4927

Automotive Half-Bridge MOSFET Driver

FEATURES AND BENEFITS DESCRIPTION

ECU A4927 Load

Figure 1: Typical Application

A4927-DS, Rev. 2 February 11, 2019

ABSOLUTE MAXIMUM RATINGS [1]

THERMAL CHARACTERISTICS: May require derating at maximum conditions

2 Additional thermal information available on the Allegro website.

Allegro MicroSystems, LLC 2

Allegro MicroSystems, LLC 3

PINOUT DIAGRAM AND TERMINAL LIST TABLE

24-Lead eTSSOP (suffix LP)

Terminal List Table

Allegro MicroSystems, LLC 4

Figure 2: Functional Block Diagram

Allegro MicroSystems, LLC 5

Continued on the next page…

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Continued on the next page…

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Continued on the next page…

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Continued on the next page…

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Allegro MicroSystems, LLC 10

VCSO = [(VCSP + VCSM) × AV] + VOOS

Figure 3: Sense Amplifier Voltage Definitions

SDI X D15 X D14 X X D0 X

Figure 4: Serial Interface Timing (X = don’t care, Z = high impedance (tri-state))

tDEAD tP(off) tP(on) tP(off)

tP(off) tDEAD tP(on) tP(off)

Figure 5: Gate Drive Timing – Control Inputs

Allegro MicroSystems, LLC 11

MOSFET turn on MOSFET turn on MOSFET on MOSFET on

Figure 6a: VDS Fault Monitor – Blank Mode Timing (VDQ = 1)

MOSFET turn on MOSFET turn on MOSFET on MOSFET on

tVDQ tVDQ tVDQ tVDQ

Figure 6b: VDS Fault Monitor – Debounce Mode Timing (VDQ = 0)

Allegro MicroSystems, LLC 12

LOGIC TRUTH TABLES

Table 2: Control Logic (Control by Serial Register)

Allegro MicroSystems, LLC 13

Allegro MicroSystems, LLC 14

Power Supplies Bootstrap Supply

Allegro MicroSystems, LLC 15

Allegro MicroSystems, LLC 16

Dead Time Gate Drive

pair of MOSFETs is switched at the same time, for example, at

The accuracy of tDEAD is determined by the accuracy of the

by, for example, the microcontroller producing the drive signals

The internally generated dead time is only present if the on com-

Allegro MicroSystems, LLC 17

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Allegro MicroSystems, LLC 19

DIAG Output low supply circumstances, or during power-up or power-down, an

Allegro MicroSystems, LLC 20

Operational Monitors MONITOR: TEMPERATURE WARNING (TW)

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