HighSpeed Electronics

SI/PI and EMC/EMI Simulation Workflows
for High-Speed Electronics

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Outline
Power Integrity
Signal Integrity
Radiated Emission Workflow
Cable Simulation

SI/PI Applications
SI/PI Workflows
Pre-layout Post-layout
analysis analysis
Signal Integrity and

Signal Integrity
Timing analysis
Power Integrity,
Decap optimization,
SSO

Pre-Layout Analysis: CST Via Wizard
Establish design
constraints
Quick answers
Design layout
to “what if”
variations
questions
Parameter  Macro enabled

sweep and/or
 Spreadsheet based
optimization
 High flexibility
 Full parameterization Examples:
 staggered vias
 Automatic port definition  differential vias
 buried vias
Pre-Layout Example: PCB Breakout Routing
Single Trace Breakout Dual Trace Breakout
Four layers are required to fully route all the TX and RX Both the signal and its complement in the
transceiver signals (increased cost), because only one differential pair are routed between the BGA
trace is routed between the BGA field per layer field and uses two routing layers. Trace neck-
down required in the BGA field to meet the
*Images courtesy of Altera Corporation
copper-to-copper clearance requirement.
Pre-Layout Example: PCB Breakout Routing
Single breakout Dual breakout
 Data rates of interest 10 – 28 Gbps (Nyquist freq 5 – 14 GHz)

 Dual trace topology provides better common mode noise rejection and crosstalk immunity
Unified EDA Import
CST Microwave Studio
CST PCB Studio
Generic Exchange Formats:

 Multilayer Gerber
 DXF
 GDSII
Importance of PDN Design
Ensure clean supply
Power
Delivery Signal Integrity
Network
(PDN)
EMC Limits

PDN Characterization
Bulk caps MB Active
caps device
VRM
Power net
Ground net
Mounting Plane Active device
inductance inductance Via inductance
 DC IR-Drop
 Partial Inductance
 AC PI Analysis
 Decap Analysis Tool
 SSO Analysis
 PCB+Pckg+Chip Courtesy of SIEMENS

Board Description
 8 metal layer board with

total thickness of 66.77mils II I
 1.8V power plane to be 70mm

analyzed located in Layer 4 Mem.
Ctrl
 1 memory controller and

2 DDR2 memory modules
130mm
Courtesy of SIEMENS
IR-Drop Simulation
1.8V 19 CPU pins, 16 Mem I pins & 16 Mem II pins
VDD Drop GND Drop DC @ 20mA
Component Voltage (V)
(V) (V) Resistance
Memory
controller 1.78849 10.507m 1.007m 575mOhm
Group
Memory
Module I 1.7889 10m 0.969m 498mOhm
Group
Memory
Module II 1.789 9.409m 0.929m 469mOhm II I
Group
Mem.
Ctrl
JEDEC 79-2F

PDN Impedance of 1.8V Net
 3 PDN Impedances are plotted
from three different components:
 D1 the memory controller
 D3 and D4 the memory modules
 The total impedance of each
component is calculated by
grouping the power pins together,
which is equivalent to:
1
Z total  N
, N  number of power pins
1

i 1 Z i

Impedance Measurement
Goals: GND pins

 Very small layout area
for probing (2mm²)
 High frequency PWR pins
measurement (up to 10GHz)

Model to Hardware Correlation
Measurement of bareboard Measurement with mounted decaps

Spatial Impedance Plot
Impedance plot on P1V8 plane Impedance plot on P1V8 plane Impedance plot on P1V8 plane
seen from memory controller seen from memory module I seen from memory module II
@2.6GHz

Decap Placement
220pF
Decaps can be manually placed

at resonance locations to
reduce impedance
SSO Analysis for 2 DQ lines
VRM
2 I/O
Buffer:
Driver
11010101101…
2 I/O
Buffer:
Input
 DDR2-400 I/O Buffer IBIS

 PRBS N=7

Transient Response
Power Supply VDD
DC Drop during
write mode
With Decaps No Decaps

Decap Analysis Tool
Over designing the PCB  Additional BOM cost  Little to
no performance improvement
Define the target impedance
Multiple goals:
Define the list of parts for
 Optimizing the BOM cost
optimization
 Optimizing the PDN impedance
Start the optimization

Decap Analysis Demo

Decap Analysis Tool – Results
Impedance curve
after optimization
Before: 76¢
After : 33¢

Transient Simulation Schematic
Maximum voltage overshoot:

 Before: 1.8961VAfter: 1.8906V
Number of components:
 Before: 23  After: 23 56% Save 43¢
Summary
Frequency Domain Analysis
• Quick and less computational effort
• Optimization via Decap Tool analysis
• No charging effect
Time Domain Analysis

• Provides more realistic I/O behavior (using IBIS buffer)
• Higher simulation time for complex board  HPC

Modeling a DDR4 Memory Channel

Building Blocks of a DDR4 System
 Memory Data-bus With two-Slots per channel
Memory Controller Motherboard Socket 1 DIMM PCB Memory Module

Hub (MCH)
•DIE •Break-out •DIE

•Package •Transmission •Package
Lines
•Break-in
Socket 2 DIMM PCB Memory Module
•DIE
•Package

One Byte Lane + Strobe = 10 Nets
Cascading Sub-models or Full Channel?
Pin Cascading TEM Cascading Full Channel

• Easy to set up • •
More setup time required Easy to set up
• •
Computationally most efficient Computationally more • High computational cost
efficient
• Concerns about accuracy as• Almost same level of accuracy
• Highest level of accuracy, no
as full channel
fringing fields are neglected and simplifications
return current discontinuities
are introduced
• Can use combination of • Requires ECAD and MCAD• Requires ECAD and MCAD
measured and simulated resultsmodels of all components models of all components
including material properties
including material properties

Pin Cascading Details
-0.03n -0.04n
-0.12p
-0.04n -0.135n
-0.3p
-0.03n -0.04n
-0.12p

TEM Cascading
Appr. 6mm
Sub-Section Interface

TEM Cascading Details

CST DS – Synopsys HSPICE Link

Field Distribution

Results Comparison Cascading Approach Model
Simulation Time
(%)
Peak Memory
Requirement
Full S-Matrix from 0 – 20GHz Motherboard 5% 10 GB
Socket 2% 5 GB
20 ports Pin Cascading
DIMM 2.5 % 4 GB
Total 9.5 % 10 GB
Motherboard (Section 1) 3% 7.5 GB
Motherboard (Section 2) +
TEM Cascading 14 % 8.5 GB
Sockets + DIMMs
Total 17 % 8.5 GB
None (Full Channel) Total Reference (100%) 30 GB
Hardware Based Acceleration Techniques
Multithreading GPU Computing
Distributed Computing MPI Computing

Summary
DDR4 is the up-and-coming standard for memory architecture.
• Tight Specifications for High-Speed Operation
Channel modelling requires high accuracy as the designs may operate close to
specification limits
• 3D Modelling can provide the necessary accuracy
• Computation times can be high but can be brought to acceptable limits with
modern-day compute hardware
• Eye-Diagram can reliably predict the quality of the channel
Simulation can be used to evaluate cost-sensitive parameters of the routing

• Pre-Layout Optimization
• Substrate Evaluation

Scope of EMC/EMI
The ability of an electrical system or device to work
EMC satisfactorily in its electromagnetic environment
without influencing the surrounding devices
(emissions), or being influenced by the surrounding
Susceptibility
equipment (susceptibility)
Emissions KHz MHz GHz

Switched Power, ESD, EMP, HIRF, Digital
Lightning Radio electronics, RADAR
Environmental
Effects (E3)
Susceptibility and emissions are well regulated areas

EMC compliance is a crucial requirement for all products!
EMC/EMI Workflows


PCB Differential Lines
Good Design Bad Design

CST BOARDCHECK
SI and EMC rules
Quick verification of
PCB layout
Automatic report
generation and
display of violations
Fully integrated in
CST PCB STUDIO™
Windows and Linux

platform support

CST BOARDCHECK: Rules
EMC Rules SI Rules

CST BOARDCHECK: Violations
Net crossing split reference plane
Net near edge of reference plane
Differential net length

mismatch

Radiated Emission Measurement Setup
Max from hor & vert, turntable at 0°, 90°, 180°, 270°

DEMO

Results Comparison
Measurement Broadband 1V Simulation

Radiated Emission Simulation Workflow

Emission Workflow & Combine Results
Only circuit simulation and post-processing needed

Results Comparison
Rectangular Pulse, 250 MHz, 100 ps rise, 1.2 V
0 0
Bad Design Good Design

Emission from PDN
Port defined at the PDN of

the driver IC
0

Emssion from PDN
Excite PDN of the driver IC Port at the PDN of the

with the current spectrum driver IC
Results Comparison
0
0
Just Traces Traces and PDN

Near Field Source Modeling
Simulation
using most
efficient solver
Simulation of
Near Field
detailed
Measurement
structure
Js, Ms n
(Ei, Hi) Js = n x Hi
S Ms = -n x Ei
E0 E1
Equivalence Principle
Enclosure and PCB

Enclosure and Simplified PCB

Enclosure and Simplified PCB
Added Screws

Cable Simulation
DEMO

WiFi antenna to USB cable coupling
USB Screened Cable
WiFi Antenna

WiFi antenna to USB Cable coupling
USB Un-screened Cable
Differential signalling

Coupled field from antenna to cable

WiFi Antenna radiation pattern

Induced current on cable

Summary
•Hybrid field/cable/circuit solution
2D (TL) cable
•Full bi-directional coupling between cable solver
and environment
•Ideal for susceptibility and emissions
analysis
3D Transient full
Circuit solver wave field
solver

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SI/PI and EMC/EMI Simulation Workflows

for High-Speed Electronics

Radiated Emission Workflow

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

Signal Integrity and

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

Parameter  Macro enabled

 Data rates of interest 10 – 28 Gbps (Nyquist freq 5 – 14 GHz)

CST Microwave Studio

CST PCB Studio

Generic Exchange Formats:

Ensure clean supply

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

 8 metal layer board with

 1.8V power plane to be 70mm

 1 memory controller and

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

Goals: GND pins

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

Measurement of bareboard Measurement with mounted decaps

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

Decaps can be manually placed

 DDR2-400 I/O Buffer IBIS

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

With Decaps No Decaps

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

Define the target impedance

Start the optimization

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

Maximum voltage overshoot:

Time Domain Analysis

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

Memory Controller Motherboard Socket 1 DIMM PCB Memory Module

•DIE •Break-out •DIE

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

Pin Cascading TEM Cascading Full Channel

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

Multithreading GPU Computing

Distributed Computing MPI Computing

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

Simulation can be used to evaluate cost-sensitive parameters of the routing

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

Emissions KHz MHz GHz

Susceptibility and emissions are well regulated areas

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

Windows and Linux