HT6P20X Series 2 OTP Encoder: Features
HT6P20X Series 2 OTP Encoder: Features
HT6P20X Series 2 OTP Encoder: Features
Applications
· Burglar alarm system · Security system
· Smoke and fire alarm system · Cordless telephones
· Garage door controllers · Other remote control systems
· Car door controllers
General Description
The HT6P20X is a CMOS LSI encoder designed for re- grammable process. In addition, the chip offers various
mote control system applications. It encodes 24 bits of packaging for flexible combination of programmable ad-
information and then serially transmits it via the DOUT dress/data so as to meet various applications. Its pro-
pin upon receipt of transmission enable (DATA pins: grammable address/data is transmitted together with
D0~D7) signals. The combination of address and data the anti-code bits via RF or infrared transmission me-
bits of the HT6P20X is designed using one time pro- dium upon receipt of a trigger signal.
Block Diagram
O S C 1 A d d re s s
O s c illa to r
O S C 2 C o u n te r
V P P P r o g r a m m in g M ix e r &
D O U T
S IO C ir c u it D r iv e r
C o n tr o l U n it D a ta L a tc h
P G M D 0 D 7
Note: Address/Data numbers are available in various combinations, refer to the functional description.
Pin Assignment
2 4 -A d d re s s 2 2 -A d d re s s 2 0 -A d d re s s
0 -D a ta 2 -D a ta 4 -D a ta
D 1 1 1 6 D 0
D 2 2 1 5 P G M
D 3 3 1 4 S IO
V S S 4 1 3 V P P
P G M 1 8 S IO D 0 1 8 N C N C 5 1 2 V D D
V S S 2 7 V P P D 1 2 7 V D D N C 6 1 1 D O U T
O S C 2 3 6 V D D V S S 3 6 D O U T N C 7 1 0 O S C 1
O S C 1 4 5 D O U T O S C 2 4 5 O S C 1 N C 8 9 O S C 2
H T 6 P 2 0 A H T 6 P 2 0 B H T 6 P 2 0 D
8 D IP /S O P 8 D IP /S O P 1 6 D IP /N S O P
Pin Description
HT6P20D
Internal
Pin No. Pin Name I/O Description
Connection
16 CMOS IN Data input and transmission enable (active low)
D0~D3 I
1~3 Pull-high They can be externally set to VSS or left open.
4 VSS ¾ ¾ Negative power supply, ground
5~8 NC ¾ ¾ No connection
9 OSC2 O OSCILLATOR Oscillator output pin
10 OSC1 I OSCILLATOR Oscillator input pin
11 DOUT O CMOS OUT Data serial transmission output
12 VDD ¾ ¾ Positive power supply
CMOS Programming address/control code input and mode code output for
14 SIO I/O
IN/OUT mode verification
CMOS IN
15 PGM I Program mode control pin, active low
Pull-high
C M O S IN /O U T C M O S IN
C M O S O U T O S C IL L A T O R
P u ll- h ig h
V D D
O S C 1 O S C 2
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
VDD Operating Voltage ¾ ¾ 2 ¾ 12 V
ISTB Standby Current 12V Oscillator stops ¾ 1 2 mA
IDD Operating Current 12V No load, fOSC=3kHz ¾ 200 400 mA
VIH ²H² Input Voltage ¾ ¾ 0.8VDD ¾ VDD V
VIL ²L² Input Voltage ¾ ¾ 0 ¾ 0.2VDD V
RPH D0~D7 Pull-high Resistance 12V ¾ ¾ 150 300 kW
5V 0.9VDD -2 -5 ¾ mA
Source
12V 0.9VDD -6.5 -15 ¾ mA
IDOUT Output Current
5V 0.1VDD 2 5 ¾ mA
Sink
12V 0.1VDD 6 15 ¾ mA
fOSC Oscillator Frequency 12V ROSC=1.4MW ¾ 3 ¾ kHz
Functional Description
Normal Operation
The HT6P20X encodes and transmits address/data to a decoder upon receipt of a trigger signal. The address codes of
the HT6P20A are always transmitted as long as power (VDD) is supplied. The transmission function of the HT6P20B/D
is enabled by the D0~D7 pins (active low). The following is the transmission timing of the HT6P20X:
D 0 ~ D 7
< 1 w o rd > 1 w o rd
E n c o d e r
D O U T
Transmission timing
fo s c
1 c lo c k
D O U T
1 /3 b it 0 1 0 1
p ilo t p e r io d ( A 0 ~ A 1 9 , 6 0 c lo c k s ) ( D 3 ~ D 0 , 1 2 c lo c k s ) a n ti- c o d e p e r io d
( 2 3 c lo c k s ) a d d r e s s c o d e p e r io d d a ta c o d e p e r io d ( 4 b its )
The HT6P20A/B/D detects the logic state of the internal programmed address and the external data pins, and then trans-
mits the detected information during the code period. Each address/data bit can be set to one of the following two logic
states:
fo s c
" O n e "
"Z e ro "
A d d re s s /
D a ta b it
Flowchart
P o w e r o n
S ta n d b y m o d e
N o
P G M = 0 ?
N o Y e s
T r a n s m is s io n
e n a b le d ?
P r o g r a m m in g
Y e s m o d e
A d d re s s /d a ta w o rd s
tr a n s m itte d
N o P r o g r a m m in g
c o m p le te d ?
Y e s
N o T r a n s m is s io n
s till e n a b le d
Y e s
N o te : O n e tim e p r o g r a m m a b le
A d d re s s /d a ta w o rd s
tr a n s m itte d
c o n tin u o u s ly
Application Circuits
T r a n s m itte r C ir c u it
T r a n s m itte r C ir c u it 1 1 6
D 1 D 0
2 D 2 1 5
P G M
3 D 3 S IO 1 4 + 1 2 V
1 8
P G M S IO 4 1 3
V S S V P P
2 7 + 1 2 V 5 N C V D D 1 2
V S S V P P
6 N C D O U T 1 1 L E D
3 6
O S C 2 V D D R o s c
7 N C O S C 1 1 0
T E L E D
R o s c
4 5 8 9
O S C 1 D O U T N C O S C 2
H T 6 P 2 0 A H T 6 P 2 0 D
R o s c @ 1 .4 M W R o s c @ 1 .4 M W
T r a n s m itte r C ir c u it
1 1 6
D 1 D 0
2 1 5
D 2 P G M
3 1 4 + 1 2 V
D 3 S IO
4 1 3
V S S V P P 1 0 0 W
5 1 2
N C V D D
6 D O U T 1 1 0 .1 m F
N C
1 0 R o s c
7 N C O S C 1
8 9
N C O S C 2
H T 6 P 2 0 D
R o s c @ 1 .4 M W
+ 1 2 V
1 0 0 k W
T r a n s m itte r C ir c u it 4 .7 k W T r a n s m itte r C ir c u it
1 D 1 D 0 1 6 1 D 1 D 0 1 6
2 D 2 1 5 2 D 2 1 5
P G M P G M
3 D 3 S IO 1 4 3 D 3 S IO 1 4
+ 1 2 V
4 V S S V P P 1 3 4 V S S V P P 1 3
1 0 0 W 1 0 0 W
5 N C V D D 1 2 5 N C V D D 1 2
6 1 1 0 .1 m F L E D 6 1 1 0 .1 m F L E D
N C D O U T N C D O U T
7 1 0 7 N C O S C 1 1 0
N C O S C 1
8 9 R o s c 8 9 R o s c
N C O S C 2 N C O S C 2
H T 6 P 2 0 D H T 6 P 2 0 D
R o s c @ 1 .4 M W R o s c @ 1 .4 M W
Note: In order to prevent the IC from getting damaged due to the latch up, the 100W resistor or the LED which can
also be a transmission indicator is indispensible when VDD=9V~12V.
Package Information
8-pin DIP (300mil) Outline Dimensions
8 5
B
1 4
D
a I
E G
Dimensions in mil
Symbol
Min. Nom. Max.
A 355 ¾ 375
B 240 ¾ 260
C 125 ¾ 135
D 125 ¾ 145
E 16 ¾ 20
F 50 ¾ 70
G ¾ 100 ¾
H 295 ¾ 315
I 335 ¾ 375
a 0° ¾ 15°
1 6 9
B
1 8
D
a
E G I
F
Dimensions in mil
Symbol
Min. Nom. Max.
A 745 ¾ 775
B 240 ¾ 260
C 125 ¾ 135
D 125 ¾ 145
E 16 ¾ 20
F 50 ¾ 70
G ¾ 100 ¾
H 295 ¾ 315
I 335 ¾ 375
a 0° ¾ 15°
8 5
A B
1 4
C '
G
D H
E F a
Dimensions in mil
Symbol
Min. Nom. Max.
A 228 ¾ 244
B 149 ¾ 157
C 14 ¾ 20
C¢ 189 ¾ 197
D 53 ¾ 69
E ¾ 50 ¾
F 4 ¾ 10
G 22 ¾ 28
H 4 ¾ 12
a 0° ¾ 10°
1 6 9
A B
1 8
C '
G
D H
E F a
Dimensions in mil
Symbol
Min. Nom. Max.
A 228 ¾ 244
B 149 ¾ 157
C 14 ¾ 20
C¢ 386 ¾ 394
D 53 ¾ 69
E ¾ 50 ¾
F 4 ¾ 10
G 22 ¾ 28
H 4 ¾ 12
a 0° ¾ 10°
D
T 2
A B C
T 1
SOP 8N
Symbol Description Dimensions in mm
A Reel Outer Diameter 330±1.0
B Reel Inner Diameter 62±1.5
13.0+0.5
C Spindle Hole Diameter
-0.2
D Key Slit Width 2.0±0.15
12.8+0.3
T1 Space Between Flange
-0.2
T2 Reel Thickness 18.2±0.2
P 0 P 1
D t
F
W
B 0
C
D 1 P
K 0
A 0
SOP 8N
Symbol Description Dimensions in mm
12.0+0.3
W Carrier Tape Width
-0.1
P Cavity Pitch 8.0±0.1
E Perforation Position 1.75±0.1
F Cavity to Perforation (Width Direction) 5.5±0.1
D Perforation Diameter 1.55±0.1
D1 Cavity Hole Diameter 1.5+0.25
P0 Perforation Pitch 4.0±0.1
P1 Cavity to Perforation (Length Direction) 2.0±0.1
A0 Cavity Length 6.4±0.1
B0 Cavity Width 5.20±0.1
K0 Cavity Depth 2.1±0.1
t Carrier Tape Thickness 0.3±0.05
C Cover Tape Width 9.3
NSOP 16N
Symbol Description Dimensions in mm
W Carrier Tape Width 16.0±0.3
P Cavity Pitch 8.0±0.1
E Perforation Position 1.75±0.1
F Cavity to Perforation (Width Direction) 7.5±0.1
D Perforation Diameter 1.55+0.1
D1 Cavity Hole Diameter 1.5+0.25
P0 Perforation Pitch 4.0±0.1
P1 Cavity to Perforation (Length Direction) 2.0±0.1
A0 Cavity Length 6.5±0.1
B0 Cavity Width 10.3±0.1
K0 Cavity Depth 2.1±0.1
t Carrier Tape Thickness 0.3±0.05
C Cover Tape Width 13.3