R5F21255SNFP Renesas PDF

REJ09B0244-0300
www.DataSheet4U.com
R8C/24 Group, R8C/25 Group

16 Hardware Manual
RENESAS 16-BIT SINGLE-CHIP MCU

R8C FAMILY / R8C/2x SERIES
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Technology Corp. without notice. Please review the latest information published
by Renesas Technology Corp. through various means, including the Renesas Technology
Corp. website (http://www.renesas.com).
Rev.3.00
Revision Date: Feb 29, 2008 www.renesas.com
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
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application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins

Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
 The input pins of CMOS products are generally in the high-impedance state. In operation
www.DataSheet4U.com with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
 The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
 The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
 When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
 The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
How to Use This Manual
1. Purpose and Target Readers
This manual is designed to provide the user with an understanding of the hardware functions and electrical
characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic
knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual.
The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral
functions, and electrical characteristics; and usage notes.
Particular
www.DataSheet4U.com attention should be paid to the precautionary notes when using the manual. These notes occur
within the body of the text, at the end of each section, and in the Usage Notes section.
The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer
to the text of the manual for details.
The following documents apply to the R8C/24 Group, R8C/25 Group. Make sure to refer to the latest versions of these
documents. The newest versions of the documents listed may be obtained from the Renesas Technology Web site.
Document Type Description Document Title Document No.

Datasheet Hardware overview and electrical characteristics R8C/24 Group, REJ03B0117
R8C/25 Group
Datasheet
Hardware manual Hardware specifications (pin assignments, R8C/24 Group, This hardware
memory maps, peripheral function R8C/25 Group manual
specifications, electrical characteristics, timing Hardware Manual
charts) and operation description
Note: Refer to the application notes for details on
using peripheral functions.
Software manual Description of CPU instruction set R8C/Tiny Series REJ09B0001
Software Manual
Application note Information on using peripheral functions and Available from Renesas
application examples Technology Web site.
Sample programs
Information on writing programs in assembly
language and C
Renesas Product specifications, updates on documents,
technical update etc.
2. Notation of Numbers and Symbols
The notation conventions for register names, bit names, numbers, and symbols used in this manual are described
below.
(1) Register Names, Bit Names, and Pin Names

Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word
“register,” “bit,” or “pin” to distinguish the three categories.
Examples the PM03 bit in the PM0 register
P3_5 pin, VCC pin
(2) Notation of Numbers

www.DataSheet4U.com The indication “b” is appended to numeric values given in binary format. However, nothing is appended to the
values of single bits. The indication “h” is appended to numeric values given in hexadecimal format. Nothing
is appended to numeric values given in decimal format.
Examples Binary: 11b
Hexadecimal: EFA0h
Decimal: 1234
3. Register Notation
The symbols and terms used in register diagrams are described below.
XXX Register *1
b7 b6 b5 b4 b3 b2 b1 b0
0 Symbol Address After Reset

XXX XXX 00h
Bit Symbol Bit Name Function RW

*2
b1 b0
XXX0 XXX bits 1 0: XXX RW
www.DataSheet4U.com 0 1: XXX
1 0: Do not set.
XXX1 1 1: XXX RW
Nothing is assigned. If necessary, set to 0.

(b2) When read, the content is undefined.
*3
(b3) Reserved bits Set to 0. RW

*4
XXX bits Function varies according to the operating

XXX4 RW
mode.
XXX5 WO
XXX6 RW
XXX7 XXX bit 0: XXX

RO
1: XXX
*1
Blank: Set to 0 or 1 according to the application.
0: Set to 0.
1: Set to 1.
X: Nothing is assigned.
*2
RW: Read and write.
RO: Read only.
WO: Write only.
−: Nothing is assigned.
*3
• Reserved bit
Reserved bit. Set to specified value.
*4
• Nothing is assigned
Nothing is assigned to the bit. As the bit may be used for future functions, if necessary, set to 0.
• Do not set to a value
Operation is not guaranteed when a value is set.
• Function varies according to the operating mode.
The function of the bit varies with the peripheral function mode. Refer to the register diagram for information
on the individual modes.
4. List of Abbreviations and Acronyms
Abbreviation Full Form

ACIA Asynchronous Communication Interface Adapter
bps bits per second
CRC Cyclic Redundancy Check
DMA Direct Memory Access
DMAC Direct Memory Access Controller
GSM Global System for Mobile Communications
Hi-Z
www.DataSheet4U.com High Impedance
IEBus Inter Equipment bus
I/O Input/Output
IrDA Infrared Data Association
LSB Least Significant Bit
MSB Most Significant Bit
NC Non-Connection
PLL Phase Locked Loop
PWM Pulse Width Modulation
SFR Special Function Registers
SIM Subscriber Identity Module
UART Universal Asynchronous Receiver/Transmitter
VCO Voltage Controlled Oscillator
All trademarks and registered trademarks are the property of their respective owners.
Table of Contents
SFR Page Reference ........................................................................................................................... B - 1
1. Overview ......................................................................................................................................... 1
1.1 Applications ............................................................................................................................................... 1
1.2 Performance Overview .............................................................................................................................. 2
1.3 Block Diagram .......................................................................................................................................... 4
1.4 Product Information .................................................................................................................................. 5
1.5 Pin Assignments ........................................................................................................................................ 9
1.6 Pin Functions ........................................................................................................................................... 11
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2. Central Processing Unit (CPU) ..................................................................................................... 13
2.1 Data Registers (R0, R1, R2, and R3) ...................................................................................................... 14
2.2 Address Registers (A0 and A1) ............................................................................................................... 14
2.3 Frame Base Register (FB) ....................................................................................................................... 14
2.4 Interrupt Table Register (INTB) .............................................................................................................. 14
2.5 Program Counter (PC) ............................................................................................................................. 14
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) .................................................................. 14
2.7 Static Base Register (SB) ........................................................................................................................ 14
2.8 Flag Register (FLG) ................................................................................................................................ 14
2.8.1 Carry Flag (C) ..................................................................................................................................... 14
2.8.2 Debug Flag (D) ................................................................................................................................... 14
2.8.3 Zero Flag (Z) ....................................................................................................................................... 14
2.8.4 Sign Flag (S) ....................................................................................................................................... 14
2.8.5 Register Bank Select Flag (B) ............................................................................................................ 14
2.8.6 Overflow Flag (O) .............................................................................................................................. 14
2.8.7 Interrupt Enable Flag (I) ..................................................................................................................... 15
2.8.8 Stack Pointer Select Flag (U) .............................................................................................................. 15
2.8.9 Processor Interrupt Priority Level (IPL) ............................................................................................. 15
2.8.10 Reserved Bit ........................................................................................................................................ 15
3. Memory ......................................................................................................................................... 16
3.1 R8C/24 Group ......................................................................................................................................... 16
3.2 R8C/25 Group ......................................................................................................................................... 17
4. Special Function Registers (SFRs) ............................................................................................... 18
5. Resets ........................................................................................................................................... 25
5.1 Hardware Reset ....................................................................................................................................... 28
5.1.1 When Power Supply is Stable ............................................................................................................. 28
5.1.2 Power On ............................................................................................................................................ 28
5.2 Power-On Reset Function ....................................................................................................................... 30
5.3 Voltage Monitor 0 Reset ......................................................................................................................... 31
5.6 Watchdog Timer Reset ............................................................................................................................ 32
5.7 Software Reset ......................................................................................................................................... 32
6. Voltage Detection Circuit .............................................................................................................. 33

6.1 VCC Input Voltage .................................................................................................................................. 40
A-1
6.1.1 Monitoring Vdet0 ............................................................................................................................... 40
6.1.2 Monitoring Vdet1 ............................................................................................................................... 40
6.1.3 Monitoring Vdet2 ............................................................................................................................... 40
6.3 Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset ..................................................................... 42
6.4 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset ..................................................................... 44
7. Programmable I/O Ports ............................................................................................................... 46

7.1 Functions of Programmable I/O Ports ..................................................................................................... 46
7.2
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Effect on Peripheral Functions ................................................................................................................ 47
7.3 Pins Other than Programmable I/O Ports ................................................................................................ 47
7.4 Port settings ............................................................................................................................................. 59
7.5 Unassigned Pin Handling ........................................................................................................................ 70
8. Processor Mode ............................................................................................................................ 71

8.1 Processor Modes ...................................................................................................................................... 71
9. Bus ................................................................................................................................................ 72
10. Clock Generation Circuit ............................................................................................................... 73

10.1 XIN Clock ............................................................................................................................................... 82
10.2 On-Chip Oscillator Clocks ...................................................................................................................... 83
10.2.1 Low-Speed On-Chip Oscillator Clock ................................................................................................ 83
10.2.2 High-Speed On-Chip Oscillator Clock ............................................................................................... 83
10.3 XCIN Clock ............................................................................................................................................. 84
10.4 CPU Clock and Peripheral Function Clock ............................................................................................. 85
10.4.1 System Clock ...................................................................................................................................... 85
10.4.2 CPU Clock .......................................................................................................................................... 85
10.4.3 Peripheral Function Clock (f1, f2, f4, f8, and f32) ............................................................................. 85
10.4.4 fOCO ................................................................................................................................................... 85
10.4.5 fOCO40M ........................................................................................................................................... 85
10.4.6 fOCO-F ............................................................................................................................................... 85
10.4.7 fOCO-S ............................................................................................................................................... 85
10.4.8 fOCO128 ............................................................................................................................................. 85
10.4.9 fC4 and fC32 ....................................................................................................................................... 86
10.5 Power Control .......................................................................................................................................... 87
10.5.1 Standard Operating Mode ................................................................................................................... 87
10.5.2 Wait Mode .......................................................................................................................................... 89
10.5.3 Stop Mode ........................................................................................................................................... 93
10.6 Oscillation Stop Detection Function ....................................................................................................... 96
10.6.1 How to Use Oscillation Stop Detection Function ............................................................................... 96
10.7 Notes on Clock Generation Circuit ......................................................................................................... 99
10.7.1 Stop Mode ........................................................................................................................................... 99
10.7.2 Wait Mode .......................................................................................................................................... 99
10.7.3 Oscillation Stop Detection Function ................................................................................................... 99
10.7.4 Oscillation Circuit Constants .............................................................................................................. 99
A-2
11. Protection .................................................................................................................................... 100
12. Interrupts ..................................................................................................................................... 101

12.1 Interrupt Overview ................................................................................................................................ 101
12.1.1 Types of Interrupts ............................................................................................................................ 101
12.1.2 Software Interrupts ........................................................................................................................... 102
12.1.3 Special Interrupts .............................................................................................................................. 103
12.1.4 Peripheral Function Interrupt ............................................................................................................ 103
12.1.5 Interrupts and Interrupt Vectors ........................................................................................................ 104
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12.1.6 Interrupt Control ............................................................................................................................... 106
12.2 INT Interrupt ......................................................................................................................................... 115
12.2.1 INTi Interrupt (i = 0 to 3) .................................................................................................................. 115
12.2.2 INTi Input Filter (i = 0 to 3) .............................................................................................................. 117
12.3 Key Input Interrupt ................................................................................................................................ 118
12.4 Address Match Interrupt ........................................................................................................................ 120
12.5 Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupts, and I2C bus Interface
Interrupt (Interrupts with Multiple Interrupt Request Sources) ............................................................ 122
12.6 Notes on Interrupts ................................................................................................................................ 124
12.6.1 Reading Address 00000h .................................................................................................................. 124
12.6.2 SP Setting .......................................................................................................................................... 124
12.6.3 External Interrupt and Key Input Interrupt ....................................................................................... 124
12.6.4 Changing Interrupt Sources .............................................................................................................. 125
12.6.5 Changing Interrupt Control Register Contents ................................................................................. 126
13. Watchdog Timer .......................................................................................................................... 127

13.1 Count Source Protection Mode Disabled .............................................................................................. 130
13.2 Count Source Protection Mode Enabled ............................................................................................... 131
14. Timers ......................................................................................................................................... 132

14.1 Timer RA ............................................................................................................................................... 134
14.1.1 Timer Mode ...................................................................................................................................... 137
14.1.2 Pulse Output Mode ........................................................................................................................... 139
14.1.3 Event Counter Mode ......................................................................................................................... 141
14.1.4 Pulse Width Measurement Mode ...................................................................................................... 143
14.1.5 Pulse Period Measurement Mode ..................................................................................................... 146
14.1.6 Notes on Timer RA ........................................................................................................................... 149
14.2 Timer RB ............................................................................................................................................... 150
14.2.1 Timer Mode ...................................................................................................................................... 154
14.2.2 Programmable Waveform Generation Mode .................................................................................... 157
14.2.3 Programmable One-shot Generation Mode ...................................................................................... 159
14.2.4 Programmable Wait One-Shot Generation Mode ............................................................................. 163
14.2.5 Notes on Timer RB ........................................................................................................................... 167
14.3 Timer RD ............................................................................................................................................... 171
14.3.1 Count Sources ................................................................................................................................... 176
14.3.2 Buffer Operation ............................................................................................................................... 177
14.3.3 Synchronous Operation ..................................................................................................................... 179
14.3.4 Pulse Output Forced Cutoff .............................................................................................................. 180
14.3.5 Input Capture Function ..................................................................................................................... 182
14.3.6 Output Compare Function ................................................................................................................ 196
A-3
14.3.7 PWM Mode ....................................................................................................................................... 213
14.3.8 Reset Synchronous PWM Mode ....................................................................................................... 226
14.3.9 Complementary PWM Mode ............................................................................................................ 236
14.3.10 PWM3 Mode ..................................................................................................................................... 250
14.3.11 Timer RD Interrupt ........................................................................................................................... 262
14.3.12 Notes on Timer RD ........................................................................................................................... 264
14.4 Timer RE ............................................................................................................................................... 270
14.4.1 Real-Time Clock Mode .................................................................................................................... 271
14.4.2 Output Compare Mode ..................................................................................................................... 279
14.4.3 Notes on Timer RE ........................................................................................................................... 285
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15. Serial Interface ............................................................................................................................ 288

15.1 Clock Synchronous Serial I/O Mode ..................................................................................................... 294
15.1.1 Polarity Select Function .................................................................................................................... 297
15.1.2 LSB First/MSB First Select Function ............................................................................................... 297
15.1.3 Continuous Receive Mode ................................................................................................................ 298
15.2 Clock Asynchronous Serial I/O (UART) Mode .................................................................................... 299
15.2.1 Bit Rate ............................................................................................................................................. 303
15.3 Notes on Serial Interface ....................................................................................................................... 304
16. Clock Synchronous Serial Interface ............................................................................................ 305

16.1 Mode Selection ...................................................................................................................................... 305
16.2 Clock Synchronous Serial I/O with Chip Select (SSU) ........................................................................ 306
16.2.1 Transfer Clock .................................................................................................................................. 315
16.2.2 SS Shift Register (SSTRSR) ............................................................................................................. 317
16.2.3 Interrupt Requests ............................................................................................................................. 318
16.2.4 Communication Modes and Pin Functions ....................................................................................... 319
16.2.5 Clock Synchronous Communication Mode ...................................................................................... 320
16.2.6 Operation in 4-Wire Bus Communication Mode .............................................................................. 327
16.2.7 SCS Pin Control and Arbitration ...................................................................................................... 333
16.2.8 Notes on Clock Synchronous Serial I/O with Chip Select ............................................................... 334
16.3 I2C bus Interface .................................................................................................................................... 335
16.3.1 Transfer Clock .................................................................................................................................. 345
16.3.2 Interrupt Requests ............................................................................................................................. 346
16.3.3 I2C bus Interface Mode ..................................................................................................................... 347
16.3.4 Clock Synchronous Serial Mode ...................................................................................................... 358
16.3.5 Noise Canceller ................................................................................................................................. 361
16.3.6 Bit Synchronization Circuit .............................................................................................................. 362
16.3.7 Examples of Register Setting ............................................................................................................ 363
16.3.8 Notes on I2C bus Interface ................................................................................................................ 367
17. Hardware LIN .............................................................................................................................. 368

17.1 Features ................................................................................................................................................. 368
17.2 Input/Output Pins .................................................................................................................................. 369
17.3 Register Configuration .......................................................................................................................... 370
17.4 Functional Description .......................................................................................................................... 372
17.4.1 Master Mode ..................................................................................................................................... 372
17.4.2 Slave Mode ....................................................................................................................................... 375
17.4.3 Bus Collision Detection Function ..................................................................................................... 379
A-4
17.4.4 Hardware LIN End Processing ......................................................................................................... 380
17.5 Interrupt Requests .................................................................................................................................. 381
17.6 Notes on Hardware LIN ........................................................................................................................ 382
18. A/D Converter ............................................................................................................................. 383

18.1 One-Shot Mode ..................................................................................................................................... 387
18.2 Repeat Mode .......................................................................................................................................... 390
18.3 Sample and Hold ................................................................................................................................... 393
18.4 A/D Conversion Cycles ......................................................................................................................... 393
18.5
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Internal Equivalent Circuit of Analog Input .......................................................................................... 394
18.6 Output Impedance of Sensor under A/D Conversion ............................................................................ 395
18.7 Notes on A/D Converter ........................................................................................................................ 396
19. Flash Memory ............................................................................................................................. 397

19.1 Overview ............................................................................................................................................... 397
19.2 Memory Map ......................................................................................................................................... 398
19.3 Functions to Prevent Rewriting of Flash Memory ................................................................................ 400
19.3.1 ID Code Check Function .................................................................................................................. 400
19.3.2 ROM Code Protect Function ............................................................................................................ 401
19.4 CPU Rewrite Mode ............................................................................................................................... 402
19.4.1 EW0 Mode ........................................................................................................................................ 403
19.4.2 EW1 Mode ........................................................................................................................................ 403
19.4.3 Software Commands ......................................................................................................................... 412
19.4.4 Status Registers ................................................................................................................................. 417
19.4.5 Full Status Check .............................................................................................................................. 418
19.5 Standard Serial I/O Mode ...................................................................................................................... 420
19.5.1 ID Code Check Function .................................................................................................................. 420
19.6 Parallel I/O Mode .................................................................................................................................. 424
19.6.1 ROM Code Protect Function ............................................................................................................ 424
19.7 Notes on Flash Memory ........................................................................................................................ 425
19.7.1 CPU Rewrite Mode ........................................................................................................................... 425
20. Electrical Characteristics ............................................................................................................ 428
21. Usage Notes ............................................................................................................................... 454

21.1 Notes on Clock Generation Circuit ....................................................................................................... 454
21.1.1 Stop Mode ......................................................................................................................................... 454
21.1.2 Wait Mode ........................................................................................................................................ 454
21.1.3 Oscillation Stop Detection Function ................................................................................................. 454
21.1.4 Oscillation Circuit Constants ............................................................................................................ 454
21.2 Notes on Interrupts ................................................................................................................................ 455
21.2.1 Reading Address 00000h .................................................................................................................. 455
21.2.2 SP Setting .......................................................................................................................................... 455
21.2.3 External Interrupt and Key Input Interrupt ....................................................................................... 455
21.2.4 Changing Interrupt Sources .............................................................................................................. 456
21.2.5 Changing Interrupt Control Register Contents ................................................................................. 457
21.3 Notes on Timers .................................................................................................................................... 458
21.3.1 Notes on Timer RA ........................................................................................................................... 458
21.3.2 Notes on Timer RB ........................................................................................................................... 459
A-5
21.3.3 Notes on Timer RD ........................................................................................................................... 463
21.3.4 Notes on Timer RE ........................................................................................................................... 469
21.4 Notes on Serial Interface ....................................................................................................................... 472
21.5 Notes on Clock Synchronous Serial Interface ....................................................................................... 473
21.5.1 Notes on Clock Synchronous Serial I/O with Chip Select ............................................................... 473
21.5.2 Notes on I2C bus Interface ................................................................................................................ 473
21.6 Notes on Hardware LIN ........................................................................................................................ 474
21.7 Notes on A/D Converter ........................................................................................................................ 475
21.8 Notes on Flash Memory ........................................................................................................................ 476
21.8.1 CPU Rewrite Mode ........................................................................................................................... 476
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21.9 Notes on Noise ...................................................................................................................................... 479
21.9.1 Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and
Latch-up ............................................................................................................................................ 479
21.9.2 Countermeasures against Noise Error of Port Control Registers ..................................................... 479
22. Notes on On-Chip Debugger ...................................................................................................... 480
Appendix 1. Package Dimensions ........................................................................................................ 481
Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator ............ 482
Appendix 3. Example of Oscillation Evaluation Circuit ......................................................................... 483
Index ..................................................................................................................................................... 484
A-6
SFR Page Reference
Address Register Symbol Page Address Register Symbol Page
0000h 0040h
0001h 0041h
0002h 0042h
0003h 0043h
0004h Processor Mode Register 0 PM0 71 0044h
0005h Processor Mode Register 1 PM1 71 0045h
0006h System Clock Control Register 0 CM0 75 0046h
0007h System Clock Control Register 1 CM1 76 0047h
0008h 0048h Timer RD0 Interrupt Control Register TRD0IC 107
0009h 0049h Timer RD1 Interrupt Control Register TRD1IC 107
000Ah Protect Register PRCR 100 004Ah Timer RE Interrupt Control Register TREIC 106
000Bh 004Bh
000Ch Oscillation Stop Detection Register OCD 77 004Ch
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000Dh Watchdog Timer Reset Register WDTR 129 004Dh Key Input Interrupt Control Register KUPIC 106
000Eh Watchdog Timer Start Register WDTS 129 004Eh A/D Conversion Interrupt Control Register ADIC 106
000Fh Watchdog Timer Control Register WDC 128 004Fh SSU/IIC Interrupt Control Register SSUIC/IICIC 107
0010h Address Match Interrupt Register 0 RMAD0 121 0050h
0011h 0051h UART0 Transmit Interrupt Control Register S0TIC 106
0012h 0052h UART0 Receive Interrupt Control Register S0RIC 106
0013h Address Match Interrupt Enable Register AIER 121 0053h UART1 Transmit Interrupt Control Register S1TIC 106
0014h Address Match Interrupt Register 1 RMAD1 121 0054h UART1 Receive Interrupt Control Register S1RIC 106
0015h 0055h INT2 Interrupt Control Register INT2IC 108
0016h 0056h Timer RA Interrupt Control Register TRAIC 106
0017h 0057h
0018h 0058h Timer RB Interrupt Control Register TRBIC 106
0019h 0059h INT1 Interrupt Control Register INT1IC 108
001Ah 005Ah INT3 Interrupt Control Register INT3IC 108
001Bh 005Bh
001Ch Count Source Protection Mode Register CSPR 129 005Ch
001Dh 005Dh INT0 Interrupt Control Register INT0IC 108
001Eh 005Eh
001Fh 005Fh
0020h 0060h
0021h 0061h
0022h 0062h
0023h High-Speed On-Chip Oscillator Control FRA0 78 0063h
Register 0 0064h
0024h High-Speed On-Chip Oscillator Control FRA1 78
Register 1 0065h
0025h High-Speed On-Chip Oscillator Control FRA2 79 0066h
Register 2 0067h
0026h
0068h
0027h
0069h
0028h Clock Prescaler Reset Flag CPSRF 80
006Ah
0029h High-Speed On-Chip Oscillator Control FRA4 79
Register 4 006Bh
002Ah 006Ch
002Bh High-Speed On-Chip Oscillator Control FRA6 79 006Dh
Register 6 006Eh
002Ch High-Speed On-Chip Oscillator Control FRA7 79
Register 7 006Fh
0070h
0030h 0071h
0031h Voltage Detection Register 1 VCA1 36 0072h
0032h Voltage Detection Register 2 VCA2 36, 80 0073h
0033h 0074h
0034h 0075h
0035h 0076h
0036h Voltage Monitor 1 Circuit Control Register VW1C 38 0077h
0039h 007Ah
003Ah 007Bh
003Bh 007Ch
003Ch 007Dh
003Dh 007Eh
003Eh 007Fh
003Fh
NOTE:
1. The blank regions are reserved. Do not access locations
in these regions.
B-1
0080h 00C0h A/D Register AD 386
0081h 00C1h
0082h 00C2h
0083h 00C3h
0084h 00C4h
0085h 00C5h
0086h 00C6h
0087h 00C7h
0088h 00C8h
0089h 00C9h
008Ah 00CAh
008Bh 00CBh
008Ch 00CCh
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008Dh 00CDh
008Eh 00CEh
008Fh 00CFh
0090h 00D0h
0091h 00D1h
0092h 00D2h
0093h 00D3h
0094h 00D4h A/D Control Register 2 ADCON2 386
0095h 00D5h
0098h 00D8h
0099h 00D9h
009Ah 00DAh
009Bh 00DBh
009Ch 00DCh
009Dh 00DDh
009Eh 00DEh
009Fh 00DFh
00A0h UART0 Transmit/Receive Mode Register U0MR 291 00E0h Port P0 Register P0 56
00A1h UART0 Bit Rate Register U0BRG 291 00E1h Port P1 Register P1 56
00A2h UART0 Transmit Buffer Register U0TB 290 00E2h Port P0 Direction Register PD0 56
00A3h 00E3h Port P1 Direction Register PD1 56
00A4h UART0 Transmit/Receive Control Register 0 U0C0 292 00E4h Port P2 Register P2 56
00A5h UART0 Transmit/Receive Control Register 1 U0C1 293 00E5h Port P3 Register P3 56
00A6h UART0 Receive Buffer Register U0RB 290 00E6h Port P2 Direction Register PD2 56
00A7h 00E7h Port P3 Direction Register PD3 56
00A8h UART1 Transmit/Receive Mode Register U1MR 291 00E8h Port P4 Register P4 56
00A9h UART1 Bit Rate Register U1BRG 291 00E9h
00AAh UART1 Transmit Buffer Register U1TB 290 00EAh Port P4 Direction Register PD4 56
00ABh 00EBh
00ACh UART1 Transmit/Receive Control Register 0 U1C0 292 00ECh Port P6 Register P6 56
00ADh UART1 Transmit/Receive Control Register 1 U1C1 293 00EDh
00AEh UART1 Receive Buffer Register U1RB 290 00EEh Port P6 Direction Register PD6 56
00AFh 00EFh
00B0h 00F0h
00B1h 00F1h
00B2h 00F2h
00B3h 00F3h
00B4h 00F4h Port P2 Drive Capacity Control Register P2DRR 58
00B5h 00F5h UART1 Function Select Register U1SR 293
00B6h 00F6h
00B7h 00F7h
00B8h SS Control Register H / IIC bus Control Register 1 SSCRH/ICCR1 308, 338 00F8h Port Mode Register PMR 58, 293,
00B9h SS Control Register L / IIC bus Control Register 2 SSCRL/ICCR2 314, 344
309, 339
00F9h External Input Enable Register INTEN 115
00BAh SS Mode Register / IIC bus Mode Register SSMR/ICMR 310, 340
00BBh SS Enable Register / IIC bus Interrupt Enable Register SSER/ICIER 00FAh INT Input Filter Select Register INTF 116
311, 341
00BCh SS Status Register / IIC bus Status Register SSSR/ICSR 00FBh Key Input Enable Register KIEN 119
312, 342
00BDh SS Mode Register 2 / Slave Address Register SSMR2/SAR 00FCh Pull-Up Control Register 0 PUR0 57
313, 343
00BEh SS Transmit Data Register/IIC bus Transmit SSTDR/ICDRT 00FDh Pull-Up Control Register 1 PUR1 57
314, 343
Data Register 00FEh
00BFh SS Receive Data Register/IIC bus Receive SSRDR/ICDRR 314, 344 00FFh
Data Register
NOTE:
in these regions.
B-2
0100h Timer RA Control Register TRACR 135 0130h
0101h Timer RA I/O Control Register TRAIOC 135, 137, 140, 0131h
142, 144, 147 0132h
0102h Timer RA Mode Register TRAMR 136 0133h
0103h Timer RA Prescaler Register TRAPRE 136 0134h
0104h Timer RA Register TRA 136 0135h
0105h 0136h
0106h LIN Control Register LINCR 370 0137h Timer RD Start Register TRDSTR 184, 198, 215,
0107h LIN Status Register LINST 371 228, 238, 252
0108h Timer RB Control Register TRBCR 151 0138h Timer RD Mode Register TRDMR 184, 198, 215,
0109h Timer RB One-Shot Control Register TRBOCR 228, 239, 252
151
0139h Timer RD PWM Mode Register TRDPMR 185, 199, 216
010Ah Timer RB I/O Control Register TRBIOC 152, 154, 158,
160, 165 013Ah Timer RD Function Control Register TRDFCR 186, 200, 217,
010Bh Timer RB Mode Register TRBMR 229, 240, 253
www.DataSheet4U.com 152
013Bh Timer RD Output Master Enable Register TRDOER1 201, 218, 230,
010Ch Timer RB Prescaler Register TRBPRE 153 1 241, 254
010Dh Timer RB Secondary Register TRBSC 153 013Ch Timer RD Output Master Enable Register TRDOER2 201, 218, 230,
010Eh Timer RB Primary Register TRBPR 153 2 241, 254
010Fh 013Dh Timer RD Output Control Register TRDOCR 202, 219, 255
0110h 013Eh Timer RD Digital Filter Function Select TRDDF0 187
0111h Register 0
013Fh Timer RD Digital Filter Function Select TRDDF1 187
0112h Register 1
0113h 0140h Timer RD Control Register 0 TRDCR0 188, 203, 219,
0114h 231, 242, 256
0115h 0141h Timer RD I/O Control Register A0 TRDIORA0 189, 204
0116h 0142h Timer RD I/O Control Register C0 TRDIORC0 190, 205
0117h 0143h Timer RD Status Register 0 TRDSR0 191, 206, 220,
232, 243, 257
0118h Timer RE Second Data Register / Counter TRESEC 273, 281
Data Register 0144h Timer RD Interrupt Enable Register 0 TRDIER0 192, 207, 221,
0119h Timer RE Minute Data Register / Compare TREMIN 233, 244, 258
273, 281
Data Register 0145h Timer RD PWM Mode Output Level TRDPOCR0 222
011Ah Timer RE Hour Data Register TREHR 274 Control Register 0
0146h Timer RD Counter 0 TRD0 192, 207, 222,
011Bh Timer RE Day of Week Data Register TREWK 274
0147h 233, 245, 258
011Ch Timer RE Control Register 1 TRECR1 275, 282 0148h Timer RD General Register A0 TRDGRA0 193, 208, 223,
011Dh Timer RE Control Register 2 TRECR2 276, 282 0149h 234, 245, 259
011Eh Timer RE Count Source Select Register TRECSR 277, 283 014Ah Timer RD General Register B0 TRDGRB0 193, 208, 223,
011Fh 014Bh 234, 245, 259
0120h 014Ch Timer RD General Register C0 TRDGRC0 193, 208,
014Dh 223, 234, 259
0121h
014Eh Timer RD General Register D0 TRDGRD0 193, 208, 223,
0122h 014Fh 234, 245, 259
0123h 0150h Timer RD Control Register 1 TRDCR1 188, 203,
0124h 219, 242
0125h 0151h Timer RD I/O Control Register A1 TRDIORA1 189, 204
0126h 0152h Timer RD I/O Control Register C1 TRDIORC1 190, 205
0127h 0153h Timer RD Status Register 1 TRDSR1 191, 206, 220,
232, 243, 257
0128h
0154h Timer RD Interrupt Enable Register 1 TRDIER1 192, 207, 221,
0129h
233, 244, 258
012Ah 0155h Timer RD PWM Mode Output Level TRDPOCR1 222
012Bh Control Register 1
012Ch 0156h Timer RD Counter 1 TRD1 192, 207, 222,
0157h 245
012Dh
0158h Timer RD General Register A1 TRDGRA1 193, 208, 223,
012Eh 0159h 234, 245, 259
012Fh 015Ah Timer RD General Register B1 TRDGRB1 193, 208, 223,
015Bh 234, 245, 259
NOTE: 015Ch Timer RD General Register C1 TRDGRC1 193, 208, 223,
1. The blank regions are reserved. Do not access locations 015Dh 234, 245, 259
in these regions. 015Eh Timer RD General Register D1 TRDGRD1 193, 208, 223,
015Fh 234, 245, 259
B-3
0160h 01A0h
0161h 01A1h
0162h 01A2h
0163h 01A3h
0164h 01A4h
0165h 01A5h
0166h 01A6h
0167h 01A7h
0168h 01A8h
0169h 01A9h
016Ah 01AAh
016Bh 01ABh
016Ch 01ACh
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016Dh 01ADh
016Eh 01AEh
016Fh 01AFh
0170h 01B0h
0171h 01B1h
0172h 01B2h
0173h 01B3h Flash Memory Control Register 4 FMR4 408
0174h 01B4h
0176h 01B6h
0178h 01B8h
0179h 01B9h
017Ah 01BAh
017Bh 01BBh
017Ch 01BCh
017Dh 01BDh
017Eh 01BEh
017Fh
0180h FFFFh Option Function Select Register OFS 27, 128, 401
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
NOTE:
in these regions.
B-4
REJ09B0244-0300
SINGLE-CHIP 16-BIT CMOS MCU Rev.3.00
Feb 29, 2008
1. Overview
These MCUs are fabricated using a high-performance silicon gate CMOS process, embedding the R8C/Tiny Series
CPU core, and are packaged in a 52-pin molded-plastic LQFP or a 64-pin molded-plastic FLGA. It implements
sophisticated instructions for a high level of instruction efficiency. With 1 Mbyte of address space, they are capable of
executing instructions at high speed.
Furthermore, the R8C/25 Group has on-chip data flash (1 KB x 2 blocks).
The difference between the R8C/24 Group and R8C/25 Group is only the presence or absence of data flash. Their
peripheral
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functions are the same.
1.1 Applications
Electronic household appliances, office equipment, audio equipment, consumer products, etc.
Rev.3.00 Feb 29, 2008 Page 1 of 485

REJ09B0244-0300
R8C/24 Group, R8C/25 Group 1. Overview
1.2 Performance Overview

Table 1.1 outlines the Functions and Specifications for R8C/24 Group and Table 1.2 outlines the Functions and
Specifications for R8C/25 Group.
Table 1.1 Functions and Specifications for R8C/24 Group

Item Specification
CPU Number of fundamental 89 instructions
instructions
Minimum instruction execution 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
time 100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V)
Operating mode Single-chip
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Address space 1 Mbyte
Memory capacity Refer to Table 1.3 Product Information for R8C/24 Group
Peripheral Ports I/O ports: 41 pins, Input port: 3 pins
Functions LED drive ports I/O ports: 8 pins
Timers Timer RA: 8 bits × 1 channel
Timer RB: 8 bits × 1 channel
(Each timer equipped with 8-bit prescaler)
Timer RD: 16 bits × 2 channels
(Input capture and output compare circuits)
Timer RE: With real-time clock and compare match function
Serial interfaces 2 channels (UART0, UART1)
Clock synchronous serial I/O, UART
Clock synchronous serial 1 channel
interface I2C bus Interface(1)
Clock synchronous serial I/O with chip select
LIN module Hardware LIN: 1 channel (timer RA, UART0)
A/D converter 10-bit A/D converter: 1 circuit, 12 channels
Watchdog timer 15 bits × 1 channel (with prescaler)
Reset start selectable
Interrupts Internal: 11 sources, External: 5 sources, Software: 4
sources, Priority levels: 7 levels
Clock Clock generation 3 circuits
circuits • XIN clock generation circuit (with on-chip feedback resistor)
• On-chip oscillator (high speed, low speed)
High-speed on-chip oscillator has a frequency
adjustment function
• XCIN clock generation circuit (32 kHz)
Real-time clock (timer RE)
Oscillation stop detection function XIN clock oscillation stop detection function
Voltage detection circuit On-chip
Power-on reset circuit On-chip
Electrical Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz)
Characteristics VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)
VCC = 2.2 to 5.5 V (f(XIN) = 5 MHz)
Current consumption Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
Typ. 2.0 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz)
Typ. 0.7 µA (VCC = 3.0 V, stop mode)
Flash Memory Programming and erasure voltage VCC = 2.7 to 5.5 V
Programming and erasure endurance 100 times
Operating Ambient Temperature -20 to 85°C (N version)
-40 to 85°C (D version)(2)
-20 to 105°C (Y version)(3)
Package 52-pin molded-plastic LQFP
64-pin molded-plastic FLGA
NOTES:
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. Specify the D version if D version functions are to be used.
3. Please contact Renesas Technology sales offices for the Y version.
Rev.3.00 Feb 29, 2008 Page 2 of 485

REJ09B0244-0300
Table 1.2 Functions and Specifications for R8C/25 Group

Item Specification
CPU Number of fundamental 89 instructions
instructions
Minimum instruction execution 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
time 100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V)
Operating mode Single-chip
Address space 1 Mbyte
Memory capacity Refer to Table 1.4 Product Information for R8C/25 Group
Peripheral Ports I/O ports: 41 pins, Input port: 3 pins
Functions LED drive ports I/O ports: 8 pins
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Timers Timer RA: 8 bits × 1 channel
Timer RB: 8 bits × 1 channel
(Each timer equipped with 8-bit prescaler)
Timer RD: 16 bits × 2 channels
(Input capture and output compare circuits)
Timer RE: With real-time clock and compare match function
Serial interface 2 channels (UART0, UART1)
Clock synchronous serial I/O, UART
Clock synchronous serial 1 channel
interface I2C bus Interface(1)
Clock synchronous serial I/O with chip select
LIN module Hardware LIN: 1 channel (timer RA, UART0)
A/D converter 10-bit A/D converter: 1 circuit, 12 channels
Watchdog timer 15 bits × 1 channel (with prescaler)
Reset start selectable
Interrupts Internal: 11 sources, External: 5 sources, Software: 4
sources, Priority levels: 7 levels
Clock Clock generation 3 circuits
circuits • XIN clock generation circuit (with on-chip feedback
resistor)
• On-chip oscillator (high speed, low speed)
High-speed on-chip oscillator has a frequency
adjustment function
• XCIN clock generation circuit (32 kHz)
Real-time clock (timer RE)
Oscillation stop detection function XIN clock oscillation stop detection function
Voltage detection circuit On-chip
Power-on reset circuit On-chip
Electrical Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz)
Characteristics VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)
VCC = 2.2 to 5.5 V (f(XIN) = 5 MHz)
Current consumption Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
Typ. 2.0 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz)
Typ. 0.7 µA (VCC = 3.0 V, stop mode)
Flash memory Programming and erasure voltage VCC = 2.7 to 5.5 V
Programming and erasure 1,0000 times (data flash)
endurance 1,000 times (program ROM)
Operating Ambient Temperature -20 to 85°C (N version)
-40 to 85°C (D version)(2)
-20 to 105°C (Y version)(3)
Package 52-pin molded-plastic LQFP
64-pin molded-plastic FLGA
NOTES:
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. Specify the D version if D version functions are to be used.
Rev.3.00 Feb 29, 2008 Page 3 of 485

REJ09B0244-0300
1.3 Block Diagram

Figure 1.1 shows a Block Diagram.
8 8 8 6 3 3 8
I/O ports Port P0 Port P1 Port P2 Port P3 Port P4 Port P6
Peripheral functions
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A/D converter System clock
(10 bits × 12 channels) generation circuit
Timers
XIN-XOUT
Timer RA (8 bits) High-speed on-chip oscillator
Timer RB (8 bits) UART or Low-speed on-chip oscillator
Timer RD clock synchronous serial I/O XCIN-XCOUT
(16 bits × 2 channels) (8 bits × 2 channels)
Timer RE (8 bits)
I2C bus interface or clock synchronous

serial I/O with chip select
(8 bits × 1 channel)
LIN module
(1 channel)
Watchdog timer R8C/Tiny Series CPU core Memory

(15 bits)
R0H R0L SB ROM(1)
R1H R1L
USP
R2
R3 ISP
INTB RAM(2)
A0
PC
A1
FB FLG
Multiplier
NOTES:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
Figure 1.1 Block Diagram
Rev.3.00 Feb 29, 2008 Page 4 of 485

REJ09B0244-0300
1.4 Product Information

Table 1.3 lists the Product Information for R8C/24 Group and Table 1.4 lists the Product Information for R8C/25
Group.
Table 1.3 Product Information for R8C/24 Group Current of Feb. 2008
Type No. ROM Capacity RAM Capacity Package Type Remarks
R5F21244SNFP 16 Kbytes 1 Kbyte PLQP0052JA-A N version
R5F21245SNFP 24 Kbytes 2 Kbytes PLQP0052JA-A Blank product
R5F21246SNFP 32 Kbytes 2 Kbytes PLQP0052JA-A
R5F21247SNFP 48 Kbytes 2.5 Kbytes PLQP0052JA-A
R5F21248SNFP
www.DataSheet4U.com 64 Kbytes 3 Kbytes PLQP0052JA-A
R5F21244SNLG 16 Kbytes 1 Kbyte PTLG0064JA-A
R5F21246SNLG 32 Kbytes 2 Kbytes PTLG0064JA-A
R5F21244SDFP 16 Kbytes 1 Kbyte PLQP0052JA-A D version
R5F21245SDFP 24 Kbytes 2 Kbytes PLQP0052JA-A Blank product
R5F21246SDFP 32 Kbytes 2 Kbytes PLQP0052JA-A
R5F21247SDFP 48 Kbytes 2.5 Kbytes PLQP0052JA-A
R5F21248SDFP 64 Kbytes 3 Kbytes PLQP0052JA-A
R5F21244SNXXXFP 16 Kbytes 1 Kbyte PLQP0052JA-A N version
R5F21245SNXXXFP 24 Kbytes 2 Kbytes PLQP0052JA-A Factory
R5F21246SNXXXFP 32 Kbytes 2 Kbytes PLQP0052JA-A programming
R5F21247SNXXXFP 48 Kbytes 2.5 Kbytes PLQP0052JA-A product(1)
R5F21248SNXXXFP 64 Kbytes 3 Kbytes PLQP0052JA-A
R5F21244SNXXXLG 16 Kbytes 1 Kbyte PTLG0064JA-A
R5F21246SNXXXLG 32 Kbytes 2 Kbytes PTLG0064JA-A
R5F21244SDXXXFP 16 Kbytes 1 Kbyte PLQP0052JA-A D version
R5F21245SDXXXFP 24 Kbytes 2 Kbytes PLQP0052JA-A Factory
R5F21246SDXXXFP 32 Kbytes 2 Kbytes PLQP0052JA-A programming
R5F21247SDXXXFP 48 Kbytes 2.5 Kbytes PLQP0052JA-A product(1)
R5F21248SDXXXFP 64 Kbytes 3 Kbytes PLQP0052JA-A
NOTE:
1. The user ROM is programmed before shipment.
Rev.3.00 Feb 29, 2008 Page 5 of 485

REJ09B0244-0300
Type No. R 5 F 21 24 6 S N XXX FP

Package type:
FP: PLQP0052JA-A (0.65 mm pin-pitch, 10 mm square body)
LG: PTLG0064JA-A (0.65 mm pin-pitch, 6 mm square body)
ROM number
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
Y: Operating ambient temperature -20°C to 105°C(1)
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S: Low-voltage version
ROM capacity
4: 16 KB
5: 24 KB
6: 32 KB
7: 48 KB
8: 64 KB
R8C/24 Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
NOTE:
Figure 1.2 Type Number, Memory Size, and Package of R8C/24 Group
Rev.3.00 Feb 29, 2008 Page 6 of 485

REJ09B0244-0300
Table 1.4 Product Information for R8C/25 Group Current of Feb. 2008
ROM Capacity RAM
Type No. Package Type Remarks
Program ROM Data flash Capacity
R5F21254SNFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0052JA-A N version
R5F21255SNFP 24 Kbytes 1 Kbyte × 2 2 Kbytes PLQP0052JA-A Blank product
R5F21256SNFP 32 Kbytes 1 Kbyte × 2 2 Kbytes PLQP0052JA-A
R5F21257SNFP 48 Kbytes 1 Kbyte × 2 2.5 Kbytes PLQP0052JA-A
R5F21258SNFP 64 Kbytes 1 Kbyte × 2 3 Kbytes PLQP0052JA-A
R5F21254SNLG 16 Kbytes 1 Kbyte × 2 1 Kbyte PTLG0064JA-A
R5F21256SNLG
www.DataSheet4U.com 32 Kbytes 1 Kbyte × 2 2 Kbytes PTLG0064JA-A
R5F21254SDFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0052JA-A D version
R5F21255SDFP 24 Kbytes 1 Kbyte × 2 2 Kbytes PLQP0052JA-A Blank product
R5F21256SDFP 32 Kbytes 1 Kbyte × 2 2 Kbytes PLQP0052JA-A
R5F21257SDFP 48 Kbytes 1 Kbyte × 2 2.5 Kbytes PLQP0052JA-A
R5F21258SDFP 64 Kbytes 1 Kbyte × 2 3 Kbytes PLQP0052JA-A
R5F21254SNXXXFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0052JA-A N version
R5F21255SNXXXFP 24 Kbytes 1 Kbyte × 2 2 Kbytes PLQP0052JA-A Factory
R5F21256SNXXXFP 32 Kbytes 1 Kbyte × 2 2 Kbytes PLQP0052JA-A programming
R5F21257SNXXXFP 48 Kbytes 1 Kbyte × 2 2.5 Kbytes PLQP0052JA-A product(1)
R5F21258SNXXXFP 64 Kbytes 1 Kbyte × 2 3 Kbytes PLQP0052JA-A
R5F21254SNXXXLG 16 Kbytes 1 Kbyte × 2 1 Kbyte PTLG0064JA-A
R5F21256SNXXXLG 32 Kbytes 1 Kbyte × 2 2 Kbytes PTLG0064JA-A
R5F21254SDXXXFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0052JA-A D version
R5F21255SDXXXFP 24 Kbytes 1 Kbyte × 2 2 Kbytes PLQP0052JA-A Factory
R5F21256SDXXXFP 32 Kbytes 1 Kbyte × 2 2 Kbytes PLQP0052JA-A programming
R5F21257SDXXXFP 48 Kbytes 1 Kbyte × 2 2.5 Kbytes PLQP0052JA-A product(1)
R5F21258SDXXXFP 64 Kbytes 1 Kbyte × 2 3 Kbytes PLQP0052JA-A
NOTE:
1. The user ROM is programmed before shipment.
Rev.3.00 Feb 29, 2008 Page 7 of 485

REJ09B0244-0300
Type No. R 5 F 21 25 6 S N XXX FP

Package type:
FP: PLQP0052JA-A (0.65 mm pin-pitch, 10 mm square body)
LG: PTLG0064JA-A (0.65 mm pin-pitch, 6 mm square body)
ROM number
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
Y: Operating ambient temperature -20°C to 105°C(1)
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S: Low-voltage version
ROM capacity
4: 16 KB
5: 24 KB
6: 32 KB
7: 48 KB
8: 64 KB
R8C/25 Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
NOTE:
Figure 1.3 Type Number, Memory Size, and Package of R8C/25 Group
Rev.3.00 Feb 29, 2008 Page 8 of 485

REJ09B0244-0300
1.5 Pin Assignments

Figure 1.4 shows PLQP0052JA-A Package Pin Assignments (Top View). Figure 1.5 shows PTLG0064JA-A
Package Pin Assignments.
P6_7/INT3/RXD1
P6_6/INT2/TXD1
Pin assignments (top view)
P1_2/KI2/AN10
P1_0/KI0/AN8
P1_1/KI1/AN9
P3_0/TRAO
P3_1/TRBO
P6_5/CLK1
P4_5/INT0
P0_7/AN0
P6_3
P6_4
NC
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39
38
37
36
35
34
33
32
31
30
29
28
27
NC 40 26 NC
P0_6/AN1 41 25 P1_3/KI3/AN11
P0_5/AN2 42 24 P1_4/TXD0
P0_4/AN3 43 23 P1_5/RXD0/(TRAIO)/(INT1)(2)
P4_2/VREF 44 22 P1_6/CLK0
P6_0/TREO 45 21 P1_7/TRAIO/INT1
R8C/24 Group
P6_2 46 20 P2_0/TRDIOA0/TRDCLK
R8C/25 Group
P6_1 47 19 P2_1/TRDIOB0
P0_3/AN4 48 18 P2_2/TRDIOC0
P0_2/AN5 49 17 P2_3/TRDIOD0
P0_1/AN6 50 16 P2_4/TRDIOA1
P0_0/AN7 51 15 P2_5/TRDIOB1
P3_7/SSO 52 14 P2_6/TRDIOC1
10
11
12
13
1
2
3
4
5
6
7
8
9
P3_3/SSI
P2_7/TRDIOD1
XOUT/P4_7
P3_5/SCL/SSCK
P3_4/SDA/SCS
MODE
VSS/AVSS
P4_4/XCOUT
RESET
NC
P4_3/XCIN
P4_6/XIN
VCC/AVCC
(1)
Package: PLQP0052JA-A(52P6A-A)
0.65 mm pin pitch, 10 mm square body
NOTES:
1. P4_7 is an input-only port.
2. Can be assigned to the pin in parentheses by a program.
NC: Non-Connection
Figure 1.4 PLQP0052JA-A Package Pin Assignments (Top View)
Rev.3.00 Feb 29, 2008 Page 9 of 485

REJ09B0244-0300
Pin assignments (top perspective view)
A B C D E F G H
8
3 50 48 46 45 NC 36 NC
8
P3_3/SSI P0_1/AN6 P0_3/AN4 P6_2 P6_0/TREO P6_4
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7
4 51 49 NC 44 34 35 NC
7
P3_4/SDA/ P0_0/AN7 P0_2/AN5 P4_2/VREF P3_0/TRAO P6_5/CLK1
SCS
6
NC 5 52 47 43 42 NC 33 6
MODE P3_7/SSO P6_1 P0_4/AN3 P0_5/AN2 P3_1/TRBO
5
7 NC 6 2 37 NC 41 38 5
P4_4/XCOUT P4_3/XCIN P3_5/SCL/ P6_3 P0_6/AN1 P0_7/AN0
SSCK
4
13 12 NC 9 8 32 31 NC
4
P2_7/ VCC/AVCC XOUT/ RESET P1_0/KI0/ P1_1/KI1/
TRDIOD1 P4_7(1) AN8 AN9
3
NC 10 16 19 23 NC NC 30 3
VSS/AVSS P2_4/ P2_1/ P1_5/RXD0/ P1_2/KI2/
TRDIOA1 TRDIOB0 (TRAIO)/(INT1)(2) AN10
2
NC 11 17 20 NC 24 28 NC
2
XIN/P4_6 P2_3/ P2_0/TRDIOA0/ P1_4/TXD0 P6_6/INT2/
TRDIOD0 TRDCLK TXD1
1
14 15 18 21 22 25 27 29 1
P2_6/ P2_5/ P2_2/ P1_7/TRAIO/ P1_6/CLK0 P1_3/KI3/ P4_5/INT0 P6_7/INT3/
TRDIOC1 TRDIOB1 TRDIOC0 INT1 AN11 RXD1
A B C D E F G H
Package: PTLG0064JA-A(64F0G)
0.65 mm pin pitch, 6 mm square body
NOTES: R5F21244S
1. P4_7 is an input-only port. NLG
2. Can be assigned to the pin in parentheses by a program. JAPAN
3. In the figure, the numbers in circles are the pin numbers
of the 52-pin LQFP package (PLQP0052JA-A).
NC: Non-Connection
Pin assignments (top view)
Figure 1.5 PTLG0064JA-A Package Pin Assignments
Rev.3.00 Feb 29, 2008 Page 10 of 485

REJ09B0244-0300
1.6 Pin Functions

Table 1.5 lists Pin Functions.
Table 1.5 Pin Functions

Type Symbol I/O Type Description
Power supply input VCC, VSS I Apply 2.2 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.
Analog power AVCC, AVSS I Power supply for the A/D converter.
supply input Connect a capacitor between AVCC and AVSS.
Reset input RESET I Input “L” on this pin resets the MCU.
MODE MODE I Connect this pin to VCC via a resistor.
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XIN clock input XIN I These pins are provided for XIN clock generation circuit I/O.
Connect a ceramic resonator or a crystal oscillator between
XIN clock output XOUT O the XIN and XOUT pins. To use an external clock, input it to
the XIN pin and leave the XOUT pin open.
XCIN clock input XCIN I These pins are provided for XCIN clock generation circuit I/O.
Connect a crystal oscillator between the XCIN and XCOUT
XCIN clock output XCOUT O pins. To use an external clock, input it to the XCIN pin and
leave the XCOUT pin open.
INT interrupt input INT0 to INT3 I INT interrupt input pins.
INT0 is timer RD input pin. INT1 is timer RA input pin.
Key input interrupt KI0 to KI3 I Key input interrupt input pins
Timer RA TRAIO I/O Timer RA I/O pin
TRAO O Timer RA output pin
Timer RB TRBO O Timer RB output pin
Timer RD TRDIOA0, TRDIOA1, I/O Timer RD I/O ports
TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1,
TRDIOD0, TRDIOD1
TRDCLK I External clock input pin
Timer RE TREO O Divided clock output pin
Serial interface CLK0, CLK1 I/O Transfer clock I/O pin
RXD0, RXD1 I Serial data input pins
TXD0, TXD1 O Serial data output pins
I2C bus interface SCL I/O Clock I/O pin
SDA I/O Data I/O pin
Clock synchronous SSI I/O Data I/O pin
serial I/O with chip SCS I/O Chip-select signal I/O pin
select
SSCK I/O Clock I/O pin
SSO I/O Data I/O pin
Reference voltage VREF I Reference voltage input pin to A/D converter
input
A/D converter AN0 to AN11 I Analog input pins to A/D converter
I/O port P0_0 to P0_7, I/O CMOS I/O ports. Each port has an I/O select direction
P1_0 to P1_7, register, allowing each pin in the port to be directed for input
P2_0 to P2_7, or output individually.
P3_0, P3_1, Any port set to input can be set to use a pull-up resistor or not
P3_3 to P3_5, P3_7, by a program.
P4_3 to P4_5, P2_0 to P2_7 also function as LED drive ports.
P6_0 to P6_7
Input port P4_2, P4_6, P4_7 I Input-only ports
I: Input O: Output I/O: Input and output
Rev.3.00 Feb 29, 2008 Page 11 of 485

REJ09B0244-0300
Table 1.6 Pin Name Information by Pin Number

I/O Pin Functions for of Peripheral Modules
Clock
Pin
Control Pin Port Serial Synchronous I2C bus A/D
Number Interrupt Timer
Interface Serial I/O with Interface Converter
Chip Select
2 P3_5 SSCK SCL
3 P3_3 SSI
4 P3_4 SCS SDA
5 MODE
6 XCIN P4_3
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7 XCOUT P4_4
8 RESET
9 XOUT P4_7
10 VSS/AVSS
11 XIN P4_6
12 VCC/AVCC
13 P2_7 TRDIOD1
14 P2_6 TRDIOC1
15 P2_5 TRDIOB1
16 P2_4 TRDIOA1
17 P2_3 TRDIOD0
18 P2_2 TRDIOC0
19 P2_1 TRDIOB0
20 P2_0 TRDIOA0/TRDCLK
21 P1_7 INT1 TRAIO
22 P1_6 CLK0
23 P1_5 (INT1)(1) (TRAIO)(1) RXD0
24 P1_4 TXD0
25 P1_3 KI3 AN11
27 P4_5 INT0 INT0
28 P6_6 INT2 TXD1
29 P6_7 INT3 RXD1
30 P1_2 KI2 AN10
31 P1_1 KI1 AN9
32 P1_0 KI0 AN8
33 P3_1 TRBO
34 P3_0 TRAO
35 P6_5 CLK1
36 P6_4
37 P6_3
38 P0_7 AN0
41 P0_6 AN1
42 P0_5 AN2
43 P0_4 AN3
44 VREF P4_2
45 P6_0 TREO
46 P6_2
47 P6_1
48 P0_3 AN4
49 P0_2 AN5
50 P0_1 AN6
51 P0_0 AN7
52 P3_7 SSO
NOTE:
1. Can be assigned to the pin in parentheses by a program.
Rev.3.00 Feb 29, 2008 Page 12 of 485

REJ09B0244-0300
R8C/24 Group, R8C/25 Group 2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register bank.
b31 b15 b8b7 b0
R2 R0H (high-order of R0) R0L (low-order of R0)

R3 R1H (high-order of R1) R1L (low-order of R1)
Data registers(1)
R2
R3
www.DataSheet4U.com A0
Address registers(1)
A1
FB Frame base register(1)
b19 b15 b0
INTBH INTBL Interrupt table register
The 4 high order bits of INTB are INTBH and

the 16 low order bits of INTB are INTBL.
b19 b0
PC Program counter
b15 b0
USP User stack pointer
ISP Interrupt stack pointer
SB Static base register
b15 b0
FLG Flag register
b15 b8 b7 b0
IPL U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
NOTE:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1 CPU Registers
Rev.3.00 Feb 29, 2008 Page 13 of 485

REJ09B0244-0300
2.1 Data Registers (R0, R1, R2, and R3)

R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is
analogous to R2R0.
2.2 Address Registers (A0 and A1)

A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32-
bit address register (A1A0).
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2.3 Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4 Interrupt Table Register (INTB)

INTB is a 20-bit register that indicates the start address of an interrupt vector table.
2.5 Program Counter (PC)

PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7 Static Base Register (SB)

SB is a 16-bit register for SB relative addressing.
2.8 Flag Register (FLG)

FLG is an 11-bit register indicating the CPU state.
2.8.1 Carry Flag (C)

The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2 Debug Flag (D)

The D flag is for debugging only. Set it to 0.
2.8.3 Zero Flag (Z)

The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4 Sign Flag (S)

The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5 Register Bank Select Flag (B)

Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6 Overflow Flag (O)

The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
Rev.3.00 Feb 29, 2008 Page 14 of 485

REJ09B0244-0300
2.8.7 Interrupt Enable Flag (I)

The I flag enables maskable interrupts.
Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8 Stack Pointer Select Flag (U)

ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9
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Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit

If necessary, set to 0. When read, the content is undefined.
Rev.3.00 Feb 29, 2008 Page 15 of 485

REJ09B0244-0300
R8C/24 Group, R8C/25 Group 3. Memory
3. Memory
3.1 R8C/24 Group

Figure 3.1 is a Memory Map of R8C/24 Group. The R8C/24 group has 1 Mbyte of address space from addresses
00000h to FFFFFh.
The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 48-Kbyte internal
ROM area is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2-Kbyte internal
RAM area is allocated addresses 00400h to 00BFFh. The internal RAM is used not only for storing data but also
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for calling subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control
registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use
and cannot be accessed by users.
00000h
SFR
(Refer to 4. Special
Function Registers
(SFRs))
002FFh
00400h
Internal RAM
0XXXh
0FFDCh
Undefined instruction
Overflow
BRK instruction
Address match
Single step
0YYYYh Watchdog timer/oscillation stop detection/voltage monitor
Internal ROM (Reserved)

(program ROM) (Reserved)
Reset
0FFFFh 0FFFFh
Internal ROM
(program ROM)
1ZZZZh
FFFFFh
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Internal ROM Internal RAM

Part Number
Size Address 0YYYYh Address 1ZZZZh Size Address 0XXXXh
R5F21244SNFP, R5F21244SNXXXFP, 16 Kbytes 0C000h − 1 Kbyte 007FFh
R5F21244SDFP, R5F21244SDXXXFP,
R5F21244SNLG, R5F21244SNXXXLG
R5F21245SNFP, R5F21245SNXXXFP, 24 Kbytes 0A000h − 2 Kbytes 00BFFh
R5F21245SDFP, R5F21245SDXXXFP
R5F21246SNFP, R5F21246SNXXXFP, 32 Kbytes 08000h − 2 Kbytes 00BFFh
R5F21247SNFP, R5F21247SNXXXFP, 48 Kbytes 04000h − 2.5 Kbytes 00DFFh
R5F21248SNFP, R5F21248SNXXXFP, 64 Kbytes 04000h 13FFFh 3 Kbytes 00FFFh
Figure 3.1 Memory Map of R8C/24 Group
Rev.3.00 Feb 29, 2008 Page 16 of 485

REJ09B0244-0300
R8C/24 Group, R8C/25 Group 3. Memory
3.2 R8C/25 Group

Figure 3.2 is a Memory Map of R8C/25 Group. The R8C/25 group has 1 Mbyte of address space from addresses
00000h to FFFFFh.
The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a
48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal ROM (data flash) is allocated addresses 02400h to 02BFFh.
The internal RAM area is allocated higher addresses, beginning with address 00400h. For example, a 2-Kbyte
internal RAM is allocated addresses 00400h to 00BFFh. The internal RAM is used not only for storing data but
also for calling subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control
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registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use
and cannot be accessed by users.
00000h
SFR
(Refer to 4. Special
Function Registers
(SFRs))
002FFh
00400h
Internal RAM
0XXXXh
02400h
Internal ROM 0FFDCh
Undefined instruction
(data flash)(1) Overflow
02BFFh BRK instruction
Address match
Single step
0YYYYh Watchdog timer/oscillation stop detection/voltage monitor
Internal ROM (Reserved)

(program ROM) (Reserved)
Reset
0FFFFh 0FFFFh
Internal ROM
(program ROM)
1ZZZZh
FFFFFh
NOTES:
1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown.
Internal ROM Internal RAM

Part Number
Size Address 0YYYYh Address 1ZZZZh Size Address 0XXXXh
R5F21254SNFP, R5F21254SNXXXFP, 16 Kbytes 0C000h − 1 Kbyte 007FFh
R5F21255SNFP, R5F21255SNXXXFP, 24 Kbytes 0A000h − 2 Kbytes 00BFFh
R5F21256SNFP, R5F21256SNXXXFP, 32 Kbytes 08000h − 2 Kbytes 00BFFh
R5F21257SNFP, R5F21257SNXXXFP, 48 Kbytes 04000h − 2.5 Kbytes 00DFFh
R5F21258SNFP, R5F21258SNXXXFP, 64 Kbytes 04000h 13FFFh 3 Kbytes 00FFFh
Figure 3.2 Memory Map of R8C/25 Group
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REJ09B0244-0300
R8C/24 Group, R8C/25 Group 4. Special Function Registers (SFRs)
4. Special Function Registers (SFRs)

An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.7 list the special
function registers.
Table 4.1 SFR Information (1)(1)

Address Register Symbol After reset
0000h
0001h
0002h
0003h
0004h Processor Mode Register 0 PM0 00h
0005h Processor Mode Register 1 PM1 00h
0006h System Clock Control Register 0 CM0 01101000b
0007h
www.DataSheet4U.com System Clock Control Register 1 CM1 00100000b
0008h
0009h
000Ah Protect Register PRCR 00h
000Bh
000Ch Oscillation Stop Detection Register OCD 00000100b
000Dh Watchdog Timer Reset Register WDTR XXh
000Eh Watchdog Timer Start Register WDTS XXh
000Fh Watchdog Timer Control Register WDC 00X11111b
0010h Address Match Interrupt Register 0 RMAD0 00h
0011h 00h
0012h 00h
0013h Address Match Interrupt Enable Register AIER 00h
0014h Address Match Interrupt Register 1 RMAD1 00h
0015h 00h
0016h 00h
0017h
0018h
0019h
001Ah
001Bh
001Ch Count Source Protection Mode Register CSPR 00h
10000000b(6)
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h High-Speed On-Chip Oscillator Control Register 0 FRA0 00h
0024h High-Speed On-Chip Oscillator Control Register 1 FRA1 When shipping
0025h High-Speed On-Chip Oscillator Control Register 2 FRA2 00h
0026h
0027h
0028h Clock Prescaler Reset Flag CPSRF 00h
0029h High-Speed On-Chip Oscillator Control Register 4 FRA4 When shipping
002Ah
002Bh High-Speed On-Chip Oscillator Control Register 6 FRA6 When shipping
002Ch High-Speed On-Chip Oscillator Control Register 7 FRA7 When shipping
0030h
0031h Voltage Detection Register 1(2) VCA1 00001000b
0032h Voltage Detection Register 2(2) VCA2 00h(3)
00100000b(4)
0033h
0034h
0035h
0036h Voltage Monitor 1 Circuit Control Register(5) VW1C 00001000b
0037h Voltage Monitor 2 Circuit Control Register(5) VW2C 00h
0038h Voltage Monitor 0 Circuit Control Register(2) VW0C 0000X000b(3)
0100X001b(4)
0039h
003Ah
003Eh
003Fh
X: Undefined
NOTES:
2. Software reset, watchdog timer reset, and voltage monitor 1 reset or voltage monitor 2 reset do not affect this register.
3. The LVD0ON bit in the OFS register is set to 1 and hardware reset.
4. Power-on reset, voltage monitor 0 reset or the LVD0ON bit in the OFS register is set to 0, and hardware reset.
5. Software reset, watchdog timer reset, and voltage monitor 1 reset or voltage monitor 2 reset do not affect b2 and b3.
6. The CSPROINI bit in the OFS register is set to 0.
Rev.3.00 Feb 29, 2008 Page 18 of 485

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0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h Timer RD0 Interrupt Control Register TRD0IC XXXXX000b
0049h Timer RD1 Interrupt Control Register TRD1IC XXXXX000b
004Ah Timer RE Interrupt Control Register TREIC XXXXX000b
004Bh
www.DataSheet4U.com004Ch
004Dh Key Input Interrupt Control Register KUPIC XXXXX000b
004Eh A/D Conversion Interrupt Control Register ADIC XXXXX000b
004Fh SSU/IIC Interrupt Control Register(2) SSUIC / IICIC XXXXX000b
0050h
0051h UART0 Transmit Interrupt Control Register S0TIC XXXXX000b
0052h UART0 Receive Interrupt Control Register S0RIC XXXXX000b
0053h UART1 Transmit Interrupt Control Register S1TIC XXXXX000b
0054h UART1 Receive Interrupt Control Register S1RIC XXXXX000b
0055h INT2 Interrupt Control Register INT2IC XX00X000b
0056h Timer RA Interrupt Control Register TRAIC XXXXX000b
0057h
0058h Timer RB Interrupt Control Register TRBIC XXXXX000b
0059h INT1 Interrupt Control Register INT1IC XX00X000b
005Ah INT3 Interrupt Control Register INT3IC XX00X000b
005Bh
005Ch
005Dh INT0 Interrupt Control Register INT0IC XX00X000b
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
X: Undefined
NOTES:
2. Selected by the IICSEL bit in the PMR register.
Rev.3.00 Feb 29, 2008 Page 19 of 485

REJ09B0244-0300

0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
www.DataSheet4U.com008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h UART0 Transmit/Receive Mode Register U0MR 00h
00A1h UART0 Bit Rate Register U0BRG XXh
00A2h UART0 Transmit Buffer Register U0TB XXh
00A3h XXh
00A4h UART0 Transmit/Receive Control Register 0 U0C0 00001000b
00A5h UART0 Transmit/Receive Control Register 1 U0C1 00000010b
00A6h UART0 Receive Buffer Register U0RB XXh
00A7h XXh
00A8h UART1 Transmit/Receive Mode Register U1MR 00h
00A9h UART1 Bit Rate Register U1BRG XXh
00AAh UART1 Transmit Buffer Register U1TB XXh
00ABh XXh
00ACh UART1 Transmit/Receive Control Register 0 U1C0 00001000b
00ADh UART1 Transmit/Receive Control Register 1 U1C1 00000010b
00AEh UART1 Receive Buffer Register U1RB XXh
00AFh XXh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h SS Control Register H / IIC bus Control Register 1(2) SSCRH / ICCR1 00h
00B9h SS Control Register L / IIC bus Control Register 2(2) SSCRL / ICCR2 01111101b
00BAh SS Mode Register / IIC bus Mode Register(2) SSMR / ICMR 00011000b
00BBh SS Enable Register / IIC bus Interrupt Enable Register(2) SSER / ICIER 00h
00BCh SS Status Register / IIC bus Status Register(2) SSSR / ICSR 00h / 0000X000b
00BDh SS Mode Register 2 / Slave Address Register(2) SSMR2 / SAR 00h
00BEh SS Transmit Data Register / IIC bus Transmit Data Register(2) SSTDR / ICDRT FFh
00BFh SS Receive Data Register / IIC bus Receive Data Register(2) SSRDR / ICDRR FFh
X: Undefined
NOTES:
2. Selected by the IICSEL bit in the PMR register.
Rev.3.00 Feb 29, 2008 Page 20 of 485

REJ09B0244-0300

00C0h A/D Register AD XXh
00C1h XXh
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
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00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h A/D Control Register 2 ADCON2 00h
00D5h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h Port P0 Register P0 XXh
00E2h Port P0 Direction Register PD0 00h
00E9h
00EAh Port P4 Direction Register PD4 00h
00EBh
00ECh Port P6 Register P6 XXh
00EDh
00EEh Port P6 Direction Register PD6 00h
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h Port P2 Drive Capacity Control Register P2DRR 00h
00F5h UART1 Function Select Register U1SR XXh
00F6h
00F7h
00F8h Port Mode Register PMR 00h
00F9h External Input Enable Register INTEN 00h
00FAh INT Input Filter Select Register INTF 00h
00FBh Key Input Enable Register KIEN 00h
00FCh Pull-Up Control Register 0 PUR0 00h
00FDh Pull-Up Control Register 1 PUR1 XX00XX00b
00FEh
00FFh
X: Undefined
NOTE:
Rev.3.00 Feb 29, 2008 Page 21 of 485

REJ09B0244-0300

0100h Timer RA Control Register TRACR 00h
0101h Timer RA I/O Control Register TRAIOC 00h
0102h Timer RA Mode Register TRAMR 00h
0103h Timer RA Prescaler Register TRAPRE FFh
0104h Timer RA Register TRA FFh
0105h
0106h LIN Control Register LINCR 00h
0107h LIN Status Register LINST 00h
0108h Timer RB Control Register TRBCR 00h
0109h Timer RB One-Shot Control Register TRBOCR 00h
010Ah Timer RB I/O Control Register TRBIOC 00h
010Bh Timer RB Mode Register TRBMR 00h
010Ch Timer RB Prescaler Register TRBPRE FFh
www.DataSheet4U.com010Dh Timer RB Secondary Register TRBSC FFh
010Eh Timer RB Primary Register TRBPR FFh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h Timer RE Second Data Register / Counter Data Register TRESEC 00h
0119h Timer RE Minute Data Register / Compare Data Register TREMIN 00h
011Ah Timer RE Hour Data Register TREHR 00h
011Bh Timer RE Day of Week Data Register TREWK 00h
011Ch Timer RE Control Register 1 TRECR1 00h
011Dh Timer RE Control Register 2 TRECR2 00h
011Eh Timer RE Count Source Select Register TRECSR 00001000b
011Fh
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h Timer RD Start Register TRDSTR 11111100b
0138h Timer RD Mode Register TRDMR 00001110b
0139h Timer RD PWM Mode Register TRDPMR 10001000b
013Ah Timer RD Function Control Register TRDFCR 10000000b
013Bh Timer RD Output Master Enable Register 1 TRDOER1 FFh
013Ch Timer RD Output Master Enable Register 2 TRDOER2 01111111b
013Dh Timer RD Output Control Register TRDOCR 00h
013Eh Timer RD Digital Filter Function Select Register 0 TRDDF0 00h
013Fh Timer RD Digital Filter Function Select Register 1 TRDDF1 00h
X: Undefined
NOTE:
Rev.3.00 Feb 29, 2008 Page 22 of 485

REJ09B0244-0300

0140h Timer RD Control Register 0 TRDCR0 00h
0141h Timer RD I/O Control Register A0 TRDIORA0 10001000b
0142h Timer RD I/O Control Register C0 TRDIORC0 10001000b
0143h Timer RD Status Register 0 TRDSR0 11100000b
0144h Timer RD Interrupt Enable Register 0 TRDIER0 11100000b
0145h Timer RD PWM Mode Output Level Control Register 0 TRDPOCR0 11111000b
0146h Timer RD Counter 0 TRD0 00h
0147h 00h
0148h Timer RD General Register A0 TRDGRA0 FFh
0149h FFh
014Ah Timer RD General Register B0 TRDGRB0 FFh
014Bh FFh
014Ch Timer RD General Register C0 TRDGRC0 FFh
www.DataSheet4U.com014Dh FFh
014Eh Timer RD General Register D0 TRDGRD0 FFh
014Fh FFh
0150h Timer RD Control Register 1 TRDCR1 00h
0151h Timer RD I/O Control Register A1 TRDIORA1 10001000b
0152h Timer RD I/O Control Register C1 TRDIORC1 10001000b
0153h Timer RD Status Register 1 TRDSR1 11000000b
0154h Timer RD Interrupt Enable Register 1 TRDIER1 11100000b
0155h Timer RD PWM Mode Output Level Control Register 1 TRDPOCR1 11111000b
0156h Timer RD Counter 1 TRD1 00h
0157h 00h
0158h Timer RD General Register A1 TRDGRA1 FFh
0159h FFh
015Ah Timer RD General Register B1 TRDGRB1 FFh
015Bh FFh
015Ch Timer RD General Register C1 TRDGRC1 FFh
015Dh FFh
015Eh Timer RD General Register D1 TRDGRD1 FFh
015Fh FFh
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
X: Undefined
NOTE:
Rev.3.00 Feb 29, 2008 Page 23 of 485

REJ09B0244-0300

0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
www.DataSheet4U.com018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h Flash Memory Control Register 4 FMR4 01000000b
01B4h
01B5h Flash Memory Control Register 1 FMR1 1000000Xb
01B6h
01B7h Flash Memory Control Register 0 FMR0 00000001b
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
FFFFh Option Function Select Register OFS (Note 2)

X: Undefined
NOTES:
2. The OFS register cannot be changed by a program. Use a flash programmer to write to it.
Rev.3.00 Feb 29, 2008 Page 24 of 485

REJ09B0244-0300
R8C/24 Group, R8C/25 Group 5. Resets
5. Resets
The following resets are implemented: hardware reset, power-on reset, voltage monitor 0 reset, voltage monitor 1
reset, voltage monitor 2 reset, watchdog timer reset, and software reset.
Table 5.1 lists the Reset Names and Sources.
Table 5.1 Reset Names and Sources

Reset Name Source
Hardware reset Input voltage of RESET pin is held “L”
Power-on reset VCC rises
Voltage monitor 0 reset VCC falls (monitor voltage: Vdet0)
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Watchdog timer reset Underflow of watchdog timer
Software reset Write 1 to PM03 bit in PM0 register
Hardware reset
RESET SFRs
Bits VCA25,
VW0C0, and
VW0C6
SFRs
Bits VCA25,
VW0C0, and
Power-on reset Power-on reset VW0C6
VCC
circuit
Voltage monitor 0 reset SFRs

Voltage Bits VCA13, VCA26, VCA27,
Voltage monitor 1 reset VW1C2, VW1C3,
detection
VW2C2, VW2C3,
circuit VW0C1, VW0F0,
Voltage monitor 2 VW0F1, and VW0C7
reset
Watchdog timer
Watchdog reset
timer
Pin, CPU, and
SFR bits other than
those listed above
CPU
Software reset
VCA13: Bit in VCA1 register

VCA25, VCA26, VCA27: Bits in VCA2 register
VW0C0, VW0C1, VW0C6, VW0F0, VW0F1, VW0C7: Bits in VW0C register
VW1C2, VW1C3: Bits in VW1C register
Figure 5.1 Block Diagram of Reset Circuit
Rev.3.00 Feb 29, 2008 Page 25 of 485

REJ09B0244-0300
Table 5.2 shows the Pin Functions while RESET Pin Level is “L”, Figure 5.2 shows the CPU Register Status after
Reset, Figure 5.3 shows the Reset Sequence, and Figure 5.4 shows the OFS Register.
Table 5.2 Pin Functions while RESET Pin Level is “L”

Pin Name Pin Functions
P0, P1, P2 Input port
P3_0, P3_1, P3_3 to P3_5, P3_7 Input port
P4_2 to P4_7 Input port
P6 Input port
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b15 b0
0000h Data register(R0)

0000h Address register(A0)
0000h Address register(A1)
0000h Frame base register(FB)
b19 b0
00000h Interrupt table register(INTB)

Content of addresses 0FFFEh to 0FFFCh Program counter(PC)
b15 b0
0000h User stack pointer(USP)
0000h Interrupt stack pointer(ISP)
0000h Static base register(SB)
b15 b0
0000h Flag register(FLG)
b15 b8 b7 b0
IPL U I O B S Z D C
Figure 5.2 CPU Register Status after Reset
Rev.3.00 Feb 29, 2008 Page 26 of 485

REJ09B0244-0300
fOCO-S
RESET pin
10 cycles or more are needed(1)
fOCO-S clock × 32 cycles(2)
Internal reset
signal
Start time of flash memory
CPU clock × 28 cycles
(CPU clock × 14 cycles)
CPU clock
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0FFFCh 0FFFEh
Address
(internal address
signal)
0FFFDh Content of reset vector
NOTES:
1. Hardware reset.
2. When the “L” input width to the RESET pin is set to fOCO-S clock × 32 cycles or more, setting the RESET pin to “H” also sets the internal
reset signal to “H” at the same.
Figure 5.3 Reset Sequence
Option Function Select Register(1)

b7 b6 b5 b4 b3 b2 b1 b0
1 1 1 Symbol Address When Shipping

OFS 0FFFFh FFh(3)
Watchdog timer start 0 : Starts w atchdog timer automatically after reset
WDTON RW
select bit 1 : Watchdog timer is inactive after reset
— Reserved bit Set to 1.
RW
(b1)
ROM code protect 0 : ROM code protect disabled
ROMCR RW
disabled bit 1 : ROMCP1 enabled
ROM code protect bit 0 : ROM code protect enabled
ROMCP1 RW
1 : ROM code protect disabled
RW
(b4)
Voltage detection 0 0 : Voltage monitor 0 reset enabled after hardw are
circuit start bit(2) reset
LVD0ON 1 : Voltage monitor 0 reset disabled after hardw are RW
reset
RW
(b6)
Count source protect 0 : Count source protect mode enabled after reset
CSPROINI mode after reset select 1 : Count source protect mode disabled after reset RW
bit
NOTES:
1. The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not
w rite additions to the OFS register.
2. To use the pow er-on reset, set the LVD0ON bit to 0 (voltage monitor 0 reset enabled after reset).
3. If the block including the OFS register is erased, FFh is set to the OFS register.
Figure 5.4 OFS Register
Rev.3.00 Feb 29, 2008 Page 27 of 485

REJ09B0244-0300
5.1 Hardware Reset

A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the supply voltage
meets the recommended operating conditions, pins, CPU, and SFRs are all reset (refer to Table 5.2 Pin Functions
while RESET Pin Level is “L”). When the input level applied to the RESET pin changes from “L” to “H”, a
program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip
oscillator clock divided by 8 is automatically selected as the CPU clock.
Refer to 4. Special Function Registers (SFRs) for the state of the SFRs after reset.
The internal RAM is not reset. If the RESET pin is pulled “L” while writing to the internal RAM is in progress, the
contents of internal RAM will be undefined.
Figure 5.5 shows an Example of Hardware Reset Circuit and Operation and Figure 5.6 shows an Example of
Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation.
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5.1.1 When Power Supply is Stable
(1) Apply “L” to the RESET pin.
(2) Wait for 10 µs or more.
(3) Apply “H” to the RESET pin.
5.1.2 Power On
(1) Apply “L” to the RESET pin.
(2) Let the supply voltage increase until it meets the recommended operating conditions.
(3) Wait for td(P-R) or more to allow the internal power supply to stabilize (refer to 20. Electrical
Characteristics).
(4) Wait for 10 µs or more.
(5) Apply “H” to the RESET pin.
Rev.3.00 Feb 29, 2008 Page 28 of 485

REJ09B0244-0300
VCC 2.2 V
VCC
0V
RESET
RESET
0.2 VCC or below
0V
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td(P-R) + 10 µs or more
NOTE:
1. Refer to 20. Electrical Characteristics.
Figure 5.5 Example of Hardware Reset Circuit and Operation
5V
Supply voltage
detection circuit
VCC 2.2 V
RESET VCC
0V
5V
RESET
0V
td(P-R) + 10 µs or more
Example when
VCC = 5 V
NOTE:
Figure 5.6 Example of Hardware Reset Circuit (Usage Example of External Supply Voltage
Detection Circuit) and Operation
Rev.3.00 Feb 29, 2008 Page 29 of 485

REJ09B0244-0300
5.2 Power-On Reset Function

When the RESET pin is connected to the VCC pin via a pull-up resistor, and the VCC pin voltage level rises while
the rise gradient is trth or more, the power-on reset function is enabled and the MCU resets its pins, CPU, and SFR.
When a capacitor is connected to the RESET pin, too, always keep the voltage to the RESET pin 0.8VCC or more.
When the input voltage to the VCC pin reaches the Vdet0 level or above, the low-speed on-chip oscillator clock
starts counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held “H”
and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock divided by 8 is
automatically selected as the CPU clock after reset.
Refer to 4. Special Function Registers (SFRs) for the states of the SFR after power-on reset.
The voltage monitor 0 reset is enabled after power-on reset.
Figure 5.7 shows an Example of Power-On Reset Circuit and Operation.
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VCC
4.7 kΩ
(reference)
RESET
Vdet0(3) Vdet0(3)
2.2V trth
External trth
Power VCC
Vpor2
Vpor1
tw(por1) Sampling time(1, 2)
Internal
reset signal
(“L” valid)
1 1
× 32 × 32
fOCO-S fOCO-S
NOTES:
1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage
range (2.2 V or above) during the sampling time.
2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details.
3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit for details.
5. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS
register to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the
VCA2 register to 1.
Figure 5.7 Example of Power-On Reset Circuit and Operation
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REJ09B0244-0300
5.3 Voltage Monitor 0 Reset

A reset is applied using the on-chip voltage detection 0 circuit. The voltage detection 0 circuit monitors the input
voltage to the VCC pin. The voltage to monitor is Vdet0.
When the input voltage to the VCC pin reaches the Vdet0 level or below, the pins, CPU, and SFR are reset.
When the input voltage to the VCC pin reaches the Vdet0 level or above, the low-speed on-chip oscillator clock
start counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held “H”
and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock divided by 8 is
automatically selected as the CPU clock after reset.
The LVD0ON bit in the OFS register can be used to enable or disable voltage monitor 0 reset after a hardware reset.
Setting the LVD0ON bit is only valid after a hardware reset.
To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register
to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register
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to 1.
The LVD0ON bit cannot be changed by a program. To set the LVD0ON bit, write 0 (voltage monitor 0 reset
enabled after hardware reset) or 1 (voltage monitor 0 reset disabled after hardware reset) to bit 5 of address 0FFFFh
using a flash programmer.
Refer to Figure 5.4 OFS Register for details of the OFS register.
Refer to 4. Special Function Registers (SFRs) for the status of the SFR after voltage monitor 0 reset.
The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet0 level or below while
writing to the internal RAM is in progress, the contents of internal RAM are undefined.
Refer to 6. Voltage Detection Circuit for details of voltage monitor 0 reset.

When the input voltage to the VCC pin reaches the Vdet1 level or below, the pins, CPU, and SFR are reset and a
program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip
The voltage monitor 1 does not reset some portions of the SFR. Refer to 4. Special Function Registers (SFRs) for
details.

When the input voltage to the VCC pin reaches the Vdet2 level or below, the pins, CPU, and SFR are reset and the
program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on-chip
The voltage monitor 2 does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details.
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REJ09B0244-0300
5.6 Watchdog Timer Reset

When the PM12 bit in the PM1 register is set to 1 (reset when watchdog timer underflows), the MCU resets its pins,
CPU, and SFR if the watchdog timer underflows. Then the program beginning with the address indicated by the
reset vector is executed. After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected as
the CPU clock.
The watchdog timer reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details.
The internal RAM is not reset. When the watchdog timer underflows, the contents of internal RAM are undefined.
Refer to 13. Watchdog Timer for details of the watchdog timer.
5.7 Software Reset

When the PM03 bit in the PM0 register is set to 1 (MCU reset), the MCU resets its pins, CPU, and SFR. The
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program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on-chip
oscillator clock divided by 8 is automatically selected for the CPU clock.
The software reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details.
The internal RAM is not reset.
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REJ09B0244-0300
R8C/24 Group, R8C/25 Group 6. Voltage Detection Circuit
6. Voltage Detection Circuit

The voltage detection circuit monitors the input voltage to the VCC pin. This circuit can be used to monitor the VCC
input voltage by a program. Alternately, voltage monitor 0 reset, voltage monitor 1 interrupt, voltage monitor 1 reset,
voltage monitor 2 interrupt, and voltage monitor 2 reset can also be used.
Table 6.1 lists the Specifications of Voltage Detection Circuit and Figures 6.1 to 6.4 show the Block Diagrams. Figures
6.5 to 6.8 show the Associated Registers.
Table 6.1 Specifications of Voltage Detection Circuit

Item Voltage Detection 0 Voltage Detection 1 Voltage Detection 2
VCC Monitor Voltage to monitor Vdet0 Vdet1 Vdet2
Detection target Whether passing Passing through Vdet1 by Passing through Vdet2 by
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through Vdet0 by rising rising or falling rising or falling
or falling
Monitor None VW1C3 bit in VW1C VCA13 bit in VCA1
register register
Whether VCC is higher or Whether VCC is higher or
lower than Vdet1 lower than Vdet2
Process Reset Voltage monitor 0 reset Voltage monitor 1 reset Voltage monitor 2 reset
When Voltage Reset at Vdet0 > VCC; Reset at Vdet1 > VCC; Reset at Vdet2 > VCC;
is Detected restart CPU operation restart CPU operation restart CPU operation
at VCC > Vdet0 after a specified time after a specified time
Interrupt None Voltage monitor 1 Voltage monitor 2
interrupt interrupt
Interrupt request at Vdet1 Interrupt request at Vdet2
> VCC and VCC > Vdet1 > VCC and VCC > Vdet2
when digital filter is when digital filter is
enabled; enabled;
interrupt request at Vdet1 interrupt request at Vdet2
> VCC or VCC > Vdet1 > VCC or VCC > Vdet2
when digital filter is when digital filter is
disabled disabled
Digital Filter Switch Available Available Available
enabled/disabled
Sampling time (Divide-by-n of fOCO-S) (Divide-by-n of fOCO-S) (Divide-by-n of fOCO-S)
×4 ×4 ×4
n: 1, 2, 4, and 8 n: 1, 2, 4, and 8 n: 1, 2, 4, and 8
Rev.3.00 Feb 29, 2008 Page 33 of 485

REJ09B0244-0300
VCC VCA27
Noise Voltage detection 2

+ signal
Internal filter
reference -
≥ Vdet2
voltage VCA1 register
b3
VCA26 VCA13 bit

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Voltage detection 1
+ Noise
signal
filter
-
≥ Vdet1
VW1C register
b3
VCA25 VW1C3 bit
Voltage detection 0
+ signal
-
≥ Vdet0
Figure 6.1 Block Diagram of Voltage Detection Circuit
Voltage monitor 0 reset generation circuit
VW0F1 to VW0F0
= 00b
= 01b
Voltage detection 0 circuit = 10b
= 11b
fOCO-S 1/2 1/2 1/2
VCA25
VW0C1
VCC +
Digital
Internal Voltage filter
- detection 0
reference
voltage signal
Voltage detection 0
signal is held “H” when Voltage monitor 0
VCA25 bit is set to 0 VW0C1 reset signal
(disabled)
VW0C0
VW0C7 VW0C6
VW0C0 to VW0C1, VW0F0 to VW0F1, VW0C6, VW0C7: Bits in VW0C register

Figure 6.2 Block Diagram of Voltage Monitor 0 Reset Generation Circuit
Rev.3.00 Feb 29, 2008 Page 34 of 485

REJ09B0244-0300
Voltage monitor 1 interrupt/reset generation circuit
VW1F1 to VW1F0
= 00b
= 01b
Voltage detection 1 circuit = 10b VW1C2 bit is set to 0 (not detected) by
writing 0 by a program.
= 11b When VCA26 bit is set to 0 (voltage
fOCO-S 1/2 1/2 1/2
detection 1 circuit disabled), VW1C2
VCA26 bit is set to 0
VW1C1
VW1C3 Watchdog
timer interrupt
VCC + signal
Digital
Noise filter
Voltage filter
Internal - VW1C2
reference detection
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voltage (Filter width: 200 ns) 1 signal
Voltage detection 1 signal
Voltage monitor 1
is held “H” when VCA26 bit
interrupt signal Non-maskable
is set to 0 (disabled)
interrupt signal
VW1C1
Oscillation stop
detection
interrupt signal
VW1C7
VW1C0
VW1C6 Voltage monitor 1
reset signal
VW1C0 to VW1C3, VW1F0, VW1F1, VW1C6, VW1C7: Bits in VW1C register

Figure 6.3 Block Diagram of Voltage Monitor 1 Interrupt/Reset Generation Circuit
Voltage monitor 2 interrupt/reset generation circuit
VW2F1 to VW2F0
= 00b
= 01b
Voltage detection 2 circuit = 10b VW2C2 bit is set to 0 (not detected) by
= 11b writing 0 by a program.
fOCO-S 1/2 1/2 1/2 When VCA27 bit is set to 0 (voltage
detection 2 circuit disabled), VW2C2
VCA27
bit is set to 0
VCA13 VW2C1
Watchdog
timer interrupt
VCC + signal
Digital
Noise filter
Voltage filter
Internal - VW2C2
reference detection
(Filter width: 200 ns) 2 signal
voltage
Voltage detection 2 signal
is held “H” when VCA27 bit Voltage monitor 2
is set to 0 (disabled) interrupt signal Non-maskable
interrupt signal
VW2C1
Oscillation stop
detection
Watchdog timer block interrupt signal
VW2C3
VW2C7
Watchdog timer
underflow signal This bit is set to 0 (not detected) by writing 0 VW2C0
by a program. VW2C6 Voltage monitor 2
reset signal
VW2C0 to VW2C3, VW2F0, VW2F1, VW2C6, VW2C7: Bits in VW2C register

Figure 6.4 Block Diagram of Voltage Monitor 2 Interrupt/Reset Generation Circuit
Rev.3.00 Feb 29, 2008 Page 35 of 485

REJ09B0244-0300
Voltage Detection Register 1

b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 0 Symbol Address After Reset(2)

VCA1 0031h 00001000b
— Reserved bits Set to 0.
RW
(b2-b0)
Voltage detection 2 signal monitor 0 : VCC < Vdet2
VCA13 flag(1) 1 : VCC ≥ Vdet2 or voltage detection 2 RO
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RW
(b7-b4)
NOTES:
1. The VCA13 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled).
The VCA13 bit is set to 1 (VCC ≥ Vdet 2) w hen the VCA27 bit in the VCA2 register is set to 0 (voltage detection 2
circuit disabled).
2. The softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this
register.
Voltage Detection Register 2(1)

b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 Symbol Address After Reset(5)

The LVD0ON bit in the OFS register is
set to 1 and hardw are reset : 00h
Pow er-on reset, voltage monitor 0 reset
or LVD0ON bit in the OFS register is
VCA2 0032h set to 0, and hardw are reset : 00100000b
Internal pow er low 0 : Disables low consumption
VCA20 RW
consumption enable bit(6) 1 : Enables low consumption
RW
(b4-b1)
Voltage detection 0 enable 0 : Voltage detection 0 circuit disabled
VCA25 RW
bit(2) 1 : Voltage detection 0 circuit enabled
VCA26 RW
VCA27 RW
NOTES:
1. Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VCA2 register.
2. To use the voltage monitor 0 reset, set the VCA25 bit to 1.
After the VCA25 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
3. To use the voltage monitor 1 interrupt/reset or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1.
operation.
4. To use the voltage monitor 2 interrupt/reset or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1.
operation.
5. Softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this
register.
6. Use the VCA20 bit only w hen entering to w ait mode. To set the VCA20 bit, follow the procedure show n in Figure
10.9 Procedure for Enabling Reduced Internal Pow er Consum ption Using VCA20 bit.
Figure 6.5 Registers VCA1 and VCA2
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Voltage Monitor 0 Circuit Control Register(1)

b7 b6 b5 b4 b3 b2 b1 b0
0 Symbol Address After Reset(2)

set to 1 and hardw are reset : 0000X000b
or LVD0ON bit in the OFS register is set
VW0C 0038h to 0, and hardw are reset : 0100X001b
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Voltage monitor 0 reset 0 : Disable
VW0C0 RW
enable bit(3) 1 : Enable
Voltage monitor 0 digital filter 0 : Digital filter enabled mode
disable mode select bit (digital filter circuit enabled)
VW0C1 1 : Digital filter disabled mode RW
(digital filter circuit disabled)
Reserved bit Set to 0.
VW0C2 RW
— Reserved bit When read, the content is undefined.

RO
(b3)
Sampling clock select bits b5 b4
VW0F0 0 0 : fOCO-S divided by 1 RW
0 1 : fOCO-S divided by 2
VW0F1 RW
Voltage monitor 0 circuit When the VW0C0 bit is set to 1 (voltage monitor 0
VW0C6 mode select bit reset enabled), set to 1. RW
Voltage monitor 0 reset When the VW0C1 bit is set to 1 (digital filter
VW0C7 generation condition select disabled mode), set to 1. RW
bit(4)
NOTES:
1. Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VW0C register.
2. The value remains unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage
monitor 2 reset.
3. The VW0C0 bit is enabled w hen the VCA25 bit in the VCA2 register is set to 1 (voltage detection 0 circuit
enabled). Set the VW0C0 bit to 0 (disable), w hen the VCA25 bit is set to 0 (voltage detection 0 circuit disabled).
4. The VW0C7 bit is enabled w hen the VW0C1 bit set to 1 (digital filter disabled mode).
Figure 6.6 VW0C Register
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b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After Reset(8)

VW1C 0036h 00001000b
Voltage monitor 1 interrupt/reset 0 : Disable
VW1C0 RW
disable mode select bit(2) (digital filter circuit enabled)
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Voltage change detection 0 : Not detected
VW1C2 RW
flag(3, 4, 8) 1 : Vdet1 crossing detected
Voltage detection 1 signal monitor 0 : VCC < Vdet1
VW1C3 flag(3, 8) 1 : VCC ≥ Vdet1 or voltage detection 1 RO
circuit disabled
VW1F1 RW
Voltage monitor 1 circuit mode 0 : Voltage monitor 1 interrupt mode
VW1C6 RW
select bit(5) 1 : Voltage monitor 1 reset mode
Voltage monitor 1 interrupt/reset 0 : When VCC reaches Vdet1 or above
generation condition select bit(7, 9) 1 : When VCC reaches Vdet1 or below
VW1C7 RW
NOTES:
1. Set the PRC3 bit in the PRCR register to 1 (rew rite enable) before w riting to the VW1C register.
2. To use the voltage monitor 1 interrupt to exit stop mode and to return again, w rite 0 to the VW1C1 bit before w riting
1.
3. Bits VW1C2 and VW1C3 are enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit
enabled).
4. Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is
w ritten to it).
5. The VW1C6 bit is enabled w hen the VW1C0 bit is set to 1 (voltage monitor 1 interrupt/enabled reset).
6. The VW1C0 bit is enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit enabled).
Set the VW1C0 bit to 0 (disable) w hen the VCA26 bit is set to 0 (voltage detection 1 circuit disabled).
7. The VW1C7 bit is enabled w hen the VW1C1 bit is set to 1 (digital filter disabled mode).
8. Bits VW1C2 and VW1C3 remain unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset,
or voltage monitor 2 reset.
9. When the VW1C6 bit is set to 1 (voltage monitor 1 reset mode), set the VW1C7 bit to 1 (w hen VCC reaches Vdet1 or
below ). (Do not set to 0.)
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b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After Reset(8)

VW2C 0037h 00h
Voltage monitor 2 interrupt/reset 0 : Disable
VW2C0 RW
disable mode select bit(2) (digital filter circuit enabled)
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Voltage change detection 0 : Not detected
VW2C2 RW
flag(3, 4, 8) 1 : VCC has crossed Vdet2
WDT detection flag(4, 8) 0 : Not detected
VW2C3 RW
1 : Detected
VW2F1 RW
Voltage monitor 2 circuit mode 0 : Voltage monitor 2 interrupt mode
VW2C6 RW
select bit(5) 1 : Voltage monitor 2 reset mode
Voltage monitor 2 interrupt/reset 0 : When VCC reaches Vdet2 or above
generation condition select bit(7, 9) 1 : When VCC reaches Vdet2 or below
VW2C7 RW
NOTES:
1. Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VW2C register.
2. To use the voltage monitor 2 interrupt to exit stop mode and to return again, w rite 0 to the VW2C1
bit before w riting 1.
enabled).
4. Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is
w ritten to it).
5. The VW2C6 bit is enabled w hen the VW2C0 bit is set to 1 (voltage monitor 2 interrupt/enables reset).
enabled). Set the VW2C0 bit to 0 (disable) w hen the VCA27 bit is set to 0 (voltage detection 2 circuit disabled).
7. The VW2C7 bit is enabled w hen the VW2C1 bit is set to 1 (digital filter disabled mode).
8. Bits VW2C2 and VW2C3 remain unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset,
or voltage monitor 2 reset.
9. When the VW2C6 bit is set to 1 (voltage monitor 2 reset mode), set the VW2C7 bit to 1 (w hen VCC reaches Vdet2
or below ). (Do not set to 0.)
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6.1 VCC Input Voltage
6.1.1 Monitoring Vdet0

Vdet0 cannot be monitored.

Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled). After td(E-A) has elapsed
(refer to 20. Electrical Characteristics), Vdet1 can be monitored by the VW1C3 bit in the VW1C register.

www.DataSheet4U.com Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled). After td(E-A) has elapsed
(refer to 20. Electrical Characteristics), Vdet2 can be monitored by the VCA13 bit in the VCA1 register.
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Table 6.2 lists the Procedure for Setting Bits Associated with Voltage Monitor Reset and Figure 6.9 shows an
Example of Voltage Monitor 0 Reset Operation. To use the voltage monitor 0 reset to exit stop mode, set the
VW0C1 bit in the VW0C register to 1 (digital filter disabled).
Table 6.2 Procedure for Setting Bits Associated with Voltage Monitor Reset
Step When Using Digital Filter When Not Using Digital Filter
1 Set the VCA25 bit in the VCA2 register to 1 (voltage detection 0 circuit enabled)
2 Wait for td(E-A)
Select the sampling clock of the digital filter Set the VW0C7 bit in the VW0C register to
www.DataSheet4U.com 3 by the VW0F0 to VW0F1 bits in the VW0C 1
register
Set the VW0C1 bit in the VW0C register to Set the VW0C1 bit in the VW0C register to
4(1)
0 (digital filter enabled) 1 (digital filter disabled)
5(1) Set the VW0C6 bit in the VW0C register to 1 (voltage monitor 0 reset mode)
6 Set the VW0C2 bit in the VW0C register to 0
7 Set the CM14 bit in the CM1 register to 0 −
(low-speed on-chip oscillator on)
8 Wait for 4 cycles of the sampling clock of − (No wait time required)
the digital filter
9 Set the VW0C0 bit in the VW0C register to 1 (voltage monitor 0 reset enabled)
NOTE:
1. When the VW0C0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1
instruction).
VCC
Vdet0
1
× 32
Sampling clock of fOCO-S
digital filter × 4 cycles
When the VW0C1 bit is set

Internal reset signal
to 0 (digital filter enabled)
1
× 32
fOCO-S
When the VW0C1 bit is set

to 1 (digital filter disabled) Internal reset signal
and the VW0C7 bit is set
to 1
VW0C1 and VW0C7: Bits in VW0C register
The above applies under the following conditions.

• VCA25 bit in VCA2 register = 1 (voltage detection 0 circuit enabled)
• VW0C0 bit in VW0C register = 1 (voltage monitor 0 reset enabled)
• VW0C6 bit in VW0C register = 1 (voltage monitor 0 reset mode)
When the internal reset signal is held “L”, the pins, CPU and SFR are reset.
The internal reset signal level changes from “L” to “H”, and a program is executed beginning with the address indicated by
the reset vector.
Refer to 4. Special Function Registers (SFRs) for the SFR status after reset.
Figure 6.9 Example of Voltage Monitor 0 Reset Operation
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6.3 Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset

Table 6.3 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt and Reset. Figure 6.10
shows an Example of Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset Operation. To use the voltage
monitor 1 interrupt or voltage monitor 1 reset to exit stop mode, set the VW1C1 bit in the VW1C register to 1
(digital filter disabled).
Table 6.3 Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt and Reset
When Using Digital Filter When Not Using Digital Filter
Step Voltage Monitor 1 Voltage Monitor 1 Voltage Monitor 1 Voltage Monitor 1
Interrupt Reset Interrupt Reset
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2 Wait for td(E-A)
Select the sampling clock of the digital filter Select the timing of the interrupt and reset
3 by the VW1F0 to VW1F1 bits in the VW1C request by the VW1C7 bit in the VW1C
register register(1)
Set the VW1C1 bit in the VW1C register to 0 Set the VW1C1 bit in the VW1C register to 1
4(2)
(digital filter enabled) (digital filter disabled)
5(2) Set the VW1C6 bit in Set the VW1C6 bit in Set the VW1C6 bit in Set the VW1C6 bit in
the VW1C register to the VW1C register to the VW1C register to the VW1C register to
0 (voltage monitor 1 1 (voltage monitor 1 0 (voltage monitor 1 1 (voltage monitor 1
interrupt mode) reset mode) interrupt mode) reset mode)
6 Set the VW1C2 bit in the VW1C register to 0 (passing of Vdet1 is not detected)
8 Wait for 4 cycles of the sampling clock of the − (No wait time required)
digital filter
9 Set the VW1C0 bit in the VW1C register to 1 (voltage monitor 1 interrupt/reset enabled)
NOTES:
1. Set the VW1C7 bit to 1 (when VCC reaches Vdet1 or below) for the voltage monitor 1 reset.
instruction).
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VCC
Vdet1
2.2 V(1)
1
VW1C3 bit
0
4 cycles of sampling clock of digital filter 4 cycles of sampling clock of digital filter
VW1C2 bit
0
Set to 0 by a program
When the VW1C1 bit is set Set to 0 by interrupt request
to 0 (digital filter enabled) acknowledgement
Voltage monitor 1
interrupt request
(VW1C6 = 0)

(VW1C6 = 1)
1
When the VW1C1 bit is VW1C2 bit
set to 1 (digital filter 0
disabled) and the Set to 0 by interrupt
VW1C7 bit is set to 0 Voltage monitor 1 request
(Vdet1 or above) interrupt request acknowledgement
(VW1C6 = 0)
1
VW1C2 bit
0
When the VW1C1 bit is Set to 0 by interrupt
set to 1 (digital filter Voltage monitor 1 request acknowledgement
disabled) and the interrupt request
VW1C7 bit is set to 1 (VW1C6 = 0)
(Vdet1 or below)

(VW1C6 = 1)
VW1C1, VW1C2, VW1C3, VW1C6, VW1C7: Bit in VW1C Register

• VW1C0 bit in VW1C register = 1 (voltage monitor 1 interrupt and voltage monitor 1 reset enabled)
NOTE:
1. If voltage monitor 0 reset is not used, set the power supply to VCC ≥ 2.2.
Figure 6.10 Example of Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset Operation
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6.4 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset

Table 6.4 lists the Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset. Figure 6.11
shows an Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Operation. To use the voltage
monitor 2 interrupt or voltage monitor 2 reset to exit stop mode, set the VW2C1 bit in the VW2C register to 1
(digital filter disabled).
Table 6.4 Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset
When Using Digital Filter When Not Using Digital Filter
Step Voltage Monitor 2 Voltage Monitor 2 Voltage Monitor 2 Voltage Monitor 2
Interrupt Reset Interrupt Reset
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2 Wait for td(E-A)
Select the sampling clock of the digital filter Select the timing of the interrupt and reset
3 by the VW2F0 to VW2F1 bits in the VW2C request by the VW2C7 bit in the VW2C
register register(1)
Set the VW2C1 bit in the VW2C register to 0 Set the VW2C1 bit in the VW2C register to 1
4
(digital filter enabled) (digital filter disabled)
5(2) Set the VW2C6 bit in Set the VW2C6 bit in Set the VW2C6 bit in Set the VW2C6 bit in
the VW2C register to the VW2C register to the VW2C register to the VW2C register to
0 (voltage monitor 2 1 (voltage monitor 2 0 (voltage monitor 2 1 (voltage monitor 2
interrupt mode) reset mode) interrupt mode) reset mode)
6 Set the VW2C2 bit in the VW2C register to 0 (passing of Vdet2 is not detected)
8 Wait for 4 cycles of the sampling clock of the − (No wait time required)
digital filter
9 Set the VW2C0 bit in the VW2C register to 1 (voltage monitor 2 interrupt/reset enabled)
NOTES:
1. Set the VW2C7 bit to 1 (when VCC reaches Vdet2 or below) for the voltage monitor 2 reset.
instruction).
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VCC
Vdet2
2.2 V(1)
1
VCA13 bit
0
4 cycles of sampling clock of digital filter 4 cycles of sampling clock of digital filter
VW2C2 bit
0
When the VW2C1 bit is set Set to 0 by interrupt request
to 0 (digital filter enabled) acknowledgement
Voltage monitor 2
interrupt request
(VW2C6 = 0)

(VW2C6 = 1)
1
When the VW2C1 bit is VW2C2 bit
set to 1 (digital filter 0
disabled) and the Set to 0 by interrupt
VW2C7 bit is set to 0 Voltage monitor 2 request
(Vdet2 or above) interrupt request acknowledgement
(VW2C6 = 0)
1
VW2C2 bit
0
When the VW2C1 bit is Set to 0 by interrupt
set to 1 (digital filter Voltage monitor 2 request acknowledgement
disabled) and the interrupt request
VW2C7 bit is set to 1 (VW2C6 = 0)
(Vdet2 or below)

(VW2C6 = 1)

VW2C1, VW2C2, VW2C6, VW2C7: Bits in VW2C register

• VW2C0 bit in VW2C register = 1 (voltage monitor 2 interrupt and voltage monitor 2 reset enabled)
NOTE:
1. When voltage monitor 0 reset is not used, set the power supply to VCC ≥ 2.2.
Figure 6.11 Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Operation
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R8C/24 Group, R8C/25 Group 7. Programmable I/O Ports
7. Programmable I/O Ports

There are 41 programmable Input/Output ports (I/O ports) P0 to P2, P3_0, P3_1, P3_3 to P3_5, P3_7, P4_3 to P4_5,
and P6. Also, P4_6 and P4_7 can be used as input-only ports if the XIN clock oscillation circuit is not used, and the
P4_2 can be used as an input-only port if the A/D converter is not used.
Table 7.1 lists an Overview of Programmable I/O Ports.
Table 7.1 Overview of Programmable I/O Ports

Ports I/O Type of Output I/O Setting Internal Pull-Up Resister
P0 to P2, P6 I/O CMOS3 State Set per bit Set every 4 bits(1)
P3_0, P3_1, P3_3 to
I/O CMOS3 State Set per bit Set every 3 bits(1)
P3_4, P3_5, P3_7
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P4_3 I/O CMOS3 State Set per bit Set every bit(1)
P4_4, P4_5 I/O CMOS3 State Set per bit Set every 2 bits(1)
P4_2(2)
I (No output function) None None
P4_6, P4_7(3)
NOTES:
1. In input mode, whether an internal pull-up resistor is connected or not can be selected by registers
PUR0 and PUR1.
2. When the A/D converter is not used, this port can be used as the input-only port.
3. When the XIN clock oscillation circuit is not used, these ports can be used as the input-only ports.
7.1 Functions of Programmable I/O Ports

The PDi_j (j = 0 to 7) bit in the PDi (i = 0 to 4, 6) register controls I/O of the ports P0 to P2, P3_0, P3_1, P3_3 to
P3_5, P3_7, P4_3 to P4_5, and P6. The Pi register consists of a port latch to hold output data and a circuit to read
pin states.
Figures 7.1 to 7.7 show the Configurations of Programmable I/O Ports. Table 7.2 lists the Functions of
Programmable I/O Ports. Also, Figure 7.9 shows the PDi (i = 0 to 4 and 6) Registers. Figure 7.10 shows the Pi (i =
0 to 4 and 6) Registers, Figure 7.11 shows Registers PUR0 and PUR1, Figure 7.12 shows the PMR Register, Figure
7.13 shows the P2DRR Register.
Table 7.2 Functions of Programmable I/O Ports

Operation When Value of PDi_j Bit in PDi Register(1)
Accessing
When PDi_j Bit is Set to 0 (Input Mode) When PDi_j Bit is Set to 1 (Output Mode)
Pi Register
Reading Read pin input level Read the port latch
Write to the port latch. The value written to
Writing Write to the port latch
the port latch is output from the pin.
i = 0 to 4, 6 j = 0 to 7
NOTE:
1. Nothing is assigned to bits PD3_2, PD3_6, PD4_0 to PD4_2, PD4_6, and PD4_7.
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7.2 Effect on Peripheral Functions

Programmable I/O ports function as I/O ports for peripheral functions (Refer to Table 1.6 Pin Name Information
by Pin Number).
Table 7.3 lists the Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 0 to 4, 6 j = 0 to
7). Refer to the description of each function for information on how to set peripheral functions.
Table 7.3 Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 0 to 4, 6 j = 0 to 7)
I/O of Peripheral Functions PDi_j Bit Settings for Shared Pin Functions
Input Set this bit to 0 (input mode).
Output This bit can be set to either 0 or 1 (output regardless of the port setting)
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7.3 Pins Other than Programmable I/O Ports
Figure 7.8 shows the Configuration of I/O Pins.
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P0 Pull-up selection
Direction
register
(Note 1)
Data bus Port latch
(Note 1)
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Analog input
P1_0 to P1_3 Pull-up selection
Direction
register
1
(Note 1)
Output from individual peripheral function
Data bus Port latch
(Note 1)
Input to individual peripheral function
Analog input
P1_4 Pull-up selection
Direction
register
1
(Note 1)
Data bus Port latch
(Note 1)
NOTE:
1. symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
Figure 7.1 Configuration of Programmable I/O Ports (1)
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P1_5 and P1_7 Pull-up selection
Direction
register
“1”
(Note 1)
Data bus Port latch
(Note 1)
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Digital
INT1 input
filter
Direction
register
“1”
(Note 1)
Data bus Port latch
(Note 1)
P2 Drive capacity select
Pull-up selection
Direction
register
“1”
(Note 1)
Data bus Port latch
(Note 1)
Drive capacity select
NOTE:
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P3_0 and P3_1 Pull-up selection
Direction
register
1
(Note 1)
Data bus Port latch
(Note 1)
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P3_3, P3_4, P3_5, and P3_7 Pull-up selection
Direction
register
1
(Note 1)
Data bus Port latch
(Note 1)
NOTE:
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P4_2/VREF (Note 1)
Data bus
(Note 1)
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P4_3/XCIN Pull-up selection
Direction
register
(Note 1)
Data bus Port latch
(Note 1)
Clocked inverter(2)
(Note 3)
P4_4/XCOUT Pull-up selection
Direction
register
(Note 1)
Data bus Port latch
(Note 1)
NOTES:
2. When CM10 = 1 or CM04 = 0, the clocked inverter is cut off.
3. When CM04 = 0 the feedback resistor is disconnected.
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Direction
register
(Note 1)
Data bus Port latch
(Note 1)
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Digital
INT0 and Input to individual peripheral function
filter
P4_6/XIN (Note 1)
Data bus
(Note 1)
Clocked inverter(2)
(Note 3)
P4_7/XOUT (Note 1)
(Note 4)
Data bus
(Note 1)
NOTES:
2. When CM05 = 1, CM10 = 1, or CM13 = 0, the clocked inverter is cut off.
3. When CM10 = 1 or CM13 = 0, the feedback resistor is disconnected.
4. When CM05 = CM13 = 1 or CM10 = CM13 = 1, this pin is pulled up.
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Direction
register
1
(Note 1)
Data bus Port latch
(Note 1)
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P6_1, P6_2, P6_3, and P6_4

Pull-up selection
Direction
register
(Note 1)
Data bus Port latch
(Note 1)
Direction
register
1
(Note 1)
Data bus Port latch
(Note 1)
NOTE:
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Direction
register
1
(Note 1)
Data bus Port latch
(Note 1)
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Digital
INT2 input
filter
Direction
register
(Note 1)
Data bus Port latch
(Note 1)
Digital
INT3 input
filter
NOTE:
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MODE
MODE signal input
(Note 1)
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RESET (Note 1)
RESET signal input
(Note 1)
NOTE:
Figure 7.8 Configuration of I/O Pins
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Port Pi Direction Register (i = 0 to 4, 6)(1, 2)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After Reset

PD0(3) 00E2h 00h
PD1 00E3h 00h
PD2 00E6h 00h
PD3 00E7h 00h
PD4 00EAh 00h
PD6 00EEh 00h
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PDi_0 Port Pi_0 direction bit 0 : Input mode RW
PDi_1 Port Pi_1 direction bit (functions as an input port) RW
PDi_2 Port Pi_2 direction bit 1 : Output mode RW
PDi_3 Port Pi_3 direction bit (functions as an output port) RW
PDi_4 Port Pi_4 direction bit RW
NOTES:
1. Bits PD3_2 and PD3_6 in the PD3 register are unavailable on this MCU.
If it is necessary to set bits PD3_2 and PD3_6, set to 0 (input mode). When read, the content is 0.
2. Bits PD4_0 to PD4_2, PD4_6, and PD4_7 in the PD4 register are unavailable on this MCU.
If it is necessary to set bits PD4_0 to PD4_2, PD4_6 and PD4_7 in the PD4 register, set to 0 (input mode). When read,
the content is 0.
3. Write to the PD0 register w ith the next instruction after that used to set the PRC2 bit in the PRCR register to 1 (w rite
enabled).
Figure 7.9 PDi (i = 0 to 4 and 6) Registers
Port Pi Register (i = 0 to 4, 6)(1, 2)

b7 b6 b5 b4 b3 b2 b1 b0

P0 00E0h Undefined
P1 00E1h Undefined
P2 00E4h Undefined
P3 00E5h Undefined
P4 00E8h Undefined
P6 00ECh Undefined
Pi_0 Port Pi_0 bit The pin level of any I/O port w hich is set RW
Pi_1 Port Pi_1 bit to input mode can be read by reading the RW
Pi_2 Port Pi_2 bit corresponding bit in this register. The pin RW
Pi_3 Port Pi_3 bit level of any I/O port w hich is set to output RW
Pi_4 Port Pi_4 bit mode can be controlled by w riting to the RW
corresponding bit in this register.
Pi_5 Port Pi_5 bit RW
0 : “L” level
Pi_6 Port Pi_6 bit RW
1 : “H” level
Port Pi_7 bit
Pi_7 RW
NOTES:
1. Bits P3_2 and P3_6 in the P3 register are unavailable on this MCU.
If it is necessary to set bits P3_2 and P3_6, set to 0 (“L” level). When read, the content is 0.
2. Bits P4_0 and P4_1 in the P4 register are unavailable on this MCU.
If it is necessary to set bits P4_0 and P4_1, set to 0 (“L” level). When read, the content is 0.
Figure 7.10 Pi (i = 0 to 4 and 6) Registers
Rev.3.00 Feb 29, 2008 Page 56 of 485

REJ09B0244-0300
Pull-Up Control Register 0

b7 b6 b5 b4 b3 b2 b1 b0

PUR0 00FCh 00h
PU00 P0_0 to P0_3 pull-up(1) 0 : Not pulled up RW
PU01 P0_4 to P0_7 pull-up(1) 1 : Pulled up RW
www.DataSheet4U.com
P3_0, P3_1, and P3_3 pll-up(1) 0 : Not pulled up
PU06 RW
1 : Pulled up
(1)
P3_4 to P3_5, and P3_7 pll-up 0 : Not pulled up
PU07 RW
1 : Pulled up
NOTE:
1. When this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up.
Pull-Up Control Register 1

b7 b6 b5 b4 b3 b2 b1 b0
0 0 Symbol Address After Reset

PUR1 00FDh XX00XX00b
P4_3 pull-up(1) 0 : Not pulled up
PU10 RW
1 : Pulled up
P4_4 and P4_5 pull-up(1) 0 : Not pulled up
PU11 RW
1 : Pulled up
RW
(b3-b2)
— Nothing is assigned. If necessary, set to 0.
—
(b7-b6) When read, the content is 0.
NOTE:
1. When this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up.
Figure 7.11 Registers PUR0 and PUR1
Rev.3.00 Feb 29, 2008 Page 57 of 485

REJ09B0244-0300
Port Mode Register

b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 Symbol Address After Reset

PMR 00F8h 00h
—
(b3-b0)
Port CLK1/TXD1/RXD1 sw itch bit 0 : I/O ports P6_5, P6_6, P6_7
U1PINSEL RW
1 : CLK1, TXD1, RXD1
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—
(b6-b5)
SSU / I2C bus sw itch bit 0 : Selects SSU function
IICSEL RW
1 : Selects I2C bus function
Figure 7.12 PMR Register
Port P2 Drive Capacity Control Register

b7 b6 b5 b4 b3 b2 b1 b0

P2DRR 00F4h 00h
P2DRR0 P2_0 drive capacity Set P2 output transistor drive capacity RW
P2DRR1 P2_1 drive capacity 0 : Low RW
P2DRR2 P2_2 drive capacity 1 : High(1) RW
P2DRR3 P2_3 drive capacity RW
NOTE:
1. Both “H” and “L” output are set to high drive capacity.
Figure 7.13 P2DRR Register
Rev.3.00 Feb 29, 2008 Page 58 of 485

REJ09B0244-0300
7.4 Port settings

Tables 7.4 to 7.47 list the port settings.
Table 7.4 Port P0_0/AN7

Register PD0 ADCON0
Function
Bit PD0_0 CH2 CH1 CH0 ADGSEL0
0 X X X X Input port(1)
Setting
1 X X X X Output port
Value
0 1 1 1 0 A/D converter input (AN7)
X: 0 or 1
NOTE:
www.DataSheet4U.com1. Pulled up by setting the PU00 bit in the PUR0 register to 1.

Register PD0 ADCON0
Function
Setting
Value
X: 0 or 1
NOTE:
1. Pulled up by setting the PU00 bit in the PUR0 register to 1.

Register PD0 ADCON0
Function
Setting
Value
X: 0 or 1
NOTE:

Register PD0 ADCON0
Function
Setting
Value
X: 0 or 1
NOTE:

Register PD0 ADCON0
Function
Setting
Value
X: 0 or 1
NOTE:
Rev.3.00 Feb 29, 2008 Page 59 of 485

REJ09B0244-0300

Register PD0 ADCON0
Function
Setting
Value
X: 0 or 1
NOTE:

www.DataSheet4U.com
Register PD0 ADCON0
Function
Setting
Value
X: 0 or 1
NOTE:

Register PD0 ADCON0
Function
Setting
Value
X: 0 or 1
NOTE:
Table 7.12 Port P1_0/KI0/AN8

Register PD1 KIEN ADCON0
Function
Bit PD1_0 KI0EN CH2 CH1 CH0 ADGSEL0
0 X X X X X Input port(1)
Setting 1 X X X X X Output port
Value 0 1 X X X X KI0 input
0 X 1 0 0 1 A/D converter input (AN8)
X: 0 or 1
NOTE:

Function
X: 0 or 1
NOTE:
Rev.3.00 Feb 29, 2008 Page 60 of 485

REJ09B0244-0300

Function
X: 0 or 1
NOTE:
www.DataSheet4U.com
Function
X: 0 or 1
NOTE:
Table 7.16 Port P1_4/TXD0

Register PD1 U0MR
Function
Bit PD1_4 SMD2 SMD1 SMD0
0 0 0 0 Input port(1)
1 0 0 0 Output port
Setting 0 0 1
Value 1 0 0
X TXD0 output(2)
1 0 1
1 1 0
X: 0 or 1
NOTES:
2. N-channel open drain output by setting the NCH bit in the U0C0 register to 1.
Table 7.17 Port P1_5/RXD0/(TRAIO)/(INT1)

Register PD1 TRAIOC TRAMR INTEN
Function
Bit PD1_5 TIOSEL TOPCR TMOD2 TMOD1 TMOD0 INT1EN
0 X X X X
0 X 1 X X X X Input port(1)
X X Other than 001b
0 X X X X
1 X 1 X X X X Output port
Setting
X X Other than 001b
Value
X Other than 001b
0 X X RXD0 input
0 0 0 1
0 1 X Other than 001b X TRAIO input
0 1 X Other than 001b 1 TRAIO/INT1 input
X 1 0 0 0 1 X TRAIO pulse output
X: 0 or 1
NOTE:
Rev.3.00 Feb 29, 2008 Page 61 of 485

REJ09B0244-0300
Table 7.18 Port P1_6/CLK0

Register PD1 U0MR
Function
Bit PD1_6 SMD2 SMD1 SMD0 CKDIR
Other than 001b X
0 Input port(1)
X X X 1
Setting
1 Other than 001b X Output port
Value
0 X X X 1 CLK0 (external clock) input
X 0 0 1 0 CLK0 (internal clock) output
X: 0 or 1
NOTE:
w w w . D a t a S h e e t 4 U . c o m
Table 7.19 Port P1_7/TRAIO/INT1
Register PD1 TRAIOC TRAMR INTEN
Function
Bit PD1_7 TIOSEL TOPCR TMOD2 TMOD1 TMOD0 INT1EN
1 X X X X
0 X 1 X X X X Input port(1)
X X Other than 001b
1 X X X X
Setting 1 X 1 X X X X Output port
Value
X X Other than 001b
0 0 X Other than 001b X TRAIO input
0 0 X Other than 001b 1 TRAIO/INT1 input
X 0 0 0 0 1 X TRAIO pulse output
X: 0 or 1
NOTE:
Table 7.20 Port P2_0/TRDIOA0/TRDCLK

Register PD2 TRDOER1 TRDFCR TRDIORA0
Function
Bit PD2_0 EA0 CMD1 CMD0 STCLK PWM3 IOA2 IOA1 IOA0
0 1 X X X X X X X Input port(1)
1 1 X X X X X X X Output port(2)
0 X 0 0 0 1 1 X X Timer mode (input capture function)
Setting
0 X X X 1 1 0 0 0 External clock input (TRDCLK)
Value
X 0 0 0 0 0 X X X PWM3 mode waveform output(2)
0 0 1 Timer mode waveform output
X 0 0 0 0 1
0 1 X (output compare function)(2)
X: 0 or 1
NOTES:
2. Output drive capacity high by setting the P2DRR0 bit in the P2DRR register to 1.
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Table 7.21 Port P2_1/TRDIOB0

Register PD2 TRDOER1 TRDFCR TRDPMR TRDIORA0
Function
Bit PD2_1 EB0 CMD1 CMD0 PWM3 PWMB0 IOB2 IOB1 IOB0
1 0
X 0 X X X X X Complementary PWM mode waveform output
Setting 1 1
Value X 0 0 1 X X X X X Reset synchronous PWM mode waveform output
X 0 0 0 0 X X X X PWM3 mode waveform output(2)
X 0 0 0 1 1 X X X PWM mode waveform output(2)
www.DataSheet4U.com 0 0 1 Timer mode waveform output (output compare
X 0 0 0 1 0
0 1 X function)(2)
X: 0 or 1
NOTES:
Table 7.22 Port P2_2/TRDIOC0

Register PD2 TRDOER1 TRDFCR TRDPMR TRDIORC0
Function
Bit PD2_2 EC0 CMD1 CMD0 PWM3 PWMC0 IOC2 IOC1 IOC0
1 0 Complementary PWM mode waveform
X 0 X X X X X
Setting 1 1 output(2)
Value Reset synchronous PWM mode waveform
X 0 0 1 X X X X X
output(2)
0 0 1 Timer mode waveform output (output
X 0 0 0 1 0
0 1 X compare function)(2)
X: 0 or 1
NOTES:
Table 7.23 Port P2_3/TRDIOD0

Function
Bit PD2_3 ED0 CMD1 CMD0 PWM3 PWMD0 IOD2 IOD1 IOD0
X 0 X X X X X
X 0 0 1 X X X X X
output(2)
X 0 0 0 1 0
X: 0 or 1
NOTES:
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REJ09B0244-0300
Table 7.24 Port P2_4/TRDIOA1

Register PD2 TRDOER1 TRDFCR TRDIORA1
Function
Bit PD2_4 EA1 CMD1 CMD0 PWM3 IOA2 IOA1 IOA0
0 1 X X X X X X Input port(1)
1 1 X X X X X X Output port(2)
0 X 0 0 1 1 X X Timer mode (input capture function)
Setting 1 0
X 0 X X X X Complementary PWM mode waveform output(2)
Value 1 1
X 0 0 1 X X X X Reset synchronous PWM mode waveform output(2)
0 0 1 Timer mode waveform output
X 0 0 0 1
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X: 0 or 1
NOTES:
Table 7.25 Port P2_5/TRDIOB1

Register PD2 TRDOER1 TRDFCR TRDPMR TRDIORA1
Function
Bit PD2_5 EB1 CMD1 CMD0 PWM3 PWMB1 IOB2 IOB1 IOB0
X 0 X X X X X
X 0 0 1 X X X X X
output(2)
X 0 0 0 1 0
X: 0 or 1
NOTES:
Table 7.26 Port P2_6/TRDIOC1

Function
Bit PD2_6 EC1 CMD1 CMD0 PWM3 PWMC1 IOC2 IOC1 IOC0
X 0 X X X X X
X 0 0 1 X X X X X
output(2)
X 0 0 0 1 0
X: 0 or 1
NOTES:
Rev.3.00 Feb 29, 2008 Page 64 of 485

REJ09B0244-0300
Table 7.27 Port P2_7/TRDIOD1

Function
Bit PD2_7 ED1 CMD1 CMD0 PWM3 PWMD1 IOD2 IOD1 IOD0
X 0 X X X X X
X 0 0 1 X X X X X
output(2)
www.DataSheet4U.com 0 0 1 Timer mode waveform output
X 0 0 0 1 0
X: 0 or 1
NOTES:
Table 7.28 Port P3_0/TRAO

Register PD3 TRAIOC
Function
Bit PD3_0 TOENA
0 0 Input port(1)
Setting
1 0 Output port
Value
X 1 TRAO output
X: 0 or 1
NOTE:
Table 7.29 Port P3_1/TRBO

Register PD3 TRBMR TRBIOC
Function
Bit PD3_1 TMOD1 TMOD0 TOCNT
0 0 0 X Input port(1)
Setting 1 0 0 X
Output port
Value X 01b 1
X Other than 00b 0 TRBO output
X: 0 or 1
NOTE:
Table 7.30 Port P3_3/SSI

Clock Synchronous Serial I/O with Chip Select
Register PD3 (Refer to Table 16.4 Association between PMR
Function
Communication Modes and I/O Pins.)
Bit PD3_3 SSI output control SSI input control IICSEL
0 0 0
0 Input port(1)
X X 1
Setting 0 0 0
1 Output port(2)
Value X X 1
X 0 1 0 SSI input
X 1 0 0 SSI output(2)
X: 0 or 1
NOTES:
2. N-channel open drain output by setting the SOOS bit in the SSMR2 register to 1 when this pin functions as output.
Rev.3.00 Feb 29, 2008 Page 65 of 485

REJ09B0244-0300
Table 7.31 Port P3_4/SDA/SCS

Register PD3 SSMR2 PMR ICCR1
Function
Bit PD3_4 CSS1 CSS0 IICSEL ICE
0 0 0 0 X
Input port(1)
0 0 0 X 0
1 0 0 0 X
Output port(2)
Setting 1 0 0 X 0
Value X 0 1 0 X SCS input
1 0
X 0 X SCS output(2)
1 1
www.DataSheet4U.com X X X 1 1 SDA input/output
X: 0 or 1
NOTES:
2. N-channel open drain output by setting the CSOS bit in the SSMR2 register to 1 when this pin functions as output.
Table 7.32 Port P3_5/SCL/SSCK

Register PD3 (Refer to Table 16.4 Association between PMR ICCR1
Communication Modes and I/O Pins.) Function
Bit PD3_5 SSCK output control SSCK input control IICSEL ICE
0 0 0 0 X
Input port(1)
0 0 0 X 0
1 0 0 0 X
Setting Output port(2)
1 0 0 X 0
Value
X 0 1 0 0 SSCK input
X 1 0 0 0 SSCK output(2)
X 1 0 1 1 SCL input/output
X: 0 or 1
NOTES:
2. N-channel open drain output by setting the CSOS bit in the SSMR2 register to 1 when this pin functions as output.
Table 7.33 Port P3_7/SSO

Register PD3 (Refer to Table 16.4 Association between SSMR2 PMR
Communication Modes and I/O Pins.) Function
Bit PD3_7 SSO output control SSO input control SOOS IICSEL
0 0 0 X 0
Input port(1)
0 X X X 1
1 0 0 0 0
Output port
Setting 1 X X 0 1
Value X 0 1 0 0 SSO input
X 1 0 0 0 SSO output (CMOS output)
SSO output (N-channel open-drain
X 1 0 1 0
output)
X: 0 or 1
NOTE:
Table 7.34 Port P4_2/VREF

Register ADCON1
Function
Bit VCUT
Setting 0 Input port
Value 1 Input port/VREF input
Rev.3.00 Feb 29, 2008 Page 66 of 485

REJ09B0244-0300
Table 7.35 Port P4_3/XCIN

Register PD4 CM0 CM1 Circuit specifications
Oscillation Feedback Function
Bit PD4_3 CM04 CM10 CM12
buffer resistor
0 0 X X OFF OFF Input port(1)
1 0 X X OFF OFF Output port
XCIN-XCOUT oscillation (on-chip feedback resistor
X 1 0 0 ON ON
enabled)
Setting XCIN-XCOUT oscillation (on-chip feedback resistor
X 1 0 1 ON OFF
Value disabled)
0 OFF ON
X 1 1 XCIN-XCOUT oscillation stop
www.DataSheet4U.com 1 OFF OFF
0 ON ON
X 1 0 External XCIN input
1 ON OFF
X: 0 or 1
NOTE:
Table 7.36 Port P4_4/XCOUT

Register PD4 CM0 CM1 Circuit specifications
Bit PD4_4 CM04 CM10 CM12
buffer resistor
0 0 X X OFF OFF Input port(1)
1 0 X X OFF OFF Output port
XCIN-XCOUT oscillation (on-chip feedback resistor
X 1 0 0 ON ON
enabled)
Setting XCIN-XCOUT oscillation (on-chip feedback resistor
X 1 0 1 ON OFF
Value disabled)
0 OFF ON
X 1 1 XCIN-XCOUT oscillation stop
1 OFF OFF
0 ON ON
X 1 0 External XCOUT output (inverted output of XCIN)(2)
1 ON OFF
X: 0 or 1
NOTES:
2. Since the XCIN-XCOUT oscillation buffer operates with internal step-down power, the XCOUT output level cannot be used as
the CMOS level signal directly.
Table 7.37 Port P4_5/INT0

Register PD4 INTEN
Function
Bit PD4_5 INT0EN
0 X Input port(1)
Setting
1 X Output port
Value
0 1 INT0 input
X: 0 or 1
NOTE:
Rev.3.00 Feb 29, 2008 Page 67 of 485

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Table 7.38 Port P4_6/XIN

Register CM1 CM0 Circuit specifications
Bit CM13 CM10 CM05
buffer resistor
0 X X OFF OFF Input port
1 0 0 ON ON XIN-XOUT oscillation
Setting
1 0 1 OFF ON External XIN input
Value
1 1 0 OFF OFF XIN-XOUT oscillation stop
X: 0 or 1
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Table 7.39 Port P4_7/XOUT
Register CM1 CM0 Circuit specifications
Bit CM13 CM10 CM05
buffer resistor
0 X X OFF OFF Input port
1 0 0 ON ON XIN-XOUT oscillation
Setting
1 0 1 OFF ON XOUT is “H” pull-up
Value
X: 0 or 1
Table 7.40 Port P6_0/TREO

Register PD6 TRECR1
Function
Bit PD6_0 TOENA
0 0 Input port(1)
Setting
1 0 Output port
Value
X 1 TREO output
X: 0 or 1
NOTE:
Table 7.41 Port P6_1

Register PD6
Function
Bit PD6_1
Setting 0 Input port(1)
Value 1 Output port
NOTE:

Register PD6
Function
Bit PD6_2
Value 1 Output port
NOTE:

Register PD6
Function
Bit PD6_3
Value 1 Output port
NOTE:
Rev.3.00 Feb 29, 2008 Page 68 of 485

REJ09B0244-0300

Register PD6
Function
Bit PD6_4
Value 1 Output port
NOTE:
Table 7.45 Port P6_5/CLK1

Register PD6 PMR U1MR
Function
www.DataSheet4U.com Bit PD6_5 U1PINSEL SMD2 SMD1 SMD0 CKDIR
X Other than 001b X
0 0 X X X X Input port(1)
X X X X 1
Setting
X Other than 001b
Value X
1 0 X X X Output port
X X X X 0
0 1 X X X 1 CLK1 (external clock) input
X 1 0 0 1 0 CLK1 (internal clock) output
X: 0 or 1
NOTE:
Table 7.46 Port P6_6/INT2/TXD1

Register PD6 PMR U1MR U1C0 INTEN
Function
Bit PD6_6 U1PINSEL SMD2 SMD1 SMD0 NCH INT2EN
X 0 0 0
0 X X Input port(1)
0 X X X
X 0 0 0
1 X X Output port
0 X X X
0 X X X X X 1 INT2 input
0 0 1
Setting
1 0 0
Value X 1 0 X TXD1 output (CMOS output)
1 0 1
1 1 0
0 0 1
1 0 0
X 1 1 X TXD1 output (N-channel open-drain output)
1 0 1
1 1 0
X: 0 or 1
NOTE:
Table 7.47 Port P6_7/INT3/RXD1

Register PD6 PMR INTEN
Function
Bit PD6_7 U1PINSEL INT3EN
0 X X Input port(1)
Setting 1 X X Output port
Value 0 X 1 INT3 input
0 1 X RXD1 input
X: 0 or 1
NOTE:
Rev.3.00 Feb 29, 2008 Page 69 of 485

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7.5 Unassigned Pin Handling

Table 7.48 lists the Unassigned Pin Handling.
Table 7.48 Unassigned Pin Handling

Pin Name Connection
Ports P0 to P2, P3_0, • After setting to input mode, connect each pin to VSS via a resistor (pull-
P3_1, P3_3 to P3_7, down) or connect each pin to VCC via a resistor (pull-up).(2)
P4_3 to P4_5, P6 • After setting to output mode, leave these pins open.(1,2)
Ports P4_6, P4_7 Connect to VCC via a pull-up resistor(2)
Port P4_2, VREF Connect to VCC
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RESET (3) Connect to VCC via a pull-up resistor(2)
NC Open or Connect to VCC and VSS
NOTES:
1. If these ports are set to output mode and left open, they remain in input mode until they are switched
to output mode by a program. The voltage level of these pins may be undefined and the power
current may increase while the ports remain in input mode.
The content of the direction registers may change due to noise or program runaway caused by
noise. In order to enhance program reliability, the program should periodically repeat the setting of
the direction registers.
2. Connect these unassigned pins to the MCU using the shortest wire length (2 cm or less) possible.
3. When the power-on reset function is in use.
MCU
Port P0 to P2, P3_0, (Input mode )

: :
P3_1, P3_3 to P3_7, :
:
P4_3 to P4_5, P6 (Input mode)
(Output mode) Open
Port P4_6, P4_7
RESET(1)
Port P4_2/VREF
NOTE:
1. When the power-on reset function is in use.
Figure 7.14 Unassigned Pin Handling
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REJ09B0244-0300
R8C/24 Group, R8C/25 Group 8. Processor Mode
8. Processor Mode
8.1 Processor Modes

Single-chip mode can be selected as the processor mode.
Table 8.1 lists Features of Processor Mode. Figure 8.1 shows the PM0 Register and Figure 8.2 shows the PM1
Register.
Table 8.1 Features of Processor Mode

Processor Mode Accessible Areas Pins Assignable as I/O Port Pins
Single-chip mode SFR, internal RAM, internal ROM All pins are I/O ports or peripheral
www.DataSheet4U.com function I/O pins
Processor Mode Register 0(1)

b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 Symbol Address After Reset

PM0 0004h 00h
RW
(b2-b0)
Softw are reset bit The MCU is reset w hen this bit is set to 1.
PM03 RW
When read, the content is 0.
—
NOTE:
1. Set the PRC1 bit in the PRCR register to 1 (w rite enable) before rew riting the PM0 register.
Figure 8.1 PM0 Register
Processor Mode Register 1(1)

b7 b6 b5 b4 b3 b2 b1 b0

PM1 0005h 00h
RW
(b1-b0)
WDT interrupt/reset sw itch bit 0 : Watchdog timer interrupt
PM12 RW
1 : Watchdog timer reset(2)
—
RW
(b7)
NOTES:
1. Set the PRC1 bit in the PRCR register to 1 (w rite enable) before rew riting the PM1 register.
2. The PM12 bit is set to 1 by a program (and remains unchanged even if 0 is w ritten to it).
When the CSPRO bit in the CSPR register is set to 1 (count source protect mode enabled), the PM12 bit is
automatically set to 1.
Figure 8.2 PM1 Register
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R8C/24 Group, R8C/25 Group 9. Bus
9. Bus
The bus cycles differ when accessing ROM/RAM, and when accessing SFR.
Table 9.1 lists Bus Cycles by Access Space of the R8C/24 Group and Table 9.2 lists Bus Cycles by Access Space of
the R8C/25 Group.
ROM/RAM and SFR are connected to the CPU by an 8-bit bus. When accessing in word (16-bit) units, these areas are
accessed twice in 8-bit units.
Table 9.3 lists Access Units and Bus Operations.
Table 9.1 Bus Cycles by Access Space of the R8C/24 Group

Access Area Bus Cycle
SFR 2 cycles of CPU clock
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ROM/RAM 1 cycle of CPU clock
Table 9.2 Bus Cycles by Access Space of the R8C/25 Group

Access Area Bus Cycle
SFR/Data flash 2 cycles of CPU clock
Program ROM/RAM 1 cycle of CPU clock
Table 9.3 Access Units and Bus Operations
Area SFR, data flash ROM (program ROM), RAM
Even address
CPU clock CPU clock
Byte access
Address Even Address Even
Data Data Data Data
Odd address CPU clock

Byte access CPU clock
Address Odd Odd

Address
Data Data Data
Data
Even address
CPU clock CPU clock
Word access
Address Even Even+1 Address Even Even+1

Data Data Data Data Data Data
Odd address CPU clock CPU clock

Word access
Address Odd Odd+1 Address Odd Odd+1
Data Data Data Data Data Data
However, only following SFRs are connected with the 16-bit bus:
Timer RD: registers TRDi (i = 0,1), TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi
Therefore, they are accessed once in 16-bit units. The bus operation is the same as “Area: SFR, data flash, even address
byte access” in Table 9.3 Access Units and Bus Operations, and 16-bit data is accessed at a time.
Rev.3.00 Feb 29, 2008 Page 72 of 485

REJ09B0244-0300
R8C/24 Group, R8C/25 Group 10. Clock Generation Circuit
10. Clock Generation Circuit

The clock generation circuit has:
• XIN clock oscillation circuit
• XCIN clock oscillation circuit
• Low-speed on-chip oscillator
• High-speed on-chip oscillator
Table 10.1 lists the Specifications of Clock Generation Circuit. Figure 10.1 shows a Clock Generation Circuit. Figures
10.2 to 10.8 show clock associated registers. Figure 10.9 shows the Procedure for Enabling Reduced Internal Power
Consumption Using VCA20 bit.
Table 10.1 Specifications of Clock Generation Circuit

w w w . D a t a S h e e t 4 U . c o m
On-Chip Oscillator
XIN Clock XCIN Clock Oscillation
Item High-Speed On-Chip Low-Speed On-Chip
Oscillation Circuit Circuit
Oscillator Oscillator
Applications • CPU clock source • CPU clock source • CPU clock source • CPU clock source
• Peripheral function • Timer RA and timer RE • Peripheral function • Peripheral function
clock source clock source clock source clock source
• CPU and peripheral • CPU and peripheral
function clock function clock
sources when XIN sources when XIN
clock stops oscillating clock stops oscillating
Clock frequency 0 to 20 MHz 32.768 kHz Approx. 40 MHz(4) Approx. 125 kHz
Connectable • Ceramic resonator • Crystal oscillator − −
oscillator • Crystal oscillator
Oscillator XIN, XOUT(1) XCIN, XCOUT(2) −(1) −(1)
connect pins
Oscillation stop, Usable Usable Usable Usable
restart function
Oscillator status Stop Stop Stop Oscillate
after reset
Others Externally • Externally generated − −
generated clock can clock can be input
be input(3) • On-chip feedback
resistor Rf (connected/
not connected,
selectable)
NOTES:
1. These pins can be used as P4_6 or P4_7 when using the on-chip oscillator clock as the CPU clock while the
XIN clock oscillation circuit is not used.
2. These pins can be used as P4_3 and P4_4 when using the XIN clock oscillation circuit and on-chip oscillator
clock for a CPU clock while the XCIN clock oscillation circuit is not used.
3. Set the CM05 bit in the CM0 register to 1 (XIN clock stopped) and the CM13 bit in the CM1 register to 1 (XIN-
XOUT pin) when an external clock is input.
4. The clock frequency is automatically set to up to 20 MHz by a divider when using the high-speed on-chip
oscillator as the CPU clock source.
Rev.3.00 Feb 29, 2008 Page 73 of 485

REJ09B0244-0300
Clock prescaler
fC4
fC fC32
1/4 1/8
FRA1 register
Frequency adjustable
FRA00 High-speed fOCO40M
on-chip
XCOUT oscillator FRA2 register fOCO128
XCIN Divider
(1/128)
Divider Watchdog SSU /
timer I2C bus
fOCO-F
FRA01 = 1 fOCO A/D

INT0 Timer RA Timer RB Timer RD Timer RE converter UART0 UART1
FRA01 = 0 On-chip oscillator
clock
www.DataSheet4U.com CM04
Low-speed
on-chip Power-on
CM14 oscillator reset circuit
fOCO-S
Voltage
detection
circuit
CM10 = 1 (stop mode) S Q
b f1
RESET R
c f2
Power-on reset
Oscillation
Software reset stop d f4
Interrupt request S Q detection
e f8
WAIT instruction XIN clock
R
OCD2 = 1 g f32
CM13 CM07 = 0
a h
Divider
CPU clock
XIN XOUT OCD2 = 0 fC
CM07 = 1
CM13
CM05
System clock
CM02
d e g
b c
a 1/2 1/2 1/2 1/2 1/2
CM06 = 0
CM17 to CM16 = 11b
CM06 = 1
CM06 = 0
h
CM17 to
CM16 = 10b
CM02, CM04, CM05, CM06, CM07: Bits in CM0 register CM06 = 0

CM10, CM13, CM14, CM16, CM17: Bits in CM1 register CM17 to CM16 = 01b
OCD0, OCD1, OCD2: Bits in OCD register
FRA00, FRA01: Bits in FRA0 register
CM06 = 0
CM17 to CM16 = 00b
Detail of divider
Oscillation Stop Detection Circuit
Forcible discharge when OCD0 = 0
Pulse generation
circuit for clock edge Charge,
XIN clock discharge Oscillation stop detection
detection and
charge, discharge circuit interrupt generation Oscillation stop detection,
control circuit circuit detection Watchdog timer,
OCD1 Watchdog timer Voltage monitor 1 interrupt,
interrupt Voltage monitor 2 interrupt
Voltage monitor 1
interrupt
Voltage monitor 2
interrupt
OCD2 bit switch signal
CM14 bit switch signal
Figure 10.1 Clock Generation Circuit
Rev.3.00 Feb 29, 2008 Page 74 of 485

REJ09B0244-0300
System Clock Control Register 0(1)

b7 b6 b5 b4 b3 b2 b1 b0

CM0 0006h 01101000b
RW
(b1-b0)
WAIT peripheral function clock 0 : Peripheral function clock does not stop
stop bit in w ait mode
www.DataSheet4U.com CM02 1 : Peripheral function clock stops in w ait RW
mode
XCIN-XCOUT drive capacity 0 : Low
CM03 RW
select bit(9) 1 : High
(6)
Port, XCIN-XCOUT sw itch bit 0 : I/O port P4_3, P4_4
CM04 RW
1 : XCIN-XCOUT pin(7)
XIN clock (XIN-XOUT) 0 : XIN clock oscillates
CM05 RW
stop bit(2, 4) 1 : XIN clock stops (3)
System clock division select bit 0 : CM16, CM17 enabled
CM06 RW
0(5) 1 : Divide-by-8 mode
(8)
CPU clock select bit 0 : System clock
CM07 RW
1 : XCIN clock
NOTES:
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the CM0 register.
2. The CM05 bit stops the XIN clock w hen the high-speed on-chip oscillator mode, low -speed on-chip oscillator mode is
selected. Do not use this bit to detect w hether the XIN clock is stopped. To stop the XIN clock, set the bits in the
follow ing order:
(a) Set bits OCD1 to OCD0 in the OCD register to 00b.
(b) Set the OCD2 bit to 1 (selects on-chip oscillator clock).
3. During external clock input, only the clock oscillation buffer is turned off and clock input is acknow ledged.
4. When the CM05 bit is set to 1 (XIN clock stopped) and the CM13 bit in the CM1 register is set to 0 (P4_6, P4_7), P4_6
and P4_7 can be used as input ports.
5. When entering stop mode, the CM06 bit is set to 1 (divide-by-8 mode).
6. The CM04 bit can be set to 1 by a program but cannot be set to 0.
7. To use the XCIN clock, set the CM04 bit to 1. Also, set ports P4_3 and P4_4 as input ports w ithout pull-up.
8. Set the CM07 bit to 1 from 0 (XCIN clock) after setting the CM04 bit to 1 (XCIN-XCOUT pin) and allow ing XCIN clock
oscillation to stabilize.
9. The MCU enters stop mode, the CM03 bit is set to 1 (high). Rew rite the CM03 bit w hile the XCIN clock oscillation
stabilizes.
Figure 10.2 CM0 Register
Rev.3.00 Feb 29, 2008 Page 75 of 485

REJ09B0244-0300
System Clock Control Register 1(1)

b7 b6 b5 b4 b3 b2 b1 b0

CM1 0007h 00100000b
All clock stop control bit(4, 7, 8) 0 : Clock operates
CM10 RW
1 : Stops all clocks (stop mode)
XIN-XOUT on-chip feedback resistor 0 : On-chip feedback resistor enabled
CM11 RW
select bit 1 : On-chip feedback resistor disabled
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XCIN-XCOUT on-chip feedback 0 : On-chip feedback resistor enabled
CM12 RW
resistor select bit 1 : On-chip feedback resistor disabled
(7, 9)
Port XIN-XOUT sw itch bit 0 : Input ports P4_6, P4_7
CM13 RW
1 : XIN-XOUT pin
Low -speed on-chip oscillation stop 0 : Low -speed on-chip oscillator on
CM14 RW
bit(5, 6, 8) 1 : Low -speed on-chip oscillator off
(2)
XIN-XOUT drive capacity select bit 0 : Low
CM15 RW
1 : High
(3)
System clock division select bits 1 b7 b6
CM16 0 0 : No division mode RW
0 1 : Divide-by-2 mode
1 0 : Divide-by-4 mode
CM17 1 1 : Divide-by-16 mode RW
NOTES:
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the CM1 register.
2. When entering stop mode, the CM15 bit is set to 1 (drive capacity high).
3. When the CM06 bit is set to 0 (bits CM16, CM17 enabled), bits CM16 to CM17 are enabled.
4. If the CM10 bit is set to 1 (stop mode), the on-chip feedback resistor is disabled.
5. When the OCD2 bit is set to 0 (XIN clock selected), the CM14 bit is set to 1 (low -speed on-chip oscillator stopped).
When the OCD2 bit is set to 1 (on-chip oscillator clock selected), the CM14 bit is set to 0 (low -speed on-chip
oscillator on). It remains unchanged even if 1 is w ritten to it.
6. When using the voltage monitor 1 interrupt or voltage monitor 2 interrupt (w hen using the digital filter), set the CM14
bit to 0 (low -speed on-chip oscillator on).
7. When the CM10 bit is set to 1 (stop mode) and the CM13 bit is set to 1 (XIN-XOUT pin), the XOUT (P4_7) pin goes “H”.
When the CM13 bit is set to 0 (input ports, P4_6, P4_7), P4_7 (XOUT) enters input mode.
8. In count source protect mode (Refer to 13.2 Count Source Protection Mode Enabled), the value remains
unchanged even if bits CM10 and CM14 are set.
9. Once the CM13 bit is set to 1 by a program, it cannot be set to 0.
Figure 10.3 CM1 Register
Rev.3.00 Feb 29, 2008 Page 76 of 485

REJ09B0244-0300
Oscillation Stop Detection Register(1)

b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 Symbol Address After Reset

OCD 000Ch 00000100b
Oscillation stop detection enable 0 : Oscillation stop detection function
bit(7) disabled(2)
OCD0 1 : Oscillation stop detection function RW
enabled
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Oscillation stop detection 0 : Disabled(2)
OCD1 RW
interrupt enable bit 1 : Enabled
(4) (7)
System clock select bit 0 : Selects XIN clock
OCD2 1 : Selects on-chip oscillator clock(3) RW
Clock monitor bit(5, 6) 0 : XIN clock oscillates

OCD3 RO
1 : XIN clock stops
RW
(b7-b4)
NOTES:
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting to the OCD register.
2. Set bits OCD1 to OCD0 to 00b before entering stop mode, high-speed on-chip oscillator mode, or low -speed on-chip
oscillator mode (XIN clock stops).
3. The CM14 bit is set to 0 (low -speed on-chip oscillator on) if the OCD2 bit is set to 1 (on-chip oscillator clock
selected).
4. The OCD2 bit is automatically set to 1 (on-chip oscillator clock selected) if a XIN clock oscillation stop is detected
w hile bits OCD1 to OCD0 are set to 11b. If the OCD3 bit is set to 1 (XIN clock stopped), the OCD2 bit remains
unchanged even w hen set to 0 (XIN clock selected).
5. The OCD3 bit is enabled w hen the OCD0 bit is set to 1 (oscillation stop detection function enabled).
6. The OCD3 bit remains 0 (XIN clock oscillates) if bits OCD1 to OCD0 are set to 00b.
7. Refer to Figure 10.16 Procedure for Sw itching Clock Source from Low -Speed On-Chip Oscillator to XIN
Clock for the sw itching procedure w hen the XIN clock re-oscillates after detecting an oscillation stop.
Figure 10.4 OCD Register
Rev.3.00 Feb 29, 2008 Page 77 of 485

REJ09B0244-0300
High-Speed On-Chip Oscillator Control Register 0(1)

b7 b6 b5 b4 b3 b2 b1 b0

FRA0 0023h 00h
High-speed on-chip oscillator 0 : High-speed on-chip oscillator off
FRA00 RW
enable bit 1 : High-speed on-chip oscillator on
(3)
High-speed on-chip oscillator 0 : Selects low -speed on-chip oscillator
FRA01 RW
select bit(2) 1 : Selects high-speed on-chip oscillator
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RW
(b7-b2)
NOTES:
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the FRA0 register.
2. Change the FRA01 bit under the follow ing conditions.
• FRA00 = 1 (high-speed on-chip oscillation)
• The CM14 bit in the CM1 register = 0 (low -speed on-chip oscillator on)
• Bits FRA22 to FRA20 in the FRA2 register:
All divide ratio mode settings are supported w hen VCC = 3.0 V to 5.5 V 000b to 111b
Divide ratio of 4 or more w hen VCC = 2.7 V to 5.5 V 010b to 111b (divide by 4 or more)
Divide ratio of 8 or more w hen VCC = 2.2 V to 5.5 V 110b to 111b (divide by 8 or more)
3. When setting the FRA01 bit to 0 (low -speed on-chip oscillator selected), do not set the FRA00 bit to 0 (high-speed
on-chip oscillator off) at the same time.
Set the FRA00 bit to 0 after setting the FRA01 bit to 0.

b7 b6 b5 b4 b3 b2 b1 b0

FRA1 0024h When Shipping
Function RW
The frequency of the high-speed on-chip oscillator is adjusted w ith bits 0 to 7.
High-speed on-chip oscillator frequency = 40 MHz (FRA1 register = value w hen shipping)
Setting the FRA1 register to a low er value results in a higher frequency.
Setting the FRA1 register to a higher value results in a low er frequency.(2) RW
NOTES:
2. When changing the values of the FRA1 register, adjust the FRA1 register so that the frequency of the high-speed
on-chip oscillator clock w ill be 40 MHz or less.
Figure 10.5 Registers FRA0 and FRA1
Rev.3.00 Feb 29, 2008 Page 78 of 485

REJ09B0244-0300

b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 Symbol Address After Reset

FRA2 0025h 00h
High-speed on-chip oscillator Selects the dividing ratio for the high-
frequency sw itching bits speed on-chip oscillator clock.
FRA20 b2 b1 b0
RW
0 0 0: Divide-by-2 mode
www.DataSheet4U.com 0 0 1: Divide-by-3 mode
FRA21 0 1 1: Divide-by-5 mode RW
FRA22 1 1 1: Divide-by-9 mode RW

RW
(b7-b3)
NOTE:
High-Speed On-Chip Oscillator Control Register 4

b7 b6 b5 b4 b3 b2 b1 b0

FRA4 0029h When Shipping
Function RW
Stores data for frequency correction w hen VCC = 2.7 to 5.5 V. (The value is the same as that
of the FRA1 register after a reset.) Optimal frequency correction to match the voltage RO
conditions can be achieved by transferring this value to the FRA1 register.

b7 b6 b5 b4 b3 b2 b1 b0

FRA6 002Bh When Shipping
Function RW
Stores data for frequency correction w hen VCC = 2.2 to 5.5 V. Optimal frequency correction
to match the voltage conditions can be achieved by transferring this value to the FRA1 RO
register.

b7 b6 b5 b4 b3 b2 b1 b0

FRA7 002Ch When Shipping
Function RW
36.864 MHz frequency correction data is stored.
The oscillation frequency of the high-speed on-chip oscillator can be adjusted to 36.864 MHz RO
by transferring this value to the FRA1 register.
Figure 10.6 Registers FRA2, FRA4, FRA6 and FRA7
Rev.3.00 Feb 29, 2008 Page 79 of 485

REJ09B0244-0300
Clock Prescaler Reset Flag

b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 0 Symbol Address After Reset

CPSRF 0028h 00h
RW
(b6-b0)
(1)
Clock prescaler reset flag Setting this bit to 1 initializes the clock
CPSR RW
prescaler. (When read, the content is 0)
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NOTE:
1. Only w rite 1 to this bit w hen selecting the XCIN clock as the CPU clock, .
Figure 10.7 CPSRF Register
Voltage Detection Register 2(1)

b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 Symbol Address After Reset(5)

set to 1 and hardw are reset : 00h
or LVD0ON bit in the OFS register is
VCA2 0032h set to 0, and hardw are reset : 00100000b
Internal pow er low 0 : Disables low consumption
VCA20 RW
consumption enable bit(6) 1 : Enables low consumption
RW
(b4-b1)
VCA25 RW
VCA26 RW
VCA27 RW
NOTES:
1. Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VCA2 register.
2. To use the voltage monitor 0 reset, set the VCA25 bit to 1.
operation.
3. To use the voltage monitor 1 interrupt/reset or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1.
operation.
4. To use the voltage monitor 2 interrupt/reset or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1.
operation.
5. Softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this
register.
6. Use the VCA20 bit only w hen entering to w ait mode. To set the VCA20 bit, follow the procedure show n in Figure
10.9 Procedure for Enabling Reduced Internal Pow er Consum ption Using VCA20 bit.
Figure 10.8 VCA2 Register
Rev.3.00 Feb 29, 2008 Page 80 of 485

REJ09B0244-0300
Exit wait mode by interrupt

(Note 1)
Handling procedure of internal power
In interrupt routine
low consumption enabled by VCA20 bit
Enter low-speed clock mode or low-speed VCA20 ← 0 (internal power low consumption
Step (1) Step (5)
on-chip oscillator mode disabled)(2)
Stop XIN clock and high-speed on-chip Start XIN clock or high-speed on-chip If it is necessary to start
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Step (2) Step (6) the high-speed clock or
oscillator clock oscillator clock
the high-speed on-chip
oscillator in the interrupt
routine, execute steps (5)
VCA20 ← 1 (internal power low consumption to (7) in the interrupt
Step (3) Step (7) (Wait until XIN clock oscillation stabilizes)
enabled)(2, 3) routine.
Enter high-speed clock mode or

Step (4) Enter wait mode(4) Step (8)
high-speed on-chip oscillator mode
VCA20 ← 0 (internal power low consumption Interrupt handling

Step (5)
disabled)(2)
Enter low-speed clock mode or

Start XIN clock or high-speed on-chip Step (1)
Step (6) low-speed on-chip oscillator mode
oscillator clock If the high-speed clock or
high-speed on-chip
Stop XIN clock and high-speed on-chip oscillator is started in the
Step (2) interrupt routine, execute
Step (7) (Wait until XIN clock oscillation stabilizes) oscillator clock
steps (1) to (3) at the last of
the interrupt routine.
VCA20 ← 1 (internal power low consumption

Enter high-speed clock mode or Step (3)
Step (8) enabled)(2, 3)
Interrupt handling completed
NOTES:
1. Execute this routine to handle all interrupts generated in wait mode.
However, this does not apply if it is not necessary to start the high-speed clock or high-speed on-chip oscillator during the interrupt
routine.
2. Do not set the VCA20 bit to 0 with the instruction immediately after setting the VCA20 bit to 1. Also, do not do the opposite.
3. When the VCA20 bit is set to 1, do not set the CM10 bit to 1 (stop mode).
4. When entering wait mode, follow 10.7.2 Wait Mode.
Figure 10.9 Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit
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REJ09B0244-0300
The clocks generated by the clock generation circuits are described below.
10.1 XIN Clock

This clock is supplied by the XIN clock oscillation circuit. This clock is used as the clock source for the CPU and
peripheral function clocks. The XIN clock oscillation circuit is configured by connecting a resonator between the
XIN and XOUT pins. The XIN clock oscillation circuit includes an on-chip feedback resistor, which is
disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed by the
chip. The XIN clock oscillation circuit may also be configured by feeding an externally generated clock to the XIN
pin.
Figure 10.10 shows Examples of XIN Clock Connection Circuit.
In reset and after reset, the XIN clock stops.
The XIN clock starts oscillating when the CM05 bit in the CM0 register is set to 0 (XIN clock oscillates) after
www.DataSheet4U.com
setting the CM13 bit in the CM1 register to 1 (XIN- XOUT pin).
To use the XIN clock for the CPU clock source, set the OCD2 bit in the OCD register to 0 (select XIN clock) after
the XIN clock is oscillating stably.
The power consumption can be reduced by setting the CM05 bit in the CM0 register to 1 (XIN clock stops) if the
OCD2 bit is set to 1 (select on-chip oscillator clock).
When an external clock is input to the XIN pin are input, the XIN clock does not stop if the CM05 bit is set to 1. If
necessary, use an external circuit to stop the clock.
In stop mode, all clocks including the XIN clock stop. Refer to 10.5 Power Control for details.
MCU MCU
(on-chip feedback resistor) (on-chip feedback resistor)
XIN XOUT XIN XOUT
Open
Rf(1) Rd(1)
Externally derived clock
CIN COUT VCC

VSS
Ceramic resonator external circuit External clock input circuit
NOTE:
1. Insert a damping resistor if required. The resistance will vary depending on the oscillator and the
oscillation drive capacity setting. Use the value recommended by the manufacturer of the oscillator.
Use high drive when oscillation starts and, if it is necessary to switch the oscillation drive capacity, do so
after oscillation stabilizes.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator
manufacturer's data sheet specifies that a feedback resistor be added to the chip externally, insert a
feedback resistor between XIN and XOUT following the instructions.
To use this MCU with supply voltage below VCC = 2.7 V, it is recommended to set the CM11 bit in the
CM1 register to 1 (on-chip feedback resistor disabled), the CM15 bit to 1 (high drive capacity), and
connect the feedback resistor to the chip externally.
Figure 10.10 Examples of XIN Clock Connection Circuit
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REJ09B0244-0300
10.2 On-Chip Oscillator Clocks

These clocks are supplied by the on-chip oscillators (high-speed on-chip oscillator and a low-speed on-chip
oscillator). The on-chip oscillator clock is selected by the FRA01 bit in the FRA0 register.
10.2.1 Low-Speed On-Chip Oscillator Clock

The clock generated by the low-speed on-chip oscillator is used as the clock source for the CPU clock,
peripheral function clock, fOCO, and fOCO-S.
After reset, the on-chip oscillator clock generated by the low-speed on-chip oscillator divided by 8 is selected as
the CPU clock.
If the XIN clock stops oscillating when bits OCD1 to OCD0 in the OCD register are set to 11b, the low-speed
on-chip oscillator automatically starts operating, supplying the necessary clock for the MCU.
www.DataSheet4U.com The frequency of the low-speed on-chip oscillator varies depending on the supply voltage and the operating
ambient temperature. Application products must be designed with sufficient margin to allow for frequency
changes.
10.2.2 High-Speed On-Chip Oscillator Clock

The clock generated by the high-speed on-chip oscillator is used as the clock source for the CPU clock,
peripheral function clock, fOCO, fOCO-F, and fOCO40M.
To use the high-speed on-chip oscillator clock as the clock source for the CPU clock, peripheral clock, fOCO,
and fOCO-F, set bits FRA20 to FRA22 in the FRA2 register as follows:
• All divide ratio mode settings are supported when VCC = 3.0 V to 5.5 V 000b to 111b
• Divide ratio of 4 or more when VCC = 2.7 V to 5.5 V 010b to 111b (divide by 4 or more)
• Divide ratio of 8 or more when VCC = 2.2 V to 5.5 V 110b to 111b (divide by 8 or more)
After reset, the on-chip oscillator clock generated by the high-speed on-chip oscillator stops. Oscillation is
started by setting the FRA00 bit in the FRA0 register to 1 (high-speed on-chip oscillator on). The frequency can
be adjusted by registers FRA1 and FRA2.
The frequency correction data (the value is the same as that of the FRA1 register after a reset) corresponding to
the supply voltage ranges VCC = 2.7 V to 5.5 V is stored in FRA4 register. Furthermore, the frequency
correction data corresponding to the supply voltage ranges VCC = 2.2 V to 5.5 V is stored in FRA6 register. To
use separate correction values to match these voltage ranges, transfer them from FRA4 or FRA6 register to the
FRA1 register.
The frequency correction data of 36.864 MHz is stored in the FRA7 register. To set the frequency of the high-
speed on-chip oscillator to 36.864 MHz, transfer the correction value in the FRA7 register to the FRA1 register
before use. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial
interface is used in UART mode (refer to Table 15.7 Bit Rate Setting Example in UART Mode (Internal
Clock Selected)).
Since there are differences in the amount of frequency adjustment among the bits in the FRA1 register, make
adjustments by changing the settings of individual bits. Adjust the FRA1 register so that the frequency of the
high-speed on-chip oscillator clock will be 40 MHz or less.
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REJ09B0244-0300
10.3 XCIN Clock

This clock is supplied by the XCIN clock oscillation circuit. This clock is used as the clock source for the CPU
clock, timer RA, and timer RE. The XCIN clock oscillation circuit is configured by connecting a resonator between
the XCIN and XCOUT pins. The XCIN clock oscillation circuit includes an on-chip a feedback resistor, which is
disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed in the
chip. The XCIN clock oscillation circuit may also be configured by feeding an externally generated clock to the
XCIN pin.
Figure 10.11 shows Examples of XCIN Clock Connection Circuits.
During and after reset, the XCIN clock stops.
The XCIN clock starts oscillating when the CM04 bit in the CM0 register is set to 1 (XCIN-XCOUT pin).
To use the XCIN clock for the CPU clock source, set the CM07 bit in the CM0 register to 1 (XCIN clock) after the
XCIN clock is oscillating stably. To input an external clock to the XCIN pin, set the CM04 bit in the CM0 register
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to 1 (XCIN-XCOUT pin) and leave the XCOUT pin open.
This MCU has an on-chip feedback resistor and on-chip resistor disable/enable switching is possible by the CM12
bit in the CM1 register.
In stop mode, all clocks including the XCIN clock stop. Refer to 10.5 Power Control for details.
MCU MCU
(on-chip feedback resistor) (on-chip feedback resistor)
XCIN XCOUT XCIN XCOUT
Open
Rf(1)
Rd(1)
Externally derived clock
CIN COUT VCC

VSS
External crystal oscillator circuit External clock input circuit
NOTE:
1. Insert a damping resistor and feedback resistor if required. The resistance will vary depending on the oscillator and
the oscillation drive capacity setting. Use the value recommended by the manufacturer of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added to the chip externally, insert a feedback resistor between
XCIN and XCOUT following the instructions.
Figure 10.11 Examples of XCIN Clock Connection Circuits
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REJ09B0244-0300
10.4 CPU Clock and Peripheral Function Clock

There are a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions. Refer
to Figure 10.1 Clock Generation Circuit.
10.4.1 System Clock

The system clock is the clock source for the CPU and peripheral function clocks. Either the XIN clock or the
on-chip oscillator clock can be selected.
10.4.2 CPU Clock

The CPU clock is an operating clock for the CPU and watchdog timer.
www.DataSheet4U.com When the CM07 bit in the CM0 register is set to 0 (system clock), the system clock can be divided by 1 (no
division), 2, 4, 8, or 16 to produce the CPU clock. Use the CM06 bit in the CM0 register and bits CM16 to
CM17 in the CM1 register to select the value of the division.
When the CM07 bit in the CM0 register is set to 1 (XCIN clock), the XCIN clock is used for the CPU clock.
Use the XCIN clock while the XCIN clock oscillation stabilizes.
After reset, the low-speed on-chip oscillator clock divided by 8 provides the CPU clock.
When entering stop mode from high-speed clock mode, the CM06 bit is set to 1 (divide-by-8 mode).
10.4.3 Peripheral Function Clock (f1, f2, f4, f8, and f32)
The peripheral function clock is the operating clock for the peripheral functions.
The clock fi (i = 1, 2, 4, 8, and 32) is generated by the system clock divided by i. The clock fi is used for timers
RA, RB, RD, and RE, the serial interface and the A/D converter.
When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to 1 (peripheral function
clock stops in wait mode), the clock fi stop.
10.4.4 fOCO
fOCO is an operating clock for the peripheral functions.
fOCO runs at the same frequency as the on-chip oscillator clock and can be used as the source for timer RA.
When the WAIT instruction is executed, the clocks fOCO does not stop.
10.4.5 fOCO40M
fOCO40M is used as the count source for timer RD. fOCO40M is generated by the high-speed on-chip
oscillator and supplied by setting the FRA00 bit to 1.
When the WAIT instruction is executed, the clock fOCO40M does not stop.
fOCO40M can be used with supply voltage VCC = 3.0 to 5.5 V.
10.4.6 fOCO-F
fOCO-F is used as the count source for the A/D converter. fOCO-F is generated by the high-speed on-chip
oscillator and supplied by setting the FRA00 bit to 1.
When the WAIT instruction is executed, the clock fOCO-F does not stop.
10.4.7 fOCO-S
fOCO-S is an operating clock for the watchdog timer and voltage detection circuit. fOCO-S is supplied by
setting the CM14 bit to 0 (low-speed on-chip oscillator on) and uses the clock generated by the low-speed on-
chip oscillator. When the WAIT instruction is executed or in count source protect mode of the watchdog timer,
fOCO-S does not stop.
10.4.8 fOCO128
fOCO128 is generated by fOCO divided by 128.
The clock fOCO128 is used for capture signal of timer RD (channel 0).
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10.4.9 fC4 and fC32

The clock fC4 and fC32 are used for timer RA and timer RE.
Use fC4 and fC32 while the XCIN clock oscillation stabilizes.
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10.5 Power Control

There are three power control modes. All modes other than wait mode and stop mode are referred to as standard
operating mode.
10.5.1 Standard Operating Mode

Standard operating mode is further separated into four modes.
In standard operating mode, the CPU clock and the peripheral function clock are supplied to operate the CPU
and the peripheral function clocks. Power consumption control is enabled by controlling the CPU clock
frequency. The higher the CPU clock frequency, the more processing power increases. The lower the CPU
clock frequency, the more power consumption decreases. When unnecessary oscillator circuits stop, power
consumption is further reduced.
www.DataSheet4U.com Before the clock sources for the CPU clock can be switched over, the new clock source needs to be oscillating
and stable. If the new clock source is the XIN clock or XCIN clock, allow sufficient wait time in a program
until oscillation is stabilized before exiting.
Table 10.2 Settings and Modes of Clock Associated Bits

OCD
CM1 Register CM0 Register FRA0 Register
Register
Modes
CM17,
OCD2 CM14 CM13 CM07 CM06 CM05 CM04 FRA01 FRA00
CM16
High-speed No division 0 00b − 1 0 0 0 − − −
clock mode Divide-by-2 0 01b − 1 0 0 0 − − −
Divide-by-4 0 10b − 1 0 0 0 − − −
Divide-by-8 0 − − 1 0 1 0 − − −
Divide-by-16 0 11b − 1 0 0 0 − − −
Low-speed No division − − − − 1 − − 1 − −
clock mode
High-speed No division 1 00b − − 0 0 − − 1 1
on-chip Divide-by-2 1 01b − − 0 0 − − 1 1
oscillator Divide-by-4 1 10b − − 0 0 − − 1 1
mode
Divide-by-8 1 − − − 0 1 − − 1 1
Divide-by-16 1 11b − − 0 0 − − 1 1
Low-speed No division 1 00b 0 − 0 0 − − 0 −
on-chip Divide-by-2 1 01b 0 − 0 0 − − 0 −
oscillator Divide-by-4 1 10b 0 − 0 0 − − 0 −
mode
Divide-by-8 1 − 0 − 0 1 − − 0 −
Divide-by-16 1 11b 0 − 0 0 − − 0 −
X: can be 0 or 1, no change in outcome
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10.5.1.1 High-Speed Clock Mode

The XIN clock divided by 1 (no division), 2, 4, 8, or 16 provides the CPU clock. Set the CM06 bit to 1 (divide-
by-8 mode) when transiting to high-speed on-chip oscillator mode, low-speed on-chip oscillator mode. If the
CM14 bit is set to 0 (low-speed on-chip oscillator on) or the FRA00 bit in the FRA0 register is set to 1 (high-
speed on-chip oscillator on), fOCO can be used as timer RA. When the FRA00 bit is set to 1, fOCO40M can be
used as timer RD. When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the
watchdog timer and voltage detection circuit.
10.5.1.2 Low-Speed Clock Mode

The XCIN clock divided by 1 (no division) provides the CPU clock.
In this mode, stopping the XIN clock and high-speed on-chip oscillator, and setting the FMR47 bit in the FMR4
www.DataSheet4U.com register to 1 (flash memory low consumption current read mode enabled) enables low consumption operation.
When the FRA00 bit is set to 1, fOCO40M can be used as timer RD. When the CM14 bit is set to 0 (low-speed
on-chip oscillator on), fOCO-S can be used for the watchdog timer and voltage detection circuit.
To enter wait mode from low-speed clock mode, setting the VCA20 bit in the VCA2 register to 1 (internal
power low consumption enabled) enables lower consumption current in wait mode.
When enabling reduced internal power consumption using the VCA20 bit, follow Figure 10.13 Procedure for
Enabling Reduced Internal Power Consumption Using VCA20 bit.
10.5.1.3 High-Speed On-Chip Oscillator Mode

The high-speed on-chip oscillator is used as the on-chip oscillator clock when the FRA00 bit in the FRA0
register is set to 1 (high-speed on-chip oscillator on) and the FRA01 bit in the FRA0 register is set to 1. The on-
chip oscillator divided by 1 (no division), 2, 4, 8, or 16 provides the CPU clock. Set the CM06 bit to 1 (divide-
by-8 mode) when transiting to high-speed clock mode. If the FRA00 bit is set to 1, fOCO40M can be used as
timer RD. When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the
10.5.1.4 Low-Speed On-Chip Oscillator Mode

If the CM14 bit in the CM1 register is set to 0 (low-speed on-chip oscillator on) or the FRA01bit in the FRA0
register is set to 0, the low-speed on-chip oscillator provides the on-chip oscillator clock.
The on-chip oscillator clock divided by 1 (no division), 2, 4, 8 or 16 provides the CPU clock. The on-chip
oscillator clock is also the clock source for the peripheral function clocks. Set the CM06 bit to 1 (divide-by-8
mode) when transiting to high-speed clock mode. When the FRA00 bit is set to 1, fOCO40M can be used as
timer RD. When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used as the
In this mode, stopping the XIN clock and high-speed on-chip oscillator, and setting the FMR47 bit in the FMR4
register to 1 (flash memory low consumption current read mode enabled) enables low consumption operation.
To enter wait mode from low-speed on-chip oscillator mode, setting the VCA20 bit in the VCA2 register to 1
(internal power low consumption enabled) enables lower consumption current in wait mode.
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10.5.2 Wait Mode

Since the CPU clock stops in wait mode, the CPU, which operates using the CPU clock, and the watchdog
timer, when count source protection mode is disabled, stop. The XIN clock, XCIN clock, and on-chip oscillator
clock do not stop and the peripheral functions using these clocks continue operating.
10.5.2.1 Peripheral Function Clock Stop Function

If the CM02 bit is set to 1 (peripheral function clock stops in wait mode), the f1, f2, f4, f8, and f32 clocks stop
in wait mode. This reduces power consumption.
10.5.2.2 Entering Wait Mode

www.DataSheet4U.com The MCU enters wait mode when the WAIT instruction is executed.
When the OCD2 bit in the OCD register is set to 1 (on-chip oscillator selected as system clock), set the OCD1
bit in the OCD register to 0 (oscillation stop detection interrupt disabled) before executing the WAIT
instruction.
If the MCU enters wait mode while the OCD1 bit is set to 1 (oscillation stop detection interrupt enabled),
current consumption is not reduced because the CPU clock does not stop.
10.5.2.3 Pin Status in Wait Mode

The I/O port is the status before wait mode was entered is maintained.
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10.5.2.4 Exiting Wait Mode

The MCU exits wait mode by a reset or a peripheral function interrupt.
The peripheral function interrupts are affected by the CM02 bit. When the CM02 bit is set to 0 (peripheral
function clock does not stop in wait mode), all peripheral function interrupts can be used to exit wait mode.
When the CM02 bit is set to 1 (peripheral function clock stops in wait mode), the peripheral functions using the
peripheral function clock stop operating and the peripheral functions operated by external signals or on-chip
oscillator clock can be used to exit wait mode.
Table 10.3 lists Interrupts to Exit Wait Mode and Usage Conditions.
Table 10.3 Interrupts to Exit Wait Mode and Usage Conditions

Interrupt CM02 = 0 CM02 = 1
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Serial interface interrupt Usable when operating with internal Usable when operating with external
or external clock clock
Clock synchronous serial I/O Usable in all modes (Do not use)
with chip select interrupt / I2C
bus interface interrupt
Key input interrupt Usable Usable
A/D conversion interrupt Usable in one-shot mode (Do not use)
Timer RA interrupt Usable in all modes Can be used if there is no filter in
event counter mode.
Usable by selecting fOCO or fC32
as count source.
Timer RB interrupt Usable in all modes (Do not use)
Timer RD interrupt Usable in all modes Usable by selecting fOCO40M as
count source
Timer RE interrupt Usable in all modes Usable when operating in real time
clock mode
INT interrupt Usable Usable (INT0 to INT3 can be used if
there is no filter.)
Voltage monitor 1 interrupt Usable Usable
Voltage monitor 2 interrupt Usable Usable
Oscillation stop detection Usable (Do not use)
interrupt
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Figure 10.12 shows the Time from Wait Mode to Interrupt Routine Execution.
When using a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT
instruction.
(1) Set the interrupt priority level in bits ILVL2 to ILVL0 in the interrupt control registers of the peripheral
function interrupts to be used for exiting wait mode. Set bits ILVL2 to ILVL0 of the peripheral function
interrupts that are not to be used for exiting wait mode to 000b (interrupt disabled).
(2) Set the I flag to 1.
(3) Operate the peripheral function to be used for exiting wait mode.
When exiting by a peripheral function interrupt, the time (number of cycles) between interrupt request
generation and interrupt routine execution is determined by the settings of the FMSTP bit in the FMR0 register
and the CM07 bit in the CM0 register, as described in Figure 10.12.
www.DataSheet4U.com The CPU clock, when exiting wait mode by a peripheral function interrupt, is the same clock as the CPU clock
when the WAIT instruction is executed.
FMR0 Register CM0 Register Time until Flash Memory Time until CPU Clock Time for Interrupt
Remarks
FMSTP Bit CM07 Bit is Activated (T1) is Supplied (T2) Sequence (T3)
0 Period of system clock Period of CPU clock Period of CPU clock
0 (system clock) × 12 cycles + 30 µs (max.) × 6 cycles × 20 cycles
(flash memory Following total
operates) 1 Period of XCIN clock time is the time
Same as above Same as above
(XCIN clock) × 12 cycles + 30 µs (max.) from wait mode
0 Period of system clock until an interrupt
1 × 12 cycles Same as above Same as above routine is
(system clock)
(flash memory executed.
stops) 1 Period of XCIN clock
Same as above Same as above
(XCIN clock) × 12 cycles
T1 T2 T3
Flash memory
Wait mode CPU clock restart sequence Interrupt sequence
activation sequence
Interrupt request generated
Figure 10.12 Time from Wait Mode to Interrupt Routine Execution
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10.5.2.5 Reducing Internal Power Consumption

Internal power consumption can be reduced by using low-speed clock mode or low-speed on-chip oscillator
mode. Figure 10.13 shows the Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit.
Exit wait mode by interrupt

(Note 1)
Handling procedure of internal power
In interrupt routine
www.DataSheet4U.com low consumption enabled by VCA20 bit
Enter low-speed clock mode or low-speed VCA20 ← 0 (internal power low consumption
Step (1) Step (5)
on-chip oscillator mode disabled)(2)
Stop XIN clock and high-speed on-chip Start XIN clock or high-speed on-chip If it is necessary to start
Step (2) Step (6) the high-speed clock or
oscillator clock oscillator clock
the high-speed on-chip
oscillator in the interrupt
routine, execute steps (5)
VCA20 ← 1 (internal power low consumption to (7) in the interrupt
Step (3) Step (7) (Wait until XIN clock oscillation stabilizes)
enabled)(2, 3) routine.
Enter high-speed clock mode or

Step (4) Enter wait mode(4) Step (8)
VCA20 ← 0 (internal power low consumption Interrupt handling

Step (5)
disabled)(2)
Enter low-speed clock mode or

Start XIN clock or high-speed on-chip Step (1)
Step (6) low-speed on-chip oscillator mode
oscillator clock If the high-speed clock or
high-speed on-chip
Stop XIN clock and high-speed on-chip oscillator is started in the
Step (2) interrupt routine, execute
Step (7) (Wait until XIN clock oscillation stabilizes) oscillator clock
steps (1) to (3) at the last of
the interrupt routine.
VCA20 ← 1 (internal power low consumption

Enter high-speed clock mode or Step (3)
Step (8) enabled)(2, 3)
Interrupt handling completed
NOTES:
1. Execute this routine to handle all interrupts generated in wait mode.
However, this does not apply if it is not necessary to start the high-speed clock or high-speed on-chip oscillator during the interrupt
routine.
2. Do not set the VCA20 bit to 0 with the instruction immediately after setting the VCA20 bit to 1. Also, do not do the opposite.
3. When the VCA20 bit is set to 1, do not set the CM10 bit to 1 (stop mode).
4. When entering wait mode, follow 10.7.2 Wait Mode.
Figure 10.13 Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit
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10.5.3 Stop Mode

Since the oscillator circuits stop in stop mode, the CPU clock and peripheral function clock stop and the CPU
and peripheral functions that use these clocks stop operating. The least power required to operate the MCU is in
stop mode. If the voltage applied to the VCC pin is VRAM or more, the contents of internal RAM is
maintained.
The peripheral functions clocked by external signals continue operating.
Table 10.4 lists Interrupts to Exit Stop Mode and Usage Conditions.
Table 10.4 Interrupts to Exit Stop Mode and Usage Conditions

Interrupt Usage Conditions
Key input interrupt −
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INT0 to INT3 interrupt Can be used if there is no filter
Timer RA interrupt Can be used if there is no filter when external pulse is counted in event
counter mode
Serial interface interrupt When external clock is selected
Voltage monitor 1 interrupt Usable in digital filter disabled mode (VW1C1 bit in VW1C register is set
to 1)
Voltage monitor 2 interrupt Usable in digital filter disabled mode (VW2C1 bit in VW2C register is set
to 1)
10.5.3.1 Entering Stop Mode

The MCU enters stop mode when the CM10 bit in the CM1 register is set to 1 (all clocks stop). At the same
time, the CM06 bit in the CM0 register is set to 1 (divide-by-8 mode) and the CM15 bit in the CM1 register is
set to 1 (XIN clock oscillator circuit drive capacity high).
When using stop mode, set bits OCD1 to OCD0 to 00b before entering stop mode.
10.5.3.2 Pin Status in Stop Mode

The status before wait mode was entered is maintained.
However, when the CM13 bit in the CM1 register is set to 1 (XIN-XOUT pins), the XOUT(P4_7) pin is held
“H”. When the CM13 bit is set to 0 (input ports P4_6 and P4_7), the P4_7(XOUT pin) is held in input status.
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10.5.3.3 Exiting Stop Mode

The MCU exits stop mode by a reset or peripheral function interrupt.
Figure 10.14 shows the Time from Stop Mode to Interrupt Routine Execution.
When using a peripheral function interrupt to exit stop mode, set up the following before setting the CM10 bit
to 1.
(1) Set the interrupt priority level in bits ILVL2 to ILVL0 of the peripheral function interrupts to be used
for exiting stop mode. Set bits ILVL2 to ILVL0 of the peripheral function interrupts that are not to be
used for exiting stop mode to 000b (interrupt disabled).
(2) Set the I flag to 1.
(3) Operates the peripheral function to be used for exiting stop mode.
When exiting by a peripheral function interrupt, the interrupt sequence is executed when an interrupt
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request is generated and the CPU clock supply is started.
If the clock used immediately before stop mode is a system clock and stop mode is exited by a peripheral
function interrupt, the CPU clock becomes the previous system clock divided by 8.
FMR0 Register CM0 Register Time until Flash Memory Time until CPU Clock Time for Interrupt
is Activated (T2) is Supplied (T3) Sequence (T4) Remarks
FMSTP Bit CM07 Bit
Period of system clock Period of CPU clock Period of CPU clock Following total
0 0 (system clock) × 6 cycles
× 12 cycles + 30 µs (max.) × 20 cycles time of T0 to
(flash memory
operates) Period of XCIN clock T4 is the time
1 (XCIN clock) × 12 cycles + 30 µs (max.) Same as above Same as above
from stop
Period of system clock mode until an
0 (system clock) Same as above Same as above
1 × 12 cycles interrupt
(flash memory stops) Period of XCIN clock handling is
1 (XCIN clock) Same as above Same as above executed.
× 12 cycles
T0 T1 T2 T3 T4
Oscillation time of
Stop Internal power CPU clock source Flash memory CPU clock restart
Interrupt sequence
mode stability time used immediately activation sequence sequence
before stop mode
150 µs
Interrupt (max.)
request
generated
Figure 10.14 Time from Stop Mode to Interrupt Routine Execution
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Figure 10.15 shows the State Transitions in Power Control Mode.
State Transitions in Power Control Mode
Reset
Standard operating mode
Low-speed on-chip oscillator mode

CM07 = 0
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CM14 = 0
OCD2 = 1
CM14 = 0
FRA01 = 0 CM04 = 1
OCD2 = 1
FRA01 = 0 CM07 = 1
CM05 = 0 CM07 = 0
CM13 = 1 CM14 = 0
OCD2 = 0 FRA00 = 1 OCD2 = 1
FRA01 = 1 FRA01 = 0
CM04 = 1
High-speed clock mode CM07 = 1
CM05 = 0 Low-speed clock mode
CM07 = 0 CM04 = 1
CM13 = 1 CM07 = 1
OCD2 = 0 CM05 = 0
CM07 = 0
CM13 = 1
CM14 = 0
OCD2 = 0
FRA01 = 0
OCD2 = 1
FRA00 = 1
CM04 = 1
FRA01 = 1
CM07 = 1
CM05 = 0 CM07 = 0
CM13 = 1 OCD2 = 1
OCD2 = 0 High-speed on-chip oscillator mode FRA00 = 1
CM07 = 0 FRA01 = 1
OCD2 = 1
FRA00 = 1
FRA01 = 1
Interrupt WAIT instruction Interrupt CM10 = 1
Wait mode Stop mode
CPU operation stops All oscillators stop
CM04, CM05, CM07: Bits in CM0 register

CM13, CM14: Bits in CM1 register
OCD2: Bit in OCD register
FRA00, FRA01: Bits in FRA0 register
Figure 10.15 State Transitions in Power Control Mode
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10.6 Oscillation Stop Detection Function

The oscillation stop detection function detects the stop of the XIN clock oscillating circuit. The oscillation stop
detection function can be enabled and disabled by the OCD0 bit in the OCD register.
Table 10.5 lists the Specifications of Oscillation Stop Detection Function.
When the XIN clock is the CPU clock source and bits OCD1 to OCD0 are set to 11b, the system is placed in the
following state if the XIN clock stops.
• OCD2 bit in OCD register = 1 (on-chip oscillator clock selected)
• OCD3 bit in OCD register = 1 (XIN clock stops)
• CM14 bit in CM1 register = 0 (low-speed on-chip oscillator oscillates)
• Oscillation stop detection interrupt request is generated.
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Table 10.5 Specifications of Oscillation Stop Detection Function
Item Specification
Oscillation stop detection clock and f(XIN) ≥ 2 MHz
frequency bandwidth
Enabled condition for oscillation stop Set bits OCD1 to OCD0 to 11b
detection function
Operation at oscillation stop detection Oscillation stop detection interrupt is generated
10.6.1 How to Use Oscillation Stop Detection Function

• The oscillation stop detection interrupt shares a vector with the voltage monitor 1 interrupt, the voltage
monitor 2 interrupt, and the watchdog timer interrupt. When using the oscillation stop detection interrupt and
watchdog timer interrupt, the interrupt source needs to be determined.
Table 10.6 lists the Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer, Voltage
Monitor 1, and Voltage Monitor 2 Interrupts. Figure 10.17 shows an Example of Determining Interrupt
Source for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt.
• When the XIN clock restarts after oscillation stop, switch the XIN clock to the clock source of the CPU clock
and peripheral functions by a program.
Figure 10.16 shows the Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator to XIN
Clock.
• To enter wait mode while using the oscillation stop detection function, set the CM02 bit to 0 (peripheral
function clock does not stop in wait mode).
• Since the oscillation stop detection function is a function for cases where the XIN clock is stopped by an
external cause, set bits OCD1 to OCD0 to 00b when the XIN clock stops or is started by a program, (stop
mode is selected or the CM05 bit is changed).
• This function cannot be used when the XIN clock frequency is 2 MHz or below. In this case, set bits OCD1 to
OCD0 to 00b.
• To use the low-speed on-chip oscillator clock for the CPU clock and clock sources of peripheral functions
after detecting the oscillation stop, set the FRA01 bit in the FRA0 register to 0 (low-speed on-chip oscillator
selected) and bits OCD1 to OCD0 to 11b.
To use the high-speed on-chip oscillator clock for the CPU clock and clock sources of peripheral functions
after detecting the oscillation stop, set the FRA00 bit to 1 (high-speed on-chip oscillator on) and the FRA01
bit to 1 (high-speed on-chip oscillator selected) and then set bits OCD1 to OCD0 to 11b.
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Table 10.6 Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer,
Voltage Monitor 1, and Voltage Monitor 2 Interrupts
Generated Interrupt Source Bit Showing Interrupt Cause
Oscillation stop detection (a) OCD3 bit in OCD register = 1
((a) or (b)) (b) OCD1 to OCD0 bits in OCD register = 11b and OCD2 bit = 1
Watchdog timer VW2C3 bit in VW2C register = 1
Voltage monitor 1 VW1C2 bit in VW1C register = 1
Voltage monitor 2 VW2C2 bit in VW2C register = 1
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Switch to XIN clock
NO Multiple confirmations
that OCD3 bit is set to 0 (XIN
clock oscillates) ?
YES
Set OCD1 to OCD0 bits to 00b
Set OCD2 bit to 0

(select XIN clock)
End
OCD3 to OCD0: Bits in OCD register
Figure 10.16 Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator to XIN
Clock
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Interrupt sources judgment
OCD3 = 1 ? NO
(XIN clock stopped)
YES
OCD1 = 1
(oscillation stop detection
www.DataSheet4U.com interrupt enabled) and OCD2 = 1 NO
(on-chip oscillator clock selected
as system clock) ?
YES
VW2C3 = 1 ?
NO
(Watchdog timer
underflow)
YES
VW2C2 = 1 ? NO
(passing Vdet2)
YES
Set OCD1 bit to 0 (oscillation stop

detection interrupt disabled). (1)
To oscillation stop detection To watchdog timer To voltage monitor 2 To voltage monitor 1

interrupt routine interrupt routine interrupt routine interrupt routine
NOTE:
1. This disables multiple oscillation stop detection interrupts.
OCD1 to OCD3: Bits in OCD register

Figure 10.17 Example of Determining Interrupt Source for Oscillation Stop Detection, Watchdog
Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt
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10.7 Notes on Clock Generation Circuit
10.7.1 Stop Mode

When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the
CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instruction
which sets the CM10 bit to 1 (stop mode) and the program stops.
Insert at least 4 NOP instructions following the JMP.B instruction after the instruction which sets the CM10 bit
to 1.
• Program example to enter stop mode

BCLR 1,FMR0 ; CPU rewrite mode disabled
www.DataSheet4U.com BSET 0,PRCR ; Protect disabled
FSET I ; Enable interrupt
BSET 0,CM1 ; Stop mode
JMP.B LABEL_001
LABEL_001 :
NOP
NOP
NOP
NOP
10.7.2 Wait Mode

When entering wait mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and
execute the WAIT instruction. An instruction queue pre-reads 4 bytes from the WAIT instruction and the
program stops. Insert at least 4 NOP instructions after the WAIT instruction.
• Program example to execute the WAIT instruction

WAIT ; Wait mode
NOP
NOP
NOP
NOP
10.7.3 Oscillation Stop Detection Function

Since the oscillation stop detection function cannot be used if the XIN clock frequency is 2 MHz or below, set
bits OCD1 to OCD0 to 00b.
10.7.4 Oscillation Circuit Constants

Ask the manufacturer of the oscillator to specify the best oscillation circuit constants for your system.
To use this MCU with supply voltage below VCC = 2.7 V, it is recommended to set the CM11 bit in the CM1
register to 1 (on-chip feedback resistor disabled), the CM15 bit to 1 (high drive capacity), and connect the
feedback resistor to the chip externally.
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R8C/24 Group, R8C/25 Group 11. Protection
11. Protection
The protection function protects important registers from being easily overwritten when a program runs out of control.
Figure 11.1 shows the PRCR Register. The registers protected by the PRCR register are listed below.
• Registers protected by PRC0 bit: Registers CM0, CM1, OCD, FRA0, FRA1, and FRA2
• Registers protected by PRC1 bit: Registers PM0 and PM1
• Registers protected by PRC2 bit: PD0 register
• Registers protected by PRC3 bit: Registers VCA2, VW0C, VW1C, and VW2C
Protect Register
b7 b6 b5 b4 b3 b2 b1 b0
www.DataSheet4U.com 0 0 Symbol Address After Reset

PRCR 000Ah 00h
Protect bit 0 Writing to registers CM0, CM1, OCD, FRA0, FRA1,
and FRA2 is enabled.
PRC0 0 : Disables w riting RW
1 : Enables w riting
Protect bit 1 Writing to registers PM0 and PM1 is enabled.
Protect bit 2 Writing to the PD0 register is enabled.
1 : Enables w riting(1)
Protect bit 3 Writing to registers VCA2, VW0C, VW1C, and
VW2C is enabled.
RW
(b5-b4)
— Reserved bits When read, the content is 0.
RO
(b7-b6)
NOTE:
1. This bit is set to 0 after w riting 1 to the PRC2 bit and executing a w rite to any address. Since the other bits are not
set to 0, set them to 0 by a program.
Figure 11.1 PRCR Register
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R8C/24 Group, R8C/25 Group 12. Interrupts
12. Interrupts
12.1 Interrupt Overview
12.1.1 Types of Interrupts

Figure 12.1 shows the Types of Interrupts.
Undefined instruction (UND instruction)

www.DataSheet4U.com Overflow (INTO instruction)
Software
BRK instruction
(non-maskable interrupts)
INT instruction
Interrupts Watchdog timer

Oscillation stop detection
Voltage monitor 1
Special Voltage monitor 2
(non-maskable interrupts) Single step(2)
Hardware
Address break(2)
Address match
Peripheral functions(1)
(maskable interrupts)
NOTES:
1. Peripheral function interrupts in the MCU are used to generate peripheral interrupts.
2. Do not use this interrupt. This is for use with development tools only.
Figure 12.1 Types of Interrupts
• Maskable Interrupts: The interrupt enable flag (I flag) enables or disables these interrupts. The
interrupt priority order can be changed based on the interrupt priority level.
• Non-Maskable Interrupts: The interrupt enable flag (I flag) does not enable or disable these interrupts.
The interrupt priority order cannot be changed based on interrupt priority
level.
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12.1.2 Software Interrupts

A software interrupt is generated when an instruction is executed. Software interrupts are non-maskable.
12.1.2.1 Undefined Instruction Interrupt

The undefined instruction interrupt is generated when the UND instruction is executed.
12.1.2.2 Overflow Interrupt

The overflow interrupt is generated when the O flag is set to 1 (arithmetic operation overflow) and the INTO
instruction is executed. Instructions that set the O flag are: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX,
NEG, RMPA, SBB, SHA, and SUB.
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12.1.2.3 BRK Interrupt
A BRK interrupt is generated when the BRK instruction is executed.
12.1.2.4 INT Instruction Interrupt

An INT instruction interrupt is generated when the INT instruction is executed. The INT instruction can select
software interrupt numbers 0 to 63. Software interrupt numbers 3 to 31 are assigned to the peripheral function
interrupt. Therefore, the MCU executes the same interrupt routine when the INT instruction is executed as
when a peripheral function interrupt is generated. For software interrupt numbers 0 to 31, the U flag is saved to
the stack during instruction execution and the U flag is set to 0 (ISP selected) before the interrupt sequence is
executed. The U flag is restored from the stack when returning from the interrupt routine. For software interrupt
numbers 32 to 63, the U flag does not change state during instruction execution, and the selected SP is used.
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12.1.3 Special Interrupts

Special interrupts are non-maskable.
12.1.3.1 Watchdog Timer Interrupt

The watchdog timer interrupt is generated by the watchdog timer. For details, refer to 13. Watchdog Timer.
12.1.3.2 Oscillation Stop Detection Interrupt

The oscillation stop detection interrupt is generated by the oscillation stop detection function. For details of the
oscillation stop detection function, refer to 10. Clock Generation Circuit.
12.1.3.3
www.DataSheet4U.com Voltage Monitor 1 Interrupt
The voltage monitor 1 interrupt is generated by the voltage detection circuit. For details of the voltage detection
circuit, refer to 6. Voltage Detection Circuit.
12.1.3.4 Voltage Monitor 2 Interrupt

The voltage monitor 2 interrupt is generated by the voltage detection circuit. For details of the voltage detection
circuit, refer to 6. Voltage Detection Circuit.
12.1.3.5 Single-Step Interrupt, and Address Break Interrupt

Do not use these interrupts. They are for use by development tools only.
12.1.3.6 Address Match Interrupt

The address match interrupt is generated immediately before executing an instruction that is stored at an
address indicated by registers RMAD0 to RMAD1 when the AIER0 or AIER1 bit in the AIER register is set to
1 (address match interrupt enable). For details of the address match interrupt, refer to 12.4 Address Match
Interrupt.
12.1.4 Peripheral Function Interrupt

The peripheral function interrupt is generated by the internal peripheral function of the MCU and is a maskable
interrupt. Refer to Table 12.2 Relocatable Vector Tables for sources of the peripheral function interrupt. For
details of peripheral functions, refer to the descriptions of individual peripheral functions.
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12.1.5 Interrupts and Interrupt Vectors

There are 4 bytes in each vector. Set the starting address of an interrupt routine in each interrupt vector. When
an interrupt request is acknowledged, the CPU branches to the address set in the corresponding interrupt vector.
Figure 12.2 shows an Interrupt Vector.
MSB LSB
Vector address (L)
Low address
Mid address
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0000 High address
Vector address (H) 0000 0000
Figure 12.2 Interrupt Vector
12.1.5.1 Fixed Vector Tables

The fixed vector tables are allocated addresses 0FFDCh to 0FFFFh.
Table 12.1 lists the Fixed Vector Tables. The vector addresses (H) of fixed vectors are used by the ID code
check function. For details, refer to 19.3 Functions to Prevent Rewriting of Flash Memory.
Table 12.1 Fixed Vector Tables

Vector Addresses
Interrupt Source Remarks Reference
Address (L) to (H)
Undefined instruction 0FFDCh to 0FFDFh Interrupt on UND R8C/Tiny Series Software
instruction Manual
Overflow 0FFE0h to 0FFE3h Interrupt on INTO
instruction
BRK instruction 0FFE4h to 0FFE7h If the content of address
0FFE7h is FFh,
program execution
starts from the address
shown by the vector in
the relocatable vector
table.
Address match 0FFE8h to 0FFEBh 12.4 Address Match
Interrupt
Single step(1) 0FFECh to 0FFEFh
Watchdog timer, 0FFF0h to 0FFF3h 13. Watchdog Timer
Oscillation stop detection, 10. Clock Generation Circuit
Voltage monitor 1, 6. Voltage Detection Circuit
Voltage monitor 2
Address break(1) 0FFF4h to 0FFF7h
(Reserved) 0FFF8h to 0FFFBh
Reset 0FFFCh to 0FFFFh 5. Resets
NOTE:
1. Do not use these interrupts. They are for use by development tools only.
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12.1.5.2 Relocatable Vector Tables

The relocatable vector tables occupy 256 bytes beginning from the starting address set in the INTB register.
Table 12.2 lists the Relocatable Vector Tables.
Table 12.2 Relocatable Vector Tables

Software
Vector Addresses(1) Interrupt Control
Interrupt Source Interrupt Reference
Address (L) to Address (H) Register
Number
BRK instruction(3) +0 to +3 (0000h to 0003h) 0 − R8C/Tiny Series Software
Manual
(Reserved) 1 to 2 − −
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Timer RD +32 to +35 (0020h to 0023h) 8 TRD0IC 14.3 Timer RD
(channel 0)
Timer RD +36 to +39 (0024h to 0027h) 9 TRD1IC
(channel 1)
Timer RE +40 to +43 (0028h to 002Bh) 10 TREIC 14.4 Timer RE
Key input +52 to +55 (0034h to 0037h) 13 KUPIC 12.3 Key Input Interrupt
A/D +56 to +59 (0038h to 003Bh) 14 ADIC 18. A/D Converter
Clock synchronous +60 to +63 (003Ch to 003Fh) 15 SSUIC/IICIC 16.2 Clock Synchronous
serial I/O with chip Serial I/O with Chip
select / I2C bus Select (SSU),
interface(2) 16.3 I2C bus Interface
(Reserved) 16 − −
UART0 transmit +68 to +71 (0044h to 0047h) 17 S0TIC 15. Serial Interface
UART0 receive +72 to +75 (0048h to 004Bh) 18 S0RIC
UART1 transmit +76 to +79 (004Ch to 004Fh) 19 S1TIC
UART1 receive +80 to +83 (0050h to 0053h) 20 S1RIC
INT2 +84 to +87 (0054h to 0057h) 21 INT2IC 12.2 INT Interrupt
Timer RA +88 to +91 (0058h to 005Bh) 22 TRAIC 14.1 Timer RA
Timer RB +96 to +99 (0060h to 0063h) 24 TRBIC 14.2 Timer RB
INT3 +104 to +107 (0068h to 006Bh) 26 INT3IC
Software interrupt(3) +128 to +131 (0080h to 0083h) to 32 to 63 − R8C/Tiny Series Software
+252 to +255 (00FCh to 00FFh) Manual
NOTES:
1. These addresses are relative to those in the INTB register.
2. The IICSEL bit in the PMR register switches functions.
3. The I flag does not disable these interrupts.
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12.1.6 Interrupt Control

The following describes enabling and disabling the maskable interrupts and setting the priority for
acknowledgement. The explanation does not apply to nonmaskable interrupts.
Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in each interrupt control register to enable or
disable maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control
register.
Figure 12.3 shows the Interrupt Control Register, Figure 12.4 shows Registers TRD0IC, TRD1IC, SSUIC, and
IICIC and Figure 12.5 shows the INTiIC Register.
Interrupt Control Register(2)

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TREIC 004Ah XXXXX000b
KUPIC 004Dh XXXXX000b
ADIC 004Eh XXXXX000b
S0TIC 0051h XXXXX000b
S0RIC 0052h XXXXX000b
S1TIC 0053h XXXXX000b
S1RIC 0054h XXXXX000b
b7 b6 b5 b4 b3 b2 b1 b0 TRAIC 0056h XXXXX000b
TRBIC 0058h XXXXX000b

Interrupt priority level select bits b2 b1 b0
ILVL0 0 0 0 : Level 0 (interrupt disable) RW

0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
ILVL1 RW
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
ILVL2 1 1 1 : Level 7 RW
Interrupt request bit 0 : Requests no interrupt

IR RW(1)
1 : Requests interrupt
—
(b7-b4) When read, the content is undefined.
NOTES:
1. Only 0 can be w ritten to the IR bit. Do not w rite 1.
2. Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated.
Refer to 12.6.5 Changing Interrupt Control Register Contents .
Figure 12.3 Interrupt Control Register
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Interrupt Control Register(1)

TRD0IC 0048h XXXXX000b
b7 b6 b5 b4 b3 b2 b1 b0 TRD1IC 0049h XXXXX000b
SSUIC/IICIC(2) 004Fh XXXXX000b

ILVL0 0 0 0 : Level 0 (interrupt disable) RW

0 0 1 : Level 1
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0 1 0 : Level 2
0 1 1 : Level 3
ILVL1 RW
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6

IR RO
—
NOTES:
Refer to 12.6.5 Changing Interrupt Control Register Contents.
2. The IICSEL bit in the PMR register sw itches functions.
Figure 12.4 Registers TRD0IC, TRD1IC, SSUIC, and IICIC
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INTi Interrupt Control Register (i=0 to 3)(2)

INT2IC 0055h XX00X000b
INT1IC 0059h XX00X000b
b7 b6 b5 b4 b3 b2 b1 b0 INT3IC 005Ah XX00X000b
0 INT0IC 005Dh XX00X000b

www.DataSheet4U.com 0 0 0 : Level 0 (interrupt disable)
ILVL0 RW
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
ILVL1 RW
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6

IR RW(1)
Polarity sw itch bit(4) 0 : Selects falling edge
POL RW
1 : Selects rising edge(3)
RW
(b5)
—
NOTES:
1. Only 0 can be w ritten to the IR bit. (Do not w rite 1.)
Refer to 12.6.5 Changing Interrupt Control Register Contents.
3. If the INTiPL bit in the INTEN register is set to 1 (both edges), set the POL bit to 0 (selects falling edge).
4. The IR bit may be set to 1 (requests interrupt) w hen the POL bit is rew ritten. Refer to 12.6.4 Changing Interrupt
Sources.
Figure 12.5 INTiIC Register
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12.1.6.1 I Flag
The I flag enables or disables maskable interrupts. Setting the I flag to 1 (enabled) enables maskable interrupts.
Setting the I flag to 0 (disabled) disables all maskable interrupts.
12.1.6.2 IR Bit
The IR bit is set to 1 (interrupt requested) when an interrupt request is generated. Then, when the interrupt
request is acknowledged and the CPU branches to the corresponding interrupt vector, the IR bit is set to 0 (=
interrupt not requested).
The IR bit can be set to 0 by a program. Do not write 1 to this bit.
However, the IR bit operations of the timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select
Interrupt and the I 2 C bus Interface Interrupt are different. Refer to 12.5 Timer RD Interrupt, Clock
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Synchronous Serial I/O with Chip Select Interrupts, and I2C bus Interface Interrupt (Interrupts with
Multiple Interrupt Request Sources).
12.1.6.3 Bits ILVL2 to ILVL0 and IPL

Interrupt priority levels can be set using bits ILVL2 to ILVL0.
Table 12.3 lists the Settings of Interrupt Priority Levels and Table 12.4 lists the Interrupt Priority Levels
Enabled by IPL.
The following are conditions under which an interrupt is acknowledged:

• I flag = 1
• IR bit = 1
• Interrupt priority level > IPL
The I flag, IR bit, bits ILVL2 to ILVL0, and IPL are independent of each other. They do not affect one another.
Table 12.3 Settings of Interrupt Priority Table 12.4 Interrupt Priority Levels Enabled by
Levels IPL
ILVL2 to ILVL0 Bits Interrupt Priority Level Priority Order IPL Enabled Interrupt Priority Levels
000b Level 0 (interrupt disabled) − 000b Interrupt level 1 and above
001b Level 1 Low 001b Interrupt level 2 and above
010b Level 2 010b Interrupt level 3 and above
111b Level 7 High 111b All maskable interrupts are disabled
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12.1.6.4 Interrupt Sequence

An interrupt sequence is performed between an interrupt request acknowledgement and interrupt routine
execution.
When an interrupt request is generated while an instruction is being executed, the CPU determines its interrupt
priority level after the instruction is completed. The CPU starts the interrupt sequence from the following cycle.
However, for the SMOVB, SMOVF, SSTR, or RMPA instruction if an interrupt request is generated while the
instruction is being executed, the MCU suspends the instruction to start the interrupt sequence. The interrupt
sequence is performed as indicated below.
Figure 12.6 shows the Time Required for Executing Interrupt Sequence.
(1) The CPU gets interrupt information (interrupt number and interrupt request level) by reading address
00000h. The IR bit for the corresponding interrupt is set to 0 (interrupt not requested).(2)
www.DataSheet4U.com (2) The FLG register is saved to a temporary register(1) in the CPU immediately before entering the
interrupt sequence.
(3) The I, D and U flags in the FLG register are set as follows:
The I flag is set to 0 (interrupts disabled).
The D flag is set to 0 (single-step interrupt disabled).
The U flag is set to 0 (ISP selected).
However, the U flag does not change state if an INT instruction for software interrupt number 32 to 63
is executed.
(4) The CPU’s internal temporary register(1) is saved to the stack.
(5) The PC is saved to the stack.
(6) The interrupt priority level of the acknowledged interrupt is set in the IPL.
(7) The starting address of the interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, instructions are executed from the starting address of the interrupt
routine.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
CPU Clock
Address Bus Address Undefined SP-2 SP-1 SP-4 SP-3 VEC VEC+1 VEC+2 PC
0000h
Data Bus Interrupt Undefined SP-2 SP-1 SP-4 SP-3 VEC VEC+1 VEC+2
information contents contents contents contents contents contents contents
RD Undefined
WR
The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is
ready to acknowledge instructions.
Figure 12.6 Time Required for Executing Interrupt Sequence
NOTES:
1. This register cannot be accessed by the user.
2. Refer to 12.5 Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupts, and
I2C bus Interface Interrupt (Interrupts with Multiple Interrupt Request Sources) for the IR bit
operations of the timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupt, and the
I2C bus Interface Interrupt.
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12.1.6.5 Interrupt Response Time

Figure 12.7 shows the Interrupt Response Time. The interrupt response time is the period between an interrupt
request generation and the execution of the first instruction in the interrupt routine. The interrupt response time
includes the period between interrupt request generation and the completion of execution of the instruction
(refer to (a) in Figure 12.7) and the period required to perform the interrupt sequence (20 cycles, refer to (b) in
Figure 12.7).
Interrupt request is generated. Interrupt request is acknowledged.
Time
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Instruction in
Instruction Interrupt sequence
interrupt routine
(a) 20 cycles (b)
Interrupt response time
(a) Period between interrupt request generation and the completion of execution of an
instruction. The length of time varies depending on the instruction being executed. The
DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a
register is set as the divisor).
(b) 21 cycles for address match and single-step interrupts.
Figure 12.7 Interrupt Response Time
12.1.6.6 IPL Change when Interrupt Request is Acknowledged

When an interrupt request of a maskable interrupt is acknowledged, the interrupt priority level of the
acknowledged interrupt is set in the IPL.
When a software interrupt or special interrupt request is acknowledged, the level listed in Table 12.5 is set in
the IPL.
Table 12.5 lists the IPL Value When Software or Special Interrupt Is Acknowledged.
Table 12.5 IPL Value When Software or Special Interrupt Is Acknowledged

Interrupt Source Value Set in IPL
Watchdog timer, oscillation stop detection, voltage monitor 1, 7
voltage monitor 2, Address break
Software, address match, single-step Not changed
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12.1.6.7 Saving a Register

In the interrupt sequence, the FLG register and PC are saved to the stack.
After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG
register, are saved to the stack, the 16 low-order bits in the PC are saved.
Figure 12.8 shows the Stack State Before and After Acknowledgement of Interrupt Request.
The other necessary registers are saved by a program at the beginning of the interrupt routine. The PUSHM
instruction can save several registers in the register bank being currently used(1) with a single instruction.
NOTE:
1. Selectable from registers R0, R1, R2, R3, A0, A1, SB, and FB.
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Address Stack Address Stack
MSB LSB MSB LSB
[SP]
m−4 m−4 PCL New SP value
m−3 m−3 PCM
m−2 m−2 FLGL
m−1 m−1 FLGH PCH

[SP]
m m
Previous stack contents SP value before Previous stack contents PCH : 4 high-order bits of PC
interrupt is generated PCM : 8 middle-order bits of PC
m+1 m+1 PCL : 8 low-order bits of PC
Previous stack contents Previous stack contents FLGH : 4 high-order bits of FLG
FLGL : 8 low-order bits of FLG
Stack state before interrupt request Stack state after interrupt request
is acknowledged is acknowledged
NOTE:
1. When executing software number 32 to 63 INT instructions,
this SP is specified by the U flag. Otherwise it is ISP.
Figure 12.8 Stack State Before and After Acknowledgement of Interrupt Request
The register saving operation, which is performed as part of the interrupt sequence, saved in 8 bits at a time in
four steps.
Figure 12.9 shows the Register Saving Operation.
Stack
Address
Sequence in which
order registers are
saved
[SP]−5
[SP]−4 PCL (3)
[SP]−3 PCM (4)
Saved, 8 bits at a time

[SP]−2 FLGL (1)
[SP]−1 (2)
FLGH PCH
PCH : 4 high-order bits of PC
PCM : 8 middle-order bits of PC
[SP] PCL : 8 low-order bits of PC
Completed saving FLGH : 4 high-order bits of FLG
registers in four FLGL : 8 low-order bits of FLG
operations.
NOTE:
1. [SP] indicates the initial value of the SP when an interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4. When executing
software number 32 to 63 INT instructions, this SP is specified by the U
flag. Otherwise it is ISP.
Figure 12.9 Register Saving Operation
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12.1.6.8 Returning from an Interrupt Routine

When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have
been saved to the stack, are automatically restored. The program, that was running before the interrupt request
was acknowledged, starts running again.
Restore registers saved by a program in an interrupt routine using the POPM instruction or others before
executing the REIT instruction.
12.1.6.9 Interrupt Priority

If two or more interrupt requests are generated while a single instruction is being executed, the interrupt with
the higher priority is acknowledged.
Set bits ILVL2 to ILVL0 to select the desired priority level for maskable interrupts (peripheral functions).
www.DataSheet4U.com However, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by
hardware, and the higher priority interrupts acknowledged.
The priority levels of special interrupts, such as reset (reset has the highest priority) and watchdog timer, are set
by hardware.
Figure 12.10 shows the Priority Levels of Hardware Interrupts.
The interrupt priority does not affect software interrupts. The MCU jumps to the interrupt routine when the
instruction is executed.
High
Reset
Address break
Watchdog timer
Voltage monitor 1
Voltage monitor 2
Peripheral function
Single step
Address match
Low
Figure 12.10 Priority Levels of Hardware Interrupts
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12.1.6.10 Interrupt Priority Judgement Circuit

The interrupt priority judgement circuit selects the highest priority interrupt, as shown in Figure 12.11.
Priority level of interrupt Highest

Level 0 (default value)
INT3
Timer RB
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INT0
INT1
UART1 receive
Priority of peripheral function interrupts
UART0 receive (if priority levels are same)
A/D conversion
Timer RE
Timer RD0
INT2
UART1 transmit
UART0 transmit
SSU / I2C bus(1)
Key input
Timer RD1
IPL Lowest
Interrupt request level
judgment output signal
I flag Interrupt request

acknowledged
Address match
Watchdog timer
Voltage monitor 1
Voltage monitor 2
NOTE:
1. The IICSEL bit in the PMR register switches functions.
Figure 12.11 Interrupt Priority Level Judgement Circuit
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12.2 INT Interrupt
12.2.1 INTi Interrupt (i = 0 to 3)

The INTi interrupt is generated by an INTi input. When using the INTi interrupt, the INTiEN bit in the INTEN
register is set to 1 (enable). The edge polarity is selected using the INTiPL bit in the INTEN register and the
POL bit in the INTiIC register.
Inputs can be passed through a digital filter with three different sampling clocks.
The INT0 pin is shared with the pulse output forced cutoff of timer RD and the external trigger input of timer
RB.
Figure 12.12 shows the INTEN Register. Figure 12.13 shows the INTF Register.
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External Input Enable Register

b7 b6 b5 b4 b3 b2 b1 b0

INTEN 00F9h 00h
_____
INT0 input enable bit 0 : Disable
INT0EN RW
1 : Enable
_____
INT0 input polarity select bit(1,2) 0 : One edge
INT0PL RW
1 : Both edges
_____
INT1EN RW
1 : Enable
_____
INT1PL RW
1 : Both edges
_____
INT2EN RW
1 : Enable
_____
INT2PL RW
1 : Both edges
_____
INT3EN RW
1 : Enable
_____
INT3PL RW
1 : Both edges
NOTES:
1. When setting the INTiPL bit (i = 0 to 3) to 1 (both edges), set the POL bit in the INTiIC register to 0 (selects falling
edge).
2. The IR bit in the INTiIC register may be set to 1 (requests interrupt) w hen the INTiPL bit is rew ritten. Refer to 12.6.4
Changing Interrupt Sources.
Figure 12.12 INTEN Register
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_______
INT0 Input Filter Select Register
b7 b6 b5 b4 b3 b2 b1 b0

INTF 00FAh 00h
_____ b1 b0
INT0 input filter select bits 0 0 : No filter
INT0F0 RW
0 1 : Filter w ith f1 sampling
www.DataSheet4U.com INT0F1 1 1 : Filter w ith f32 sampling RW
_____ b3 b2
INT1F0 RW
INT1F1 1 1 : Filter w ith f32 sampling RW
_____ b5 b4
INT2F0 RW
_____ b7 b6
INT3F0 RW
Figure 12.13 INTF Register
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12.2.2 INTi Input Filter (i = 0 to 3)

The INTi input contains a digital filter. The sampling clock is selected by bits INTiF1 to INTiF0 in the INTF
register.
The INTi level is sampled every sampling clock cycle and if the sampled input level matches three times, the IR
bit in the INTiIC register is set to 1 (interrupt requested).
Figure 12.14 shows the Configuration of INTi Input Filter. Figure 12.15 shows an Operating Example of INTi
Input Filter.
INTiF1 to INTiF0
f1 = 01b
www.DataSheet4U.com = 10b Sampling clock
f8
= 11b
f32 INTiEN
Other than
INTiF1 to INTiF0
INTi = 00b INTi interrupt
Digital filter
(input level
Port direction matches 3x) = 00b INTiPL = 0
register(1)
Both edges
detection
INTiPL = 1
circuit
INTiF0, INTiF1: Bits in INTF register
INTiEN, INTiPL: Bits in INTEN register
i = 0 to 3
NOTE:
1. INT0: Port P4_5 direction register
INT1: Port P1_5 direction register when using the P1_5 pin
Port P1_7 direction register when using the P1_7 pin
INT2: Port P6_6 direction register
INT3: Port P6_7 direction register
Figure 12.14 Configuration of INTi Input Filter
INTi input
Sampling
timing
IR bit in
INTiIC register
This is an operation example when bits INTiF1 to INTiF0 in the

INTiF register are set to 01b, 10b, or 11b (digital filter enabled).
i = 0 to 3
Figure 12.15 Operating Example of INTi Input Filter
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12.3 Key Input Interrupt

A key input interrupt request is generated by one of the input edges of pins K10 to K13. The key input interrupt can
be used as a key-on wake-up function to exit wait or stop mode.
The KIiEN (i = 0 to 3) bit in the KIEN register can select whether or not the pins are used as KIi input. The KIiPL
bit in the KIEN register can select the input polarity.
When inputting “L” to the KIi pin which sets the KIiPL bit to 0 (falling edge), the input of the other pins K10 to
K13 is not detected as interrupts. Also, when inputting “H” to the KIi pin, which sets the KIiPL bit to 1 (rising
edge), the input of the other pins K10 to K13 is not detected as interrupts.
Figure 12.16 shows a Block Diagram of Key Input Interrupt.
www.DataSheet4U.com PU02 bit in PUR0 register

Pull-up KUPIC register
PD1_3 bit in PD1 register
transistor
KI3EN bit
PD1_3 bit
KI3PL = 0
KI3
KI3PL = 1
KI2EN bit
Pull-up PD1_2 bit
transistor
KI2PL = 0
Interrupt control Key input interrupt
KI2 circuit request
KI2PL = 1
KI1EN bit
Pull-up PD1_1 bit
transistor
KI1PL = 0
KI1
KI1PL = 1
KI0EN bit KI0EN, KI1EN, KI2EN, KI3EN,
Pull-up KI0PL, KI1PL, KI2PL, KI3PL: Bits in KIEN register
PD1_0 bit
transistor PD1_0, PD1_1, PD1_2, PD1_3: Bits in PD1 register
KI0PL = 0
KI0
KI0PL = 1
Figure 12.16 Block Diagram of Key Input Interrupt
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Key Input Enable Register(1)

b7 b6 b5 b4 b3 b2 b1 b0

KIEN 00FBh 00h
KI0 input enable bit 0 : Disable
KI0EN RW
1 : Enable
KI0 input polarity select bit 0 : Falling edge
KI0PL RW
1 : Rising edge
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KI1EN RW
1 : Enable
KI1PL RW
1 : Rising edge
KI2EN RW
1 : Enable
KI2PL RW
1 : Rising edge
KI3EN RW
1 : Enable
KI3PL RW
1 : Rising edge
NOTE:
1. The IR bit in the KUPIC register may be set to 1 (requests interrupt) w hen the KIEN register is rew ritten.
Refer to 12.6.4 Changing Interrupt Sources.
Figure 12.17 KIEN Register
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12.4 Address Match Interrupt

An address match interrupt request is generated immediately before execution of the instruction at the address
indicated by the RMADi register (i = 0 or 1). This interrupt is used as a break function by the debugger. When
using the on-chip debugger, do not set an address match interrupt (registers of AIER, RMAD0, and RMAD1 and
fixed vector tables) in a user system.
Set the starting address of any instruction in the RMADi register. Bits AIER0 and AIER1 in the AIER0 register can
be used to select enable or disable of the interrupt. The I flag and IPL do not affect the address match interrupt.
The value of the PC (Refer to 12.1.6.7 Saving a Register for the value of the PC) which is saved to the stack when
an address match interrupt is acknowledged varies depending on the instruction at the address indicated by the
RMADi register. (The appropriate return address is not saved on the stack.) When returning from the address match
interrupt, return by one of the following means:
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• Change the content of the stack and use the REIT instruction.
• Use an instruction such as POP to restore the stack as it was before the interrupt request was acknowledged.
Then use a jump instruction.
Table 12.6 lists the Values of PC Saved to Stack when Address Match Interrupt is Acknowledged.
Figure 12.18 shows Registers AIER and RMAD0 to RMAD1.
Table 12.6 Values of PC Saved to Stack when Address Match Interrupt is Acknowledged
Address Indicated by RMADi Register (i = 0 or 1) PC Value Saved(1)
• Instruction with 2-byte operation code(2) Address indicated by
• Instruction with 1-byte operation code(2) RMADi register + 2
ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest
OR.B:S #IMM8,dest MOV.B:S #IMM8,dest STZ #IMM8,dest
STNZ #IMM8,dest STZX #IMM81,#IMM82,dest
CMP.B:S #IMM8,dest PUSHM src POPM dest
JMPS #IMM8 JSRS #IMM8
MOV.B:S #IMM,dest (however, dest = A0 or A1)
• Instructions other than the above Address indicated by
RMADi register + 1
NOTES:
1. Refer to the 12.1.6.7 Saving a Register for the PC value saved.
2. Operation code: Refer to the R8C/Tiny Series Software Manual (REJ09B0001).
Chapter 4. Instruction Code/Number of Cycles contains diagrams showing
operation code below each syntax. Operation code is shown in the bold frame in the
diagrams.
Table 12.7 Correspondence Between Address Match Interrupt Sources and Associated Registers
Address Match Interrupt Source Address Match Interrupt Enable Bit Address Match Interrupt Register
Address match interrupt 0 AIER0 RMAD0
Address match interrupt 1 AIER1 RMAD1
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Address Match Interrupt Enable Register

b7 b6 b5 b4 b3 b2 b1 b0

AIER 0013h 00h
Address match interrupt 0 enable bit 0 : Disable
AIER0 RW
1 : Enable
Address match interrupt 1 enable bit 0 : Disable
AIER1 RW
1 : Enable
www.DataSheet4U.com — Nothing is assigned. If necessary, set to 0.
—
Address Match Interrupt Register i (i = 0 or 1)

(b23) (b19) (b16) (b15) (b8)
b7 b3 b0 b7 b0 b7 b0

RMAD0 0012h-0010h 000000h
RMAD1 0016h-0014h 000000h
Function Setting Range RW
Address setting register for address match interrupt 00000h to FFFFFh RW
—
Figure 12.18 Registers AIER and RMAD0 to RMAD1
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12.5 Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select
Interrupts, and I2C bus Interface Interrupt (Interrupts with Multiple Interrupt
Request Sources)
The timer RD (channel 0) interrupt, timer RD (channel 1) interrupt, clock synchronous serial I/O with chip select
interrupt, and I2C bus interface interrupt each have multiple interrupt request sources. An interrupt request is
generated by the logical OR of several interrupt request factors and is reflected in the IR bit in the corresponding
interrupt control register. Therefore, each of these peripheral functions has its own interrupt request source status
register (status register) and interrupt request source enable register (enable register) to control the generation of
interrupt requests (change the IR bit in the interrupt control register). Table 12.8 lists the Registers Associated with
Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupt, and I2C bus Interface Interrupt and
Figure 12.19 shows a Block Diagram of Timer RD Interrupt.
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Table 12.8 Registers Associated with Timer RD Interrupt, Clock Synchronous Serial I/O with
Chip Select Interrupt, and I2C bus Interface Interrupt
Status Register of Enable Register of Interrupt Control
Interrupt Request Source Interrupt Request Source Register
Timer RD Channel 0 TRDSR0 TRDIER0 TRD0IC
Channel 1 TRDSR1 TRDIER1 TRD1IC
Clock synchronous serial SSSR SSER SSUIC
I/O with chip select
I2C bus interface ICSR ICIER IICIC
Channel i
IMFA bit
Timer RD (channel i)
IMIEA bit interrupt request
(IR bit in TRDiIC register)
IMFB bit
IMIEB bit
IMFC bit
IMIEC bit
IMFD bit
IMIED bit
UDF bit
OVF bit
OVIE bit
i = 0 or 1
IMFA, IMFB, IMFC, IMFD, OVF, UDF: Bits in TRDSRi register
IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRDIER register
Figure 12.19 Block Diagram of Timer RD Interrupt
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As with other maskable interrupts, the timer RD (channel 0) interrupt, timer RD (channel 1) interrupt, clock
synchronous serial I/O with chip select interrupt, and I2C bus interface interrupt are controlled by the combination
of the I flag, IR bit, bits ILVL0 to ILVL2, and IPL. However, since each interrupt source is generated by a
combination of multiple interrupt request sources, the following differences from other maskable interrupts apply:
• When bits in the enable register corresponding to bits set to 1 in the status register are set to 1 (enable
interrupt), the IR bit in the interrupt control register is set to 1 (interrupt requested).
• When either bits in the status register or bits in the enable register corresponding to bits in the status register, or
both, are set to 0, the IR bit is set to 0 (interrupt not requested). Basically, even though the interrupt is not
acknowledged after the IR bit is set to 1, the interrupt request will not be maintained. Also, the IR bit is not set
to 0 even if 0 is written to the IR bit.
• Individual bits in the status register are not automatically set to 0 even if the interrupt is acknowledged.
Therefore, the IR bit is also not automatically set to 0 when the interrupt is acknowledged. Set each bit in the
www.DataSheet4U.com status register to 0 in the interrupt routine. Refer to the status register figure for how to set individual bits in the
status register to 0.
• When multiple bits in the enable register are set to 1 and other request sources are generated after the IR bit is
set to 1, the IR bit remains 1.
• When multiple bits in the enable register are set to 1, determine by the status register which request source
causes an interrupt.
Refer to chapters of the individual peripheral functions (14.3 Timer RD, 16.2 Clock Synchronous Serial I/O with
Chip Select (SSU) and 16.3 I2C bus Interface) for the status register and enable register.
Refer to 12.1.6 Interrupt Control for the interrupt control register.
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12.6 Notes on Interrupts
12.6.1 Reading Address 00000h

Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads
interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At
this time, the acknowledged interrupt IR bit is set to 0.
If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the
enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be
generated.
12.6.2 SP Setting
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Set any value in the SP before an interrupt is acknowledged. The SP is set to 0000h after reset. Therefore, if an
interrupt is acknowledged before setting a value in the SP, the program may run out of control.
12.6.3 External Interrupt and Key Input Interrupt

Either “L” level or an “H” level of width shown in the Electrical Characteristics is necessary for the signal input
to pins INT0 to INT3 and pins KI0 to KI3, regardless of the CPU clock.
For details, refer to Table 20.21 (VCC = 5V), Table 20.27 (VCC = 3V), Table 20.33 (VCC = 2.2V) External
Interrupt INTi (i = 0 to 3) Input.
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12.6.4 Changing Interrupt Sources

The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source
changes. When using an interrupt, set the IR bit to 0 (no interrupt requested) after changing the interrupt source.
In addition, changes of interrupt sources include all factors that change the interrupt sources assigned to
individual software interrupt numbers, polarities, and timing. Therefore, if a mode change of a peripheral
function involves interrupt sources, edge polarities, and timing, set the IR bit to 0 (no interrupt requested) after
the change. Refer to the individual peripheral function for its related interrupts.
Figure 12.20 shows an Example of Procedure for Changing Interrupt Sources.
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Interrupt source change
Disable interrupts(2, 3)
Change interrupt source (including mode

of peripheral function)
Set the IR bit to 0 (interrupt not requested)

using the MOV instruction(3)
Enable interrupts (2, 3)
Change completed
IR bit: The interrupt control register bit of an

interrupt whose source is changed.
NOTES:
1. Execute the above settings individually. Do not execute two
or more settings at once (by one instruction).
2. To prevent interrupt requests from being generated, disable
the peripheral function before changing the interrupt
source. In this case, use the I flag if all maskable interrupts
can be disabled. If all maskable interrupts cannot be
disabled, use bits ILVL0 to ILVL2 of the interrupt whose
source is changed.
3. Refer to 12.6.5 Changing Interrupt Control Register
Contents for the instructions to be used and usage notes.
Figure 12.20 Example of Procedure for Changing Interrupt Sources
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12.6.5 Changing Interrupt Control Register Contents

(a) The contents of an interrupt control register can only be changed while no interrupt requests
corresponding to that register are generated. If interrupt requests may be generated, disable interrupts
before changing the interrupt control register contents.
(b) When changing the contents of an interrupt control register after disabling interrupts, be careful to
choose appropriate instructions.
Changing any bit other than IR bit
If an interrupt request corresponding to a register is generated while executing the instruction, the IR bit
may not be set to 1 (interrupt requested), and the interrupt request may be ignored. If this causes a
problem, use the following instructions to change the register: AND, OR, BCLR, BSET
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Changing IR bit
If the IR bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction used.
Therefore, use the MOV instruction to set the IR bit to 0.
(c) When disabling interrupts using the I flag, set the I flag as shown in the sample programs below. Refer
to (b) regarding changing the contents of interrupt control registers by the sample programs.
Sample programs 1 to 3 are for preventing the I flag from being set to 1 (interrupts enabled) before the interrupt
control register is changed for reasons of the internal bus or the instruction queue buffer.
Example 1: Use NOP instructions to prevent I flag from being set to 1 before interrupt control register
is changed
INT_SWITCH1:
FCLR I ; Disable interrupts
AND.B #00H,0056H ; Set TRAIC register to 00h
NOP ;
NOP
FSET I ; Enable interrupts
Example 2: Use dummy read to delay FSET instruction

INT_SWITCH2:
MOV.W MEM,R0 ; Dummy read
Example 3: Use POPC instruction to change I flag

INT_SWITCH3:
PUSHC FLG
POPC FLG ; Enable interrupts
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R8C/24 Group, R8C/25 Group 13. Watchdog Timer
13. Watchdog Timer

The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is
recommended to improve the reliability of the system. The watchdog timer contains a 15-bit counter and allows
selection of count source protection mode enable or disable.
Table 13.1 lists information on the Count Source Protection Mode.
Refer to 5.6 Watchdog Timer Reset for details on the watchdog timer.
Figure 13.1 shows the Block Diagram of Watchdog Timer. Figure 13.2 shows the Registers OFS and WDC, Figure
13.3 shows Registers WDTR, WDTS, and CSPR.
Table 13.1 Count Source Protection Mode

Count Source Protection Count Source Protection
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Mode Disabled Mode Enabled
Count source CPU clock Low-speed on-chip oscillator
clock
Count operation Decrement
Count start condition Either of the following can be selected
• After reset, count starts automatically
• Count starts by writing to WDTS register
Count stop condition Stop mode, wait mode None
Reset condition of watchdog • Reset
timer • Write 00h to the WDTR register before writing FFh
• Underflow
Operation at the time of underflow Watchdog timer interrupt or Watchdog timer reset
watchdog timer reset
Prescaler
CM07 = 0,
WDC7 = 0
1/16
CSPRO = 0 PM12 = 0
1/128 Watchdog timer
CM07 = 0, interrupt request
WDC7 = 1
CPU clock 1/2 Watchdog timer
CM07 = 1
PM12 = 1
fOCO-S Watchdog
CSPRO = 1
timer reset
Set to
7FFFh(1)
Write to WDTR register
(“L” active)
CSPRO: Bit in CSPR register

WDC7: Bit in WDC register
PM12: Bit in PM1 register
CM07: Bit in CM0 register
NOTE:
1. When the CSPRO bit is set to 1 (count source protection mode enabled), 0FFFh is set.
Figure 13.1 Block Diagram of Watchdog Timer
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b7 b6 b5 b4 b3 b2 b1 b0

OFS 0FFFFh FFh(3)
WDTON RW
RW
(b1)
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ROMCR RW
ROMCP1 RW
RW
(b4)
reset
RW
(b6)
bit
NOTES:
Watchdog Timer Control Register

b7 b6 b5 b4 b3 b2 b1 b0

WDC 000Fh 00X11111b
— High-order bits of w atchdog timer
RO
(b4-b0)
— Reserved bit Set to 0. When read, the content is undefined.
RW
(b5)
RW
(b6)
Prescaler select bit 0 : Divide-by-16
WDC7 RW
1 : Divide-by-128
Figure 13.2 Registers OFS and WDC
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Watchdog Timer Reset Register

b7 b0

WDTR 000Dh Undefined
Function RW
When 00h is w ritten before w riting FFh, the w atchdog timer is reset.(1)
The default value of the w atchdog timer is 7FFFh w hen count source protection
mode is disabled and 0FFFh w hen count source protection mode is enabled.(2) WO
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NOTES:
1. Do not generate an interrupt betw een w hen 00h and FFh are w ritten.
2. When the CSPRO bit in the CSPR register is set to 1 (count source protection mode enabled),
0FFFh is set in the w atchdog timer.
Watchdog Timer Start Register

b7 b0

WDTS 000Eh Undefined
Function RW
The w atchdog timer starts counting after a w rite instruction to this register.
WO
Count Source Protection Mode Register

b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 0 Symbol Address After Reset(1)

CSPR 001Ch 00h
RW
(b6-b0)
Count source protection mode 0 : Count source protection mode disabled
CSPRO RW
select bit(2) 1 : Count source protection mode enabled
NOTES:
1. When 0 is w ritten to the CSPROINI bit in the OFS register, the value after reset is 10000000b.
2. Write 0 before w riting 1 to set the CSPRO bit to 1. 0 cannot be set by a program.
Figure 13.3 Registers WDTR, WDTS, and CSPR
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13.1 Count Source Protection Mode Disabled

The count source of the watchdog timer is the CPU clock when count source protection mode is disabled.
Table 13.2 lists the Watchdog Timer Specifications (with Count Source Protection Mode Disabled).
Table 13.2 Watchdog Timer Specifications (with Count Source Protection Mode Disabled)
Item Specification
Count source CPU clock
Period Division ratio of prescaler (n) × count value of watchdog timer (32768)(1)
CPU clock
www.DataSheet4U.com n: 16 or 128 (selected by WDC7 bit in WDC register)
Example: When the CPU clock frequency is 16 MHz and prescaler
divided by 16, the period is approximately 32.8 ms
Count start condition The WDTON bit(2) in the OFS register (0FFFFh) selects the operation
of the watchdog timer after a reset
• When the WDTON bit is set to 1 (watchdog timer is in stop state after
reset)
The watchdog timer and prescaler stop after a reset and the count
starts when the WDTS register is written to
• When the WDTON bit is set to 0 (watchdog timer starts automatically
after exiting)
The watchdog timer and prescaler start counting automatically after a
reset
• Underflow
Count stop condition Stop and wait modes (inherit the count from the held value after exiting
modes)
Operation at time of underflow • When the PM12 bit in the PM1 register is set to 0
Watchdog timer interrupt
• When the PM12 bit in the PM1 register is set to 1
Watchdog timer reset (refer to 5.6 Watchdog Timer Reset)
NOTES:
1. The watchdog timer is reset when 00h is written to the WDTR register before FFh. The prescaler is
reset after the MCU is reset. Some errors in the period of the watchdog timer may be caused by the
prescaler.
2. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address
0FFFFh with a flash programmer.
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13.2 Count Source Protection Mode Enabled

The count source of the watchdog timer is the low-speed on-chip oscillator clock when count source protection
mode is enabled. If the CPU clock stops when a program is out of control, the clock can still be supplied to the
watchdog timer.
Table 13.3 lists the Watchdog Timer Specifications (with Count Source Protection Mode Enabled).
Table 13.3 Watchdog Timer Specifications (with Count Source Protection Mode Enabled)
Item Specification
Count source Low-speed on-chip oscillator clock
Period
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Count value of watchdog timer (4096)
Low-speed on-chip oscillator clock
Example: Period is approximately 32.8 ms when the low-speed on-
chip oscillator clock frequency is 125 kHz
Count start condition The WDTON bit(1) in the OFS register (0FFFFh) selects the operation
of the watchdog timer after a reset.
• When the WDTON bit is set to 1 (watchdog timer is in stop state
after reset)
The watchdog timer and prescaler stop after a reset and the count
starts when the WDTS register is written to
• When the WDTON bit is set to 0 (watchdog timer starts
automatically after reset)
The watchdog timer and prescaler start counting automatically after
a reset
• Underflow
Count stop condition None (The count does not stop in wait mode after the count starts.
The MCU does not enter stop mode.)
Operation at time of underflow Watchdog timer reset (Refer to 5.6 Watchdog Timer Reset.)
Registers, bits • When setting the CSPPRO bit in the CSPR register to 1 (count
source protection mode is enabled)(2), the following are set
automatically
- Set 0FFFh to the watchdog timer
- Set the CM14 bit in the CM1 register to 0 (low-speed on-chip
oscillator on)
- Set the PM12 bit in the PM1 register to 1 (The watchdog timer is
reset when watchdog timer underflows)
• The following conditions apply in count source protection mode
- Writing to the CM10 bit in the CM1 register is disabled (It remains
unchanged even if it is set to 1. The MCU does not enter stop
mode.)
- Writing to the CM14 bit in the CM1 register is disabled (It remains
unchanged even if it is set to 1. The low-speed on-chip oscillator
does not stop.)
NOTES:
1. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address
0FFFFh with a flash programmer.
2. Even if 0 is written to the CSPROINI bit in the OFS register, the CSPRO bit is set to 1.
The CSPROINI bit cannot be changed by a program. To set the CSPROINI bit, write 0 to bit 7 of
address 0FFFFh with a flash programmer.
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R8C/24 Group, R8C/25 Group 14. Timers
14. Timers
The MCU has two 8-bit timers with 8-bit prescalers, two 16-bit timers, and a timer with a 4-bit counter and an 8-bit
counter. The two 8-bit timers with 8-bit prescalers are timer RA and timer RB. These timers contain a reload register to
store the default value of the counter. The 16-bit timer is timer RD, and has input capture and output compare
functions. The 4 and 8-bit counters are timer RE, and has an output compare function. All the timers operate
independently.
Table 14.1 lists Functional Comparison of Timers.
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Table 14.1 Functional Comparison of Timers

Item Timer RA Timer RB Timer RD Timer RE
Configuration 8-bit timer with 8- 8-bit timer with 8- 16-bit free-run timer × 2 4-bit counter
bit prescaler (with bit prescaler (with (with input capture and 8-bit counter
reload register) reload register) output compare)
Count Decrement Decrement Increment/Decrement Increment
Count sources • f1 • f1 • f1 • f4
• f2 • f2 • f2 • f8
• f8 • f8 • f4 • f32
• fOCO • Timer RA • f8 • fC4
• fC32 underflow • f32
• fOCO40M
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Function Timer mode Provided Provided Provided Not provided
(input capture function,
output compare function)
Pulse output mode Provided Not provided Not provided Not provided
Event counter mode Provided Not provided Not provided Not provided
Pulse width Provided Not provided Not provided Not provided
measurement mode
Pulse period Provided Not provided Not provided Not provided
measurement mode
Programmable Not provided Provided Not provided Not provided
waveform
generation mode
Programmable one- Not provided Provided Not provided Not provided
shot generation
mode
Programmable wait Not provided Provided Not provided Not provided
one-shot generation
mode
Input capture mode Not provided Not provided Provided Not provided
Output compare Not provided Not provided Provided Provided
mode
PWM mode Not provided Not provided Provided Not provided
Reset synchronized Not provided Not provided Provided Not provided
PWM mode
Complementary Not provided Not provided Provided Not provided
PWM mode
PWM3 mode Not provided Not provided Provided Not provided
Real-time clock Not provided Not provided Not provided Provided
mode
Input pin TRAIO INT0 INT0, TRDCLK, −
TRDIOA0, TRDIOA1,
TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1,
TRDIOD0, TRDIOD1
Output pin TRAO TRBO TRDIOA0, TRDIOA1, TREO
TRAIO TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1,
TRDIOD0, TRDIOD1
Related interrupt Timer RA interrupt Timer RB interrupt Compare match/input Timer RE
INT1 interrupt INT0 interrupt Capture A0 to D0 interrupt interrupt
Compare match/input
Capture A1 to D1 interrupt
Overflow interrupt
Underflow interrupt(1)
INT0 interrupt
Timer stop Provided Provided Provided Provided
NOTE:
1. The underflow interrupt can be set to channel 1.
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14.1 Timer RA
Timer RA is an 8-bit timer with an 8-bit prescaler.
The prescaler and timer each consist of a reload register and counter. The reload register and counter are allocated
at the same address, and can be accessed when accessing registers TRAPRE and TRA (refer to Tables 14.2 to 14.6
the Specifications of Each Mode).
The count source for timer RA is the operating clock that regulates the timing of timer operations such as counting
and reloading.
Figure 14.1 shows a Block Diagram of Timer RA. Figures 14.2 and 14.3 show the registers associated with Timer
RA.
Timer RA has the following five operating modes:

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• Timer mode: The timer counts the internal count source.
• Pulse output mode: The timer counts the internal count source and outputs pulses of which
polarity inverted by underflow of the timer.
• Event counter mode: The timer counts external pulses.
• Pulse width measurement mode: The timer measures the pulse width of an external pulse.
• Pulse period measurement mode: The timer measures the pulse period of an external pulse.
Data bus
TCK2 to TCK0 bit Reload Reload

= 000b register register
f1 TCKCUT bit TMOD2 to TMOD0
= 001b = other than 010b TCSTF bit
f8
= 010b Underflow signal
fOCO
= 011b Counter Counter Timer RA interrupt
f2
= 100b TMOD2 to TMOD0
fC32 = 010b TRAPRE register TRA register
TIPF1 to TIPF0 bits (prescaler) (timer)
= 01b
f1
= 10b
f8
= 11b TMOD2 to TMOD0
f32
= 011b or 100b
TIPF1 to TIPF0 bits
TIOSEL = 0 = other than Digital Polarity Count control
INT1/TRAIO (P1_7) pin 000b
filter switching circle
Measurement completion
INT1/TRAIO (P1_5) pin signal
TIOSEL = 1 = 00b
TMOD2 to TMOD0 = 001b
TEDGSEL = 1
TOPCR bit Q
Toggle flip-flop CK
Q CLR
TOENA bit TEDGSEL = 0
Write to TRAMR register
TRAO pin Write 1 to TSTOP bit
TCSTF, TSTOP: Bits in TRACR register
TEDGSEL, TOPCR, TOENA, TIOSEL, TIPF1, TIPF0: Bits in TRAIOC register
TMOD2 to TMOD0, TCK2 to TCK0, TCKCUT: Bits in TRAMR register
Figure 14.1 Block Diagram of Timer RA
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Timer RA Control Register(4)

b7 b6 b5 b4 b3 b2 b1 b0

TRACR 0100h 00h
Timer RA count start bit(1) 0 : Count stops
TSTART RW
1 : Count starts
Timer RA count status flag(1) 0 : Count stops
TCSTF RO
1 : During count
www.DataSheet4U.com Timer RA count forcible stop When this bit is set to 1, the count is forcibly
TSTOP RW
bit(2) stopped. When read, its content is 0.
—
(b3) When read, the content is 0.
Active edge judgment 0 : Active edge not received
TEDGF flag(3, 5) 1 : Active edge received RW
(end of measurement period)
Timer RA underflow flag(3, 5) 0 : No underflow
TUNDF RW
1 : Underflow
—
NOTES:
1. Refer to 14.1.6 Notes on Tim er RA.
2. When the TSTOP bit is set to 1, bits TSTART and TCSTF and registers TPRAPRE and TRA are set to the values after
a reset.
3. Bits TEDGF and TUNDF can be set to 0 by w riting 0 to these bits by a program. How ever, their value remains
unchanged w hen 1 is w ritten.
4. In pulse w idth measurement mode and pulse period measurement mode, use the MOV instruction to set the TRACR
register. If it is necessary to avoid changing the values of bits TEDGF and TUNDF, w rite 1 to them.
5. Set to 0 in timer mode, pulse output mode, and event counter mode.
Timer RA I/O Control Register

b7 b6 b5 b4 b3 b2 b1 b0

TRAIOC 0101h 00h
TRAIO polarity sw itch bit Function varies depending on operating mode.
TEDGSEL RW
TRAIO output control bit

TOPCR RW
TRAO output enable bit

TOENA RW
_____
INT1/TRAIO select bit
TIOSEL RW
TIPF0 TRAIO input filter select bits

RW
TIPF1
—
Figure 14.2 Registers TRACR and TRAIOC
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Timer RA Mode Register(1)

b7 b6 b5 b4 b3 b2 b1 b0

TRAMR 0102h 00h
Timer RA operating mode b2 b1 b0
TMOD0 select bits 0 0 0 : Timer mode RW
0 0 1 : Pulse output mode
0 1 0 : Event counter mode
TMOD1 0 1 1 : Pulse w idth measurement mode RW
www.DataSheet4U.com 1 0 0 : Pulse period measurement mode
101:
1 1 0 : Do not set.
TMOD2 RW
111:

—
Timer RA count source b6 b5 b4
TCK0 select bits 0 0 0 : f1 RW
0 0 1 : f8
0 1 0 : fOCO
TCK1 0 1 1 : f2 RW
1 0 0 : fC32
101:
1 1 0 : Do not set.
TCK2 RW
111:
Timer RA count source 0 : Provides count source

TCKCUT RW
cutoff bit 1 : Cuts off count source
NOTE:
1. When both the TSTART and TCSTF bits in the TRACR register are set to 0 (count stops), rew rite this register.
Timer RA Prescaler Register

b7 b0

TRAPRE 0103h FFh(1)
Mode Function Setting Range RW
Timer mode Counts an internal count source 00h to FFh RW
Pulse output mode Counts an internal count source 00h to FFh RW
Event counter mode Counts an external count source 00h to FFh RW
Pulse w idth Counts internal count source
00h to FFh RW
measurement mode
Pulse period
00h to FFh RW
measurement mode
NOTE:
1. When the TSTOP bit in the TRACR register is set to 1, the TRAPRE register is set to FFh.
Timer RA Register
b7 b0

TRA 0104h FFh(1)
Counts on underflow of timer RA prescaler
All modes 00h to FFh RW
register
NOTE:
1. When the TSTOP bit in the TRACR register is set to 1, the TRA register is set to FFh.
Figure 14.3 Registers TRAMR, TRAPRE, and TRA
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14.1.1 Timer Mode

In this mode, the timer counts an internally generated count source (refer to Table 14.2 Timer Mode
Specifications).
Figure 14.4 shows the TRAIOC Register in Timer Mode.
Table 14.2 Timer Mode Specifications

Item Specification
Count sources f1, f2, f8, fOCO, fC32
Count operations • Decrement
• When the timer underflows, the contents of the reload register are reloaded
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and the count is continued.
Divide ratio 1/(n+1)(m+1)
n: Value set in TRAPRE register, m: Value set in TRA register
Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register.
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
Interrupt request When timer RA underflows [timer RA interrupt].
generation timing
INT1/TRAIO pin Programmable I/O port, or INT1 interrupt input
function
TRAO pin function Programmable I/O port
Read from timer The count value can be read by reading registers TRA and TRAPRE.
Write to timer • When registers TRAPRE and TRA are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 14.1.1.1 Timer Write
Control during Count Operation).

b7 b6 b5 b4 b3 b2 b1 b0

TRAIOC 0101h 00h
TRAIO polarity sw itch bit Set to 0 in timer mode.
TEDGSEL RW
TRAIO output control bit

TOPCR RW

TOENA RW
_____ _____
INT1/TRAIO select bit 0 : INT1/TRAIO pin (P1_7)
TIOSEL _____ RW
1 : INT1/TRAIO pin (P1_5)
TIPF0 TRAIO input filter select bits Set to 0 in timer mode.
RW
TIPF1
—
Figure 14.4 TRAIOC Register in Timer Mode
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14.1.1.1 Timer Write Control during Count Operation

Timer RA has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each
consist of a reload register and a counter. When writing to the prescaler or timer, values are written to both the
reload register and counter.
However, values are transferred from the reload register to the counter of the prescaler in synchronization with
the count source. In addition, values are transferred from the reload register to the counter of the timer in
synchronization with prescaler underflows. Therefore, if the prescaler or timer is written to when count
operation is in progress, the counter value is not updated immediately after the WRITE instruction is executed.
Figure 14.5 shows an Operating Example of Timer RA when Counter Value is Rewritten during Count
Operation.
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Set 01h to the TRAPRE register and 25h to

the TRA register by a program.
Count source
After writing, the reload register is

written to at the first count source.
Reloads register of Previous value New value (01h)
timer RA prescaler
Reload at
second count Reload at
source underflow
Counter of 06h 05h 04h 01h 00h 01h 00h 01h 00h 01h 00h
timer RA prescaler
written to at the first underflow.
Reloads register of
timer RA Previous value New value (25h)
Reload at the second underflow
Counter of timer RA 03h 02h 25h 24h
IR bit in TRAIC
register 0
The IR bit remains unchanged until underflow is
generated by a new value.

Both bits TSTART and TCSTF in the TRACR register are set to 1 (During count).
Figure 14.5 Operating Example of Timer RA when Counter Value is Rewritten during Count
Operation
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14.1.2 Pulse Output Mode

In pulse output mode, the internally generated count source is counted, and a pulse with inverted polarity is
output from the TRAIO pin each time the timer underflows (refer to Table 14.3 Pulse Output Mode
Specifications).
Figure 14.6 shows the TRAIOC Register in Pulse Output Mode.
Table 14.3 Pulse Output Mode Specifications

Item Specification
• When the timer underflows, the contents in the reload register is reloaded and
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the count is continued.
n: Value set in TRAPRE register, m: Value set in TRA register
Interrupt request When timer RA underflows [timer RA interrupt].
generation timing
INT1/TRAIO pin Pulse output, programmable output port, or INT1 interrupt(1)
function
TRAO pin function Programmable I/O port or inverted output of TRAIO(1)
Write to timer • When registers TRAPRE and TRA are written while the count is stopped, values
are written to both the reload register and counter.
written to the reload register and counter (refer to 14.1.1.1 Timer Write Control
during Count Operation).
Select functions • TRAIO output polarity switch function
The TEDGSEL bit in the TRAIOC register selects the level at the start of pulse
output.(1)
• TRAO output function
Pulses inverted from the TRAIO output polarity can be output from the TRAO
pin (selectable by the TOENA bit in the TRAIOC register).
• Pulse output stop function
Output from the TRAIO pin is stopped by the TOPCR bit in the TRAIOC
register.
• INT1/TRAIO pin select function
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
NOTE:
1. The level of the output pulse becomes the level when the pulse output starts when the TRAMR
register is written to.
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b7 b6 b5 b4 b3 b2 b1 b0

TRAIOC 0101h 00h
TRAIO polarity sw itch bit 0 : TRAIO output starts at “H”
TEDGSEL RW
1 : TRAIO output starts at “L”
TRAIO output control bit 0 : TRAIO output
TOPCR RW
1 : Port P1_7 or P1_5
www.DataSheet4U.com TRAO output enable bit 0 : Port P3_0
TOENA RW
1 : TRAO output (inverted TRAIO output from P3_0)
_____ _____
TIOSEL _____ RW
TIPF0 TRAIO input filter select bits Set to 0 in pulse output mode. RW
TIPF1 RW
—
Figure 14.6 TRAIOC Register in Pulse Output Mode
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14.1.3 Event Counter Mode

In event counter mode, external signal inputs to the INT1/TRAIO pin are counted (refer to Table 14.4 Event
Counter Mode Specifications).
Figure 14.7 shows the TRAIOC Register in Event Counter Mode.
Table 14.4 Event Counter Mode Specifications

Item Specification
Count source External signal which is input to TRAIO pin (active edge selectable by a program)
• When the timer underflows, the contents of the reload register are reloaded and
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the count is continued.
n: setting value of TRAPRE register, m: setting value of TRA register
Interrupt request • When timer RA underflows [timer RA interrupt].
generation timing
INT1/TRAIO pin Count source input (INT1 interrupt input)
function
TRAO pin function Programmable I/O port or pulse output(1)
Write to timer • When registers TRAPRE and TRA are written while the count is stopped, values
are written to both the reload register and counter.
written to the reload register and counter (refer to 14.1.1.1 Timer Write Control
during Count Operation).
Select functions • NT1 input polarity switch function
The TEDGSEL bit in the TRAIOC register selects the active edge of the count
source.
• Count source input pin select function
• Pulse output function
Pulses of inverted polarity can be output from the TRAO pin each time the timer
underflows (selectable by the TOENA bit in the TRAIOC register).(1)
• Digital filter function
Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital filter
and select the sampling frequency.
NOTE:
1. The level of the output pulse becomes the level when the pulse output starts when the TRAMR
register is written to.
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b7 b6 b5 b4 b3 b2 b1 b0

TRAIOC 0101h 00h
TRAIO polarity sw itch bit 0 : Starts counting at rising edge of the TRAIO
input or TRAIO starts output at “L”
TEDGSEL RW
1 : Starts counting at falling edge of the TRAIO
input or TRAIO starts output at “H”
www.DataSheet4U.com TRAIO output control bit Set to 0 in event counter mode.
TOPCR RW
TRAO output enable bit 0 : Port P3_0

TOENA RW
1 : TRAO output
_____ _____
TIOSEL _____ RW
TRAIO input filter select b5 b4
TIPF0 bits (1) 0 0 : No filter
1 0 : Filter w ith f8 sampling RW
TIPF1 1 1 : Filter w ith f32 sampling

—
NOTE:
1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined.
Figure 14.7 TRAIOC Register in Event Counter Mode
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14.1.4 Pulse Width Measurement Mode

In pulse width measurement mode, the pulse width of an external signal input to the INT1/TRAIO pin is
measured (refer to Table 14.5 Pulse Width Measurement Mode Specifications).
Figure 14.8 shows the TRAIOC Register in Pulse Width Measurement Mode and Figure 14.9 shows an
Operating Example of Pulse Width Measurement Mode.
Table 14.5 Pulse Width Measurement Mode Specifications

Item Specification
• Continuously counts the selected signal only when measurement pulse is “H”
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level, or conversely only “L” level.
• When the timer underflows, the contents of the reload register are reloaded
and the count is continued.
Interrupt request • When timer RA underflows [timer RA interrupt].
generation timing • Rising or falling of the TRAIO input (end of measurement period) [timer RA
interrupt]
INT1/TRAIO pin function Measured pulse input (INT1 interrupt input)
Select functions • Measurement level select
The TEDGSEL bit in the TRAIOC register selects the “H” or “L” level period.
• Measured pulse input pin select function
Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital
filter and select the sampling frequency.
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b7 b6 b5 b4 b3 b2 b1 b0

TRAIOC 0101h 00h
TRAIO polarity sw itch bit 0 : TRAIO input starts at “L”
TEDGSEL RW
1 : TRAIO input starts at “H”
TRAIO output control bit Set to 0 in pulse w idth measurement mode.
TOPCR RW
www.DataSheet4U.com TRAO output enable bit

TOENA RW
_____ _____
TIOSEL _____ RW

—
NOTE:
Figure 14.8 TRAIOC Register in Pulse Width Measurement Mode
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n = high level: the contents of TRA register, low level: the contents of TRAPRE register
FFFFh
Count start Underflow
n
Content of counter (hex)
Count stop
Count stop
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Count start Count start

0000h
Period
Set to 1 by program
TSTART bit in 1
TRACR register 0
Measured pulse 1
(TRAIO pin input) 0
Set to 0 when interrupt request is acknowledged, or set by program
IR bit in TRAIC 1
register 0
Set to 0 by program
TEDGF bit in 1
TRACR register 0
Set to 0 by program
TUNDF bit in 1
TRACR register 0

• “H” level width of measured pulse is measured. (TEDGSEL = 1)
• TRAPRE = FFh
Figure 14.9 Operating Example of Pulse Width Measurement Mode
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14.1.5 Pulse Period Measurement Mode

In pulse period measurement mode, the pulse period of an external signal input to the INT1/TRAIO pin is
measured (refer to Table 14.6 Pulse Period Measurement Mode Specifications).
Figure 14.10 shows the TRAIOC Register in Pulse Period Measurement Mode and Figure 14.11 shows an
Operating Example of Pulse Period Measurement Mode.
Table 14.6 Pulse Period Measurement Mode Specifications

Item Specification
• After the active edge of the measured pulse is input, the contents of the read-
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out buffer are retained at the first underflow of timer RA prescaler. Then timer
RA reloads the contents in the reload register at the second underflow of
timer RA prescaler and continues counting.
Count stop conditions • 0 (count stops) is written to TSTART bit in the TRACR register.
Interrupt request • When timer RA underflows or reloads [timer RA interrupt].
generation timing • Rising or falling of the TRAIO input (end of measurement period) [timer RA
interrupt]
INT1/TRAIO pin function Measured pulse input(1) (INT1 interrupt input)
Select functions • Measurement period select
The TEDGSEL bit in the TRAIOC register selects the measurement period of
the input pulse.
• Measured pulse input pin select function
Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital
filter and select the sampling frequency.
NOTE:
1. Input a pulse with a period longer than twice the timer RA prescaler period. Input a pulse with a
longer “H” and “L” width than the timer RA prescaler period. If a pulse with a shorter period is input to
the TRAIO pin, the input may be ignored.
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b7 b6 b5 b4 b3 b2 b1 b0

TRAIOC 0101h 00h
TRAIO polarity sw itch bit 0 : Measures measurement pulse from one
rising edge to next rising edge
TEDGSEL 1 : Measures measurement pulse from one RW
falling edge to next falling edge
www.DataSheet4U.com TRAIO output control bit Set to 0 in pulse period measurement mode.
TOPCR RW

TOENA RW
_____ _____
TIOSEL _____ RW

—
NOTE:
Figure 14.10 TRAIOC Register in Pulse Period Measurement Mode
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Underflow signal of
timer RA prescaler
Set to 1 by program
TSTART bit in 1
TRACR register 0
Starts counting
1
Measurement pulse
www.DataSheet4U.com (TRAIO pin input) 0
TRA reloads TRA reloads
Contents of TRA 0Fh 0Eh 0Dh 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 0Fh 0Eh 0Dh 01h 00h 0Fh 0Eh
Underflow
Retained Retained
Contents of read-out
0Fh 0Eh 0Dh 0Bh 0Ah 09h 0Dh 01h 00h 0Fh 0Eh
buffer(1)
TRA read(3)
(Note 2) (Note 2)
TEDGF bit in 1
TRACR register 0
Set to 0 by program (Note 4)

(Note 6)
TUNDF bit in 1
TRACR register 0
Set to 0 by program (Note 5)
IR bit in TRAIC 1
register 0
Set to 0 when interrupt request is acknowledged, or set by program
Conditions: The period from one rising edge to the next rising edge of the measured pulse is measured (TEDGSEL = 0) with
the default value of the TRA register as 0Fh.
NOTES:
1. The contents of the read-out buffer can be read by reading the TRA register in pulse period measurement mode.
2. After an active edge of the measured pulse is input, the TEDGF bit in the TRACR register is set to 1 (active edge found) when the timer
RA prescaler underflows for the second time.
3. The TRA register should be read before the next active edge is input after the TEDGF bit is set to 1 (active edge found).
The contents in the read-out buffer are retained until the TRA register is read. If the TRA register is not read before the next active edge
is input, the measured result of the previous period is retained.
4. To set to 0 by a program, use a MOV instruction to write 0 to the TEDGF bit in the TRACR register. At the same time, write 1 to the
TUNDF bit in the TRACR register.
5. To set to 0 by a program, use a MOV instruction to write 0 to the TUNDF bit. At the same time, write 1 to the TEDGF bit.
6. Bits TUNDF and TEDGF are both set to 1 if timer RA underflows and reloads on an active edge simultaneously.
Figure 14.11 Operating Example of Pulse Period Measurement Mode
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14.1.6 Notes on Timer RA

• Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the
count starts.
• Even if the prescaler and timer RA are read out in 16-bit units, these registers are read 1 byte at a time by
the MCU. Consequently, the timer value may be updated during the period when these two registers are
being read.
• In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by
writing 0 to these bits by a program. However, these bits remain unchanged if 1 is written. When using the
READ-MODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0
although these bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or
TUNDF bit which is not supposed to be set to 0 with the MOV instruction.
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• When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and
TUNDF are undefined. Write 0 to bits TEDGF and TUNDF before the count starts.
• The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts.
• When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler
immediately after the count starts, then set the TEDGF bit to 0.
• The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1
(count starts) while the count is stopped.
During this time, do not access registers associated with timer RA(1) other than the TCSTF bit. Timer RA
starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (during count).
The TCSTF bit remains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0.
During this time, do not access registers associated with timer RA(1) other than the TCSTF bit.
NOTE:
1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA.
• When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow
three or more cycles of the count source clock for each write interval.
• When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three
or more cycles of the prescaler underflow for each write interval.
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14.2 Timer RB
Timer RB is an 8-bit timer with an 8-bit prescaler.
The prescaler and timer each consist of a reload register and counter (refer to Tables 14.7 to 14.10 the
Specifications of Each Mode).
Timer RB has timer RB primary and timer RB secondary as reload registers.
The count source for timer RB is the operating clock that regulates the timing of timer operations such as counting
and reloading.
Figure 14.12 shows a Block Diagram of Timer RB. Figures 14.13 to 14.15 show the registers associated with timer
RB.
Timer RB has four operation modes listed as follows:

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• Timer mode: The timer counts an internal count source (peripheral
function clock or timer RA underflows).
• Programmable waveform generation mode: The timer outputs pulses of a given width successively.
• Programmable one-shot generation mode: The timer outputs a one-shot pulse.
• Programmable wait one-shot generation mode: The timer outputs a delayed one-shot pulse.
Data bus
TRBSC TRBPR
register register
Reload Reload Reload
register register register
TCK1 to TCK0 bits TCKCUT bit
f1 = 00b
= 01b Timer RB interrupt
f8 Counter Counter (timer RB)
Timer RA underflow = 10b
TRBPRE register (Timer)
f2 = 11b (prescaler)
TMOD1 to TMOD0 bits
= 10b or 11b
TSTART bit
TOSSTF bit
INT0 interrupt
Input polarity
INT0 pin Digital filter selected to be one Polarity
edge or both edges select
INT0PL bit
INOSEG bit INOSTG bit
TMOD1 to TMOD0 bits INT0EN bit
= 01b, 10b, 11b TOPL = 1
TOCNT = 0 Q
Toggle flip-flop CK
TRBO pin Q CLR
P3_1 bit in P3 register TOPL = 0
TOCNT = 1 TCSTF bit
TMOD1 to TMOD0 bits
TSTART, TCSTF: Bit in TRBCR register = 01b, 10b, 11b
TOSSTF: Bit in TRBOCR register
TOPL, TOCNT, INOSTG, INOSEG: Bits in TRBIOC register
TMOD1 to TMOD0, TCK1 to TCK0, TCKCUT: Bits in TRBMR register
Figure 14.12 Block Diagram of Timer RB
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Timer RB Control Register

b7 b6 b5 b4 b3 b2 b1 b0

TRBCR 0108h 00h
Timer RB count start bit(1) 0 : Count stops
TSTART RW
1 : Count starts
Timer RB count status flag(1) 0 : Count stops
TCSTF RO
1 : During count(3)
www.DataSheet4U.com Timer RB count forcible stop When this bit is set to 1, the count is forcibly
TSTOP RW
bit(1, 2) stopped. When read, its content is 0.
—
NOTES:
1. Refer to 14.2.5 Notes on Tim er RB.
2. When the TSTOP bit is set to 1, registers TRBPRE, TRBSC, TRBPR, and bits TSTART and TCSTF, and the TOSSTF bit
in the TRBOCR register are set to values after a reset.
3. Indicates that count operation is in progress in timer mode or programmable w aveform mode. In programmable one-
shot generation mode or programmable w ait one-shot generation mode, indicates that a one-shot pulse trigger has
been acknow ledged.
Timer RB One-Shot Control Register(2)

b7 b6 b5 b4 b3 b2 b1 b0

TRBOCR 0109h 00h
Timer RB one-shot start bit When this bit is set to 1, one-shot trigger
TOSST RW
generated. When read, its content is 0.
Timer RB one-shot stop bit When this bit is set to 1, counting of one-shot
TOSSP pulses (including programmable w ait one-shot RW
pulses) stops. When read, its content is 0.
Timer RB one-shot status 0 : One-shot stopped
TOSSTF RO
flag(1) 1 : One-shot operating (Including w ait period)
—
NOTES:
1. When 1 is set to the TSTOP bit in the TRBCR register, the TOSSTF bit is set to 0.
2. This register is enabled w hen bits TMOD1 to TMOD0 in the TRBMR register is set to 10b (programmable one-shot
generation mode) or 11b (programmable w ait one-shot generation mode).
Figure 14.13 Registers TRBCR and TRBOCR
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Timer RB I/O Control Register

b7 b6 b5 b4 b3 b2 b1 b0

TRBIOC 010Ah 00h
Timer RB output level select Function varies depending on operating mode.
TOPL RW
bit
Timer RB output sw itch bit
TOCNT RW
www.DataSheet4U.com One-shot trigger control bit

INOSTG RW
One-shot trigger polarity

INOSEG RW
select bit
—
Timer RB Mode Register

b7 b6 b5 b4 b3 b2 b1 b0

TRBMR 010Bh 00h
Timer RB operating mode b1 b0
TMOD0 select bits (1) 0 0 : Timer mode RW
0 1 : Programmable w aveform generation mode
1 0 : Programmable one-shot generation mode
TMOD1 1 1 : Programmable w ait one-shot generation mode RW

—
Timer RB w rite control bit(2) 0 : Write to reload register and counter
TWRC RW
1 : Write to reload register only
Timer RB count source b5 b4
TCK0 select bits (1) 0 0 : f1 RW
0 1 : f8
1 0 : Timer RA underflow
TCK1 1 1 : f2 RW

—
Timer RB count source 0 : Provides count source
TCKCUT RW
cutoff bit(1) 1 : Cuts off count source
NOTES:
1. Change bits TMOD1 and TMOD0; TCK1 and TCK0; and TCKCUT w hen both the TSTART and TCSTF bits in the TRBCR
register set to 0 (count stops).
2. The TWRC bit can be set to either 0 or 1 in timer mode. In programmable w aveform generation mode, programmable
one-shot generation mode, or programmable w ait one-shot generation mode, the TWRC bit must be set to 1 (w rite to
reload register only).
Figure 14.14 Registers TRBIOC and TRBMR
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Timer RB Prescaler Register(1)

b7 b0

TRBPRE 010Ch FFh
Counts an internal count source or timer RA 00h to FFh
Timer mode RW
underflow s
Programmable w aveform Counts an internal count source or timer RA 00h to FFh
RW
generation mode underflow s
Programmable one-shot Counts an internal count source or timer RA 00h to FFh
www.DataSheet4U.com RW
Programmable w ait one-shot Counts an internal count source or timer RA 00h to FFh
RW
NOTE:
1. When the TSTOP bit in the TRBCR register is set to 1, the TRBPRE register is set to FFh.
Timer RB Secondary Register(3, 4)

b7 b0

TRBSC 010Dh FFh
Disabled 00h to FFh
Timer mode —
Programmable w aveform Counts timer RB prescaler underflow s (1) 00h to FFh

WO(2)
generation mode
Programmable one-shot Disabled 00h to FFh
—
generation mode
Programmable w ait one-shot Counts timer RB prescaler underflow s 00h to FFh
WO(2)
generation mode (one-shot w idth is counted)
NOTES:
1. The values of registers TRBPR and TRBSC are reloaded to the counter alternately and counted.
2. The count value can be read out by reading the TRBPR register even w hen the secondary period is being counted.
3. When the TSTOP bit in the TRBCR register is set to 1, the TRBSC register is set to FFh.
4. To w rite to the TRBSC register, perform the follow ing steps.
(1) Write the value to the TRBSC register.
(2) Write the value to the TRBPR register. (If the value does not change, w rite the same value second time.)
Timer RB Primary Register(2)

b7 b0

TRBPR 010Eh FFh
Counts timer RB prescaler underflow s 00h to FFh
Timer mode RW
Programmable w aveform Counts timer RB prescaler underflow s (1) 00h to FFh

RW
generation mode
Programmable one-shot Counts timer RB prescaler underflow s 00h to FFh
RW
generation mode (one-shot w idth is counted)
Programmable w ait one-shot Counts timer RB prescaler underflow s 00h to FFh
RW
generation mode (w ait period w idth is counted)
NOTES:
1. The values of registers TRBPR and TRBSC are reloaded to the counter alternately and counted.
2. When the TSTOP bit in the TRBCR register is set to 1, the TRBPR register is set to FFh.
Figure 14.15 Registers TRBPRE, TRBSC, and TRBPR
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14.2.1 Timer Mode

In timer mode, a count source which is internally generated or timer RA underflows are counted (refer to Table
14.7 Timer Mode Specifications). Registers TRBOCR and TRBSC are not used in timer mode.
Figure 14.16 shows the TRBIOC Register in Timer Mode.
Table 14.7 Timer Mode Specifications

Item Specification
Count sources f1, f2, f8, timer RA underflow
• When the timer underflows, it reloads the reload register contents before the
www.DataSheet4U.com count continues (when timer RB underflows, the contents of timer RB primary
reload register is reloaded).
n: setting value in TRBPRE register, m: setting value in TRBPR register
Count start condition 1 (count starts) is written to the TSTART bit in the TRBCR register.
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRBCR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRBCR register.
Interrupt request When timer RB underflows [timer RB interrupt].
generation timing
TRBO pin function Programmable I/O port
INT0 pin function Programmable I/O port or INT0 interrupt input
Read from timer The count value can be read out by reading registers TRBPR and TRBPRE.
Write to timer • When registers TRBPRE and TRBPR are written while the count is stopped,
• When registers TRBPRE and TRBPR are written to while count operation is in
progress:
If the TWRC bit in the TRBMR register is set to 0, the value is written to both
the reload register and the counter.
If the TWRC bit is set to 1, the value is written to the reload register only.
(Refer to 14.2.1.1 Timer Write Control during Count Operation.)

b7 b6 b5 b4 b3 b2 b1 b0

TRBIOC 010Ah 00h
Timer RB output level select Set to 0 in timer mode.
TOPL RW
bit
Timer RB output sw itch bit
TOCNT RW
One-shot trigger control bit

INOSTG RW

INOSEG RW
select bit
—
Figure 14.16 TRBIOC Register in Timer Mode
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14.2.1.1 Timer Write Control during Count Operation

Timer RB has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each
consist of a reload register and a counter. In timer mode, the TWRC bit in the TRBMR register can be used to
select whether writing to the prescaler or timer during count operation is performed to both the reload register
and counter or only to the reload register.
However, values are transferred from the reload register to the counter of the prescaler in synchronization with
the count source. In addition, values are transferred from the reload register to the counter of the timer in
synchronization with prescaler underflows. Therefore, even if the TWRC bit is set for writing to both the reload
register and counter, the counter value is not updated immediately after the WRITE instruction is executed. In
addition, if the TWRC bit is set for writing to the reload register only, the synchronization of the writing will be
shifted if the prescaler value changes. Figure 14.17 shows an Operating Example of Timer RB when Counter
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Value is Rewritten during Count Operation.
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When the TWRC bit is set to 0 (write to reload register and counter)
Set 01h to the TRBPRE register and 25h to

the TRBPR register by a program.
Count source

written with the first count source.

timer RB prescaler
Reload with Reload on
www.DataSheet4U.com the second underflow
count source
Counter of 06h 05h 04h 01h 00h 01h 00h 01h 00h 01h 00h
timer RB prescaler
written on the first underflow.
Reloads register of
timer RB Previous value New value (25h)
Reload on the second

underflow
Counter of timer RB 03h 02h 25h 24h
IR bit in TRBIC
register 0
The IR bit remains unchanged until underflow

is generated by a new value.
When the TWRC bit is set to 1 (write to reload register only)
Set 01h to the TRBPRE register and 25h to

the TRBPR register by a program.
Count source

written with the first count source.

timer RB prescaler
Reload on
underflow
Counter of 06h 05h 04h 03h 02h 01h 00h 01h 00h 01h 00h 01h 00h 01h
timer RB prescaler
written on the first underflow.
Reloads register of
timer RB Previous value New value (25h)
Reload on
underflow
Counter of timer RB 03h 02h 01h 00h 25h
IR bit in TRBIC
register 0
Only the prescaler values are updated,
extending the duration until timer RB underflow.

Both bits TSTART and TCSTF in the TRBCR register are set to 1 (During count).
Figure 14.17 Operating Example of Timer RB when Counter Value is Rewritten during Count
Operation
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14.2.2 Programmable Waveform Generation Mode

In programmable waveform generation mode, the signal output from the TRBO pin is inverted each time the
counter underflows, while the values in registers TRBPR and TRBSC are counted alternately (refer to Table
14.8 Programmable Waveform Generation Mode Specifications). Counting starts by counting the setting
value in the TRBPR register. The TRBOCR register is unused in this mode.
Figure 14.18 shows the TRBIOC Register in Programmable Waveform Generation Mode. Figure 14.19 shows
an Operating Example of Timer RB in Programmable Waveform Generation Mode.
Table 14.8 Programmable Waveform Generation Mode Specifications

Item Specification
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• When the timer underflows, it reloads the contents of the primary reload and
secondary reload registers alternately before the count continues.
Width and period of Primary period: (n+1)(m+1)/fi
output waveform Secondary period: (n+1)(p+1)/fi
Period: (n+1){(m+1)+(p+1)}/fi
fi: Count source frequency
n: Value set in TRBPRE register
m: Value set in TRBPR register
p: Value set in TRBSC register
Count start condition 1 (count starts) is written to the TSTART bit in the TRBCR register.
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRBCR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRBCR register.
Interrupt request In half a cycle of the count source, after timer RB underflows during the
generation timing secondary period (at the same time as the TRBO output change) [timer RB
interrupt]
TRBO pin function Programmable output port or pulse output
Read from timer The count value can be read out by reading registers TRBPR and TRBPRE(1).
Write to timer • When registers TRBPRE, TRBSC, and TRBPR are written while the count is
stopped, values are written to both the reload register and counter.
• When registers TRBPRE, TRBSC, and TRBPR are written to during count
operation, values are written to the reload registers only.(2)
Select functions • Output level select function
The TOPL bit in the TRBIOC register selects the output level during primary and
secondary periods.
• TRBO pin output switch function
Timer RB pulse output or P3_1 latch output is selected by the TOCNT bit in the
TRBIOC register.(3)
NOTES:
1. Even when counting the secondary period, the TRBPR register may be read.
2. The set values are reflected in the waveform output beginning with the following primary period after
writing to the TRBPR register.
3. The value written to the TOCNT bit is enabled by the following.
• When count starts.
• When a timer RB interrupt request is generated.
The contents after the TOCNT bit is changed are reflected from the output of the following
primary period.
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b7 b6 b5 b4 b3 b2 b1 b0

TRBIOC 010Ah 00h
Timer RB output level select 0 : Outputs “H” for primary period
bit Outputs “L” for secondary period
Outputs “L” w hen the timer is stopped
TOPL 1 : Outputs “L” for primary period RW
Outputs “H” for secondary period
www.DataSheet4U.com Outputs “H” w hen the timer is stopped
Timer RB output sw itch bit 0 : Outputs timer RB w aveform
TOCNT RW
1 : Outputs value in P3_1 port latch
One-shot trigger control bit Set to 0 in programmable w aveform generation
INOSTG RW
mode.
INOSEG RW
select bit
—
Figure 14.18 TRBIOC Register in Programmable Waveform Generation Mode
Set to 1 by program
TSTART bit in TRBCR 1

register 0
Count source
Timer RB prescaler
underflow signal
Timer RB secondary reloads Timer RB primary reloads
Counter of timer RB 01h 00h 02h 01h 00h 01h 00h 02h
Set to 0 when interrupt

request is acknowledged,
or set by program.
IR bit in TRBIC 1
register 0
Set to 0 by program
TOPL bit in TRBIO 1

register 0
Waveform
output starts Waveform output inverted Waveform output starts
1
TRBO pin output
0
Primary period Secondary period Primary period
Initial output is the same level
as during secondary period.

TRBPRE = 01h, TRBPR = 01h, TRBSC = 02h
TRBIOC register TOCNT = 0 (timer RB waveform is output from the TRBO pin)
Figure 14.19 Operating Example of Timer RB in Programmable Waveform Generation Mode
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14.2.3 Programmable One-shot Generation Mode

In programmable one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program or an
external trigger input (input to the INT0 pin) (refer to Table 14.9 Programmable One-Shot Generation Mode
Specifications). When a trigger is generated, the timer starts operating from the point only once for a given
period equal to the set value in the TRBPR register. The TRBSC register is not used in this mode.
Figure 14.20 shows the TRBIOC Register in Programmable One-Shot Generation Mode. Figure 14.21 shows
an Operating Example of Programmable One-Shot Generation Mode.
Table 14.9 Programmable One-Shot Generation Mode Specifications

Item Specification
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Count operations • Decrement the setting value in the TRBPR register
• When the timer underflows, it reloads the contents of the reload register before
the count completes and the TOSSTF bit is set to 0 (one-shot stops).
• When the count stops, the timer reloads the contents of the reload register
before it stops.
One-shot pulse (n+1)(m+1)/fi
output time fi: Count source frequency,
n: Setting value in TRBPRE register, m: Setting value in TRBPR register(2)
Count start conditions • The TSTART bit in the TRBCR register is set to 1 (count starts) and the next
trigger is generated.
• Set the TOSST bit in the TRBOCR register to 1 (one-shot starts)
• Input trigger to the INT0 pin
Count stop conditions • When reloading completes after timer RB underflows during primary period.
• When the TOSSP bit in the TRBOCR register is set to 1 (one-shot stops).
• When the TSTART bit in the TRBCR register is set to 0 (count stops).
• When the TSTOP bit in the TRBCR register is set to 1 (count forcibly stops).
Interrupt request In half a cycle of the count source, after the timer underflows (at the same time as
generation timing the TRBO output ends) [timer RB interrupt]
TRBO pin function Pulse output
INT0 pin functions • When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigger
disabled): programmable I/O port or INT0 interrupt input
• When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot trigger
enabled): external trigger (INT0 interrupt input)
Write to timer • When registers TRBPRE and TRBPR are written while the count is stopped,
• When registers TRBPRE and TRBPR are written during the count, values are
written to the reload register only (the data is transferred to the counter at the
following reload).(1)
The TOPL bit in the TRBIOC register selects the output level of the one-shot
pulse waveform.
• One-shot trigger select function
Refer to 14.2.3.1 One-Shot Trigger Selection.
NOTES:
1. The set value is reflected at the following one-shot pulse after writing to the TRBPR register.
2. Do not set both the TRBPRE and TRBPR registers to 00h.
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b7 b6 b5 b4 b3 b2 b1 b0

TRBIOC 010Ah 00h
Timer RB Output Level 0 : Outputs one-shot pulse “H”
Select Bit Outputs “L” w hen the timer is stopped
TOPL 1 : Outputs one-shot pulse “L” RW
Outputs “H” w hen the timer is stopped
www.DataSheet4U.com Timer RB Output Sw itch Bit Set to 0 in programmable one-shot generation
TOCNT RW
mode.
_____
One-Shot Trigger Control 0 : INT0 pin one-shot trigger disabled
INOSTG _____ RW
Bit(1) 1 : INT0 pin one-shot trigger enabled
One-Shot Trigger Polarity 0 : Falling edge trigger
INOSEG RW
Select Bit(1) 1 : Rising edge trigger
—
(b7-b4) When read, its content is 0.
NOTE:
1. Refer to 14.2.3.1 One-shot Trigger Selection.
Figure 14.20 TRBIOC Register in Programmable One-Shot Generation Mode
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Set to 1 by program

register 0
Set to 0 when Set to 1 by INT0 pin

Set to 1 by setting 1 to counting ends input trigger
TOSST bit in TRBOCR
TOSSTF bit in TRBOCR 1 register
register 0
www.DataSheet4U.com INT0 pin input
Count source
Timer RB prescaler
underflow signal
Count starts Timer RB primary reloads Count starts Timer RB primary reloads
Counter of timer RB 01h 00h 01h 00h 01h
Set to 0 when interrupt request is

acknowledged, or set by program.
IR bit in TRBIC 1
register 0
Set to 0 by program
TOPL bit in 1
TRBIOC register 0
Waveform output starts Waveform output ends Waveform output starts Waveform output ends
1
TRBIO pin output
0
TRBPRE = 01h, TRBPR = 01h

TRBIOC register TOPL = 0, TOCNT = 0
INOSTG = 1 (INT0 one-shot trigger enabled)
INOSEG = 1 (edge trigger at rising edge)
Figure 14.21 Operating Example of Programmable One-Shot Generation Mode
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14.2.3.1 One-Shot Trigger Selection

In programmable one-shot generation mode and programmable wait one-shot generation mode, operation starts
when a one-shot trigger is generated while the TCSTF bit in the TRBCR register is set to 1 (count starts).
A one-shot trigger can be generated by either of the following causes:
• 1 is written to the TOSST bit in the TRBOCR register by a program.
• Trigger input from the INT0 pin.
When a one-shot trigger occurs, the TOSSTF bit in the TRBOCR register is set to 1 (one-shot operation in
progress) after one or two cycles of the count source have elapsed. Then, in programmable one-shot generation
mode, count operation begins and one-shot waveform output starts. (In programmable wait one-shot generation
mode, count operation starts for the wait period.) If a one-shot trigger occurs while the TOSSTF bit is set to 1,
no retriggering occurs.
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To use trigger input from the INT0 pin, input the trigger after making the following settings:
• Set the PD4_5 bit in the PD4 register to 0 (input port).
• Select the INT0 digital filter with bits INT0F1 and INT0F0 in the INTF register.
• Select both edges or one edge with the INT0PL bit in INTEN register. If one edge is selected, further select
falling or rising edge with the INOSEG bit in TRBIOC register.
• Set the INT0EN bit in the INTEN register to 0 (enabled).
• After completing the above, set the INOSTG bit in the TRBIOC register to 1 (INT pin one-shot trigger
enabled).
Note the following points with regard to generating interrupt requests by trigger input from the INT0 pin.
• Processing to handle the interrupts is required. Refer to 12. Interrupts, for details.
• If one edge is selected, use the POL bit in the INT0IC register to select falling or rising edge. (The
INOSEG bit in the TRBIOC register does not affect INT0 interrupts).
• If a one-shot trigger occurs while the TOSSTF bit is set to 1, timer RB operation is not affected, but the
value of the IR bit in the INT0IC register changes.
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14.2.4 Programmable Wait One-Shot Generation Mode

In programmable wait one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program
or an external trigger input (input to the INT0 pin) (refer to Table 14.10 Programmable Wait One-Shot
Generation Mode Specifications). When a trigger is generated from that point, the timer outputs a pulse only
once for a given length of time equal to the setting value in the TRBSC register after waiting for a given length
of time equal to the setting value in the TRBPR register.
Figure 14.22 shows the TRBIOC Register in Programmable Wait One-Shot Generation Mode. Figure 14.23
shows an Operating Example of Programmable Wait One-Shot Generation Mode.
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Table 14.10 Programmable Wait One-Shot Generation Mode Specifications

Item Specification
Count operations • Decrement the timer RB primary setting value.
• When a count of the timer RB primary underflows, the timer reloads the
contents of timer RB secondary before the count continues.
• When a count of the timer RB secondary underflows, the timer reloads the
contents of timer RB primary before the count completes and the TOSSTF
bit is set to 0 (one-shot stops).
• When the count stops, the timer reloads the contents of the reload register
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before it stops.
Wait time (n+1)(m+1)/fi
n: Value set in the TRBPRE register, m Value set in the TRBPR register(2)
One-shot pulse output time (n+1)(p+1)/fi
n: Value set in the TRBPRE register, p: Value set in the TRBSC register
Count start conditions • The TSTART bit in the TRBCR register is set to 1 (count starts) and the
next trigger is generated.
• Set the TOSST bit in the TRBOCR register to 1 (one-shot starts).
• Input trigger to the INT0 pin
Count stop conditions • When reloading completes after timer RB underflows during secondary
period.
• When the TOSSP bit in the TRBOCR register is set to 1 (one-shot stops).
• When the TSTART bit in the TRBCR register is set to 0 (count starts).
• When the TSTOP bit in the TRBCR register is set to 1 (count forcibly
stops).
Interrupt request In half a cycle of the count source after timer RB underflows during
generation timing secondary period (complete at the same time as waveform output from the
TRBO pin) [timer RB interrupt].
TRBO pin function Pulse output
INT0 pin functions • When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot
trigger disabled): programmable I/O port or INT0 interrupt input
• When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot
trigger enabled): external trigger (INT0 interrupt input)
Write to timer • When registers TRBPRE, TRBSC, and TRBPR are written while the count
stops, values are written to both the reload register and counter.
• When registers TRBPRE, TRBSC, and TRBPR are written to during count
operation, values are written to the reload registers only.(1)
The TOPL bit in the TRBIOC register selects the output level of the one-
shot pulse waveform.
• One-shot trigger select function
Refer to 14.2.3.1 One-Shot Trigger Selection.
NOTES:
1. The set value is reflected at the following one-shot pulse after writing to registers TRBSC and
TRBPR.
2. Do not set both the TRBPRE and TRBPR registers to 00h.
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TRBIOC 010Ah 00h
Timer RB output level select 0 : Outputs one-shot pulse “H”.
bit Outputs “L” w hen the timer stops or during
w ait.
TOPL 1 : Outputs one-shot pulse “L”. RW
Outputs “H” w hen the timer stops or during
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w ait.
Timer RB output sw itch bit Set to 0 in programmable w ait one-shot generation
TOCNT RW
mode.
_____
One-shot trigger control bit(1) 0 : INT0 pin one-shot trigger disabled
INOSTG _____ RW
1 : INT0 pin one-shot trigger enabled
One-shot trigger polarity 0 : Falling edge trigger
INOSEG RW
select bit(1) 1 : Rising edge trigger
—
NOTE:
1. Refer to 14.2.3.1 One-shot Trigger Selection.
Figure 14.22 TRBIOC Register in Programmable Wait One-Shot Generation Mode
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Set to 1 by program

register 0
Set to 1 by setting 1 to TOSST bit in TRBOCR Set to 0 when

register, or INT0 pin input trigger. counting ends
TOSSTF bit in TRBOCR 1
register 0
www.DataSheet4U.com INT0 pin input
Count source
Timer RB prescaler
underflow signal
Count starts Timer RB secondary reloads Timer RB primary reloads
Counter of timer RB 01h 00h 04h 03h 02h 01h 00h 01h
Set to 0 when interrupt request is

acknowledged, or set by program.
IR bit in TRBIC 1
register 0
Set to 0 by program
TOPL bit in 1
TRBIOC register 0
Wait starts Waveform output starts Waveform output ends
1
TRBIO pin output
0
Wait One-shot pulse

(primary period) (secondary period)
TRBPRE = 01h, TRBPR = 01h, TRBSC = 04h

INOSTG = 1 (INT0 one-shot trigger enabled)
INOSEG = 1 (edge trigger at rising edge)
Figure 14.23 Operating Example of Programmable Wait One-Shot Generation Mode
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14.2.5 Notes on Timer RB

• Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the
count starts.
• Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time by the
MCU. Consequently, the timer value may be updated during the period when these two registers are being
read.
• In programmable one-shot generation mode and programmable wait one-shot generation mode, when
setting the TSTART bit in the TRBCR register to 0 (count stops) or setting the TOSSP bit in the TRBOCR
register to 1 (one-shot stops), the timer reloads the value of reload register and stops. Therefore, in
programmable one-shot generation mode and programmable wait one-shot generation mode, read the timer
count value before the timer stops.
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• The TCSTF bit remains 0 (count stops) for 1 to 2 cycles of the count source after setting the TSTART bit to
1 (count starts) while the count is stopped.
During this time, do not access registers associated with timer RB(1) other than the TCSTF bit.
The TCSTF bit remains 1 for 1 to 2 cycles of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RB counting is stopped when the TCSTF bit is set to 0.
NOTE:
1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and
TRBPR.
• If the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately.
• If 1 is written to the TOSST or TOSSP bit in the TRBOCR register, the value of the TOSSTF bit changes
after one or two cycles of the count source have elapsed. If the TOSSP bit is written to 1 during the period
between when the TOSST bit is written to 1 and when the TOSSTF bit is set to 1, the TOSSTF bit may be
set to either 0 or 1 depending on the content state. Likewise, if the TOSST bit is written to 1 during the
period between when the TOSSP bit is written to 1 and when the TOSSTF bit is set to 0, the TOSSTF bit
may be set to either 0 or 1.
14.2.5.1 Timer mode

The following workaround should be performed in timer mode.
To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following
points:
• When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
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14.2.5.2 Programmable waveform generation mode

The following three workarounds should be performed in programmable waveform generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
write interval.
(2) To change registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), synchronize
the TRBO output cycle using a timer RB interrupt, etc. This operation should be preformed only once in
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the same output cycle. Also, make sure that writing to the TRBPR register does not occur during period
A shown in Figures 14.24 and 14.25.
The following shows the detailed workaround examples.

• Workaround example (a):
As shown in Figure 14.24, write to registers TRBSC and TRBPR in the timer RB interrupt routine. These
write operations must be completed by the beginning of period A.
Period A
Count source/
prescaler
underflow signal
TRBO pin output Primary period Secondary period
IR bit in (a) Interrupt request is Ensure sufficient time

TRBIC register acknowledged
(b)
Interrupt Instruction in Set the secondary and then

Interrupt request sequence interrupt routine
is generated the primary register immediately
(a) Period between interrupt request generation and the completion of execution of an instruction. The length of time
varies depending on the instruction being executed.
The DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as
the divisor).
(b) 20 cycles. 21 cycles for address match and single-step interrupts.
Figure 14.24 Workaround Example (a) When Timer RB interrupt is Used
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• Workaround example (b):

As shown in Figure 14.25 detect the start of the primary period by the TRBO pin output level and write to
registers TRBSC and TRBPR. These write operations must be completed by the beginning of period A.
If the port register’s bit value is read after the port direction register’s bit corresponding to the TRBO pin is
set to 0 (input mode), the read value indicates the TRBO pin output value.
Period A
Count source/
prescaler
www.DataSheet4U.com underflow signal
Read value of the port register’s

bit corresponding to the TRBO pin
(when the bit in the port direction
register is set to 0)
(i) (ii) (iii)
Ensure sufficient time
The TRBO output inversion Upon detecting (i), set the secondary and
is detected at the end of the then the primary register immediately.
secondary period.
Figure 14.25 Workaround Example (b) When TRBO Pin Output Value is Read
(3) To stop the timer counting in the primary period, use the TSTOP bit in the TRBCR register. In this case,
registers TRBPRE and TRBPR are initialized and their values are set to the values after reset.
14.2.5.3 Programmable one-shot generation mode

The following two workarounds should be performed in programmable one-shot generation mode.
following points:
• When the TRBPRE register is written continuously during count operation (TCSTF bit is set to 1), allow
three or more cycles of the count source for each write interval.
• When the TRBPR register is written continuously during count operation (TCSTF bit is set to 1), allow
three or more cycles of the prescaler underflow for each write interval.
(2) Do not set both the TRBPRE and TRBPR registers to 00h.
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14.2.5.4 Programmable wait one-shot generation mode

The following three workarounds should be performed in programmable wait one-shot generation mode.
following points:
write interval.
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(3) Set registers TRBSC and TRBPR using the following procedure.
(a) To use “INT0 pin one-shot trigger enabled” as the count start condition
Set the TRBSC register and then the TRBPR register. At this time, after writing to the TRBPR
register, allow an interval of 0.5 or more cycles of the count source before trigger input from the
INT0 pin.
(b) To use “writing 1 to TOSST bit” as the start condition
Set the TRBSC register, the TRBPR register, and then TOSST bit. At this time, after writing to the
TRBPR register, allow an interval of 0.5 or more cycles of the count source before writing to the
TOSST bit.
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14.3 Timer RD
Timer RD has 2 16-bit timers (channels 0 and 1). Each channel has 4 I/O pins.
The operation clock of timer RD is f1 or fOCO40M. Table 14.11 lists the Timer RD Operation Clocks.
Table 14.11 Timer RD Operation Clocks

Condition Operation Clock of Timer RD
The count source is f1, f2, f4, f8, f32, or TRDCLK input f1
(bits TCK2 to TCK0 in registers TRDCR0 and TRDCR1 are set to a value from 000b
to 101b).
The count source is fOCO40M fOCO40M
(bits TCK2 to TCK0 in registers TRDCR0 and TRDCR1 are set to 110b).
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Figure 14.26 shows a Block Diagram of Timer RD. Timer RD has 5 modes:
• Timer mode
- Input capture function Transfer the counter value to a register with an external signal as the
trigger
- Output compare function Detect register value matches with a counter
(Pin output can be changed at detection)
The following 4 modes use the output compare function.

• PWM mode Output pulse of any width continuously
• Reset synchronous PWM mode Output three-phase waveforms (6) without sawtooth wave modulation
and dead time
• Complementary PWM mode Output three-phase waveforms (6) with triangular wave modulation and
dead time
• PWM3 mode Output PWM waveforms (2) with a fixed period
In the input capture function, output compare function, and PWM mode, channels 0 and 1 have the equivalent
functions, and functions or modes can be selected individually for each pin. Also, a combination of these functions
and modes can be used in 1 channel.
In reset synchronous PWM mode, complementary PWM mode, and PWM3 mode, a waveform is output with a
combination of counters and registers in channels 0 and 1.
Tables 14.12 to 14.20 list the Pin Functions of timer RD.
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Table 14.12 Pin Functions TRDIOA0/TRDCLK(P2_0)

Register TRDOER1 TRDFCR TRDIORA0
Function
Bit EA0 PWM3 STCLK CMD1, CMD0 IOA3 IOA2_IOA0
0 0 0 00b X XXXb PWM3 mode waveform output
0 1 0 00b 1 001b, 01Xb Timer mode waveform output (output compare function)
Setting
1 0 00b X 1XXb Timer mode trigger input (input capture function)(1)
value X
1 1 XXb X 000b External clock input (TRDCLK)(1)
Other than above I/O port
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NOTE:
1. Set the PD2_0 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function) and external clock
input (TRDCLK).
Table 14.13 Pin Functions TRDIOB0(P2_1)

Register TRDOER1 TRDFCR TRDPMR TRDIORA0
Function
Bit EB0 PWM3 CMD1, CMD0 PWMB0 IOB2_IOB0
0 X 1Xb X XXXb Complementary PWM mode waveform output
0 X 01b X XXXb Reset synchronous PWM mode waveform output
0 0 00b X XXXb PWM3 mode waveform output
Setting
0 1 00b 1 XXXb PWM mode waveform output
value
0 1 00b 0 001b, 01Xb Timer mode waveform output (output compare function)
X 1 00b 0 1XXb Timer mode trigger input (input capture function)(1)
NOTE:
1. Set the PD2_1 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function).
Table 14.14 Pin Functions TRDIOC0(P2_2)

Register TRDOER1 TRDFCR TRDPMR TRDIORC0
Function
Bit EC0 PWM3 CMD1, CMD0 PWMC0 IOC2_IOC0
Setting 0 1 00b 1 XXXb PWM mode waveform output

value 0 1 00b 0 001b, 01Xb Timer mode waveform output (output compare function)
NOTE:
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Table 14.15 Pin Functions TRDIOD0(P2_3)

Function
Bit ED0 PWM3 CMD1, CMD0 PWMD0 IOD2_IOD0

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NOTE:
Table 14.16 Pin Functions TRDIOA1(P2_4)

Register TRDOER1 TRDFCR TRDIORA1
Function
Bit EA1 PWM3 CMD1, CMD0 IOA2_IOA0
0 X 1Xb XXXb Complementary PWM mode waveform output
0 X 01b XXXb Reset synchronous PWM mode waveform output
Setting
0 1 00b 001b, 01Xb Timer mode waveform output (output compare function)
value
X 1 00b 1XXb Timer mode trigger input (input capture function)(1)
NOTE:
Table 14.17 Pin Functions TRDIOB1(P2_5)

Register TRDOER1 TRDFCR TRDPMR TRDIORA1
Function
Bit EB1 PWM3 CMD1, CMD0 PWMB1 IOB2_IOB0

NOTE:
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Table 14.18 Pin Functions TRDIOC1(P2_6)

Function
Bit EC1 PWM3 CMD1, CMD0 PWMC1 IOC2_IOC0

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NOTE:
Table 14.19 Pin Functions TRDIOD1(P2_7)

Function
Bit ED1 PWM3 CMD1, CMD0 PWMD1 IOD2_IOD0

NOTE:
Table 14.20 Pin Functions INT0(P4_5)

Register TRDOER2 INTEN PD4
Function
Bit PTO INT0PL INT0EN PD4_5
Setting 1 0 1 0 Pulse output forced cutoff signal input

value Other than above I/O port or INT0 interrupt input
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f1, f2, f4, f8, f32,

fOCO40M
Channel i
TRDi register
TRDGRAi register
TRDGRBi register INT0

Count source
TRDGRCi register TRDIOA0/TRDCLK
select circuit
TRDGRDi register TRDIOB0
TRDDFi register Timer RD control TRDIOC0
www.DataSheet4U.com TRDCRi register circuit TRDIOD0
TRDIORAi register TRDIOA1
TRDIORCi register TRDIOB1

TRDSRi register TRDIOC1
Data bus
TRDIERi register TRDIOD1

TRDPOCRi register
TRDSTR register Channel 0 interrupt

request
TRDMR register
Channel 1 interrupt
TRDPMR register request
TRDFCR register
A/D trigger
TRDOER1 register
TRDOER2 register
TRDOCR register
i = 0 or 1
Figure 14.26 Block Diagram of Timer RD
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14.3.1 Count Sources

The count source selection method is the same in all modes. However, in PWM3 mode, the external clock
cannot be selected.
Table 14.21 Count Source Selection

Count Source Selection
f1, f2, f4, f8, f32 The count source is selected by bits TCK2 to TCK0 in the TRDCRi register.
fOCO40M(1) The FRA00 bit in the FRA0 register is set to 1 (high-speed on-chip oscillator
frequency).
Bits TCK2 to TCK0 in the TRDCRi register is set to 110b (fOCO40M).
External
www.DataSheet4U.com signal input The STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
to TRDCLK pin Bits TCK2 to TCK0 in the TRDCRi register are set to 101b
(count source: external clock).
The valid edge is selected by bits CKEG1 to CKEG0 in the TRDCRi register.
The PD2_0 bit in the PD2 register is set to 0 (input mode).
i = 0 or 1
NOTE:
1. The count source fOCO40M can be used with VCC = 3.0 to 5.5 V.
TCK2 to TCK0
f1
= 000b
= 001b
f2
= 010b
f4
= 011b Count source
f8 TRDi register
= 100b
f32
= 110b
fOCO40M
= 101b
CKEG1 to CKEG0
STCLK = 1
Valid edge
TRDCLK/ selected
TRDIOA0
STCLK = 0
TRDIOA0 I/O or programmable I/O port
TCK2 to TCK0, CKEG1 to CKEG0: Bits in TRDCRi register

STCLK: Bit in TRDFCR register
Figure 14.27 Block Diagram of Count Source
Set the pulse width of the external clock which inputs to the TRDCLK pin to 3 cycles or above of the operation
clock of timer RD (refer to Table 14.11 Timer RD Operation Clocks).
When selecting fOCO40M for the count source, set the FRA00 bit in the FRA0 register to 1 (high-speed on-
chip oscillator on) before setting bits TCK2 to TCK0 in the TRDCRi register (i = 0 or 1) to 110b (fOCO40M).
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14.3.2 Buffer Operation

The TRDGRCi (i = 0 or 1) register can be used as the buffer register of the TRDGRAi register, and the
TRDGRDi register can be used as the buffer register of the TRDGRBi register by means of bits BFCi and BFDi
in the TRDMR register.
• TRDGRAi buffer register: TRDGRCi register
• TRDGRBi buffer register: TRDGRDi register
Buffer operation depends on the mode. Table 14.22 lists the Buffer Operation in Each Mode.
Figure 14.28 shows the Buffer Operation in Input Capture Function, and Figure 14.29 shows the Buffer
Operation in Output Compare Function.
Table 14.22 Buffer Operation in Each Mode

www.DataSheet4U.comFunction and Mode Transfer Timing Transfer Register
Input capture function Input capture signal input Transfer content in TRDGRAi
(TRDGRBi) register to buffer register
Output compare function Compare match with TRDi register Transfer content in buffer register to
PWM mode and TRDGRAi (TRDGRBi) register TRDGRAi (TRDGRBi) register
Reset synchronous PWM Compare match withTRD0 register Transfer content in buffer register to
mode and TRDGRA0 register TRDGRAi (TRDGRBi) register
Complementary PWM • Compare match with TRD0 register Transfer content in buffer register to
mode and TRDGRA0 register registers TRDGRB0, TRDGRA1, and
• TRD1 register underflow TRDGRB1
PWM3 mode Compare match with TRD0 register Transfer content in buffer register to
and TRDGRA0 register registers TRDGRA0, TRDGRB0,
TRDGRA1, and TRDGRB1
i = 0 or 1
TRDIOAi input
(input capture signal)
TRDGRCi register TRDGRAi

TRDi
(buffer) register
TRDIOAi input
TRDi register n-1 n n+1
Transfer
TRDGRAi register m n
Transfer
TRDGRCi register
m
(buffer)
i = 0 or 1
The above applies under the following conditions:

• The BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the buffer register of
the TRDGRAi register).
• Bits IOA2 to IOA0 in the TRDIORAi register are set to 100b (input capture at the falling edge).
Figure 14.28 Buffer Operation in Input Capture Function
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Compare match signal
TRDGRCi register TRDGRAi

Comparator TRDi
(buffer) register
TRDi register m-1 m m+1

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TRDGRAi register m n
Transfer
TRDGRCi register
n
(buffer)
TRDIOAi output
i = 0 or 1

• BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the buffer register of
the TRDGRAi register).
• Bits IOA2 to IOA0 in the TRDIORAi register are set to 001b (“L” output by the compare match).
Figure 14.29 Buffer Operation in Output Compare Function
Perform the following for the timer mode (input capture and output compare functions).
When using the TRDGRCi (i = 0 or 1) register as the buffer register of the TRDGRAi register
• Set the IOC3 bit in the TRDIORCi register to 1 (general register or buffer register).
• Set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi register.
When using the TRDGRDi register as the buffer register of the TRDGRBi register
• Set the IOD3 bit in the TRDIORDi register to 1 (general register or buffer register).
• Set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi register.
Bits IMFC and IMFD in the TRDSRi register are set to 1 at the input edge of the TRDIOCi pin when also using
registers TRDGRCi and TRDGRDi as the buffer register in the input capture function.
When also using registers TRDGRCi and TRDGRDi as buffer registers for the output compare function, reset
synchronous PWM mode, complementary PWM mode, and PWM3 mode, bits IMFC and IMFD in the TRDSRi
register are set to 1 by a compare match with the TRDi register.
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14.3.3 Synchronous Operation

The TRD1 register is synchronized with the TRD0 register.
• Synchronous preset
When the SYNC bit in the TRDMR register is set to 1 (synchronous operation), the data is written to both
the TRD0 and TRD1 registers after writing to the TRDi register.
• Synchronous clear
When the SYNC bit in the TRDMR register is set to 1 and bits CCLR2 to CCLR0 in the TRDCRi register
are set to 011b (synchronous clear), the TRD0 register is set to 0000h at the same time as the TRD1 register
is set to 0000h.
Also, when the SYNC bit in the TRDMR register is set to 1 and bits CCLR2 to CCLR0 in the TRDCRi
register are set to 011b (synchronous clear), the TRD1 register is set to 0000h at the same time as the TRD0
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register is set to 0000h.
TRDIOA0 input
Set to 0000h by input capture

Value in
TRD0 register n writing
n n is set
Value in
TRD1 register
n n is set
Set to 0000h with TRD0 register
• The SYNC bit in the TRDMR register is set to 1 (synchronous operation).

• Bits CCLR2 to CCLR0 in the TRDCR0 register are set to 001b (set the TRD0 register to 0000h in input capture).
Bits CCLR2 to CCLR0 in the TRDCR1 register are set to 011b (set the TRD1 register to 0000h synchronizing with
the TRD0 register).
• Bits IOA2 to IOA0 in the TRDIORA0 register are set to 100b.
• Bits CMD1 to CMD0 in the TRDFCR register are set to 00b. (Input capture at the rising edge of the TRDIOA0 input)
The PWM 3 bit in the TRDFCR register is set to 1.
Figure 14.30 Synchronous Operation
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14.3.4 Pulse Output Forced Cutoff

In the output compare function, PWM mode, reset synchronous PWM mode, complementary PWM mode, and
PWM3 mode, the TRDIOji (i = 0 or 1, j = either A, B, C, or D) output pin can be forcibly set to a programmable
I/O port by the INT0 pin input, and pulse output can be cut off.
The pins used for output in these functions or modes can function as the output pin of timer RD when the
applicable bit in the TRDOER1 register is set to 0 (enable timer RD output). When the PTO bit in the
TRDOER2 register to 1 (INT0 of pulse output forced cutoff signal input enabled), all bits in the TRDOER1
register are set to 1 (disable timer RD output, the TRDIOji output pin is used as the programmable I/O port)
after “L” is applied to the INT0 pin. The TRDIOji output pin is set to the programmable I/O port after “L” is
applied to the INT0 pin and waiting for 1 to 2 cycles of the timer RD operation clock (refer to Table 14.11
Timer RD Operation Clocks).
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Set as below when using this function:
• Set the pin status (high impedance, “L” or “H” output) to pulse output forced cutoff by registers P2 and
PD2.
• Set the INT0EN bit in the INTEN register to 1 (enable INT0 input) and the INT0PL bit to 0 (one edge).
• Set the PD4_5 bit in the PD4 register to 0 (input mode).
• Set the INT0 digital filter by bits INT0F1 to INT0F0 in the INTF register.
• Set the PTO bit in the TRDOER2 register to 1 (enable pulse output forced cutoff signal input INT0).
According to the selection of the POL bit in the INT0IC register and change of the INT0 pin input, the IR bit in
the INT0IC register is set to 1 (interrupt request). Refer to 12. Interrupts for details of interrupts.
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EA0 bit
EA0 bit
D Q
writing value
INT0 input Timer RD
S TRDIOA0
output data
PTO bit Port P2_0

output data
Port P2_0
input data
EB0 bit
EB0 bit
D Q
writing value
Timer RD
S output data
TRDIOB0
Port P2_1
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output data
Port P2_1
input data
EC0 bit
EC0 bit
D Q
writing value
Timer RD
S
output data
TRDIOC0
Port P2_2
output data
Port P2_2
input data
ED0 bit
ED0 bit writing
D Q
value
Timer RD
S TRDIOD0
output data
Port P2_3
output data
Port P2_3
input data
EA1 bit
EA1 bit writing
D Q
value
Timer RD
S TRDIOA1
output data
Port P2_4
output data
Port P2_4
input data
EB1 bit
EB1 bit writing
D Q
value
Timer RD
S TRDIOB1
output data
Port P2_5
output data
Port P2_5
input data
EC1 bit
EC1 bit
D Q
writing value
Timer RD
S TRDIOC1
output data
Port P2_6
output data
Port P2_6
input data
ED1 bit
ED1 bit
D Q
writing value
Timer RD
S TRDIOD1
output data
Port P2_7
output data
Port P2_7
input data
PTO: Bit in TRDOER2 register

EA0, EB0, EC0, ED0, EA1, EB1, EC1, ED1: Bits in TRDOER1 register
Figure 14.31 Pulse Output Forced Cutoff
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14.3.5 Input Capture Function

The input capture function measures the external signal width and period. The content of the TRDi register
(counter) is transferred to the TRDGRji register as a trigger of the TRDIOji (i = 0 or 1, j = either A, B, C, or D)
pin external signal (input capture). Since this function is enabled with a combination of the TRDIOji pin and
TRDGRji register, the input capture function, or any other mode or function, can be selected for each individual
pin.
The TRDGRA0 register can also select fOCO128 signal as input-capture trigger input.
Figure 14.32 shows a Block Diagram of Input Capture Function, Table 14.23 lists the Input Capture Function
Specifications. Figures 14.33 to 14.43 show the Registers Associated with Input Capture Function, and Figure
14.44 shows an Operating Example of Input Capture Function.
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Input capture
signal
TRDIOAi(3)
TRDGRAi
(Note 1) TRDi register
register
TRDGRCi
register
TRDIOCi
Input capture
signal
Input capture
signal
TRDIOBi
TRDGRBi
(Note 2) register
Divided fOCO128
fOCO
by 128
IOA3 = 0
Input capture
signal
TRDIOA0 IOA3 = 1
TRDGRDi
register
NOTE 3: The trigger input of the TRDGRA0 register
can select the TRDIOA0 pin input or
TRDIODi
Input capture fOCO128 signal.
signal
i = 0 or 1
NOTE 1: When the BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the buffer register of the
TRDGRAi register).
NOTE 2: When the BFDi bit in the TRDMR register is set to 1 (the TRDGRDi register is used as the buffer register of the
TRDGRBi register).
Figure 14.32 Block Diagram of Input Capture Function
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Table 14.23 Input Capture Function Specifications

Item Specification
Count sources f1, f2, f4, f8, f32, fOCO40M
External signal input to the TRDCLK pin (valid edge selected by a
program)
Count operations Increment
Count period When bits CCLR2 to CCLR0 in the TRDCRi register are set to 000b
(free-running operation).
1/fk × 65536 fk: Frequency of count source
Count
www.DataSheet4U.com start condition 1 (count starts) is written to the TSTARTi bit in the TRDSTR register.
Count stop condition 0 (count stops) is written to the TSTARTi bit in the TRDSTR register
when the CSELi bit in the TRDSTR register is set to 1.
Interrupt request generation • Input capture (valid edge of TRDIOji input or fOCO128 signal edge)
timing • TRDi register overflows
TRDIOA0 pin function Programmable I/O port, input-capture input, or TRDCLK (external clock)
input
TRDIOB0, TRDIOC0, Programmable I/O port, or input-capture input (selectable by pin)
TRDIOD0, TRDIOA1 to
TRDIOD1 pin functions
Read from timer The count value can be read by reading the TRDi register.
Write to timer • When the SYNC bit in the TRDMR register is set to 0 (channels 0 and
1 operate independently).
Data can be written to the TRDi register.
• When the SYNC bit in the TRDMR register is set to 1 (channels 0 and
1 operate synchronously).
Data can be written to both the TRD0 and TRD1 registers by writing to
the TRDi register.
Select functions • Input-capture input pin selected
Either 1 pin or multiple pins among TRDIOAi, TRDIOBi, TRDIOCi, or
TRDIODi.
• Input-capture input valid edge selected
The rising edge, falling edge, or both the rising and falling edges
• The timing when the TRDi register is set to 0000h
At overflow or input capture
• Buffer operation (Refer to 14.3.2 Buffer Operation.)
• Synchronous operation (Refer to 14.3.3 Synchronous Operation.)
• Digital filter
The TRDIOji input is sampled, and when the sampled input level
match as 3 times, the level is determined.
• Input-capture trigger selected
fOCO128 can be selected for input-capture trigger input of the
TRDGRA0 register.
i = 0 or 1, j = either A, B, C, or D
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Timer RD Start Register(1)

b7 b6 b5 b4 b3 b2 b1 b0

TRDSTR 0137h 11111100b
TRD0 count start flag 0 : Count stops
TSTART0 RW
1 : Count starts
TRD1 count start flag 0 : Count stops
TSTART1 RW
1 : Count starts
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TRD0 count operation select bit Set to 1 in the input capture function.
CSEL0 RW
TRD1 count operation select bit Set to 1 in the input capture function.
CSEL1 RW

—
NOTE:
1. Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 14.3.12.1
TRDSTR Register of Notes on Tim er RD.
Timer RD Mode Register

b7 b6 b5 b4 b3 b2 b1 b0

TRDMR 0138h 00001110b
Timer RD synchronous bit 0 : Registers TRD0 and TRD1
operate independently
SYNC 1 : Registers TRD0 and TRD1 RW
operate synchronously
—
TRDGRC0 register function select 0 : General register
BFC0 RW
bit 1 : Buffer register of TRDGRA0 register
TRDGRD0 register function select 0 : General register
BFD0 RW
bit 1 : Buffer register of TRDGRB0 register
BFC1 RW
BFD1 RW
Figure 14.33 Registers TRDSTR and TRDMR in Input Capture Function
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Timer RD PWM Mode Register

b7 b6 b5 b4 b3 b2 b1 b0

TRDPMR 0139h 10001000b
PWM mode of TRDIOB0 select bit Set to 0 (timer mode) in the input capture
PWMB0 RW
function.
PWM mode of TRDIOC0 select bit Set to 0 (timer mode) in the input capture
PWMC0 RW
function.
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PWM mode of TRDIOD0 select bit Set to 0 (timer mode) in the input capture
PWMD0 RW
function.
—
PWM mode of TRDIOB1 select bit Set to 0 (timer mode) in the input capture
PWMB1 RW
function.
PWM mode of TRDIOC1 select bit Set to 0 (timer mode) in the input capture
PWMC1 RW
function.
PWM mode of TRDIOD1 select bit Set to 0 (timer mode) in the input capture
PWMD1 RW
function.
—
Figure 14.34 TRDPMR Register in Input Capture Function
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Timer RD Function Control Register

b7 b6 b5 b4 b3 b2 b1 b0

TRDFCR 013Ah 10000000b
Combination mode select bits (1) Set to 00b (timer mode, PWM mode, or
CMD0 RW
PWM3 mode) in the input capture function.
CMD1 RW
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Normal-phase output level select bit This bit is disabled in the input capture
(in reset synchronous PWM mode or function.
OLS0 complementary PWM mode) RW
Counter-phase output level select bit This bit is disabled in the input capture
A/D trigger enable bit This bit is disabled in the input capture
ADTRG (in complementary PWM mode) function. RW
A/D trigger edge select bit This bit is disabled in the input capture
ADEG (in complementary PWM mode) function. RW
External clock input select bit 0 : External clock input disabled

STCLK RW
1 : External clock input enabled
PWM3 mode select bit(2) Set this bit to 1 (other than PWM3 mode) in
PWM3 RW
the input capture function.
NOTES:
1. Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits are set to 0 (count stops).
2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is
enabled.
Figure 14.35 TRDFCR Register in Input Capture Function
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Timer RD Digital Filter Function Select Register i (i = 0 or 1)

b7 b6 b5 b4 b3 b2 b1 b0

TRDDF0 013Eh 00h
TRDDF1 013Fh 00h
TRDIOA pin digital filter function 0 : Function is not used
DFA RW
select bit 1 : Function is used
TRDIOB pin digital filter function 0 : Function is not used
www.DataSheet4U.com DFB RW
TRDIOC pin digital filter function 0 : Function is not used
DFC RW
TRDIOD pin digital filter function 0 : Function is not used
DFD RW
—
Clock select bits for digital filter b7 b6
function 0 0 : f32
DFCK0 0 1 : f8 RW
1 0 : f1
1 1 : Count source (clock selected by
bits TCK2 to TCK0 in the
DFCK1 TRDCRi register) RW
Figure 14.36 Registers TRDDF0 to TRDDF1 in Input Capture Function
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REJ09B0244-0300
Timer RD Control Register i (i = 0 or 1)

b7 b6 b5 b4 b3 b2 b1 b0

TRDCR0 0140h 00h
TRDCR1 0150h 00h
Count source select bits b2 b1 b0
TCK0 0 0 0 : f1 RW
0 0 1 : f2
www.DataSheet4U.com 0 1 0 : f4
TCK1 0 1 1 : f8 RW
1 0 0 : f32
1 0 1 : TRDCLK input(1)
1 1 0 : fOCO40M
TCK2 RW
1 1 1 : Do not set.
External clock edge select bits (2) b4 b3
CKEG0 0 0 : Count at the rising edge RW

0 1 : Count at the falling edge
1 0 : Count at both edges
1 1 : Do not set.
CKEG1 RW
TRDi counter clear select bits b7 b6 b5

0 0 0 : Disable clear (free-running
operation)
CCLR0 0 0 1 : Clear by input capture in the RW
TRDGRAi register
0 1 0 : Clear by input capture in the
TRDGRBi register
0 1 1 : Synchronous clear (clear
simultaneously w ith other
CCLR1 RW
channel counter)(3)
1 0 0 : Do not set.
TRDGRCi register
TRDGRDi register
CCLR2 RW
1 1 1 : Do not set.
NOTES:
1. This setting is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
2. Bits CKEG1 to CKEG0 are enabled w hen bits TCK2 to TCK0 are set to 101b (TRDCLK input) and the STCLK bit in the
TRDFCR register is set to 1 (external clock input enabled).
3. This setting is enabled w hen the SYNC bit in the TRDMR register is set to 1 (registers TRD0 and TRD1 operate
synchronously).
Figure 14.37 Registers TRDCR0 to TRDCR1 in Input Capture Function
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REJ09B0244-0300
Timer RD I/O Control Register Ai (i = 0 or 1)

b7 b6 b5 b4 b3 b2 b1 b0

TRDIORA0 0141h 10001000b
TRDIORA1 0151h 10001000b
TRDGRA control bits b1 b0
0 0 : Input capture to the TRDGRAi register
IOA0 at the rising edge RW
www.DataSheet4U.com 0 1 : Input capture to the TRDGRAi register
at the falling edge
1 0 : Input capture to the TRDGRAi register
IOA1 at both edges RW
1 1 : Do not set.
TRDGRA mode select bit(1) Set to 1 (input capture) in the input capture
IOA2 RW
function.
Input capture input sw itch 0 : fOCO128 Signal
IOA3 RW
bit(3, 4) 1 : TRDIOA0 pin input
TRDGRB control bits b5 b4
0 0 : Input capture to the TRDGRBi register
IOB0 at the rising edge RW
at the falling edge
IOB1 at both edges RW
1 1 : Do not set.
TRDGRB mode select bit(2) Set to 1 (input capture) in the input capture
IOB2 RW
function.
—
NOTES:
1. To select 1 (the TRDGRCi register is used as a buffer register of the TRDGRAi register) for this bit by the BFCi bit in
the TRDMR register, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi
register.
2. To select 1 (the TRDGRDi register is used as a buffer register of the TRDGRBi register) for this bit by the BFDi bit in
the TRDMR register, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi
register.
3. The IOA3 bit is enabled in the TRDIORA0 register only. Set to the IOA3 bit in TRDIORA1 to 1.
4. The IOA3 bit is enabled w hen the IOA2 bit is set to 1 (input capture function).
Figure 14.38 Registers TRDIORA0 to TRDIORA1 in Input Capture Function
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REJ09B0244-0300
Timer RD I/O Control Register Ci (i = 0 or 1)

b7 b6 b5 b4 b3 b2 b1 b0

TRDIORC0 0142h 10001000b
TRDIORC1 0152h 10001000b
TRDGRC control bits b1 b0
0 0 : Input capture to the TRDGRCi register
IOC0 at the rising edge RW
www.DataSheet4U.com 0 1 : Input capture to the TRDGRCi register
at the falling edge
1 0 : Input capture to the TRDGRCi register
IOC1 at both edges RW
1 1 : Do not set.
TRDGRC mode select bit(1) Set to 1 (input capture) in the input capture
IOC2 RW
function.
TRDGRC register function Set to 1 (general register or buffer register) in
IOC3 RW
select bit the input capture function.
TRDGRD control bits b5 b4
0 0 : Input capture to the TRDGRDi register
IOD0 at the rising edge RW
at the falling edge
IOD1 at both edges RW
1 1 : Do not set.
TRDGRD mode select bit(2) Set to 1 (input capture) in the input capture
IOD2 RW
function.
TRDGRD register function Set to 1 (general register or buffer register) in
IOD3 RW
select bit the input capture function.
NOTES:
register.
register.
Figure 14.39 Registers TRDIORC0 to TRDIORC1 in Input Capture Function
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Timer RD Status Register i (i = 0 or 1)

b7 b6 b5 b4 b3 b2 b1 b0

TRDSR0 0143h 11100000b
TRDSR1 0153h 11000000b
Input capture/compare match [Source for setting this bit to 0]
flag A Write 0 after read(2)
[Source for setting this bit to 1]
www.DataSheet4U.com TRDSR0 register:
fOCO128 signal edge w hen the IOA3 bit in the
TRDIORA0 register is set to 0 (fOCO128 signal)
IMFA TRDIOA0 pin input edge w hen the IOA3 bit in the RW
TRDIORA0 register is set to 1 (TRDIOA0 input)(3)
TRDSR1 register:
Input edge of TRDIOA1 pin(3)

flag B Write 0 after read(2)
IMFB [Source for setting this bit to 1] RW
Input edge of TRDIOBi pin(3)
flag C Write 0 after read(2)
IMFC [Source for setting this bit to 1] RW
Input edge of TRDIOCi pin(4)
flag D Write 0 after read(2)
IMFD [Source for setting this bit to 1] RW
Input edge of TRDIODi pin(4)
Overflow flag [Source for setting this bit to 0]
Write 0 after read(2)
OVF [Source for setting this bit to 1] RW
When the TRDi register overflow s
Underflow flag(1) This bit is disabled in the input capture function.
UDF RW

—
NOTES:
1. Nothing is assigned to b5 in the TRDSR0 register. When w riting to b5, w rite 0. When reading, the content is 1.
2. The w riting results are as follow s:
• This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit.
• This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (This bit remains 1 even
if it is set to 1 from 0 after reading, and w riting 0.)
• This bit remains unchanged if 1 is w ritten to it.
3. Edge selected by bits IOj1 to IOj0 (j = A or B) in the TRDIORAi register.
4. Edge selected by bits IOk1 to IOk0 (k = C or D) in the TRDIORCi register
Including w hen the BFki bit in the TRDMR register is set to 1 (TRDGRki is used as the buffer register).
Figure 14.40 Registers TRDSR0 to TRDSR1 in Input Capture Function
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REJ09B0244-0300
Timer RD Interrupt Enable Register i (i = 0 or 1)

b7 b6 b5 b4 b3 b2 b1 b0

TRDIER0 0144h 11100000b
TRDIER1 0154h 11100000b
Input capture/compare match 0 : Disable interrupt (IMIA) by the IMFA bit
IMIEA RW
interrupt enable bit A 1 : Enable interrupt (IMIA) by the IMFA bit
Input capture/compare match 0 : Disable interrupt (IMIB) by the IMFB bit
www.DataSheet4U.com IMIEB RW
interrupt enable bit B 1 : Enable interrupt (IMIB) by the IMFB bit
Input capture/compare match 0 : Disable interrupt (IMIC) by the IMFC bit
IMIEC RW
interrupt enable bit C 1 : Enable interrupt (IMIC) by the IMFC bit
Input capture/compare match 0 : Disable interrupt (IMID) by the IMFD bit
IMIED RW
interrupt enable bit D 1 : Enable interrupt (IMID) by the IMFD bit
Overflow /underflow interrupt 0 : Disable interrupt (OVI) by the OVF bit
OVIE RW
enable bit 1 : Enable interrupt (OVI) by the OVF bit
—
Figure 14.41 Registers TRDIER0 to TRDIER1 in Input Capture Function
Timer RD Counter i (i = 0 or 1)(1)

(b15) (b8)
b7 b0 b7 b0

TRD0 0147h-0146h 0000h
TRD1 0157h-0156h 0000h
Count the count source. Count operation is incremented. 0000h to FFFFh
When an overflow occurs, the OVF bit in the TRDSRi register is set to 1. RW
NOTE:
1. Access the TRDi register in 16-bit units. Do not access it in 8-bit units.
Figure 14.42 Registers TRD0 to TRD1 in Input Capture Function
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Timer RD General Registers Ai, Bi, Ci, and Di (i = 0 or 1)(1)

(b15) (b8)
b7 b0 b7 b0
TRDGRA0 0149h-0148h FFFFh

TRDGRB0 014Bh-014Ah FFFFh
TRDGRC0 014Dh-014Ch FFFFh
TRDGRD0 014Fh-014Eh FFFFh
www.DataSheet4U.com TRDGRB1 015Bh-015Ah FFFFh
Function RW
Refer to Table 14.24 TRDGRji Register Functions in Input Capture Function.
RW
NOTE:
1. Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.
Figure 14.43 Registers TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi in Input Capture Function
The following registers are disabled in the input capture function: TRDOER1, TRDOER2, TRDOCR,
TRDPOCR0, and TRDPOCR1.
Table 14.24 TRDGRji Register Functions in Input Capture Function

Register Setting Register Function Input-Capture Input Pin
TRDGRAi − General register TRDIOAi
The value in the TRDi register can be read at input
TRDGRBi TRDIOBi
capture.
TRDGRCi BFCi = 0 General register TRDIOCi
TRDGRDi BFDi = 0 TRDIODi
capture.
TRDGRCi BFCi = 1 Buffer register TRDIOAi
TRDGRDi BFDi = 1 TRDIOBi
capture. (Refer to 14.3.2 Buffer Operation.)
BFCi, BFDi: Bits in TRDMR register
Set the pulse width of the input capture signal applied to the TRDIOji pin to 3 cycles or more of the timer RD
operation clock (refer to Table 14.11 Timer RD Operation Clocks) for no digital filter (the DFj bit in the
TRDDFi register set to 0).
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TRDCLK input
count source
Count value
in TRDi register
FFFFh
0009h
www.DataSheet4U.com 0006h
0000h
TSTARTi bit in 1
TRDSTR register 0
65536
TRDIOAi input
TRDGRAi register 0006h 0009h
Transfer Transfer
TRDGRCi register 0006h
IMFA bit in 1
TRDSRi register 0
1 Set to 0 by a program
OVF bit in
TRDSRi register 0
i = 0 or 1

Bits CCLR2 to CCLR0 in the TRDCRi register are set to 001b. (the TRDi register set to 0000h by TRDGRAi register input capture).
Bits TCK2 to TCK0 in the TRDCRi register are set to 101b (TRDCLK input for the count source).
Bits CKEG1 to CKEG0 in the TRDCRi register are set to 01b (count at the falling edge for the count source).
Bits IOA2 to IOA0 in the TRDIORAi register are set to 101b (input capture at the falling edge of the TRDIOAi input).
The BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the buffer register of the TRDGRAi register).
Figure 14.44 Operating Example of Input Capture Function
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14.3.5.1 Digital Filter

The TRDIOji input is sampled, and when the sampled input level matches 3 times, its level is determined.
Select the digital filter function and sampling clock by the TRDDFi register.
TCK2 to TCK0 DFCK1 to DFCK0

fOCO40M = 110b = 00b
= 101b f32
TRDCLK = 01b
f8
= 100b
f32 = 10b
f1
= 011b = 11b
f8
Count source
f4 = 010b
IOA2 to IOA0
f2 = 001b IOB2 to IOB0
www.DataSheet4U.com = 000b
IOC3 to IOC0
f1 IOD3 to IOD0
Sampling clock
DFj
C C C C 1
Match
Edge detection
TRDIOji input signal D Q D Q D Q D Q detection
circuit
circuit
Latch Latch Latch Latch
0
Timer RD operation clock
f1, fOCO40M)
D Q
Latch
Clock period selected by

bits TCK2 to TCK0 or
bits DFCK1 to DFCK0
Sampling clock
TRDIOji input signal
Recognition of the
signal change with
Input signal through 3-time match
digital filtering
Signal transmission delayed

up to 5-sampling clock
Transmission cannot be
performed without 3-time match
because the input signal is
assumed to be noise.
TCK0 to TCK2: Bits in TRDCRi register

DFCK0 to DFCK1 and DFj: Bits in TRDDF register
IOA0 to IOA2 and IOB0 to IOB2: Bits in TRDIORAi register
IOC0 to IOC3 and IOD0 to IOD3: Bits in TRDIORCi register
Figure 14.45 Block Diagram of Digital Filter
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14.3.6 Output Compare Function

This function detects matches (compare match) between the content of the TRDGRji (j = either A, B, C, or D)
register and the content of the TRDi (i = 0 or 1) register. When the content matches, a user-set level is output
from the TRDIOji pin. Since this function is enabled with a combination of the TRDIOji pin and TRDGRji
register, the output compare function, or any other mode or function, can be selected for each individual pin.
Figure 14.46 shows a Block Diagram of Output Compare Function, Table 14.25 lists the Output Compare
Function Specifications. Figures 14.47 to 14.58 list the Registers Associated with Output Compare Function,
and Figure 14.59 shows an Operating Example of Output Compare Function.
Channel 0
www.DataSheet4U.com
TRD0

Output
TRDIOA0
control
IOC3 = 0 in
TRDIORC0 register Comparator TRDGRA0

Output
TRDIOC0 IOC3 = 1
control
Comparator TRDGRC0

Output
TRDIOB0
control IOD3 = 0 in
TRDIORD0 register Comparator TRDGRB0

Output
TRDIOD0 IOD3 = 1
control
Comparator TRDGRD0
Channel 1
TRD1

Output
TRDIOA1 control
IOC3 = 0 in

Output
TRDIOC1 control IOC3 = 1
Comparator TRDGRC1

Output
TRDIOB1 control
IOD3 = 0 in
TRDIORD1 register
Comparator TRDGRB1

Output
TRDIOD1 control IOD3 = 1
Comparator TRDGRD1
Figure 14.46 Block Diagram of Output Compare Function
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Table 14.25 Output Compare Function Specifications

Item Specification
External signal input to the TRDCLK pin (valid edge selected by a program)
Count period • When bits CCLR2 to CCLR0 in the TRDCRi register are set to 000b (free-
running operation)
1/fk × 65536 fk: Frequency of count source
• Bits CCLR1 to CCLR0 in the TRDCRi register are set to 01b or 10b (set the
TRDi register to 0000h at the compare match in the TRDGRji register).
www.DataSheet4U.com Frequency of count source x (n+1)
n: Setting value in the TRDGRji register
Waveform output timing Compare match
Count start condition 1 (count starts) is written to the TSTARTi bit in the TRDSTR register.
Count stop conditions • 0 (count stops) is written to the TSTARTi bit in the TRDSTR register when the
CSELi bit in the TRDSTR register is set to 1.
The output compare output pin holds output level before the count stops.
• When the CSELi bit in the TRDSTR register is set to 0, the count stops at the
compare match in the TRDGRAi register.
The output compare output pin holds level after output change by the compare
match.
Interrupt request generation • Compare match (content of the TRDi register matches content of the TRDGRji
timing register.)
• TRDi register overflows
TRDIOA0 pin function Programmable I/O port, output-compare output, or TRDCLK (external clock) input
TRDIOB0, TRDIOC0, TRDIOD0, Programmable I/O port or output-compare output (Selectable by pin)
TRDIOA1 to TRDIOD1 pin
functions
INT0 pin function Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt
input
Write to timer • When the SYNC bit in the TRDMR register is set to 0 (channels 0 and 1 operate
independently).
Data can be written to the TRDi register.
• When the SYNC bit in the TRDMR register is set to 1 (channels 0 and 1 operate
synchronously).
Data can be written to both the TRD0 and TRD1 registers by writing to the TRDi
register.
Select functions • Output-compare output pin selected
Either 1 pin or multiple pins among TRDIOAi, TRDIOBi, TRDIOCi, or TRDIODi.
• Output level at the compare match selected
“L” output, “H” output, or output level inversed
• Initial output level selected
Set the level at period from the count start to the compare match.
• Timing to set the TRDi register to 0000h
Overflow or compare match in the TRDGRAi register
• Output pin in registers TRDGRCi and TRDGRDi changed
The TRDGRCi register can be used as output control of the TRDIOAi pin and
the TRDGRDi register can be used as output control of the TRDIOBi pin.
• Pulse output forced cutoff signal input (Refer to 14.3.4 Pulse Output Forced
Cutoff.)
• Timer RD can be used as the internal timer without output.
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b7 b6 b5 b4 b3 b2 b1 b0

TRDSTR 0137h 11111100b
TRD0 count start flag(4) 0 : Count stops (2)
TSTART0 RW
1 : Count starts
TSTART1 RW
1 : Count starts
www.DataSheet4U.com
TRD0 count operation 0 : Count stops at the compare match w ith the
select bit TRDGRA0 register
CSEL0 1 : Count continues at the compare match w ith the RW
TRDGRA0 register
TRD1 count operation 0 : Count stops at the compare match w ith the
select bit TRDGRA1 register
CSEL1 1 : Count continues at the compare match w ith the RW
TRDGRA1 register
—
NOTES:
2. When the CSEL0 bit is set to 1, w rite 0 to the TSTART0 bit.
4. When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count
stops).
stops).

b7 b6 b5 b4 b3 b2 b1 b0

TRDMR 0138h 00001110b
Timer RD synchronous bit 0 : Registers TRD0 and TRD1
operate independently
SYNC 1 : Registers TRD0 and TRD1 RW
operate synchronously
—
BFC0 RW
bit(1) 1 : Buffer register of TRDGRA0 register
BFD0 RW
bit(1) 1 : Buffer register of TRDGRB0 register
BFC1 RW
bit(1) 1 : Buffer register of TRDGRA1 register
BFD1 RW
bit(1) 1 : Buffer register of TRDGRB1 register
NOTE:
1. When selecting 0 (change the TRDGRji register output pin) by the IOj3 (j = C or D) bit in the TRDIORCi (i = 0 or 1)
register, set the BFji bit in the TRDMR register to 0.
Figure 14.47 Registers TRDSTR and TRDMR in Output Compare Function
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b7 b6 b5 b4 b3 b2 b1 b0

TRDPMR 0139h 10001000b
PWM mode of TRDIOB0 select bit Set to 0 (timer mode) in the output
PWMB0 RW
compare function.
PWM mode of TRDIOC0 select bit Set to 0 (timer mode) in the output
PWMC0 RW
compare function.
www.DataSheet4U.com
PWM mode of TRDIOD0 select bit Set to 0 (timer mode) in the output
PWMD0 RW
compare function.
—
PWM mode of TRDIOB1 select bit Set to 0 (timer mode) in the output
PWMB1 RW
compare function.
PWM mode of TRDIOC1 select bit Set to 0 (timer mode) in the output
PWMC1 RW
compare function.
PWM mode of TRDIOD1 select bit Set to 0 (timer mode) in the output
PWMD1 RW
compare function.
—
Figure 14.48 TRDPMR Register in Output Compare Function
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b7 b6 b5 b4 b3 b2 b1 b0

CMD0 RW
PWM3 mode) in the output compare
function.
CMD1 RW
www.DataSheet4U.com
Normal-phase output level select bit This bit is disabled in the output compare
Counter-phase output level select bit This bit is disabled in the output compare
A/D trigger enable bit This bit is disabled in the output compare
ADTRG RW
(in complementary PWM mode) function.
A/D trigger edge select bit This bit is disabled in the output compare
ADEG RW
(in complementary PWM mode) function.
STCLK RW
PWM3 RW
the output compare function.
NOTES:
enabled.
Figure 14.49 TRDFCR Register in Output Compare Function
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Timer RD Output Master Enable Register 1

b7 b6 b5 b4 b3 b2 b1 b0

TRDOER1 013Bh FFh
TRDIOA0 output disable bit 0 : Enable output
EA0 1 : Disable output (The TRDIOA0 pin is RW
used as a programmable I/O port.)
TRDIOB0 output disable bit 0 : Enable output
www.DataSheet4U.com 1 : Disable output (The TRDIOB0 pin is
EB0 RW
TRDIOC0 output disable bit 0 : Enable output
EC0 1 : Disable output (The TRDIOC0 pin is RW
TRDIOD0 output disable bit 0 : Enable output
ED0 1 : Disable output (The TRDIOD0 pin is RW
EB1 1 : Disable output (The TRDIOB1 pin is RW

b7 b6 b5 b4 b3 b2 b1 b0

TRDOER2 013Ch 01111111b
—
_____
INT0 of pulse output forced 0 : Pulse output forced cutoff input disabled
cutoff signal input enabled 1 : Pulse output forced cutoff input enabled
PTO bit(1) (All bits in the TRDOER1 register RW
are set to 1 (disable output) w hen “L” is
_____
applied to the INT0 pin.)
NOTE:
1. Refer to 14.3.4 Pulse Output Forced Cutoff.
Figure 14.50 Registers TRDOER1 to TRDOER2 in Output Compare Function
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Timer RD Output Control Register(1, 2)

b7 b6 b5 b4 b3 b2 b1 b0

TRDOCR 013Dh 00h
TRDIOA0 output level select bit 0 : Initial output “L”
TOA0 RW
1 : Initial output “H”
TRDIOB0 output level select bit 0 : Initial output “L”
TOB0 RW
1 : Initial output “H”
www.DataSheet4U.com
TRDIOC0 initial output level select bit 0 : “L”
TOC0 RW
1 : “H”
TRDIOD0 initial output level select bit
TOD0 RW
TRDIOA1 initial output level select bit

TOA1 RW
TRDIOB1 initial output level select bit

TOB1 RW
TRDIOC1 initial output level select bit

TOC1 RW
TRDIOD1 initial output level select bit

TOD1 RW
NOTES:
1. Write to the TRDOCR register w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count
stopped).
2. If the pin function is set for w aveform output (refer to Tables 14.12 to 14.19), the initial output level is output w hen
the TRDOCR register is set.
Figure 14.51 TRDOCR Register in Output Compare Function
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b7 b6 b5 b4 b3 b2 b1 b0

TRDCR0 0140h 00h
TRDCR1 0150h 00h
TCK0 0 0 0 : f1 RW
0 0 1 : f2
TCK1 0 1 1 : f8 RW
1 0 0 : f32
1 1 0 : fOCO40M
TCK2 RW
1 1 1 : Do not set.
External clock edge select b4 b3
CKEG0 bits (2) 0 0 : Count at the rising edge RW

1 1 : Do not set.
CKEG1 RW
TRDi counter clear select b7 b6 b5
bits 0 0 0 : Disable clear (free-running operation)

0 0 1 : Clear by compare match w ith the
CCLR0 RW
TRDGRAi register
TRDGRBi register
0 1 1 : Synchronous clear (clear
simultaneously w ith other channel
CCLR1 counter)(3) RW
1 0 0 : Do not set.
TRDGRCi register
CCLR2 TRDGRDi register RW
1 1 1 : Do not set.
NOTES:
3. This setting is enabled w hen the SYNC bit in the TRDMR register is set to 1 (TRD0 and TRD1 operate
synchronously).
Figure 14.52 Registers TRDCR0 to TRDCR1 in Output Compare Function
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Timer RD I/O Control Register Ai (i = 0 or 1)

b7 b6 b5 b4 b3 b2 b1 b0

TRDIORA0 0141h 10001000b
TRDIORA1 0151h 10001000b
TRDGRA control bits b1 b0
0 0 : Disable pin output by the compare match
(TRDIOAi pin functions as programmable
IOA0 RW
www.DataSheet4U.com I/O port)
0 1 : “L” output at compare match w ith
the TRDGRAi register
1 0 : “H” output at compare match w ith
the TRDGRAi register
IOA1 1 1 : Toggle output by compare match RW
w ith the TRDGRAi register
TRDGRA mode select bit(1) Set to 0 (output compare) in the output compare
IOA2 RW
function.
Input capture input sw itch Set to 1.
IOA3 RW
bit
TRDGRB control bits b5 b4
0 0 : Disable pin output by the compare match
(TRDIOBi pin functions as programmable
IOB0 RW
I/O port)
0 1 : “L” output at compare match
w ith the TRDGRBi register
1 0 : “H” output at compare match
w ith the TRDGRBi
IOB1 1 1 : Toggle output by compare match RW
w ith the TRDGRBi register
TRDGRB mode select bit(2) Set to 0 (output compare) in the output compare
IOB2 RW
function.
—
NOTES:
register.
register.
Figure 14.53 Registers TRDIORA0 to TRDIORA1 in Output Compare Function
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REJ09B0244-0300
Timer RD I/O Control Register Ci (i = 0 or 1)

b7 b6 b5 b4 b3 b2 b1 b0

TRDIORC0 0142h 10001000b
TRDIORC1 0152h 10001000b
TRDGRC control bits b1 b0
0 0 : Disable pin output by compare match
IOC0 0 1 : “L” output at compare match w ith RW
www.DataSheet4U.com the TRDGRCi register
the TRDGRCi register
IOC1 1 1 : Toggle output by compare match RW
w ith the TRDGRCi register
TRDGRC mode select bit(1) Set to 0 (output compare) in the output compare
IOC2 RW
function.
TRDGRC register function 0 : TRDIOA output register
select bit (Refer to 14.3.6.1 Changing Output Pins in
IOC3 Registers TRDGRCi (i = 0 or 1) and RW
TRDGRDi.)
1 : General register or buffer register
TRDGRD control bits b5 b4
0 0 : Disable pin output by compare match
IOD0 0 1 : “L” output at compare match w ith RW
the TRDGRDi register
the TRDGRDi register
IOD1 1 1 : Toggle output by compare match RW
w ith the TRDGRDi register
TRDGRD mode select bit(2) Set to 0 (output compare) in the output compare
IOD2 RW
function.
TRDGRD register function 0 : TRDIOB output register
select bit (Refer to 14.3.6.1 Changing Output Pins in
IOD3 Registers TRDGRCi (i = 0 or 1) and RW
TRDGRDi.)
1 : General register or buffer register
NOTES:
register.
register.
Figure 14.54 Registers TRDIORC0 to TRDIORC1 in Output Compare Function
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Timer RD Status Register i (i=0 or 1)

b7 b6 b5 b4 b3 b2 b1 b0

TRDSR0 0143h 11100000b
TRDSR1 0153h 11000000b
flag A Write 0 after read(2).
IMFA [Source for setting this bit to 1] RW
www.DataSheet4U.com When the value in the TRDi register matches w ith
the value in the TRDGRAi register.
flag B Write 0 after read(2).
When the value in the TRDi register matches w ith
the value in the TRDGRBi register.
flag C Write 0 after read(2).
the value in the TRDGRCi register (3).
flag D Write 0 after read(2).
the value in the TRDGRDi register (3).
Write 0 after read(2).
When the TRDi register overflow s.
Underflow flag(1) This bit is disabled in the output compare function.
UDF RW

—
NOTES:
• This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (This bit remains
1 even if it is set to 1 from 0 after reading, and w riting 0.)
3. Including w hen the BFji bit in the TRDMR register is set to 1 (TRDGRji is used as the buffer register).
Figure 14.55 Registers TRDSR0 to TRDSR1 in Output Compare Function
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b7 b6 b5 b4 b3 b2 b1 b0

TRDIER0 0144h 11100000b
TRDIER1 0154h 11100000b
Input capture/compare match 0 : Disable interrupt (IMIA) by the
interrupt enable bit A IMFA bit
IMIEA 1 : Enable interrupt (IMIA) by the RW
www.DataSheet4U.com IMFA bit
Input capture/compare match 0 : Disable interrupt (IMIB) by the
interrupt enable bit B IMFB bit
IMIEB 1 : Enable interrupt (IMIB) by the RW
IMFB bit
Input capture/compare match 0 : Disable interrupt (IMIC) by the
interrupt enable bit C IMFC bit
IMIEC 1 : Enable interrupt (IMIC) by the RW
IMFC bit
Input capture/compare match 0 : Disable interrupt (IMID) by the
interrupt enable bit D IMFD bit
IMIED 1 : Enable interrupt (IMID) by the RW
IMFD bit
Overflow /underflow interrupt enable 0 : Disable interrupt (OVI) by the
bit OVF bit
OVIE 1 : Enable interrupt (OVI) by the RW
OVF bit
—
Figure 14.56 Registers TRDIER0 to TRDIER1 in Output Compare Function

(b15) (b8)
b7 b0 b7 b0

TRD0 0147h-0146h 0000h
TRD1 0157h-0156h 0000h
Count a count source. Count operation is incremented. 0000h to FFFFh
NOTE:
Figure 14.57 Registers TRD0 to TRD1 in Output Compare Function
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Timer RD General Register Ai, Bi, Ci and Di (i = 0 or 1)(1)

(b15) (b8)
b7 b0 b7 b0

Function RW
Refer to Table 14.26 TRDGRji Register Function in Output Com pare Function.
RW
NOTE:
Figure 14.58 Registers TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi in Output Compare Function
The following registers are disabled in the output compare function: TRDDF0, TRDDF1, TRDPOCR0, and
TRDPOCR1.
Table 14.26 TRDGRji Register Function in Output Compare Function

Setting Output-Compare
Register Register Function
BFji IOj3 Output Pin
TRDGRAi − − General register. Write the compare value. TRDIOAi
TRDGRBi TRDIOBi
TRDGRCi 0 1 General register. Write the compare value. TRDIOCi
TRDGRDi TRDIODi
TRDGRCi 1 1 Buffer register. Write the next compare value. TRDIOAi
TRDGRDi (Refer to 14.3.2 Buffer Operation.) TRDIOBi
TRDGRCi 0 0 TRDIOAi output control. (Refer to 14.3.6.1 Changing TRDIOAi
TRDGRDi Output Pins in Registers TRDGRCi (i = 0 or 1) and TRDIOBi
TRDGRDi.)
BFji: Bit in TRDMR register IOj3: Bit in TRDIORCi register
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Count source
Value in TRDi register
www.DataSheet4U.com p
Count
restarts
Count
stops
TSTARTi bit in 1
TRDSTR register 0
m+1 m+1
Output level
held
TRDIOAi output
Output inverted by compare match
Initial output “L”

IMFA bit in 1
TRDSRi register 0
n+1
TRDIOBi output
“H” output by compare match
n+1 Output level
held
IMFB bit in 1
TRDSRi register 0
P+1 Output level
held
“L” output by compare match
TRDIOCi output
Initial output “H”
IMFC bit in 1
TRDSRi register 0
i = 0 or 1 M: Value set in TRDGRAi register

n: Value set in TRDGRBi register
p: Value set in TRDGRCi register

The CSELi bit in the TRDSTR register is set to 1 (the TRDi register is not stopped by compare match).
Bits BFCi and BFDi in the TRDMR register are set to 0 (registers TRDGRCi and TRDGRDi are not used as buffer registers).
Bits EAi, EBi, and ECi in the TRDOER1 register are set to 0 (enable the TRDIOAi, TRDIOBi and TRDIOCi pin outputs).
Bits CCLR2 to CCLR0 in the TRDCRi register are set to 001b (set the TRDi register to 000h by compare match in the TRDGRAi register).
Bits TOAi and TOBi in the TRDOCR register is set to 0 (initial output “L” to compare match), the TOCi bit is set to 1 (initial output “H” to compare match).
Bits IOA2 to IOA0 in the TRDIORAi register are set to 011b (TRDIOAi output inverted at TRDGRAi register compare match).
Bits IOB2 to IOB0 in the TRDIORAi register are set to 010b (TRDIOBi “H” output at TRDGRBi register compare match).
Bits IOC3 to IOC0 in the TRDIORCi register are set to 1001b (TRDIOCi “L” output at TRDGRCi register compare match).
The IOD3 bit in the TRDIORCi register is set to 1 (TRDGRDi register does not control TRDIOBi pin output).
Figure 14.59 Operating Example of Output Compare Function
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14.3.6.1 Changing Output Pins in Registers TRDGRCi (i = 0 or 1) and TRDGRDi

The TRDGRCi register can be used for output control of the TRDIOAi pin, and the TRDGRDi register can be
used for output control of the TRDIOBi pin. Therefore, each pin output can be controlled as follows:
• TRDIOAi output is controlled by the values in registers TRDGRAi and TRDGRCi.
• TRDIOBi output is controlled by the values in registers TRDGRBi and TRDGRDi.
Change output pins in registers TRDGRCi and TRDGRDi as follows:

• Select 0 (change TRDGRji register output pin) by the IOj3 (j = C or D) bit in the TRDIORCi register.
• Set the BFji bit in the TRDMR register to 0 (general register).
• Set different values in registers TRDGRCi and TRDGRAi. Also, set different values in registers
TRDGRDi and TRDGRBi.
www.DataSheet4U.com Figure 14.61 shows an Operating Example When TRDGRCi Register is Used for Output Control of TRDIOAi
Pin and TRDGRDi Register is Used for Output Control of TRDIOBi Pin.
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Channel 0
TRD0

Output
TRDIOA0
control IOC3 = 0 in

Output
TRDIOC0 IOC3 = 1
control
www.DataSheet4U.com Comparator TRDGRC0

Output
TRDIOB0
control IOD3 = 0 in
TRDIORD0 register Comparator TRDGRB0

Output
TRDIOD0 IOD3 = 1
control
Comparator TRDGRD0
Channel 1
TRD1

Output
TRDIOA1 control
IOC3 = 0 in

Output
TRDIOC1 control IOC3 = 1
Comparator TRDGRC1

Output
TRDIOB1 control
IOD3 = 0 in
TRDIORD1 register
Comparator TRDGRB1

Output
TRDIOD1 control IOD3 = 1
Comparator TRDGRD1
Figure 14.60 Changing Output Pins in Registers TRDGRCi and TRDGRDi
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Count source
FFFFh
m
www.DataSheet4U.com p
0000h
m+1
n+1 m-n
p+1
q+1 p-q

TRDIOAi output
IMFA bit in 1
TRDSRi register 0
Set to 0 by a program Set to 0 by a program
IMFC bit in 1
TRDSRi register 0

TRDIOBi output
IMFB bit in 1
TRDSRi register 0

IMFD bit in 1
TRDSRi register 0
m: Value set in TRDGRAi register

n: Value set in TRDGRCi register
p: Value set in TRDGRBi register
i = 0 or 1 q: Value set in TRDGRDi register

The CSELi bit in the TRDSTR register is set to 1 (the TRDi register is not stopped by compare match).
Bits BFCi and BFDi in the TRDMR register are set to 0 (registers TRDGRCi and TRDGRDi are not used as buffer register).
Bits EAi and EBi in the TRDOER1 register are set to 0 (enable TRDIOAi and TRDIOBi pin outputs).
Bits CCLR2 to CCLR0 in the TRDCRi register are set to 001b (set the TRDi register to 0000h by compare match in the TRDGRAi register).
Bits TOAi and TOBi in the TRDOCR register are set to 0 (initial output “L” to compare match).
Bits IOA2 to IOA0 in the TRDIORAi register are set to 011b (TRDIOAi output inverted at TRDGRAi register compare match).
Bits IOB2 to IOB0 in the TRDIORAi register are set to 011b (TRDIOBi output inverted at TRDGRBi register compare match).
Bits IOC3 to IOC0 in the TRDIORCi register are set to 0011b (TRDIOAi output inverted at TRDGRCi register compare match).
Bits IOD3 to IOD0 in the TRDIORCi register are set to 0011b (TRDIOBi output inverted at TRDGRDi register compare match).
Figure 14.61 Operating Example When TRDGRCi Register is Used for Output Control of TRDIOAi
Pin and TRDGRDi Register is Used for Output Control of TRDIOBi Pin
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14.3.7 PWM Mode

In PWM mode, a PWM waveform is output. Up to 3 PWM waveforms with the same period can be output by 1
channel. Also, up to 6 PWM waveforms with the same period can be output by synchronizing channels 0 and 1.
Since this mode functions by a combination of the TRDIOji (i = 0 or 1, j = B, C, or D) pin and TRDGRji
register, the PWM mode, or any other mode or function, can be selected for each individual pin. (However,
since the TRDGRAi register is used when using any pin for PWM mode, the TRDGRAi register cannot be used
for other modes.)
Figure 14.62 shows a Block Diagram of PWM Mode, and Table 14.27 lists the PWM Mode Specifications.
Figures 14.63 to 14.72 show the Registers Associated with PWM Mode, and Figures 14.73 and 14.74 show
Operating Examples of PWM Mode.
www.DataSheet4U.com
TRDi
TRDIOBi Comparator TRDGRAi

(Note 1)
TRDIOCi Output Comparator TRDGRBi

control Compare match signal
TRDIODi Comparator TRDGRCi

Compare match signal (Note 2)
Comparator TRDGRDi
i = 0 or 1
NOTES:
1. When the BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the
buffer register of the TRDGRAi register).
2. When the BFDi bit in the TRDMR register is set to 1 (the TRDGRDi register is used as the
buffer register of the TRDGRBi register).
Figure 14.62 Block Diagram of PWM Mode
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REJ09B0244-0300
Table 14.27 PWM Mode Specifications

Item Specification
program)
PWM waveform PWM period: 1/fk x (m+1)
Active level width: 1/fk x (m-n)
Inactive level width: 1/fk x (n+1)
www.DataSheet4U.com
fk: Frequency of count source
m: Value set in the TRDGRAi register
n: Value set in the TRDGRji register
m+1
n+1 m-n (When “L” is selected as the active level)
Count start condition 1 (count starts) is written to the TSTARTi bit in the TRDSTR register.
Count stop conditions • 0 (count stops) is written to the TSTARTi bit in the TRDSTR register
when the CSELi bit in the TRDSTR register is set to 1.
The PWM output pin holds output level before the count stops.
• When the CSELi bit in the TRDSTR register is set to 0, the count
stops at the compare match in the TRDGRAi register.
The PWM output pin holds level after output change by compare
match.
Interrupt request generation • Compare match (The content of the TRDi register matches content of
timing the TRDGRhi register.)
• TRDi register overflows
TRDIOA0 pin function Programmable I/O port or TRDCLK (external clock) input
TRDIOA1 pin function Programmable I/O port
TRDIOB0, TRDIOC0, TRDIOD0, Programmable I/O port or pulse output (selectable by pin)
TRDIOB1, TRDIOC1, TRDIOD1
pin functions
INT0 pin function Programmable I/O port, pulse output forced cutoff signal input, or INT0
interrupt input
Write to timer The value can be written to the TRDi register.
Select functions • 1 to 3 PWM output pins selected per 1 channel
Either 1 pin or multiple pins of the TRDIOBi, TRDIOCi or TRDIODi
pin.
• The active level selected by pin.
• Initial output level selected by pin.
• Pulse output forced cutoff signal input (Refer to 14.3.4 Pulse Output
Forced Cutoff.)
i = 0 or 1
j = either B, C, or D
h = either A, B, C, or D
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b7 b6 b5 b4 b3 b2 b1 b0

TRDSTR 0137h 11111100b
TSTART0 RW
1 : Count starts
TSTART1 RW
1 : Count starts
www.DataSheet4U.com
TRD0 count operation select bit 0 : Count stops at compare match w ith
the TRDGRA0 register
CSEL0 1 : Count continues at compare match w ith RW
—
NOTES:
stops).
stops).

b7 b6 b5 b4 b3 b2 b1 b0

TRDMR 0138h 00001110b
Timer RD synchronous bit 0 : Registers TRD0 and TRD1 operate
independently
SYNC 1 : Registers TRD0 and TRD1 operate RW
synchronously
—
TRDGRC0 register function 0 : General register
BFC0 RW
select bit 1 : Buffer register of TRDGRA0 register
TRDGRD0 register function 0 : General register
BFD0 RW
select bit 1 : Buffer register of TRDGRB0 register
TRDGRC1 register function 0 : General register
BFC1 RW
select bit 1 : Buffer register of TRDGRA1 register
TRDGRD1 register function 0 : General register
BFD1 RW
select bit 1 : Buffer register of TRDGRB1 register
Figure 14.63 Registers TRDSTR and TRDMR in PWM Mode
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b7 b6 b5 b4 b3 b2 b1 b0

TRDPMR 0139h 10001000b
PWM mode of TRDIOB0 select bit 0 : Timer mode
PWMB0 RW
1 : PWM mode
PWM mode of TRDIOC0 select bit 0 : Timer mode
PWMC0 RW
1 : PWM mode
www.DataSheet4U.com
PWM mode of TRDIOD0 select bit 0 : Timer mode
PWMD0 RW
1 : PWM mode
—
PWM mode of TRDIOB1 select bit 0 : Timer mode
PWMB1 RW
1 : PWM mode
PWM mode of TRDIOC1 select bit 0 : Timer mode
PWMC1 RW
1 : PWM mode
PWM mode of TRDIOD1 select bit 0 : Timer mode
PWMD1 RW
1 : PWM mode
—
Figure 14.64 TRDPMR Register in PWM Mode
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b7 b6 b5 b4 b3 b2 b1 b0

CMD0 RW
PWM3 mode) in PWM mode.
CMD1 RW
www.DataSheet4U.com
Normal-phase output level select Bit This bit is disabled in PWM mode.
(in reset synchronous PWM mode or
Counter-phase output level select bit This bit is disabled in PWM mode.
(in reset synchronous PWM mode or
A/D trigger enable bit This bit is disabled in PWM mode.

ADTRG RW
(in complementary PWM mode)
A/D trigger edge select bit This bit is disabled in PWM mode.
ADEG RW
(in complementary PWM mode)
STCLK RW
PWM3 RW
PWM mode.
NOTES:
enabled.
Figure 14.65 TRDFCR Register in PWM Mode
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b7 b6 b5 b4 b3 b2 b1 b0

TRDOER1 013Bh FFh
EB0 RW

b7 b6 b5 b4 b3 b2 b1 b0

TRDOER2 013Ch 01111111b
—
_____
cutoff signal input enabled bit(1) 1 : Pulse output forced cutoff input enabled
(All bits in the TRDOER1 register
PTO RW
_____
NOTE:
Figure 14.66 Registers TRDOER1 to TRDOER2 in PWM Mode
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Timer RD Output Control Register(1)

b7 b6 b5 b4 b3 b2 b1 b0

TRDOCR 013Dh 00h
TRDIOA0 output level select bit Set this bit to 0 (enable output) in
TOA0 RW
PWM mode.
TOB0 TRDIOB0 output level select bit(2) 0 : Initial output is inactive RW
TOC0 TRDIOC0 initial output level select bit(2) level RW
www.DataSheet4U.com 1 : Initial output is active level
TOD0 TRDIOD0 initial output level select bit(2) RW
TRDIOA1 initial output level select bit Set this bit to 0 (enable output) in
TOA1 RW
PWM mode.
TOB1 TRDIOB1 initial output level select bit(2) 0 : Inactive level RW
TOC1 TRDIOC1 initial output level select bit(2) 1 : Active level RW
TOD1 TRDIOD1 initial output level select bit(2) RW
NOTES:
1. Write to the TRDOCR register w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count
stops).
2. If the pin function is set for w aveform output (refer to Tables 14.13 to 14.15 and Tables 14.17 to 14.19), the initial
output level is output w hen the TRDOCR register is set.

b7 b6 b5 b4 b3 b2 b1 b0

TRDCR0 0140h 00h
TRDCR1 0150h 00h
TCK0 0 0 0 : f1 RW
0 0 1 : f2
0 1 0 : f4
TCK1 0 1 1 : f8 RW
1 0 0 : f32
1 1 0 : fOCO40M
TCK2 RW
1 1 1 : Do not set.

1 1 : Do not set.
CKEG1 RW
CCLR0 TRDi counter clear select bits Set to 001b (the TRDi register cleared at RW
CCLR1 compare match w ith TRDGRAi register) in PWM RW
CCLR2 mode. RW
NOTES:
Figure 14.67 Registers TRDOCR and TRDCR0 to TRDCR1 in PWM Mode
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REJ09B0244-0300
Timer RD Status Register i (i=0 or 1)

b7 b6 b5 b4 b3 b2 b1 b0

TRDSR0 0143h 11100000b
TRDSR1 0153h 11000000b
Underflow flag(1) This bit is disabled in PWM mode.
UDF RW

—
NOTES:
• This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (This bit remains
1 even if it is set to 1 from 0 after reading, and w riting 0.)
• This bit remains unchanged if 1 is w ritten.
Figure 14.68 Registers TRDSR0 to TRDSR1 in PWM Mode
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b7 b6 b5 b4 b3 b2 b1 b0

TRDIER0 0144h 11100000b
TRDIER1 0154h 11100000b
IMFB bit
IMFC bit
IMFD bit
bit OVF bit
OVF bit
—
Figure 14.69 Registers TRDIER0 to TRDIER1 in PWM Mode
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Timer RD PWM Mode Output Level Control Register i (i = 0 or 1)

b7 b6 b5 b4 b3 b2 b1 b0

TRDPOCR0 0145h 11111000b
TRDPOCR1 0155h 11111000b
PWM mode output level control bit 0 : “L” active TRDIOBi output level is
B selected
POLB 1 : “H” active TRDIOBi output level is RW
www.DataSheet4U.com selected
PWM mode output level control bit 0 : “L” active TRDIOCi output level is
C selected
POLC 1 : “H” active TRDIOCi output level is RW
selected
PWM mode output level control bit 0 : “L” active TRDIODi output level is
D selected
POLD 1 : “H” active TRDIODi output level is RW
selected
—
Figure 14.70 Registers TRDPOCR0 to TRDPOCR1 in PWM Mode

(b15) (b8)
b7 b0 b7 b0

TRD0 0147h-0146h 0000h
TRD1 0157h-0156h 0000h
NOTE:
Figure 14.71 Registers TRD0 to TRD1 in PWM Mode
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(b15) (b8)
b7 b0 b7 b0

Function RW
Refer to Table 14.28 TRDGRji Register Functions in PWM Mode.
RW
NOTE:
Figure 14.72 Registers TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi in PWM Mode
The following registers are disabled in the PWM mode: TRDDF0, TRDDF1, TRDIORA0, TRDIORC0,
TRDIORA1, and TRDIORC1.
Table 14.28 TRDGRji Register Functions in PWM Mode

Register Setting Register Function PWM Output Pin
TRDGRAi − General register. Set the PWM period −
TRDGRBi − General register. Set the changing point of PWM output TRDIOBi
TRDGRCi BFCi = 0 General register. Set the changing point of PWM output TRDIOCi
TRDGRDi BFDi = 0 TRDIODi
TRDGRCi BFCi = 1 Buffer register. Set the next PWM period. −
(Refer to 14.3.2 Buffer Operation.)
TRDGRDi BFDi = 1 Buffer register. Set the changing point of the next PWM TRDIOBi
output. (Refer to 14.3.2 Buffer Operation.)
i = 0 or 1
BFCi, BFDi: Bits in TRDMR register
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Count source

m
p
www.DataSheet4U.com
m+1
n+1 m-n
TRDIOBi output Active level “H” Inactive level “L”
Initial output “L” to p+1 m-p

compare match
TRDIOCi output Initial output “H” to Inactive level “H”

compare match
q+1 m-q
TRDIODi output Active level “L”
Initial output “L” to

1 compare match
IMFA bit in
TRDSRi register 0

IMFB bit in 1
TRDSRi register 0
IMFC bit in 1
TRDSRi register 0

IMFD bit in 1
TRDSRi register 0
m: Value set in TRDGRAi register

n: Value set in TRDGRBi register
i = 0 or 1 p: Value set in TRDGRCi register
q: Value set in TRDGRDi register
Bits BFCi and BFDi in the TRDMR register are set to 0 (registers TRDGRCi and TRDGRDi are not used as buffer registers).
Bits EBi, ECi and EDi in the TRDOER1 register are set to 0 (enable TRDIOBi, TRDIOCi and TRDIODi pin outputs).
Bits TOBi and TOCi in the TRDOCR register are set to 0 (inactive level), the TODi bit is set to 1 (active level).
The POLB bit in the TRDPOCRi register is set to 1 (active level “H”), bits POLC and POLD are set to 0 (active level “L”).
Figure 14.73 Operating Example of PWM Mode
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p
m
q
n
0000h
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TSTARTi bit in 1
TRDSTR register Since no compare match in the TRDGRBi register is
0
generated, “L” is not applied to the TRDIOBi output
TRDIOBi output Duty 0%
TRDGRBi register n p (p>m) q
Rewrite by a program
IMFA bit in 1
TRDSRi register
0
IMFB bit in 1
TRDSRi register
0
p
n
0000h
TSTARTi bit in 1
When compare matches with registers TRDGRAi and TRDGRBi are generated
TRDSTR register simultaneously, the compare match with the TRDGRBi register has priority.
0
“L” is applied to the TRDIOBi output without any change.
TRDIOBi output Duty 100%
“L” is applied to TRDIOBi output at compare match

with the TRDGRBi register with no change.
TRDGRBi register n m p
Rewrite by a program
IMFA bit in 1
TRDSRi register
0
IMFB bit in 1
TRDSRi register
0
i = 0 or 1 m: Value set in TRDGRAi register

The EBi bit in the TRDOER1 register is set to 0 (enable TRDIOBi output).
The POLB bit in the TRDPOCRi register is set to 0 (active level “L”).
Figure 14.74 Operating Example of PWM Mode (Duty 0%, Duty 100%)
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14.3.8 Reset Synchronous PWM Mode

In this mode, 3 normal-phases and 3 counter-phases of the PWM waveform are output with the same period
(three-phase, sawtooth wave modulation, and no dead time).
Figure 14.75 shows a Block Diagram of Reset Synchronous PWM Mode, and Table 14.29 lists the Reset
Synchronous PWM Mode Specifications. Figures 14.76 to 14.83 show the Registers Associated with Reset
Synchronous PWM Mode and Figure 14.84 shows an Operating Example of Reset Synchronous PWM Mode.
Refer to Figure 14.74 Operating Example of PWM Mode (Duty 0%, Duty 100%) for an operating example
of PWM Mode with duty 0% and duty 100%.
Buffer(1) Waveform control

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TRDGRC0 TRDGRA0
Period TRDIOC0
register register
Normal-phase
TRDIOB0
TRDGRD0 TRDGRB0 PWM1 Counter-phase
register register TRDIOD0
Normal-phase
TRDGRC1 TRDGRA1 TRDIOA1
PWM2 Counter-phase
register register TRDIOC1
Normal-phase
TRDGRD1 TRDGRB1 TRDIOB1
PWM3 Counter-phase
NOTE:
1. When bits BFC0, BFD0, BFC1, and BFD1 in the TRDMR register are set to 1 (buffer register).
Figure 14.75 Block Diagram of Reset Synchronous PWM Mode
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Table 14.29 Reset Synchronous PWM Mode Specifications

Item Specification
program)
Count operations The TRD0 register is incremented (the TRD1 register is not used).
PWM waveform PWM period : 1/fk × (m+1)
Active level width of normal-phase : 1/fk × (m-n)
Active level width of counter-phase: 1/fk × (n+1)
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m: Value set in the TRDGRA0 register
n: Value set in the TRDGRB0 register (PWM1 output),
Value set in the TRDGRA1 register (PWM2 output),
Value set in the TRDGRB1 register (PWM3 output)
m+1
Normal-phase
m-n
Counter-phase
n+1 (When “L” is selected as the active level)
Count start condition 1 (count starts) is written to the TSTART0 bit in the TRDSTR register.
Count stop conditions • 0 (count stops) is written to the TSTART0 bit in the TRDSTR register
when the CSEL0 bit in the TRDSTR register is set to 1.
The PWM output pin holds output level before the count stops
• When the CSEL0 bit in the TRDSTR register is set to 0, the count
stops at the compare match in the TRDGRA0 register.
The PWM output pin holds level after output change at compare
match.
Interrupt request generation • Compare match (the content of the TRD0 register matches content
timing of registers TRDGRj0, TRDGRA1, and TRDGRB1).
• The TRD0 register overflows
TRDIOB0 pin function PWM1 output normal-phase output
TRDIOD0 pin function PWM1 output counter-phase output
TRDIOA1 pin function PWM2 output normal-phase output
TRDIOC1 pin function PWM2 output counter-phase output
TRDIOC0 pin function Output inverted every PWM period
INT0 pin function Programmable I/O port, pulse output forced cutoff signal input, or
INT0 interrupt input
Read from timer The count value can be read by reading the TRD0 register.
Write to timer The value can be written to the TRD0 register.
Select functions • The active level of normal-phase and counter-phase and initial
output level selected individually.
• Pulse output forced cutoff signal input (Refer to 14.3.4 Pulse
Output Forced Cutoff.)
j = either A, B, C, or D
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TRDSTR 0137h 11111100b
TSTART0 RW
1 : Count starts
TSTART1 RW
1 : Count starts
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TRD0 count operation select bit 0 : Count stops at compare match w ith the
TRDGRA0 register
CSEL0 1 : Count continues at compare match w ith the RW
TRDGRA0 register
TRD1 count operation select bit 0 : Count stops at compare match w ith the
TRDGRA1 register
CSEL1 1 : Count continues at compare match w ith the RW
TRDGRA1 register
—
NOTES:
stops).
stops).

b7 b6 b5 b4 b3 b2 b1 b0

TRDMR 0138h 00001110b
Timer RD synchronous bit Set this bit to 0 (registers TRD0 and TRD1
SYNC operate independently) in reset synchronous RW
PWM mode.
—
BFC0 RW
BFD0 RW
BFC1 RW
BFD1 RW
Figure 14.76 Registers TRDSTR and TRDMR in Reset Synchronous PWM Mode
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Combination mode select bits (1, 2) Set to 01b (reset synchronous PWM
CMD0 RW
mode) in reset synchronous PWM mode.
CMD1 RW
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Normal-phase output level select bit 0 : Initial output “H”
(in reset synchronous PWM mode or Active level “L”
OLS0 complementary PWM mode) 1 : Initial output “L” RW
Active level “H”
Counter-phase output level select bit 0 : Initial output “H”

A/D trigger enable bit This bit is disabled in reset synchronous

ADTRG RW
(in complementary PWM mode) PWM mode.
A/D trigger edge select bit This bit is disabled in reset synchronous
ADEG RW
(in complementary PWM mode) PWM mode.
STCLK RW
PWM3 mode select bit(3) This bit is disabled in reset synchronous
PWM3 RW
PWM mode.
NOTES:
1. When bits CMD1 to CMD0 are set to 01b, 10b, or 11b, the MCU enters reset synchronous PWM mode or
complementary PWM mode in spite of the setting of the TRDPMR register.
enabled.
Figure 14.77 TRDFCR Register in Reset Synchronous PWM Mode
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TRDOER1 013Bh FFh
TRDIOA0 output disable bit Set this bit to 1 (the TRDIOA0 pin is
EA0 used as a programmable I/O port) in reset RW
synchronous PWM mode.
EB0 RW

b7 b6 b5 b4 b3 b2 b1 b0

TRDOER2 013Ch 01111111b
—
_____
PTO RW
_____
NOTE:
Figure 14.78 Registers TRDOER1 to TRDOER2 in Reset Synchronous PWM Mode
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Timer RD Control Register 0(3)

b7 b6 b5 b4 b3 b2 b1 b0

TRDCR0 0140h 00h
Count source select bits b2 b1b0
TCK0 0 0 0 : f1 RW
0 0 1 : f2
0 1 0 : f4
TCK1 RW
1 0 0 : f32
1 1 0 : fOCO40M
TCK2 RW
1 1 1 : Do not set.

1 1 : Do not set.
CKEG1 RW
CCLR0 TRD0 counter clear select bits Set to 001b (TRD0 register cleared at compare RW
CCLR1 match w ith TRDGRA0 register) in reset RW
CCLR2 synchronous PWM mode. RW
NOTES:
3. The TRDCR1 register is not used in reset synchronous PWM mode.
Figure 14.79 TRDCR0 Register in Reset Synchronous PWM Mode
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TRDSR0 0143h 11100000b
TRDSR1 0153h 11000000b
Input capture/compare match [Source for setting this bit to 0”]
Underflow flag(1) This bit is disabled in reset synchronous PWM
UDF RW
mode.
—
NOTES:
• This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit (this bit remains
1 even if it is set to 1 from 0 after reading, and w riting 0).
Figure 14.80 Registers TRDSR0 to TRDSR1 in Reset Synchronous PWM Mode
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TRDIER0 0144h 11100000b
TRDIER1 0154h 11100000b
IMFB bit
IMFC bit
IMFD bit
bit OVF bit
OVF bit
—
Figure 14.81 Registers TRDIER0 to TRDIER1 in Reset Synchronous PWM Mode
Timer RD Counter 0(1, 2)

(b15) (b8)
b7 b0 b7 b0

TRD0 0147h-0146h 0000h
When an overflow occurs, the OVF bit in the TRDSR0 register is set to 1. RW
NOTES:
1. Access the TRD0 register in 16-bit units. Do not access it in 8-bit units.
2. The TRD1 register is not used in reset synchronous PWM mode.
Figure 14.82 TRD0 Registrar in Reset Synchronous PWM Mode
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(b15) (b8)
b7 b0 b7 b0

Function RW
Refer to Table 14.30 TRDGRji Register Functions in Reset Synchronous PWM Mode.
RW
NOTE:
Figure 14.83 Registers TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi in Reset Synchronous PWM Mode
The following registers are disabled in the reset synchronous PWM mode: TRDPMR, TRDOCR, TRDDF0,
TRDDF1, TRDIORA0, TRDIORC0, TRDPOCR0, TRDIORA1, TRDIORC1, and TRDPOCR1.
Table 14.30 TRDGRji Register Functions in Reset Synchronous PWM Mode

TRDGRA0 − General register. Set the PWM period. (Output inverted every PWM
period and TRDIOC0 pin)
TRDGRB0 − General register. Set the changing point of TRDIOB0
PWM1 output. TRDIOD0
TRDGRC0 BFC0 = 0 (These registers are not used in reset −
TRDGRD0 BFD0 = 0 synchronous PWM mode.)
TRDGRA1 − General register. Set the changing point of TRDIOA1
PWM2 output. TRDIOC1
TRDGRB1 − General register. Set the changing point of TRDIOB1
PWM3 output. TRDIOD1
TRDGRC1 BFC1 = 0 (These points are not used in reset −
TRDGRD1 BFD1 = 0 synchronous PWM mode.)
TRDGRC0 BFC0 = 1 Buffer register. Set the next PWM period. (Output inversed every PWM
(Refer to 14.3.2 Buffer Operation.) period and TRDIOC0 pin)
TRDGRD0 BFD0 = 1 Buffer register. Set the changing point of TRDIOB0
the next PWM1 output. TRDIOD0
TRDGRC1 BFC1 = 1 Buffer register. Set the changing point of TRDIOA1
the next PWM2 output. TRDIOC1
TRDGRD1 BFD1 = 1 Buffer register. Set the changing point of TRDIOB1
the next PWM3 output. TRDIOD1
BFC0, BFD0, BFC1, BFD1: Bits in TRDMR register
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Count source
Value in TRD0 register
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q
0000h
TSTARTi bit in 1
TRDSTR register 0 m+1
m-n
TRDIOB0 output
n+1
TRDIOD0 output
m-p
TRDIOA1 output
p+1
TRDIOC1 output
m-q
TRDIOB1 output
q+1 Active level “L”
TRDIOD1 output
Active level “L”
TRDIOC0 output
IMFA bit in 1
TRDSR0 register 0

IMFB bit in 1
TRDSR0 register 0
IMFA bit in 1
TRDSR1 register 0

IMFB bit in 1
TRDSR1 register 0
Transfer from the buffer register to the Transfer from the buffer register to the
general register during buffer operation general register during buffer operation
m: Value set in TRDGRA0 register

n: Value set in TRDGRB0 register
i = 0 or 1 p: Value set in TRDGRA1 register
q: Value set in TRDGRB1 register
Bits OLS1 and OLS0 in the TRDFCR register are set to 0 (initial output level “H”, active level “L”).
Figure 14.84 Operating Example of Reset Synchronous PWM Mode
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14.3.9 Complementary PWM Mode

In this mode, 3 normal-phases and 3 counter-phases of the PWM waveform are output with the same period
(three-phase, triangular wave modulation, and with dead time).
Figure 14.85 shows a Block Diagram of Complementary PWM Mode, and Table 14.31 lists the
Complementary PWM Mode Specifications. Figures 14.86 to 14.94 show the Registers Associated with
Complementary PWM Mode, Figure 14.95 shows the Output Model of Complementary PWM Mode, and
Figure 14.96 shows an Operating Example of Complementary PWM Mode.
Buffer Waveform control

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TRDGRA0
Period TRDIOC0
register
Normal-phase
TRDIOB0
TRDGRD0 TRDGRB0 PWM1
register register Counter-phase
TRDIOD0
Normal-phase
TRDGRC1 TRDGRA1 TRDIOA1
PWM2 Counter-phase
register register TRDIOC1
Normal-phase
TRDGRD1 TRDGRB1 TRDIOB1
PWM3 Counter-phase
Figure 14.85 Block Diagram of Complementary PWM Mode
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Table 14.31 Complementary PWM Mode Specifications

Item Specification
External signal input to the TRDCLK pin (valid edge selected by a program)
Set bits TCK2 to TCK0 in the TRDCR1 register to the same value (same count
source) as bits TCK2 to TCK0 in the TRDCR0 register.
Count operations Increment or decrement
Registers TRD0 and TRD1 are decremented with the compare match in registers
TRD0 and TRDGRA0 during increment operation. The TRD1 register value is
changed from 0000h to FFFFh during decrement operation, and registers TRD0 and
TRD1 are incremented.
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PWM operations PWM period: 1/fk × (m+2-p) × 2(1)
Dead time: p
Active level width of normal-phase: 1/fk × (m-n-p+1) × 2
Active level width of counter-phase: 1/fk × (n+1-p) × 2
n: Value set in the TRDGRB0 register (PWM1 output)
Value set in the TRDGRA1 register (PWM2 output)
Value set in the TRDGRB1 register (PWM3 output)
p: Value set in the TRD0 register
m+2-p
n+1
Normal-phase
Counter-phase
n+1-p p m-p-n+1 (When “L” is selected as the active level)
Count start condition 1 (count starts) is written to bits TSTART0 and TSTART1 in the TRDSTR register.
Count stop conditions 0 (count stops) is written to bits TSTART0 and TSTART1 in the TRDSTR register
(The PWM output pin holds output level before the count stops.)
Interrupt request generation • Compare match (The content of the TRDi register matches content of the TRDGRji
timing register.)
• The TRD1 register underflows
TRDIOA1 pin function PWM2 output normal-phase output
TRDIOC1 pin function PWM2 output counter-phase output
TRDIOC0 pin function Output inverted every 1/2 period of PWM
INT0 pin function Programmable I/O port, pulse output forced cutoff signal input or INT0 interrupt input
Write to timer The value can be written to the TRDi register.
Select functions • Pulse output forced cutoff signal input (Refer to 14.3.4 Pulse Output Forced
Cutoff.)
• The active level of normal-phase and counter-phase and initial output level
selected individually
• Transfer timing from the buffer register selected
• A/D trigger generated
NOTE:
1. After a count starts, the PWM period is fixed.
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TRDSTR 0137h 11111100b
TSTART0 RW
1 : Count starts
TSTART1 RW
1 : Count starts
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—
NOTES:
stops).
stops).
Figure 14.86 TRDSTR Register in Complementary PWM Mode
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TRDMR 0138h 00001110b
Timer RD synchronous bit Set this bit to 0 (registers TRD0 and TRD1
operate independently) in complementary
SYNC PWM mode. RW
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—
TRDGRC0 register function select bit Set this bit to 0 (general register) in
BFC0 complementary PWM mode. RW
TRDGRD0 register function select bit 0 : General register

BFD0 1 : Buffer register of TRDGRB0 register RW
TRDGRC1 register function select bit 0 : General register

BFC1 1 : Buffer register of TRDGRA1 register RW
TRDGRD1 register function select bit 0 : General register

BFD1 1 : Buffer register of TRDGRB1 register RW
Figure 14.87 TRDMR Register in Complementary PWM Mode
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Combination mode select bits (1,2) b1 b0
1 0 : Complementary PWM mode
(transfer from the
CMD0 buffer register to the general RW
www.DataSheet4U.com register at the underflow in
the TRD1 register)
1 1 : Complementary PWM mode
(transfer from the
buffer register to the general
CMD1 register at the compare match w ith RW
registers TRD0 and TRDGRA0.)
Other than above : Do not set.
Normal-phase output level select bit 0 : Initial output “H”

Counter-phase output level select bit 0 : Initial output “H”

A/D trigger enable bit 0 : Disable A/D trigger

ADTRG (in complementary PWM mode) 1 : Enable A/D trigger (3) RW
A/D trigger edge select bit 0 : A/D trigger is generated at

(in complementary PWM mode) compare match betw een registers
ADEG TRD0 and TRDGRA0 RW
1 : A/D trigger is generated at underflow
in the TRD1 register
STCLK RW
PWM3 mode select bit(4) This bit is disabled in complementary PWM
PWM3 RW
mode.
NOTES:
1. When setting bits CMD1 to CMD0 to 10b or 11b, the MCU enters complementary PWM mode in spite of the setting of
the TRDPMR register.
3. Set the ADCAP bit in the ADC0N0 register to 1 (starts by timer RD).
enabled.
Figure 14.88 TRDFCR Register in Complementary PWM Mode
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TRDOER1 013Bh FFh
TRDIOA0 output disable bit Set this bit to 1 (the TRDIOA0 pin is
used as a programmable I/O port) in
EA0 complementary PWM mode. RW
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b7 b6 b5 b4 b3 b2 b1 b0

TRDOER2 013Ch 01111111b
—
_____
PTO RW
_____
NOTE:
Figure 14.89 Registers TRDOER1 to TRDOER2 in Complementary PWM Mode
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TRDCR0 0140h 00h
TRDCR1 0150h 00h
Count source select bits (2) b2 b1 b0
TCK0 0 0 0 : f1 RW
0 0 1 : f2
TCK1 0 1 1 : f8 RW
1 0 0 : f32
1 1 0 : fOCO40M
TCK2 RW
1 1 1 : Do not set.
External clock edge select bits (2,3) b4 b3

1 1 : Do not set.
CKEG1 RW
TRDi counter clear select bits Set to 000b (disable clearing (free-running
CCLR0 RW
operation)) in complementary PWM mode.
CCLR1 RW
CCLR2 RW
NOTES:
2. Set bits TCK2 to TCK0 and bits CKEG1 to CKEG0 in registers TRDCR0 and TRDCR1 to the same values.
Figure 14.90 Registers TRDCR0 to TRDCR1 in Complementary PWM Mode
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TRDSR0 0143h 11100000b
TRDSR1 0153h 11000000b
Input capture/compare match flag A [Source for setting this bit to 0]
www.DataSheet4U.com IMFA When the value in the TRDi register RW
matches w ith the value in the TRDGRAi
register.
Input capture/compare match flag B [Source for setting this bit to 0]

IMFB When the value in the TRDi register RW
matches w ith the value in the TRDGRBi
register.
Input capture/compare match flag C [Source for setting this bit to 0]
IMFC When the value in the TRDi register RW
matches w ith the value in the TRDGRCi
register (3).
Input capture/compare match flag D [Source for setting this bit to 0]

IMFD When the value in the TRDi register RW
matches w ith the value in the TRDGRDi
register (3).
Underflow flag(1) [Source for setting this bit to 0]
UDF [Source for setting this bit to 1] RW
When the TRD1 register underflow s.
—
NOTES:
Figure 14.91 Registers TRDSR0 to TRDSR1 in Complementary PWM Mode
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TRDIER0 0144h 11100000b
TRDIER1 0154h 11100000b
IMFB bit
IMFC bit
IMFD bit
bit OVF and UDF bits
OVF and UDF bits
—
Figure 14.92 Registers TRDIER0 to TRDIER1 in Complementary PWM Mode
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Timer RD Counter 0(1)

(b15) (b8)
b7 b0 b7 b0

TRD0 0147h-0146h 0000h
Set the dead time. 0000h to FFFFh
Count a count source. Count operation is incremented or decremented.
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NOTE:
Timer RD Counter 1(1)

(b15) (b8)
b7 b0 b7 b0

TRD1 0157h-0156h 0000h
Select 0000h. 0000h to FFFFh
Count a count source. Count operation is incremented or decremented.
When an underflow occurs, the UDF bit in the TRDSR1 register is set to 1. RW
NOTE:
Figure 14.93 Registers TRD0 to TRD1 in Complementary PWM Mode
Timer RD General Registers Ai, Bi, C1, and Di (i = 0 or 1)(1, 2)

(b15) (b8)
b7 b0 b7 b0

Function RW
Refer to Table 14.32 TRDGRji Register Functions in Com plem entary PWM Mode .
RW
NOTES:
2. The TRDGRC0 register is not used in complementary PWM mode.
Figure 14.94 Registers TRDGRAi, TRDGRBi, TRDGRC1, and TRDGRDi in Complementary PWM Mode
The following registers are disabled in the complementary PWM mode: TRDPMR, TRDOCR, TRDDF0,
TRDDF1, TRDIORA0, TRDIORC0, TRDPOCR0, TRDIORA1, TRDIORC1, and TRDPOCR1.
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Table 14.32 TRDGRji Register Functions in Complementary PWM Mode

TRDGRA0 − General register. Set the PWM period at initialization. (Output inverted every half
Setting range: Setting value or above in TRD0 register period of TRDIOC0 pin)
FFFFh - TRD0 register setting value or below
Do not write to this register when the TSTART0 and TSTART1
bits in the TRDSTR register are set to 1 (count starts).
TRDGRB0 − General register. Set the changing point of PWM1 output at TRDIOB0
initialization. TRDIOD0
Setting range: Setting value or above in TRD0 register
TRDGRA0 register - TRD0 register setting
www.DataSheet4U.com value or below
TRDGRA1 − General register. Set the changing point of PWM2 output at TRDIOA1
initialization. TRDIOC1
value or below
TRDGRB1 − General register. Set the changing point of PWM3 output at TRDIOB1
initialization. TRDIOD1
value or below
TRDGRC0 − This register is not used in complementary PWM mode. −
TRDGRD0 BFD0 = 1 Buffer register. Set the changing point of next PWM1 output. TRDIOB0
(Refer to 14.3.2 Buffer Operation.) TRDIOD0
value or below
Set this register to the same value as the TRDGRB0 register
for initialization.
TRDGRC1 BFC1 = 1 Buffer register. Set the changing point of next PWM2 output. TRDIOA1
(Refer to 14.3.2 Buffer Operation.) TRDIOC1
value or below
Set this register to the same value as the TRDGRA1 register
for initialization.
TRDGRD1 BFD1 = 1 Buffer register. Set the changing point of next PWM3 output. TRDIOB1
(Refer to 14.3.2 Buffer Operation.) TRDIOD1
value or below
Set this register to the same value as the TRDGRB1 register
for initialization.
Since values cannot be written to the TRDGRB0, TRDGRA1, or TRDGRB1 register directly after count
operation starts (prohibited item), use the TRDGRD0, TRDGRC1, or TRDGRD1 register as a buffer register.
However, to write data to the TRDGRD0, TRDGRC1, or TRDGRD1 register, set bits BFD0, BFC1, and BFD1
to 0 (general register). After this, bits BFD0, BFC1, and BFD1 may be set to 1 (buffer register).
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Value in TRDGRA0 Value in TRD0 register

register
Value in TRDGRB0
register
Value in TRDGRA1
register
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Value in TRDGRB1
register
0000h
TRDIOB0 output
TRDIOD0 output
TRDIOA1 output
TRDIOC1 output
TRDIOB1 output
TRDIOD1 output
TRDIOC0 output
i = 0 or 1
Figure 14.95 Output Model of Complementary PWM Mode
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Count source
m+1
m
n
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0000h
Set to
FFFFh
Bits TSTART0 and TSTART1 1

in TRDSTR register 0
TRDIOB0 output
Active level “L”

TRDIOD0 output
TRDIOC0 output
m+2-p
n+1 m-p-n+1
n+1-p p p n+1-p
(m-p-n+1) × 2 Dead (n+1-p) × 2

Width of normal- time Width of counter-phase active level
phase active level
UDF bit in 1
TRDSR1 register 0
IMFA bit in 1 Set to 0 by a program

TRDSR0 register 0
TRDGRB0 register n n
Transfer (when bits CMD1 to CMD0 are set to 11b) Transfer (when bits CMD1 to CMD0
are set to 10b)
TRDGRD0 register n Following data
Modify with a program

IMFB bit in 1 Set to 0 by a program Set to 0 by a program
TRDSR0 register 0
CMD0, CMD1: Bits in TRDFCR register m: Value set in TRDGRA0 register

n: Value set in TRDGRB0 register
i = 0 or 1 p: Value set in TRD0 register

Bits OLS1 and OLS0 in TRDFCR are set to 0 (initial output level “H”, active level “L” for normal-phase and counter-phase)
Figure 14.96 Operating Example of Complementary PWM Mode
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14.3.9.1 Transfer Timing from Buffer Register

• Transfer from the TRDGRD0, TRDGRC1, or TRDGRD1 register to the TRDGRB0, TRDGRA1, or
TRDGRB1 register.
When bits CMD1 to CMD0 in the TRDFCR register are set to 10b, the content is transferred when the
TRD1 register underflows.
When bits CMD1 to CMD0 are set to 11b, the content is transferred at compare match between registers
TRD0 and TRDGRA0.
14.3.9.2 A/D Trigger Generation

Compare match between registers TRD0 and TRDGRA0 and TRD1 underflow can be used as the conversion
start trigger of the A/D converter. The trigger is selected by bits ADEG and ADTRG in the TRDFCR register.
www.DataSheet4U.com Also, set the ADCAP bit in the ADCON0 register to 1 (starts by timer RD).
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14.3.10 PWM3 Mode

In this mode, 2 PWM waveforms are output with the same period.
Figure 14.97 shows a Block Diagram of PWM3 Mode, and Table 14.33 lists the PWM3 Mode Specifications.
Figures 14.98 to 14.106 show the Registers Associated with PWM3 Mode, and Figure 14.107 shows an
Operating Example of PWM3 Mode.
Buffer
TRD0 Comparator TRDGRA0 TRDGRC0

www.DataSheet4U.com Output
TRDIOA0 Compare match signal
control
Comparator TRDGRA1 TRDGRC1
Comparator TRDGRB0 TRDGRD0
Output
TRDIOB0 Compare match signal
control
Comparator TRDGRB1 TRDGRD1
Figure 14.97 Block Diagram of PWM3 Mode
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Table 14.33 PWM3 Mode Specifications

Item Specification
Count operations The TRD0 register is incremented (the TRD1 is not used).
PWM waveform PWM period: 1/fk × (m+1)
Active level width of TRDIOA0 output: 1/fk × (m-n)
Active level width of TRDIOB0 output: 1/fk × (p-q)
www.DataSheet4U.com
n: Value set in the TRDGRA1 register
p: Value set in the TRDGRB0 register
q: Value set in the TRDGRB1 register
m+1
n+1
p+1
q+1
TRDIOA0 output
m-n
TRDIOB0 output
p-q
(When “H” is selected as the active level)
Count start condition 1 (count starts) is written to the TSTART0 bit in the TRDSTR register.
Count stop conditions • 0 (count stops) is written to the TSTART0 bit in the TRDSTR register
The PWM output pin holds output level before the count stops
• When the CSEL0 bit in the TRDSTR register is set to 0, the count
stops at the compare match with the TRDGRA0 register.
The PWM output pin holds level after output change by compare
match.
Interrupt request generation • Compare match (The content of the TRDi register matches content
timing of the TRDGRji register.)
• The TRD0 register overflows
TRDIOA0, TRDIOB0 pin PWM output
functions
TRDIOC0, TRDIOD0, TRDIOA1 Programmable I/O port
to TRDIOD1 pin functions
INT0 pin function Programmable I/O port, pulse output forced cutoff signal input, or
INT0 interrupt input
Read from timer The count value can be read by reading the TRD0 register.
Write to timer The value can be written to the TRD0 register.
Select functions • Pulse output forced cutoff signal input (Refer to 14.3.4 Pulse
Output Forced Cutoff.)
• Buffer Operation (Refer to 14.3.2 Buffer Operation.)
• Active level selectable by pin
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b7 b6 b5 b4 b3 b2 b1 b0

TRDSTR 0137h 11111100b
TSTART0 RW
1 : Count starts
TSTART1 RW
1 : Count starts
www.DataSheet4U.com
[this bit is not used in PWM3 mode] the TRDGRA1 register
—
NOTES:
stops).
stops).

b7 b6 b5 b4 b3 b2 b1 b0

TRDMR 0138h 00001110b
Timer RD synchronous bit Set this bit to 0 (TRD0 and TRD1 operate
SYNC RW
independently) in PWM3 mode.
—
BFC0 RW
BFD0 RW
BFC1 RW
BFD1 RW
Figure 14.98 Registers TRDSTR and TRDMR in PWM3 Mode
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b7 b6 b5 b4 b3 b2 b1 b0

CMD0 RW
PWM3 mode) in PWM3 mode.
CMD1 RW
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Normal-phase output level select bit This bit is disabled in PWM3 mode.
(enabled in reset synchronous PWM
OLS0 mode or complementary PWM mode) RW
Counter-phase output level select bit This bit is disabled in PWM3 mode.
(enabled in reset synchronous PWM
OLS1 mode or complementary PWM mode) RW
A/D trigger enable bit This bit is disabled in PWM3 mode.

ADTRG (enabled in complementary PWM mode) RW
A/D trigger edge select bit This bit is disabled in PWM3 mode.
ADEG (enabled in complementary PWM mode) RW
External clock input select bit Set this bit to 0 (external clock input
STCLK RW
disabled) in PWM3 mode.
PWM3 mode select bit(2) Set this bit to 0 (PWM3 mode) in PWM3
PWM3 RW
mode.
NOTES:
enabled.
Figure 14.99 TRDFCR Register in PWM3 Mode
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b7 b6 b5 b4 b3 b2 b1 b0

TRDOER1 013Bh FFh
EB0 RW
EC0 TRDIOC0 output disable bit Set these bits to 1 (programmable I/O port) RW
ED0 TRDIOD0 output disable bit in PWM3 mode. RW
EA1 TRDIOA1 output disable bit RW
EB1 TRDIOB1 output disable bit RW
EC1 TRDIOC1 output disable bit RW
ED1 TRDIOD1 output disable bit RW

b7 b6 b5 b4 b3 b2 b1 b0

TRDOER2 013Ch 01111111b
—
_____
cutoff signal input enabled 1 : Pulse output forced cutoff input enabled
bit(1) (All bits in the TRDOER1 register
PTO RW
_____
NOTE:
Figure 14.100 Registers TRDOER1 to TRDOER2 in PWM3 Mode
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Timer RD Output Control Register(1)

b7 b6 b5 b4 b3 b2 b1 b0

TRDOCR 013Dh 00h
TRDIOA0 output level select 0 : Active level “H”,
bit(2) initial output “L”,
output “H” at compare match w ith the
TRDGRA1register,
www.DataSheet4U.com output “L” at compare match w ith the
TRDGRA0 register
TOA0 1 : Active level “L”, RW
initial output “H”,
output “L” at compare match w ith the
TRDGRA1register,
TRDGRA0 register
TRDIOB0 output level select 0 : Active level “H”,

bit(2) initial output “L”,
TRDGRB1register,
TRDGRB0 register
TOB0 1 : Active level “L”, RW
initial output “H”,
TRDGRB1register,
TRDGRB0 register
TRDIOC0 initial output level These bits are disabled in PWM3 mode.
TOC0 RW
select bit
TRDIOD0 initial output level
TOD0 RW
select bit
TRDIOA1 initial output level
TOA1 RW
select bit
TRDIOB1 initial output level
TOB1 RW
select bit
TRDIOC1 initial output level
TOC1 RW
select bit
TRDIOD1 initial output level
TOD1 RW
select bit
NOTES:
1. Write to the TRDOCR register w hen both bits TSTART0 and TSTART1 in the TRDSTR register are set to 0 (count
2. If the pin function is set for w aveform output (refer to Tables 14.12 and 14.13), the initial output level is output w hen
the TRDOCR register is set.
Figure 14.101 TRDOCR Register in PWM3 Mode
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Timer RD Control Register 0(2)

b7 b6 b5 b4 b3 b2 b1 b0

TRDCR0 0140h 00h
Count source select bits b2 b1b0
TCK0 0 0 0 : f1 RW
0 0 1 : f2
0 1 0 : f4
TCK1 RW
1 0 0 : f32
1 0 1 : Do not set.
1 1 0 : fOCO40M
TCK2 RW
1 1 1 : Do not set.
CKEG0 External clock edge select bits (1) These bits are disabled in PWM3 mode. RW
CKEG1 RW
CCLR0 TRD0 counter clear select bits Set to 001b (the TRD0 register cleared at RW
CCLR1 compare match w ith TRDGRA0 register) in RW
CCLR2 PWM3 mode. RW
NOTES:
2. The TRDCR1 register is not used in PWM3 mode.
Figure 14.102 TRDCR0 Register in PWM3 Mode
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b7 b6 b5 b4 b3 b2 b1 b0

TRDSR0 0143h 11100000b
TRDSR1 0153h 11000000b
Input capture/compare match flag A [Source for setting this bit to 0]
www.DataSheet4U.com IMFA When the value in the TRDi register RW
matches w ith the value in the TRDGRAi
register.
Input capture/compare match flag B [Source for setting this bit to 0]

IMFB When the value in the TRDi register RW
matches w ith the value in the TRDGRBi
register.
Input capture/compare match flag C [Source for setting this bit to 0]

IMFC When the value in the TRDi register RW
matches w ith the value in the TRDGRCi
register (2).
Input capture/compare match flag D [Source for setting this bit to 0]

IMFD When the value in the TRDi register RW
matches w ith the value in the TRDGRDi
register (2).

Underflow flag(1) This bit is disabled in PWM3 mode.
UDF RW

—
NOTES:
2. Including w hen the BFji (j = C or D) bit in the TRDMR register is set to 1 (TRDGRji is used as the buffer register).
Figure 14.103 Registers TRDSR0 to TRDSR1 in PWM3 Mode
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b7 b6 b5 b4 b3 b2 b1 b0

TRDIER0 0144h 11100000b
TRDIER1 0154h 11100000b
IMFB bit
IMFC bit
IMFD bit
bit OVF bit
OVF bit
—
Figure 14.104 Registers TRDIER0 to TRDIER1 in PWM3 Mode
Timer RD Counter 0(1, 2)

(b15) (b8)
b7 b0 b7 b0

TRD0 0147h-0146h 0000h
NOTES:
2. The TRD1 register is not used in PWM3 mode.
Figure 14.105 TRD0 Register in PWM3 Mode
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(b15) (b8)
b7 b0 b7 b0

www.DataSheet4U.com
Function RW
Refer to Table 14.34 TRDGRji Register Functions in PWM3 Mode.
RW
NOTE:
Figure 14.106 Registers TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi in PWM3 Mode
The following registers are disabled in the PWM3 mode function: TRDPMR, TRDDF0, TRDDF1,
TRDIORA0, TRDIORC0, TRDPOCR0, TRDIORA1, TRDIORC1, and TRDPOCR1.
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Table 14.34 TRDGRji Register Functions in PWM3 Mode

TRDGRA0 − General register. Set the PWM period. TRDIOA0
Setting range: Value set in TRDGRA1 register or above
TRDGRA1 General register. Set the changing point (the active level
timing) of PWM output.
Setting range: Value set in TRDGRA0 register or below
TRDGRB0 General register. Set the changing point (the timing that TRDIOB0
returns to initial output level) of PWM output.
Setting range: Value set in TRDGRB1 register or above
www.DataSheet4U.com Value set in TRDGRA0 register or below
TRDGRB1 General register. Set the changing point (active level timing) of
PWM output.
Setting range: Value set in TRDGRB0 register or below
TRDGRC0 BFC0 = 0 (These registers is not used in PWM3 mode.) −
TRDGRC1 BFC1 = 0
TRDGRD0 BFD0 = 0
TRDGRD1 BFD1 = 0
TRDGRC0 BFC0 = 1 Buffer register. Set the next PWM period. TRDIOA0
Setting range: Value set in TRDGRC1 register or above
TRDGRC1 BFC1 = 1 Buffer register. Set the changing point of next PWM output.
Setting range: Value set in TRDGRC0 register or below
TRDGRD0 BFD0 = 1 Buffer register. Set the changing point of next PWM output. TRDIOB0
Setting range: Value set in TRDGRD1 register or above,
setting value or below in TRDGRC0 register.
TRDGRD1 BFD1 = 1 Buffer register. Set the changing point of next PWM output.
Setting range: Value set in TRDGRD0 register or below
Registers TRDGRC0, TRDGRC1, TRDGRD0, and TRDGRD1 are not used in PWM3 mode. To use them as
buffer registers, set bits BFC0, BFC1, BFD0, and BFD1 to 0 (general register) and write a value to the
TRDGRC0, TRDGRC1, TRDGRD0, or TRDGRD1 register. After this, bits BFC0, BFC1, BFD0, and BFD1
may be set to 1 (buffer register).
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Count source
FFFFh
m
www.DataSheet4U.com
q
0000h
TSTART0 bit in 1
TRDSTR register 0
Count stop
CSEL0 bit in 1
TRDSTR register 0
m+1
n+1 m-n
p+1
q+1 p-q
Output “H” at compare

match with the
TRDIOA0 output TRDGRA1 register
Output “L” at compare match

Initial output “L” with the TRDGRA0 register
TRDIOB0 output
IMFA bit in 1
TRDSR0 register 0
IMFB bit in 1
TRDSR0 register 0
TRDGRA0 register m m
Transfer Transfer
TRDGRC0 register m Following data
Transfer from buffer register to Transfer from buffer register to

general register general register

n: Value set in TRDGRA1 register
p: Value set in TRDGRB0 register
j = either A or B q: Value set in TRDGRB1 register

• Both the TOA0 and TOB0 bits in the TRDOCR register are set to 0 (initial output level “L”, output “H” by compare match with the
TRDGRj1 register, output “L” at compare match with the TRDGRj0 register).
• The BFC0 bit in the TRDMR register is set to 1 (the TRDGRC0 register is used as the buffer register of the TRDGRA0 register).
Figure 14.107 Operating Example of PWM3 Mode
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14.3.11 Timer RD Interrupt

Timer RD generates the timer RD interrupt request based on 6 sources for each channel. The timer RD interrupt
has 1 TRDiIC register (bits IR, and ILVL0 to ILVL2), and 1 vector for each channel.
Table 14.35 lists the Registers Associated with Timer RD Interrupt, and Figure 14.108 shows a Block Diagram
of Timer RD Interrupt.
Table 14.35 Registers Associated with Timer RD Interrupt

Timer RD Timer RD Timer RD
Status Register Interrupt Enable Register Interrupt Control Register
www.DataSheet4U.com
Channel i
IMFA bit
Timer RD interrupt request
IMIEA bit
(IR bit in TRDiIC register)
IMFB bit
IMIEB bit
IMFC bit
IMIEC bit
IMFD bit
IMIED bit
UDF bit
OVF bit
OVIE bit
i = 0 or 1
IMFA, IMFB, IMFC, IMFD, OVF, UDF: Bits in TRDSRi register
IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRDIER register
Figure 14.108 Block Diagram of Timer RD Interrupt
As with other maskable interrupts, the timer RD interrupt is controlled by the combination of the I flag, IR bit,
bits ILVL0 to ILVL2, and IPL. However, since the interrupt source (timer RD interrupt) is generated by a
combination of multiple interrupt request sources, the following differences from other maskable interrupts
apply:
• When bits in the TRDSRi register corresponding to bits set to 1 in the TRDIERi register are set to 1 (enable
interrupt), the IR bit in the TRDiIC register is set to 1 (interrupt requested).
• When either bits in the TRDSRi register or bits in the TRDIERi register corresponding to bits in the
TRDSRi register, or both of them, are set to 0, the IR bit is set to 0 (interrupt not requested). Therefore,
even though the interrupt is not acknowledged after the IR bit is set to 1, the interrupt request will not be
maintained.
• When the conditions of other request sources are met, the IR bit remains 1.
• When multiple bits in the TRDIERi register are set to 1, which request source causes an interrupt is
determined by the TRDSRi register.
• Since each bit in the TRDSRi register is not automatically set to 0 even if the interrupt is acknowledged, set
each bit to 0 in the interrupt routine. For information on how to set these bits to 0, refer to the descriptions
of the registers used in the different modes (Figures 14.40, 14.55, 14.68, 14.80, 14.91, and 14.103).
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Refer to Registers TRDSR0 to TRDSR1 in each mode (Figures 14.40, 14.55, 14.68, 14.80, 14.91, and
14.103) for the TRDSRi register. Refer to Registers TRDIER0 to TRDIER1 in each mode (Figures 14.41,
14.56, 14.69, 14.81, 14.92, and 14.104) for the TRDIERi register.
Refer to 12.1.6 Interrupt Control for information on the TRDiIC register and 12.1.5.2 Relocatable Vector
Tables for the interrupt vectors.
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14.3.12 Notes on Timer RD
14.3.12.1 TRDSTR Register

• Set the TRDSTR register using the MOV instruction.
• When the CSELi (i = 0 to 1) is set to 0 (the count stops at compare match of registers TRDi and
TRDGRAi), the count does not stop and the TSTARTi bit remains unchanged even if 0 (count stops) is
written to the TSTARTi bit.
• Therefore, set the TSTARTi bit to 0 to change other bits without changing the TSTARTi bit when the
CSELi bit is se to 0.
• To stop counting by a program, set the TSTARTi bit after setting the CSELi bit to 1. Although the CSELi
www.DataSheet4U.com bit is set to 1 and the TSTARTi bit is set to 0 at the same time (with 1 instruction), the count cannot be
stopped.
• Table 14.36 lists the TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops to use the TRDIOji
(j = A, B, C, or D) pin with the timer RD output.
Table 14.36 TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops

Count Stop TRDIOji Pin Output when Count Stops
When the CSELi bit is set to 1, set the TSTARTi bit to 0 and the count Hold the output level immediately before the
stops. count stops.
When the CSELi bit is set to 0, the count stops at compare match of Hold the output level after output changes by
registers TRDi and TRDGRAi. compare match.
14.3.12.2 TRDi Register (i = 0 or 1)

• When writing the value to the TRDi register by a program while the TSTARTi bit in the TRDSTR register
is set to 1 (count starts), avoid overlapping with the timing for setting the TRDi register to 0000h, and then
write. If the timing for setting the TRDi register to 0000h overlaps with the timing for writing the value to
the TRDi register, the value is not written and the TRDi register is set to 0000h.
These precautions are applicable when selecting the following by bits CCLR2 to CCLR0 in the
TRDCRi register.
- 001b (Clear by the TRDi register at compare match with the TRDGRAi register.)
- 010b (Clear by the TRDi register at compare match with the TRDGRBi register.)
- 011b (Synchronous clear)
- 101b (Clear by the TRDi register at compare match with the TRDGRCi register.)
- 110b (Clear by the TRDi register at compare match with the TRDGRDi register.)
• When writing the value to the TRDi register and continuously reading the same register, the value before
writing may be read. In this case, execute the JMP.B instruction between the writing and reading.
Program example MOV.W #XXXXh, TRD0 ;Writing
JMP.B L1 ;JMP.B
L1: MOV.W TRD0,DATA ;Reading
14.3.12.3 TRDSRi Register (i = 0 or 1)

When writing the value to the TRDSRi register and continuously reading the same register, the value before
Program example MOV.B #XXh, TRDSR0 ;Writing
JMP.B L1 ;JMP.B
L1: MOV.B TRDSR0,DATA ;Reading
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14.3.12.4 Count Source Switch

• Switch the count source after the count stops.
Change procedure
(1) Set the TSTARTi (i = 0 or 1) bit in the TRDSTR register to 0 (count stops).
(2) Change bits TCK2 to TCK0 in the TRDCRi register.
• When changing the count source from fOCO40M to another source and stopping fOCO40M, wait 2 cycles
of f1 or more after setting the clock switch, and then stop fOCO40M.
Change procedure
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(3) Wait 2 or more cycles of f1.
(4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator stops).
14.3.12.5 Input Capture Function

• Set the pulse width of the input capture signal to 3 or more cycles of the timer RD operation clock (refer to
Table 14.11 Timer RD Operation Clocks).
• The value in the TRDi register is transferred to the TRDGRji register 2 to 3 cycles of the timer RD
operation clock after the input capture signal is applied to the TRDIOji pin (i = 0 or 1, j = either A, B, C, or
D) (no digital filter).
14.3.12.6 Reset Synchronous PWM Mode

• When reset synchronous PWM mode is used for motor control, make sure OLS0 = OLS1.
• Set to reset synchronous PWM mode by the following procedure:
Change procedure
(1) Set the TSTART0 bit in the TRDSTR register to 0 (count stops).
(2) Set bits CMD1 to CMD0 in the TRDFCR register to 00b (timer mode, PWM mode, and PWM3 mode).
(3) Set bits CMD1 to CMD0 to 01b (reset synchronous PWM mode).
(4) Set the other registers associated with timer RD again.
14.3.12.7 Complementary PWM Mode

• When complementary PWM mode is used for motor control, make sure OLS0 = OLS1.
• Change bits CMD1 to CMD0 in the TRDFCR register in the following procedure.
Change procedure: When setting to complementary PWM mode (including re-set), or changing the transfer
timing from the buffer register to the general register in complementary PWM mode.
(1) Set both the TSTART0 and TSTART1 bits in the TRDSTR register to 0 (count stops).
(3) Set bits CMD1 to CMD0 to 10b or 11b (complementary PWM mode).
(4) Set the registers associated with other timer RD again.
Change procedure: When stopping complementary PWM mode

(2) Set bits CMD1 to CMD to 00b (timer mode, PWM mode, and PWM3 mode).
• Do not write to TRDGRA0, TRDGRB0, TRDGRA1, or TRDGRB1 register during operation.

When changing the PWM waveform, transfer the values written to registers TRDGRD0, TRDGRC1, and
TRDGRD1 to registers TRDGRB0, TRDGRA1, and TRDGRB1 using the buffer operation.
However, to write data to the TRDGRD0, TRDGRC1, or TRDGRD1 register, set bits BFD0, BFC1, and
BFD1 to 0 (general register). After this, bits BFD0, BFC1, and BFD1 may be set to 1 (buffer register).
The PWM period cannot be changed.
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REJ09B0244-0300
• If the value in the TRDGRA0 register is assumed to be m, the TRD0 register counts m-1, m, m+1, m, m-1,
in that order, when changing from increment to decrement operation.
When changing from m to m+1, the IMFA bit is set to 1. Also, bits CMD1 to CMD0 in the TRDFCR
register are set to 11b (complementary PWM mode, buffer data transferred at compare match between
registers TRD0 and TRDGRA0), the content in the buffer registers (TRDGRD0, TRDGRC1, and
TRDGRD1) is transferred to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1).
During m+1, m, and m-1 operation, the IMFA bit remains unchanged and data are not transferred to
registers such as the TRDGRA0 register.
Count value in TRD0

www.DataSheet4U.com register
m+1
Setting value in
TRDGRA0
register m
1 No change
IMFA bit in
TRDSR0 register 0
Transferred from
Not transferred from buffer register
buffer register
When bits CMD1 to CMD0 in the
TRDGRB0 register
TRDFCR register are set to 11b
TRDGRA1 register
(transfer from the buffer register to the
TRDGRB1 register
general register at compare match of
between registers TRD0 and
TRDGRA0).
Figure 14.109 Operation at Compare Match between Registers TRD0 and TRDGRA0 in
Complementary PWM Mode
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• The TRD1 register counts 1, 0, FFFFh, 0, 1, in that order, when changing from decrement to increment
operation.
The UDF bit is set to 1 when changing between 1, 0, and FFFFh operation. Also, when bits CMD1 to
CMD0 in the TRDFCR register are set to 10b (complementary PWM mode, buffer data transferred at
underflow in the TRD1 register), the content in the buffer registers (TRDGRD0, TRDGRC1, and
TRDGRD1) is transferred to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1). During
FFFFh, 0, 1 operation, data are not transferred to registers such as the TRDGRB0 register. Also, at this
time, the OVF bit remains unchanged.
Count value in TRD0

www.DataSheet4U.com
register
FFFFh
UDF bit in 1
TRDSR0 register 0
1 No change
OVF bit in
TRDSR0 register 0
Transferred from Not transferred from buffer register

buffer register
TRDGRB0 register TRDFCR register are set to 10b
TRDGRA1 register (transfer from the buffer register to the
TRDGRB1 register general register when the TRD1 register
underflows).
Figure 14.110 Operation when TRD1 Register Underflows in Complementary PWM Mode
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REJ09B0244-0300
• Select with bits CMD1 to CMD0 the timing of data transfer from the buffer register to the general register.
However, transfer takes place with the following timing in spite of the value of bits CMD1 to CMD0 in the
following cases:
Value in buffer register ≥ value in TRDGRA0 register:

Transfer take place at underflow of the TRD1 register.
After this, when the buffer register is set to 0001h or above and a smaller value than the value of the
TRDGRA0 register, and the TRD1 register underflows for the first time after setting, the value is
transferred to the general register. After that, the value is transferred with the timing selected by bits CMD1
to CMD0.
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n3
m+1
Count value in TRD0
n2 register
n1
Count value in TRD1
0000h register
TRDGRD0 register n2 n3 n2 n1
Transfer Transfer Transfer

Transfer
TRDGRB0 register n1 n2 n3 n2 n1
Transfer with timing set by Transfer at Transfer at Transfer with timing set by
bits CMD1 to CMD0 underflow of TRD1 underflow of TRD1 bits CMD1 to CMD0
register because of register because
n3 > m of first setting to
n2 < m
TRDIOB0 output
TRDIOD0 output

• Bits CMD1 to CMD0 in the TRDFCR register are set to 11b (data in the buffer register is transferred at compare match
between registers TRD0 and TRDGRA0 in complementary PWM mode).
• Both the OSL0 and OLS1 bits in the TRDFCR register are set to 1 (active ‘H” for normal-phase and counter-phase).
Figure 14.111 Operation when Value in Buffer Register ≥ Value in TRDGRA0 Register in
Rev.3.00 Feb 29, 2008 Page 268 of 485

REJ09B0244-0300
When the value in the buffer register is set to 0000h:

Transfer takes place at compare match between registers TRD0 and TRDGRA0.
TRDGRA0 register, and a compare match occurs between registers TRD0 and TRDGRA0 for the first time
after setting, the value is transferred to the general register. After that, the value is transferred with the
timing selected by bits CMD1 to CMD0.
m+1
n2 Count value in TRD0 register
n1
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Count value in TRD1 register
0000h
TRDGRD0 register n1 0000h n1
Transfer Transfer Transfer Transfer
TRDGRB0 register n2 n1 0000h n1
Transfer at compare Transfer at compare

Transfer with timing Transfer with timing
match between match between
set by bits CMD1 to set by bits CMD1 to
registers TRD0 and registers TRD0 and
CMD0 TRDGRA0 because TRDGRA0 because CMD0
content in of first setting to
TRDGRD0 register 0001h ≤ n1 < m
is set to 0000h
TRDIOB0 output
TRDIOD0 output

• Bits CMD1 to CMD0 in the TRDFCR register are set to 10b (data in the buffer register is transferred at underflow of the TRD1 register in
PWM mode).
• Both the OLS0 and OLS1 bits in the TRDFCR register are set to 1 (active “H” for normal-phase and counter-phase).
Figure 14.112 Operation when Value in Buffer Register Is Set to 0000h in Complementary PWM
Mode
14.3.12.8 Count Source fOCO40M

• The count source fOCO40M can be used with supply voltage VCC = 3.0 to 5.5 V. For supply voltage other
than that, do not set bits TCK2 to TCK0 in registers TRDCR0 and TRDCR to 110b (select fOCO40M as
the count source).
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REJ09B0244-0300
14.4 Timer RE
Timer RE has the 4-bit counter and 8-bit counter. Timer RE has the following 2 modes:
• Real-time clock mode Generate 1-second signal from fC4 and count seconds, minutes, hours, and days of
the week.
• Output compare mode Count a count source and detect compare matches.
The count source for timer RE is the operating clock that regulates the timing of timer operations.
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REJ09B0244-0300
14.4.1 Real-Time Clock Mode

In real-time clock mode, a 1-second signal is generated from fC4 using a divide-by-2 frequency divider, 4-bit
counter, and 8-bit counter and used to count seconds, minutes, hours, and days of the week. Figure 14.113
shows a Block Diagram of Real-Time Clock Mode and Table 14.37 lists the Real-Time Clock Mode
Specifications. Figures 14.114 to 14.118, and Figures 14.120 and 14.121 show the Registers Associated with
Real-Time Clock Mode. Table 14.38 lists the Interrupt Sources, Figure 14.119 shows the Definition of Time
Representation and Figure 14.122 shows the Operating Example in Real-Time Clock Mode.
(1/16) (1/256)
www.DataSheet4U.com (1s)
fC4 1/2 4-bit counter 8-bit counter Overflow
Data bus
Overflow Overflow Overflow

TRESEC TREMIN TREHR TREWK
register register register register
000
H12_H24 PM WKIE
bit bit
Timing Timer RE
DYIE control interrupt
HRIE
INT
MNIE bit
SEIE
BSY
bit
H12_H24, PM, INT: Bits in TRECR1 register

BSY: Bit in registers TRESEC, TREMIN, TREHR, and TREWK
Figure 14.113 Block Diagram of Real-Time Clock Mode
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REJ09B0244-0300
Table 14.37 Real-Time Clock Mode Specifications

Item Specification
Count source fC4
Count operation Increment
Count start condition 1 (count starts) is written to TSTART bit in TRECR1 register
Count stop condition 0 (count stops) is written to TSTART bit in TRECR1 register
Interrupt request generation Select any one of the following:
timing • Update second data
• Update minute data
www.DataSheet4U.com • Update hour data
• Update day of week data
• When day of week data is set to 000b (Sunday)
TREO pin function Programmable I/O ports or output of f2, f4, or f8
Read from timer When reading TRESEC, TREMIN, TREHR, or TREWK register, the count
value can be read. The values read from registers TRESEC, TREMIN,
and TREHR are represented by the BCD code.
Write to timer When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer
stops), the value can be written to registers TRESEC, TREMIN, TREHR,
and TREWK. The values written to registers TRESEC, TREMIN, and
TREHR are represented by the BCD codes.
Select function • 12-hour mode/24-hour mode switch function
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REJ09B0244-0300
Timer RE Second Data Register

b7 b6 b5 b4 b3 b2 b1 b0

TRESEC 0118h 00h
Setting
Range
SC00 1st digit of second count bits Count 0 to 9 every second. When the 0 to 9 RW
SC01 digit moves up, 1 is added to the 2nd (BCD RW
SC02 digit of second. code) RW
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SC03 RW
SC10 2nd digit of second count bits When counting 0 to 5, 60 seconds 0 to 5 RW
SC11 are counted. (BCD RW
SC12 code) RW
Timer RE busy flag This bit is set to 1 w hile registers TRESEC,
TREMIN, TREHR, and TREWK are updated.
BSY RO
Figure 14.114 TRESEC Register in Real-Time Clock Mode
Timer RE Minute Data Register

b7 b6 b5 b4 b3 b2 b1 b0

TREMIN 0119h 00h
Setting
Range
MN00 1st digit of minute count bits Count 0 to 9 every minute. When the 0 to 9 RW
MN01 digit moves up, 1 is added to the 2nd (BCD RW
MN02 digit of minute. code) RW
MN03 RW
MN10 2nd digit of minute count bits When counting 0 to 5, 60 minutes are 0 to 5 RW
MN11 counted. (BCD RW
MN12 code) RW
TREMIN, TREHR, and TREWK are updated.
BSY RO
Figure 14.115 TREMIN Register in Real-Time Clock Mode
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REJ09B0244-0300
Timer RE Hour Data Register

b7 b6 b5 b4 b3 b2 b1 b0

TREHR 011Ah 00h
Setting
Range
HR00 1st digit of hour count bits Count 0 to 9 every hour. When the 0 to 9 RW
HR01 digit moves up, 1 is added to the 2nd (BCD RW
HR02 digit of hour. code) RW
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HR03 RW
2nd digit of hour count bits Count 0 to 1 w hen the H12_H24 bit is 0 to 2
HR10 RW
set to 0 (12-hour mode). (BCD
Count 0 to 2 w hen the H12_H24 bit is code)
HR11 set to 1 (24-hour mode). RW

—
BSY TREMIN, TREHR, and TREWK are updated. RO
Figure 14.116 TREHR Register in Real-Time Clock Mode
Timer RE Day of Week Data Register

b7 b6 b5 b4 b3 b2 b1 b0

TREWK 011Bh 00h
Day of w eek count bits b2 b1 b0
WK0 0 0 0 : Sunday RW
0 0 1 : Monday
0 1 0 : Tuesday
0 1 1 : Wednesday
WK1 RW
1 0 0 : Thursday
1 0 1 : Friday
1 1 0 : Saturday
WK2 1 1 1 : Do not set. RW

—
BSY TREMIN, TREHR, and TREWK are updated. RO
Figure 14.117 TREWK Register in Real-Time Clock Mode
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REJ09B0244-0300
Timer RE Control Register 1

b7 b6 b5 b4 b3 b2 b1 b0

TRECR1 011Ch 00h
—
Timer RE count status flag 0 : Count stopped
TCSTF RO
1 : Counting
www.DataSheet4U.com TREO pin output enable bit 0 : Disable clock output

TOENA RW
1 : Enable clock output
Interrupt request timing bit Set to 1 in real-time clock mode.
INT RW
Timer RE reset bit When setting this bit to 0, after setting it to 1, the
follow ings w ill occur.
• Registers TRESEC, TREMIN, TREHR, TREWK,
and TRECR2 are set to 00h.
TRERST • Bits TCSTF, INT, PM, H12_H24, and TSTART RW
in the TRECR1 register are set to 0.
• The 8-bit counter is set to 00h and
the 4-bit counter is set to 0h.
A.m./p.m. bit When the H12_H24 bit is set to 0

(12-hour mode)(1)
0 : a.m.
PM 1 : p.m. RW
When the H12_H24 bit is set to 1 (24-hour
mode), its value is undefined.
Operating mode select bit 0 : 12-hour mode

H12_H24 RW
1 : 24-hour mode
Timer RE count start bit 0 : Count stops
TSTART RW
1 : Count starts
NOTE:
1. This bit is automatically modified w hile timer RE counts.
Figure 14.118 TRECR1 Register in Real-Time Clock Mode
Noon
H12_H24 bit = 1
(24-hour mode)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Contents of
TREHR Register H12_H24 bit = 0
(12-hour mode)
0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5
Contents of PM bit 0 (a.m.) 1 (p.m.)

Contents in TREWK register 000 (Sunday)
Date changes
H12_H24 bit = 1
(24-hour mode)
18 19 20 21 22 23 0 1 2 3 ⋅⋅⋅
Contents of
TREHR Register H12_H24 bit = 0
(12-hour mode)
6 7 8 9 10 11 0 1 2 3 ⋅⋅⋅
Contents of PM bit 1 (p.m.) 0 (a.m.) ⋅⋅⋅

Contents in TREWK register 000 (Sunday) 001 (Monday) ⋅⋅⋅
PM bit and H12_H24 bits: Bits in TRECR1 register

The above applies to the case when count starts from a.m. 0 on Sunday.
Figure 14.119 Definition of Time Representation
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REJ09B0244-0300

b7 b6 b5 b4 b3 b2 b1 b0

TRECR2 011Dh 00h
Periodic interrupt triggered every 0 : Disable periodic interrupt triggered
second enable bit(1) every second
SEIE 1 : Enable periodic interrupt triggered RW
every second
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minute enable bit(1) every minute
MNIE 1 : Enable periodic interrupt triggered RW
every minute
hour enable bit(1) every hour
HRIE 1 : Enable periodic interrupt triggered RW
every hour
Periodic interrupt triggered every day 0 : Disable periodic interrupt triggered
enable bit(1) every day
DYIE 1 : Enable periodic interrupt triggered RW
every day
w eek enable bit(1) every w eek
WKIE 1 : Enable periodic interrupt triggered RW
every w eek
Compare match interrupt enable bit Set to 0 in real-time clock mode.
COMIE RW

—
NOTE:
1. Do not set multiple enable bits to 1 (enable interrupt).
Figure 14.120 TRECR2 Register in Real-Time Clock Mode
Table 14.38 Interrupt Sources

Factor Interrupt Source Interrupt Enable Bit
Periodic interrupt Value in TREWK register is set to 000b (Sunday) WKIE
triggered every week (1-week period)
Periodic interrupt TREWK register is updated (1-day period) DYIE
triggered every day
Periodic interrupt TREHR register is updated (1-hour period) HRIE
triggered every hour
Periodic interrupt TREMIN register is updated (1-minute period) MNIE
triggered every minute
Periodic interrupt TRESEC register is updated (1-second period) SEIE
triggered every second
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REJ09B0244-0300
Timer RE Count Source Select Register

b7 b6 b5 b4 b3 b2 b1 b0

TRECSR 011Eh 00001000b
Count source select bits Set to 00b in real-time clock mode.
RCS0 RW
RCS1 RW
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4-bit counter select bit Set to 0 in real-time clock mode.
RCS2 RW
Real-time clock mode select bit Set to 1 in real-time clock mode.

RCS3 RW

—
Clock output select bits (1) b6 b5
RCS5 0 0 : f2 RW
0 1 : f4
1 0 : f8
1 1 : Do not set.
RCS6 RW

—
NOTE:
1. Write to bits RCS5 to RCS6 w hen the TOENA bit in the TRECR1 register is set to 0 (disable clock output).
Figure 14.121 TRECSR Register in Real-Time Clock Mode
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REJ09B0244-0300
1s
Approx. Approx.
62.5 ms 62.5 ms
BSY bit
Bits SC12 to SC00 in

58 59 00
TRESEC register
Bits MN12 to MN00 in

TREMIN register 03 04
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Bits HR11 to HR00 in

(Not changed)
TREHR register
1
PM bit in
(Not changed)
TRECR1 register
0
Bits WK2 to WK0 in (Not changed)

TREWK register
Set to 0 by acknowledgement
of interrupt request
1 or a program
IR bit in TREIC register
(when SEIE bit in TRECR2 register is set
to 1 (enable periodic interrupt triggered 0
every second))
IR bit in TREIC register 1

(when MNIE bit in TRECR2 register is set
to 1 (enable periodic interrupt triggered 0
every minute))
BSY: Bit in registers TRESEC, TREMIN, TREHR, and TREWK
Figure 14.122 Operating Example in Real-Time Clock Mode
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REJ09B0244-0300
14.4.2 Output Compare Mode

In output compare mode, the internal count source divided by 2 is counted using the 4-bit or 8-bit counter and
compare value match is detected with the 8-bit counter. Figure 14.123 shows a Block Diagram of Output
Compare Mode, and Table 14.39 lists the Output Compare Mode Specifications. Figures 14.124 to 14.128 show
the Registers Associated with Output Compare Mode, and Figure 14.129 shows the Operating Example in
Output Compare Mode.
f4
RCS6 to RCS5
f8
= 00b TOENA bit
RCS1 to RCS0 f2
= 00b = 01b
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= 10b TREO pin
= 01b RCS2 = 1
4-bit
= 10b 1/2 = 11b
f32 counter 8-bit T Q
= 11b counter
fC4 R
RCS2 = 0 Reset
TRERST bit
Match
Comparison signal
circuit Timer RE interrupt
COMIE bit
TRERST, TOENA: Bits in TRECR1 register TRESEC TREMIN

COMIE: Bit in TRECR2 register
RCS0 to RCS2, RCS5 to RCS6: Bits in TRECSR register
Data bus
Figure 14.123 Block Diagram of Output Compare Mode
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REJ09B0244-0300
Table 14.39 Output Compare Mode Specifications

Item Specification
Count sources f4, f8, f32, fC4
Count operations • Increment
• When the 8-bit counter content matches with the TREMIN register
content, the value returns to 00h and count continues. The count value
is held while count stops.
Count period • When RCS2 = 0 (4-bit counter is not used)
1/fi x 2 x (n+1)
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• When RCS2 = 1 (4-bit counter is used)
1/fi x 32 x (n+1)
fi: Frequency of count source
n: Setting value of TREMIN register
Count start condition 1 (count starts) is written to the TSTART bit in the TRECR1 register
Count stop condition 0 (count stops) is written to the TSTART bit in the TRECR1 register
Interrupt request generation When the 8-bit counter content matches with the TREMIN register content
timing
TREO pin function Select any one of the following:
• Programmable I/O ports
• Output f2, f4, or f8
• Compare output
Read from timer When reading the TRESEC register, the 8-bit counter value can be read.
When reading the TREMIN register, the compare value can be read.
Write to timer Writing to the TRESEC register is disabled.
When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer
stops), writing to the TREMIN register is enabled.
Select functions • Select use of 4-bit counter
• Compare output function
Every time the 8-bit counter value matches the TREMIN register value,
TREO output polarity is reversed. The TREO pin outputs “L” after reset
is deasserted and the timer RE is reset by the TRERST bit in the
TRECR1 register. Output level is held by setting the TSTART bit to 0
(count stops).
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REJ09B0244-0300
Timer RE Counter Data Register

b7 b6 b5 b4 b3 b2 b1 b0

TRESEC 0118h 00h
Function RW
8-bit counter data can be read.
Although Timer RE stops counting, the count value is held. RO
The TRESEC register is set to 00h at the compare match.
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Figure 14.124 TRESEC Register in Output Compare Mode
Timer RE Compare Data Register

b7 b6 b5 b4 b3 b2 b1 b0

TREMIN 0119h 00h
Function RW
8-bit compare data is stored.
RW
Figure 14.125 TREMIN Register in Output Compare Mode
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REJ09B0244-0300

b7 b6 b5 b4 b3 b2 b1 b0

TRECR1 011Ch 00h
—
Timer RE count status flag 0 : Count stopped
TCSTF RO
1 : Counting
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TREO pin output enable bit 0 : Disable clock output
TOENA RW
1 : Enable clock output
Interrupt request timing bit Set to 0 in output compare mode.
INT RW
Timer RE reset bit When setting this bit to 0, after setting it to 1, the
follow ing w ill occur.
• Registers TRESEC, TREMIN, TREHR, TREWK,
and TRECR2 are set to 00h.
TRERST • Bits TCSTF, INT, PM, H12_H24, and TSTART RW
in the TRECR1 register are set to 0.
• The 8-bit counter is set to 00h and
the 4-bit counter is set to 0h.
PM A.m./p.m. bit Set to 0 in output compare mode. RW

H12_H24 Operating mode select bit RW
Timer RE count start bit 0 : Count stops
TSTART RW
1 : Count starts
Figure 14.126 TRECR1 Register in Output Compare Mode

b7 b6 b5 b4 b3 b2 b1 b0

TRECR2 011Dh 00h
Periodic interrupt triggered every Set to 0 in output compare mode.
SEIE RW
second enable bit
Periodic interrupt triggered every
MNIE RW
minute enable bit
HRIE RW
hour enable bit
DYIE RW
day enable bit
WKIE RW
w eek enable bit
Compare match interrupt enable bit 0 : Disable compare match interrupt
COMIE RW
1 : Enable compare match interrupt
—
Figure 14.127 TRECR2 Register in Output Compare Mode
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REJ09B0244-0300
Timer RE Count Source Select Register

b7 b6 b5 b4 b3 b2 b1 b0

TRECSR 011Eh 00001000b
Count source select bits b1 b0
RCS0 0 0 : f4 RW
0 1 : f8
1 0 : f32
www.DataSheet4U.com 1 1 : fC4
RCS1 RW
4-bit counter select bit 0 : Not used

RCS2 RW
1 : Used
RCS3 Real-time clock mode select bit Set to 0 in output compare mode. RW
—
Clock output select bits (1) b6 b5
RCS5 0 0 : f2 RW
0 1 : f4
1 0 : f8
1 1 : Compare output
RCS6 RW

—
NOTE:
1. Write to bits RCS5 to RCS6 w hen the TOENA bit in the TRECR1 register is set to 0 (disable clock output).
Figure 14.128 TRECSR Register in Output Compare Mode
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REJ09B0244-0300
Count starts
Matched
(hexadecimal number)
8-bit counter content
Matched Matched
TREMIN register
setting value
00h
Time
TSTART bit in 1
TRECR1 register
2 cycles of maximum count source
TCSTF bit in 1
TRECR1 register 0
Set to 0 by acknowledgement of interrupt request or a program
IR bit in 1
TREIC register 0
TREO output 1
0
Output polarity is inverted

when the compare matches

TOENA bit in TRECR1 register = 1 (enable clock output)
COMIE bit in TRECR2 register = 1 (enable compare match interrupt)
RCS6 to RCS5 bits in TRECSR register = 11b (compare output)
Figure 14.129 Operating Example in Output Compare Mode
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REJ09B0244-0300
14.4.3 Notes on Timer RE
14.4.3.1 Starting and Stopping Count

Timer RE has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which indicates
count start or stop. Bits TSTART and TCSTF are in the TRECR1 register.
Timer RE starts counting and the TCSTF bit is set to 1 (count starts) when the TSTART bit is set to 1 (count
starts). It takes up to 2 cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to
1. During this time, do not access registers associated with timer RE(1) other than the TCSTF bit.
Also, timer RE stops counting when setting the TSTART bit to 0 (count stops) and the TCSTF bit is set to 0
(count stops). It takes the time for up to 2 cycles of the count source until the TCSTF bit is set to 0 after setting
the TSTART bit to 0. During this time, do not access registers associated with timer RE other than the TCSTF
www.DataSheet4U.com bit.
NOTE:
1. Registers associated with timer RE: TRESEC, TREMIN, TREHR, TREWK, TRECR1, TRECR2, and
TRECSR.
14.4.3.2 Register Setting

Write to the following registers or bits when timer RE is stopped.
• Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2
• Bits H12_H24, PM, and INT in TRECR1 register
• Bits RCS0 to RCS3 in TRECSR register
Timer RE is stopped when bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped).
Also, set all above-mentioned registers and bits (immediately before timer RE count starts) before setting the
TRECR2 register.
Figure 14.130 shows a Setting Example in Real-Time Clock Mode.
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REJ09B0244-0300
TSTART in TRECR1 = 0
Stop timer RE operation

TCSTF in TRECR1 = 0?
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TREIC←00h
(disable timer RE interrupt)
TRERST in TRECR1 = 1
Timer RE register
and control circuit reset
Setting of registers TRECSR, Select clock output

TRESEC, TREMIN, TREHR, Select clock source
TREWK, and bits H12_H24, PM, Seconds, minutes, hours, days of week, operating mode
and INT in TRECR1 register Set a.m./p.m., interrupt timing
Setting of TRECR2 Select interrupt source
Setting of TREIC (IR bit ←0,

select interrupt priority level)
Start timer RE operation
Figure 14.130 Setting Example in Real-Time Clock Mode
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REJ09B0244-0300
14.4.3.3 Time Reading Procedure of Real-Time Clock Mode

In real-time clock mode, read registers TRESEC, TREMIN, TREHR, and TREWK when time data is updated
and read the PM bit in the TRECR1 register when the BSY bit is set to 0 (not while data is updated).
Also, when reading several registers, an incorrect time will be read if data is updated before another register is
read after reading any register.
In order to prevent this, use the reading procedure shown below.
• Using an interrupt
Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the
TRECR1 register in the timer RE interrupt routine.
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• Monitoring with a program 1
Monitor the IR bit in the TREIC register with a program and read necessary contents of registers TRESEC,
TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the IR bit in the TREIC
register is set to 1 (timer RE interrupt request generated).

(1) Monitor the BSY bit.
(2) Monitor until the BSY bit is set to 0 after the BSY bit is set to 1 (approximately 62.5 ms while the BSY
bit is set to 1).
(3) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the
TRECR1 register after the BSY bit is set to 0.
• Using read results if they are the same value twice

TRECR1 register.
(2) Read the same register as (1) and compare the contents.
(3) Recognize as the correct value if the contents match. If the contents do not match, repeat until the read
contents match with the previous contents.
Also, when reading several registers, read them as continuously as possible.
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REJ09B0244-0300
R8C/24 Group, R8C/25 Group 15. Serial Interface
15. Serial Interface

The serial interface consists of two channels (UART0 and UART1). Each UARTi (i = 0 or 1) has an exclusive timer to
generate the transfer clock and operates independently.
Figure 15.1 shows a UARTi (i = 0 or 1) Block Diagram. Figure 15.2 shows a UARTi Transmit/Receive Unit.
UARTi has two modes: clock synchronous serial I/O mode and clock asynchronous serial I/O mode (UART mode).
Figures 15.3 to 15.6 show the Registers Associated with UARTi.
(UART0)
RXD0 TXD0
www.DataSheet4U.com UART reception Receive
1/16 clock
CLK1 to CLK0 = 00b CKDIR = 0 Clock Reception control
Internal circuit Transmit/
f1 synchronous type
= 01b U0BRG register
receive
f8 UART transmission Transmit unit
= 10b 1/(n0+1) 1/16
f32 Transmission clock
Clock control circuit
External synchronous type
CKDIR = 1
1/2 CKDIR = 0
Clock synchronous type
(when internal clock is selected)
(when external clock is selected) CKDIR = 1
CLK
polarity
CLK0 switch
circuit
TXD1EN
(UART1)
RXD1 TXD1
UART reception Receive
1/16 clock
CLK1 to CLK0 = 00b CKDIR = 0 Clock Reception control
Internal circuit Transmit/
f1 synchronous type
= 01b U1BRG register
receive
f8 Transmit
= 10b UART transmission unit
f32 1/(n0+1) 1/16 clock
Transmission
Clock control circuit
External synchronous type
CKDIR = 1
1/2 CKDIR = 0
(when external clock is selected) CKDIR = 1
U1PINSEL Clock synchronous type
CLK U1PINSEL
polarity
CLK1 switch
circuit
Figure 15.1 UARTi (i = 0 or 1) Block Diagram
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Clock
synchronous
PRYE = 0 type
PAR Clock UART (7 bits)
1SP disabled synchronous UART (7 bits) UARTi receive register
type UART (8 bits)
RXDi SP SP PAR
PAR UART Clock
2SP enabled UART (9 bits)
synchronous
PRYE = 1 type
UART (8 bits)
UART (9 bits)
0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 UiRB register
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MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
MSB/LSB conversion circuit
D8 D7 D6 D5 D4 D3 D2 D1 D0 UiTB register
UART (8 bits)
UART (9 bits)
PRYE = 1 Clock
PAR UART (9 bits) synchronous
2SP enabled UART type
SP SP PAR TXDi
1SP PAR Clock UART (7 bits) UARTi transmit register
UART (7 bits)
disabled synchronous UART (8 bits)
PRYE = 0 type
Clock i = 0 or 1
0 synchronous SP: Stop bit
type PAR: Parity bit
Figure 15.2 UARTi Transmit/Receive Unit
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UARTi Transmit Buffer Register (i = 0 or 1)(1, 2)

(b15) (b8)
b7 b0 b7 b0

U0TB 00A3h-00A2h Undefined
U1TB 00ABh-00AAh Undefined
Function RW
— Transmit data
WO
(b8-b0)
—
NOTES:
1. When the transfer data length is 9 bits, w rite data to high byte first, then low byte.
2. Use the MOV instruction to w rite to this register.
UARTi Receive Buffer Register (i = 0 or 1)(1)

(b15) (b8)
b7 b0 b7 b0

U0RB 00A7h-00A6h Undefined
U1RB 00AFh-00AEh Undefined
— Receive data (D7 to D0)
— RO
(b7-b0)
— Receive data (D8)
— RO
(b8)
—
Overrun error flag(2) 0 : No overrun error
OER RO
1 : Overrun error
Framing error flag(2) 0 : No framing error
FER RO
1 : Framing error
Parity error flag(2) 0 : No parity error
PER RO
1 : Parity error
Error sum flag(2) 0 : No error
SUM RO
1 : Error
NOTES:
1. Read out the UiRB register in 16-bit units.
2. Bits SUM, PER, FER, and OER are set to 0 (no error) w hen bits SMD2 to SMD0 in the UiMR register are set to 000b
(serial interface disabled) or the RE bit in the UiC1 register is set to 0 (receive disabled). The SUM bit is set to 0 (no
error) w hen bits PER, FER, and OER are set to 0 (no error). Bits PER and FER are set to 0 even w hen the higher byte
of the UiRB register is read out.
Also, bits PER and FER are set to 0 w hen reading the high-order byte of the UiRB register.
Figure 15.3 Registers U0TB to U1TB and U0RB to U1RB
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UARTi Bit Rate Register (i = 0 or 1)(1, 2, 3)

b7 b0

U0BRG 00A1h Undefined
U1BRG 00A9h Undefined
Assuming the set value is n, UiBRG divides the count source by n+1 00h to FFh
WO
NOTES:
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1. Write to this register w hile the serial I/O is neither transmitting nor receiving.
2. Use the MOV instruction to w rite to this register.
3. After setting the CLK0 to CLK1 bits of the UiC0 register, w rite to the UiBRG register.
UARTi Transmit/Receive Mode Register (i = 0 or 1)

b7 b6 b5 b4 b3 b2 b1 b0

U0MR 00A0h 00h
U1MR 00A8h 00h
Serial I/O mode select bits b2 b1 b0
SMD0 0 0 0 : Serial interface disabled RW
0 0 1 : Clock synchronous serial I/O mode
1 0 0 : UART mode transfer data 7 bits long
SMD1 1 0 1 : UART mode transfer data 8 bits long RW
1 1 0 : UART mode transfer data 9 bits long
Other than above : Do not set.
SMD2 RW
Internal/external clock select bit 0 : Internal clock

CKDIR RW
1 : External clock(1)
Stop bit length select bit 0 : 1 stop bit
STPS RW
1 : 2 stop bits
Odd/even parity select bit Enable w hen PRYE = 1
PRY 0 : Odd parity RW
1 : Even parity
Parity enable bit 0 : Parity disabled
PRYE RW
1 : Parity enabled
RW
(b7)
NOTE:
1. Set the PD1_6 bit in the PD1 register to 0 (input).
Figure 15.4 Registers U0BRG to U1BRG and U0MR to U1MR
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UARTi Transmit/Receive Control Register 0 (i = 0 or 1)

b7 b6 b5 b4 b3 b2 b1 b0

U0C0 00A4h 00001000b
U1C0 00ACh 00001000b
BRG count source select b1 b0
CLK0 bits (1) 0 0 : Selects f1 RW
0 1 : Selects f8
www.DataSheet4U.com 1 0 : Selects f32
CLK1 1 1 : Do not set. RW

RW
(b2)
Transmit register empty 0 : Data in transmit register (during transmit)
TXEPT flag 1 : No data in transmit register (transmit completed) RO

—
Data output select bit 0 : TXDi pin is for CMOS output
NCH RW
1 : TXDi pin is for N-channel open drain output
CLK polarity select bit 0 : Transmit data is output at falling edge of transfer
clock and receive data is input at rising edge
CKPOL 1 : Transmit data is output at rising edge of transfer RW
clock and receive data is input at falling edge
Transfer format select bit 0 : LSB first
UFORM RW
1 : MSB first
NOTE:
1. If the BRG count source is sw itched, set the UiBRG register again.
Figure 15.5 Registers U0C0 to U1C0
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UARTi Transmit/Receive Control Register 1 (i = 0 or 1)

b7 b6 b5 b4 b3 b2 b1 b0

U0C1 00A5h 00000010b
U1C1 00ADh 00000010b
Transmit enable bit(1) 0 : Disables transmission
TE RW
1 : Enables transmission
Transmit buffer empty flag 0 : Data in UiTB register
www.DataSheet4U.com TI RO
1 : No data in UiTB register
Receive enable bit 0 : Disables reception
RE RW
1 : Enables reception
Receive complete flag(1) 0 : No data in UiRB register
RI RO
1 : Data in UiRB register
UARTi transmit interrupt cause 0 : Transmission buffer empty (TI=1)
UiIRS RW
select bit 1 : Transmission completed (TXEPT=1)
UARTi continuous receive mode 0 : Disables continuous receive mode
UiRRM RW
enable bit(2) 1 : Enables continuous receive mode
—
NOTES:
1. The RI bit is set to 0 w hen the higher byte of the UiRB register is read out.
2. Set the UiRRM bit to 0 (disables continuous receive mode) in UART mode.
UART1 Function Select Register

b7 b0

U1SR 00F5h Undefined
Function RW
Set to 0Fh w hen using UART1.
As a result, UART1 can be used for clock synchronous or clock asynchronous serial I/O.
Do not set values other than 0Fh. WO
When read, its content is undefined.
Port Mode Register

b7 b6 b5 b4 b3 b2 b1 b0

PMR 00F8h 00h
—
(b3-b0)
U1PINSEL RW
—
(b6-b5)
IICSEL RW
Figure 15.6 Registers U0C1 to U1C1, U1SR, and PMR
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15.1 Clock Synchronous Serial I/O Mode

In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock.
Table 15.1 lists the Clock Synchronous Serial I/O Mode Specifications. Table 15.2 lists the Registers Used and
Settings in Clock Synchronous Serial I/O Mode.
Table 15.1 Clock Synchronous Serial I/O Mode Specifications

Item Specification
Transfer data format • Transfer data length: 8 bits
Transfer clocks • CKDIR bit in UiMR register is set to 0 (internal clock): fi/(2(n+1))
fi = f1, f8, f32 n = value set in UiBRG register: 00h to FFh
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• The CKDIR bit is set to 1 (external clock): input from CLKi pin
Transmit start conditions • Before transmission starts, the following requirements must be met(1)
- The TE bit in the UiC1 register is set to 1 (transmission enabled)
- The TI bit in the UiC1 register is set to 0 (data in the UiTB register)
Receive start conditions • Before reception starts, the following requirements must be met(1)
- The RE bit in the UiC1 register is set to 1 (reception enabled)
- The TE bit in the UiC1 register is set to 1 (transmission enabled)
- The TI bit in the UiC1 register is set to 0 (data in the UiTB register)
Interrupt request • When transmitting, one of the following conditions can be selected
generation timing - The UiIRS bit is set to 0 (transmit buffer empty):
When transferring data from the UiTB register to UARTi transmit register
(when transmission starts).
- The UiIRS bit is set to 1 (transmission completes):
When completing data transmission from UARTi transmit register.
• When receiving
When data transfer from the UARTi receive register to the UiRB register
(when reception completes).
Error detection • Overrun error(2)
This error occurs if the serial interface starts receiving the next data item
before reading the UiRB register and receives the 7th bit of the next data.
Select functions • CLK polarity selection
Transfer data input/output can be selected to occur synchronously with the
rising or the falling edge of the transfer clock.
• LSB first, MSB first selection
Whether transmitting or receiving data begins with bit 0 or begins with bit 7
can be selected.
• Continuous receive mode selection
Receive is enabled immediately by reading the UiRB register.
i = 0 or 1
NOTES:
1. If an external clock is selected, ensure that the external clock is “H” when the CKPOL bit in the UiC0
register is set to 0 (transmit data output at falling edge and receive data input at rising edge of
transfer clock), and that the external clock is “L” when the CKPOL bit is set to 1 (transmit data output
at rising edge and receive data input at falling edge of transfer clock).
2. If an overrun error occurs, the receive data (b0 to b8) of the UiRB register will be undefined. The IR
bit in the SiRIC register remains unchanged.
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Table 15.2 Registers Used and Settings in Clock Synchronous Serial I/O Mode(1)
Register Bit Function
UiTB 0 to 7 Set data transmission
UiRB 0 to 7 Data reception can be read
OER Overrun error flag
UiBRG 0 to 7 Set bit rate
UiMR SMD2 to SMD0 Set to 001b
CKDIR Select the internal clock or external clock
UiC0 CLK1 to CLK0 Select the count source in the UiBRG register
www.DataSheet4U.com TXEPT Transmit register empty flag
NCH Select TXDi pin output mode
CKPOL Select the transfer clock polarity
UFORM Select the LSB first or MSB first
UiC1 TE Set this bit to 1 to enable transmission/reception
TI Transmit buffer empty flag
RE Set this bit to 1 to enable reception
RI Reception complete flag
UiIRS Select the UARTi transmit interrupt source
UiRRM Set this bit to 1 to use continuous receive mode
i = 0 or 1
NOTE:
1. Set bits which are not in this table to 0 when writing to the above registers in clock synchronous
serial I/O mode.
Table 15.3 lists the I/O Pin Functions in Clock Synchronous Serial I/O Mode. The TXDi pin outputs “H” level
between the operating mode selection of UARTi (i = 0 or 1) and transfer start. (If the NCH bit is set to 1 (N-channel
open-drain output), this pin is in a high-impedance state.)
Table 15.3 I/O Pin Functions in Clock Synchronous Serial I/O Mode
Pin Name Function Selection Method
TXD0 (P1_4) Output serial data (Outputs dummy data when performing reception only)
RXD0 (P1_5) Input serial data PD1_5 bit in PD1 register = 0
(P1_5 can be used as an input port when performing
transmission only)
CLK0 (P1_6) Output transfer clock CKDIR bit in U0MR register = 0
Input transfer clock CKDIR bit in U0MR register = 1
PD1_6 bit in PD1 register = 0
TXD1 (P6_6) Output serial data U1PINSEL bit in PMR register = 1
(Outputs dummy data when performing reception only)
RXD1 (P6_7) Input serial data U1PINSEL bit in PMR register = 1
(P6_7 can be used as an input port when performing
transmission only)
CLK1 (P6_5) Output transfer clock U1PINSEL bit in PMR register = 1
CKDIR bit in U1MR register = 0
Input transfer clock U1PINSEL bit in PMR register = 1
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• Example of transmit timing (when internal clock is selected)

TC
Transfer clock
TE bit in UiC1 1
register 0 Set data in UiTB register
TI bit in UiC1 1
register 0
Transfer from UiTB register to UARTi transmit register
TCLK Stop pulsing because the TE bit is set to 0

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CLKi
TXDi D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
TXEPT bit in 1
UiC0 register 0
IR bit in SiTIC 1
register 0
Set to 0 when interrupt request is acknowledged, or set by a program

TC=TCLK=2(n+1)/fi
fi: Frequency of UiBRG count source (f1, f8, f32)
The above applies under the following settings: n: Setting value to UiBRG register
• CKDIR bit in UiMR register = 0 (internal clock)
• CKPOL bit in UiC0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock)
• UiIRS bit in UiC1 register = 0 (an interrupt request is generated when the transmit buffer is empty)
• Example of receive timing (when external clock is selected)
RE bit in UiC1 1
register 0
TE bit in UiC1 1
register Write dummy data to UiTB register
0
TI bit in UiC1 1
register 0
1/fEXT
CLKi
Receive data is taken in
RXDi D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5
Transfer from UARTi receive register to

Read out from UiRB register
UiRB register
RI bit in UiC1 1
register
0
IR bit in SiRIC 1
register 0
The above applies under the following settings:

• CKDIR bit in UiMR register = 1 (external clock)
• CKPOL bit in UiC0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock)
The following conditions are met when “H” is applied to the CLKi pin before receiving data:
• TE bit in UiC1 register = 1 (enables transmit)
• RE bit in UiC1 register = 1 (enables receive)
• Write dummy data to the UiTB register
fEXT: Frequency of external clock
i = 0 or 1
Figure 15.7 Transmit and Receive Timing Example in Clock Synchronous Serial I/O Mode
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15.1.1 Polarity Select Function

Figure 15.8 shows the Transfer Clock Polarity. Use the CKPOL bit in the UiC0 (i = 0 or 1) register to select the
transfer clock polarity.
• When the CKPOL bit in the UiC0 register = 0 (output transmit data at the falling
edge and input receive data at the rising edge of the transfer clock)
CLKi(1)
TXDi D0 D1 D2 D3 D4 D5 D6 D7
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RXDi D0 D1 D2 D3 D4 D5 D6 D7
• When the CKPOL bit in the UiC0 register = 1 (output transmit data at the rising
edge and input receive data at the falling edge of the transfer clock)
CLKi(2)
NOTES:
1. When not transferring, the CLKi pin level is “H”.
2. When not transferring, the CLKi pin level is “L”.
i = 0 or 1
Figure 15.8 Transfer Clock Polarity
15.1.2 LSB First/MSB First Select Function

Figure 15.9 shows the Transfer Format. Use the UFORM bit in the UiC0 (i = 0 or 1) register to select the
transfer format.
• When UFORM bit in UiC0 register = 0 (LSB first)(1)
CLKi
• When UFORM bit in UiC0 register = 1 (MSB first)(1)
CLKi
NOTE:
1. The above applies when the CKPOL bit in the UiC0 register is
set to 0 (output transmit data at the falling edge and input receive
data at the rising edge of the transfer clock).
i = 0 or 1
Figure 15.9 Transfer Format
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15.1.3 Continuous Receive Mode

Continuous receive mode is selected by setting the UiRRM (i = 0 or 1) bit in the UiC1 register to 1 (enables
continuous receive mode). In this mode, reading the UiRB register sets the TI bit in the UiC1 register to 0 (data
in the UiTB register). When the UiRRM bit is set to 1, do not write dummy data to the UiTB register by a
program.
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15.2 Clock Asynchronous Serial I/O (UART) Mode

The UART mode allows data transmission and reception after setting the desired bit rate and transfer data format.
Table 15.4 lists the UART Mode Specifications. Table 15.5 lists the Registers Used and Settings for UART Mode.
Table 15.4 UART Mode Specifications

Item Specification
Transfer data formats • Character bit (transfer data): Selectable among 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: Selectable among odd, even, or none
• Stop bit: Selectable among 1 or 2 bits
Transfer
www.DataSheet4U.com clocks • CKDIR bit in UiMR register is set to 0 (internal clock): fj/(16(n+1))
fj = f1, f8, f32 n = value set in UiBRG register: 00h to FFh
• CKDIR bit is set to 1 (external clock): fEXT/(16(n+1))
fEXT: Input from CLKi pin, n = value set in UiBRG register: 00h to FFh
Transmit start conditions • Before transmission starts, the following are required
- TE bit in UiC1 register is set to 1 (transmission enabled)
- TI bit in UiC1 register is set to 0 (data in UiTB register)
Receive start conditions • Before reception starts, the following are required
- RE bit in UiC1 register is set to 1 (reception enabled)
- Start bit detected
Interrupt request • When transmitting, one of the following conditions can be selected
generation timing - UiIRS bit is set to 0 (transmit buffer empty):
When transferring data from the UiTB register to UARTi transmit
register (when transmission starts).
- UiIRS bit is set to 1 (transfer ends):
When serial interfac.e completes transmitting data from the UARTi
transmit register
• When receiving
When transferring data from the UARTi receive register to UiRB register
(when reception ends).
Error detection • Overrun error(1)
This error occurs if the serial interface starts receiving the next data item
before reading the UiRB register and receive the bit preceding the final
stop bit of the next data item.
• Framing error
This error occurs when the set number of stop bits is not detected.
• Parity error
This error occurs when parity is enabled, and the number of 1’s in parity
and character bits do not match the number of 1’s set.
• Error sum flag
This flag is set is set to 1 when an overrun, framing, or parity error is
generated.
i = 0 or 1
NOTE:
1. If an overrun error occurs, the receive data (b0 to b8) of the UiRB register will be undefined. The IR
bit in the SiRIC register remains unchanged.
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Table 15.5 Registers Used and Settings for UART Mode

Register Bit Function
UiTB 0 to 8 Set transmit data(1)
UiRB 0 to 8 Receive data can be read(1, 2)
OER,FER,PER,SUM Error flag
UiBRG 0 to 7 Set a bit rate
UiMR SMD2 to SMD0 Set to 100b when transfer data is 7 bits long
Set to 101b when transfer data is 8 bits long
Set to 110b when transfer data is 9 bits long
www.DataSheet4U.com CKDIR Select the internal clock or external clock
STPS Select the stop bit
PRY, PRYE Select whether parity is included and whether odd or even
UiC0 CLK0, CLK1 Select the count source for the UiBRG register
TXEPT Transmit register empty flag
NCH Select TXDi pin output mode
CKPOL Set to 0
UFORM LSB first or MSB first can be selected when transfer data is 8 bits
long. Set to 0 when transfer data is 7 or 9 bits long.
UiC1 TE Set to 1 to enable transmit
TI Transmit buffer empty flag
RE Set to 1 to enable receive
RI Receive complete flag
UiIRS Select the source of UARTi transmit interrupt
UiRRM Set to 0
i = 0 or 1
NOTES:
1. The bits used for transmit/receive data are as follows: Bits 0 to 6 when transfer data is 7 bits long;
bits 0 to 7 when transfer data is 8 bits long; bits 0 to 8 when transfer data is 9 bits long.
2. The following bits are undefined: Bits 7 and 8 when transfer data is 7 bits long; bit 8 when transfer
data is 8 bits long.
Table 15.6 lists the I/O Pin Functions in UART Mode. After the UARTi (i = 0 or 1) operating mode is selected, the
TXDi pin outputs “H” level. (If the NCH bit is set to 1 (N-channel open-drain output), this pin is in a high-
impedance state) until transfer starts.)
Table 15.6 I/O Pin Functions in UART Mode

Pin name Function Selection Method
TXD0 (P1_4) Output serial data (Cannot be used as a port when performing reception only)
RXD0 (P1_5) Input serial data PD1_5 bit in PD1 register = 0
(P1_5 can be used as an input port when performing transmission only)
CLK0 (P1_6) Programmable I/O Port CKDIR bit in U0MR register = 0
Input transfer clock CKDIR bit in U0MR register = 1
TXD1 (P6_6) Output serial data U1PINSEL bit in PMR register = 1
(Cannot be used as a port when performing reception only)
RXD1 (P6_7) Input serial data U1PINSEL bit in PMR register = 1
(P6_7 can be used as an input port when performing transmission only)
CLK1 (P6_5) Programmable I/O Port CKDIR bit in U1MR register = 0
Input transfer clock U1PINSEL bit in PMR register = 1
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• Transmit timing when transfer data is 8 bits long (parity enabled, 1 stop bit)
TC
Transfer clock
TE bit in UiC1 1
register 0 Write data to UiTB register
TI bit in UiC1 1
register 0
Transfer from UiTB register to UARTi transmit register Stop pulsing
because the TE bit is set to 0
Start Parity Stop
www.DataSheet4U.com bit bit bit
TXDi ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1
TXEPT bit in 1
UiC0 register 0
IR bit SiTIC 1
register 0
The above timing diagram applies under the following conditions: TC=16 (n + 1) / fj or 16 (n + 1) / fEXT
• PRYE bit in UiMR register = 1 (parity enabled) fj: Frequency of UiBRG count source (f1, f8, f32)
• STPS bit in UiMR register = 0 (1 stop bit) fEXT: Frequency of UiBRG count source (external clock)
• UiIRS bit in UiC1 register = 1 (an interrupt request is generated when transmit completes) n: Setting value to UiBRG register
i = 0 to 1
• Transmit timing when transfer data is 9 bits long (parity disabled, 2 stop bits)
TC
Transfer clock
TE bit in UiC1 1
register 0
Write data to UiTB register
TI bit in UiC1 1
register 0
Start Stop Stop

bit bit bit
TXDi ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1
TXEPT bit in 1
UiC0 register 0
IR bit in SiTIC 1
register 0
The above timing diagram applies under the following conditions:

• PRYE bit in UiMR register = 0 (parity disabled)
TC=16 (n + 1) / fj or 16 (n + 1) / fEXT
• STPS bit in UiMR register = 1 (2 stop bits) fj: Frequency of UiBRG count source (f1, f8, f32)
• UiIRS bit in UiC1 register = 0 (an interrupt request is generated when transmit buffer is empty) fEXT: Frequency of UiBRG count source (external clock)
n: Setting value to UiBRG register
i = 0 to 1
Figure 15.10 Transmit Timing in UART Mode
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• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
UiBRG output
UiC1 register 1
RE bit 0
Stop bit
RXDi Start bit D0 D1 D7
www.DataSheet4U.com Determined to be “L” Receive data taken in
Transfer clock
Reception triggered when transfer clock

is generated by falling edge of start bit Transferred from UARTi receive
register to UiRB register
UiC1 register 1
RI bit 0
SiRIC register 1
IR bit 0
Set to 0 when interrupt request is accepted, or set by a program

The above timing diagram applies when the register bits are set as follows:
• UiMR register PRYE bit = 0 (parity disabled)
• UiMR register STPS bit = 0 (1 stop bit)
i = 0 or 1
Figure 15.11 Receive Timing Example in UART Mode
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15.2.1 Bit Rate

In UART mode, the bit rate is the frequency divided by the UiBRG (i = 0 or 1) register.
UART mode
• Internal clock selected
UiBRG register setting value = fj -1
Bit Rate × 16
Fj: Count source frequency of the UiBRG register (f1, f8, or f32)
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• External clock selected
UiBRG register setting value = fEXT
-1
Bit Rate × 16
fEXT: Count source frequency of the UiBRG register (external clock)
i = 0 or 1
Figure 15.12 Calculation Formula of UiBRG (i = 0 or 1) Register Setting Value
Table 15.7 Bit Rate Setting Example in UART Mode (Internal Clock Selected)
System Clock = 20 MHz System Clock = 18.432 MHz(1) System Clock = 8 MHz
UiBRG
Bit Rate UiBRG Setting UiBRG Setting UiBRG Actual Setting
Count Actual Time Actual Time
(bps) Setting Error Setting Error Setting Time Error
Source (bps) (bps)
Value (%) Value (%) Value (bps) (%)
1200 f8 129 (81h) 1201.92 0.16 119 (77h) 1200.00 0.00 51 (33h) 1201.92 0.16
2400 f8 64 (40h) 2403.85 0.16 59 (3Bh) 2400.00 0.00 25 (19h) 2403.85 0.16
4800 f8 32 (20h) 4734.85 -1.36 29 (1Dh) 4800.00 0.00 12 (0Ch) 4807.69 0.16
9600 f1 129 (81h) 9615.38 0.16 119 (77h) 9600.00 0.00 51 (33h) 9615.38 0.16
14400 f1 86 (56h) 14367.82 -0.22 79 (4Fh) 14400.00 0.00 34 (22h) 14285.71 -0.79
19200 f1 64 (40h) 19230.77 0.16 59 (3Bh) 19200.00 0.00 25 (19h) 19230.77 0.16
28800 f1 42 (2Ah) 29069.77 0.94 39 (27h) 28800.00 0.00 16 (10h) 29411.76 2.12
38400 f1 32 (20h) 37878.79 -1.36 29 (1Dh) 38400.00 0.00 12 (0Ch) 38461.54 0.16
57600 f1 21 (15h) 56818.18 -1.36 19 (13h) 57600.00 0.00 8 (08h) 55555.56 -3.55
115200 f1 10 (0Ah) 113636.36 -1.36 9 (09h) 115200.00 0.00 − − −
i = 0 or 1
NOTE:
1. For the high-speed on-chip oscillator, the correction value in the FRA7 register should be written into the FRA1
register.
This applies when the high-speed on-chip oscillator is selected as the system clock and bits FRA22 to FRA20
in the FRA2 register are set to 000b (divide-by-2 mode). For the precision of the high-speed on-chip oscillator,
refer to 20. Electrical Characteristics.
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15.3 Notes on Serial Interface

• When reading data from the UiRB (i = 0 or 1) register either in the clock synchronous serial I/O mode or in the
clock asynchronous serial I/O mode. Ensure the data is read in 16-bit units. When the high-order byte of the
UiRB register is read, bits PER and FER in the UiRB register and the RI bit in the UiC1 register are set to 0.
To check receive errors, read the UiRB register and then use the read data.
Example (when reading receive buffer register):

MOV.W 00A6H,R0 ; Read the U0RB register
• When writing data to the UiTB register in the clock asynchronous serial I/O mode with 9-bit transfer data
length, write data to the high-order byte first then the low-order byte, in 8-bit units.
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Example (when reading transmit buffer register):
MOV.B #XXH,00A3H ; Write the high-order byte of U0TB register
MOV.B #XXH,00A2H ; Write the low-order byte of U0TB register
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R8C/24 Group, R8C/25 Group 16. Clock Synchronous Serial Interface
16. Clock Synchronous Serial Interface

The clock synchronous serial interface is configured as follows.
Clock synchronous serial interface
Clock synchronous serial I/O with chip select (SSU) Clock synchronous communication mode
4-wire bus communication mode
I2C bus Interface I2C bus interface mode

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Clock synchronous serial mode
The clock synchronous serial interface uses the registers at addresses 00B8h to 00BFh. Registers, bits, symbols, and
functions vary even for the same addresses depending on the mode. Refer to the register diagrams of each function for
details.
Also, the differences between clock synchronous communication mode and clock synchronous serial mode are the
options of the transfer clock, clock output format, and data output format.
16.1 Mode Selection

The clock synchronous serial interface has four modes.
Table 16.1lists the Mode Selections. Refer to 16.2 Clock Synchronous Serial I/O with Chip Select (SSU) and the
sections that follow for details of each mode.
Table 16.1 Mode Selections

Bit 0 in 00BDh
IICSEL Bit Bit 7 in 00B8h
(SSUMS Bit in SSMR2
in PMR (ICE Bit in ICCR1 Function Mode
Register, FS Bit in
Register Register)
SAR Register)
0 0 0 Clock synchronous Clock synchronous
serial I/O with chip communication mode
0 0 1 select 4-wire bus communication mode
1 1 0 I2C bus interface I2C bus interface mode
1 1 1 Clock synchronous serial mode
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16.2 Clock Synchronous Serial I/O with Chip Select (SSU)

Clock synchronous serial I/O with chip select supports clock synchronous serial data communication.
Table 16.2 lists the Clock Synchronous Serial I/O with Chip Select Specifications, and Figure 16.1 shows a Block
Diagram of Clock Synchronous Serial I/O with Chip Select. Figures 16.2 to 16.9 show Clock Synchronous Serial
I/O with Chip Select Associated Registers.
Table 16.2 Clock Synchronous Serial I/O with Chip Select Specifications
Item Specification
Transfer data format • Transfer data length: 8 bits
Continuous transmission and reception of serial data are supported since
both transmitter and receiver have buffer structures.
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Operating modes • Clock synchronous communication mode
• 4-wire bus communication mode (including bidirectional communication)
Master/slave device Selectable
I/O pins SSCK (I/O): Clock I/O pin
SSI (I/O): Data I/O pin
SSO (I/O): Data I/O pin
SCS (I/O): Chip-select I/O pin
Transfer clocks • When the MSS bit in the SSCRH register is set to 0 (operates as slave
device), external clock is selected (input from SSCK pin).
• When the MSS bit in the SSCRH register is set to 1 (operates as master
device), internal clock (selectable among f1/256, f1/128, f1/64, f1/32, f1/16,
f1/8 and f1/4, output from SSCK pin) is selected.
• Clock polarity and phase of SSCK can be selected.
Receive error detection • Overrun error
Overrun error occurs during reception and completes in error. While the
RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and
when next serial data receive is completed, the ORER bit is set to 1.
Multimaster error • Conflict error
detection When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus
communication mode) and the MSS bit in the SSCRH register is set to 1
(operates as master device) and when starting a serial communication, the
CE bit in the SSSR register is set to 1 if “L” applies to the SCS pin input.
When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus
communication mode), the MSS bit in the SSCRH register is set to 0
(operates as slave device) and the SCS pin input changes state from “L” to
“H”, the CE bit in the SSSR register is set to 1.
Interrupt requests 5 interrupt requests (transmit-end, transmit-data-empty, receive-data-full,
overrun error, and conflict error).(1)
Select functions • Data transfer direction
Selects MSB-first or LSB-first
• SSCK clock polarity
Selects “L” or “H” level when clock stops
• SSCK clock phase
Selects edge of data change and data download
NOTE:
1. Clock synchronous serial I/O with chip select has only one interrupt vector table.
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f1
Internal clock (f1/i) Internal clock

generation
circuit
Multiplexer
SSCK
www.DataSheet4U.com SSMR register
SSCRL register
SSCRH register
Transmit/receive
SCS SSER register
control circuit
SSSR register
Data bus
SSMR2 register
SSTDR register
SSO SSTRSR register

Selector
SSI
SSRDR register
Interrupt requests
(TXI, TEI, RXI, OEI, and CEI)
i = 4, 8, 16, 32, 64, 128, or 256
Figure 16.1 Block Diagram of Clock Synchronous Serial I/O with Chip Select
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SS Control Register H
b7 b6 b5 b4 b3 b2 b1 b0

SSCRH 00B8h 00h
Transfer clock rate select bits (1) b2 b1 b0
CKS0 0 0 0 : f1/256 RW
0 0 1 : f1/128
0 1 0 : f1/64
www.DataSheet4U.com 0 1 1 : f1/32
CKS1 RW
1 0 0 : f1/16
1 0 1 : f1/8
1 1 0 : f1/4
CKS2 RW
1 1 1 : Do not set.

—
(2)
Master/slave device select bit 0 : Operates as slave device
MSS RW
1 : Operates as master device
(3)
Receive single stop bit 0 : Maintains receive operation after
receiving 1 byte of data
RSSTP 1 : Completes receive operation after RW
receiving 1 byte of data
—
NOTES:
1. The set clock is used w hen the internal clock is selected.
2. The SSCK pin functions as the transfer clock output pin w hen the MSS bit is set to 1 (operates as master device).
The MSS bit is set to 0 (operates as slave device) w hen the CE bit in the SSSR register is set to 1 (conflict error
occurs).
3. The RSSTP bit is disabled w hen the MSS bit is set to 0 (operates as slave device).
Figure 16.2 SSCRH Register
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SS Control Register L
b7 b6 b5 b4 b3 b2 b1 b0

SSCRL 00B9h 01111101b
—
Clock synchronous When this bit is set to 1, the clock synchronous serial
serial I/O w ith chip I/O w ith chip select control block and SSTRSR register
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select control part are reset.
SRES reset bit The values of the registers (1) in the clock synchronous RW
serial I/O w ith chip select register are maintained.

—
SOL w rite protect bit(2) The output level can be changed by the SOL bit w hen
this bit is set to 0.
SOLP The SOLP bit remains unchanged even if 1 is w ritten to RW
it. When read, the content is 1.
Serial data output value When read
setting bit 0 : The serial data output is set to “L”.
1 : The serial data output is set to “H”.
SOL When w ritten(2,3) RW
0 : The data output is “L” after the serial data output.
1 : The data output is “H” after the serial data output.

—
—
NOTES:
1. Registers SSCRH, SSCRL, SSMR, SSER, SSSR, SSMR2, SSTDR, and SSRDR.
2. The data output after serial data is output can be changed by w riting to the SOL bit before or after transfer. When
w riting to the SOL bit, set the SOLP bit to 0 and the SOL bit to 0 or 1 simultaneously by the MOV instruction.
3. Do not w rite to the SOL bit during data transfer.
Figure 16.3 SSCRL Register
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SS Mode Register
b7 b6 b5 b4 b3 b2 b1 b0

SSMR 00BAh 00011000b
Bits counter 2 to 0 b2 b1 b0
BC0 0 0 0 : 8 bits left RO
0 0 1 : 1 bit left
0 1 0 : 2 bits left
www.DataSheet4U.com 0 1 1 : 3 bits left
BC1 RO
1 0 0 : 4 bits left
1 0 1 : 5 bits left
1 1 0 : 6 bits left
BC2 RO
1 1 1 : 7 bits left

RW
—
(1)
SSCK clock phase select bit 0 : Change data at odd edge
(Dow nload data at even edge)
CPHS 1 : Change data at even edge RW
(Dow nload data at odd edge)
SSCK clock polarity select bit(1) 0 : “H” w hen clock stops
CPOS RW
1 : “L” w hen clock stops
MSB first/LSB first select bit 0 : Transfers data MSB first
MLS RW
1 : Transfers data LSB first
NOTE:
1. Refer to 16.2.1.1 Association betw een Transfer Clock Polarity, Phase, and Data for the settings of the CPHS
and CPOS bits.
Figure 16.4 SSMR Register
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SS Enable Register
b7 b6 b5 b4 b3 b2 b1 b0

SSER 00BBh 00h
Conflict error interrupt enable bit 0 : Disables conflict error interrupt request
1 : Enables conflict error interrupt request
CEIE RW

—
Receive enable bit 0 : Disables receive
RE RW
1 : Enables receive
Transmit enable bit 0 : Disables transmit
TE RW
1 : Enables transmit
Receive interrupt enable bit 0 : Disables receive data full and overrun
error interrupt request
RIE 1 : Enables receive data full and overrun RW
error interrupt request
Transmit end interrupt enable bit 0 : Disables transmit end interrupt request
TEIE RW
1 : Enables transmit end interrupt request
Transmit interrupt enable bit 0 : Disables transmit data empty interrupt
request
TIE 1 : Enables transmit data empty interrupt RW
request
Figure 16.5 SSER Register
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SS Status Register(7)
b7 b6 b5 b4 b3 b2 b1 b0

SSSR 00BCh 00h
Conflict error flag(1) 0 : No conflict errors generated
CE RW
1 : Conflict errors generated(2)
—
www.DataSheet4U.com (1)
Overrun error flag 0 : No overrun errors generated
ORER RW
1 : Overrun errors generated(3)
—
Receive data register full 0 : No data in SSRDR register
RDRF (1,4) RW
1 : Data in SSRDR register
(1, 5)
Transmit end 0 : The TDRE bit is set to 0 w hen transmitting
the last bit of transmit data
TEND 1 : The TDRE bit is set to 1 w hen transmitting RW
the last bit of transmit data
Transmit data empty (1, 5, 6) 0 : Data is not transferred from registers SSTDR to
SSTRSR
TDRE 1 : Data is transferred from registers SSTDR to RW
SSTRSR
NOTES:
1. Writing 1 to CE, ORER, RDRF, TEND, or TDRE bits invalid. To set any of these bits to 0, first read 1 then w rite 0.
2. When the serial communication is started w hile the SSUMS bit in the SSMR2 register is set to 1 (four-w ire bus
communication mode) and the MSS bit in the SSCRH register is set to 1 (operates as master device), the CE bit is set
_____ _____
to 1 if “L” is applied to the SCS pin input. Refer to 16.2.7 SCS Pin Control and Arbitration for more information.
When the SSUMS bit in the SSMR2 register is set to 1 (four-w ire bus communication mode), the MSS bit in the
_____
SSCRH register is set to 0 (operates as slave device) and the SCS pin input changes the level from “L” to “H” during
transfer, the CE bit is set to 1.
3. Indicates w hen overrun errors occur and receive completes by error reception. If the next serial data receive
operation is completed w hile the RDRF bit is set to 1 (data in the SSRDR register), the ORER bit is set to 1. After the
ORER bit is set to 1 (overrun error), transmit and receive operations are disabled w hile the bit remains 1.
4. The RDRF bit is set to 0 w hen reading out the data from the SSRDR register.
5. Bits TEND and TDRE are set to 0 w hen w riting data to the SSTDR register.
6. The TDRE bit is set to 1 w hen the TE bit in the SSER register is set to 1 (transmit enabled).
7. When accessing the SSSR register continuously, insert one or more NOP instructions betw een the instructions to
access it.
Figure 16.6 SSSR Register
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SS Mode Register 2
b7 b6 b5 b4 b3 b2 b1 b0

SSMR2 00BDh 00h
Clock synchronous serial I/O w ith 0 : Clock synchronous communication mode
SSUMS RW
chip select mode select bit(1) 1 : Four-w ire bus communication mode
_____
SCS pin open drain output 0 : CMOS output
CSOS RW
select bit 1 : N-channel open drain output
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Serial data pin open output drain 0 : CMOS output(5)
SOOS RW
select bit(1) 1 : N-channel open drain output
SSCK pin open drain output 0 : CMOS output
SCKOS RW
select bit 1 : N-channel open drain output
_____
SCS pin select bits (2) b5 b4
0 0 : Functions as port
CSS0 _____ RW
0 1 : Functions as SCS input pin
_____
1 0 : Functions as SCS output pin(3)
_____
1 1 : Functions as SCS output pin(3)
CSS1 RW
SSCK pin select bit 0 : Functions as port

SCKS RW
1 : Functions as serial clock pin
(1, 4)
Bidirectional mode enable bit 0 : Standard mode (communication using 2
pins of data input and data output)
BIDE 1 : Bidirectional mode (communication using RW
1 pin of data input and data output)
NOTES:
1. Refer to 16.2.2.1 Association betw een Data I/O Pins and SS Shift Register for information on combinations of
data I/O pins.
_____
2. The SCS pin functions as a port, regardless of the values of bits CSS0 and CSS1 w hen the SSUMS bit is set to 0
(clock synchronous communication mode).
3. This bit functions as the SCS input pin before starting transfer.
4. The BIDE bit is disabled w hen the SSUMS bit is set to 0 (clock synchronous communication mode).
5. The SSI pin and SSO pin corresponding port direction bits are set to 0 (input mode) w hen the SOOS bit is set to 0
(CMOS output).
Figure 16.7 SSMR2 Register
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SS Transmit Data Register

b7 b6 b5 b4 b3 b2 b1 b0

SSTDR 00BEh FFh
Function RW
Store the transmit data.
The stored transmit data is transferred to the SSTRSR register and transmission is started
w hen it is detected that the SSTRSR register is empty.
When the next transmit data is w ritten to the SSTDR register during the data transmission from RW
www.DataSheet4U.com the SSTRSR register, the data can be transmitted continuously.
When the MLS bit in the SSMR register is set to 1 (transfer data w ith LSB-first), the data in
w hich MSB and LSB are reversed is read, after w riting to the SSTDR register.
SS Receive Data Register

b7 b6 b5 b4 b3 b2 b1 b0

SSRDR 00BFh FFh
Function RW
Store the receive data.(1)
The receive data is transferred to the SSRDR register and the receive operation is completed
w hen 1 byte of data has been received by the SSTRSR register. At this time, the next receive RO
operation is possible. Continuous reception is possible using registers SSTRSR and SSRDR.
NOTE:
1. The SSRDR register retains the data received before an overrun error occurs (ORER bit in the SSSR register set to 1
(overrun error)). When an overrun error occurs, the receive data may contain errors and therefore should be
discarded.
Figure 16.8 Registers SSTDR and SSRDR
Port Mode Register

b7 b6 b5 b4 b3 b2 b1 b0

PMR 00F8h 00h
—
(b3-b0)
U1PINSEL RW
—
(b6-b5)
IICSEL RW
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16.2.1 Transfer Clock

The transfer clock can be selected from among seven internal clocks (f1/256, f1/128, f1/64, f1/32, f1/16, f1/8,
and f1/4) and an external clock.
When using clock synchronous serial I/O with chip select, set the SCKS bit in the SSMR2 register to 1 and
select the SSCK pin as the serial clock pin.
When the MSS bit in the SSCRH register is set to 1 (operates as master device), an internal clock can be
selected and the SSCK pin functions as output. When transfer is started, the SSCK pin outputs clocks of the
transfer rate selected by bits CKS0 to CKS2 in the SSCRH register.
When the MSS bit in the SSCRH register is set to 0 (operates as slave device), an external clock can be selected
and the SSCK pin functions as input.
16.2.1.1
www.DataSheet4U.com Association between Transfer Clock Polarity, Phase, and Data
The association between the transfer clock polarity, phase and data changes according to the combination of the
SSUMS bit in the SSMR2 register and bits CPHS and CPOS in the SSMR register.
Figure 16.10 shows the Association between Transfer Clock Polarity, Phase, and Transfer Data.
Also, the MSB-first transfer or LSB-first transfer can be selected by setting the MLS bit in the SSMR register.
When the MLS bit is set to 1, transfer is started from the LSB and proceeds to the MSB. When the MLS bit is
set to 0, transfer is started from the MSB and proceeds to the LSB.
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• SSUMS = 0 (clock synchronous communication mode), CPHS bit = 0 (data change at odd
edge), and CPOS bit = 0 (“H” when clock stops)
SSCK
SSO, SSI b0 b1 b2 b3 b4 b5 b6 b7
www.DataSheet4U.com • SSUMS = 1 (4-wire bus communication mode) and CPHS = 0 (data change at odd edge)
SSCK
CPOS = 0
(“H” when clock stops)
SSCK
CPOS = 1
(“L” when clock stops)
SCS
• SSUMS = 1 (4-wire bus communication mode) and CPHS = 1 (data download at odd edge)
SSCK
CPOS = 0
(“H” when clock stops)
SSCK
CPOS = 1
(“L” when clock stops)
SCS
CPHS and CPOS: Bits in SSMR register, SSUMS: Bits in SSMR2 register
Figure 16.10 Association between Transfer Clock Polarity, Phase, and Transfer Data
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16.2.2 SS Shift Register (SSTRSR)

The SSTRSR register is a shift register for transmitting and receiving serial data.
When transmit data is transferred from the SSTDR register to the SSTRSR register and the MLS bit in the
SSMR register is set to 0 (MSB-first), the bit 0 in the SSTDR register is transferred to bit 0 in the SSTRSR
register. When the MLS bit is set to 1 (LSB-first), bit 7 in the SSTDR register is transferred to bit 0 in the
SSTRSR register.
16.2.2.1 Association between Data I/O Pins and SS Shift Register

The connection between the data I/O pins and SSTRSR register (SS shift register) changes according to a
combination of the MSS bit in the SSCRH register and the SSUMS bit in the SSMR2 register. The connection
also changes according to the BIDE bit in the SSMR2 register.
www.DataSheet4U.com Figure 16.11 shows the Association between Data I/O Pins and SSTRSR Register.
• SSUMS = 0 • SSUMS = 1 (4-wire bus communication mode),

(clock synchronous communication mode) BIDE = 0 (standard mode), and MSS = 1 (operates as
master device)
SSTRSR register SSO SSTRSR register SSO
SSI SSI
• SSUMS = 1 (4-wire bus communication mode), • SSUMS = 1 (4-wire bus communication mode) and
BIDE = 0 (standard mode), and MSS = 0 (operates BIDE = 1 (bidirectional mode)
as slave device)
SSTRSR register SSO SSTRSR register SSO
SSI SSI
Figure 16.11 Association between Data I/O Pins and SSTRSR Register
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16.2.3 Interrupt Requests

Clock synchronous serial I/O with chip select has five interrupt requests: transmit data empty, transmit end,
receive data full, overrun error, and conflict error. Since these interrupt requests are assigned to the clock
synchronous serial I/O with chip select interrupt vector table, determining interrupt sources by flags is required.
Table 16.3 shows the Clock Synchronous Serial I/O with Chip Select Interrupt Requests.
Table 16.3 Clock Synchronous Serial I/O with Chip Select Interrupt Requests
Interrupt Request Abbreviation Generation Condition
Transmit data empty TXI TIE = 1, TDRE = 1
Transmit end TEI TEIE = 1, TEND = 1
Receive data full
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RXI RIE = 1, RDRF = 1
Overrun error OEI RIE = 1, ORER = 1
Conflict error CEI CEIE = 1, CE = 1
CEIE, RIE, TEIE and TIE: Bits in SSER register
ORER, RDRF, TEND and TDRE: Bits in SSSR register
If the generation conditions in Table 16.3 are met, a clock synchronous serial I/O with chip select interrupt request
is generated. Set each interrupt source to 0 by a clock synchronous serial I/O with chip select interrupt routine.
However, the TDRE and TEND bits are automatically set to 0 by writing transmit data to the SSTDR register and
the RDRF bit is automatically set to 0 by reading the SSRDR register. In particular, the TDRE bit is set to 1 (data
transmitted from registers SSTDR to SSTRSR) at the same time transmit data is written to the SSTDR register.
Setting the TDRE bit to 0 (data not transmitted from registers SSTDR to SSTRSR) can cause an additional byte of
data to be transmitted.
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16.2.4 Communication Modes and Pin Functions

Clock synchronous serial I/O with chip select switches the functions of the I/O pins in each communication
mode according to the setting of the MSS bit in the SSCRH register and bits RE and TE in the SSER register.
Table 16.4 shows the Association between Communication Modes and I/O Pins.
Table 16.4 Association between Communication Modes and I/O Pins

Bit Setting Pin State
Communication Mode
SSUMS BIDE MSS TE RE SSI SSO SSCK
Clock synchronous 0 Disabled 0 0 1 Input −(1) Input
communication mode 1 0 −(1) Output Input
www.DataSheet4U.com 1 Input Output Input
1 0 1 Input −(1) Output
1 0 −(1) Output Output
1 Input Output Output
4-wire bus 1 0 0 0 1 −(1) Input Input
communication mode 1 0 Output −(1) Input
1 Output Input Input
1 0 1 Input −(1) Output
1 Input Output Output
4-wire bus 1 1 0 0 1 −(1) Input Input
(bidirectional) 1 0 −(1) Output Input
communication mode(2) 1 0 1 −(1) Input Output
NOTES:
1. This pin can be used as a programmable I/O port.
2. Do not set both bits TE and RE to 1 in 4-wire bus (bidirectional) communication mode.
SSUMS and BIDE: Bits in SSMR2 register
MSS: Bit in SSCRH register
TE and RE: Bits in SSER register
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16.2.5 Clock Synchronous Communication Mode
16.2.5.1 Initialization in Clock Synchronous Communication Mode

Figure 16.12 shows Initialization in Clock Synchronous Communication Mode. To initialize, set the TE bit in
the SSER register to 0 (transmit disabled) and the RE bit to 0 (receive disabled) before data transmission or
reception.
Set the TE bit to 0 and the RE bit to 0 before changing the communication mode or format.
Setting the RE bit to 0 does not change the contents of flags RDRF and ORER or the contents of the SSRDR
register.
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Start
SSER register RE bit ← 0

TE bit ← 0
SSMR2 register SSUMS bit ← 0
SSMR register CPHS bit ← 0

CPOS bit ← 0
Set MLS bit
SSCRH register Set MSS bit
SSMR2 register SCKS bit ← 1

Set SOOS bit
SSCRH register Set bits CKS0 to CKS2

Set RSSTP bit
SSSR register ORER bit ← 0(1)
SSER register RE bit ← 1 (receive)

TE bit ← 1 (transmit)
Set bits RIE, TEIE, and TIE
End
NOTE:
1. Write 0 after reading 1 to set the ORER bit to 0.
Figure 16.12 Initialization in Clock Synchronous Communication Mode
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16.2.5.2 Data Transmission

Figure 16.13 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation for Data
Transmission (Clock Synchronous Communication Mode). During data transmission, the clock synchronous
serial I/O with chip select operates as described below.
When clock synchronous serial I/O with chip select is set as a master device, it outputs a synchronous clock and
data. When clock synchronous serial I/O with chip select is set as a slave device, it outputs data synchronized
with the input clock.
When the TE bit is set to 1 (transmit enabled) before writing the transmit data to the SSTDR register, the TDRE
bit is automatically set to 0 (data not transferred from registers SSTDR to SSTRSR) and the data is transferred
from registers SSTDR to SSTRSR.
After the TDRE bit is set to 1 (data transferred from registers SSTDR to SSTRSR), transmission starts. When
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the TIE bit in the SSER register is set to 1, the TXI interrupt request is generated. When one frame of data is
transferred while the TDRE bit is set to 0, data is transferred from registers SSTDR to SSTRSR and
transmission of the next frame is started. If the 8th bit is transmitted while the TDRE bit is set to 1, the TEND
bit in the SSSR register is set to 1 (the TDRE bit is set to 1 when the last bit of the transmit data is transmitted)
and the state is retained. The TEI interrupt request is generated when the TEIE bit in the SSER register is set to
1 (transmit-end interrupt request enabled). The SSCK pin is fixed “H” after transmit-end.
Transmission cannot be performed while the ORER bit in the SSSR register is set to 1 (overrun error). Confirm
that the ORER bit is set to 0 before transmission.
Figure 16.14 shows a Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode).
• SSUMS = 0 (clock synchronous communication mode), CPHS = 0 (data change at

odd numbers), and CPOS = 0 (“H” when clock stops)
SSCK
SSO b0 b1 b7 b0 b1 b7
1 frame 1 frame
TDRE bit in 1
SSSR register TEI interrupt request
0
generation
TEND bit in 1 TXI interrupt request generation

SSSR register
0
Processing
by program Write data to SSTDR register
Figure 16.13 Example of Clock Synchronous Serial I/O with Chip Select Operation for Data
Transmission (Clock Synchronous Communication Mode)
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REJ09B0244-0300
Start
Initialization
(1) Read TDRE bit in SSSR register (1) After reading the SSSR register and confirming
that the TDRE bit is set to 1, write the transmit
data to the SSTDR register. When the transmit
data is written to the SSTDR register, the TDRE
No
www.DataSheet4U.com TDRE = 1 ? bit is automatically set to 0.
Yes
Write transmit data to SSTDR register
Data
Yes
(2) transmission (2) Determine whether data transmission continues.
continues?
No
(3) Read TEND bit in SSSR register

(3) When data transmission is completed, the TEND
bit is set to 1. Set the TEND bit to 0 and the TE bit
to 0 and complete transmit mode.
No
TEND = 1 ?
Yes
SSSR register TEND bit ← 0(1)
SSER register TE bit ← 0
End
NOTE:
1. Write 0 after reading 1 to set the TEND bit to 0.
Figure 16.14 Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode)
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REJ09B0244-0300
16.2.5.3 Data Reception

Figure 16.15 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation for Data
Reception (Clock Synchronous Communication Mode).
During data reception, clock synchronous serial I/O with chip select operates as described below. When the
clock synchronous serial I/O with chip select is set as the master device, it outputs a synchronous clock and
inputs data. When clock synchronous serial I/O with chip select is set as a slave device, it inputs data
synchronized with the input clock.
When clock synchronous serial I/O with chip select is set as a master device, it outputs a receive clock and starts
receiving by performing dummy read of the SSRDR register.
After 8 bits of data are received, the RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and
receive data is stored in the SSRDR register. When the RIE bit in the SSER register is set to 1 (RXI and OEI
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interrupt requests enabled), the RXI interrupt request is generated. If the SSDR register is read, the RDRF bit is
automatically set to 0 (no data in the SSRDR register).
Read the receive data after setting the RSSTP bit in the SSCRH register to 1 (after receiving 1 byte of data, the
receive operation is completed). Clock synchronous serial I/O with chip select outputs a clock for receiving 8
bits of data and stops. After that, set the RE bit in the SSER register to 0 (receive disabled) and the RSSTP bit to
0 (receive operation is continued after receiving the 1 byte of data) and read the receive data. If the SSRDR
register is read while the RE bit is set to 1 (receive enabled), a receive clock is output again.
When the 8th clock rises while the RDRF bit is set to 1, the ORER bit in the SSSR register is set to 1 (overrun
error: OEI) and the operation is stopped. When the ORER bit is set to 1, receive cannot be performed. Confirm
that the ORER bit is set to 0 before restarting receive.
Figure 16.16 shows a Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication
Mode).
• SSUMS = 0 (clock synchronous communication mode), CPHS = 0 (data download at

even edges), and CPOS bit = 0 (“H” when clock stops)
SSCK
SSI b0 b7 b0 b7 b0 b7
1 frame 1 frame
RDRF bit in 1
SSSR register
0
RXI interrupt request RXI interrupt request
RSSTP bit in 1 generation generation
SSCRH register RXI interrupt request
0 generation
Processing Dummy read in Read data in SSRDR Set RSSTP bit to 1 Read data in
by program SSRDR register register SSRDR register
Figure 16.15 Example of Clock Synchronous Serial I/O with Chip Select Operation for Data
Reception (Clock Synchronous Communication Mode)
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REJ09B0244-0300
Start
Initialization
(1) Dummy read of SSRDR register (1) After setting each register in the clock synchronous
serial I/O with chip select register, a dummy read of
the SSRDR register is performed and the receive
operation is started.
(2) Last data Yes
received? (2) Determine whether it is the last 1 byte of data to be
www.DataSheet4U.com received. If so, set to stop after the data is received.
No
Read ORER bit in SSSR register
Yes
(3) ORER = 1 ? (3) If a receive error occurs, perform error
(6) Processing after reading the ORER bit. Then set
the ORER bit to 0. Transmission/reception cannot
No be restarted while the ORER bit is set to 1.
Read RDRF bit in SSSR register
(4) No (4) Confirm that the RDRF bit is set to 1. If the RDRF
RDRF = 1 ? bit is set to 1, read the receive data in the SSRDR
register. When the SSRDR register is read, the
Yes RDRF bit is automatically set to 0.
Read receive data in SSRDR register
(5) SSCRH register RSSTP bit ← 1 (5) Before the last 1 byte of data is received, set the
RSSTP bit to 1 and stop after the data is
received.
Read ORER bit in SSSR register
Yes
(6) ORER = 1 ?
No
Read RDRF in SSSR register
No (7) Confirm that the RDRF bit is set to 1. When the

RDRF = 1 ? receive operation is completed, set the RSSTP bit to
(7) 0 and the RE bit to 0 before reading the last 1 byte
Yes of data. If the SSRDR register is read before setting
the RE bit to 0, the receive operation is restarted
SSCRH register RSSTP bit ← 0 again.
Overrun
SSER register RE bit ← 0 error
processing
End
Figure 16.16 Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication
Mode)
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16.2.5.4 Data Transmission/Reception

Data transmission/reception is an operation combining data transmission and reception which were described
earlier. Transmission/reception is started by writing data to the SSTDR register.
When the 8th clock rises or the ORER bit is set to 1 (overrun error) while the TDRE bit is set to 1 (data is
transferred from registers SSTDR to SSTRSR), the transmit/receive operation is stopped.
When switching from transmit mode (TE = 1) or receive mode (RE = 1) to transmit/receive mode (Te = RE =
1), set the TE bit to 0 and RE bit to 0 before switching. After confirming that the TEND bit is set to 0 (the
TDRE bit is set to 0 when the last bit of the transmit data is transmitted), the RDRF bit is set to 0 (no data in the
SSRDR register), and the ORER bit is set to 0 (no overrun error), set bits TE and RE to 1.
Figure 16.17 shows a Sample Flowchart of Data Transmission/Reception (Clock Synchronous Communication
Mode).
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Start
Initialization
(1) Read TDRE bit in SSSR register (1) After reading the SSSR register and confirming
that the TDRE bit is set to 1, write the transmit
data to the SSTDR register. When the transmit
www.DataSheet4U.com data is written to the SSTDR register, the TDRE
No
TDRE = 1 ? bit is automatically set to 0.
Yes
Write transmit data to SSTDR register
(2) Read RDRF bit in SSSR register

(2) Confirm that the RDRF bit is set to 1. If the RDRF
bit is set to 1, read the receive data in the SSRDR
No register. When the SSRDR register is read, the
RDRF = 1 ? RDRF bit is automatically set to 0.
Yes
Data
Yes (3) Determine whether the data transmission
(3) transmission(2)
continues? continues
No
(4) Read TEND bit in SSSR register (4) When the data transmission is completed, the
TEND bit in the SSSR register is set to 1.
No
TEND = 1 ?
Yes
(5) SSSR register TEND bit ← 0(1) (5) Set the TEND bit to 0 and bits RE and TE in
(6) the SSER register to 0 before ending transmit/
receive mode.
(6) TE bit ← 0
End
NOTE:
1. Write 0 after reading 1 to set the TEND bit to 0.
Figure 16.17 Sample Flowchart of Data Transmission/Reception (Clock Synchronous

Communication Mode)
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16.2.6 Operation in 4-Wire Bus Communication Mode

In 4-wire bus communication mode, a 4-wire bus consisting of a clock line, a data input line, a data output line,
and a chip select line is used for communication. This mode includes bidirectional mode in which the data input
line and data output line function as a single pin.
The data input line and output line change according to the settings of the MSS bit in the SSCRH register and
the BIDE bit in the SSMR2 register. For details, refer to 16.2.2.1 Association between Data I/O Pins and SS
Shift Register. In this mode, clock polarity, phase, and data settings are performed by bits CPOS and CPHS in
the SSMR register. For details, refer to 16.2.1.1 Association between Transfer Clock Polarity, Phase, and
Data.
When this MCU is set as the master device, the chip select line controls output. When clock synchronous serial
I/O with chip select is set as a slave device, the chip select line controls input. When it is set as the master
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device, the chip select line controls output of the SCS pin or controls output of a general port according to the
setting of the CSS1 bit in the SSMR2 register. When the MCU is set as a slave device, the chip select line sets
the SCS pin as an input pin by setting bits CSS1 and CSS0 in the SSMR2 register to 01b.
In 4-wire bus communication mode, the MLS bit in the SSMR register is set to 0 and communication is
performed MSB-first.
16.2.6.1 Initialization in 4-Wire Bus Communication Mode

Figure 16.18 shows Initialization in 4-Wire Bus Communication Mode. Before the data transit/receive
operation, set the TE bit in the SSER register to 0 (transmit disabled), the RE bit in the SSER register to 0
(receive disabled), and initialize the clock synchronous serial I/O with chip select.
To change the communication mode or format, set the TE bit to 0 and the RE bit to 0 before making the change.
Setting the RE bit to 0 does not change the settings of flags RDRF and ORER or the contents of the SSRDR
register.
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Start

TE bit ← 0
SSMR2 register SSUMS bit ← 1
(1) SSMR register Set bits CPHS and CPOS (1) The MLS bit is set to 0 for MSB-first transfer.
www.DataSheet4U.com MLS bits ← 0 The clock polarity and phase are set by bits
CPHS and CPOS.
SSCRH register Set MSS bit
SSMR2 register SCKS bit ← 1 (2) Set the BIDE bit to 1 in bidirectional mode and
Set bits SOOS, CSS0 to set the I/O of the SCS pin by bits CSS0 and
(2) CSS1.
CSS1, and BIDE
SSCRH register Set bits CKS0 to CKS2

Set RSSTP bit
SSSR register ORER bit ← 0(1)
SSER register RE bit ← 1 (receive)

TE bit ← 1 (transmit)
Set bits RIE, TEIE, and TIE
End
NOTE:
1. Write 0 after reading 1 to set the ORER bit to 0.
Figure 16.18 Initialization in 4-Wire Bus Communication Mode
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16.2.6.2 Data Transmission

Figure 16.19 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation during Data
Transmission (4-Wire Bus Communication Mode). During the data transmit operation, clock synchronous
serial I/O with chip select operates as described below.
When the MCU is set as the master device, it outputs a synchronous clock and data. When the MCU is set as a
slave device, it outputs data in synchronization with the input clock while the SCS pin is “L”.
When the transmit data is written to the SSTDR register after setting the TE bit to 1 (transmit enabled), the
TDRE bit is automatically set to 0 (data has not been transferred from registers SSTDR to SSTRSR) and the
data is transferred from registers SSTDR to SSTRSR. After the TDRE bit is set to 1 (data is transferred from
registers SSTDR to SSTRSR), transmission starts. When the TIE bit in the SSER register is set to 1, a TXI
interrupt request is generated.
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After 1 frame of data is transferred while the TDRE bit is set to 0, the data is transferred from registers SSTDR
to SSTRSR and transmission of the next frame is started. If the 8th bit is transmitted while TDRE is set to 1,
TEND in the SSSR register is set to 1 (when the last bit of the transmit data is transmitted, the TDRE bit is set
to 1) and the state is retained. If the TEIE bit in the SSER register is set to 1 (transmit-end interrupt requests
enabled), a TEI interrupt request is generated. The SSCK pin remains “H” after transmit-end and the SCS pin is
held “H”. When transmitting continuously while the SCS pin is held “L”, write the next transmit data to the
SSTDR register before transmitting the 8th bit.
Transmission cannot be performed while the ORER bit in the SSSR register is set to 1 (overrun error). Confirm
that the ORER bit is set to 0 before transmission.
In contrast to the clock synchronous communication mode, the SSO pin is placed in high-impedance state while
the SCS pin is placed in high-impedance state when operating as a master device and the SSI pin is placed in
high-impedance state while the SCS pin is placed in “H” input state when operating as a slave device.
The sample flowchart is the same as that for the clock synchronous communication mode (refer to Figure 16.14
Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode)).
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REJ09B0244-0300
• CPHS bit = 0 (data change at odd edges) and CPOS bit = 0 (“H” when clock stops)
High-impedance
SCS
(output)
SSCK
1 frame 1 frame
www.DataSheet4U.com
TDRE bit in 1
SSSR register TEI interrupt request is
0
generated
TXI interrupt request is TXI interrupt request is
TEND bit in 1
generated generated
SSSR register
0
Processing Data write to SSTDR register

by program
• CPHS bit = 1 (data change at even edges) and CPOS bit = 0 (“H” when clock stops)
High-impedance
SCS
(output)
SSCK
1 frame 1 frame
TDRE bit in 1
SSSR register TEI interrupt request is
0 generated
TXI interrupt request is TXI interrupt request is

TEND bit in 1
generated generated
SSSR register
0
Processing Data write to SSTDR register

by program
CPHS, CPOS: Bits in SSMR register
Figure 16.19 Example of Clock Synchronous Serial I/O with Chip Select Operation during Data
Transmission (4-Wire Bus Communication Mode)
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16.2.6.3 Data Reception

Figure 16.20 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation during Data
Reception (4-Wire Bus Communication Mode). During data reception, clock synchronous serial I/O with chip
select operates as described below.
When the MCU is set as the master device, it outputs a synchronous clock and inputs data. When the MCU is
set as a slave device, it outputs data synchronized with the input clock while the SCS pin receives “L” input.
When the MCU is set as the master device, it outputs a receive clock and starts receiving by performing a
dummy read of the SSRDR register.
After 8 bits of data are received, the RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and
receive data is stored in the SSRDR register. When the RIE bit in the SSER register is set to 1 (RXI and OEI
interrupt requests enabled), an RXI interrupt request is generated. When the SSRDR register is read, the RDRF
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bit is automatically set to 0 (no data in the SSRDR register).
Read the receive data after setting the RSSTP bit in the SSCRH register to 1 (after receiving 1-byte data, the
receive operation is completed). Clock synchronous serial I/O with chip select outputs a clock for receiving 8
bits of data and stops. After that, set the RE bit in the SSER register to 0 (receive disabled) and the RSSTP bit to
0 (receive operation is continued after receiving 1-byte data) and read the receive data. When the SSRDR
register is read while the RE bit is set to 1 (receive enabled), a receive clock is output again.
When the 8th clock rises while the RDRF bit is set to 1, the ORER bit in the SSSR register is set to 1 (overrun
error: OEI) and the operation is stopped. When the ORER bit is set to 1, reception cannot be performed.
Confirm that the ORER bit is set to 0 before restarting reception.
The timing with which bits RDRF and ORER are set to 1 varies depending on the setting of the CPHS bit in the
SSMR register. Figure 16.20 shows when bits RDRF and ORER are set to 1.
When the CPHS bit is set to 1 (data download at the odd edges), bits RDRF and ORER are set to 1 at some
point during the frame.
The sample flowchart is the same as that for the clock synchronous communication mode (refer to Figure 16.16
Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication Mode)).
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REJ09B0244-0300
• CPHS bit = 0 (data download at even edges) and CPOS bit = 0 (“H” when clock stops)
High-impedance
SCS
(output)
SSCK
www.DataSheet4U.com 1 frame 1 frame
RDRF bit in 1
SSSR register
0
1 RXI interrupt request RXI interrupt request

RSSTP bit in
is generated is generated RXI interrupt request
SSCRH register
0 is generated
Processing Dummy read in Data read in SSRDR Set RSSTP Data read in SSRDR
by program SSRDR register register bit to 1 register
• CPHS bit = 1 (data download at odd edges) and CPOS bit = 0 (“H” when clock stops)
High-impedance
SCS
(output)
SSCK
1 frame 1 frame
RDRF bit in 1
SSSR register
0
RXI interrupt request RXI interrupt request

RSSTP bit in 1
is generated is generated RXI interrupt request
SSCRH register
0 is generated
Processing Dummy read in Data read in SSRDR Set RSSTP Data read in SSRDR
by program SSRDR register register bit to 1 register
CPHS and CPOS: Bit in SSMR register
Figure 16.20 Example of Clock Synchronous Serial I/O with Chip Select Operation during Data
Reception (4-Wire Bus Communication Mode)
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16.2.7 SCS Pin Control and Arbitration

When setting the SSUMS bit in the SSMR2 register to 1 (4-wire bus communication mode) and the CSS1 bit in
the SSMR2 register to 1 (functions as SCS output pin), set the MSS bit in the SSCRH register to 1 (operates as
the master device) and check the arbitration of the SCS pin before starting serial transfer. If clock synchronous
serial I/O with chip select detects that the synchronized internal SCS signal is held “L” in this period, the CE bit
in the SSSR register is set to 1 (conflict error) and the MSS bit is automatically set to 0 (operates as a slave
device).
Figure 16.21 shows the Arbitration Check Timing.
Future transmit operations are not performed while the CE bit is set to 1. Set the CE bit to 0 (no conflict error)
before starting transmission.
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SCS input
Internal SCS
(synchronization)
MSS bit in 1
SSCRH register 0
Transfer start
Data write to
SSTDR register
CE
High-impedance
SCS output
Maximum time of SCS internal
synchronization
During arbitration detection
Figure 16.21 Arbitration Check Timing
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16.2.8 Notes on Clock Synchronous Serial I/O with Chip Select

Set the IICSEL bit in the PMR register to 0 (select clock synchronous serial I/O with chip select function) to use
the clock synchronous serial I/O with chip select function.
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16.3 I2C bus Interface

The I2C bus interface is the circuit that performs serial communication based on the data transfer format of the
Philips I2C bus.
Table 16.5 lists the I2C bus Interface Specifications, Figure 16.22 shows a Block Diagram of I2C bus interface, and
Figure 16.23 shows the External Circuit Connection Example of Pins SCL and SDA. Figures 16.24 to 16.31 show
the registers associated with the I2C bus interface.
* I2C bus is a trademark of Koninklijke Philips Electronics N. V.
Table 16.5 I2C bus Interface Specifications

www.DataSheet4U.com Item Specification
Communication formats • I C bus format
2
- Selectable as master/slave device
- Continuous transmit/receive operation (because the shift register, transmit
data register, and receive data register are independent)
- Start/stop conditions are automatically generated in master mode
- Automatic loading of acknowledge bit during transmission
- Bit synchronization/wait function (In master mode, the state of the SCL
signal is monitored per bit and the timing is synchronized automatically. If
the transfer is not possible yet, the SCL signal goes “L” and the interface
stands by.)
- Support for direct drive of pins SCL and SDA (N-channel open drain output)
• Clock synchronous serial format
- Continuous transmit/receive operation (because the shift register, transmit
data register, and receive data register are independent)
I/O pins SCL (I/O): Serial clock I/O pin
SDA (I/O): Serial data I/O pin
Transfer clocks • When the MST bit in the ICCR1 register is set to 0
The external clock (input from the SCL pin)
• When the MST bit in the ICCR1 register is set to 1
The internal clock selected by bits CKS0 to CKS3 in the ICCR1 register
(output from the SCL pin)
Receive error detection • Overrun error detection (clock synchronous serial format)
Indicates an overrun error during reception. When the last bit of the next data
item is received while the RDRF bit in the ICSR register is set to 1 (data in the
ICDRR register), the AL bit is set to 1.
Interrupt sources • I C bus format .................................. 6 sources(1)
2
Transmit data empty (including when slave address matches), transmit ends,
receive data full (including when slave address matches), arbitration lost,
NACK detection, and stop condition detection.
• Clock synchronous serial format ...... 4 sources(1)
Transmit data empty, transmit ends, receive data full and overrun error
Select functions 2
• I C bus format
- Selectable output level for acknowledge signal during reception
• Clock synchronous serial format
- MSB-first or LSB-first selectable as data transfer direction
NOTE:
1. All sources use one interrupt vector for I2C bus interface.
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REJ09B0244-0300
f1
Transfer clock
generation
circuit
Output
SCL ICCR1 register
control
Transmit/receive
control circuit ICCR2 register
www.DataSheet4U.com Noise
canceller ICMR register
ICDRT register
Output SAR register

SDA
control ICDRS register
Data bus
Noise
Address comparison
canceller
circuit
ICDRR register
Bus state judgment

circuit
Arbitration judgment
ICSR register
circuit
ICIER register
Interrupt generation
circuit
Interrupt request
(TXI, TEI, RXI, STPI, NAKI)
Figure 16.22 Block Diagram of I2C bus interface
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REJ09B0244-0300
VCC VCC
SCL SCL
SCL input
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SCL output
SDA SDA
SDA input
SDA output
SCL SCL
(Master) SCL input SCL input
SCL output SCL output
SDA SDA
SDA input SDA input
SDA output SDA output
(Slave 1) (Slave 2)
Figure 16.23 External Circuit Connection Example of Pins SCL and SDA
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IIC bus Control Register 1

b7 b6 b5 b4 b3 b2 b1 b0

ICCR1 00B8h 00h
Transmit clock select bits 3 to b3 b2 b1 b0
0(1) 0 0 0 0 : f1/28
CKS0 0 0 0 1 : f1/40 RW
0 0 1 0 : f1/48
www.DataSheet4U.com 0 0 1 1 : f1/64
0 1 0 0 : f1/80
CKS1 0 1 0 1 : f1/100 RW
0 1 1 0 : f1/112
0 1 1 1 : f1/128
1 0 0 0 : f1/56
1 0 0 1 : f1/80
CKS2 RW
1 0 1 0 : f1/96
1 0 1 1 : f1/128
1 1 0 0 : f1/160
1 1 0 1 : f1/200
CKS3 1 1 1 0 : f1/224 RW
1 1 1 1 : f1/256
Transfer/receive select bit b5 b4

(2, 3, 6)
TRS 0 0 : Slave Receive Mode(4) RW
0 1 : Slave Transmit Mode
Master/slave select bit(5, 6) 1 0 : Master Receive Mode
MST 1 1 : Master Transmit Mode RW
Receive disable bit After reading the ICDRR register w hile the TRS bit
is set to 0
RCVD 0 : Maintains the next receive operation RW
1 : Disables the next receive operation
IIC bus interface enable bit 0 : This module is halted

(Pins SCL and SDA are set to port function)
ICE 1 : This module is enabled for transfer RW
operations
(Pins SCL and SDA are bus drive state)
NOTES:
1. Set according to the necessary transfer rate in master mode. Refer to Table 16.6 Transfer Rate
Examples for the transfer rate. This bit is used for maintaining of the setup time in transmit mode of slave mode.
The time is 10Tcyc w hen the CKS3 bit is set to 0 and 20Tcyc w hen the CKS3 bit is set to 1. (1Tcyc = 1/f1(s))
2. Rew rite the TRS bit betw een transfer frames.
3. When the first 7 bit after the start condition in slave receive mode match w ith the slave address set in the SAR
register and the 8th bit is set to 1, the TRS bit is set to 1.
4. In master mode w ith the I2C bus format, w hen arbitration is lost, bits MST and TRS are set to 0
and the IIC enters slave receive mode.
5. When an overrun error occurs in master receive mode of the clock synchronous serial format, the MST bit
is set to 0 and the IIC enters slave receive mode.
6. In multimaster operation use the MOV instruction to set bits TRS and MST.
Figure 16.24 ICCR1 Register
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IIC bus Control Register 2

b7 b6 b5 b4 b3 b2 b1 b0

ICCR2 00B9h 01111101b
—
IIC control part reset bit When hang-up occurs due to communication failure
during I2C bus interface operation, w rite 1, to reset the
www.DataSheet4U.com control block of the I2C bus interface w ithout setting
IICRST RW
ports or initializing registers.

—
SCL monitor flag 0 : SCL pin is set to “L”
SCLO RO
1 : SCL pin is set to “H”
(1)
SDAO w rite protect bit When rew rite to SDAO bit, w rite 0 simultaneously.
SDAOP RW
SDA output value control When read
bit 0 : SDA pin output is held “L”
1 : SDA pin output is held “H”
SDAO When w ritten(1,2) RW
0 : SDA pin output is changed to “L”
1 : SDA pin output is changed to high-impedance
(“H” output via external pull-up resistor)
Start/stop condition When w riting to the to BBSY bit, w rite 0

generation disable bit simultaneously.(3)
SCP When read, the content is 1. RW
Writing 1 is invalid.
Bus busy bit(4) When read
0 : Bus is in released state
(SDA signal changes from “L” to “H” w hile SCL
signal is in “H” state)
1 : Bus is in occupied state
BBSY (SDA signal changes from “H” to “L” w hile SCL RW
signal is in “H” state)
When w ritten(3)
0 : Generates stop condition
1 : Generates start condition
NOTES:
1. When w riting to the SDAO bit, w rite 0 to the SDAOP bit using the MOV instruction simultaneously.
2. Do not w rite during a transfer operation.
3. This bit is enabled in master mode. When w riting to the BBSY bit, w rite 0 to the SCP bit using the MOV
instruction simultaneously. Execute the same w ay w hen the start condition is regenerating.
4. This bit is disabled w hen the clock synchronous serial format is used.
Figure 16.25 ICCR2 Register
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IIC bus Mode Register

b7 b6 b5 b4 b3 b2 b1 b0

ICMR 00BAh 00011000b
Bits counter 2 to 0 I2C bus format (remaining transfer bit count w hen
read out and data bit count of next transfer w hen
w ritten).(1,2)
b2 b1 b0
www.DataSheet4U.com BC0 0 0 0 : 9 bits (3) RW

0 0 1 : 2 bits
0 1 0 : 3 bits
0 1 1 : 4 bits
1 0 0 : 5 bits
1 0 1 : 6 bits
1 1 0 : 7 bits
1 1 1 : 8 bits
BC1 Clock synchronous serial format (w hen read, the RW
remaining transfer bit count and w hen w ritten
000b).
b2 b1 b0
0 0 0 : 8 bits
0 0 1 : 1 bit
0 1 0 : 2 bits
0 1 1 : 3 bits
1 0 0 : 4 bits
BC2 RW
1 0 1 : 5 bits
1 1 0 : 6 bits
1 1 1 : 7 bits
BC w rite protect bit When rew riting bits BC0 to BC2, w rite 0
BCWP simultaneously.(2,4) RW
—
RW
(b5)
Wait insertion bit(5) 0 : No w ait
(Transfer data and acknow ledge bit
consecutively)
WAIT 1 : Wait RW
(After the clock falls for the final
data bit, “L” period is extended for tw o
transfer clocks cycles)
MSB-first/LSB-first select 0 : Data transfer w ith MSB-first(6)

MLS RW
bit 1 : Data transfer w ith LSB-first
NOTES:
1. Rew rite betw een transfer frames. When w riting values other than 000b, w rite w hen the SCL signal is “L”.
2. When w riting to bits BC0 to BC2, w rite 0 to the BCWP bit using the MOV instruction.
3. After data including the acknow ledge bit is transferred, these bits are automatically set to 000b. When the start
condition is detected, these bits are automatically set to 000b.
4. Do not rew rite w hen the clock synchronous serial format is used.
5. The setting value is enabled in master mode of the I2C bus format. It is disabled in slave mode of the I2C
bus format or w hen the clock synchronous serial format is used.
6. Set to 0 w hen the I2C bus format is used.
Figure 16.26 ICMR Register
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IIC bus Interrupt Enable Register

b7 b6 b5 b4 b3 b2 b1 b0

ICIER 00BBh 00h
Transmit acknow ledge 0 : 0 is transmitted as acknow ledge bit in
select bit receive mode.
ACKBT 1 : 1 is transmitted as acknow ledge bit in RW
receive mode.
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Receive acknow ledge bit 0 : Acknow ledge bit received from
receive device in transmit mode is set to 0.
ACKBR 1 : Acknow ledge bit received from RO
receive device in transmit mode is set to 1.
Acknow ledge bit judgment 0 : Value of receive acknow ledge bit is ignored
select bit and continuous transfer is performed.
ACKE 1 : When receive acknow ledge bit is set to 1, RW
continuous transfer is halted.
Stop condition detection 0 : Disables stop condition detection interrupt
interrupt enable bit request
STIE 1 : Enables stop condition detection interrupt RW
request(2)
NACK receive interrupt 0 : Disables NACK receive interrupt request and
enable bit arbitration lost/overrun error interrupt request
NAKIE 1 : Enables NACK receive interrupt request and RW
arbitration lost/overrun error interrupt request(1)
Receive interrupt enable 0 : Disables receive data full and overrun
bit error interrupt request
RIE 1 : Enables receive data full and overrun RW
error interrupt request(1)
Transmit end interrupt 0 : Disables transmit end interrupt request
TEIE enable bit 1 : Enables transmit end interrupt request RW
Transmit interrupt enable 0 : Disables transmit data empty interrupt request

TIE bit 1 : Enables transmit data empty interrupt request RW
NOTES:
1. An overrun error interrupt request is generated w hen the clock synchronous format is used.
2. Set the STIE bit to 1 (enable stop condition detection interrupt request) w hen the STOP bit in the ICSR register is set
to 0.
Figure 16.27 ICIER Register
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IIC bus Status Register(7)

b7 b6 b5 b4 b3 b2 b1 b0

ICSR 00BCh 0000X000b
General call address When the general call address is detected, this flag
ADZ RW
recognition flag(1,2) is set to 1.
Slave address recognition This flag is set to 1 w hen the first frame follow ing
flag(1) start condition matches bits SVA0 to SVA6 in the
AAS SAR register in slave receive mode. (Detect the RW
www.DataSheet4U.com slave address and generate call address)
Arbitration lost When the I2C bus format is used, this flag indicates
flag/overrun error flag(1) that arbitration has been lost in master mode. In the
follow ing cases, this flag is set to 1(3).
• When the internal SDA signal and SDA pin
level do not match at the rise of the SCL signal
in master transmit mode
AL • When the start condition is detected and the SDA RW
pin is held “H” in master transmit/receive mode
This flag indicates an overrun error w hen the clock
synchronous format is used.
In the follow ing case, this flag is set to 1.
• When the last bit of the next data item is
received w hile the RDRF bit is set to 1
Stop condition detection When the stop condition is detected after the frame
STOP RW
flag(1) is transferred, this flag is set to 1.
No acknow ledge detection When no acknow ledge is detected from the receive
NACKF RW
flag(1,4) device after transmission, this flag is set to 1.
Receive data register When receive data is transferred from in registers
RDRF RW
full(1,5) ICDRS to ICDRR , this flag is set to 1.
Transmit end(1,6) When the 9th clock cycle of the SCL signal in the I2C
bus format occurs w hile the TDRE bit is set to 1, this
TEND flag is set to 1. RW
This flag is set to 1 w hen the final bit of the transmit
frame is transmitted in the clock synchronous format.
Transmit data empty (1,6) In the follow ing cases, this flag is set to 1.
• Data is transferred from registers ICDRT to ICDRS
and the ICDRT register is empty
• When setting the TRS bit in the ICCR1
TDRE register to 1 (transmit mode) RW
• When generating the start condition
(including retransmit)
• When changing from slave receive mode to
slave transmit mode
NOTES:
1. Each bit is set to 0 by reading 1 before w riting 0.
2. This flag is enabled in slave receive mode of the I2C bus format.
3. When tw o or more master devices attempt to occupy the bus at nearly the same time, if the I2C bus Interface
monitors the SDA pin and the data w hich the I2C bus Interface transmits is different, the AL flag is set to 1 and the
bus is occupied by another master.
4. The NACKF bit is enabled w hen the ACKE bit in the ICIER register is set to 1 (w hen the receive acknow ledge bit is
set to 1, transfer is halted).
5. The RDRF bit is set to 0 w hen reading data from the ICDRR register.
6. Bits TEND and TDRE are set to 0 w hen w riting data to the ICDRT register.
7. When accessing the ICSR register continuously, insert one or more NOP instructions betw een the instructions to
access it.
Figure 16.28 ICSR Register
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Slave Address Register

b7 b6 b5 b4 b3 b2 b1 b0

SAR 00BDh 00h
Format select bit 0 : I2C bus format
FS RW
1 : Clock synchronous serial format
SVA0 Slave address 6 to 0 Set an address different from that of the other RW
SVA1 slave devices w hich are connected to the I2C RW
www.DataSheet4U.com bus. When the 7 high-order bits of the first frame
SVA2 RW
SVA3 transmitted after the starting condition match bits RW
SVA4 SVA0 to SVA6 in slave mode of the I2C bus RW
format, the MCU operates as a slave device.
SVA5 RW
SVA6 RW
IIC bus Transmit Data Register

b7 b6 b5 b4 b3 b2 b1 b0

ICDRT 00BEh FFh
Function RW
Store transmit data
When it is detected that the ICDRS register is empty, the stored transmit data item is
transferred to the ICDRS register and data transmission starts.
When the next transmit data item is w ritten to the ICDRT register during transmission of the RW
data in the ICDRS register, continuous transmit is enabled. When the MLS bit in the ICMR
register is set to 1 (data transferred LSB-first) and after the data is w ritten to the ICDRT
register, the MSB-LSB inverted data is read.
Figure 16.29 Registers SAR and ICDRT
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IIC bus Receive Data Register

b7 b6 b5 b4 b3 b2 b1 b0

ICDRR 00BFh FFh
Function RW
Store receive data
When the ICDRS register receives 1 byte of data, the receive data is transferred to the ICDRR RO
register and the next receive operation is enabled.
www.DataSheet4U.com
IIC bus Shift Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ICDRS
Function RW
This register is used to transmit and receive data.
The transmit data is transferred from registers ICRDT to the ICDRS and data is transmitted
from the SDA pin w hen transmitting. —
After 1 byte of data received, data is transferred from registers ICDRS to ICDRR w hile
receiving.
Figure 16.30 Registers ICDRR and ICDRS
Port Mode Register

b7 b6 b5 b4 b3 b2 b1 b0

PMR 00F8h 00h
—
(b3-b0)
U1PINSEL RW
—
(b6-b5)
IICSEL RW
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REJ09B0244-0300
16.3.1 Transfer Clock

When the MST bit in the ICCR1 register is set to 0, the transfer clock is the external clock input from the SCL
pin. When the MST bit in the ICCR1 register is set to 1, the transfer clock is the internal clock selected by bits
CKS0 to CKS3 in the ICCR1 register and the transfer clock is output from the SCL pin.
Table 16.6 lists the Transfer Rate Examples.
Table 16.6 Transfer Rate Examples

ICCR1 Register Transfer Transfer Rate
CKS3 CKS2 CKS1 CKS0 Clock f1 = 5 MHz f1 = 8 MHz f1 = 10 MHz f1 = 16 MHz f1 = 20 MHz
0 0 0 0 f1/28 179 kHz 286 kHz 357 kHz 571 kHz 714 kHz
www.DataSheet4U.com
1 f1/40 125 kHz 200 kHz 250 kHz 400 kHz 500 kHz
1 0 f1/48 104 kHz 167 kHz 208 kHz 333 kHz 417 kHz
1 f1/64 78.1 kHz 125 kHz 156 kHz 250 kHz 313 kHz
1 0 0 f1/80 62.5 kHz 100 kHz 125 kHz 200 kHz 250 kHz
1 f1/100 50.0 kHz 80.0 kHz 100 kHz 160 kHz 200 kHz
1 0 f1/112 44.6 kHz 71.4 kHz 89.3 kHz 143 kHz 179 kHz
1 f1/128 39.1 kHz 62.5 kHz 78.1 kHz 125 kHz 156 kHz
1 0 0 0 f1/56 89.3 kHz 143 kHz 179 kHz 286 kHz 357 kHz
1 f1/80 62.5 kHz 100 kHz 125 kHz 200 kHz 250 kHz
1 0 f1/96 52.1 kHz 83.3 kHz 104 kHz 167 kHz 208 kHz
1 f1/128 39.1 kHz 62.5 kHz 78.1 kHz 125 kHz 156 kHz
1 0 0 f1/160 31.3 kHz 50.0 kHz 62.5 kHz 100 kHz 125 kHz
1 f1/200 25.0 kHz 40.0 kHz 50.0 kHz 80.0 kHz 100 kHz
1 0 f1/224 22.3 kHz 35.7 kHz 44.6 kHz 71.4 kHz 89.3 kHz
1 f1/256 19.5 kHz 31.3 kHz 39.1 kHz 62.5 kHz 78.1 kHz
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16.3.2 Interrupt Requests

The I2 C bus interface has six interrupt requests when the I2C bus format is used and four interrupt requests
when the clock synchronous serial format is used.
Table 16.7 lists the Interrupt Requests of I2C bus Interface.
Since these interrupt requests are allocated at the I2C bus interface interrupt vector table, determining the source
bit by bit is necessary.
Table 16.7 Interrupt Requests of I2C bus Interface

Interrupt Request Generation Condition Format
I2C bus Clock
www.DataSheet4U.com Synchronous
Serial
Transmit data empty TXI TIE = 1 and TDRE = 1 Enabled Enabled
Transmit ends TEI TEIE = 1 and TEND = 1 Enabled Enabled
Receive data full RXI RIE = 1 and RDRF = 1 Enabled Enabled
Stop condition detection STPI STIE = 1 and STOP = 1 Enabled Disabled
NACK detection NAKI NAKIE = 1 and AL = 1 (or Enabled Disabled
Arbitration lost/overrun error NAKIE = 1 and NACKF = 1) Enabled Enabled
STIE, NAKIE, RIE, TEIE, TIE: Bits in ICIER register
AL, STOP, NACKF, RDRF, TEND, TDRE: Bits in ICSR register
When the generation conditions listed in Table 16.7 are met, an I2C bus interface interrupt request is generated.
Set the interrupt generation conditions to 0 by the I2C bus interface interrupt routine. However, bits TDRE and
TEND are automatically set to 0 by writing transmit data to the ICDRT register and the RDRF bit is
automatically set to 0 by reading the ICDRR register. When writing transmit data to the ICDRT register, the
TDRE bit is set to 0. When data is transferred from registers ICDRT to ICDRS, the TDRE bit is set to 1 and by
further setting the TDRE bit to 0, 1 additional byte may be transmitted.
Set the STIE bit to 1 (enable stop condition detection interrupt request) when the STOP bit is set to 0.
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16.3.3 I2C bus Interface Mode
16.3.3.1 I2C bus Format

Setting the FS bit in the SAR register to 0 enables communication in I2C bus format.
Figure 16.32 shows the I2C bus Format and Bus Timing. The 1st frame following the start condition consists of
8 bits.
(1) I2C bus format
(a) I2C bus format (FS = 0)

www.DataSheet4U.com
S SLA R/W A DATA A A/A P
1 7 1 1 n 1 1 1
Transfer bit count (n = 1 to 8)
1 m
Transfer frame count (m = from 1)
(b) I2C bus format (when start condition is retransmitted, FS = 0)
S SLA R/W A DATA A/A S SLA R/W A DATA A/A P
1 7 1 1 n1 1 1 7 1 1 n2 1 1
1 m1 1 m2
Upper: Transfer bit count (n1, n2 = 1 to 8)

Lower: Transfer frame count (m1, m2 = 1 or more)
(2) I2C bus timing
SDA
SCL 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9
S SLA R/W A DATA A DATA A P

Explanation of symbols
S : Start condition
The master device changes the SDA signal from “H” to “L” while the SCL signal is held “H”.
SLA : Slave address
R/W : Indicates the direction of data transmit/receive
Data is transmitted from the slave device to the master device when R/W value is 1 and from the master device to the slave device when
R/W value is 0.
A : Acknowledge
The receive device sets the SDA signal to “L”.
DATA : Transmit / receive data
P : Stop condition
The master device changes the SDA signal from “L” to “H” while the SCL signal is held “H”.
Figure 16.32 I2C bus Format and Bus Timing
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16.3.3.2 Master Transmit Operation

In master transmit mode, the master device outputs the transmit clock and data, and the slave device returns an
acknowledge signal.
Figures 16.33 and 16.34 show the Operating Timing in Master Transmit Mode (I2C bus Interface Mode).
The transmit procedure and operation in master transmit mode are as follows.
(1) Set the STOP bit in the ICSR register to 0 to reset it. Then set the ICE bit in the ICCR1 register to 1
(transfer operation enabled). Then set bits WAIT and MLS in the ICMR register and set bits CKS0 to
CKS3 in the ICCR1 register (initial setting).
(2) Read the BBSY bit in the ICCR2 register to confirm that the bus is free. Set bits TRS and MST in the
ICCR1 register to master transmit mode. The start condition is generated by writing 1 to the BBSY bit
www.DataSheet4U.com and 0 to the SCP bit by the MOV instruction.
(3) After confirming that the TDRE bit in the ICSR register is set to 1 (data is transferred from registers
ICDRT to ICDRS), write transmit data to the ICDRT register (data in which a slave address and R/W
are indicated in the 1st byte). At this time, the TDRE bit is automatically set to 0, data is transferred
from registers ICDRT to ICDRS, and the TDRE bit is set to 1 again.
(4) When transmission of 1 byte of data is completed while the TDRE bit is set to 1, the TEND bit in the
ICSR register is set to 1 at the rise of the 9th transmit clock pulse. Read the ACKBR bit in the ICIER
register, and confirm that the slave is selected. Write the 2nd byte of data to the ICDRT register. Since
the slave device is not acknowledged when the ACKBR bit is set to 1, generate the stop condition. The
stop condition is generated by the writing 0 to the BBSY bit and 0 to the SCP bit by the MOV
instruction. The SCL signal is held “L” until data is available and the stop condition is generated.
(5) Write the transmit data after the 2nd byte to the ICDRT register every time the TDRE bit is set to 1.
(6) When writing the number of bytes to be transmitted to the ICDRT register, wait until the TEND bit is
set to 1 while the TDRE bit is set to 1. Or wait for NACK (the NACKF bit in the ICSR register is set to
1) from the receive device while the ACKE bit in the ICIER register is set to 1 (when the receive
acknowledge bit is set to 1, transfer is halted). Then generate the stop condition before setting bits
TEND and NACKF to 0.
(7) When the STOP bit in the ICSR register is set to 1, return to slave receive mode.
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SCL
(master output) 1 2 3 4 5 6 7 8 9 1 2
SDA
(master output) b7 b6 b5 b4 b3 b2 b1 b0 b7 b6
Slave address
R/W
SDA
A
(slave output)
1
TDRE bit in
www.DataSheet4U.com ICSR register
0
1
TEND bit in
ICSR register
0
ICDRT register Address + R/W Data 1 Data 2
ICDRS register Address + R/W Data 1
Processing (2) Instruction of (3) Data write to ICDRT (4) Data write to ICDRT (5) Data write to ICDRT
by program start condition register (1st byte) register (2nd byte) register (3rd byte)
generation
Figure 16.33 Operating Timing in Master Transmit Mode (I2C bus Interface Mode) (1)
SCL
(master output) 9 1 2 3 4 5 6 7 8 9
SDA
b7 b6 b5 b4 b3 b2 b1 b0
(master output)
SDA
A A/A
(slave output)
1
TDRE bit in
ICSR register
0
1
TEND bit in
ICSR register
0
ICDRT register Data n
ICDRS register Data n
Processing (3) Data write to ICDRT (6) Generate stop condition and
by program register set TEND bit to 0
(7) Set to slave receive mode
Figure 16.34 Operating Timing in Master Transmit Mode (I2C bus Interface Mode) (2)
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16.3.3.3 Master Receive Operation

In master receive mode, the master device outputs the receive clock, receives data from the slave device, and
returns an acknowledge signal.
Figures 16.35 and 16.36 show the Operating Timing in Master Receive Mode (I2C bus Interface Mode).
The receive procedure and operation in master receive mode are shown below.
(1) After setting the TEND bit in the ICSR register to 0, switch from master transmit mode to master
receive mode by setting the TRS bit in the ICCR1 register to 0. Also, set the TDRE bit in the ICSR
register to 0.
(2) When performing the dummy read of the ICDRR register and starting the receive operation, the receive
clock is output in synchronization with the internal clock and data is received. The master device
www.DataSheet4U.com outputs the level set by the ACKBT bit in the ICIER register to the SDA pin at the rising edge of the 9th
clock cycle of the receive clock.
(3) The 1-frame data receive is completed and the RDRF bit in the ICSR register is set to 1 at the rise of the
9th clock cycle. At this time, when reading the ICDRR register, the received data can be read and the
RDRF bit is set to 0 simultaneously.
(4) Continuous receive operation is enabled by reading the ICDRR register every time the RDRF bit is set
to 1. If the 8th clock cycle falls after the ICDRR register is read by another process while the RDRF bit
is set to 1, the SCL signal is fixed “L” until the ICDRR register is read.
(5) If the next frame is the last receive frame and the RCVD bit in the ICCR1 register is set to 1 (disables
the next receive operation) before reading the ICDRR register, stop condition generation is enabled
after the next receive operation.
(6) When the RDRF bit is set to 1 at the rise of the 9th clock cycle of the receive clock, generate the stop
condition.
(7) When the STOP bit in the ICSR register is set to 1, read the ICDRR register and set the RCVD bit to 0
(maintain the following receive operation).
(8) Return to slave receive mode.
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Master transmit mode Master receive mode
SCL
(master output) 9 1 2 3 4 5 6 7 8 9 1
SDA
(master output) A
SDA
A b7 b6 b5 b4 b3 b2 b1 b0 b7
(slave output)
www.DataSheet4U.com
1
TDRE bit in
ICSR register
0
1
TEND bit in
ICSR register
0
1
TRS bit in
ICCR1 register
0
1
RDRF bit in
ICSR register
0
ICDRS register Data 1
ICDRR register Data 1
Processing (1) Set TEND and TRS bits to 0 before (2) Read ICDRR register (3) Read ICDRR register
by program setting TDRE bits to 0
Figure 16.35 Operating Timing in Master Receive Mode (I2C bus Interface Mode) (1)
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SCL
(master output) 9 1 2 3 4 5 6 7 8 9
SDA
(master output) A A/A
SDA
b7 b6 b5 b4 b3 b2 b1 b0
(slave output)
www.DataSheet4U.com
1
RDRF bit in
ICSR register
0
1
RCVD bit in
ICCR1 register
0
ICDRS register Data n-1 Data n
ICDRR register Data n-1 Data n
(6) Stop condition

Processing (5) Set RCVD bit to 1 before (7) Read ICDRR register before
generation
by program reading ICDRR register setting RCVD bit to 0
Figure 16.36 Operating Timing in Master Receive Mode (I2C bus Interface Mode) (2)
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16.3.3.4 Slave Transmit Operation

In slave transmit mode, the slave device outputs the transmit data while the master device outputs the receive
clock and returns an acknowledge signal.
Figures 16.37 and 16.38 show the Operating Timing in Slave Transmit Mode (I2C bus Interface Mode).
The transmit procedure and operation in slave transmit mode are as follows.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set bits WAIT and MLS in the
ICMR register and bits CKS0 to CKS3 in the ICCR1 register (initial setting). Set bits TRS and MST in
the ICCR1 register to 0 and wait until the slave address matches in slave receive mode.
(2) When the slave address matches at the 1st frame after detecting the start condition, the slave device
outputs the level set by the ACKBT bit in the ICIER register to the SDA pin at the rise of the 9th clock
www.DataSheet4U.com cycle. At this time, if the 8th bit of data (R/W) is 1, bits TRS and TDRE in the ICSR register are set to 1,
and the mode is switched to slave transmit mode automatically. Continuous transmission is enabled by
writing transmit data to the ICDRT register every time the TDRE bit is set to 1.
(3) When the TDRE bit in the ICDRT register is set to 1 after writing the last transmit data to the ICDRT
register, wait until the TEND bit in the ICSR register is set to 1 while the TDRE bit is set to 1. When the
TEND bit is set to 1, set the TEND bit to 0.
(4) The SCL signal is released by setting the TRS bit to 0 and performing a dummy read of the ICDRR
register to end the process.
(5) Set the TDRE bit to 0.
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Slave receive mode Slave transmit mode
SCL
(master output) 9 1 2 3 4 5 6 7 8 9 1
SDA A
(master output)
SCL
(slave output)
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SDA b6 b5 b4 b3 b2 b1 b0 b7
A b7
(slave output)
1
TDRE bit in
ICSR register
0
1
TEND bit in
ICSR register
0
1
TRS bit in
ICCR1 register
0
ICDRT register Data 1 Data 2 Data 3
ICDRS register Data 1 Data 2
ICDRR register
(1) Data write to ICDRT (2) Data write to ICDRT (2) Data write to ICDRT
Processing
register (data 1) register (data 2) register (data 3)
by program
Figure 16.37 Operating Timing in Slave Transmit Mode (I2C bus Interface Mode) (1)
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Slave receive
mode
Slave transmit mode
SCL
(master output) 9 1 2 3 4 5 6 7 8 9
SDA
A A
(master output)
SCL
www.DataSheet4U.com(slave output)
SDA
b7 b6 b5 b4 b3 b2 b1 b0
(slave output)
1
TDRE bit in
ICSR register
0
1
TEND bit in
ICSR register
0
1
TRS bit in
ICCR1 register
0
ICDRT register Data n
ICDRS register Data n
ICDRR register
Processing (3) Set the TEND bit to 0 (4) Dummy read of ICDRR register
by program (5) Set TDRE bit to 0
after setting TRS bit to 0
Figure 16.38 Operating Timing in Slave Transmit Mode (I2C bus Interface Mode) (2)
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16.3.3.5 Slave Receive Operation

In slave receive mode, the master device outputs the transmit clock and data, and the slave device returns an
acknowledge signal.
Figures 16.39 and 16.40 show the Operating Timing in Slave Receive Mode (I2C bus Interface Mode).
The receive procedure and operation in slave receive mode are as follows.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set bits WAIT and MLS in the
ICMR register and bits CKS0 to CKS3 in the ICCR1 register (initial setting). Set bits TRS and MST in
the ICCR1 register to 0 and wait until the slave address matches in slave receive mode.
(2) When the slave address matches at the 1st frame after detecting the start condition, the slave device
outputs the level set in the ACKBT bit in the ICIER register to the SDA pin at the rise of the 9th clock
www.DataSheet4U.com cycle. Since the RDRF bit in the ICSR register is set to 1 simultaneously, perform the dummy read (the
read data is unnecessary because it indicates the slave address and R/W).
(3) Read the ICDRR register every time the RDRF bit is set to 1. If the 8th clock cycle falls while the
RDRF bit is set to 1, the SCL signal is fixed “L” until the ICDRR register is read. The setting change of
the acknowledge signal returned to the master device before reading the ICDRR register takes affect
from the following transfer frame.
(4) Reading the last byte is performed by reading the ICDRR register in like manner.
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SCL
(master output) 9 1 2 3 4 5 6 7 8 9 1
SDA
(master output) b7 b6 b5 b4 b3 b2 b1 b0 b7
SCL
(slave output)
www.DataSheet4U.com SDA
A A
(slave output)
1
RDRF bit in
ICSR register
0
Processing (2) Dummy read of ICDRR register (2) Read ICDRR register
by program
Figure 16.39 Operating Timing in Slave Receive Mode (I2C bus Interface Mode) (1)
SCL
(master output) 9 1 2 3 4 5 6 7 8 9
SDA
(master output) b7 b6 b5 b4 b3 b2 b1 b0
SCL
(slave output)
SDA
A A
(slave output)
1
RDRF bit in
ICSR register
0
Processing (3) Set ACKBT bit to 1 (3) Read ICDRR register (4) Read ICDRR register
by program
Figure 16.40 Operating Timing in Slave Receive Mode (I2C bus Interface Mode) (2)
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16.3.4 Clock Synchronous Serial Mode
16.3.4.1 Clock Synchronous Serial Format

Set the FS bit in the SAR register to 1 to use the clock synchronous serial format for communication.
Figure 16.41 shows the Transfer Format of Clock Synchronous Serial Format.
When the MST bit in the ICCR1 register is set to 1, the transfer clock is output from the SCL pin, and when the
MST bit is set to 0, the external clock is input.
The transfer data is output between successive falling edges of the SCL clock, and data is determined at the
rising edge of the SCL clock. MSB-first or LSB-first can be selected as the order of the data transfer by setting
www.DataSheet4U.com the MLS bit in the ICMR register. The SDA output level can be changed by the SDAO bit in the ICCR2 register
during transfer standby.
SCL
Figure 16.41 Transfer Format of Clock Synchronous Serial Format
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16.3.4.2 Transmit Operation

In transmit mode, transmit data is output from the SDA pin in synchronization with the falling edge of the
transfer clock. The transfer clock is output when the MST bit in the ICCR1 register is set to 1 and input when
the MST bit is set to 0.
Figure 16.42 shows the Operating Timing in Transmit Mode (Clock Synchronous Serial Mode).
The transmit procedure and operation in transmit mode are as follows.

(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set bits CKS0 to CKS3 in the
ICCR1 register and set the MST bit (initial setting).
(2) The TDRE bit in the ICSR register is set to 1 by selecting transmit mode after setting the TRS bit in the
ICCR1 register to 1.
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(3) Data is transferred from registers ICDRT to ICDRS and the TDRE bit is automatically set to 1 by
writing transmit data to the ICDRT register after confirming that the TDRE bit is set to 1. Continuous
transmission is enabled by writing data to the ICDRT register every time the TDRE bit is set to 1. When
switching from transmit to receive mode, set the TRS bit to 0 while the TDRE bit is set to 1.
SCL 1 2 7 8 1 7 8 1
(output)
1
TRS bit in
ICCR1 register
0
1
TDRE bit in
ICSR register
0
ICDRT register Data 1 Data 2 Data 3
ICDRS register Data 1 Data 2 Data 3
Processing (3) Data write to (3) Data write to (3) Data write to (3) Data write to
by program ICDRT register ICDRT register ICDRT register ICDRT register
(2) Set TRS bit to 1
Figure 16.42 Operating Timing in Transmit Mode (Clock Synchronous Serial Mode)
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16.3.4.3 Receive Operation

In receive mode, data is latched at the rising edge of the transfer clock. The transfer clock is output when the
MST bit in the ICCR1 register is set to 1 and input when the MST bit is set to 0.
Figure 16.43 shows the Operating Timing in Receive Mode (Clock Synchronous Serial Mode).
The receive procedure and operation in receive mode are as follows.

(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set bits CKS0 to CKS3 in the
ICCR1 register and set the MST bit (initial setting).
(2) The output of the receive clock starts when the MST bit is set to 1 while the transfer clock is being
output.
(3) Data is transferred from registers ICDRS to ICDRR and the RDRF bit in the ICSR register is set to 1,
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when the receive operation is completed. Since the next byte of data is enabled when the MST bit is set
to 1, the clock is output continuously. Continuous reception is enabled by reading the ICDRR register
every time the RDRF bit is set to 1. An overrun is detected at the rise of the 8th clock cycle while the
RDRF bit is set to 1, and the AL bit in the ICSR register is set to 1. At this time, the last receive data is
retained in the ICDRR register.
(4) When the MST bit is set to 1, set the RCVD bit in the ICCR1 register to 1 (disables the next receive
operation) and read the ICDRR register. The SCL signal is fixed “H” after reception of the following
byte of data is completed.
SCL 1 2 7 8 1 7 8 1 2
(input)
1
MST bit in
ICCR1 register
0
TRS bit in 1
ICCR1 register
0
1
RDRF bit in
ICSR register
0
ICDRS register Data 1 Data 2 Data 3
ICDRR register Data 1 Data 2
Processing (2) Set MST bit to 1 (3) Read ICDRR register (3) Read ICDRR register
by program (when transfer clock is output)
Figure 16.43 Operating Timing in Receive Mode (Clock Synchronous Serial Mode)
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16.3.5 Noise Canceller

The states of pins SCL and SDA are routed through the noise canceller before being latched internally.
Figure 16.44 shows a Block Diagram of Noise Canceller.
The noise canceller consists of two cascaded latch and match detector circuits. When the SCL pin input signal
(or SDA pin input signal) is sampled on f1 and two latch outputs match, the level is passed forward to the next
circuit. When they do not match, the former value is retained.
f1 (sampling clock)
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C C
SCL or SDA D Q D Q Match
input signal Internal SCL
Latch Latch detection
or SDA signal
circuit
Period of f1
f1 (sampling clock)
Figure 16.44 Block Diagram of Noise Canceller
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16.3.6 Bit Synchronization Circuit

When setting the I2C bus interface to master mode, the high-level period may become shorter in the following
two cases:
• If the SCL signal is driven L level by a slave device
• If the rise speed of the SCL signal is reduced by a load (load capacity or pull-up resistor) on the SCL line.
Therefore, the SCL signal is monitored and communication is synchronized bit by bit.
Figure 16.45 shows the Timing of Bit Synchronization Circuit, and Table 16.8 lists the Time between Changing
SCL Signal from “L” Output to High-Impedance and Monitoring of SCL Signal.
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Reference clock of
SCL monitor timing
SCL VIH
Internal SCL
Figure 16.45 Timing of Bit Synchronization Circuit
Table 16.8 Time between Changing SCL Signal from “L” Output to High-Impedance and
Monitoring of SCL Signal
ICCR1 Register Time for Monitoring SCL
CKS3 CKS2
0 0 7.5Tcyc
1 19.5Tcyc
1 0 17.5Tcyc
1 41.5Tcyc
1Tcyc = 1/f1(s)
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16.3.7 Examples of Register Setting

Figures 16.46 to 16.49 show Examples of Register Setting When Using I2C bus interface.
Start
• Set the STOP bit in the ICSR register to 0

Initial setting • Set the IICSEL bit in the PMR register to 1
Read BBSY bit in ICCR2 register

(1) Judge the state of the SCL and SDA lines
(1) (2) Set to master transmit mode

No
BBSY = 0 ?
(3) Generate the start condition
Yes
(4) Set the transmit data of the 1st byte
ICCR1 register TRS bit ← 1 (slave address + R/W)
www.DataSheet4U.com MST bit ← 1 (2)
(5) Wait for 1 byte to be transmitted
ICCR2 register SCP bit ← 0 (3)
BBSY bit ← 1 (6) Judge the ACKBR bit from the specified slave device
Write transmit data to ICDRT register (4) (7) Set the transmit data after 2nd byte (except the last byte)
(8) Wait until the ICRDT register is empty

Read TEND bit in ICSR register
(9) Set the transmit data of the last byte
No (5) (10) Wait for end of transmission of the last byte

TEND = 1 ?
(11) Set the TEND bit to 0
Yes
Read ACKBR bit in ICIER register (12) Set the STOP bit to 0
(13) Generate the stop condition

No (6)
ACKBR = 0 ? (14) Wait until the stop condition is generated

Yes Set the TDRE bit to 0
Transmit No Master receive

mode ? mode
Yes
Write transmit data to ICDRT register (7)
Read TDRE bit in ICSR register
No (8)
TDRE = 1 ?
Yes
No
Last byte ?
(9)
Yes
Write transmit data to ICDRT register
(10)
No
TEND = 1 ?
Yes
ICSR register TEND bit ← 0 (11)
ICSR register STOP bit ← 0 (12)
ICCR2 register SCP bit ← 0 (13)

BBSY bit ← 0
Read STOP bit in ICSR register
(14)
No
STOP = 1 ?
Yes
ICCR1 register TRS bit ← 0
MST bit ← 0
(15)
ICSR register TDRE bit ← 0
End
Figure 16.46 Example of Register Setting in Master Transmit Mode (I2C bus Interface Mode)
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Master receive mode
ICSR register TEND bit ← 0 (1) Set the TEND bit to 0 and set to master receive mode.
Set the TDRE bit to 0 (1,2)
ICCR1 register TRS bit ← 0 (1) (2) Set the ACKBT bit to the transmit device (1)
ICSR register TDRE bit ← 0 (3) Dummy read the ICDRR register(1)
ICIER register ACKBT bit ← 0 (2) (4) Wait for 1 byte to be received
(5) Judge (last receive - 1)

Dummy read in ICDRR register (3)
www.DataSheet4U.com (6) Read the receive data
Read RDRF bit in ICSR register (7) Set the ACKBT bit of the last byte and set to disable
continuous receive operation (RCVD = 1)(2)
No (4) (8) Read the receive data of (last byte - 1)

RDRF = 1 ?
(9) Wait until the last byte is received
Yes
(10) Set the STOP bit to 0
Yes
Last receive (5) (11) Generate the stop condition
-1?
(12) Wait until the stop condition is generated
No
Read ICDRR register (6) (13) Read the receive data of the last byte
(14) Set the RCVD bit to 0

ICIER register ACKBT bit ← 1
(7)
ICCR1 register RCVD bit ← 1
Read ICDRR register (8)
Read RDRF bit in ICSR register
No (9)
RDRF = 1 ?
Yes
ICSR register STOP bit ← 0 (10)
ICCR2 register SCP bit ← 0

BBSY bit ← 0 (11)
Read STOP bit in ICSR register
No (12)
STOP = 1 ?
Yes
ICCR1 register RCVD bit ← 0 (14)
ICCR1 register MST bit ← 0 (15)
End
NOTES:
1. Do not generate the interrupt while processing steps (1) to (3).
2. When receiving 1 byte, skip steps (2) to (6) after (1) and jump to process of step (7).
Processing step (8) is dummy read of the ICDRR register.
Figure 16.47 Example of Register Setting in Master Receive Mode (I2C bus Interface Mode)
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Slave transmit mode

(1) Set the AAS bit to 0
ICSR register AAS bit ← 0 (1)
(2) Set the transmit data (except the last byte)
Write transmit data to ICDRT register (2)
(3) Wait until the ICRDT register is empty
Read TDRE bit in ICSR register (4) Set the transmit data of the last byte
www.DataSheet4U.com (5) Wait until the last byte is transmitted

(3)
TDRE = 1 ? (6) Set the TEND bit to 0
No
Yes
No (8) Dummy read the ICDRR register to release the

Last byte ? SCL signal
(4)
(9) Set the TDRE bit to 0
Yes
Write transmit data to ICDRT register
No (5)
TEND = 1 ?
Yes
ICSR register TEND bit ← 0 (6)
ICCR1 register TRS bit ← 0 (7)
Dummy read in ICDRR register (8)
ICSR register TDRE bit ← 0 (9)
End
Figure 16.48 Example of Register Setting in Slave Transmit Mode (I2C bus Interface Mode)
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Slave receive mode
ICSR register AAS bit ← 0 (1) (1) Set the AAS bit to 0 (1)
(2) Set the ACKBT bit to the transmit device

ICIER register ACKBT bit ← 0 (2)
(3) Dummy read the ICDRR register
Dummy read ICDRR register (3)
(4) Wait until 1 byte is received
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(5) Judge (last receive - 1)
(6) Read the receive data
No (4) (7) Set the ACKBT bit of the last byte(1)

RDRF = 1 ?
(8) Read the receive data of (last byte - 1)
Yes
(9) Wait until the last byte is received
Last receive Yes

(5) (10) Read the receive data of the last byte
-1?
No
ICIER register ACKBT bit ← 1 (7)
No (9)
RDRF = 1 ?
Yes
End
NOTE:
1. When receiving 1 byte, skip steps (2) to (6) after (1) and jump to processing step (7).
Processing step (8) is dummy read of the ICDRR register.
Figure 16.49 Example of Register Setting in Slave Receive Mode (I2C bus Interface Mode)
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16.3.8 Notes on I2C bus Interface

Set the IICSEL bit in the PMR register to 1 (select I2C bus interface function) to use the I2C bus interface.
16.3.8.1 Multimaster Operation

The following actions must be performed to use the I2C bus interface in multimaster operation.
• Transfer rate
Set the transfer rate by 1/1.8 or faster than the fastest rate of the other masters. For example, if the fastest
transfer rate of the other masters is set to 400 kbps, the I2C-bus transfer rate in this MCU should be set to
223 kbps (= 400/1.18) or more.
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• Bits MST and TRS in the ICCR1 register setting
(a) Use the MOV instruction to set bits MST and TRS.
(b) When arbitration is lost, confirm the contents of bits MST and TRS. If the contents are other than the
MST bit set to 0 and the TRS bit set to 0 (slave receive mode), set the MST bit to 0 and the TRS bit to 0
again.
16.3.8.2 Master Receive Mode

Either of the following actions must be performed to use the I2C bus interface in master receive mode.
(a) In master receive mode while the RDRF bit in the ICSR register is set to 1, read the ICDRR register
before the rising edge of the 8th clock.
(b) In master receive mode, set the RCVD bit in the ICCR1 register to 1 (disables the next receive
operation) to perform 1-byte communications.
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R8C/24 Group, R8C/25 Group 17. Hardware LIN
17. Hardware LIN

The hardware LIN performs LIN communication in cooperation with timer RA and UART0.
17.1 Features
The hardware LIN has the features listed below.
Figure 17.1 shows a Block Diagram of Hardware LIN.
Master mode
• Generates Synch Break
• Detects bus collision
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Slave mode
• Detects Synch Break
• Measures Synch Field
• Controls Synch Break and Synch Field signal inputs to UART0
• Detects bus collision
NOTE:
1. The WakeUp function is detected by INT1.
Hardware LIN
Synch Field
RXD0 pin
control Timer RA
circuit
TIOSEL = 0
RXD data
Timer RA
LSTART bit RXD0 input TIOSEL = 1 underflow signal
SBE bit control
LINE bit circuit Timer RA
Interrupt interrupt
control
Bus collision circuit
detection
circuit UART0
BCIE, SBIE,
and SFIE bits
UART0 transfer clock
UART0 TE bit
Timer RA output pulse
MST bit
TXD0 pin UART0 TXD data
LINE, MST, SBE, LSTART, BCIE, SBIE, SFIE: Bits in LINCR register
TIOSEL: Bit in TRAIOC register
TE: Bit in U0C1 register
Figure 17.1 Block Diagram of Hardware LIN
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17.2 Input/Output Pins

The pin configuration of the hardware LIN is listed in Table 17.1.
Table 17.1 Pin Configuration

Name Abbreviation Input/Output Function
Receive data input RXD0 Input Receive data input pin of the hardware LIN
Transmit data output TXD0 Output Transmit data output pin of the hardware LIN
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17.3 Register Configuration

The hardware LIN contains the registers listed below.
These registers are detailed in Figures 17.2 and 17.3.
• LIN Control Register (LINCR)
• LIN Status Register (LINST)
LIN Control Register

b7 b6 b5 b4 b3 b2 b1 b0

LINCR 0106h 00h
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Synch Field measurement- 0 : Disables Synch Field measurement-
completed interrupt enable bit completed interrupt
SFIE 1 : Enables Synch Field measurement- RW
completed interrupt
Synch Break detection interrupt 0 : Disables Synch Break detection interrupt
SBIE RW
enable bit 1 : Enables Synch Break detection interrupt
Bus collision detection interrupt 0 : Disables bus collision detection interrupt
BCIE RW
enable bit 1 : Enables bus collision detection interrupt
RXD0 input status flag 0 : RXD0 input enabled
RXDSF RO
1 : RXD0 input disabled
Synch Break detection start When this bit is set to 1, timer RA input is
LSTART bit(1) enabled and RXD0 input is disabled. RW
RXD0 input unmasking timing 0 : Unmasked after Synch Break is detected
SBE select bit (effective only in slave 1 : Unmasked after Synch Field measurement RW
mode) is completed
LIN operation mode setting bit(2) 0 : Slave mode
(Synch Break detection circuit actuated)
MST 1 : Master mode RW
(timer RA output OR’ed w ith TXD0)
LIN operation start bit 0 : Causes LIN to stop
LINE RW
1 : Causes LIN to start operating(3)
NOTES:
1. After setting the LSTART bit, confirm that the RXDSF flag is set to 1 before Synch Break input starts.
2. Before changing LIN operation modes, temporarily stop the LIN operation (LINE bit = 0).
3. Inputs to timer RA and UART0 are prohibited immediately after this bit is set to 1. (Refer to Figure 17.5 Exam ple of
Header Field Transm ission Flow chart (1) and Figure 17.9 Exam ple of Header Field Reception Flow chart
(2) .)
Figure 17.2 LINCR Register
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LIN Status Register

b7 b6 b5 b4 b3 b2 b1 b0

LINST 0107h 00h
Synch Field measurement- 1 show s Synch Field measurement completed.
SFDCT RO
completed flag
Synch Break detection flag 1 show s Synch Break detected or Synch
SBDCT RO
Break generation completed.
www.DataSheet4U.com Bus collision detection flag 1 show s Bus collision detected
BCDCT RO
SFDCT bit clear bit When this bit is set to 1, the SFDCT bit is set to
B0CLR 0. RW
SBDCT bit clear bit When this bit is set to 1, the SBDCT bit is set to
B1CLR 0. RW
BCDCT bit clear bit When this bit is set to 1, the BCDCT bit is set to
B2CLR 0. RW
—
Figure 17.3 LINST Register
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17.4 Functional Description
17.4.1 Master Mode

Figure 17.4 shows typical operation of the hardware LIN when transmitting a header field in master mode.
Figures 17.5 and 17.6 show a flowchart of the procedure for transmitting a header field.
When transmitting a header field, the hardware LIN operates as described below.
(1) When the TSTART bit in the TRACR register for timer RA is set by writing 1 in software, the hardware
LIN outputs “L” level from the TXD0 pin for the period that is set in registers TRAPRE and TRA for
timer RA.
(2) When timer RA underflows upon reaching the terminal count, the hardware LIN reverses the output of
www.DataSheet4U.com the TXD0 pin and sets the SBDCT flag in the LINST register to 1. Furthermore, if the SBIE bit in the
LINCR register is set to 1, it generates a timer RA interrupt.
(3) The hardware LIN transmits 55h via UART0.
(4) The hardware LIN transmits an ID field via UART0 after it finishes sending 55h.
(5) The hardware LIN performs communication for a response field after it finishes sending the ID field.
Synch Break Synch Field IDENTIFIER
1
TXD0 pin
0
Set by writing 1 to the
B1CLR bit in the LINST
SBDCT flag in the 1 register
LINST register 0
Cleared to 0 upon
acceptance of interrupt
IR bit in the TRAIC 1 request or by a program
register 0
(1) (2) (3) (4) (5)

LINE = 1, MST = 1, SBIE = 1
Figure 17.4 Typical Operation when Sending a Header Field
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Timer RA Set to timer mode

Bits TMOD0 to TMOD2 in TRAMR register ← 000b
Timer RA Set the pulse output level from low to start

TEDGSEL bit in TRAIOC register ← 1
For the hardware LIN

Timer RA Set the INT1/TRAIO pin to P1_5
function, set the TIOSEL bit
TIOSEL bit in TRAIOC register ← 1 in the TRAIOC register to 1.
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Timer RA Set the count source (f1, f2, f8, fOCO)
Bits TCK0 to TCK2 in TRAMR register
Set the count source and
registers TRA and TRAPRE
Timer RA Set the Synch Break width as suitable for the Synch
Break period.
TRAPRE register
TRA register
UART0 Set to transmit/receive mode

(Transfer data length: 8 bits, Internal clock, 1 stop bit,
Parity disabled)
U0MR register
UART0 Set the BRG count source (f1, f8, f32)

U0C0CLK0 to 1 bit Set the BRG count source
and U0BRG register as
UART0 Set the bit rate appropriate for the bit rate.
U0BRG register
Hardware LIN Set the LIN operation to stop

LINCR register LINE bit ← 0
Hardware LIN Set to master mode

MST bit in LINCR register ← 1
Hardware LIN Set the LIN operation to start

LINE bit in LINCR register ← 1
Hardware LIN Set the register to enable interrupts

(Bus collision detection, Synch Break detection,
Synch Field measurement)
Bits BCIE, SBIE, SFIE in LINCR register During master mode, the
Synch Field measurement-
completed interrupt cannot be
Hardware LIN Clear the status flags used.
Bits B2CLR, B1CLR, B0CLR in LINST register ← 1
A
Figure 17.5 Example of Header Field Transmission Flowchart (1)
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Timer RA Set the timer to start counting Timer RA generates Synch Break.
TSTART bit in TRACR register ← 1 If registers TRAPRE and TRA for
timer RA do not need to be read or
the register settings do not need to be
Timer RA Read the count status flag changed after writing 1 to the
TCSTF flag in TRACR register TSTART bit, the procedure for reading
www.DataSheet4U.com TCSTF flag = 1 can be omitted.
Zero to one cycle of the timer RA
NO count source is required after timer
TCSTF = 1 ?
RA starts counting before the TCSTF
YES flag is set to 1.
Hardware LIN Read the Synch Break detection flag The timer RA interrupt may be used
SBDCT flag in LINST register to terminate generation of Synch
Break.
One to two cycles of the CPU clock
NO are required after Synch Break
SBDCT = 1 ? generation completes before the
SBDCT flag is set to 1.
YES
After timer RA Synch Break is
Timer RA Set the timer to stop counting generated, the timer should be made
TSTART bit in TRACR register ← 0 to stop counting.
If registers TRAPRE and TRA for timer
Timer RA Read the count status flag RA do not need to be read or the
register settings do not need to be
TCSTF flag in TRACR register changed after writing 0 to the TSTART
bit, the procedure for reading TCSTF
flag = 0 can be omitted.
NO Zero to one cycle of the timer RA count
TCSTF = 0 ?
source is required after timer RA stops
YES counting before the TCSTF flag is set
to 0.
UART0 Communication via UART0
TE bit in U0C1 register ← 1 Transmit the Synch Field.
U0TB register ← 0055h
UART0 Communication via UART0

Transmit the ID field.
U0TB register ← ID field
Figure 17.6 Example of Header Field Transmission Flowchart (2)
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17.4.2 Slave Mode

Figure 17.7 shows typical operation of the hardware LIN when receiving a header field in slave mode. Figure
17.8 through Figure 17.10 show a flowchart for the procedure for receiving a header field.
When receiving a header field, the hardware LIN operates as described below.
(1) Synch Break detection is enabled by writing 1 to the LSTART bit in the LINCR register of the hardware
LIN.
(2) When “L” level is input for a duration equal to or greater than the period set in timer RA, the hardware
LIN detects it as Synch Break. At this time, the SBDCT flag in the LINST register is set to 1.
Furthermore, if the SBIE bit in the LINCR register is set to 1, the hardware LIN generates a timer RA
interrupt. Then it goes to Synch Field measurement.
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(3) The hardware LIN receives a Synch Field (55h). At this time, it measures the period of the start bit and
bits 0 to 6 by using timer RA. In this case, it is possible to select whether to input the Synch Field signal
to RXD0 of UART0 by setting the SBE bit in the LINCR register accordingly.
(4) The hardware LIN sets the SFDCT flag in the LINST register to 1 when it finishes measuring the Synch
Field. Furthermore, if the SFIE bit in the LINCR register is set to 1, it generates a timer RA interrupt.
(5) After it finishes measuring the Synch Field, calculate a transfer rate from the count value of timer RA
and set to UART0 and registers TRAPRE and TRA of timer RA again.
(6) The hardware LIN performs communication for a response field after it finishes receiving the ID field.
Synch Break Synch Field IDENTIFIER
1
RXD0 pin
0
RXD0 input for 1

UART0 0 Set by writing 1 to
Cleared to 0 when Synch
the LSTART bit in
Field measurement
the LINCR register
RXDSF flag in the 1 finishes
LINCR register 0
Set by writing 1 to
the B1CLR bit in
SBDCT flag in the 1 the LINST register
LINST register 0
Measure this period Set by writing 1 to the
B0CLR bit in the LINST
SFDCT flag in the 1 register
LINST register 0 Cleared to 0 upon
acceptance of
interrupt request or
IR bit in the TRAIC 1 by a program
register 0
(1) (2) (3) (4) (5) (6)

LINE = 1, MST = 0, SBE = 1, SBIE = 1, SFIE = 1
Figure 17.7 Typical Operation when Receiving a Header Field
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REJ09B0244-0300
Timer RA Set to pulse width measurement mode

Bits TMOD0 to TMOD2 in the TRAMR register ← 011b
Timer RA Set the pulse width measurement level low

TEDGSEL bit in the TRAIOC register ← 0
Timer RA Set the INT1/TRAIO pin to P1_5 For the hardware LIN
function, set the TIOSEL bit
www.DataSheet4U.com TIOSEL bit in the TRAIOC register ← 1 in the TRAIOC register to 1.
Timer RA Set the count source (f1, f2, f8, fOCO)

Bits TCK0 to TCK2 in the TRAMR register
Set the count source and registers
TRA and TRAPRE as appropriate
Timer RA Set the Synch Break width for the Synch Break period.
TRAPRE register
TRA register

LINE bit in the LINCR register ← 0
Hardware LIN Set to slave mode

MST bit in the LINCR register ← 0
Hardware LIN Set the LIN operation to start

Select the timing at which to

Hardware LIN Set the RXD0 input unmasking timing unmask the RXD0 input for UART0.
(After Synch Break detection, or after Synch If the RXD0 input is chosen to be
Field measurement) unmasked after detection of Synch
SBE bit in the LINCR register Break, the Synch Field signal is
also input to UART0.
Hardware LIN Set the register to enable interrupts

Bits BCIE, SBIE, SFIE in the LINCR register
Figure 17.8 Example of Header Field Reception Flowchart (1)
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Hardware LIN Clear the status flags

(Bus collision detection, Synch Break
detection, Synch Field measurement)
Bits B2CLR, B1CLR, B0CLR in the LINST
register ← 1
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Timer RA waits until the timer starts
Timer RA Set to start a pulse width measurement counting.
TSTART bit in the TRACR register ← 1
Timer RA Read the count status flag

TCSTF flag in the TRACR register Zero to one cycle of the timer RA
count source is required after timer
RA starts counting before the TCSTF
NO flag is set to 1.
TCSTF = 1 ?
Hardware LIN waits until the RXD0
YES input for UART0 is masked.
Hardware LIN Set to start Synch Break detection Do not apply “L” level to the RXD pin
until the RXDSF flag reads 1 after
LSTART bit in the LINCR register ← 1 writing 1 to the LSTART bit. This is
because the signal applied during this
time is input directly to UART0.
Hardware LIN Read the RXD0 input status flag
RXDSF flag in the LINCR register and zero to one cycle of the timer RA
count source are required after the
LSTART bit is set to 1 before the
NO RXDSF flag is set to 1. After this,
RXDSF = 1 ?
input to timer RA and UART0 is
YES enabled.
Hardware LIN detects a Synch Break.
Hardware LIN Read the Synch Break detection flag The interrupt of the timer RA may be
SBDCT flag in the LINST register used.
When Synch Break is detected, timer
RA is reloaded with the initially set
NO count value.
SBDCT = 1 ?
Even if the duration of the input “L”
level is shorter than the set period,
YES timer RA is reloaded with the initially
B set count value and waits until the
next “L” level is input.
are required after Synch Break
detection before the SBDCT flag is
set to 1.
When the SBE bit in the LINCR
register is set to 0 (unmasked after
Synch Break is detected), timer RA
can be used in timer mode after the
SBDCT flag in the LINST register is
set to 1 and the RXDSF flag is set to
0.
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B Hardware LIN measures the Synch

Field.
YES The interrupt of timer RA may be
Hardware LIN Read the Synch Field measurement- used (the SBDCT flag is set when
completed flag the timer RA counter underflows
SFDCT flag in the LINST register upon reaching the terminal count).
When the SBE bit in the LINCR
register is set to 1 (unmasked after
Synch Field measurement is
NO completed), timer RA may be used
SFDCT = 1 ?
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in timer mode after the SFDCT bit in
the LINST register is set to 1.
YES
UART0 Set the UART0 communication rate
U0BRG register
Set a communication rate based on
the Synch Field measurement
Timer RA Set the Synch Break width again result.
TRAPRE register
TRA register
UART0 Communication via UART0 Communication via UART0

(The SBDCT flag is set when the
Clock asynchronous serial interface (UART) mode
timer RA counter underflows upon
Transmit ID field reaching the terminal count.)
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17.4.3 Bus Collision Detection Function

The bus collision detection function can be used when UART0 is enabled for transmission (TE bit in the U0C1
register = 1).
Figure 17.11 shows the Typical Operation when a Bus Collision is Detected.
1
TXD0 pin
0
1
RXD0 pin
1
Transfer clock
0
LINE bit in the 1
LINCR register 0
TE bit in the U0C1 1
register 0
Set by writing 1 to
the B2CLR bit in the
BCDCT flag in the 1 LINST register
LINST register 0
Cleared to 0 upon
acceptance of interrupt
IR bit in the TRAIC 1 request or by a program
register 0
Figure 17.11 Typical Operation when a Bus Collision is Detected
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17.4.4 Hardware LIN End Processing

Figure 17.12 shows an Example of Hardware LIN Communication Completion Flowchart.
Use the following timing for hardware LIN end processing:
• If the hardware bus collision detection function is used
Perform hardware LIN end processing after checksum transmission completes.
• If the bus collision detection function is not used
Perform hardware LIN end processing after header field transmission and reception complete.
Timer RA Set the timer to stop counting

TSTART bit in TRACR register ← 0 Set the timer to stop counting.
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Timer RA Read the count status flag Zero to one cycle of the timer
TCSTF flag in TRACR register RA count source is required
after timer RA starts counting
before the TCSTF flag is set to
NO 1.
TCSTF = 0 ?
YES
When the bus collision
UART0 Complete transmission via UART0 detection function is not used,
end processing for the UART0
transmission is not required.
Hardware LIN Clear the status flags
(Bus collision detection, Synch Break
detection, Synch Field measurement)
Bits B2CLR, B1CLR, B0CLR in the LINST After clearing hardware LIN
register ← 1 status flag, stop the
hardware LIN operation.

Figure 17.12 Example of Hardware LIN Communication Completion Flowchart
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REJ09B0244-0300
17.5 Interrupt Requests

There are four interrupt requests that are generated by the hardware LIN: Synch Break detection, Synch Break
generation completed, Synch Field measurement, and bus collision detection. These interrupts are shared with
timer RA.
Table 17.2 lists the Interrupt Requests of Hardware LIN.
Table 17.2 Interrupt Requests of Hardware LIN

Interrupt Request Status Flag Cause of Interrupt
Synch Break detection SBDCT Generated when timer RA has underflowed after measuring
the “L” level duration of RXD0 input, or when a “L” level is
www.DataSheet4U.com input for a duration longer than the Synch Break period
during communication.
Synch Break generation Generated when “L” level output to TXD0 for the duration set
completed by timer RA completes.
Synch Field SFDCT Generated when measurement for 6 bits of the Synch Field
measurement by timer RA is completed.
Bus collision detection BCDCT Generated when the RXD0 input and TXD0 output values
differed at data latch timing while UART0 is enabled for
transmission.
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17.6 Notes on Hardware LIN

For the time-out processing of the header and response fields, use another timer to measure the duration of time
with a Synch Break detection interrupt as the starting point.
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R8C/24 Group, R8C/25 Group 18. A/D Converter
18. A/D Converter

The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling
amplifier. The analog input shares pins P0_0 to P0_7, and P1_0 to P1_3. Therefore, when using these pins, ensure that
the corresponding port direction bits are set to 0 (input mode).
When not using the A/D converter, set the VCUT bit in the ADCON1 register to 0 (Vref unconnected) so that no
current will flow from the VREF pin into the resistor ladder. This helps to reduce the power consumption of the chip.
The result of A/D conversion is stored in the AD register.
Table 18.1 lists the Performance of A/D converter. Figure 18.1 shows a Block Diagram of A/D Converter.
Figures 18.2 and 18.3 show the A/D converter-related registers.
Table 18.1 Performance of A/D converter

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Item Performance
A/D conversion method Successive approximation (with capacitive coupling amplifier)
Analog input voltage(1) 0 V to AVCC
Operating clock φAD(2) 4.2 V ≤ AVCC ≤ 5.5 V f1, f2, f4, fOCO-F
2.2 V ≤ AVCC < 4.2 V f2, f4, fOCO-F
Resolution 8 bits or 10 bits selectable
Absolute accuracy AVCC = Vref = 5 V, φAD = 10 MHz
• 8-bit resolution ±2 LSB
AVCC = Vref = 3.3 V, φAD = 10 MHz
AVCC = Vref = 2.2 V, φAD = 5 MHz
Operating mode One-shot and repeat(3)
Analog input pin 12 pins (AN0 to AN11)
A/D conversion start condition • Software trigger
Set the ADST bit in the ADCON0 register to 1 (A/D conversion starts)
• Capture
Timer RD interrupt request is generated while the ADST bit is set to 1
Conversion rate per pin • Without sample and hold function
8-bit resolution: 49φAD cycles, 10-bit resolution: 59φAD cycles
• With sample and hold function
8-bit resolution: 28φAD cycles, 10-bit resolution: 33φAD cycles
NOTES:
1. The analog input voltage does not depend on use of a sample and hold function.
When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh
in 10-bit mode and FFh in 8-bit mode.
2. When 2.7 V ≤ AVCC ≤ 5.5 V, the frequency of φAD must be 10 MHz or below.
When 2.2 V ≤ AVCC < 2.7 V, the frequency of φAD must be 5 MHz or below.
Without a sample and hold function, the φAD frequency should be 250 kHz or above.
With a sample and hold function, the φAD frequency should be 1 MHz or above.
3. In repeat mode, only 8-bit mode can be used.
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CKS0 = 1
fOCO-F A/D conversion rate selection
f1 CKS1 = 1
CKS0 = 0 CKS0 = 1
φAD
f2
CKS1 = 0
f4
CKS0 = 0
VCUT = 0
AVSS
VCUT = 1 Resistor ladder
www.DataSheet4U.com VREF
Successive conversion register

ADCAP = 0
Software trigger ADCON0
Trigger
Timer RD
interrupt request ADCAP = 1 Vcom
AD register Decoder
Comparator
VIN
Data bus
CH2 to CH0 = 000b

P0_7/AN0
CH2 to CH0 = 001b
P0_6/AN1
CH2 to CH0 = 010b
P0_5/AN2 ADGSEL0 = 0
CH2 to CH0 = 011b
P0_4/AN3
CH2 to CH0 = 100b
P0_3/AN4
CH2 to CH0 = 101b
P0_2/AN5
CH2 to CH0 = 110b
P0_1/AN6 ADGSEL0 = 1
CH2 to CH0 = 111b
P0_0/AN7
CH2 to CH0 = 100b

P1_0/AN8
CH2 to CH0 = 101b
P1_1/AN9
CH2 to CH0 = 110b
P1_2/AN10
CH2 to CH0 = 111b
P1_3/AN11
CH0 to CH2, ADGSEL0, CKS0: Bits in ADCON0 register

CKS1, VCUT: Bits in ADCON1 register
Figure 18.1 Block Diagram of A/D Converter
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A/D Control Register 0(1)

b7 b6 b5 b4 b3 b2 b1 b0

ADCON0 00D6h 00h
Analog input pin select bits (Note 4)
CH0 RW
CH1 RW
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CH2 RW
A/D operating mode select 0 : One-shot mode

MD RW
bit(2) 1 : Repeat mode
(4)
A/D input group select bit 0 : Selects port P0 group (AN0 to AN7)
ADGSEL0 RW
1 : Selects port P1 group (AN8 to AN11)
A/D conversion automatic 0 : Starts at softw are trigger (ADST bit)
ADCAP start bit 1 : Starts at timer RD RW
(complementary PWM mode)
A/D conversion start flag 0 : Stops A/D conversion
ADST RW
1 : Starts A/D conversion
Frequency select bit 0 [When CKS1 in ADCON1 register = 0]
0 : Selects f4
1 : Selects f2
CKS0 [When CKS1 in ADCON1 register = 1] RW
0 : Selects f1(3)
1 : Selects fOCO-F
NOTES:
1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result is undefined.
2. When changing A/D operating mode, set the analog input pin again.
3. Set øAD frequency to 10 MHz or below .
4. The analog input pin can be selected according to a combination of bits CH0 to CH2 and the ADGSEL0 bit.
CH2 to CH0 ADGSEL0 = 0 ADGSEL0 = 1
000b AN0 Do not set.
001b AN1
010b AN2
011b AN3
100b AN4 AN8
101b AN5 AN9
110b AN6 AN10
111b AN7 AN11
Figure 18.2 ADCON0 Register
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b7 b6 b5 b4 b3 b2 b1 b0

ADCON1 00D7h 00h
RW
(b2-b0)
8/10-bit mode select bit(2) 0 : 8-bit mode
BITS RW
1 : 10-bit mode
www.DataSheet4U.com Frequency select bit 1 Refer to the description of the CKS0 bit in the
CKS1 RW
ADCON0 register function
Vref connect bit(3) 0 : Vref not connected
VCUT RW
1 : Vref connected
RW
(b6-b7)
NOTES:
2. Set the BITS bit to 0 (8-bit mode) in repeat mode.
3. When the VCUT bit is set to 1 (connected) from 0 (not connected), w ait for 1 µs or more before starting
A/D conversion.

b7 b6 b5 b4 b3 b2 b1 b0

ADCON2 00D4h 00h
A/D conversion method select bit 0 : Without sample and hold
SMP RW
1 : With sample and hold
RW
(b3-b1)
—
NOTE:
A/D Register
(b15) (b8)
b7 b0 b7 b0

AD 00C1h-00C0h Undefined
Function RW
When BITS bit in ADCON1 register is set to 1 When BITS bit in ADCON1 register is set to 0
RW
(10-bit mode). (8-bit mode).
8 low -order bits in A/D conversion result A/D conversion result
RO
2 high-order bits in A/D conversion result When read, the content is undefined.
RO
Nothing is assigned. If necessary, set to 0.

—
Figure 18.3 Registers ADCON1, ADCON2, and AD
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18.1 One-Shot Mode

In one-shot mode, the input voltage of one selected pin is A/D converted once.
Table 18.2 lists the One-Shot Mode Specifications. Figures 18.4 and 18.5 show Registers ADCON0 and ADCON1
in One-Shot Mode.
Table 18.2 One-Shot Mode Specifications

Item Specification
Function The input voltage of one pin selected by bits CH2 to CH0 and ADGSEL0 is
A/D converted once
Start condition • When the ADCAP bit is set to 0 (software trigger):
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Set the ADST bit to 1 (A/D conversion starts)
• When the ADCAP bit is set to 1 (starts in timer RD (complementary PWM
mode):
A compare match between registers TRD0 and TRDGRA0 or a TRD1
underflow is generated while the ADST bit is set to 1
Stop condition • A/D conversion completes (when the ADCAP bit is set to 0 (software
trigger) ADST bit is set to 0)
• Set the ADST bit to 0
Interrupt request generation A/D conversion completes
timing
Input pin Select one of AN0 to AN11
Reading of A/D conversion Read AD register
result
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b7 b6 b5 b4 b3 b2 b1 b0

ADCON0 00D6h 00h
CH0 RW
CH1 RW
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CH2 RW
A/D operating mode select 0 : One-shot mode

MD RW
bit(2)
(4)
A/D input group select bit 0 : Selects port P0 group (AN0 to AN7)
ADGSEL0 RW
ADST RW
0 : Selects f4
1 : Selects f2
0 : Selects f1(3)
1 : Selects fOCO-F
NOTES:
2. After changing the A/D operating mode, select the analog input pin again.
001b AN1
010b AN2
011b AN3
100b AN4 AN8
101b AN5 AN9
110b AN6 AN10
111b AN7 AN11
Figure 18.4 ADCON0 Register in One-Shot Mode
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b7 b6 b5 b4 b3 b2 b1 b0

ADCON1 00D7h 00h
RW
(b2-b0)
8/10-bit mode select bit 0 : 8-bit mode
BITS RW
1 : 10-bit mode
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Frequency select bit 1 Refer to the description of the CKS0 bit in the
CKS1 RW
(2)
Vref connect bit 1 : Vref connected
VCUT RW

RW
(b6-b7)
NOTES:
A/D conversion.
Figure 18.5 ADCON1 Register in One-Shot Mode
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18.2 Repeat Mode

In repeat mode, the input voltage of one selected pin is A/D converted repeatedly.
Table 18.3 lists the Repeat Mode Specifications. Figures 18.6 and 18.7 show Registers ADCON0 and ADCON1 in
Repeat Mode.
Table 18.3 Repeat Mode Specifications

Item Specification
Function The Input voltage of one pin selected by bits CH2 to CH0 and ADGSEL0 is
A/D converted repeatedly
Start conditions • When the ADCAP bit is set to 0 (software trigger):
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Set the ADST bit to 1 (A/D conversion starts)
• When the ADCAP bit is set to 1 (starts in timer RD (complementary PWM
mode)):
A compare match between registers TRD0 and TRDGRA0 or a TRD1
underflow is generated while the ADST bit is set to 1
Stop condition Set the ADST bit to 0
Interrupt request generation Not generated
timing
Input pin Select one of AN0 to AN11
Reading of result of A/D Read AD register
converter
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b7 b6 b5 b4 b3 b2 b1 b0

ADCON0 00D6h 00h
CH0 RW
CH1 RW
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CH2 RW
A/D operating mode select 1 : Repeat mode

MD RW
bit(2)
A/D input group select bit(4) 0 : Selects port P0 group (AN0 to AN7)
ADGSEL0 RW
ADST RW
0 : Selects f4
1 : Selects f2
0 : Selects f1(3)
1 : Do not set.
NOTES:
2. After changing A/D operation mode, select the analog input pin again.
001b AN1
010b AN2
011b AN3
100b AN4 AN8
101b AN5 AN9
110b AN6 AN10
111b AN7 AN11
Figure 18.6 ADCON0 Register in Repeat Mode
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b7 b6 b5 b4 b3 b2 b1 b0
0 0 1 0 0 0 0 Symbol Address After Reset

ADCON1 00D7h 00h
RW
(b2-b0)
8/10-bit mode select bit(2) 0 : 8-bit mode
BITS RW
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Frequency select bit 1 Refer to the description of the CKS0 bit in the
CKS1 RW
Vref connect bit(3) 1 : Vref connected
VCUT RW

RW
(b6-b7)
NOTES:
2. Set the BITS bit to 0 (8-bit mode) in repeat mode.
A/D conversion.
Figure 18.7 ADCON1 Register in Repeat Mode
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18.3 Sample and Hold

When the SMP bit in the ADCON2 register is set to 1 (sample and hold function enabled), the A/D conversion rate
per pin increases. The sample and hold function is available in all operating modes. Start A/D conversion after
selecting whether the sample and hold circuit is to be used or not.
Figure 18.8 shows a Timing Diagram of A/D Conversion.
Sample and hold

disabled Conversion time of 1st bit 2nd bit
Sampling time Comparison Sampling time Comparison Sampling time Comparison

www.DataSheet4U.com 4ø AD cycles time 2.5ø AD cycles time 2.5ø AD cycles time
* Repeat until conversion ends
Sample and hold

enabled 2nd bit
Conversion time of 1st bit
Sampling time Comparison Comparison Comparison Comparison

4ø AD cycles time time time time
* Repeat until conversion ends
Figure 18.8 Timing Diagram of A/D Conversion
18.4 A/D Conversion Cycles

Figure 18.9 shows the A/D Conversion Cycles.
Conversion time at the 2nd

Conversion time at the 1st bit End process
bit and the follows
Conversion Sampling Comparison Sampling Comparison

A/D Conversion Mode End process
Time Time Time Time Time
Without Sample & Hold 8 bits 49φAD 4φAD 2.0φAD 2.5φAD 2.5φAD 8.0φAD
Without Sample & Hold 10 bits 59φAD 4φAD 2.0φAD 2.5φAD 2.5φAD 8.0φAD
With Sample & Hold 8 bits 28φAD 4φAD 2.5φAD 0.0φAD 2.5φAD 4.0φAD
With Sample & Hold 10 bits 33φAD 4φAD 2.5φAD 0.0φAD 2.5φAD 4.0φAD
Figure 18.9 A/D Conversion Cycles
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18.5 Internal Equivalent Circuit of Analog Input

Figure 18.10 shows the Internal Equivalent Circuit of Analog Input.
VCC
VCC VSS
AVCC
ON Resistor
Parasitic Diode ON Resistor Approx. 0.6kΩ
Approx. 2kΩ Wiring Resistor Analog Input C = Approx.1.5pF
AN0 Approx. 0.2kΩ
Voltage AMP
www.DataSheet4U.com VIN
SW1 SW2
Parasitic Diode ON Resistor
Approx. 5kΩ
Sampling
Control Signal SW3
SW4
VSS
i Ladder-type i Ladder-type
i = 12 Switches Chopper-type
Wiring Resistors
AVSS
Amplifier
ON Resistor
Approx. 2kΩ Wiring Resistor
Approx. 0.2kΩ
AN11
SW1
A/D Successive
b4 b2 b1 b0 Reference Conversion Register
A/D Control Register 0 Control Signal
VREF Vref
SW5 Comparison
Resistor voltage
ladder ON Resistor
Approx. 0.6k f
AVSS A/D Conversion
Interrupt Request
Comparison reference voltage
(Vref) generator
Sampling Comparison
SW1 conducts only on the ports selected for analog input.
Connect to
SW2 and SW3 are open when A/D conversion is not in progress;
Control signal their status varies as shown by the waveforms in the diagrams on the left.
for SW2 Connect to
Connect to SW4 conducts only when A/D conversion is not in progress.
Control signal SW5 conducts when compare operation is in progress.

for SW3 Connect to
NOTE:
1. Use only as a standard for designing this data.
Mass production may cause some changes in device characteristics.
Figure 18.10 Internal Equivalent Circuit of Analog Input
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18.6 Output Impedance of Sensor under A/D Conversion

To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 18.11 has to be completed
within a specified period of time. T (sampling time) as the specified time. Let output impedance of sensor
equivalent circuit be R0, internal resistance of microcomputer be R, precision (error) of the A/D converter be X,
and the resolution of A/D converter be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit mode).
1
– -------------------------- t
 C ( R0 + R ) 
VC is generally VC = VIN  1 – e 
 
VC = VIN – ---- VIN = VIN  1 – ----

And when t = T, X X
Y  Y
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1
– --------------------------T
e C ( R0 + R) = X ----
Y
1
– -------------------------- T = ln X
----
C ( R0 + R ) Y
Hence, T
R0 = – ------------------- – R
X
C • ln ----
Y
Figure 18.11 shows the Analog Input Pin and External Sensor Equivalent Circuit. When the difference between
VIN and VC becomes 0.1LSB, we find impedance R0 when voltage between pins VC changes from 0 to VIN-
(0.1/1024) VIN in time T. (0.1/1024) means that A/D precision drop due to insufficient capacitor charge is held to
0.1LSB at time of A/D conversion in the 10-bit mode. Actual error however is the value of absolute precision
added to 0.1LSB.
When f(XIN) = 10 MHz, T = 0.25 µs in the A/D conversion mode without sample & hold. Output impedance R0
for sufficiently charging capacitor C within time T is determined as follows.
T = 0.25 µs, R = 2.8 kΩ, C = 6.0 pF, X = 0.1, and Y = 1024. Hence,
0.25 × 10 – 6 3
- – 2.8 ×10 ≈ 1.7 ×10
3
R0 = – --------------------------------------------------
6.0 × 10 – 12 • ln ----------- 0.1 -
1024
Thus, the allowable output impedance of the sensor equivalent circuit, making the precision (error) 0.1LSB or less,
is approximately 1.7 kΩ. maximum.
MCU
Sensor equivalent
circuit
R0 R (2.8 kΩ)
VIN
C (6.0 pF)
VC
NOTE:
1. The capacity of the terminal is assumed to be 4.5 pF.
Figure 18.11 Analog Input Pin and External Sensor Equivalent Circuit
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REJ09B0244-0300
18.7 Notes on A/D Converter

• Write to each bit (other than bit 6) in the ADCON0 register, each bit in the ADCON1 register, or the SMP bit
in the ADCON2 register when A/D conversion is stopped (before a trigger occurs).
• When the VCUT bit in the ADCON1 register is changed from 0 (VREF not connected) to 1 (VREF
connected), wait for at least 1 µs before starting the A/D conversion.
• After changing the A/D operating mode, select an analog input pin again.
• When using the one-shot mode, ensure that A/D conversion is completed before reading the AD register. The
IR bit in the ADIC register or the ADST bit in the ADCON0 register can be used to determine whether A/D
conversion is completed.
• When using the repeat mode, select the frequency of the A/D converter operating clock φAD or more for the
CPU clock during A/D conversion.
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Do not select the fOCO-F for the φAD.
• If the ADST bit in the ADCON0 register is set to 0 (A/D conversion stops) by a program and A/D conversion
is forcibly terminated during an A/D conversion operation, the conversion result of the A/D converter will be
undefined. If the ADST bit is set to 0 by a program, do not use the value of the AD register.
• Connect 0.1 µF capacitor between the P4_2/VREF pin and AVSS pin.
• Do not enter stop mode during A/D conversion.
• Do not enter wait mode when the CM02 bit in the CM0 register is set to 1 (peripheral function clock stops in
wait mode) during A/D conversion.
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R8C/24 Group, R8C/25 Group 19. Flash Memory
19. Flash Memory
19.1 Overview
In the flash memory, rewrite operations to the flash memory can be performed in three modes: CPU rewrite,
standard serial I/O, and parallel I/O.
Table 19.1 lists the Flash Memory Performance (refer to Table 1.1 Functions and Specifications for R8C/24
Group and Table 1.2 Functions and Specifications for R8C/25 Group for items not listed in Table 19.1).
Table 19.1 Flash Memory Performance

Item Specification
Flash
www.DataSheet4U.com memory operating mode 3 modes (CPU rewrite, standard serial I/O, and parallel I/O)
Division of erase block Refer to Figure 19.1 and Figure 19.2
Programming method Byte unit
Erase method Block erase
Programming and erasure control method(3) Program and erase control by software command
Rewrite control method Rewrite control for blocks 0 and 1 by FMR02 bit in FMR0 register
Rewrite control for block 0 by FMR15 bit and Block 1 by FMR16 bit in
FMR1 register
Number of commands 5 commands
Programming and Blocks 0 and 1 (program R8C/24 Group: 100 times; R8C/25 Group: 1,000 times
erasure ROM)
endurance(1) Blocks A and B (data 10,000 times
flash)(2)
ID code check function Standard serial I/O mode supported
ROM code protect Parallel I/O mode supported
NOTES:
1. Definition of programming and erasure endurance
The programming and erasure endurance is defined on a per-block basis. If the programming and erasure
endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are
performed to block A, a 1-Kbyte block, and then the block is erased, the erase count stands at one. When
performing 100 or more rewrites, the actual erase count can be reduced by executing programming operations
in such a way that all blank areas are used before performing an erase operation. Avoid rewriting only particular
blocks and try to average out the programming and erasure endurance of the blocks. It is also advisable to
retain data on the erase count of each block and limit the number of erase operations to a certain number.
2. Blocks A and B are implemented only in the R8C/25 group.
3. To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform
programming and erasure at less than 2.7 V.
Table 19.2 Flash Memory Rewrite Modes

Flash memory Standard Serial I/O
CPU Rewrite Mode Parallel I/O Mode
Rewrite mode Mode
Function User ROM area is rewritten by executing User ROM area is User ROM area is
software commands from the CPU. rewritten by a rewritten by a
EW0 mode: Rewritable in the RAM dedicated serial dedicated parallel
EW1 mode: Rewritable in flash memory programmer. programmer.
Areas which can User ROM area User ROM area User ROM area
be rewritten
Operating mode Single chip mode Boot mode Parallel I/O mode
ROM Programmer None Serial programmer Parallel programmer
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19.2 Memory Map

The flash memory contains a user ROM area and a boot ROM area (reserved area). Figure 19.1 shows the Flash
Memory Block Diagram for R8C/24 Group. Figure 19.2 shows a Flash Memory Block Diagram for R8C/25 Group.
The user ROM area of the R8C/25 Group contains an area (program ROM) which stores MCU operating programs
and blocks A and B (data flash) each 1 Kbyte in size.
The user ROM area is divided into several blocks. The user ROM area can be rewritten in CPU rewrite mode and
standard serial I/O and parallel I/O modes.
When rewriting blocks 0 and 1 in CPU rewrite mode, set the FMR02 bit in the FMR0 register to 1 (rewrite
enabled). When the FMR15 bit in the FMR1 register is set to 0 (rewrite enabled), block 0 is rewritable. When the
FMR16 bit is set to 0 (rewrite enabled), block 1 is rewritable.
The rewrite control program for standard serial I/O mode is stored in the boot ROM area before shipment. The boot
ROM area and the user ROM area share the same address, but have separate memory areas.
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48 Kbytes ROM product 64 Kbytes ROM product

04000h 04000h
32 Kbytes ROM product

08000h Block 1: 32 Kbytes(1) Block 1: 32 Kbytes(1)
(1)
Block 1: 16 Kbytes
0BFFFh 0BFFFh 0BFFFh
0C000h 0C000h 0C000h
Program ROM
Block 0: 16 Kbytes(1) Block 0: 16 Kbytes(1)

0FFFFh 0FFFFh 0FFFFh
10000h Block 0: 32 Kbytes(1)
User ROM area User ROM area
13FFFh
User ROM area
24 Kbytes ROM product

0A000h Program ROM
Block 1: 8 Kbytes(1)
0BFFFh 16 Kbytes ROM product
0C000h 0C000h

0E000h
8 Kbytes
User ROM area User ROM area Boot ROM area
(reserved area)(2)
NOTES:
1. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled) and the FMR15 bit in the FMR1 register is set to 0 (rewrite
enabled), block 0 is rewritable. When the FMR16 bit is set to 0 (rewrite enabled), block 1 is rewritable (only for CPU rewrite mode).
2. This area is for storing the boot program provided by Renesas Technology.
Figure 19.1 Flash Memory Block Diagram for R8C/24 Group
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32 Kbytes ROM product 48 Kbytes ROM product 64 Kbytes ROM product

02400h Block A: 1 Kbyte 02400h Block A: 1 Kbyte 02400h Block A: 1 Kbyte
Data flash
Block B: 1 Kbyte Block B: 1 Kbyte Block B: 1 Kbyte
02BFFh 02BFFh 02BFFh
04000h 04000h
08000h Block 1: 32 Kbytes(1) Block 1: 32 Kbytes(1)

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Block 1: 16 Kbytes(1)
0BFFFh 0BFFFh 0BFFFh
0C000h 0C000h 0C000h
Program ROM
(1)
Block 0: 16 Kbytes Block 0: 16 Kbytes(1)
10000h Block 0: 32 Kbytes(1)
User ROM area User ROM area
13FFFh
User ROM area
24 Kbytes ROM product 16 Kbytes ROM product

02400h Block A: 1 Kbyte 02400h Block A: 1 Kbyte
Data flash
Block B: 1 Kbyte Block B: 1 Kbyte
02BFFh 02BFFh
0A000h
Block 1: 8 Kbytes(1) Program ROM
0BFFFh
0C000h 0C000h
0E000h
8 Kbytes
User ROM area User ROM area Boot ROM area
(reserved area)(2)
NOTES:
1. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled) and the FMR15 bit in the FMR1 register is set to 0 (rewrite
enabled), block 0 is rewritable. When the FMR16 bit is set to 0 (rewrite enabled), block 1 is rewritable (only for CPU rewrite mode).
2. This area is for storing the boot program provided by Renesas Technology.
Figure 19.2 Flash Memory Block Diagram for R8C/25 Group
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19.3 Functions to Prevent Rewriting of Flash Memory

Standard serial I/O mode has an ID code check function, and parallel I/O mode has a ROM code protect function to
prevent the flash memory from being read or rewritten easily.
19.3.1 ID Code Check Function

This function is used in standard serial I/O mode. Unless the flash memory is blank, the ID codes sent from the
programmer and the ID codes written in the flash memory are checked to see if they match. If the ID codes do
not match, the commands sent from the programmer are not acknowledged. The ID codes consist of 8 bits of
data each, the areas of which, beginning with the first byte, are 00FFDFh, 00FFE3h, 00FFEBh, 00FFEFh,
00FFF3h, 00FFF7h, and 00FFFBh. Write programs in which the ID codes are set at these addresses and write
them to the flash memory.
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Address
00FFDFh to 00FFDCh ID1 Undefined instruction vector
00FFE3h to 00FFE0h ID2 Overflow vector
00FFE7h to 00FFE4h BRK instruction vector
00FFEBh to 00FFE8h ID3 Address match vector
00FFEFh to 00FFECh ID4 Single step vector

Oscillation stop detection/watchdog
00FFF3h to 00FFF0h ID5 timer/voltage monitor 1 and voltage
monitor 2 vector
00FFF7h to 00FFF4h ID6 Address break
00FFFBh to 00FFF8h ID7 (Reserved)
00FFFFh to 00FFFCh (Note 1) Reset vector
4 bytes
NOTE:
1. The OFS register is assigned to 00FFFFh.
Refer to Figure 19.4 OFS Register for OFS register details.
Figure 19.3 Address for Stored ID Code
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19.3.2 ROM Code Protect Function

The ROM code protect function disables reading or changing the contents of the on-chip flash memory by the
OFS register in parallel I/O mode. Figure 19.4 shows the OFS Register.
The ROM code protect function is enabled by writing 0 to the ROMCP1 bit and 1 to the ROMCR bit. It disables
reading or changing the contents of the on-chip flash memory.
Once ROM code protect is enabled, the content in the internal flash memory cannot be rewritten in parallel I/O
mode. To disable ROM code protect, erase the block including the OFS register with CPU rewrite mode or
standard serial I/O mode.

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b7 b6 b5 b4 b3 b2 b1 b0

OFS 0FFFFh FFh(3)
WDTON RW
RW
(b1)
ROMCR RW
ROMCP1 RW
RW
(b4)
reset
RW
(b6)
bit
NOTES:
Figure 19.4 OFS Register
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19.4 CPU Rewrite Mode

In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU.
Therefore, the user ROM area can be rewritten directly while the MCU is mounted on a board without using a
ROM programmer. Execute the program and block erase commands only to blocks in the user ROM area.
The flash module has an erase-suspend function when an interrupt request is generated during an erase operation in
CPU rewrite mode. It performs an interrupt process after the erase operation is halted temporarily. During erase-
suspend, the user ROM area can be read by a program.
In case an interrupt request is generated during an auto-program operation in CPU rewrite mode, the flash module
has a program-suspend function which performs the interrupt process after the auto-program operation is
suspended. During program-suspend, the user ROM area can be read by a program.
CPU rewrite mode has an erase write 0 mode (EW0 mode) and an erase write 1 mode (EW1 mode). Table 19.3 lists
the
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Differences between EW0 Mode and EW1 Mode.
Table 19.3 Differences between EW0 Mode and EW1 Mode

Item EW0 Mode EW1 Mode
Operating mode Single-chip mode Single-chip mode
Areas in which a rewrite User ROM area User ROM area
control program can be
located
Areas in which a rewrite Necessary to transfer to any area other Executing directly in user ROM or RAM
control program can be than the flash memory (e.g., RAM) before area possible
executed executing
Areas which can be User ROM area User ROM area
rewritten However, blocks which contain a rewrite
control program are excluded(1)
Software command None • Program and block erase commands
restrictions Cannot be run on any block which
contains a rewrite control program
• Read status register command
Cannot be executed
Modes after program or Read status register mode Read array mode
erase
Modes after read status Read status register mode Do not execute this command
register
CPU status during auto- Operating Hold state (I/O ports hold state before the
write and auto-erase command is executed)
Flash memory status • Read bits FMR00, FMR06, and FMR07 Read bits FMR00, FMR06, and FMR07 in
detection in the FMR0 register by a program the FMR0 register by a program
• Execute the read status register
command and read bits SR7, SR5, and
SR4 in the status register.
Conditions for transition to Set bits FMR40 and FMR41 in the FMR4 The FMR40 bit in the FMR4 register is set
erase-suspend register to 1 by a program. to 1 and the interrupt request of the
enabled maskable interrupt is generated
Conditions for transitions to Set bits FMR40 and FMR42 in the FMR4 The FMR40 bit in the FMR4 register is set
program-suspend register to 1 by a program. to 1 and the interrupt request of the
enabled maskable interrupt is generated
CPU clock 5 MHz or below No restriction (on clock frequency to be
used)
NOTE:
1. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled), rewriting block 0 is enabled by setting
the FMR15 bit in the FMR1 register to 0 (rewrite enabled), and rewriting block 1 is enabled by setting the
FMR16 bit to 0 (rewrite enabled).
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19.4.1 EW0 Mode

The MCU enters CPU rewrite mode and software commands can be acknowledged by setting the FMR01 bit in
the FMR0 register to 1 (CPU rewrite mode enabled). In this case, since the FMR11 bit in the FMR1 register is
set to 0, EW0 mode is selected.
Use software commands to control program and erase operations. The FMR0 register or the status register can
be used to determine when program and erase operations complete.
During auto-erasure, set the FMR40 bit to 1 (erase-suspend enabled) and the FMR41 bit to 1 (request erase-
suspend). Wait for td(SR-SUS) and ensure that the FMR46 bit is set to 1 (read enabled) before accessing the
user ROM area. The auto-erase operation can be restarted by setting the FMR41 bit to 0 (erase restarts).
To enter program-suspend during the auto-program operation, set the FMR40 bit to 1 (suspend enabled) and the
FMR42 bit to 1 (request program-suspend). Wait for td(SR-SUS) and ensure that the FMR46 bit is set to 1 (read
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enabled) before accessing the user ROM area. The auto-program operation can be restarted by setting the
FMR42 bit to 0 (program restarts).
19.4.2 EW1 Mode

The MCU is switched to EW1 mode by setting the FMR11 bit to 1 (EW1 mode) after setting the FMR01 bit to
1 (CPU rewrite mode enabled).
The FMR0 register can be used to determine when program and erase operations complete. Do not execute
commands that use the read status register in EW1 mode.
To enable the erase-suspend function during auto-erasure, execute the block erase command after setting the
FMR40 bit to 1 (erase-suspend enabled). The interrupt to enter erase-suspend should be in interrupt enabled
status. After waiting for td(SR-SUS) after the block erase command is executed, the interrupt request is
acknowledged.
When an interrupt request is generated, the FMR41 bit is automatically set to 1 (requests erase-suspend) and the
auto-erase operation suspends. If an auto-erase operation does not complete (FMR00 bit is 0) after an interrupt
process completes, the auto-erase operation restarts by setting the FMR41 bit to 0 (erasure restarts)
To enable the program-suspend function during auto-programming, execute the program command after setting
the FMR40 bit to 1 (suspend enabled). The interrupt to enter program-suspend should be in interrupt enabled
status. After waiting for td(SR-SUS) after the program command is executed, an interrupt request is
acknowledged.
When an interrupt request is generated, the FMR42 bit is automatically set to 1 (request program-suspend) and
the auto-program operation suspends. When the auto-program operation does not complete (FMR00 bit is 0)
after the interrupt process completes, the auto-program operation can be restarted by setting the FMR42 bit to 0
(programming restarts).
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Figure 19.5 shows the FMR0 Register. Figure 19.6 shows the FMR1 Register. Figure 19.7 shows the FMR4
Register.
19.4.2.1 FMR00 Bit

This bit indicates the operating status of the flash memory. The bits value is 0 during programming, erasure
(including suspend periods), or erase-suspend mode; otherwise, it is 1.
19.4.2.2 FMR01 Bit

The MCU is made ready to accept commands by setting the FMR01 bit to 1 (CPU rewrite mode).
19.4.2.3
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FMR02 Bit
Rewriting of blocks 0 and 1 does not accept program or block erase commands if the FMR02 bit is set to 0
(rewrite disabled).
Rewriting of blocks 0 and 1 is controlled by bits FMR15 and FMR16 if the FMR02 bit is set to 1 (rewrite
enabled).
19.4.2.4 FMSTP Bit

This bit is used to initialize the flash memory control circuits, and also to reduce the amount of current
consumed by the flash memory. Access to the flash memory is disabled by setting the FMSTP bit to 1.
Therefore, the FMSTP bit must be written to by a program transferred to the RAM.
In the following cases, set the FMSTP bit to 1:
• When flash memory access resulted in an error while erasing or programming in EW0 mode (FMR00 bit
not reset to 1 (ready))
• To provide lower consumption in high-speed on-chip oscillator mode, low-speed on-chip oscillator mode
(XIN clock stops), and low-speed clock mode (XIN clock stops).
Figure 19.11 shows the handling to provide lower consumption in high-speed on-chip oscillator mode, low-
speed on-chip oscillator mode (XIN clock stops), and low-speed clock mode (XIN clock stops). Handle
according to this flowchart. Note that when going to stop or wait mode while the CPU rewrite mode is disabled,
the FMR0 register does not need to be set because the power for the flash memory is automatically turned off
and is turned back on again after returning from stop or wait mode.
19.4.2.5 FMR06 Bit

This is a read-only bit indicating the status of an auto-program operation. The bit is set to 1 when a program
error occurs; otherwise, it is set to 0. For details, refer to the description in 19.4.5 Full Status Check.
19.4.2.6 FMR07 Bit

This is a read-only bit indicating the status of an auto-erase operation. The bit is set to 1 when an erase error
occurs; otherwise, it is set to 0. Refer to 19.4.5 Full Status Check for details.
19.4.2.7 FMR11 Bit

Setting this bit to 1 (EW1 mode) places the MCU in EW1 mode.
19.4.2.8 FMR15 Bit

When the FMR02 bit is set to 1 (rewrite enabled) and the FMR15 bit is set to 0 (rewrite enabled), block 0
accepts program and block erase commands.
19.4.2.9 FMR16 Bit

When the FMR02 bit is set to 1 (rewrite enabled) and the FMR16 bit is set to 0 (rewrite enabled), block 1
accepts program and block erase commands.
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19.4.2.10 FMR40 Bit

The suspend function is enabled by setting the FMR40 bit to 1 (enable).
19.4.2.11 FMR41 Bit

In EW0 mode, the MCU enters erase-suspend mode when the FMR41 bit is set to 1 by a program. The FMR41
bit is automatically set to 1 (request erase-suspend) when an interrupt request of an enabled interrupt is
generated in EW1 mode, and then the MCU enters erase-suspend mode.
Set the FMR41 bit to 0 (erase restarts) when the auto-erase operation restarts.
19.4.2.12 FMR42 Bit

www.DataSheet4U.com In EW0 mode, the MCU enters program-suspend mode when the FMR42 bit is set to 1 by a program. The
FMR42 bit is automatically set to 1 (request program-suspend) when an interrupt request of an enabled
interrupt is generated in EW1 mode, and then the MCU enters program-suspend mode.
Set the FMR42 bit to 0 (program restart) when the auto-program operation restarts.
19.4.2.13 FMR43 Bit

When the auto-erase operation starts, the FMR43 bit is set to 1 (erase execution in progress). The FMR43 bit
remains set to 1 (erase execution in progress) during erase-suspend operation.
When the auto-erase operation ends, the FMR43 bit is set to 0 (erase not executed).
19.4.2.14 FMR44 Bit

When the auto-program operation starts, the FMR44 bit is set to 1 (program execution in progress). The FMR44
bit remains set to 1 (program execution in progress) during program-suspend operation.
When the auto-program operation ends, the FMR44 bit is set to 0 (program not executed).
19.4.2.15 FMR46 Bit

The FMR46 bit is set to 0 (reading disabled) during auto-program or auto-erase execution and set to 1 (reading
enabled) in suspend mode. Do not access the flash memory while this bit is set to 0.
19.4.2.16 FMR47 Bit

Power consumption when reading the flash memory can be reduced by setting the FMR47 bit to 1 (enabled) in
low-speed clock mode (XIN clock stops) and low-speed on-chip oscillator mode (XIN clock stops).
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Flash Memory Control Register 0

b7 b6 b5 b4 b3 b2 b1 b0

FMR0 01B7h 00000001b
___
RY/BY status flag 0 : Busy (w riting or erasing in progress)
FMR00 RO
1 : Ready
CPU rew rite mode select bit(1) 0 : CPU rew rite mode disabled
FMR01 RW
1 : CPU rew rite mode enabled
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Block 0, 1 rew rite enable bit(2, 6) 0 : Disables rew rite
FMR02 RW
1 : Enables rew rite
Flash memory stop bit(3, 5) 0 : Enables flash memory operation
1 : Stops flash memory
FMSTP (enters low -pow er consumption state RW
and flash memory is reset)
RW
(b5-b4)
Program status flag(4) 0 : Completed successfully
FMR06 RO
1 : Terminated by error
Erase status flag(4) 0 : Completed successfully
FMR07 RO
1 : Terminated by error
NOTES:
1. To set this bit to 1, set it to 1 immediately after setting it first to 0. Do not generate an interrupt betw een setting the bit
to 0 and setting it to 1. Enter read array mode and set this bit to 0.
2. Set this bit to 1 immediately after setting it first to 0 w hile the FMR01 bit is set to 1.
Do not generate an interrupt betw een setting the bit to 0 and setting it to 1.
3. Set this bit by a program transferred to the RAM.
4. This bit is set to 0 by executing the clear status command.
5. This bit is enabled w hen the FMR01 bit is set to 1 (CPU rew rite mode enabled). When the FMR01 bit is set to 0,
w riting 1 to the FMSTP bit causes the FMSTP bit to be set to 1. The flash memory does not enter low -pow er
consumption state nor is it reset.
6. When setting the FMR01 bit to 0 (CPU rew rite mode disabled), the FMR02 bit is set to 0 (disables rew rite).
Figure 19.5 FMR0 Register
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b7 b6 b5 b4 b3 b2 b1 b0

FMR1 01B5h 1000000Xb
— Reserved bit When read, the content is undefined.
RO
(b0)
(1, 2)
EW1 mode select bit 0 : EW0 mode
FMR11 RW
1 : EW1 mode
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RW
(b4-b2)
(2,3)
Block 0 rew rite disable bit 0 : Enables rew rite
FMR15 RW
1 : Disables rew rite
(2,3)
Block 1 rew rite disable bit 0 : Enables rew rite
FMR16 RW
1 : Disables rew rite
RW
(b7)
NOTES:
1. To set this bit to 1, set it to 1 immediately after setting it first to 0 w hile the FMR01 bit is set to 1 (CPU rew rite mode
enable). Do not generate an interrupt betw een setting the bit to 0 and setting it to 1.
2. This bit is set to 0 by setting the FMR01 bit to 0 (CPU rew rite mode disabled).
3. When the FMR01 bit is set to 1 (CPU rew rite mode enabled), bits FMR15 and FMR16 can be w ritten to.
To set this bit to 0, set it to 0 immediately after setting it first to 1.
To set this bit to 1, set it to 1.
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b7 b6 b5 b4 b3 b2 b1 b0

FMR4 01B3h 01000000b
Erase-suspend function 0 : Disable
FMR40 RW
(2)
Erase-suspend request bit 0 : Erase restart
FMR41 RW
1 : Erase-suspend request
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Program-suspend request bit 0 : Program restart
FMR42 RW
1 : Program-suspend request
Erase command flag 0 : Erase not executed
FMR43 RO
1 : Erase execution in progress
Program command flag 0 : Program not executed
FMR44 RO
1 : Program execution in progress
RO
(b5)
Read status flag 0 : Disables reading
FMR46 RO
1 : Enables reading
Low -pow er consumption read 0 : Disable
FMR47 RW
mode enable bit (1, 4, 5) 1 : Enable
NOTES:
1. To set this bit to 1, set it to 1 immediately after setting it first to 0. Do not generate an interrupt betw een setting the bit
to 0 and setting it to 1.
2. This bit is enabled w hen the FMR40 bit is set to 1 (enable) and it can be w ritten to during the period betw een issuing
an erase command and completing the erase. (This bit is set to 0 during periods other than above.)
In EW0 mode, it can be set to 0 or 1 by a program.
In EW1 mode, it is automatically set to 1 if a maskable interrupt is generated during an erase
operation w hile the FMR40 bit is set to 1. Do not set this bit to 1 by a program (0 can be w ritten).
3. The FMR42 bit is enabled only w hen the FMR40 bit is set to 1 (enable) and programming to the FMR42 bit is enabled
until auto-programming ends after a program command is generated. (This bit is set to 0 during periods other than the
above.)
In EW0 mode, 0 or 1 can be programmed to the FMR42 bit by a program.
In EW1 mode, the FMR42 bit is automatically set to 1 by generating a maskable interrupt during auto-programming
w hen the FMR40 bit is set to 1. 1 cannot be w ritten to the FMR42 bit by a program.
4. In high-speed clock mode and high-speed on-chip oscillator mode, set the FMR47 bit to 0 (disabled).
5. Set the FMR01 bit in the FMR0 register to 0 (CPU rew rite mode disabled) in low -pow er consumption read mode.
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Figure 19.8 shows the Timing of Suspend Operation.
Erasure Erasure Programming Programming Programming Programming Erasure Erasure

starts suspends starts suspends restarts ends restarts ends
During erasure During programming During programming During erasure
FMR00 bit in 1
Remains 0 during suspend
FMR0 register 0
FMR46 bit in
FMR4 register 0
FMR44 bit in 1
FMR4 register 0
FMR43 bit in 1
FMR4 register 0 Remains 1 during suspend
Check that the Check that the Check the status, Check the status,
FMR43 bit is set to 1 FMR44 bit is set to 1 and that the and that the
(during erase (during program programming ends erasure ends
execution), and that execution), and that normally. normally.
the erase-operation the program has not
has not ended. ended.
The above figure shows an example of the use of program-suspend during programming following erase-suspend.
NOTE:
1. If program-suspend is entered during erase-suspend, always restart programming.
Figure 19.8 Timing of Suspend Operation
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Figure 19.9 shows the How to Set and Exit EW0 Mode. Figure 19.10 shows the How to Set and Exit EW1
Mode.
EW0 Mode Operating Procedure

Rewrite control program
Write 0 to the FMR01 bit before writing 1

(CPU rewrite mode enabled)(2)
Set registers(1) CM0 and CM1

Execute software commands
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Transfer a rewrite control program which uses CPU

rewrite mode to the RAM. Execute the read array command(3)
Write 0 to the FMR01 bit

Jump to the rewrite control program which has been (CPU rewrite mode disabled)
transferred to the RAM.
(The subsequent process is executed by the rewrite
control program in the RAM.)
Jump to a specified address in the flash memory
NOTES:
1. Select 5 MHz or below for the CPU clock by the CM06 bit in the CM0 register and bits CM16 to CM17 in the CM1 register.
2. To set the FMR01 bit to 1, write 0 to the FMR01 bit before writing 1. Do not generate an interrupt between writing 0 and 1.
Write to the FMR01 bit in the RAM.
3. Disable the CPU rewrite mode after executing the read array command.
Figure 19.9 How to Set and Exit EW0 Mode
EW1 Mode Operating Procedure
Program in ROM
Write 0 to the FMR01 bit before writing 1 (CPU

rewrite mode enabled)(1)
Write 0 to the FMR11 bit before writing 1 (EW1
mode)
Execute software commands

(CPU rewrite mode disabled)
NOTE:
1. To set the FMR01 bit to 1, write 0 to the FMR01 bit before writing 1.
Do not generate an interrupt between writing 0 and 1.
Figure 19.10 How to Set and Exit EW1 Mode
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High-speed on-chip oscillator mode,

low-speed on-chip oscillator mode
(XIN clock stops), and low-speed
clock mode (XIN clock stops)
program
Transfer a high-speed on-chip oscillator mode, low-
speed on-chip oscillator mode (XIN clock stops), and
low-speed clock mode (XIN clock stops) program to Write 0 to the FMR01 bit before writing 1
the RAM. (CPU rewrite mode enabled)
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Jump to the high-speed on-chip oscillator mode, low- Write 1 to the FMSTP bit (flash memory stops.
speed on-chip oscillator mode (XIN clock stops), and low power consumption mode)(1)
low-speed clock mode (XIN clock stops) program
which has been transferred to the RAM.
(The subsequent processing is executed by the
Switch the clock source for the CPU clock.
program in the RAM.)
Turn XIN off
Process in high-speed on-chip oscillator

mode, low-speed on-chip oscillator mode
(XIN clock stops), and low-speed clock
mode (XIN clock stops)
Turn XIN clock on → wait until oscillation

stabilizes → switch the clock source for CPU
clock(2)
Write 0 to the FMSTP bit

(flash memory operation)

(CPU rewrite mode disabled)
NOTES:
1. Set the FMR01 bit to 1 (CPU rewrite mode enabled) before setting the
FMSTP bit to 1.
2. Before switching to a different clock source for the CPU, make sure
Wait until the flash memory circuit stabilizes
the designated clock is stable. (30 µs)(3)
3. Insert a 30 µs wait time in a program. Do not access to the flash
memory during this wait time.
Jump to a specified address in the flash memory
Figure 19.11 Process to Reduce Power Consumption in High-Speed On-Chip Oscillator Mode,
Low-Speed On-Chip Oscillator Mode (XIN Clock Stops) and Low-Speed Clock Mode
(XIN Clock Stops)
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19.4.3 Software Commands

The software commands are described below. Read or write commands and data in 8-bit units.
Table 19.4 Software Commands

First Bus Cycle Second Bus Cycle
Command Data Data
Mode Address Mode Address
(D7 to D0) (D7 to D0)
Read array Write × FFh
Read status register Write × 70h Read × SRD
Clear status register Write × 50h
Program
www.DataSheet4U.com Write WA 40h Write WA WD
Block erase Write × 20h Write BA D0h
SRD: Status register data (D7 to D0)
WA: Write address (ensure the address specified in the first bus cycle is the same address as the write
address specified in the second bus cycle.)
WD: Write data (8 bits)
BA: Given block address
×: Any specified address in the user ROM area
19.4.3.1 Read Array Command

The read array command reads the flash memory.
The MCU enters read array mode when FFh is written in the first bus cycle. When the read address is entered in
the following bus cycles, the content of the specified address can be read in 8-bit units.
Since the MCU remains in read array mode until another command is written, the contents of multiple
addresses can be read continuously.
In addition, the MCU enters read array mode after a reset.
19.4.3.2 Read Status Register Command

The read status register command is used to read the status register.
When 70h is written in the first bus cycle, the status register can be read in the second bus cycle (refer to 19.4.4
Status Registers). When reading the status register, specify an address in the user ROM area.
Do not execute this command in EW1 mode.
The MCU remains in read status register mode until the next read array command is written.
19.4.3.3 Clear Status Register Command

The clear status register command sets the status register to 0.
When 50h is written in the first bus cycle, bits FMR06 to FMR07 in the FMR0 register and SR4 to SR5 in the
status register are set to 0.
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19.4.3.4 Program Command

The program command writes data to the flash memory in 1-byte units.
By writing 40h in the first bus cycle and data in the second bus cycle to the write address, an auto-program
operation (data program and verify) will start. Make sure the address value specified in the first bus cycle is the
same address as the write address specified in the second bus cycle.
The FMR00 bit in the FMR0 register can be used to determine whether auto-programming has completed.
When suspend function disabled, the FMR00 bit is set to 0 during auto-programming and set to 1 when auto-
programming completes. When suspend function enabled, the FMR44 bit is set to 1 during auto-programming
and set to 0 when auto-programming completes.
The FMR06 bit in the FMR0 register can be used to determine the result of auto-programming after it has been
finished (refer to 19.4.5 Full Status Check).
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Do not write additions to the already programmed addresses.
When the FMR02 bit in the FMR0 register is set to 0 (rewriting disabled), or the FMR02 bit is set to 1 (rewrite
enabled) and the FMR15 bit in the FMR1 register is set to 1 (rewriting disabled), program commands targeting
block 0 are not acknowledged. When the FMR16 bit is set to 1 (rewriting disabled), program commands
targeting block 1 are not acknowledged.
Figure 19.12 shows the Program Command (When Suspend Function Disabled). Figure 19.13 shows the
Program Command (When Suspend Function Enabled).
In EW1 mode, do not execute this command for any address which a rewrite control program is allocated.
In EW0 mode, the MCU enters read status register mode at the same time auto-programming starts and the
status register can be read. The status register bit 7 (SR7) is set to 0 at the same time auto-programming starts
and set back to 1 when auto-programming completes. In this case, the MCU remains in read status register
mode until the next read array command is written. The status register can be read to determine the result of
auto-programming after auto-programming has completed.
Start
Write the command code 40h to

the write address
Write data to the write address
No
FMR00 = 1?
Yes
Full status check
Program completed
Figure 19.12 Program Command (When Suspend Function Disabled)
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EW0 Mode Start Maskable interrupt(1)
FMR40 = 1 No
FMR44 = 1 ?
Write the command code 40h Yes

to the write address
FMR42 = 1(4)
I = 1 (enable interrupt)(3)
www.DataSheet4U.com No
FMR46 = 1 ?
Access flash memory

Write data to the write address Yes
Access flash memory
No
FMR44 = 0 ?
FMR42 = 0
Yes
Full status check REIT
Program completed
EW1 Mode Start Maskable interrupt (2)
FMR40 = 1 Access flash memory
REIT
Write the command code 40h
I = 1 (enable interrupt)
Write data to the write address
FMR42 = 0
No
FMR44 = 0 ?
Yes
Full status check
Program completed
NOTES:
1. In EW0 mode, the interrupt vector table and interrupt routine for interrupts to be used should be allocated to the RAM area.
2. td(SR-SUS) is needed until the interrupt request is acknowledged after it is generated. The interrupt to enter suspend
should be in interrupt enabled status.
3. When no interrupt is used, the instruction to enable interrupts is not needed.
4. td(SR-SUS) is needed until program is suspended after the FMR42 bit in the FMR4 register is set to 1.
Figure 19.13 Program Command (When Suspend Function Enabled)
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19.4.3.5 Block Erase

When 20h is written in the first bus cycle and D0h is written to a given address of a block in the second bus
cycle, an auto-erase operation (erase and verify) of the specified block starts.
The FMR00 bit in the FMR0 register can be used to determine whether auto-erasure has completed.
The FMR00 bit is set to 0 during auto-erasure and set to 1 when auto-erasure completes.
The FMR07 bit in the FMR0 register can be used to determine the result of auto-erasure after auto-erasure has
completed (refer to 19.4.5 Full Status Check).
When the FMR02 bit in the FMR0 register is set to 0 (rewriting disabled) or the FMR02 bit is set to 1 (rewriting
enabled) and the FMR15 bit in the FMR1 register is set to 1 (rewriting disabled), the block erase commands
targeting block 0 are not acknowledged. When the FMR16 bit is set to 1 (rewriting disabled), block erase
commands targeting block 1 are not acknowledged.
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Do not use the block erase command during program-suspend.
Figure 19.14 shows the Block Erase Command (When Erase-Suspend Function Disabled). Figure 19.15 shows
the Block Erase Command (When Erase-Suspend Function Enabled).
In EW1 mode, do not execute this command for any address to which a rewrite control program is allocated.
In EW0 mode, the MCU enters read status register mode at the same time auto-erasure starts and the status
register can be read. The status register bit 7 (SR7) is set to 0 at the same time auto-erasure starts and set back to
1 when auto-erasure completes. In this case, the MCU remains in read status register mode until the next read
array command is written.
Start
Write D0h to a given block

address
No
FMR00 = 1?
Yes
Full status check
Block erase completed
Figure 19.14 Block Erase Command (When Erase-Suspend Function Disabled)
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EW0 Mode Start Maskable interrupt(1)
FMR40 = 1 No
FMR43 = 1 ?
Write the command code 20h Yes
FMR41 = 1(4)
I = 1 (enable interrupt)(3)
www.DataSheet4U.com No
FMR46 = 1 ?
Write D0h to any block
address Access flash memory
Yes
Access flash memory

No
FMR00 = 1 ?
FMR41 = 0
Yes
Full status check

REIT
EW1 Mode Start Maskable interrupt (2)
FMR40 = 1 Access flash memory

REIT
I = 1 (enable interrupt)
Write D0h to any block

address
FMR41 = 0
No
FMR00 = 1 ?
Yes
Full status check
NOTES:
1. In EW0 mode, the interrupt vector table and interrupt routine for interrupts to be used should be allocated to the RAM area.
2. td(SR-SUS) is needed until the interrupt request is acknowledged after it is generated. The interrupt to enter suspend
should be in interrupt enabled status.
3. When no interrupt is used, the instruction to enable interrupts is not needed.
4. td(SR-SUS) is needed until erase is suspended after the FMR41 bit in the FMR4 register is set to 1.
Figure 19.15 Block Erase Command (When Erase-Suspend Function Enabled)
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19.4.4 Status Registers

The status register indicates the operating status of the flash memory and whether an erase or program operation
has completed normally or in error. Status of the status register can be read by bits FMR00, FMR06, and
FMR07 in the FMR0 register.
Table 19.5 lists the Status Register Bits.
In EW0 mode, the status register can be read in the following cases:
• When a given address in the user ROM area is read after writing the read status register command
• When a given address in the user ROM area is read after executing program or block erase command but
before executing the read array command.
19.4.4.1 Sequencer Status (Bits SR7 and FMR00)

www.DataSheet4U.com The sequencer status bits indicate the operating status of the flash memory. SR7 is set to 0 (busy) during auto-
programming and auto-erasure, and is set to 1 (ready) at the same time the operation completes.
19.4.4.2 Erase Status (Bits SR5 and FMR07)

Refer to 19.4.5 Full Status Check.
19.4.4.3 Program Status (Bits SR4 and FMR06)

Refer to 19.4.5 Full Status Check.
Table 19.5 Status Register Bits

FMR0 Register Description Value after
Status Register Bit Status Name
Bit 0 1 Reset
SR0 (D0) − Reserved − − −
SR4 (D4) FMR06 Program status Completed Error 0
normally
SR5 (D5) FMR07 Erase status Completed Error 0
normally
SR7 (D7) FMR00 Sequencer Busy Ready 1
status
D0 to D7: Indicate the data bus which is read when the read status register command is executed.
Bits FMR07 (SR5) to FMR06 (SR4) are set to 0 by executing the clear status register command.
When the FMR07 bit (SR5) or FMR06 bit (SR4) is set to 1, the program and block erase commands cannot
be accepted.
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19.4.5 Full Status Check

When an error occurs, bits FMR06 to FMR07 in the FMR0 register are set to 1, indicating the occurrence of an
error. Therefore, checking these status bits (full status check) can be used to determine the execution result.
Table 19.6 lists the Errors and FMR0 Register Status. Figure 19.16 shows the Full Status Check and Handling
Procedure for Individual Errors.
Table 19.6 Errors and FMR0 Register Status

FMR0 Register (Status
Register) Status Error Error Occurrence Condition
FMR07(SR5) FMR06(SR4)
1 1 Command • When a command is not written correctly
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sequence • When invalid data other than that which can be written
error in the second bus cycle of the block erase command is
written (i.e., other than D0h or FFh)(1)
• When the program command or block erase command
is executed while rewriting is disabled by the FMR02 bit
in the FMR0 register, or the FMR15 or FMR16 bit in the
FMR1 register.
• When an address not allocated in flash memory is input
during erase command input
• When attempting to erase the block for which rewriting
is disabled during erase command input.
• When an address not allocated in flash memory is input
during write command input.
• When attempting to write to a block for which rewriting
is disabled during write command input.
1 0 Erase error • When the block erase command is executed but auto-
erasure does not complete correctly
0 1 Program error • When the program command is executed but not auto-
programming does not complete.
NOTE:
1. The MCU enters read array mode when FFh is written in the second bus cycle of these commands.
At the same time, the command code written in the first bus cycle is disabled.
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Command sequence error
Full status check

Execute the clear status register command
(set these status flags to 0)
FMR06 = 1 Yes
and Command sequence error
FMR07 = 1? Check if command is properly input
No
Re-execute the command

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Yes Erase error

FMR07 = 1? Erase error
No
Execute the clear status register command
Erase command No Block targeting for erasure

re-execution times ≤ 3 times? cannot be used
Yes
FMR06 = 1? Program error Yes
Re-execute block erase command

No
Program error
Execute the clear status register

command
Full status check completed

Specify the other address besides the
write address where the error occurs for
the program address(1)
NOTE:
1. To rewrite to the address where the program error occurs, check if the full
status check is complete normally and write to the address after the block Re-execute program command
erase command is executed.
Figure 19.16 Full Status Check and Handling Procedure for Individual Errors
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19.5 Standard Serial I/O Mode

In standard serial I/O mode, the user ROM area can be rewritten while the MCU is mounted on-board by using a
serial programmer which is suitable for the MCU.
There are three types of Standard serial I/O modes:
• Standard serial I/O mode 1 ............Clock synchronous serial I/O used to connect with a serial programmer
• Standard serial I/O mode 2 ............Clock asynchronous serial I/O used to connect with a serial programmer
• Standard serial I/O mode 3 ............Special clock asynchronous serial I/O used to connect with a serial
programmer
This MCU uses Standard serial I/O mode 2 and Standard serial I/O mode 3.
Refer to Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator.
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Contact the manufacturer of your serial programmer for details. Refer to the user’s manual of your serial
programmer for instructions on how to use it.
Table 19.7 lists the Pin Functions (Flash Memory Standard Serial I/O Mode 2), Table 19.8 lists the Pin Functions
(Flash Memory Standard Serial I/O Mode 3), and Figure 19.17 shows Pin Connections for Standard Serial I/O
Mode 3.
After processing the pins shown in Table 19.8 and rewriting the flash memory using the programmer, apply “H” to
the MODE pin and reset the hardware to run a program in the flash memory in single-chip mode.
19.5.1 ID Code Check Function

The ID code check function determines whether the ID codes sent from the serial programmer and those written
in the flash memory match (refer to 19.3 Functions to Prevent Rewriting of Flash Memory).
Table 19.7 Pin Functions (Flash Memory Standard Serial I/O Mode 2)
Pin Name I/O Description
VCC,VSS Power input Apply the voltage guaranteed for programming and
erasure to the VCC pin and 0 V to the VSS pin.
RESET Reset input I Reset input pin.
P4_6/XIN P4_6 input/clock input I Connect a ceramic resonator or crystal oscillator
between the XIN and XOUT pins.
P4_7/XOUT P4_7 input/clock output I/O
P4_3/XCIN P4_3 input/clock input I Connect crystal oscillator between pins XCIN and
XCOUT.
P4_4/XCOUT P4_4 input/clock output I/O
P0_0 to P0_7 Input port P0 I Input “H” or “L” level signal or leave the pin open.
P3_0, P3_1, P3_3 to Input port P3 I Input “H” or “L” level signal or leave the pin open.
P3_5, P3_7
P4_2/VREF, P4_5 Input port P4 I Input “H” or “L” level signal or leave the pin open.
MODE MODE I Input “L” level signal.
P6_6 TXD output O Serial data output pin.
P6_7 RXD input I Serial data input pin.
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Table 19.8 Pin Functions (Flash Memory Standard Serial I/O Mode 3)
Pin Name I/O Description
VCC,VSS Power input Apply the voltage guaranteed for programming and
erasure to the VCC pin and 0 V to the VSS pin.
RESET Reset input I Reset input pin.
P4_6/XIN P4_6 input/clock input I Connect a ceramic resonator or crystal oscillator
between the XIN and XOUT pins when connecting
P4_7/XOUT P4_7 input/clock output I/O external oscillator. Apply “H” and “L” or leave the pin
open when using as input port.
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P4_3/XCIN P4_3 input/clock input I Connect crystal oscillator between pins XCIN and
XCOUT when connecting external oscillator. Apply “H”
P4_4/XCOUT P4_4 input/clock output I/O and “L” or leave the pin open when using as a port.
P3_0, P3_1, Input port P3 I Input “H” or “L” level signal or leave the pin open.
P3_3 to P3_5,
P3_7
P4_2/VREF, Input port P4 I Input “H” or “L” level signal or leave the pin open.
P4_5
MODE MODE I/O Serial data I/O pin. Connect to the flash programmer.
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39
38
37
36
35
34
33
32
31
30
29
28
27
40 26
41 25
42 24
43 23
44 22
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45 21
R8C/24 Group
46 20
R8C/25 Group
47 19
48 18
49 17
50 16
51 15
52 14
10
11
12
13
1
2
3
4
5
6
7
8
9
MODE VSS
VCC
Connect oscillator circuit(1)

Mode setting
Signal Value
MODE Voltage from programmer
Package: PLQP0052JA-A
RESET VSS → VCC
NOTE:
1. It is not necessary to connect an oscillating circuit
when operating with the on-chip oscillator clock.
Figure 19.17 Pin Connections for Standard Serial I/O Mode 3
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19.5.1.1 Example of Circuit Application in Standard Serial I/O Mode

Figure 19.18 shows an Example of Pin Processing in Standard Serial I/O Mode 2, and Figure 19.19 shows an
Example of Pin Processing in Standard Serial I/O Mode 3. Since the controlled pins vary depending on the
programmer, refer to the manual of your serial programmer for details.
MCU
Data Output TXD
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Data Input RXD
MODE
NOTES:
1. In this example, modes are switched between single-chip mode and
standard serial I/O mode by controlling the MODE input with a switch.
2. Connecting the oscillation is necessary. Set the main clock frequency 1
MHz to 20 MHz. Refer to Appendix Figure 2.1 Connection Example
with M16C Flash Starter (M3A-0806).
Figure 19.18 Example of Pin Processing in Standard Serial I/O Mode 2
MCU
MODE I/O MODE
Reset input RESET
User reset signal
NOTES:
1. Controlled pins and external circuits vary depending on the programmer.
Refer to the programmer manual for details.
2. In this example, modes are switched between single-chip mode and
standard serial I/O mode by connecting a programmer.
3. When operating with the on-chip oscillator clock, it is not necessary to
connect an oscillating circuit.
Figure 19.19 Example of Pin Processing in Standard Serial I/O Mode 3
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19.6 Parallel I/O Mode

Parallel I/O mode is used to input and output software commands, addresses and data necessary to control (read,
program, and erase) the on-chip flash memory. Use a parallel programmer which supports this MCU. Contact the
manufacturer of the parallel programmer for more information, and refer to the user’s manual of the parallel
programmer for details on how to use it.
ROM areas shown in Figures 19.1 and 19.2 can be rewritten in parallel I/O mode.
19.6.1 ROM Code Protect Function

The ROM code protect function disables the reading and rewriting of the flash memory. (Refer to 19.3
Functions to Prevent Rewriting of Flash Memory.)
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19.7 Notes on Flash Memory
19.7.1 CPU Rewrite Mode
19.7.1.1 Operating Speed

Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit
in the CM0 register and bits CM16 to CM17 in the CM1 register. This does not apply to EW1 mode.
19.7.1.2 Prohibited Instructions

The following instructions cannot be used in EW0 mode because they reference data in the flash memory:
www.DataSheet4U.com UND, INTO, and BRK.
19.7.1.3 Interrupts
Table 19.9 lists the EW0 Mode Interrupts, and Table 19.10 lists the EW1 Mode Interrupts.
Table 19.9 EW0 Mode Interrupts

When Watchdog Timer, Oscillation Stop
When Maskable Interrupt Detection, Voltage Monitor 1, or Voltage
Mode Status
Request is Acknowledged Monitor 2 Interrupt Request is
Acknowledged
EW0 During auto-erasure Any interrupt can be used by Once an interrupt request is
allocating a vector in RAM acknowledged, auto-programming or
auto-erasure is forcibly stopped
immediately and the flash memory is
reset. Interrupt handling starts after the
fixed period and the flash memory
restarts. Since the block during auto-
erasure or the address during auto-
Auto-programming programming is forcibly stopped, the
normal value may not be read. Execute
auto-erasure again and ensure it
completes normally.
Since the watchdog timer does not stop
during the command operation,
interrupt requests may be generated.
Reset the watchdog timer regularly.
NOTES:
1. Do not use the address match interrupt while a command is being executed because the vector of
the address match interrupt is allocated in ROM.
2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed
vector is allocated in block 0.
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When Watchdog Timer, Oscillation Stop
When Maskable Interrupt Detection, Voltage Monitor 1, or Voltage
Mode Status
Request is Acknowledged Monitor 2 Interrupt Request is
Acknowledged
EW1 During auto-erasure Auto-erasure is suspended after Once an interrupt request is
(erase-suspend td(SR-SUS) and interrupt acknowledged, auto-programming or
function enabled) handling is executed. Auto- auto-erasure is forcibly stopped
erasure can be restarted by immediately and the flash memory is
setting the FMR41 bit in the reset. Interrupt handling starts after the
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FMR4 register to 0 (erase restart) fixed period and the flash memory
after interrupt handling restarts. Since the block during auto-
completes. erasure or the address during auto-
During auto-erasure Auto-erasure has priority and the programming is forcibly stopped, the
(erase-suspend interrupt request normal value may not be read. Execute
function disabled) acknowledgement is put on auto-erasure again and ensure it
standby. Interrupt handling is completes normally.
executed after auto-erasure Since the watchdog timer does not stop
completes. during the command operation,
During auto- Auto-programming is suspended interrupt requests may be generated.
programming after td(SR-SUS) and interrupt Reset the watchdog timer regularly
(program suspend handling is executed. using the erase-suspend function.
function enabled) Auto-programming can be
restarted by setting the FMR42 bit
in the FMR4 register to 0
(program restart) after interrupt
handling completes.
During auto- Auto-programming has priority
programming and the interrupt request
(program suspend acknowledgement is put on
function disabled) standby. Interrupt handling is
executed after auto-programming
completes.
NOTES:
1. Do not use the address match interrupt while a command is executing because the vector of the
address match interrupt is allocated in ROM.
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19.7.1.4 How to Access

Write 0 before writing 1 when setting the FMR01, FMR02, or FMR11 bit to 1. Do not generate an interrupt
between writing 0 and 1.
19.7.1.5 Rewriting User ROM Area

In EW0 Mode, if the supply voltage drops while rewriting any block in which a rewrite control program is
stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be
rewritten correctly. In this case, use standard serial I/O mode.
19.7.1.6 Program
www.DataSheet4U.com Do not write additions to the already programmed address.
19.7.1.7 Entering Stop Mode or Wait Mode

Do not enter stop mode or wait mode during erase-suspend.
19.7.1.8 Program and Erase Voltage for Flash Memory

To perform programming and erasure, use VCC = 2.7 to 5.5 V as the supply voltage. Do not perform
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R8C/24 Group, R8C/25 Group 20. Electrical Characteristics
20. Electrical Characteristics

The electrical characteristics of N version (Topr = -20 to 85°C) and D version (Topr = -40 to 85°C) are listed
below.
Please contact Renesas Technology sales offices for the electrical characteristics in the Y version (Topr = -20 to
105°C).
Table 20.1 Absolute Maximum Ratings

Symbol Parameter Condition Rated Value Unit
VCC/AVCC Supply voltage -0.3 to 6.5 V
VI Input voltage -0.3 to VCC + 0.3 V
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VO Output voltage -0.3 to VCC + 0.3 V
Pd Power dissipation Topr = 25°C 500(1) mW
Topr Operating ambient temperature -20 to 85 (N version) / °C
-40 to 85 (D version)
Tstg Storage temperature -65 to 150 °C
NOTE:
1. 300 mW for the PTLG0064JA-A package.
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REJ09B0244-0300
Table 20.2 Recommended Operating Conditions

Standard
Symbol Parameter Conditions Unit
Min. Typ. Max.
VCC/AVCC Supply voltage 2.2 − 5.5 V
VSS/AVSS Supply voltage − 0 − V
VIH Input “H” voltage 0.8 VCC − VCC V
VIL Input “L” voltage 0 − 0.2 VCC V
IOH(sum) Peak sum output Sum of all pins IOH(peak) − − -160 mA
“H” current
IOH(sum) Average sum Sum of all pins IOH(avg) − − -80 mA
output “H” current
w w w . D a t a S IhOH(peak)
e e t 4 U Peak
. c o output
m “H” Except P2_0 to P2_7 − − -10 mA
current P2_0 to P2_7 − − -40 mA
IOH(avg) Average output Except P2_0 to P2_7 − − -5 mA
“H” current P2_0 to P2_7 − − -20 mA
IOL(sum) Peak sum output Sum of all pins IOL(peak) − − 160 mA
“L” current
IOL(sum) Average sum Sum of all pins IOL(avg) − − 80 mA
output “L” current
IOL(peak) Peak output “L” Except P2_0 to P2_7 − − 10 mA
current P2_0 to P2_7 − − 40 mA
IOL(avg) Average output Except P2_0 to P2_7 − − 5 mA
“L” current P2_0 to P2_7 − − 20 mA
f(XIN) XIN clock input oscillation frequency 3.0 V ≤ VCC ≤ 5.5 V 0 − 20 MHz
2.7 V ≤ VCC < 3.0 V 0 − 10 MHz
2.2 V ≤ VCC < 2.7 V 0 − 5 MHz
f(XCIN) XCIN clock input oscillation frequency 2.2 V ≤ VCC ≤ 5.5 V 0 − 70 kHz
− System clock OCD2 = 0 3.0 V ≤ VCC ≤ 5.5 V 0 − 20 MHz
XlN clock selected 2.7 V ≤ VCC < 3.0 V 0 − 10 MHz
2.2 V ≤ VCC < 2.7 V 0 − 5 MHz
OCD2 = 1 FRA01 = 0 − 125 − kHz
On-chip oscillator clock Low-speed on-chip
selected oscillator clock selected
FRA01 = 1 − − 20 MHz
High-speed on-chip
oscillator clock selected
3.0 V ≤ VCC ≤ 5.5 V
FRA01 = 1 − − 10 MHz
High-speed on-chip
2.7 V ≤ VCC ≤ 5.5 V
FRA01 = 1 − − 5 MHz
High-speed on-chip
2.2 V ≤ VCC ≤ 5.5 V
NOTES:
1. VCC = 2.2 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. The average output current indicates the average value of current measured during 100 ms.
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Table 20.3 A/D Converter Characteristics

Standard
Min. Typ. Max.
− Resolution Vref = AVCC − − 10 Bit
− Absolute 10-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V − − ±3 LSB
accuracy 8-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V − − ±2 LSB
10-bit mode φAD = 10 MHz, Vref = AVCC = 3.3 V − − ±5 LSB
Rladder Resistor ladder Vref = AVCC 10 − 40 kΩ
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tconv Conversion time 10-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V 3.3 − − µs
8-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V 2.8 − − µs
Vref Reference voltage 2.2 − AVCC V
VIA Analog input voltage(2) 0 − AVCC V
− A/D operating Without sample and hold Vref = AVCC = 2.7 to 5.5 V 0.25 − 10 MHz
clock frequency With sample and hold Vref = AVCC = 2.7 to 5.5 V 1 − 10 MHz
Without sample and hold Vref = AVCC = 2.2 to 5.5 V 0.25 − 5 MHz
With sample and hold Vref = AVCC = 2.2 to 5.5 V 1 − 5 MHz
NOTES:
1. AVCC = 2.2 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in
8-bit mode.
P0
P1
P2 30pF
P3
P4
P6
Figure 20.1 Ports P0 to P4, P6 Timing Measurement Circuit
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REJ09B0244-0300
Table 20.4 Flash Memory (Program ROM) Electrical Characteristics

Standard
Min. Typ. Max.
− Program/erase endurance(2) R8C/24 Group 100(3) − − times
R8C/25 Group 1,000(3) − − times
− Byte program time − 50 400 µs
− Block erase time − 0.4 9 s
td(SR-SUS) Time delay from suspend request until − − 97+CPU clock µs
suspend × 6 cycles
− Interval from erase start/restart until 650 − − µs
following suspend request
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− Interval from program start/restart until 0 − − ns
− Time from suspend until program/erase − − 3+CPU clock µs
restart × 4 cycles
− Program, erase voltage 2.7 − 5.5 V
− Read voltage 2.2 − 5.5 V
− Program, erase temperature 0 − 60 °C
− Data hold time(7) Ambient temperature = 55°C 20 − − year
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance
still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the
number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
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Table 20.5 Flash Memory (Data flash Block A, Block B) Electrical Characteristics(4)
Standard
Min. Typ. Max.
− Program/erase endurance(2) 10,000(3) − − times
− Byte program time − 50 400 µs
(program/erase endurance ≤ 1,000 times)
− Byte program time − 65 − µs
(program/erase endurance > 1,000 times)
− Block erase time − 0.2 9 s
(program/erase endurance ≤ 1,000 times)
− Block erase time − 0.3 − s
www.DataSheet4U.com (program/erase endurance > 1,000 times)
td(SR-SUS) Time delay from suspend request until − − 97+CPU clock µs
suspend × 6 cycles
− Interval from erase start/restart until 650 − − µs
− Interval from program start/restart until 0 − − ns
− Time from suspend until program/erase − − 3+CPU clock µs
restart × 4 cycles
− Program, erase voltage 2.7 − 5.5 V
− Read voltage 2.2 − 5.5 V
− Program, erase temperature -20(8) − 85 °C
− Data hold time(9) Ambient temperature = 55 °C 20 − − year
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance
still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times
is the same as that in program ROM.
5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the
number of erase operations to a certain number.
6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
8. -40°C for D version.
9. The data hold time includes time that the power supply is off or the clock is not supplied.
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Suspend request
(maskable interrupt request)
FMR46
Clock-dependent
Fixed time time
Access restart
td(SR-SUS)
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Figure 20.2 Time delay until Suspend
Table 20.6 Voltage Detection 0 Circuit Electrical Characteristics

Standard
Symbol Parameter Condition Unit
Min. Typ. Max.
Vdet0 Voltage detection level 2.2 2.3 2.4 V
− Voltage detection circuit self power consumption VCA25 = 1, VCC = 5.0 V − 0.9 − µA
td(E-A) Waiting time until voltage detection circuit operation − − 300 µs
starts(2)
Vccmin MCU operating voltage minimum value 2.2 − − V
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version).
2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2
register to 0.

Standard
Min. Typ. Max.
− Voltage monitor 1 interrupt request generation time(2) − 40 − µs
starts(3)
NOTES:
2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.

Standard
Min. Typ. Max.
− Voltage monitor 2 interrupt request generation time(2) − 40 − µs
starts(3)
NOTES:
2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.
3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
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Table 20.9 Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics(3)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
Vpor1 Power-on reset valid voltage(4) − − 0.1 V
Vpor2 Power-on reset or voltage monitor 0 reset valid 0 − Vdet0 V
voltage
trth External power VCC rise gradient(2) 20 − − mV/msec
NOTES:
1. The measurement condition is Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. This condition (external power VCC rise gradient) does not apply if VCC ≥ 1.0 V.
3. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the
www.DataSheet4U.com VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1.
4. tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on
reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if -20°C ≤ Topr ≤ 85°C, maintain tw(por1) for
3,000 s or more if -40°C ≤ Topr < -20°C.
Vdet0(3) Vdet0(3)
2.2 V trth
External trth
Power VCC
Vpor2
Vpor1
tw(por1) Sampling time(1, 2)
Internal
reset signal
(“L” valid)
1 1
× 32 × 32
fOCO-S fOCO-S
NOTES:
1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage
range (2.2 V or above) during the sampling time.
2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details.
3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit for details.
Figure 20.3 Power-on Reset Circuit Electrical Characteristics
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REJ09B0244-0300
Table 20.10 High-speed On-Chip Oscillator Circuit Electrical Characteristics

Standard
Min. Typ. Max.
fOCO40M High-speed on-chip oscillator frequency VCC = 4.75 to 5.25 V 39.2 40 40.8 MHz
temperature • supply voltage dependence 0°C ≤ Topr ≤ 60°C(2)
VCC = 4.5 to 5.5 V 38.8 40 40.8 MHz
-20°C ≤ Topr ≤ 85°C
VCC = 4.5 to 5.5 V 38.4 40 40.8 MHz
-40°C ≤ Topr ≤ 85°C
VCC = 3.0 to 5.5 V 38.8 40 41.2 MHz
-20°C ≤ Topr ≤ 85°C(2)
www.DataSheet4U.com VCC = 3.0 to 5.5 V 38.4 40 41.6 MHz
-40°C ≤ Topr ≤ 85°C(2)
VCC = 2.7 to 5.5 V 38 40 42 MHz
-20°C ≤ Topr ≤ 85°C(2)
VCC = 2.7 to 5.5 V 37.6 40 42.4 MHz
-40°C ≤ Topr ≤ 85°C(2)
VCC = 2.2 to 5.5 V 35.2 40 44.8 MHz
-20°C ≤ Topr ≤ 85°C(3)
VCC = 2.2 to 5.5 V 34 40 46 MHz
-40°C ≤ Topr ≤ 85°C(3)
High-speed on-chip oscillator frequency when VCC = 5.0 V, Topr = 25°C − 36.864 MHz
correction value in FRA7 register is written to VCC = 3.0 to 5.5 V -3% − 3% %
FRA1 register(4) -20°C ≤ Topr ≤ 85°C
− Value in FRA1 register after reset 08h − F7h −
− Oscillation frequency adjustment unit of high- Adjust FRA1 register − +0.3 − MHz
speed on-chip oscillator (value after reset) to -1
− Oscillation stability time − 10 100 µs
− Self power consumption at oscillation VCC = 5.0 V, Topr = 25°C − 400 − µA
NOTES:
1. VCC = 2.2 to 5.5 V, Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. Standard values when the FRA1 register value after reset is assumed.
3. Standard values when the corrected value of the FRA6 register has been written to the FRA1 register.
4. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in
UART mode.
Table 20.11 Low-speed On-Chip Oscillator Circuit Electrical Characteristics

Standard
Min. Typ. Max.
fOCO-S Low-speed on-chip oscillator frequency 30 125 250 kHz
− Oscillation stability time − 10 100 µs
− Self power consumption at oscillation VCC = 5.0 V, Topr = 25°C − 15 − µA
NOTE:
1. VCC = 2.2 to 5.5 V, Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
Table 20.12 Power Supply Circuit Timing Characteristics

Standard
Min. Typ. Max.
td(P-R) Time for internal power supply stabilization during 1 − 2000 µs
power-on(2)
td(R-S) STOP exit time(3) − − 150 µs
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = 25°C.
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode.
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Table 20.13 Timing Requirements of Clock Synchronous Serial I/O with Chip Select(1)
Standard Unit
Symbol Parameter Conditions
Min. Typ. Max.
tSUCYC SSCK clock cycle time 4 − − tCYC(2)
tHI SSCK clock “H” width 0.4 − 0.6 tSUCYC
tLO SSCK clock “L” width 0.4 − 0.6 tSUCYC
tRISE SSCK clock rising Master − − 1 tCYC(2)
time Slave − − 1 µs
tFALL SSCK clock falling Master − − 1 tCYC(2)
time Slave − − 1 µs
tSU
www.DataSheet4U.com SSO, SSI data input setup time 100 − − ns
tH SSO, SSI data input hold time 1 − − tCYC(2)
tLEAD SCS setup time Slave 1tCYC + 50 − − ns
tLAG SCS hold time Slave 1tCYC + 50 − − ns
tOD SSO, SSI data output delay time − − 1 tCYC(2)
tSA SSI slave access time 2.7 V ≤ VCC ≤ 5.5 V − − 1.5tCYC + 100 ns
2.2 V ≤ VCC < 2.7 V − − 1.5tCYC + 200 ns
tOR SSI slave out open time 2.7 V ≤ VCC ≤ 5.5 V − − 1.5tCYC + 100 ns
2.2 V ≤ VCC < 2.7 V − − 1.5tCYC + 200 ns
NOTES:
1. VCC = 2.2 to 5.5 V, VSS = 0 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
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4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIH or VOH
tHI tFALL tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
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SSCK (output)
(CPOS = 0)
tLO tSUCYC
SSO (output)
tOD
SSI (input)
tSU tH
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIH or VOH
tHI tFALL tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO tSUCYC
SSO (output)
tOD
SSI (input)
tSU tH
Figure 20.4 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master)
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REJ09B0244-0300
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIH or VOH
tLEAD tHI tFALL tRISE tLAG
SSCK (input)
(CPOS = 1)
tLO
www.DataSheet4U.com tHI
SSCK (input)
(CPOS = 0)
tLO tSUCYC
SSO (input)
tSU tH
SSI (output)
tSA tOD tOR
4-Wire Bus Communication Mode, Slave, CPHS = 0
SCS (input) VIH or VOH
VIH or VOH
tLEAD tHI tFALL tRISE tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO tSUCYC
SSO (input)
tSU tH
SSI (output)
tSA tOD tOR
Figure 20.5 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave)
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REJ09B0244-0300
tHI
VIH or VOH
SSCK
VIH or VOH
tLO tSUCYC
SSO (output)
www.DataSheet4U.com tOD
SSI (input)
tSU tH
Figure 20.6 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Clock Synchronous
Communication Mode)
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Table 20.14 Timing Requirements of I2C bus Interface(1)

Standard Unit
Symbol Parameter Condition
Min. Typ. Max.
tSCL SCL input cycle time 12tCYC + 600(2) − − ns
tSCLH SCL input “H” width 3tCYC + 300(2) − − ns
tSCLL SCL input “L” width 5tCYC + 500(2) − − ns
tsf SCL, SDA input fall time − − 300 ns
tSP SCL, SDA input spike pulse rejection time − − 1tCYC(2) ns
tBUF SDA input bus-free time 5tCYC(2) − − ns
tSTAH Start condition input hold time 3tCYC(2) − − ns
www.DataSheet4U.com
tSTAS Retransmit start condition input setup time 3tCYC(2) − − ns
tSTOP Stop condition input setup time 3tCYC(2) − − ns
tSDAS Data input setup time 1tCYC + 20(2) − − ns
tSDAH Data input hold time 0 − − ns
NOTES:
1. VCC = 2.2 to 5.5 V, VSS = 0 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
VIH
SDA
VIL
tBUF
tSTAH tSCLH tSP tSTOP
tSTAS
SCL
P(2) S(1) Sr(3) P(2)
tSCLL
tsf tsr tSDAS
tSCL
tSDAH
NOTES:
1. Start condition
2. Stop condition
3. Retransmit start condition
Figure 20.7 I/O Timing of I2C bus Interface
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REJ09B0244-0300
Table 20.15 Electrical Characteristics (1) [VCC = 5 V]

Standard
Min. Typ. Max.
VOH Output “H” voltage Except P2_0 to P2_7, IOH = -5 mA VCC − 2.0 − VCC V
XOUT IOH = -200 µA VCC − 0.5 − VCC V
P2_0 to P2_7 Drive capacity HIGH IOH = -20 mA VCC − 2.0 − VCC V
Drive capacity LOW IOH = -5 mA VCC − 2.0 − VCC V
XOUT Drive capacity HIGH IOH = -1 mA VCC − 2.0 − VCC V
Drive capacity LOW IOH = -500 µA VCC − 2.0 − VCC V
VOL Output “L” voltage Except P2_0 to P2_7, IOL = 5 mA − − 2.0 V
XOUT IOL = 200 µA − − 0.45 V
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P2_0 to P2_7 Drive capacity HIGH IOL = 20 mA − − 2.0 V
Drive capacity LOW IOL = 5 mA − − 2.0 V
XOUT Drive capacity HIGH IOL = 1 mA − − 2.0 V
Drive capacity LOW IOL = 500 µA − − 2.0 V
VT+-VT- Hysteresis INT0, INT1, INT2, 0.1 0.5 − V
INT3, KI0, KI1, KI2,
KI3, TRAIO, RXD0,
RXD1, CLK0, CLK1,
SSI, SCL, SDA, SSO
RESET 0.1 1.0 − V
IIH Input “H” current VI = 5 V, Vcc = 5V − − 5.0 µA
IIL Input “L” current VI = 0 V, Vcc = 5V − − -5.0 µA
RPULLUP Pull-up resistance VI = 0 V, Vcc = 5V 30 50 167 kΩ
RfXIN Feedback XIN − 1.0 − MΩ
resistance
RfXCIN Feedback XCIN − 18 − MΩ
resistance
VRAM RAM hold voltage During stop mode 1.8 − − V
NOTE:
1. VCC = 4.2 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), f(XIN) = 20 MHz, unless otherwise specified.
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Table 20.16 Electrical Characteristics (2) [Vcc = 5 V]

(Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.)
Standard
Min. Typ. Max.
ICC Power supply High-speed XIN = 20 MHz (square wave) − 10 17 mA
current clock mode High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
(VCC = 3.3 to 5.5 V) No division
Single-chip mode,
XIN = 16 MHz (square wave) − 9 15 mA
output pins are
High-speed on-chip oscillator off
open, other pins Low-speed on-chip oscillator on = 125 kHz
are VSS No division
www.DataSheet4U.com XIN = 10 MHz (square wave) − 6 − mA
No division
XIN = 20 MHz (square wave) − 5 − mA
Divide-by-8
Divide-by-8
XIN = 10 MHz (square wave) − 2.5 − mA
Divide-by-8
High-speed XIN clock off − 10 15 mA
on-chip High-speed on-chip oscillator on fOCO = 20 MHz
oscillator mode
No division
XIN clock off − 4 − mA
High-speed on-chip oscillator on fOCO = 20 MHz
Divide-by-8
XIN clock off − 5.5 10 mA
No division
XIN clock off − 2.5 − mA
Divide-by-8
Low-speed XIN clock off − 130 300 µA
on-chip High-speed on-chip oscillator off
oscillator mode
Divide-by-8, FMR47 = 1
clock mode High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
FMR47 = 1
XIN clock off − 30 − µA
Program operation on RAM
Flash memory off, FMSTP = 1
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REJ09B0244-0300

Standard
Min. Typ. Max.
ICC Power supply Wait mode XIN clock off − 25 75 µA
current High-speed on-chip oscillator off
(VCC = 3.3 to 5.5 V) While a WAIT instruction is executed
Single-chip mode, Peripheral clock operation
output pins are VCA27 = VCA26 = VCA25 = 0
open, other pins VCA20 = 1
are VSS XIN clock off − 23 60 µA
www.DataSheet4U.com Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off − 4.0 − µA
XCIN clock oscillator on = 32 kHz (high drive)
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XCIN clock oscillator on = 32 kHz (low drive)
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
Increase during Without sample & hold − 2.6 − mA
A/D converter With sample & hold − 1.6 − mA
operation
Stop mode XIN clock off, Topr = 25°C − 0.8 3.0 µA
CM10 = 1
VCA27 = VCA26 = VCA25 = 0
XIN clock off, Topr = 85°C − 1.2 − µA
CM10 = 1
VCA27 = VCA26 = VCA25 = 0
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Timing Requirements
(Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25°C) [VCC = 5 V]
Table 20.18 XIN Input, XCIN Input

Standard
Symbol Parameter Unit
Min. Max.
tc(XIN) XIN input cycle time 50 − ns
tWH(XIN) XIN input “H” width 25 − ns
tWL(XIN) XIN input “L” width 25 − ns
tc(XCIN) XCIN input cycle time 14 − µs
tWH(XCIN) XCIN input “H” width 7 − µs
tWL(XCIN)
www.DataSheet4U.com XCIN input “L” width 7 − µs
tC(XIN) VCC = 5 V
tWH(XIN)
XIN input
tWL(XIN)
tC(XCIN)
tWH(XCIN)
XCIN input
tWL(XCIN)
Figure 20.8 XIN Input and XCIN Input Timing Diagram when VCC = 5 V
Table 20.19 TRAIO Input

Standard
Min. Max.
tc(TRAIO) TRAIO input cycle time 100 − ns
tWH(TRAIO) TRAIO input “H” width 40 − ns
tWL(TRAIO) TRAIO input “L” width 40 − ns
tC(TRAIO) VCC = 5 V
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 20.9 TRAIO Input Timing Diagram when VCC = 5 V
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Table 20.20 Serial Interface

Standard
Min. Max.
tc(CK) CLKi input cycle time 200 − ns
tW(CKH) CLKi input “H” width 100 − ns
tW(CKL) CLKi input “L” width 100 − ns
td(C-Q) TXDi output delay time − 50 ns
th(C-Q) TXDi hold time 0 − ns
tsu(D-C) RXDi input setup time 50 − ns
th(C-D) RXDi input hold time 90 − ns
i = 0 or 1
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tC(CK) VCC = 5 V
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
td(C-Q) tsu(D-C) th(C-D)
RXDi
i = 0 or 1
Figure 20.10 Serial Interface Timing Diagram when VCC = 5 V
Table 20.21 External Interrupt INTi (i = 0 to 3) Input

Standard
Min. Max.
tW(INH) INT0 input “H” width 250(1) − ns
tW(INL) INT0 input “L” width 250(2) − ns
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
VCC = 5 V
tW(INL)
INTi input
tW(INH)
i = 0 to 3
Figure 20.11 External Interrupt INTi Input Timing Diagram when VCC = 5 V
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Table 20.22 Electrical Characteristics (3) [VCC = 3 V]

Standard
Min. Typ. Max.
VOH Output “H” voltage Except P2_0 to P2_7, IOH = -1 mA VCC - 0.5 − VCC V
XOUT
P2_0 to P2_7 Drive capacity IOH = -5 mA VCC - 0.5 − VCC V
HIGH
Drive capacity IOH = -1 mA VCC - 0.5 − VCC V
LOW
XOUT Drive capacity IOH = -0.1 mA VCC - 0.5 − VCC V
HIGH
www.DataSheet4U.com Drive capacity IOH = -50 µA VCC - 0.5 − VCC V
LOW
XOUT
P2_0 to P2_7 Drive capacity IOL = 5 mA − − 0.5 V
HIGH
Drive capacity IOL = 1 mA − − 0.5 V
LOW
XOUT Drive capacity IOL = 0.1 mA − − 0.5 V
HIGH
Drive capacity IOL = 50 µA − − 0.5 V
LOW
KI3, TRAIO, RXD0,
RXD1, CLK0, CLK1,
SSI, SCL, SDA, SSO
RESET 0.1 0.4 − V
IIH Input “H” current VI = 3 V, Vcc = 3V − − 4.0 µA
IIL Input “L” current VI = 0 V, Vcc = 3V − − -4.0 µA
RPULLUP Pull-up resistance VI = 0 V, Vcc = 3V 66 160 500 kΩ
RfXIN Feedback resistance XIN − 3.0 − MΩ
RfXCIN Feedback resistance XCIN − 18 − MΩ
NOTE:
1. VCC =2.7 to 3.3 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), f(XIN) = 10 MHz, unless otherwise specified.
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Standard
Min. Typ. Max.
ICC Power supply current High-speed XIN = 10 MHz (square wave) − 6 − mA
(VCC = 2.7 to 3.3 V) clock mode High-speed on-chip oscillator off
Single-chip mode, Low-speed on-chip oscillator on = 125 kHz
No division
output pins are open,
other pins are VSS High-speed on-chip oscillator off
Divide-by-8
High-speed on- XIN clock off − 5 9 mA
chip oscillator High-speed on-chip oscillator on fOCO = 10 MHz
mode
No division
XIN clock off − 2 − mA
Divide-by-8
Low-speed on- XIN clock off − 130 300 µA
chip oscillator High-speed on-chip oscillator off
mode
clock mode High-speed on-chip oscillator off
FMR47 = 1
Wait mode XIN clock off − 25 70 µA
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off − 23 55 µA
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
operation
CM10 = 1
VCA27 = VCA26 = VCA25 = 0
CM10 = 1
VCA27 = VCA26 = VCA25 = 0
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Timing requirements
(Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25°C) [VCC = 3 V]

Standard
Min. Max.
tWL(XCIN)
tC(XIN) VCC = 3 V
tWH(XIN)
XIN input
tWL(XIN)
tC(XCIN)
tWH(XCIN)
XCIN input
tWL(XCIN)
Figure 20.12 XIN Input and XCIN Input Timing Diagram when VCC = 3 V

Standard
Min. Max.
tC(TRAIO) VCC = 3 V
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 20.13 TRAIO Input Timing Diagram when VCC = 3 V
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REJ09B0244-0300

Standard
Min. Max.
tW(CKL) CLKi Input “L” width 150 − ns
i = 0 or 1
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tC(CK) VCC = 3 V
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
RXDi
i = 0 or 1
Figure 20.14 Serial Interface Timing Diagram when VCC = 3 V

Standard
Min. Max.
tW(INH) INT0 input “H” width 380(1) − ns
NOTES:
VCC = 3 V
tW(INL)
INTi input
tW(INH)
i = 0 to 3
Figure 20.15 External Interrupt INTi Input Timing Diagram when VCC = 3 V
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Table 20.28 Electrical Characteristics (5) [VCC = 2.2 V]

Standard
Min. Typ. Max.
VOH Output “H” voltage Except P2_0 to P2_7, IOH = -1 mA VCC - 0.5 − VCC V
XOUT
P2_0 to P2_7 Drive capacity IOH = -2 mA VCC - 0.5 − VCC V
HIGH
Drive capacity IOH = -1 mA VCC - 0.5 − VCC V
LOW
XOUT Drive capacity IOH = -0.1 mA VCC - 0.5 − VCC V
HIGH
www.DataSheet4U.com Drive capacity IOH = -50 µA VCC - 0.5 − VCC V
LOW
XOUT
P2_0 to P2_7 Drive capacity IOL = 2 mA − − 0.5 V
HIGH
Drive capacity IOL = 1 mA − − 0.5 V
LOW
XOUT Drive capacity IOL = 0.1 mA − − 0.5 V
HIGH
Drive capacity IOL = 50 µA − − 0.5 V
LOW
KI3, TRAIO, RXD0,
RXD1, CLK0, CLK1,
SSI, SCL, SDA, SSO
RESET 0.05 0.15 − V
IIH Input “H” current VI = 2.2 V − − 4.0 µA
IIL Input “L” current VI = 0 V − − -4.0 µA
RPULLUP Pull-up resistance VI = 0 V 100 200 600 kΩ
RfXIN Feedback resistance XIN − 5 − MΩ
RfXCIN Feedback resistance XCIN − 35 − MΩ
NOTE:
1. VCC = 2.2 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), f(XIN) = 5 MHz, unless otherwise specified.
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Table 20.29 Electrical Characteristics (6) [Vcc = 2.2 V]

Standard
Min. Typ. Max.
ICC Power supply current High-speed clock XIN = 5 MHz (square wave) − 3.5 − mA
(VCC = 2.2 to 2.7 V) mode High-speed on-chip oscillator off
Single-chip mode, Low-speed on-chip oscillator on = 125 kHz
No division
output pins are open,
XIN = 5 MHz (square wave) − 1.5 − mA
other pins are VSS High-speed on-chip oscillator off
Divide-by-8
High-speed on- XIN clock off − 3.5 − mA
chip oscillator High-speed on-chip oscillator on fOCO = 5 MHz
mode
No division
XIN clock off − 1.5 − mA
Divide-by-8
Low-speed on- XIN clock off − 100 230 µA
chip oscillator High-speed on-chip oscillator off
mode
Low-speed clock XIN clock off − 100 230 µA
mode High-speed on-chip oscillator off
FMR47 = 1
Wait mode XIN clock off − 22 60 µA
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off − 20 55 µA
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
operation
CM10 = 1
VCA27 = VCA26 = VCA25 = 0
CM10 = 1
VCA27 = VCA26 = VCA25 = 0
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REJ09B0244-0300
Timing requirements
(Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V at Topr = 25°C) [VCC = 2.2 V]

Standard
Min. Max.
tWL(XCIN)
tC(XIN) VCC = 2.2 V

tWH(XIN)
XIN input
tWL(XIN)
tC(XCIN)
tWH(XCIN)
XCIN input
tWL(XCIN)
Figure 20.16 XIN Input and XCIN Input Timing Diagram when VCC = 2.2 V

Standard
Min. Max.
tC(TRAIO) VCC = 2.2 V

tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 20.17 TRAIO Input Timing Diagram when VCC = 2.2 V
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REJ09B0244-0300

Standard
Min. Max.
tW(CKL) CLKi input “L” width 400 − ns
i = 0 or 1
www.DataSheet4U.com
tC(CK) VCC = 2.2 V

tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
RXDi
i = 0 or 1
Figure 20.18 Serial Interface Timing Diagram when VCC = 2.2 V

Standard
Min. Max.
tW(INH) INT0 input “H” width 1000 (1) − ns
NOTES:
VCC = 2.2 V
tW(INL)
INTi input
tW(INH)
i = 0 to 3
Figure 20.19 External Interrupt INTi Input Timing Diagram when VCC = 2.2 V
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R8C/24 Group, R8C/25 Group 21. Usage Notes
21. Usage Notes
21.1 Notes on Clock Generation Circuit
21.1.1 Stop Mode

When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the
CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instruction
which sets the CM10 bit to 1 (stop mode) and the program stops.
Insert at least 4 NOP instructions following the JMP.B instruction after the instruction which sets the CM10 bit
to 1.
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• Program example to enter stop mode
BSET 0,PRCR ; Protect disabled
BSET 0,CM1 ; Stop mode
JMP.B LABEL_001
LABEL_001 :
NOP
NOP
NOP
NOP
21.1.2 Wait Mode

When entering wait mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and
execute the WAIT instruction. An instruction queue pre-reads 4 bytes from the WAIT instruction and the
program stops. Insert at least 4 NOP instructions after the WAIT instruction.
• Program example to execute the WAIT instruction

WAIT ; Wait mode
NOP
NOP
NOP
NOP
21.1.3 Oscillation Stop Detection Function

Since the oscillation stop detection function cannot be used if the XIN clock frequency is 2 MHz or below, set
bits OCD1 to OCD0 to 00b.
21.1.4 Oscillation Circuit Constants

Ask the manufacturer of the oscillator to specify the best oscillation circuit constants for your system.
To use this MCU with supply voltage below VCC = 2.7 V, it is recommended to set the CM11 bit in the CM1
register to 1 (on-chip feedback resistor disabled), the CM15 bit to 1 (high drive capacity), and connect the
feedback resistor to the chip externally.
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21.2 Notes on Interrupts
21.2.1 Reading Address 00000h

Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads
interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At
this time, the acknowledged interrupt IR bit is set to 0.
If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the
enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be
generated.
21.2.2 SP Setting
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Set any value in the SP before an interrupt is acknowledged. The SP is set to 0000h after reset. Therefore, if an
interrupt is acknowledged before setting a value in the SP, the program may run out of control.
21.2.3 External Interrupt and Key Input Interrupt

Either “L” level or an “H” level of width shown in the Electrical Characteristics is necessary for the signal input
to pins INT0 to INT3 and pins KI0 to KI3, regardless of the CPU clock.
For details, refer to Table 20.21 (VCC = 5V), Table 20.27 (VCC = 3V), Table 20.33 (VCC = 2.2V) External
Interrupt INTi (i = 0 to 3) Input.
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21.2.4 Changing Interrupt Sources

The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source
changes. When using an interrupt, set the IR bit to 0 (no interrupt requested) after changing the interrupt source.
In addition, changes of interrupt sources include all factors that change the interrupt sources assigned to
individual software interrupt numbers, polarities, and timing. Therefore, if a mode change of a peripheral
function involves interrupt sources, edge polarities, and timing, set the IR bit to 0 (no interrupt requested) after
the change. Refer to the individual peripheral function for its related interrupts.
Figure 21.1 shows an Example of Procedure for Changing Interrupt Sources.
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Interrupt source change
Disable interrupts(2, 3)
Change interrupt source (including mode

of peripheral function)
Set the IR bit to 0 (interrupt not requested)

using the MOV instruction(3)
Enable interrupts (2, 3)
Change completed
IR bit: The interrupt control register bit of an

interrupt whose source is changed.
NOTES:
1. Execute the above settings individually. Do not execute two
or more settings at once (by one instruction).
2. To prevent interrupt requests from being generated, disable
the peripheral function before changing the interrupt
source. In this case, use the I flag if all maskable interrupts
can be disabled. If all maskable interrupts cannot be
disabled, use bits ILVL0 to ILVL2 of the interrupt whose
source is changed.
3. Refer to 12.6.5 Changing Interrupt Control Register
Contents for the instructions to be used and usage notes.
Figure 21.1 Example of Procedure for Changing Interrupt Sources
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21.2.5 Changing Interrupt Control Register Contents

(a) The contents of an interrupt control register can only be changed while no interrupt requests
corresponding to that register are generated. If interrupt requests may be generated, disable interrupts
before changing the interrupt control register contents.
(b) When changing the contents of an interrupt control register after disabling interrupts, be careful to
choose appropriate instructions.
Changing any bit other than IR bit
If an interrupt request corresponding to a register is generated while executing the instruction, the IR bit
may not be set to 1 (interrupt requested), and the interrupt request may be ignored. If this causes a
problem, use the following instructions to change the register: AND, OR, BCLR, BSET
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Changing IR bit
If the IR bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction used.
Therefore, use the MOV instruction to set the IR bit to 0.
(c) When disabling interrupts using the I flag, set the I flag as shown in the sample programs below. Refer
to (b) regarding changing the contents of interrupt control registers by the sample programs.
Sample programs 1 to 3 are for preventing the I flag from being set to 1 (interrupts enabled) before the interrupt
control register is changed for reasons of the internal bus or the instruction queue buffer.
Example 1: Use NOP instructions to prevent I flag from being set to 1 before interrupt control register
is changed
INT_SWITCH1:
NOP ;
NOP
Example 2: Use dummy read to delay FSET instruction

INT_SWITCH2:
MOV.W MEM,R0 ; Dummy read
Example 3: Use POPC instruction to change I flag

INT_SWITCH3:
PUSHC FLG
POPC FLG ; Enable interrupts
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21.3 Notes on Timers
21.3.1 Notes on Timer RA

• Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the
count starts.
• Even if the prescaler and timer RA are read out in 16-bit units, these registers are read 1 byte at a time by
the MCU. Consequently, the timer value may be updated during the period when these two registers are
being read.
• In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by
writing 0 to these bits by a program. However, these bits remain unchanged if 1 is written. When using the
READ-MODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0
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although these bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or
TUNDF bit which is not supposed to be set to 0 with the MOV instruction.
• When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and
TUNDF are undefined. Write 0 to bits TEDGF and TUNDF before the count starts.
• The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts.
• When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler
immediately after the count starts, then set the TEDGF bit to 0.
• The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1
(count starts) while the count is stopped.
During this time, do not access registers associated with timer RA(1) other than the TCSTF bit. Timer RA
starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (during count).
The TCSTF bit remains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0.
During this time, do not access registers associated with timer RA(1) other than the TCSTF bit.
NOTE:
1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA.
• When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow
three or more cycles of the count source clock for each write interval.
• When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three
or more cycles of the prescaler underflow for each write interval.
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21.3.2 Notes on Timer RB

• Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the
count starts.
• Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time by the
MCU. Consequently, the timer value may be updated during the period when these two registers are being
read.
• In programmable one-shot generation mode and programmable wait one-shot generation mode, when
setting the TSTART bit in the TRBCR register to 0 (count stops) or setting the TOSSP bit in the TRBOCR
register to 1 (one-shot stops), the timer reloads the value of reload register and stops. Therefore, in
programmable one-shot generation mode and programmable wait one-shot generation mode, read the timer
count value before the timer stops.
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• The TCSTF bit remains 0 (count stops) for 1 to 2 cycles of the count source after setting the TSTART bit to
1 (count starts) while the count is stopped.
The TCSTF bit remains 1 for 1 to 2 cycles of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RB counting is stopped when the TCSTF bit is set to 0.
NOTE:
1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and
TRBPR.
• If the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately.
• If 1 is written to the TOSST or TOSSP bit in the TRBOCR register, the value of the TOSSTF bit changes
after one or two cycles of the count source have elapsed. If the TOSSP bit is written to 1 during the period
between when the TOSST bit is written to 1 and when the TOSSTF bit is set to 1, the TOSSTF bit may be
set to either 0 or 1 depending on the content state. Likewise, if the TOSST bit is written to 1 during the
period between when the TOSSP bit is written to 1 and when the TOSSTF bit is set to 0, the TOSSTF bit
may be set to either 0 or 1.
21.3.2.1 Timer mode

The following workaround should be performed in timer mode.
To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following
points:
write interval.
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21.3.2.2 Programmable waveform generation mode

The following three workarounds should be performed in programmable waveform generation mode.
following points:
write interval.
(2) To change registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), synchronize
the TRBO output cycle using a timer RB interrupt, etc. This operation should be preformed only once in
www.DataSheet4U.com the same output cycle. Also, make sure that writing to the TRBPR register does not occur during period
A shown in Figures 21.2 and 21.3.
The following shows the detailed workaround examples.

• Workaround example (a):
As shown in Figure 21.2, write to registers TRBSC and TRBPR in the timer RB interrupt routine. These
write operations must be completed by the beginning of period A.
Period A
Count source/
prescaler
underflow signal
IR bit in (a) Interrupt request is Ensure sufficient time

TRBIC register acknowledged
(b)
Interrupt Instruction in Set the secondary and then

Interrupt request sequence interrupt routine
is generated the primary register immediately
(a) Period between interrupt request generation and the completion of execution of an instruction. The length of time
varies depending on the instruction being executed.
The DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as
the divisor).
(b) 20 cycles. 21 cycles for address match and single-step interrupts.
Figure 21.2 Workaround Example (a) When Timer RB interrupt is Used
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• Workaround example (b):

As shown in Figure 21.3 detect the start of the primary period by the TRBO pin output level and write to
registers TRBSC and TRBPR. These write operations must be completed by the beginning of period A.
If the port register’s bit value is read after the port direction register’s bit corresponding to the TRBO pin is
set to 0 (input mode), the read value indicates the TRBO pin output value.
Period A
Count source/
prescaler
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Read value of the port register’s

bit corresponding to the TRBO pin
(when the bit in the port direction
register is set to 0)
(i) (ii) (iii)
Ensure sufficient time
The TRBO output inversion Upon detecting (i), set the secondary and
is detected at the end of the then the primary register immediately.
secondary period.
Figure 21.3 Workaround Example (b) When TRBO Pin Output Value is Read
(3) To stop the timer counting in the primary period, use the TSTOP bit in the TRBCR register. In this case,
registers TRBPRE and TRBPR are initialized and their values are set to the values after reset.
21.3.2.3 Programmable one-shot generation mode

The following two workarounds should be performed in programmable one-shot generation mode.
following points:
• When the TRBPRE register is written continuously during count operation (TCSTF bit is set to 1), allow
three or more cycles of the count source for each write interval.
• When the TRBPR register is written continuously during count operation (TCSTF bit is set to 1), allow
three or more cycles of the prescaler underflow for each write interval.
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21.3.2.4 Programmable wait one-shot generation mode

The following three workarounds should be performed in programmable wait one-shot generation mode.
following points:
write interval.
www.DataSheet4U.com (3) Set registers TRBSC and TRBPR using the following procedure.
(a) To use “INT0 pin one-shot trigger enabled” as the count start condition
Set the TRBSC register and then the TRBPR register. At this time, after writing to the TRBPR
register, allow an interval of 0.5 or more cycles of the count source before trigger input from the
INT0 pin.
(b) To use “writing 1 to TOSST bit” as the start condition
Set the TRBSC register, the TRBPR register, and then TOSST bit. At this time, after writing to the
TRBPR register, allow an interval of 0.5 or more cycles of the count source before writing to the
TOSST bit.
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21.3.3 Notes on Timer RD
21.3.3.1 TRDSTR Register

• Set the TRDSTR register using the MOV instruction.
• When the CSELi (i = 0 to 1) is set to 0 (the count stops at compare match of registers TRDi and
TRDGRAi), the count does not stop and the TSTARTi bit remains unchanged even if 0 (count stops) is
written to the TSTARTi bit.
• Therefore, set the TSTARTi bit to 0 to change other bits without changing the TSTARTi bit when the
CSELi bit is se to 0.
www.DataSheet4U.com • To stop counting by a program, set the TSTARTi bit after setting the CSELi bit to 1. Although the CSELi
bit is set to 1 and the TSTARTi bit is set to 0 at the same time (with 1 instruction), the count cannot be
stopped.
• Table 21.1 lists the TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops to use the TRDIOji (j
= A, B, C, or D) pin with the timer RD output.
Table 21.1 TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops

Count Stop TRDIOji Pin Output when Count Stops
When the CSELi bit is set to 1, set the TSTARTi bit to 0 and the count Hold the output level immediately before the
stops. count stops.
When the CSELi bit is set to 0, the count stops at compare match of Hold the output level after output changes by
registers TRDi and TRDGRAi. compare match.
21.3.3.2 TRDi Register (i = 0 or 1)

• When writing the value to the TRDi register by a program while the TSTARTi bit in the TRDSTR register
is set to 1 (count starts), avoid overlapping with the timing for setting the TRDi register to 0000h, and then
write. If the timing for setting the TRDi register to 0000h overlaps with the timing for writing the value to
the TRDi register, the value is not written and the TRDi register is set to 0000h.
These precautions are applicable when selecting the following by bits CCLR2 to CCLR0 in the
TRDCRi register.
- 001b (Clear by the TRDi register at compare match with the TRDGRAi register.)
- 010b (Clear by the TRDi register at compare match with the TRDGRBi register.)
- 011b (Synchronous clear)
- 101b (Clear by the TRDi register at compare match with the TRDGRCi register.)
- 110b (Clear by the TRDi register at compare match with the TRDGRDi register.)
• When writing the value to the TRDi register and continuously reading the same register, the value before
Program example MOV.W #XXXXh, TRD0 ;Writing
JMP.B L1 ;JMP.B
L1: MOV.W TRD0,DATA ;Reading
21.3.3.3 TRDSRi Register (i = 0 or 1)

When writing the value to the TRDSRi register and continuously reading the same register, the value before
Program example MOV.B #XXh, TRDSR0 ;Writing
JMP.B L1 ;JMP.B
L1: MOV.B TRDSR0,DATA ;Reading
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REJ09B0244-0300
21.3.3.4 Count Source Switch

• Switch the count source after the count stops.
Change procedure
• When changing the count source from fOCO40M to another source and stopping fOCO40M, wait 2 cycles
of f1 or more after setting the clock switch, and then stop fOCO40M.
Change procedure
www.DataSheet4U.com (3) Wait 2 or more cycles of f1.
(4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator stops).
21.3.3.5 Input Capture Function

• Set the pulse width of the input capture signal to 3 or more cycles of the timer RD operation clock (refer to
Table 14.11 Timer RD Operation Clocks).
• The value in the TRDi register is transferred to the TRDGRji register 2 to 3 cycles of the timer RD
operation clock after the input capture signal is applied to the TRDIOji pin (i = 0 or 1, j = either A, B, C, or
D) (no digital filter).
21.3.3.6 Reset Synchronous PWM Mode

• When reset synchronous PWM mode is used for motor control, make sure OLS0 = OLS1.
• Set to reset synchronous PWM mode by the following procedure:
Change procedure
(1) Set the TSTART0 bit in the TRDSTR register to 0 (count stops).
(3) Set bits CMD1 to CMD0 to 01b (reset synchronous PWM mode).
(4) Set the other registers associated with timer RD again.
21.3.3.7 Complementary PWM Mode

• When complementary PWM mode is used for motor control, make sure OLS0 = OLS1.
• Change bits CMD1 to CMD0 in the TRDFCR register in the following procedure.
Change procedure: When setting to complementary PWM mode (including re-set), or changing the transfer
timing from the buffer register to the general register in complementary PWM mode.
(3) Set bits CMD1 to CMD0 to 10b or 11b (complementary PWM mode).
(4) Set the registers associated with other timer RD again.
Change procedure: When stopping complementary PWM mode

(2) Set bits CMD1 to CMD to 00b (timer mode, PWM mode, and PWM3 mode).
• Do not write to TRDGRA0, TRDGRB0, TRDGRA1, or TRDGRB1 register during operation.

When changing the PWM waveform, transfer the values written to registers TRDGRD0, TRDGRC1, and
TRDGRD1 to registers TRDGRB0, TRDGRA1, and TRDGRB1 using the buffer operation.
However, to write data to the TRDGRD0, TRDGRC1, or TRDGRD1 register, set bits BFD0, BFC1, and
BFD1 to 0 (general register). After this, bits BFD0, BFC1, and BFD1 may be set to 1 (buffer register).
The PWM period cannot be changed.
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REJ09B0244-0300
• If the value in the TRDGRA0 register is assumed to be m, the TRD0 register counts m-1, m, m+1, m, m-1,
in that order, when changing from increment to decrement operation.
When changing from m to m+1, the IMFA bit is set to 1. Also, bits CMD1 to CMD0 in the TRDFCR
register are set to 11b (complementary PWM mode, buffer data transferred at compare match between
registers TRD0 and TRDGRA0), the content in the buffer registers (TRDGRD0, TRDGRC1, and
TRDGRD1) is transferred to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1).
During m+1, m, and m-1 operation, the IMFA bit remains unchanged and data are not transferred to
registers such as the TRDGRA0 register.
Count value in TRD0

www.DataSheet4U.com register
m+1
Setting value in
TRDGRA0
register m
1 No change
IMFA bit in
TRDSR0 register 0
Transferred from
Not transferred from buffer register
buffer register
TRDGRB0 register
TRDFCR register are set to 11b
TRDGRA1 register
(transfer from the buffer register to the
TRDGRB1 register
general register at compare match of
between registers TRD0 and
TRDGRA0).
Figure 21.4 Operation at Compare Match between Registers TRD0 and TRDGRA0 in
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REJ09B0244-0300
• The TRD1 register counts 1, 0, FFFFh, 0, 1, in that order, when changing from decrement to increment
operation.
The UDF bit is set to 1 when changing between 1, 0, and FFFFh operation. Also, when bits CMD1 to
CMD0 in the TRDFCR register are set to 10b (complementary PWM mode, buffer data transferred at
underflow in the TRD1 register), the content in the buffer registers (TRDGRD0, TRDGRC1, and
TRDGRD1) is transferred to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1). During
FFFFh, 0, 1 operation, data are not transferred to registers such as the TRDGRB0 register. Also, at this
time, the OVF bit remains unchanged.
www.DataSheet4U.com Count value in TRD0

register
FFFFh
UDF bit in 1
TRDSR0 register 0
1 No change
OVF bit in
TRDSR0 register 0
Transferred from Not transferred from buffer register

buffer register
TRDGRB0 register TRDFCR register are set to 10b
TRDGRA1 register (transfer from the buffer register to the
TRDGRB1 register general register when the TRD1 register
underflows).
Figure 21.5 Operation when TRD1 Register Underflows in Complementary PWM Mode
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REJ09B0244-0300
• Select with bits CMD1 to CMD0 the timing of data transfer from the buffer register to the general register.
However, transfer takes place with the following timing in spite of the value of bits CMD1 to CMD0 in the
following cases:
Value in buffer register ≥ value in TRDGRA0 register:

Transfer take place at underflow of the TRD1 register.
TRDGRA0 register, and the TRD1 register underflows for the first time after setting, the value is
transferred to the general register. After that, the value is transferred with the timing selected by bits CMD1
to CMD0.
www.DataSheet4U.com
n3
m+1
Count value in TRD0
n2 register
n1
Count value in TRD1
0000h register
TRDGRD0 register n2 n3 n2 n1
TRDGRB0 register n1 n2 n3 n2 n1
Transfer with timing set by Transfer at Transfer at Transfer with timing set by
bits CMD1 to CMD0 underflow of TRD1 underflow of TRD1 bits CMD1 to CMD0
register because of register because
n3 > m of first setting to
n2 < m
TRDIOB0 output
TRDIOD0 output

• Bits CMD1 to CMD0 in the TRDFCR register are set to 11b (data in the buffer register is transferred at compare match
between registers TRD0 and TRDGRA0 in complementary PWM mode).
• Both the OSL0 and OLS1 bits in the TRDFCR register are set to 1 (active ‘H” for normal-phase and counter-phase).
Figure 21.6 Operation when Value in Buffer Register ≥ Value in TRDGRA0 Register in
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REJ09B0244-0300
When the value in the buffer register is set to 0000h:

Transfer takes place at compare match between registers TRD0 and TRDGRA0.
TRDGRA0 register, and a compare match occurs between registers TRD0 and TRDGRA0 for the first time
after setting, the value is transferred to the general register. After that, the value is transferred with the
timing selected by bits CMD1 to CMD0.
m+1
n2 Count value in TRD0 register
n1
www.DataSheet4U.com
Count value in TRD1 register
0000h
TRDGRD0 register n1 0000h n1
TRDGRB0 register n2 n1 0000h n1
Transfer at compare Transfer at compare

Transfer with timing Transfer with timing
match between match between
set by bits CMD1 to set by bits CMD1 to
registers TRD0 and registers TRD0 and
CMD0 TRDGRA0 because TRDGRA0 because CMD0
content in of first setting to
TRDGRD0 register 0001h ≤ n1 < m
is set to 0000h
TRDIOB0 output
TRDIOD0 output

• Bits CMD1 to CMD0 in the TRDFCR register are set to 10b (data in the buffer register is transferred at underflow of the TRD1 register in
PWM mode).
• Both the OLS0 and OLS1 bits in the TRDFCR register are set to 1 (active “H” for normal-phase and counter-phase).
Figure 21.7 Operation when Value in Buffer Register Is Set to 0000h in Complementary PWM
Mode
21.3.3.8 Count Source fOCO40M

• The count source fOCO40M can be used with supply voltage VCC = 3.0 to 5.5 V. For supply voltage other
than that, do not set bits TCK2 to TCK0 in registers TRDCR0 and TRDCR to 110b (select fOCO40M as
the count source).
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REJ09B0244-0300
21.3.4 Notes on Timer RE
21.3.4.1 Starting and Stopping Count

Timer RE has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which indicates
count start or stop. Bits TSTART and TCSTF are in the TRECR1 register.
Timer RE starts counting and the TCSTF bit is set to 1 (count starts) when the TSTART bit is set to 1 (count
starts). It takes up to 2 cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to
1. During this time, do not access registers associated with timer RE(1) other than the TCSTF bit.
Also, timer RE stops counting when setting the TSTART bit to 0 (count stops) and the TCSTF bit is set to 0
(count stops). It takes the time for up to 2 cycles of the count source until the TCSTF bit is set to 0 after setting
the TSTART bit to 0. During this time, do not access registers associated with timer RE other than the TCSTF
www.DataSheet4U.com bit.
NOTE:
1. Registers associated with timer RE: TRESEC, TREMIN, TREHR, TREWK, TRECR1, TRECR2, and
TRECSR.
21.3.4.2 Register Setting

Write to the following registers or bits when timer RE is stopped.
• Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2
• Bits H12_H24, PM, and INT in TRECR1 register
• Bits RCS0 to RCS3 in TRECSR register
Timer RE is stopped when bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped).
Also, set all above-mentioned registers and bits (immediately before timer RE count starts) before setting the
TRECR2 register.
Figure 21.8 shows a Setting Example in Real-Time Clock Mode.
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REJ09B0244-0300
Stop timer RE operation

www.DataSheet4U.com
TREIC←00h
(disable timer RE interrupt)
Timer RE register
and control circuit reset
Setting of registers TRECSR, Select clock output

TRESEC, TREMIN, TREHR, Select clock source
TREWK, and bits H12_H24, PM, Seconds, minutes, hours, days of week, operating mode
and INT in TRECR1 register Set a.m./p.m., interrupt timing
Setting of TRECR2 Select interrupt source
Setting of TREIC (IR bit ←0,

select interrupt priority level)
Start timer RE operation
Figure 21.8 Setting Example in Real-Time Clock Mode
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REJ09B0244-0300
21.3.4.3 Time Reading Procedure of Real-Time Clock Mode

In real-time clock mode, read registers TRESEC, TREMIN, TREHR, and TREWK when time data is updated
and read the PM bit in the TRECR1 register when the BSY bit is set to 0 (not while data is updated).
Also, when reading several registers, an incorrect time will be read if data is updated before another register is
read after reading any register.
In order to prevent this, use the reading procedure shown below.
• Using an interrupt
Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the
TRECR1 register in the timer RE interrupt routine.
www.DataSheet4U.com
Monitor the IR bit in the TREIC register with a program and read necessary contents of registers TRESEC,
TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the IR bit in the TREIC
register is set to 1 (timer RE interrupt request generated).

(1) Monitor the BSY bit.
(2) Monitor until the BSY bit is set to 0 after the BSY bit is set to 1 (approximately 62.5 ms while the BSY
bit is set to 1).
TRECR1 register after the BSY bit is set to 0.
• Using read results if they are the same value twice

TRECR1 register.
(2) Read the same register as (1) and compare the contents.
(3) Recognize as the correct value if the contents match. If the contents do not match, repeat until the read
contents match with the previous contents.
Also, when reading several registers, read them as continuously as possible.
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21.4 Notes on Serial Interface

• When reading data from the UiRB (i = 0 or 1) register either in the clock synchronous serial I/O mode or in the
clock asynchronous serial I/O mode. Ensure the data is read in 16-bit units. When the high-order byte of the
UiRB register is read, bits PER and FER in the UiRB register and the RI bit in the UiC1 register are set to 0.
To check receive errors, read the UiRB register and then use the read data.
Example (when reading receive buffer register):

MOV.W 00A6H,R0 ; Read the U0RB register
• When writing data to the UiTB register in the clock asynchronous serial I/O mode with 9-bit transfer data
length, write data to the high-order byte first then the low-order byte, in 8-bit units.
www.DataSheet4U.com
Example (when reading transmit buffer register):
MOV.B #XXH,00A3H ; Write the high-order byte of U0TB register
MOV.B #XXH,00A2H ; Write the low-order byte of U0TB register
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21.5 Notes on Clock Synchronous Serial Interface
21.5.1 Notes on Clock Synchronous Serial I/O with Chip Select

Set the IICSEL bit in the PMR register to 0 (select clock synchronous serial I/O with chip select function) to use
the clock synchronous serial I/O with chip select function.
21.5.2 Notes on I2C bus Interface

Set the IICSEL bit in the PMR register to 1 (select I2C bus interface function) to use the I2C bus interface.
21.5.2.1
www.DataSheet4U.com Multimaster Operation
The following actions must be performed to use the I2C bus interface in multimaster operation.
• Transfer rate
Set the transfer rate by 1/1.8 or faster than the fastest rate of the other masters. For example, if the fastest
transfer rate of the other masters is set to 400 kbps, the I2C-bus transfer rate in this MCU should be set to
223 kbps (= 400/1.18) or more.
• Bits MST and TRS in the ICCR1 register setting

(a) Use the MOV instruction to set bits MST and TRS.
(b) When arbitration is lost, confirm the contents of bits MST and TRS. If the contents are other than the
MST bit set to 0 and the TRS bit set to 0 (slave receive mode), set the MST bit to 0 and the TRS bit to 0
again.
21.5.2.2 Master Receive Mode

Either of the following actions must be performed to use the I2C bus interface in master receive mode.
(a) In master receive mode while the RDRF bit in the ICSR register is set to 1, read the ICDRR register
before the rising edge of the 8th clock.
(b) In master receive mode, set the RCVD bit in the ICCR1 register to 1 (disables the next receive
operation) to perform 1-byte communications.
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21.6 Notes on Hardware LIN

For the time-out processing of the header and response fields, use another timer to measure the duration of time
with a Synch Break detection interrupt as the starting point.
www.DataSheet4U.com
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21.7 Notes on A/D Converter

• Write to each bit (other than bit 6) in the ADCON0 register, each bit in the ADCON1 register, or the SMP bit
in the ADCON2 register when A/D conversion is stopped (before a trigger occurs).
• When the VCUT bit in the ADCON1 register is changed from 0 (VREF not connected) to 1 (VREF
connected), wait for at least 1 µs before starting the A/D conversion.
• After changing the A/D operating mode, select an analog input pin again.
• When using the one-shot mode, ensure that A/D conversion is completed before reading the AD register. The
IR bit in the ADIC register or the ADST bit in the ADCON0 register can be used to determine whether A/D
conversion is completed.
• When using the repeat mode, select the frequency of the A/D converter operating clock φAD or more for the
CPU clock during A/D conversion.
www.DataSheet4U.com
Do not select the fOCO-F for the φAD.
• If the ADST bit in the ADCON0 register is set to 0 (A/D conversion stops) by a program and A/D conversion
is forcibly terminated during an A/D conversion operation, the conversion result of the A/D converter will be
undefined. If the ADST bit is set to 0 by a program, do not use the value of the AD register.
• Connect 0.1 µF capacitor between the P4_2/VREF pin and AVSS pin.
• Do not enter stop mode during A/D conversion.
• Do not enter wait mode when the CM02 bit in the CM0 register is set to 1 (peripheral function clock stops in
wait mode) during A/D conversion.
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21.8 Notes on Flash Memory
21.8.1 CPU Rewrite Mode
21.8.1.1 Operating Speed

Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit
in the CM0 register and bits CM16 to CM17 in the CM1 register. This does not apply to EW1 mode.
21.8.1.2 Prohibited Instructions

The following instructions cannot be used in EW0 mode because they reference data in the flash memory:
www.DataSheet4U.com UND, INTO, and BRK.
21.8.1.3 Interrupts
Table 21.2 lists the EW0 Mode Interrupts, and Table 21.3 lists the EW1 Mode Interrupts.

When Watchdog Timer, Oscillation
When Maskable Interrupt Stop Detection, Voltage Monitor 1, or
Mode Status
Request is Acknowledged Voltage Monitor 2 Interrupt Request is
Acknowledged
EW0 During auto-erasure Any interrupt can be used by Once an interrupt request is
allocating a vector in RAM acknowledged, auto-programming or
auto-erasure is forcibly stopped
immediately and the flash memory is
reset. Interrupt handling starts after the
fixed period and the flash memory
restarts. Since the block during auto-
erasure or the address during auto-
Auto-programming programming is forcibly stopped, the
normal value may not be read. Execute
auto-erasure again and ensure it
completes normally.
Since the watchdog timer does not stop
during the command operation,
interrupt requests may be generated.
Reset the watchdog timer regularly.
NOTES:
1. Do not use the address match interrupt while a command is being executed because the vector of
the address match interrupt is allocated in ROM.
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REJ09B0244-0300

When Watchdog Timer, Oscillation
When Maskable Interrupt Stop Detection, Voltage Monitor 1, or
Mode Status
Request is Acknowledged Voltage Monitor 2 Interrupt Request is
Acknowledged
EW1 During auto-erasure Auto-erasure is suspended after Once an interrupt request is
(erase-suspend td(SR-SUS) and interrupt acknowledged, auto-programming or
function enabled) handling is executed. Auto- auto-erasure is forcibly stopped
erasure can be restarted by immediately and the flash memory is
setting the FMR41 bit in the reset. Interrupt handling starts after the
www.DataSheet4U.com
FMR4 register to 0 (erase restart) fixed period and the flash memory
after interrupt handling restarts. Since the block during auto-
completes. erasure or the address during auto-
During auto-erasure Auto-erasure has priority and the programming is forcibly stopped, the
(erase-suspend interrupt request normal value may not be read. Execute
function disabled) acknowledgement is put on auto-erasure again and ensure it
standby. Interrupt handling is completes normally.
executed after auto-erasure Since the watchdog timer does not stop
completes. during the command operation,
During auto- Auto-programming is suspended interrupt requests may be generated.
programming after td(SR-SUS) and interrupt Reset the watchdog timer regularly
(program suspend handling is executed. using the erase-suspend function.
function enabled) Auto-programming can be
restarted by setting the FMR42 bit
in the FMR4 register to 0
(program restart) after interrupt
handling completes.
During auto- Auto-programming has priority
programming and the interrupt request
(program suspend acknowledgement is put on
function disabled) standby. Interrupt handling is
executed after auto-programming
completes.
NOTES:
1. Do not use the address match interrupt while a command is executing because the vector of the
address match interrupt is allocated in ROM.
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21.8.1.4 How to Access

Write 0 before writing 1 when setting the FMR01, FMR02, or FMR11 bit to 1. Do not generate an interrupt
between writing 0 and 1.
21.8.1.5 Rewriting User ROM Area

In EW0 Mode, if the supply voltage drops while rewriting any block in which a rewrite control program is
stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be
rewritten correctly. In this case, use standard serial I/O mode.
21.8.1.6 Program
www.DataSheet4U.com Do not write additions to the already programmed address.
21.8.1.7 Entering Stop Mode or Wait Mode

Do not enter stop mode or wait mode during erase-suspend.
21.8.1.8 Program and Erase Voltage for Flash Memory

To perform programming and erasure, use VCC = 2.7 to 5.5 V as the supply voltage. Do not perform
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REJ09B0244-0300
21.9 Notes on Noise
21.9.1 Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure
against Noise and Latch-up
Connect a bypass capacitor (at least 0.1 µF) using the shortest and thickest write possible.
21.9.2 Countermeasures against Noise Error of Port Control Registers

During rigorous noise testing or the like, external noise (mainly power supply system noise) can exceed the
capacity of the MCU's internal noise control circuitry. In such cases the contents of the port related registers
may be changed.
www.DataSheet4U.com As a firmware countermeasure, it is recommended that the port registers, port direction registers, and pull-up
control registers be reset periodically. However, examine the control processing fully before introducing the
reset routine as conflicts may be created between the reset routine and interrupt routines.
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R8C/24 Group, R8C/25 Group 22. Notes on On-Chip Debugger
22. Notes on On-Chip Debugger

When using the on-chip debugger to develop and debug programs for the R8C/24 Group and R8C/25 Group take note
of the following.
(1) Do not access the related UART1 registers.

(2) Some of the user flash memory and RAM areas are used by the on-ship debugger. These areas cannot be
accessed by the user.
Refer to the on-chip debugger manual for which areas are used.
(3) Do not set the address match interrupt (registers AIER, RMAD0, and RMAD1 and fixed vector tables) in a
user system.
(4) Do not use the BRK instruction in a user system.
(5)
www.DataSheet4U.com Debugging is available under the condition of supply voltage VCC = 2.7 to 5.5 V. Debugging with the on-chip
debugger under less than 2.7 V is not allowed.
Connecting and using the on-chip debugger has some special restrictions. Refer to the on-chip debugger manual for
details.
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R8C/24 Group, R8C/25 Group Appendix 1. Package Dimensions
Appendix 1. Package Dimensions

Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of
the Renesas Technology website.
JEITA Package Code RENESAS Code Previous Code MASS[Typ.]

P-LQFP52-10x10-0.65 PLQP0052JA-A 52P6A-A 0.3g Under development
HD
*1
D
39 27
www.DataSheet4U.com
NOTE)
40 26 1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
bp INCLUDE TRIM OFFSET.
b1
HE
E
*2
c1
c
Reference Dimension in Millimeters
Symbol
Min Nom Max
52 Terminal cross section D 9.9 10.0 10.1
ZE
14
E 9.9 10.0 10.1
1 13 A2 1.4
ZD Index mark HD 11.8 12.0 12.2
HE 11.8 12.0 12.2
A 1.7
F A1 0.05 0.1 0.15
c
A2
A
bp 0.27 0.32 0.37

b1 0.30
c 0.09 0.145 0.20
A1
L c1 0.125
y *3
e bp
x L1 0° 8°
e 0.65
Detail F x 0.13
y 0.10
ZD 1.1
ZE 1.1
L 0.35 0.5 0.65
L1 1.0
JEITA Package Code RENESAS Code Previous Code MASS[Typ.]

P-TFLGA64-6x6-0.65 PTLG0064JA-A 64F0G 0.07g
b1
S AB
w S B
b
D S AB
w S A
e
A
H
e
E
E
Reference Dimension in Millimeters

y S 1 2 3 4 5 6 7 8 Symbol
x4 Min Nom Max
v
Index mark
Index mark
D 6.0
(Laser mark) E 6.0
v 0.15
w 0.20
A 1.05
e 0.65
b 0.31 0.35 0.39
b1 0.39 0.43 0.47
x 0.08
y 0.10
Rev.3.00 Feb 29, 2008 Page 481 of 485

REJ09B0244-0300
R8C/24 Group, R8C/25 Group Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging
Appendix 2. Connection Examples between Serial Writer and On-Chip

Debugging Emulator
Appendix Figure 2.1 shows a Connection Example with M16C Flash Starter (M3A-0806), and Appendix Figure 2.2
shows a Connection Example with E8 Emulator (R0E000080KCE00).
TXD
VCC
52
51
50
49
48
47
46
45
44
43
42
41
40
1 39
www.DataSheet4U.com 2 38
3 37
R8C/25 Group
R8C/24 Group
4 36
MODE 5 35
6 34
7 33
RESET 8 32
Connect oscillation 9 31
circuit(1)
VSS 10 30
11 29
12 28
13 14 27
15
16
17
18
19
20
21
22
23
24
25
26
10
TXD 7 VSS
RXD 4
1 VCC
M16C flash starter

(M3A-0806)
RXD
NOTE:
1. An oscillation circuit must be connected, even when
operating with the on-chip oscillator clock.
Appendix Figure 2.1 Connection Example with M16C Flash Starter (M3A-0806)
VCC
52
51
50
49
48
47
46
45
44
43
42
41
40
Open collector buffer 1 39

2 38
4.7kΩ or more User logic
3 37
R8C/25 Group
R8C/24 Group
4 36
5 35
6 34
7 33
Connect oscillation 8 32
circuit(1) 9 31
4.7kΩ ±10% VSS 10 30

14 13 11 29
12 RESET 12 28
MODE 13 27
10
7 MODE
14
15
16
17
18
19
20
21
22
23
24
25
26
8
VCC 6
4
2
VSS
E8 emulator NOTE:
(R0E000080KCE00) 1. It is not necessary to connect an oscillation circuit
when operating with the on-chip oscillator clock.
Appendix Figure 2.2 Connection Example with E8 Emulator (R0E000080KCE00)
Rev.3.00 Feb 29, 2008 Page 482 of 485

REJ09B0244-0300
R8C/24 Group, R8C/25 Group Appendix 3. Example of Oscillation Evaluation Circuit
Appendix 3. Example of Oscillation Evaluation Circuit

Appendix Figure 3.1 shows an Example of Oscillation Evaluation Circuit.
VCC
52
51
50
49
48
47
46
45
44
43
42
41
40
1 39
www.DataSheet4U.com 2 38
3 37
4 36
R8C/25 Group
R8C/24 Group
5 35
Connect 6 34
oscillation
7 33
circuit
RESET 8 32
9 31
Connect
oscillation VSS 10 30
circuit 11 29
12 28
13 27
14
15
16
17
18
19
20
21
22
23
24
25
26
NOTE:
1. After reset, the XIN and XCIN clocks stop.
Write a program to oscillate the XIN and XCIN clocks.
Appendix Figure 3.1 Example of Oscillation Evaluation Circuit
Rev.3.00 Feb 29, 2008 Page 483 of 485

REJ09B0244-0300
R8C/24 Group, R8C/25 Group Index
Index
[A] PUR1 .....................................................................................57
AD ....................................................................................... 386
ADCON0 ............................................................................. 385
[R]
ADCON1 ............................................................................. 386
ADCON2 ............................................................................. 386 RMAD0 ................................................................................121
RMAD1 ................................................................................121
ADIC .................................................................................... 106
AIER .................................................................................... 121
[S]
[C] S0RIC ..................................................................................106
S0TIC ...................................................................................106
CM0 ....................................................................................... 75
S1RIC ..................................................................................106
CM1 ....................................................................................... 76
www.DataSheet4U.com S1TIC ...................................................................................106
CPSRF .................................................................................. 80
SAR ......................................................................................343
CSPR .................................................................................. 129
SSCRH ................................................................................308
SSCRL .................................................................................309
[F] SSER ...................................................................................311
FMR0 .................................................................................. 406 SSMR ...................................................................................310
FMR1 .................................................................................. 407 SSMR2 .................................................................................313
FMR4 .................................................................................. 408 SSRDR ................................................................................314
FRA0 ..................................................................................... 78 SSSR ...................................................................................312
FRA1 ..................................................................................... 78 SSTDR .................................................................................314
FRA2 ..................................................................................... 79 SSUIC ..................................................................................107
FRA4 ..................................................................................... 79
FRA6 ..................................................................................... 79
[T]
FRA7 ..................................................................................... 79
TRA ......................................................................................136
TRACR .................................................................................135
[I] TRAIC ..................................................................................106
ICCR1 ................................................................................. 338 TRAIOC .......................................135, 137, 140, 142, 144, 147
ICCR2 ................................................................................. 339 TRAMR ................................................................................136
ICDRR ................................................................................. 344 TRAPRE ..............................................................................136
ICDRS ................................................................................. 344 TRBCR .................................................................................151
ICDRT ................................................................................. 343 TRBIC ..................................................................................106
ICIER ................................................................................... 341 TRBIOC ...............................................152, 154, 158, 160, 165
ICMR ................................................................................... 340 TRBMR ................................................................................152
ICSR .................................................................................... 342 TRBOCR ..............................................................................151
IICIC .................................................................................... 107 TRBPR .................................................................................153
INT0IC ................................................................................. 108 TRBPRE ..............................................................................153
INT1IC ................................................................................. 108 TRBSC .................................................................................153
INTEN ................................................................................. 115 TRD0 ............................................192, 207, 222, 233, 245, 258
INTF .................................................................................... 116 TRD0IC ................................................................................107
TRD1 ............................................................192, 207, 222, 245
TRD1IC ................................................................................107
[K] TRDCR0 ......................................188, 203, 219, 231, 242, 256
KIEN .................................................................................... 119 TRDCR1 ......................................................188, 203, 219, 242
KUPIC ................................................................................. 106 TRDDF0 ...............................................................................187
TRDDF1 ...............................................................................187
TRDFCR ......................................186, 200, 217, 229, 240, 253
[L] TRDGRAi (i = 0 to 1) ....................193, 208, 223, 234, 245, 259
LINCR ................................................................................. 370 TRDGRBi (i = 0 to 1) ....................193, 208, 223, 234, 245, 259
LINST .................................................................................. 371 TRDGRCi (i = 0 to 1) ...................193, 208, 223, 234, 245, 259
TRDGRDi (i = 0 to 1) ...................193, 208, 223, 234, 245, 259
TRDIER0 ......................................192, 207, 221, 233, 244, 258
[O]
TRDIER1 ......................................192, 207, 221, 233, 244, 258
OCD ...................................................................................... 77 TRDIORA0 ...................................................................189, 204
OFS ....................................................................... 27, 128, 401 TRDIORA1 ...................................................................189, 204
TRDIORC0 ...................................................................190, 205
[P] TRDIORC1 ...................................................................190, 205
TRDMR ........................................184, 198, 215, 228, 239, 252
P2DRR .................................................................................. 58
TRDOCR ..............................................................202, 219, 255
PDi (i = 0 to 4 and 6) ............................................................. 56
TRDOER1 ............................................201, 218, 230, 241, 254
Pi (i = 0 to 4 and 6) ................................................................ 56
TRDOER2 ............................................201, 218, 230, 241, 254
PM0 ....................................................................................... 71
TRDPMR ..............................................................185, 199, 216
PM1 ....................................................................................... 71
TRDPOCR0 .........................................................................222
PMR .............................................................. 58, 293, 314, 344
TRDPOCR1 .........................................................................222
PRCR .................................................................................. 100
TRDSR0 .......................................191, 206, 220, 232, 243, 257
PUR0 ..................................................................................... 57
Rev.3.00 Feb 29, 2008 Page 484 of 485

REJ09B0244-0300
R8C/24 Group, R8C/25 Group Index
TRDSR1 ...................................... 191, 206, 220, 232, 243, 257

TRDSTR ...................................... 184, 198, 215, 228, 238, 252
TRECR1 ...................................................................... 275, 282
TRECR2 ...................................................................... 276, 282
TRECSR ..................................................................... 277, 283
TREHR ................................................................................ 274
TREIC ................................................................................. 106
TREMIN ...................................................................... 273, 281
TRESEC ...................................................................... 273, 281
TREWK ............................................................................... 274
www.DataSheet4U.com
[U]
U0BRG ................................................................................ 291
U0C0 ................................................................................... 292
U0C1 ................................................................................... 293
U0MR .................................................................................. 291
U0RB ................................................................................... 290
U0TB ................................................................................... 290
U1BRG ................................................................................ 291
U1C0 ................................................................................... 292
U1C1 ................................................................................... 293
U1MR .................................................................................. 291
U1RB ................................................................................... 290
U1SR ................................................................................... 293
U1TB ................................................................................... 290
[V]
VCA1 ..................................................................................... 36
VCA2 ............................................................................... 36, 80
VW0C .................................................................................... 37
VW1C .................................................................................... 38
VW2C .................................................................................... 39
[W]
WDC .................................................................................... 128
WDTR ................................................................................. 129
WDTS .................................................................................. 129
Rev.3.00 Feb 29, 2008 Page 485 of 485

REJ09B0244-0300
REVISION HISTORY R8C/24 Group, R8C/25 Group Hardware Manual
Description
Rev. Date
Page Summary
0.10 Jul 27, 2005 − First Edition issued
0.20 Jan 16, 2006 all pages • “Preliminary” deleted
• Symbol name “TRDMDR” → “TRDMR”, “SSUAIC” → “SSUIC”,
“IIC2AIC” → “IICIC”, and “TSTOP0, TSTOP1” → “CSEL0, CSEL1”
www.DataSheet4U.com revised
• Pin name “TCLK” → “TRDCLK” revised
• Bit name “TPSC0 to TPSC2” → “TCK0 to TCK2”, “TRD0 count stop bit”
→ “TRD0 count operation select bit”, and “TRD1 count stop bit” →
“TRD1 count operation select bit” revised
2 Table 1.1 Functions and Specifications for R8C/24 Group revised
4 Figure 1.1 Block Diagram;
“Peripheral Functions” added,
“System Clock Generation” → “System Clock Generator” revised
5 Table 1.3 Product Information for R8C/24 Group revised
6 Table 1.4 Product Information of R8C/25 Group revised
7 Figure 1.4 Pin Assignment (Top View);
“VSS” → “VSS/AVSS” and “VCC” → “VCC/AVCC” revised
8 Table 1.5 Pin Functions;
“Analog power supply input” added, “Reference voltage input” revised
9 Table 1.6 Pin Name Information by Pin Number
“VSS” → “VSS/AVSS” and “VCC” → “VCC/AVCC” revised
10 Figure 2.1 CPU Registers;
“Reserved Area” → “Reserved Bit” revised
12 2.8.10 Reserved Area;
“Reserved Area” → “Reserved bit” revised
13 Figure 3.1 Memory Map of R8C/24 Group;
“Program area” → “program ROM” revised
14 3.2 R8C/25 Group, Figure 3.2 Memory Map of R8C/25 Group;
“Data area” → “data flash”, “Program area” → “program ROM” revised
15 Table 4.1 SFR Information(1);
0012h: “X0h” → “00h”
0016h: “X0h” → “00h”
0024h: “TBD” → “When shipping”
NOTES 3 and 4 revised
24 Figure 5.4 OFS Register; NOTE1 revised and NOTE3 added
25 5.1.1 When Power Supply is Stable (2) revised
5.1.2 Power On (4) revised
26 Figure 5.5 Example of Hardware Reset Circuit and Operation and Figure
5.6 Example of Hardware Reset Circuit (Usage Example of External
Supply Voltage Detection Circuit) and Operation revised
C-1
Description
Rev. Date
Page Summary
0.20 Jan 16, 2006 27 5.2 Power-On Reset Function “When a capacitor is ... or more.” added
Figure 5.7 Example of Power-On Reset Circuit and Operation revised
28 5.4 Voltage Monitor 1 Reset;
“When ... VCC pin drops the Vdet1 ...” → “When ... VCC pin reaches to
the Vdet1 ...” revised
www.DataSheet4U.com
30 to 67 “6. Programmable I/O Ports” → “6. Voltage Detection Circuit” and
“7. Voltage Detection Circuit” → “7. Programmable I/O Ports” revised
33 Figure 6.5 Registers VCA1 and VCA2; VCA2 register revised
34 Figure 6.6 VW0C Register revised
46 Figure 7.2 Configuration of Programmable I/O Ports (2) revised
56 to 66 7.4 Port setting added;
Table 7.4 Port P0_0/AN7 to Table 7.47 Port P6_7/INT3/RXD1 added
67 Table 7.48 Unassigned Pin Handling revised
69 9. Bus revised;
“However, only following SFRs are ... accessed at a time.” added
Table 9.2 Bus Cycles by Access Space of the R8C/25 Group added,
Table 9.3 Access Unit and Bus Operations;
“SFR” → “SFR, data flash”,
“ROM/RAM” → “ROM (program ROM), RAM” revised
71 Figure 10.1 Clock Generation Circuit revised
72 Figure 10.2 CM0 Register revised
73 Figure 10.3 CM1 Register revised
75 Figure 10.5 Registers FRA0 and FRA1; FRA0 register revised
77 Figure 10.8 VCA2 Register added
78 Figure 10.9 Examples of XIN Clock Connection Circuit revised
79 10.2.2 High-Speed On-Chip Oscillator Clock;
“To use the high-speed on-chip ... or more).” added
80 10.3 XCIN Clock “To input an external clock ... pin open.” added
81 10.4.2 CPU Clock “Use the XCIN clock while ... stabilizes.” added
10.4.3 Peripheral Function Clock (f1, f2, f4, f8, f32, fC4, and fC32);
“Use fC4 and fC32 while the XCIN clock oscillation stabilizes.” added
10.4.5 fOCO40M;
“fOCO40M can be ... supply voltage VCC = 3.0 to 5.5 V.” added
10.4.8 fOCO128 added
82 Table 10.2 Settings and Modes of Clock Associated Bits revised
C-2
Description
Rev. Date
Page Summary
0.20 Jan 16, 2006 83 10.5.1.2 Low-Speed Clock Mode;
“In this mode, stopping the XIN clock ... the VCA20 bit.” added
10.5.1.4 Low-Speed On-Chip Oscillator Mode;
“In this mode, stopping the XIN clock ... the VCA20 bit.” added
84 Figure 10.11 Handling Procedure of Internal Power Low Consumption
www.DataSheet4U.com Enabled by VCA20 bit added
88 Figure 10.12 State Transition in Power Control Mode revised
89 10.6.1 How to Use Oscillation Stop Detection Function;
“• This function cannot be... is 2 MHz or below. ...” →
“• This function cannot be... is below 2 MHz. ...” revised
92 10.7.1 Stop Mode and 10.7.2 Wait Mode → 10.7.1 Stop Mode and Wait
Mode revised
10.7.3 Oscillation Stop Detection Function;
“Since ... is 2 MHz or below, ...” → “Since ... is below 2 MHz. ...” revised
“To use this MCU with supply voltage ... to the chip externally.” added
10.7.4 fOCO40M added
107 Figure 12.11 Interrupt Priority Level Judgement Circuit; NOTE2 deleted
114 Figure 12.18 Registers AIER and RMAD0 to RMAD1;
AIER and RMAD0 to RMAD1 register revised
119 12.6.7 Entering Wait Mode after Oscillation Stop Detection Interrupt is
Detected added
121 Figure 13.2 Registers OFS and WDC; OFS register NOTE1 revised and
NOTE3 added, and WDC register NOTE1 deleted
126 Table 14.1 Functional Comparison of Timers;
Input Pin: Timer RD “TRDCLK” added
127 Figure 14.1 Block Diagram of Timer RA revised
135 Table 14.3 Pulse Output Mode Specifications revised
142 Table 14.6 Pulse Period Measurement Mode Specifications revised
144 Figure 14.11 Operating Example of Pulse Period Measurement Mode revised
146 Figure 14.12 Block Diagram of Timer RB revised
147 Figure 14.13 Registers TRBCR and TRBOCR; TRBOCR register revised
149 Figure 14.15 Registers TRBPRE, TRBSC, and TRBPR;
TRBPR register revised
158 Figure 14.20 TRBIOC Register in Programmable One-Shot Generation
Mode
Figure 14.23 Registers TRBIOC and TRBMR in Programmable One-
Shot Generation Mode; TRBIOC register NOTE2 revised
162 Figure 14.25 Registers TRBIOC and TRBMR in Programmable Wait
One-Shot Generation Mode; TRBIOC register NOTE2 revised
165 -Output compare function;
“(Pin output can be changed at detection)” added
C-3
Description
Rev. Date
Page Summary
0.20 Jan 16, 2006 166 to 168 Tables 14.12 Pin Functions TRDIOA0/TRDCLK(P2_0)
Tables 14.13 Pin Functions TRDIOB0(P2_1)
Tables 14.14 Pin Functions TRDIOC0(P2_2)
Tables 14.15 Pin Functions TRDIOD0(P2_3)
Tables 14.16 Pin Functions TRDIOA1(P2_4)
www.DataSheet4U.com Tables 14.17 Pin Functions TRDIOB1(P2_5)
Tables 14.18 Pin Functions TRDIOC1(P2_6)
Tables 14.19 Pin Functions TRDIOD1(P2_7)
Tables 14.20 Pin Functions INT0(P4_5) added
170 14.3.1 Mode Selection deleted
170 Table 14.21 Count Source Selection revised
14.3.1 Count Sources;
“TRDCRi register to ...” → “TRDCRi register (i = 0 or 1) to ...” revised
171 Figure14.29 Buffer Operation in Input Capture Function revised
172 Figure14.30 Buffer Operation in Output Capture Function revised
14.3.2 Buffer Operation;
“input capture and ...” → “timer mode (input capture and ...”
“the IOC2 to IOC0 bits in ...” → “the IOC2 bit in ...”
“the IOA2 to IOA0 bits in ...” → “the IOA2 bit in ...”
“the IOD2 to IOD0 bits in ...” → “the IOD2 bit in ...”
“the IOB2 to IOC0 bits in ...” → “the IOB2 bit in ...” revised
“Bits IMFC and IMFD in the TRDSRi...input capture function.” added
173 14.3.3 Synchronous Operation;
“For the synchronous operation, ... register = 110b).” deleted
174 14.3.4 Pulse Output Forced Cutoff;
“P2D” → “PD2”, “P4D” → “PD4”, and “P4_5” → “PD4_5”, revised
“According to the selection ... details of interrupts.” added
176 14.3.5 Input Capture Function;
“The TRDGRA0 register can also ... trigger input.” added
Figure 14.33 Block Diagram of Input Capture Function revised
177 Table 14.23 Specifications of Input Capture Function revised
178 Figure 14.34 Registers TRDSTR and TRDMR in Input Capture Function
revised
179 Figure 14.35 TRDPMR Register in Input Capture Function revised
180 Figure 14.36 TRDFCR Register in Input Capture Function revised
183 Figure 14.39 Registers TRDIORA0 to TRDIORA1 in Input Capture
Function revised
184 Figure 14.40 Registers TRDIORC0 to TRDIORC1 in Input Capture
Function revised
185 Figure 14.41 Registers TRDSR0 to TRDSR1 in Input Capture Function
revised
187 Table 14.25 Input Pin Function in Input Capture Function deleted
189 14.3.5.1 Digital Filter;
“TRDDF register ...” → “TRDDFi register ...” revised
C-4
Description
Rev. Date
Page Summary
0.20 Jan 16, 2006 192 Figure 14.48 Registers TRDSTR and TRDMR in Output Compare
Function revised
193 Figure 14.49 TRDPMR Register in Output Compare Function revised
194 Figure 14.50 TRDFCR Register in Output Compare Function revised
195 Figure 14.51 Registers TRDOER1 to TRDOER2 in Output Compare
www.DataSheet4U.com
Function;
TRDOER2 register: NOTE1 added
198 Figure 14.54 Registers TRDIORA0 to TRDIORA1 in Output Compare
Function revised
199 Figure 14.55 Registers TRDIORC0 to TRDIORC1 in Output Compare
Function revised
200 Figure 14.56 Registers TRDSR0 to TRDSR1 in Output Compare
Function revised
209 Figure 14.64 Registers TRDSTR and TRDMR in PWM Mode revised
210 Figure 14.65 TRDPMR Register in PWM Mode revised
211 Figure 14.66 TRDFCR Register in PWM Mode revised
212 Figure 14.67 Registers TRDOER1 to TRDOER2 in PWM Mode;
214 Figure 14.69 Registers TRDSR0 to TRDSR1 in PWM Mode revised
222 Figure 14.77 Registers TRDSTR to TRDMR in Reset Synchronous
PWM Mode revised
223 Figure 14.78 TRDFCR Register in Reset Synchronous PWM Mode
revised
224 Figure 14.79 Registers TRDOER1 to TRDOER2 in Reset Synchronous
PWM Mode;
226 Figure 14.81 Registers TRDSR0 to TRDSR1 in Reset Synchronous
PWM Mode revised
232 Figure 14.87 TRDSTR Register in Complementary PWM Mode revised
233 Figure 14.88 TRDMR Register in Complementary PWM Mode revised
234 Figure 14.89 TRDFCR Register in Complementary PWM Mode revised
235 Figure 14.90 Registers TRDOER1 to TRDOER2 in Complementary
PWM Mode;
237 Figure 14.92 Registers TRDSR0 to TRDSR1 in Complementary PWM
Mode revised
244 Figure 14.98 Block Diagram of PWM3 Mode revised
245 Table 14.33 Specifications of PWM3 Mode revised
246 Figure 14.99 TRDSTR Register in PWM3 Mode revised
247 Figure 14.100 TRDMR Register in PWM3 Mode revised
248 Figure 14.101 TRDFCR Register in PWM3 Mode revised
C-5
Description
Rev. Date
Page Summary
0.20 Jan 16, 2006 249 Figure 14.102 Registers TRDOER1 to TRDOER2 in PWM3 Mode;
251 Figure 14.104 TRDCR0 Register in PWM3 Mode NOTE1 deleted
252 Figure 14.105 TRDSR0 Register in PWM3 Mode revised
253 Figure 14.106 TRDIER0 Register in PWM3 Mode revised
www.DataSheet4U.com
255 Table 14.34 TRDGRji Register Functions in PWM3 Mode revised
256 Figure 14.109 Operating Example of PWM3 Mode revised
259 14.3.12.1 TRDSTR Register (i = 0 or 1) added
260 14.3.12.4 “Count Clock Source Switch” → “Count Source Switch”
revised
264 14.3.12.9 Count Source fOCO40M added
275 Table 14.39 Output Compare Mode Specifications revised
281 Figure 14.132 Setting Example in Real-Time Clock Mode revised
285 Figure 15.3 Registers U0TB to U1TB and U0RB to U1RB revised
286 Figure 15.4 Registers U0BRG to U1BRG and U0MR to U1MR; U0BRG
to U1BRG register revised
287 Figure 15.5 Registers U0C0 to U1C0 NOTE1 added
295 Table 15.5 Registers Used and Settings for UART Mode;
UiBRG: “−” → “0 to 7” revised
300 Table 16.1 Mode Selections revised
358 Figure 16.46 Example of Register Setting in Master Transmit Mode
(Clock Synchronous Serial Mode);
“• Set the IICSEL bit in the PMR register to 1” added
377 Table 18.1 Performance of A/D converter revised
378 Figure 18.1 Block Diagram of A/D Converter;
“VSS” → “AVSS” and “Vref” → “Vcom” revised
387 to 389 18.4 A/D Conversion Cycles to 18.6 Inflow Current Bypass Circuit added
390 18.7 Notes on A/D Converter
“• Connect 0.1µF capacitor ... VSS pin.” →
“• Connect 0.1µF capacitor ... AVSS pin.” revised
391 Table 19.1 Flash Memory Version Performance;
• Program and Erase Endurance:(Program area) → (Program ROM),
(Data area) → (Data flash) revised
• NOTE3 added
392 19.2 Memory Map;
“The user ROM ... area ... Block A and B.” →
“The user ROM ... area (program ROM) ... Block A and B (data flash).”
revised
Figure 19.1 Flash Memory Block Diagram for R8C/24 Group revised
393 Figure 19.2 Flash Memory Block Diagram for R8C/25 Group revised
395 Figure 19.4 OFS Register; NOTE1 revised and NOTE3 added
398 19.4.2.4 FMSTP Bit revised
C-6
Description
Rev. Date
Page Summary
0.20 Jan 16, 2006 399 19.4.2.16 FMR47 Bit revised
402 Figure 19.7 FMR4 Register NOTE4 revised
405 Figure 19.11 Process to Reduce Power Consumption in High-Speed On-
Chip Oscillator Mode, Low-Speed On-Chip Oscillator Mode (XIN Clock
Stops) and Low-Speed Clock Mode (XIN Clock Stops) revised
www.DataSheet4U.com
408 19.4.3.5 Block Erase;
“The block erase command cannot be ... program-suspend.” added
409 Figure 19.14 Block Erase Command (When Using Erase-Suspend
Function) revised
412 Figure 19.15 Full Status Check and Handling Procedure for Individual
Errors revised
414 Figure 19.16 Pin Connections for Standard Serial I/O Mode revised
419 19.7.1.9 Program and Erase Voltage for Flash Memory added
420 Table 20.1 Absolute Maximum Ratings;
“VCC” →”VCC/AVCC” revised
Table 20.2 Recommended Operating Conditions revised
421 Table 20.3 A/D Converter Characteristics revised
422 Table 20.4 Flash Memory (Program ROM) Electrical Characteristics
revised
423 Table 20.5 Flash Memory (Data flash Block A, Block B) Electrical revised
424 Table 20.6 Voltage Detection 0 Circuit Electrical Characteristics revised
Table 20.7 Voltage Detection 1 Circuit Electrical Characteristics revised
Table 20.8 Voltage Detection 2 Circuit Electrical Characteristics revised
425 Table 20.9 Reset Circuit Electrical Characteristics (When Using Voltage
Monitor 0 Reset) NOTE2 revised
426 Table 20.11 High-speed On-Chip Oscillator Circuit Electrical
Characteristics revised
Table 20.12 Low-speed On-Chip Oscillator Circuit Electrical
Table 20.13 Power Supply Circuit Timing Characteristics revised
427 Table 20.14 Timing Requirements of Clock Synchronous Serial I/O with
Chip Select revised
431 Table 20.15 Timing Requirements of I2C bus Interface NOTE1 revised
432 Table 20.16 Electrical Characteristics (1) [VCC = 5 V] revised
434 Table 20.18 XIN Input, XCIN Input revised
435 Table 20.20 Serial Interface revised
437 Table 20.23 Electrical Characteristics (4) [Vcc = 3 V] revised
440 Table 20.28 Electrical Characteristics (5) [VCC = 2.2 V] revised
C-7
Description
Rev. Date
Page Summary
0.20 Jan 16, 2006 441 Table 20.29 Electrical Characteristics (6) [Vcc = 2.2 V] revised
Table 20.31 TRAIO Input, INT1 Input revised
Table 20.33 External Interrupt INTi (i = 0, 2, 3) Input
www.DataSheet4U.com
444 21.1.1 Stop Mode and 21.1.2 Wait Mode → 21.1.1 Stop Mode and Wait
Mode revised
21.1.3 Oscillation Stop Detection Function;
“Since ... is 2 MHz or below, ...” → “Since ... is below 2 MHz. ...” revised
“To use this MCU with supply voltage ... to the chip externally.” added
21.1.4 fOCO40M added
Detected added
462 21.7 Notes on A/D Converter
“• Connect 0.1µF capacitor ... VSS pin.” →
“• Connect 0.1µF capacitor ... AVSS pin.” revised
465 21.8.1.9 Program and Erase Voltage for Flash Memory added
467 22. Notes for On-Chip Debugger;
(1) and (6) added, “(2) Do not use addresses ... addresses.” deleted
468 Appendix 1. Package Dimensions;
“TBD” → “PLQP0052JA-A (52P6A-A)” added
469 Appendix Figure 2.1 Connection Example with M16C Flash Starter
(M3A-0806) revised
Appendix Figure 2.2 Connection Example with E8 Emulator
(R0E000080KCE00) revised
470 Appendix Figure 3.1 Example of Oscillation Evaluation Circuit revised
1.00 May 31, 2006 all pages “Under development” deleted
4 Figure 1.1 Block Diagram;
“System clock generator” → “System clock generation circuit” revised
5 to 6 Table 1.3 Product Information for R8C/24 Group and Table 1.4 Product
Information for R8C/25 Group; A part of (D) mark is deleted.
9 Table 1.6 Pin Name Information by Pin Number NOTE1 added
001Ch: “00h” → “00h, 10000000b” revised
0029h: High-Speed On-Chip Oscillator Control Register 4 FRA4 When shipping added
002Bh: High-Speed On-Chip Oscillator Control Register 6 FRA6 When shipping added
NOTE6 added
0118h: Timer RE Second Data Register / Counter Data Register,
0119h: Timer RE Minute Data Register / Compare Data Register
register name revised
C-8
Description
Rev. Date
Page Summary
1.00 May 31, 2006 20 Table 4.6 SFR Information(6);
0143h: “11000000b” → “11100000b” revised
24 Figure 5.4 OFS Register NOTE2 revised
25 5.1.1 When Power Supply is Stable (2) revised
5.1.2 Power On (4) revised
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26 Figure 5.5 Example of Hardware Reset Circuit and Operation and Figure
5.6 Example of Hardware Reset Circuit (Usage Example of External
Supply Voltage Detection Circuit) and Operation revised
27 Figure 5.7 Example of Power-On Reset Circuit and Operation revised
28 5.3 Voltage Monitor 0 Reset revised
33 Figure 6.5 Registers VCA1 and VCA2; VCA2 register NOTE6 revised
45 to 51 Figures 7.1 to .7.7 Configuration of Programmable I/O Ports NOTE1 added
53 Figure 7.9 PDi (i = 0 to 4 and 6) Registers NOTE3 added
54 Figure 7.11 Registers PUR0 and PUR1; After Reset revised
62 Table 7.31 Port P3_4/SDA/SCS revised
70 Table 10.1 Specifications of Clock Generation Circuit revised
71 Figure 10.1 Clock Generation Circuit revised
72 Figure 10.2 CM0 Register; NOTE6 deleted and NOTE9 revised
74 Figure 10.4 OCD Register revised
75 Figure 10.5 Registers FRA0 and FRA1; FRA0 register NOTE2 revised
76 Figure 10.6 Registers FRA2, FRA4, and FRA6;
FRA2 register NOTE2 deleted, registers FRA4 and FRA6 added
77 Figure 10.8 VCA2 Register NOTE6 revised
78 Figure 10.9 Examples of XIN Clock Connection Circuit NOTE1 revised
79 10.2.2 High-Speed On-Chip Oscillator Clock revised
81 10.4.3 Peripheral Function Clock (f1, f2, f4, f8, and f32) revised
82 10.4.9 fC4 and fC32 added
83 Table 10.2 Settings and Modes of Clock Associated Bits revised
84 10.5.1.2 Low-Speed Clock Mode revised
85 10.5.2.2 Entering Wait Mode and 10.5.2.3 Pin Status in Wait Mode
revised
86 10.5.2.4 Exiting Wait Mode;
“When using a peripheral ...instruction is executed.” page changed
Table 10.3 Interrupts to Exit Wait Mode and Usage Conditions revised
87 10.5.2.4 Exiting Wait Mode;
“When exiting by a peripheral ... CPU clock supply is started.” →
“When exiting by a peripheral ... CM07 bit in the CM0 register.” revised
Figure 10.11 Time between Wait Mode and Interrupt Routine Execution added
88 10.5.2.5 Reducing the Internal Power Consumption added
Figure 10.12 Handling Procedure of Internal Power Low Consumption
Enabled by VCA20 bit revised
C-9
Description
Rev. Date
Page Summary
1.00 May 31, 2006 89 Table 10.4 Interrupts to Exit Stop Mode and Usage Conditions revised
90 Figure 10.13 Time between Stop Mode and Interrupt Routine Execution
added
92 10.6.1 How to Use Oscillation Stop Detection Function revised
93 Figure 10.15 Procedure for Switching Clock Source from Low-Speed
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On-Chip Oscillator to XIN Clock revised
94 Figure 10.16 Example of Determining Interrupt Source for Oscillation
Stop Detection, Watchdog Timer, Voltage Monitor 1, or Voltage Monitor 2
Interrupt revised
95 10.7.1 Stop Mode and Wait Mode revised and 10.7.4 fOCO40M deleted
97 Figure 12.1 Interrupts revised
107 Table 12.5 IPL Value When Software or Special Interrupt Is
Acknowledged revised
109 Figure 12.10 Priority Levels of Hardware Interrupts revised
Detected deleted
123 Figure 13.1 Block Diagram of Watchdog Timer revised
124 Figure 13.2 Registers OFS and WDC; OFS Register NOTE2 revised
128 14. Timers; “The count source for each timer ... and reloading.” deleted
130 14.1 Timer RA; “The count source for timer RA ... and reloading.” added
Figure 14.1 Block Diagram of Timer RA revised
131 Figure 14.2 Registers TRACR and TRAIOC revised
132 Figure 14.3 Registers TRAMR, TRAPRE, and TRA revised
133 Table 14.2 Timer Mode Specifications revised
Figure 14.4 TRAIOC Register in Timer Mode revised
(Figure 14.4 TRACR Register in Timer Mode deleted, Figure 14.5
Registers TRAIOC and TRAMR in Timer Mode TRAMR register deleted)
134 14.1.1.1 Timer Write Control during Count added
Figure 14.5 Operating Example of Timer RA when Count Value is
Rewritten during Count added
135 Table 14.3 Pulse Output Mode Specifications revised
136 Figure 14.6 TRAIOC Register in Pulse Output Mode revised
(Figure 14.6 Registers TRACR and TRAIOC in Pulse Output Mode TRACR
register deleted, Figure 14.7 TRAMR Register in Pulse Output Mode deleted)
137 Table 14.4 Event Counter Mode Specifications revised
138 Figure 14.7 TRAIOC Register in Event Counter Mode revised
(Figure 14.8 Registers TRACR and TRAIOC in Event Counter Mode
TRACR register deleted, Figure 14.9 TRAMR Register in Event
Counter Mode deleted)
139 Table 14.5 Pulse Width Measurement Mode Specifications revised
C - 10
Description
Rev. Date
Page Summary
1.00 May 31, 2006 140 Figure 14.8 TRAIOC Register in Pulse Width Measurement Mode revised
(Figure 14.10 Registers TRACR and TRAIOC in Pulse Width
Measurement Mode TRACR register deleted, Figure 14.11 TRAMR
Register in Pulse Width Measurement Mode deleted)
141 Figure 14.9 Operating Example of Pulse Width Measurement Mode revised
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142 Table 14.6 Pulse Period Measurement Mode Specifications revised
143 Figure 14.10 TRAIOC Register in Pulse Period Measurement Mode revised
(Figure 14.13 Registers TRACR and TRAIOC in Pulse Period
Measurement Mode TRACR register deleted, Figure 14.14 TRAMR
Register in Pulse Period Measurement Mode deleted)
144 Figure 14.11 Operating Example of Pulse Period Measurement Mode revised
146 14.2 Timer RB; “The count source for timer RB ... and reloading.” added
• Timer mode: ... (peripheral function clock ... added
Figure 14.12 Block Diagram of Timer RB revised
147 Figure 14.13 Registers TRBCR and TRBOCR revised
148 Figure 14.14 Registers TRBIOC and TRBMR revised
149 Figure 14.15 Registers TRBPRE, TRBSC, and TRBPR revised
150 Table 14.7 Timer Mode Specifications revised
Figure 14.16 TRBIOC Register in Timer Mode revised
(Figure 14.20 Registers TRBIOC and TRBMR in Timer Mode TRBMR
register deleted)
151 14.2.1.1 Timer Write Control during Count added
152 Figure 14.17 Operating Example of Timer RB when Count Value is
Rewritten during Count added
153 Table 14.8 Programmable Waveform Generation Mode Specifications
revised
154 Figure 14.18 TRBIOC Register in Programmable Waveform Generation
Mode revised
(Figure 14.20 Registers TRBIOC and TRBMR in Timer Mode TRBMR
register deleted)
Figure 14.19 Operating Example of Timer RB in Programmable
Waveform Generation Mode revised
155 Table 14.9 Programmable One-Shot Generation Mode Specifications revised
156 Figure 14.20 TRBIOC Register in Programmable One-Shot Generation
Mode revised
(Figure 14.23 Registers TRBIOC and TRBMR in Programmable One-
Shot Generation Mode TRBMR register deleted)
157 Figure 14.21 Operating Example of Programmable One-Shot
Generation Mode revised
158 14.2.3.1 Selecting One-shot Trigger added
159 Table 14.10 Programmable Wait One-Shot Generation Mode
Specifications revised
C - 11
Description
Rev. Date
Page Summary
1.00 May 31, 2006 161 Figure 14.22 TRBIOC Register in Programmable Wait One-Shot
Generation Mode
(Figure 14.25 Registers TRBIOC and TRBMR in Programmable Wait
One-Shot Generation Mode TRBMR register deleted)
162 Figure 14.23 Operating Example of Programmable Wait One-Shot
www.DataSheet4U.com Generation Mode revised
163 14.2.5 Notes on Timer RB;
“• ... Timer RB starts counting at the first ... 1 (during count).” deleted
“• When the TSTOP bit in the TRBCR register ... immediately stops.
• If the TOSST bit or the TOSSP bit ... also be set to 0 or 1.” added
165 Table 14.12 Pin Functions TRDIOA0/TRDCLK(P2_0) revised
167 Table 14.20 Pin Functions INT0(P4_5) revised
179 Figure 14.33 TRDFCR Register in Input Capture Function NOTE2 revised
193 Figure 14.47 TRDFCR Register in Output Compare Function NOTE2 revised
210 Figure 14.63 TRDFCR Register in PWM Mode NOTE2 revised
220 Table 14.29 Reset Synchronous PWM Mode Specifications revised
222 Figure 14.75 TRDFCR Register in Reset Synchronous PWM Mode
NOTES 1 and 3 revised
225 Figure 14.78 Registers TRDSR0 to TRDSR1 in Reset Synchronous
PWM Mode revised
227 Table 14.30 TRDGRji Register Functions in Reset Synchronous PWM
Mode revised
233 Figure 14.86 TRDFCR Register in Complementary PWM Mode NOTES
1 and 4 revised
239 14.3.9 Complementary PWM Mode;
“Since a value cannot be written to ... BFC1, and BFD1.” added
244 Table 14.33 Specifications of PWM3 Mode revised
247 Figure 14.98 TRDFCR Register in PWM3 Mode NOTE2 revised
254 Table 14.34 TRDGRji Register Functions in PWM3 Mode revised,
14.3.10 PWM3 Mode; “Registers TRDGRC0, ... and BFD1.” added
258 14.3.12.1 TRDSTR Register (i = 0 or 1);
“• Table 14.36 lists the TRDIOji (j = A, B, C, ... timer RD output.” added
259 14.3.12.6 Reset Synchronous PWM Mode; Change procedure (2) revised
14.3.12.7 Complementary PWM Mode;
•Change bits CMD1 to CMD0 in the TRDFCR register in the ... ;
Change procedure: When setting to complementary ... (2) ,
Change procedure: When stopping complementary ... (1) and (2) revised
•Do not write to ... ; “However, set to the TRDGRD0, ... BFD1.” added
263 14.3.12.8 PWM3 Mode deleted
264 14.4 Timer RE; “The count source for timer RE ... operations.” added
265 Figure 14.112 Block Diagram of Real-Time Clock Mode revised
C - 12
Description
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Page Summary
1.00 May 31, 2006 287 Figure 15.6 Registers U0C1 to U1C1, U1SR, and PMR;
U0C1 to U1C1 register NOTE2 added
288 Table 15.1 Clock Synchronous Serial I/O Mode Specifications revised
289 15.1 Clock Synchronous Serial I/O Mode;
“Table 15.3 ... The TXD0 pin ...” → “Table 15.3 ... The TXDi pin ...” revised
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294 15.2 Clock Asynchronous Serial I/O (UART) Mode;
“Table 15.6 ... The TXD0 pin ...” → “Table 15.6 ... The TXDi pin ...” revised
296 Figure 15.11 Receive Timing Example in UART Mode;
“RI bit” → “IR bit” revised
300 Table 16.2 Clock Synchronous Serial I/O with Chip Select Specifications;
“φ” → “f1” revised and NOTE2 deleted
304 Figure 16.4 SSMR Register
307 Figure 16.7 SSMR2 Register revised
308 Figure 16.8 Registers SSTDR and SSRDR; SSTDR registers NOTE1 deleted
309 16.2.1 Transfer Clock; “φ” → “f1” revised
314 16.2.5.2 Data Transmission;
“When setting the MCU is set as a slave device, ... enabled.” deleted
316 Figure 16.14 Sample Flowchart of Data Transmission (Clock
Synchronous Communication Mode) NOTE2 deleted
319 16.2.5.4 Data Transmission/Reception;
“When the MCU is set as the slave device, ... enabled.” deleted
320 Figure 16.17 Sample Flowchart of Data Transmission/Reception (Clock
Synchronous Communication Mode) NOTE2 deleted
322 Figure 16.18 Initialization in 4-Wire Bus Communication Mode revised
323 16.2.6.2 Data Transmission;
“When the MCU is set as a slave device, ... enabled.” deleted
358 Figure 16.47 Example of Register Setting in Master Receive Mode (I2C
bus Interface Mode) revised
362 to 375 17. Hardware LIN;
“Sync Break” → “Synch Break” and “Sync Field” → “Synch Field” revised
362 Figure 17.1 Block Diagram of Hardware LIN revised
364 Figure 17.2 LINCR Register revised
365 Figure 17.3 LINST Register revised
366 Figure 17.4 Typical Operation when Sending a Header Field
“RAIC” → “TRAIC” revised
367 Figure 17.5 Example of Header Field Transmission Flowchart (1) revised
368 Figure 17.6 Example of Header Field Transmission Flowchart (2) revised
369 17.4.2 Slave Mode (5) revised
Figure 17.7 Typical Operation when Receiving a Header Field revised
370 Figure 17.8 Example of Header Field Reception Flowchart (1) revised
371 Figure 17.9 Example of Header Field Reception Flowchart (2) revised
C - 13
Description
Rev. Date
Page Summary
1.00 May 31, 2006 372 Figure 17.10 Example of Header Field Reception Flowchart (3) revised
373 Figure 17.11 Typical Operation when a Bus Collision is Detected;
“RAIC” → “TRAIC” revised
374 17.5 Interrupt Requests;
“There are four ... Sync Break generation completed, ... , and bus collision
www.DataSheet4U.com
detection.” → “There are three ... , and bus collision detection.” revised
Table 17.2 Interrupt Requests of Hardware LIN revised
376 Table 18.1 Performance of A/D converter revised
380 Table 18.2 One-Shot Mode Specifications revised
384 Figure 18.6 ADCON0 Register in Repeat Mode revised
386 18.3 Sample and Hold;
“... to 28 φAD cycles for 8-bit resolution or 33 φAD resolution” and
“When performing A/D conversion, charge the sampling time.” deleted
387 Figure 18.10 Internal Equivalent Circuit of Analog Input revised
388 18.6 Inflow Current Bypass Circuit deleted
18.6 Output Impedance of Sensor under A/D Conversion added
389 18.7 Notes on A/D Converter revised
394 Figure 19.4 OFS Register NOTE2 revised
395 Table 19.3 Differences between EW0 Mode and EW1 Mode revised
397 19.4.2.1 FMR00 Bit
“... (including suspend periods) ...” added
399 Figure 19.5 FMR0 Register NOTE6 added
401 Figure 19.7 FMR4 Register; NOTES 2, 3 and 4 revised and NOTE5 added
402 Figure 19.8 Timing of Suspend Operation revised
405 19.4.3.1 Read Array Command
“The MCU also enters read array mode after a reset.” added
19.4.3.2 Read Status Register Command
“The MCU remains in read status mode ... command is written.” added
406 19.4.3.4 Program Command;
“When suspend function disabled, ...”, “When suspend function
enabled, the FMR44 bit ... when auto-programming completes.” added
Figure 19.12 Program Command (When Suspend Function Disabled) title revised
407 Figure 19.13 Program Command (When Suspend Function Enabled) added
408 19.4.3.5 Block Erase revised
Figure 19.14 Block Erase Command (When Erase-Suspend Function
Disabled) title revised
409 Figure 19.15 Block Erase Command (When Erase-Suspend Function
Enabled) revised
410 Table 19.5 Status Register Bits revised
413 19.5 Standard Serial I/O Mode revised
Table 19.7 Pin Functions (Flash Memory Standard Serial I/O Mode 2) added
414 Table 19.8 Pin Functions (Flash Memory Standard Serial I/O Mode 3) revised
C - 14
Description
Rev. Date
Page Summary
1.00 May 31, 2006 415 Figure 19.17 Pin Connections for Standard Serial I/O Mode 3 title revised
416 Figure 19.18 Pin Processing in Standard Serial I/O Mode 2 added,
Figure 19.19 Pin Processing in Standard Serial I/O Mode 3 title revised
420 19.7.1.7 Reset Flash Memory deleted
421 Table 20.2 Recommended Operating Conditions revised
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422 Figure 20.1 Ports P0 to P4, P6 Timing Measurement Circuit; title revised
423 Table 20.4 Flash Memory (Program ROM) Electrical Characteristics
revised
424 Table 20.5 Flash Memory (Data flash Block A, Block B) Electrical
425 Figure 20.2 Time delay until Suspend title revised
426 Table 20.9 Voltage Monitor 0 Reset Electrical Characteristics → Table
20.9 Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical
Table 20.10 Power-on Reset Circuit Electrical Characteristics (When Not
Using Voltage Monitor 0 Reset) deleted
Figure 20.3 Power-on Reset Circuit Electrical Characteristics revised
427 Table 20.10 High-speed On-Chip Oscillator Circuit Electrical
Table 20.11 Low-speed On-Chip Oscillator Circuit Electrical
442 Table 20.28 Electrical Characteristics (6) [Vcc = 2.2 V] revised
445 21.1.1 Stop Mode and Wait Mode revised and 21.1.4 fOCO40M deleted
Detected deleted
450 21.3.2 Notes on Timer RB;
“• ... Timer RB starts counting at the first ... 1 (during count).” deleted
“• When the TSTOP bit in the TRBCR register ... immediately stops.
• If the TOSST bit or the TOSSP bit ... also be set to 0 or 1.” added
451 21.3.3.1 TRDSTR Register (i = 0 or 1) revised
452 21.3.3.6 Reset Synchronous PWM Mode; Change procedure (2) revised
21.3.3.7 Complementary PWM Mode;
•Change bits CMD1 to CMD0 in the TRDFCR register in the ...;
Change procedure: When setting to complementary ... (2) ,
Change procedure: When stopping complementary ... (1) and (2) revised
•Do not write to ...; “However, set to the TRDGRD0, ... BFD1.” added
456 21.3.3.8 PWM3 Mode deleted
462 21.6 Notes on Hardware LIN; “Sync Break” → “Synch Break” revised
463 21.7 Notes on A/D Converter revised
466 21.8.1.7 Reset Flash Memory deleted
C - 15
Description
Rev. Date
Page Summary
1.00 May 31, 2006 468 22. Notes on On-Chip Debugger; (2) revised
469 Appendix 1. Package Dimensions
“The latest package ... Renesas Technology website.” added
2.00 Nov 01, 2006 all pages “PTLG0064JA-A (64F0G)” package added
Y version added
www.DataSheet4U.com
Factory programming product added
1 1. Overview; “... or a 64-pin molded-plastic FLGA.“ added
2, 3 Table 1.1 Functions and Specifications for R8C/24 Group, Table 1.2
Functions and Specifications for R8C/25 Group;
Package: “64-pin molded-plastic FLGA” added
9 Figure 1.4 PLQP0052JA-A Package Pin Assignments (Top View);
NOTE3 revised
10 Figure 1.5 PTLG0064JA-A Package Pin Assignments added
18 Table 4.1 revised
36 Figure 6.5 NOTE6 revised
66 Table 7.33, Table 7.35 revised
78 Figure 10.5 NOTE2 added
81 Figure 10.9 revised
82 10.2.2 “Adjust the FRA1 register so that .... 40 MHz or less.” added
98 10.7.1 revised, 10.7.2 added
123 12.6.3 “and Table 20.18 (VCC = 5V), ... TRAIO Input, INT1 Input.”
deleted
127 Figure 13.2; Watchdog Timer Control Register: After Reset “When read,
the content is undefined.” added
140 Table 14.4; TRAO pin function: Specification “or pulse output” added
215 Figure 14.65 Timer RD Output Control Register NOTE2 added
262 14.3.12.7 “Do not use the TRDGRC0 register in complementary PWM
mode.” deleted
291 Table 15.1 NOTE2 revised
C - 16
Description
Rev. Date
Page Summary
2.00 Nov 01, 2006 298 Figure 15.10 revised
344 to 349 Figure 16.32, Figure 16.33, Figure 16.34, Figure 16.35, Figure 16.36
revised
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377 17.4.4 added
378 Table 17.2 Cause of Interrupt “8” → “6”
384 Table 18.2; Stop condition: Specification “when the ADCAP .... (software
trigger)” added, Input pin: Specification “AN8” → “AN0”
425 Table 20.1 Absolute Maximum Ratings; NOTE1 added
432 Table 20.10; “VCC = 4.5 V to 5.5 V -20°C ≤ Topr ≤ 85°C”, “VCC = 4.5 V to
5.5 V -40°C ≤ Topr ≤ 85°C” added
Oscillation stability time: Condition “VCC = 5.0 V, Topr = 25°C” deleted
Table 5.11; Oscillation stability time: Condition “VCC = 5.0 V,
Topr = 25°C” deleted
438 Table 20.15; IIH, IIL, RPULLUP Condition: “Vcc = 5V” added
439 Table 20.16; Condition: High-speed on-chip oscillator mode revised
440 Table 20.17 added
443 Table 20.22; IIH, IIL, RPULLUP Condition: “Vcc = 3V” added
444 Table 20.23; Condition “Increase during A/D converter operation” added
448 Table 20.29; Condition “Increase during A/D converter operation” added
475 Package Dimensions; “PTLG0064JA-A (64F0G)” added
3.00 Feb 29, 2008 − “RENESAS TECHNICAL UPDATE” reflected:
TN-16C-A164A/E, TN-16C-A165A/E, TN-16C-A166A/E,
TN-16C-A167A/E
2, 3 Table 1.1, Table 1.2 Clock; “Real-time clock (timer RE)” added
5, 7 Table 1.3, Table 1.4 revised
6, 8 Figure 1.2, Figure 1.3; ROM number “XXX” added
16, 17 Figure 3.1, Figure 3.2; “Expanded area” deleted
C - 17
Description
Rev. Date
Page Summary
3.00 Feb 29, 2008 18 Table 4.1; “002Ch” added, “003Bh” “003Ch” “003Dh” deleted
27, 128, Figure 5.4, Figure 13.2, Figure 19.4; “OFS Register” revised
401
28 5.1.1, 5.1.2; “Wait for 1/fOCO-S × 20.” → “Wait for 10 µs or more.”
www.DataSheet4U.com
29 Figure 5.5, Figure 5.6 revised
30 5.2, Figure 5.7 revised
61, 62 Table 7.17, Table 7.19 revised
65 Table 7.29, Table 7.30 revised
73 10. “(with oscillation stop detection function)” deleted
79 Figure 10.6 “FRA7 Register” added
81 Figure 10.9 added
83 10.2.2 revised
88 10.5.1.2, 10.5.1.4 revised
92 10.5.2.5, Figure 10.13 revised
96 10.6.1 revised
99 10.7.1, 10.7.2 revised
103 12.1.3.1 revised
105 Table 12.2 “Reference” revised
115 12.2.1 revised
120 Table 12.6 revised, NOTE2 added
124 12.6.4 deleted
133 Table 14.1 “• fC32” deleted
134 Figure 14.1 “TSTART” → “TCSTF”
138 Figure 14.5 “... to 0 (During count).” → “... to 1 (During count).”
149 14.1.6 revised, “• When the TRAPRE ...” “• When the TRA ...” added
150 14.2 “The reload register ...” deleted
Figure 14.12 revised
156 Figure 14.17 “... to 0 (During count).” → “... to 1 (During count).”
C - 18
Description
Rev. Date
Page Summary
3.00 Feb 29, 2008 159 Table 14.9 NOTE2 added
“...0 (one-shot stops).” → “...1 (one-shot stops).”
“TRBP pin function” → “TRBO pin function”
160 Figure 14.20 “... When write, ...” → “... If necessary, ...”
164 Table 14.10 NOTE2 added
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167 to 170 14.2.5 revised
14.2.5.1, 14.2.5.2, 14.2.5.3, 14.2.5.4 added
197, 214 Table 14.25, Table 14.27;
“at the same time as the TRDi register ... 0000h” deleted
198, 215 Figure 14.47, Figure 14.63; “TRDSTR register” revised
201 Figure 14.50 “TRDOER1 register” revised
209 Figure 14.59 “of counter clear” deleted
227, 251 Table 14.29, Table 14.33;
“at the same time as the TRD0 register ... 0000h” deleted
252 Figure 14.98 “TRDSTR register” revised
264 14.3.12.1, Table 14.36; “after the count is cleared” deleted
277 Figure 14.121 “00” → “00b”
291 Figure 15.4 “UARTi Transmit/Receive Mode Register” NOTE2 deleted
293 Figure 15.6 “(b7-b4)” → “(b7-b6)”
300 Table 15.5 NOTE2 added
304 15.3 revised
308 Figure 16.2 NOTE4 deleted
309 Figure 16.3 revised, NOTE4 deleted
312 Figure 16.6 NOTE2, NOTE7 revised
C - 19
Description
Rev. Date
Page Summary
3.00 Feb 29, 2008 314 Figure 16.8;
SSTDR register: NOTE1 deleted, SSRDR register: NOTE2 deleted
334 16.2.8.1 deleted
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343, 344 Figure 16.29, Figure 16.30; NOTE1 deleted
367 16.3.8.1 revised, 16.3.8.2 added
373 Figure 17.5 “... in LINST register → 0” → “... in LINST register → 1”
379 Figure 17.11 “SCDCT” → “BCDCT”
385, 388, Figure 18.2, Figure 18.4, Figure 18.6; NOTE4 revised
391
396 18.7 revised
403 19.4.1, 19.4.2; “(SR-ES)” → “(SR-SUS)”
404 19.4.2.4 “located outside ... memory.” → “transferred to the RAM.”
405 19.4.2.15 revised
406 Figure 19.5 NOTE3, NOTE5 revised
413 19.4.3.4 revised
418 Table 19.6 “FRM00 Register” → “FRM0 Register”
435 Table 20.10 revised, NOTE4 added
454 21.1.1, 21.1.2 revised
C - 20
Description
Rev. Date
Page Summary
3.00 Feb 29, 2008 455 21.2.4 deleted
458 21.3.1 revised, “• When the TRAPRE ...” “• When the TRA ...” added
459 to 462 21.3.2 revised
21.3.2.1, 21.3.2.2, 21.3.2.3, 21.3.2.4 added
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463 21.3.1.1, Table 21.1; “after the count is cleared” deleted
472 21.4 revised
473 2.5.1.1 deleted, 2.5.2.1 revised, 2.5.2.2 added
475 21.7 revised
482 Appendix Figure 2.1, Appendix Figure 2.2 revised
483 Appendix Figure 3.1 revised
C - 21
www.DataSheet4U.com
R8C/24 Group, R8C/25 Group Hardware Manual
Publication Data: Rev.0.10 Jul 27, 2005

Rev.3.00 Feb 29, 2008
Published by: Sales Strategic Planning Div.

Renesas Technology Corp.
© 2008. Renesas Technology Corp., All rights reserved. Printed in Japan

www.DataSheet4U.com
Hardware Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan

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REJ09B0244-0300

R8C/24 Group, R8C/25 Group

RENESAS 16-BIT SINGLE-CHIP MCU

1. Handling of Unused Pins

Document Type Description Document Title Document No.

(1) Register Names, Bit Names, and Pin Names

(2) Notation of Numbers

0 Symbol Address After Reset

Bit Symbol Bit Name Function RW

Nothing is assigned. If necessary, set to 0.

(b3) Reserved bits Set to 0. RW

XXX bits Function varies according to the operating

XXX7 XXX bit 0: XXX

Abbreviation Full Form

SFR Page Reference ........................................................................................................................... B - 1

4. Special Function Registers (SFRs) ............................................................................................... 18

6. Voltage Detection Circuit .............................................................................................................. 33

7. Programmable I/O Ports ............................................................................................................... 46

8. Processor Mode ............................................................................................................................ 71

10. Clock Generation Circuit ............................................................................................................... 73

12. Interrupts ..................................................................................................................................... 101

13. Watchdog Timer .......................................................................................................................... 127

14. Timers ......................................................................................................................................... 132

15. Serial Interface ............................................................................................................................ 288

16. Clock Synchronous Serial Interface ............................................................................................ 305

17. Hardware LIN .............................................................................................................................. 368

18. A/D Converter ............................................................................................................................. 383

19. Flash Memory ............................................................................................................................. 397

20. Electrical Characteristics ............................................................................................................ 428

21. Usage Notes ............................................................................................................................... 454

22. Notes on On-Chip Debugger ...................................................................................................... 480

Appendix 1. Package Dimensions ........................................................................................................ 481

Appendix 3. Example of Oscillation Evaluation Circuit ......................................................................... 483

Index ..................................................................................................................................................... 484

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1.2 Performance Overview

Table 1.1 Functions and Specifications for R8C/24 Group

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Table 1.2 Functions and Specifications for R8C/25 Group

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1.3 Block Diagram

I/O ports Port P0 Port P1 Port P2 Port P3 Port P4 Port P6

I2C bus interface or clock synchronous

Watchdog timer R8C/Tiny Series CPU core Memory

Figure 1.1 Block Diagram

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1.4 Product Information

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Type No. R 5 F 21 24 6 S N XXX FP

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Type No. R 5 F 21 25 6 S N XXX FP

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1.5 Pin Assignments

Figure 1.4 PLQP0052JA-A Package Pin Assignments (Top View)

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Pin assignments (top perspective view)

Figure 1.5 PTLG0064JA-A Package Pin Assignments

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