Rnsas06854 1

REJ09B0216-0300
The revision list can be viewed directly by

clicking the title page.
The revision list summarizes the locations of

revisions and additions. Details should always
be checked by referring to the relevant text.
16 H8/36079Group, H8/36077Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer

H8 Family/H8/300H Tiny Series
H8/36079 H8/36079GF, HD64F36079G
H8/36079LF, HD64F36079L
H8/36078GF, HD64F36078G
H8/36078LF, HD64F36078L
H8/36077 H8/36077GF, HD64F36077G
H8/36077LF, HD64F36077L
H8/36074GF, HD64F36074G
H8/36074LF, HD64F36074L
Rev.3.00
Revision Date: Sep. 10, 2007
Rev. 3.00 Sep. 10, 2007 Page ii of xxxii
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
Rev. 3.00 Sep. 10, 2007 Page iii of xxxii

General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins

Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through current flows internally, and a malfunction may occur.
3. Processing before Initialization

Note: When power is first supplied, the product's state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses

Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system's
operation is not guaranteed if they are accessed.
Rev. 3.00 Sep. 10, 2007 Page iv of xxxii

Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product

2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 3.00 Sep. 10, 2007 Page v of xxxii

Preface
The H8/36079 Group and H8/36077 Group are single-chip microcomputers made up of the high-
speed H8/300H CPU employing Renesas Technology original architecture as their cores, and the
peripheral functions required to configure a system. The H8/300H CPU has an instruction set that
is compatible with the H8/300 CPU.
Target Users: This manual was written for users who will be using the H8/36079 Group and
H8/36077 Group in the design of application systems. Target users are expected to
understand the fundamentals of electrical circuits, logical circuits, and
microcomputers.
Objective: This manual was written to explain the hardware functions and electrical
characteristics of the H8/36079 Group and H8/36077 Group to the target users.
Refer to the H8/300H Series Software Manual for a detailed description of the
instruction set.
Notes on reading this manual:
• In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
• In order to understand the details of the CPU's functions
Read the H8/300H Series Software Manual.
• In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 21,
List of Registers.
Example: Register name: The following notation is used for cases when the same or a
similar function, e.g. serial communication interface, is
implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
Bit order: The MSB is on the left and the LSB is on the right.
Rev. 3.00 Sep. 10, 2007 Page vi of xxxii

Notes:
When using an on-chip emulator (E7, E8) for H8/36079 and H8/36077 program development and
debugging, the following restrictions must be noted.
1. The NMI pin is reserved for the E7 or E8, and cannot be used.
2. Pins P85, P86, and P87 cannot be used. In order to use these pins, additional hardware must be
provided on the user board.
3. The following areas are used by the E7 or E8, and are not available to the user.
H8/36079 Group: H'01F000 to H'01FFFF
H8/36077 Group: H'D000 to H'DFFF
4. The following areas must on no account be accessed.
H8/36079 Group: H'FFF780 to H'FFFB7F
H8/36077 Group: H'F780 to H'FB7F
5. In usage with the E7or E8, address breaks can be set as either available to the user or for use
by the E7 or E8. If address breaks are set as being used by the E7, the address break control
registers must not be accessed.
6. In usage with the E7 or E8, NMI is an input/output pin (open-drain in output mode), P85 and
P87 are input pins, and P86 is an output pin.
7. Use channel 1 of the SCI3 (P21/RXD, P22/TXD) in on-board programming mode by boot
mode.
8. In usage with the E7or E8, the power supply voltage for H8/36079 Group products must be
greater than the reset detection voltage of the low voltage detection circuit.
Related Manuals: The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/
Rev. 3.00 Sep. 10, 2007 Page vii of xxxii

H8/36079 Group and H8/36077 Group manuals:
Document Title Document No.

H8/36079 Group, H8/36077 Group Hardware Manual This manual
H8/300H Series Software Manual REJ09B0213
User's manuals for development tools:

H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor REJ10B0058
User's Manual
H8S, H8/300 Series Simulator/Debugger User's Manual REJ10B0211
H8S, H8/300 Series High-Performance Embedded Workshop 3, Tutorial REJ10B0024
H8S, H8/300 Series High-Performance Embedded Workshop 3, User's REJ10B0026
Manual
Application notes:

H8S, H8/300 Series C/C++ Compiler Package Application Note REJ05B0464
TM
Single Power Supply F-ZTAT On-Board Programming REJ05B0520
All trademarks and registered trademarks are the property of their respective owners.
Rev. 3.00 Sep. 10, 2007 Page viii of xxxii

Contents
Section 1 Overview..................................................................................................1
1.1 Features................................................................................................................................. 1
1.2 Block Diagram...................................................................................................................... 4
1.3 Pin Arrangement ................................................................................................................... 5
1.4 Pin Functions ........................................................................................................................ 6
Section 2 CPU..........................................................................................................9
2.1 Address Space and Memory Map ....................................................................................... 11
2.2 Register Configuration........................................................................................................ 12
2.2.1 General Registers ................................................................................................ 13
2.2.2 Program Counter (PC) ........................................................................................ 14
2.2.3 Condition-Code Register (CCR) ......................................................................... 14
2.3 Data Formats....................................................................................................................... 16
2.3.1 General Register Data Formats ........................................................................... 16
2.3.2 Memory Data Formats ........................................................................................ 18
2.4 Instruction Set ..................................................................................................................... 19
2.4.1 Table of Instructions Classified by Function ...................................................... 19
2.4.2 Basic Instruction Formats ................................................................................... 29
2.5 Addressing Modes and Effective Address Calculation....................................................... 30
2.5.1 Addressing Modes .............................................................................................. 30
2.5.2 Effective Address Calculation ............................................................................ 33
2.6 Basic Bus Cycle .................................................................................................................. 36
2.6.1 Access to On-Chip Memory (RAM, ROM)........................................................ 36
2.6.2 On-Chip Peripheral Modules .............................................................................. 37
2.7 CPU States .......................................................................................................................... 38
2.8 Usage Notes ........................................................................................................................ 39
2.8.1 Notes on Data Access to Empty Areas ............................................................... 39
2.8.2 EEPMOV Instruction.......................................................................................... 39
2.8.3 Bit-Manipulation Instruction............................................................................... 40
Section 3 Exception Handling ...............................................................................45

3.1 Exception Sources and Vector Address .............................................................................. 46
3.2 Register Descriptions .......................................................................................................... 48
3.2.1 Interrupt Edge Select Register 1 (IEGR1) .......................................................... 48
3.2.2 Interrupt Edge Select Register 2 (IEGR2) .......................................................... 49
3.2.3 Interrupt Enable Register 1 (IENR1) .................................................................. 50
Rev. 3.00 Sep. 10, 2007 Page ix of xxxii

3.2.4 Interrupt Enable Register 2 (IENR2) .................................................................. 51
3.2.5 Interrupt Flag Register 1 (IRR1)......................................................................... 51
3.2.6 Interrupt Flag Register 2 (IRR2)......................................................................... 53
3.2.7 Wakeup Interrupt Flag Register (IWPR) ............................................................ 53
3.3 Reset Exception Handling .................................................................................................. 55
3.4 Interrupt Exception Handling ............................................................................................. 56
3.4.1 External Interrupts .............................................................................................. 56
3.4.2 Internal Interrupts ............................................................................................... 58
3.4.3 Interrupt Handling Sequence .............................................................................. 58
3.4.4 Interrupt Response Time..................................................................................... 60
3.5 Usage Notes ........................................................................................................................ 62
3.5.1 Interrupts after Reset........................................................................................... 62
3.5.2 Notes on Stack Area Use .................................................................................... 62
3.5.3 Notes on Rewriting Port Mode Registers ........................................................... 62
Section 4 Address Break .......................................................................................63

4.1 Register Descriptions.......................................................................................................... 64
4.1.1 Address Break Control Register (ABRKCR) ..................................................... 64
4.1.2 Address Break Status Register (ABRKSR) ........................................................ 67
4.1.3 Break Address Registers (BARE, BARH, BARL) ............................................. 67
4.1.4 Break Data Registers (BDRH, BDRL) ............................................................... 67
4.2 Operation ............................................................................................................................ 68
Section 5 Clock Pulse Generator ...........................................................................71

5.1 Features............................................................................................................................... 72
5.2 Register Descriptions.......................................................................................................... 72
5.2.1 RC Control Register (RCCR) ............................................................................. 73
5.2.2 RC Trimming Data Protect Register (RCTRMDPR).......................................... 74
5.2.3 RC Trimming Data Register (RCTRMDR) ........................................................ 75
5.2.4 Clock Control/Status Register (CKCSR) ............................................................ 76
5.3 System Clock Select Operation .......................................................................................... 79
5.3.1 Clock Control Operation..................................................................................... 79
5.3.2 Clock Switching Timing ..................................................................................... 83
5.4 Trimming of On-Chip Oscillator Frequency ...................................................................... 86
5.5 External Oscillators............................................................................................................. 88
5.5.1 Connecting Crystal Resonator ............................................................................ 88
5.5.2 Connecting Ceramic Resonator .......................................................................... 89
5.5.3 Inputting External Clock..................................................................................... 89
5.6 Subclock Oscillator............................................................................................................. 90
5.6.1 Connecting 32.768-kHz Crystal Resonator......................................................... 90
Rev. 3.00 Sep. 10, 2007 Page x of xxxii

5.6.2 Pin Connection when Not Using Subclock ......................................................... 91
5.7 Prescaler.............................................................................................................................. 91
5.7.1 Prescaler S........................................................................................................... 91
5.7.2 Prescaler W ......................................................................................................... 91
5.8 Usage Notes ........................................................................................................................ 92
5.8.1 Note on Resonators ............................................................................................. 92
5.8.2 Notes on Board Design ....................................................................................... 92
Section 6 Power-Down Modes ..............................................................................93

6.1 Register Descriptions .......................................................................................................... 94
6.1.1 System Control Register 1 (SYSCR1) ................................................................ 94
6.1.2 System Control Register 2 (SYSCR2) ................................................................ 97
6.1.3 Module Standby Control Register 1 (MSTCR1)................................................. 98
6.1.4 Module Standby Control Register 2 (MSTCR2)................................................. 99
6.2 Mode Transitions and States of LSI.................................................................................. 100
6.2.1 Sleep Mode ....................................................................................................... 103
6.2.2 Standby Mode ................................................................................................... 103
6.2.3 Subsleep Mode.................................................................................................. 104
6.2.4 Subactive Mode ................................................................................................ 104
6.3 Operating Frequency in Active Mode............................................................................... 105
6.4 Direct Transition ............................................................................................................... 105
6.4.1 Direct Transition from Active Mode to Subactive Mode.................................. 105
6.4.2 Direct Transition from Subactive Mode to Active Mode.................................. 106
6.5 Module Standby Function................................................................................................. 106
Section 7 ROM ....................................................................................................107

7.1 Block Configuration ......................................................................................................... 107
7.2 Register Descriptions ........................................................................................................ 112
7.2.1 Flash Memory Control Register 1 (FLMCR1).................................................. 112
7.2.2 Flash Memory Control Register 2 (FLMCR2).................................................. 113
7.2.3 Erase Block Register 1 (EBR1) ........................................................................ 114
7.2.4 Flash Memory Power Control Register (FLPWCR) ......................................... 116
7.2.5 Flash Memory Enable Register (FENR) ........................................................... 116
7.3 On-Board Programming Modes........................................................................................ 117
7.3.1 Boot Mode ........................................................................................................ 117
7.3.2 Programming/Erasing in User Program Mode.................................................. 120
7.4 Flash Memory Programming/Erasing ............................................................................... 121
7.4.1 Program/Program-Verify .................................................................................. 121
7.4.2 Erase/Erase-Verify............................................................................................ 124
7.4.3 Interrupt Handling when Programming/Erasing Flash Memory....................... 124
Rev. 3.00 Sep. 10, 2007 Page xi of xxxii

7.5 Program/Erase Protection ................................................................................................. 126
7.5.1 Hardware Protection ......................................................................................... 126
7.5.2 Software Protection........................................................................................... 126
7.5.3 Error Protection................................................................................................. 126
7.6 Programmer Mode ............................................................................................................ 127
7.7 Power-Down States for Flash Memory............................................................................. 127
Section 8 RAM ....................................................................................................129
Section 9 I/O Ports...............................................................................................131

9.1 Port 1................................................................................................................................. 131
9.1.1 Port Mode Register 1 (PMR1) .......................................................................... 132
9.1.2 Port Control Register 1 (PCR1) ........................................................................ 133
9.1.3 Port Data Register 1 (PDR1)............................................................................. 133
9.1.4 Port Pull-Up Control Register 1 (PUCR1)........................................................ 134
9.1.5 Pin Functions .................................................................................................... 134
9.2 Port 2................................................................................................................................. 137
9.2.4 Pin Functions .................................................................................................... 139
9.3 Port 3................................................................................................................................. 141
9.3.3 Pin Functions .................................................................................................... 142
9.4 Port 5................................................................................................................................. 145
9.4.4 Port Pull-Up Control Register 5 (PUCR5)........................................................ 148
9.4.5 Pin Functions .................................................................................................... 148
9.5 Port 6................................................................................................................................. 151
9.5.3 Pin Functions .................................................................................................... 152
9.6 Port 7................................................................................................................................. 156
9.6.3 Pin Functions .................................................................................................... 157
9.7 Port 8................................................................................................................................. 159
Rev. 3.00 Sep. 10, 2007 Page xii of xxxii

9.7.3 Pin Functions .................................................................................................... 160
9.8 Port B ................................................................................................................................ 161
9.8.1 Port Data Register B (PDRB) ........................................................................... 161
9.8.2 Pin Functions .................................................................................................... 162
9.9 Port C ................................................................................................................................ 165
9.9.1 Port Control Register C (PCRC) ....................................................................... 165
9.9.2 Port Data Register C (PDRC) ........................................................................... 166
9.9.3 Pin Functions .................................................................................................... 166
Section 10 Realtime Clock (RTC) .......................................................................167

10.1 Features............................................................................................................................. 167
10.2 Input/Output Pin ............................................................................................................... 168
10.3.1 Second Data Register/Free Running Counter Data Register (RSECDR).......... 169
10.3.2 Minute Data Register (RMINDR)..................................................................... 170
10.3.3 Hour Data Register (RHRDR) .......................................................................... 171
10.3.4 Day-of-Week Data Register (RWKDR) ........................................................... 172
10.3.5 RTC Control Register 1 (RTCCR1).................................................................. 173
10.3.6 RTC Control Register 2 (RTCCR2).................................................................. 174
10.3.7 Clock Source Select Register (RTCCSR) ......................................................... 175
10.4 Operation .......................................................................................................................... 176
10.4.1 Initial Settings of Registers after Power-On ..................................................... 176
10.4.2 Initial Setting Procedure ................................................................................... 176
10.4.3 Data Reading Procedure ................................................................................... 177
10.5 Interrupt Sources............................................................................................................... 178
Section 11 Timer B1 ............................................................................................179

11.1 Features............................................................................................................................. 179
11.2 Input/Output Pin ............................................................................................................... 180
11.3.1 Timer Mode Register B1 (TMB1) .................................................................... 181
11.3.2 Timer Counter B1 (TCB1)................................................................................ 182
11.3.3 Timer Load Register B1 (TLB1)....................................................................... 182
11.4 Operation .......................................................................................................................... 182
11.4.1 Interval Timer Operation .................................................................................. 182
11.4.2 Auto-Reload Timer Operation .......................................................................... 183
11.4.3 Event Counter Operation .................................................................................. 183
11.5 Timer B1 Operating Modes .............................................................................................. 183
Rev. 3.00 Sep. 10, 2007 Page xiii of xxxii

Section 12 Timer V .............................................................................................185
12.1 Features............................................................................................................................. 185
12.2 Input/Output Pins.............................................................................................................. 187
12.3 Register Descriptions........................................................................................................ 187
12.3.1 Timer Counter V (TCNTV) .............................................................................. 187
12.3.2 Time Constant Registers A and B (TCORA, TCORB) .................................... 188
12.3.3 Timer Control Register V0 (TCRV0) ............................................................... 188
12.3.4 Timer Control/Status Register V (TCSRV) ...................................................... 189
12.3.5 Timer Control Register V1 (TCRV1) ............................................................... 191
12.4 Operation .......................................................................................................................... 192
12.4.1 Timer V Operation............................................................................................ 192
12.5 Timer V Application Examples ........................................................................................ 195
12.5.1 Pulse Output with Arbitrary Duty Cycle........................................................... 195
12.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input .......... 196
12.6 Usage Notes ...................................................................................................................... 197
Section 13 Timer Z..............................................................................................199

13.1 Features............................................................................................................................. 199
13.3.1 Timer Start Register (TSTR) ............................................................................ 206
13.3.2 Timer Mode Register (TMDR) ......................................................................... 206
13.3.3 Timer PWM Mode Register (TPMR) ............................................................... 207
13.3.4 Timer Function Control Register (TFCR) ........................................................ 208
13.3.5 Timer Output Master Enable Register (TOER) ................................................ 210
13.3.6 Timer Output Control Register (TOCR) ........................................................... 212
13.3.7 Timer Counter (TCNT)..................................................................................... 213
13.3.8 General Registers A, B, C, and D (GRA, GRB, GRC, and GRD).................... 213
13.3.9 Timer Control Register (TCR).......................................................................... 214
13.3.10 Timer I/O Control Register (TIORA and TIORC)............................................ 215
13.3.11 Timer Status Register (TSR)............................................................................. 218
13.3.12 Timer Interrupt Enable Register (TIER) ........................................................... 220
13.3.13 PWM Mode Output Level Control Register (POCR) ....................................... 221
13.3.14 Interface with CPU ........................................................................................... 222
13.4 Operation .......................................................................................................................... 223
13.4.1 Counter Operation............................................................................................. 223
13.4.2 Waveform Output by Compare Match.............................................................. 227
13.4.3 Input Capture Function ..................................................................................... 229
13.4.4 Synchronous Operation..................................................................................... 233
13.4.5 PWM Mode ...................................................................................................... 234
Rev. 3.00 Sep. 10, 2007 Page xiv of xxxii

13.4.6 Reset Synchronous PWM Mode ....................................................................... 240
13.4.7 Complementary PWM Mode ............................................................................ 244
13.4.8 Buffer Operation ............................................................................................... 254
13.4.9 Timer Z Output Timing .................................................................................... 262
13.5 Interrupts........................................................................................................................... 265
13.5.1 Status Flag Set Timing...................................................................................... 265
13.5.2 Status Flag Clearing Timing ............................................................................. 267
13.6 Usage Notes ...................................................................................................................... 268
Section 14 Watchdog Timer ................................................................................275

14.1 Features............................................................................................................................. 275
14.2.1 Timer Control/Status Register WD (TCSRWD)............................................... 276
14.2.2 Timer Counter WD (TCWD) ............................................................................ 278
14.2.3 Timer Mode Register WD (TMWD) ................................................................ 278
14.3 Operation .......................................................................................................................... 279
Section 15 14-Bit PWM.......................................................................................281

15.1 Features............................................................................................................................. 281
15.2 Input/Output Pin ............................................................................................................... 282
15.3.1 PWM Control Register (PWCR)....................................................................... 283
15.3.2 PWM Data Registers U and L (PWDRU, PWDRL)......................................... 283
15.4 Operation .......................................................................................................................... 284
Section 16 Serial Communication Interface 3 (SCI3) .........................................285

16.1 Features............................................................................................................................. 285
16.3.1 Receive Shift Register (RSR) ........................................................................... 289
16.3.2 Receive Data Register (RDR) ........................................................................... 289
16.3.3 Transmit Shift Register (TSR) .......................................................................... 289
16.3.4 Transmit Data Register (TDR).......................................................................... 290
16.3.5 Serial Mode Register (SMR)............................................................................. 290
16.3.6 Serial Control Register 3 (SCR3)...................................................................... 292
16.3.7 Serial Status Register (SSR) ............................................................................. 294
16.3.8 Bit Rate Register (BRR) ................................................................................... 296
16.4 Operation in Asynchronous Mode .................................................................................... 303
16.4.1 Clock................................................................................................................. 303
16.4.2 SCI3 Initialization............................................................................................. 304
Rev. 3.00 Sep. 10, 2007 Page xv of xxxii

16.4.3 Data Transmission ............................................................................................ 305
16.4.4 Serial Data Reception ....................................................................................... 307
16.5 Operation in Clock Synchronous Mode............................................................................ 311
16.5.1 Clock................................................................................................................. 311
16.5.2 SCI3 Initialization............................................................................................. 311
16.5.3 Serial Data Transmission .................................................................................. 312
16.5.4 Serial Data Reception (Clock Synchronous Mode) .......................................... 314
16.5.5 Simultaneous Serial Data Transmission and Reception.................................... 316
16.6 Multiprocessor Communication Function ........................................................................ 318
16.6.1 Multiprocessor Serial Data Transmission ......................................................... 319
16.6.2 Multiprocessor Serial Data Reception .............................................................. 321
16.7 Interrupts........................................................................................................................... 325
16.8 Usage Notes ...................................................................................................................... 326
16.8.1 Break Detection and Processing ....................................................................... 326
16.8.2 Mark State and Break Sending ......................................................................... 326
16.8.3 Receive Error Flags and Transmit Operations
(Clock Synchronous Mode Only) ..................................................................... 326
16.8.4 Receive Data Sampling Timing and Reception Margin in
Asynchronous Mode......................................................................................... 327
Section 17 I2C Bus Interface 2 (IIC2)..................................................................329

17.1 Features............................................................................................................................. 329
2
17.3.1 I C Bus Control Register 1 (ICCR1) ................................................................. 332
2
17.3.2 I C Bus Control Register 2 (ICCR2) ................................................................. 335
2
17.3.3 I C Bus Mode Register (ICMR)........................................................................ 336
2
17.3.4 I C Bus Interrupt Enable Register (ICIER) ....................................................... 338
2
17.3.5 I C Bus Status Register (ICSR)......................................................................... 340
17.3.6 Slave Address Register (SAR).......................................................................... 343
2
17.3.7 I C Bus Transmit Data Register (ICDRT)......................................................... 344
2
17.3.8 I C Bus Receive Data Register (ICDRR).......................................................... 344
2
17.3.9 I C Bus Shift Register (ICDRS)........................................................................ 344
17.4 Operation .......................................................................................................................... 345
2
17.4.1 I C Bus Format.................................................................................................. 345
17.4.2 Master Transmit Operation ............................................................................... 346
17.4.3 Master Receive Operation................................................................................. 348
17.4.4 Slave Transmit Operation ................................................................................. 350
17.4.5 Slave Receive Operation................................................................................... 352
17.4.6 Clock Synchronous Serial Format .................................................................... 354
Rev. 3.00 Sep. 10, 2007 Page xvi of xxxii

17.4.7 Noise Filter ....................................................................................................... 357
17.4.8 Example of Use................................................................................................. 357
17.5 Interrupt Request............................................................................................................... 362
17.6 Bit Synchronous Circuit.................................................................................................... 363
17.7 Usage Notes ...................................................................................................................... 364
17.7.1 Issue (Retransmission) of Start/Stop Conditions .............................................. 364
2
17.7.2 WAIT Setting in I C Bus Mode Register (ICMR) ............................................ 364
17.7.3 Restriction in Use of Multi-Master ................................................................... 365
17.7.4 Continuous Data Reception in Master Receive Mode ...................................... 365
Section 18 A/D Converter....................................................................................367

18.1 Features............................................................................................................................. 367
18.3.1 A/D Data Registers A to D (ADDRA to ADDRD) .......................................... 370
18.3.2 A/D Control/Status Register (ADCSR) ............................................................ 371
18.3.3 A/D Control Register (ADCR) ......................................................................... 372
18.4 Operation .......................................................................................................................... 373
18.4.1 Single Mode...................................................................................................... 373
18.4.2 Scan Mode ........................................................................................................ 373
18.4.3 Input Sampling and A/D Conversion Time....................................................... 374
18.4.4 External Trigger Input Timing.......................................................................... 375
18.5 A/D Conversion Accuracy Definitions ............................................................................. 376
18.6 Usage Notes ...................................................................................................................... 378
18.6.1 Permissible Signal Source Impedance .............................................................. 378
18.6.2 Influences on Absolute Accuracy ..................................................................... 378
Section 19 Band-Gap Circuit, Power-On Reset, and

Low-Voltage Detection Circuits........................................................379
19.1 Features............................................................................................................................. 380
19.2.1 Low-Voltage-Detection Control Register (LVDCR) ........................................ 382
19.2.2 Low-Voltage-Detection Status Register (LVDSR)........................................... 384
19.2.3 Reset Source Decision Register (LVDRF)........................................................ 385
19.3 Operations......................................................................................................................... 386
19.3.1 Power-On Reset Circuit .................................................................................... 386
19.3.2 Low-Voltage Detection Circuit......................................................................... 387
19.3.3 Deciding Reset Source...................................................................................... 392
Rev. 3.00 Sep. 10, 2007 Page xvii of xxxii

Section 20 Power Supply Circuit ........................................................................393
20.1 Power Supply Connection of 5.0-V-Specification Microcontrollers ................................ 393
20.2 Power Supply Connection of 3.3-V-Specification Microcontrollers ................................ 394
Section 21 List of Registers.................................................................................395

21.1 Register Addresses (Address Order)................................................................................. 396
21.2 Register Bits...................................................................................................................... 403
21.3 Registers States in Each Operating Mode......................................................................... 409
Section 22 Electrical Characteristics ...................................................................415

22.1 Absolute Maximum Ratings ............................................................................................. 415
22.2 Electrical Characteristics (F-ZTAT™ 5.0-V Version) ..................................................... 416
22.2.1 Power Supply Voltage and Operating Ranges .................................................. 416
22.2.2 DC Characteristics ............................................................................................ 419
22.2.3 AC Characteristics ............................................................................................ 425
22.2.4 A/D Converter Characteristics .......................................................................... 430
22.2.5 Watchdog Timer Characteristics....................................................................... 431
22.2.6 Flash Memory Characteristics .......................................................................... 432
22.2.7 Power-Supply-Voltage Detection Circuit Characteristics................................. 434
22.2.8 LVDI External Input Voltage Detection Circuit Characteristics ...................... 434
22.2.9 Power-On Reset Circuit Characteristics ........................................................... 435
22.3 Electrical Characteristics (F-ZTAT™ 3.3-V Version) ..................................................... 436
22.3.1 Power Supply Voltage and Operating Ranges .................................................. 436
22.3.2 DC Characteristics ............................................................................................ 438
22.3.3 AC Characteristics ............................................................................................ 444
22.3.4 A/D Converter Characteristics .......................................................................... 449
22.3.5 Watchdog Timer Characteristics....................................................................... 450
22.3.6 Flash Memory Characteristics .......................................................................... 451
22.3.7 Power-Supply-Voltage Detection Circuit Characteristics................................. 453
22.3.8 LVDI External Input Voltage Detection Circuit Characteristics ...................... 453
22.3.9 Power-On Reset Circuit Characteristics ........................................................... 454
22.4 Operation Timing.............................................................................................................. 455
22.5 Output Load Condition ..................................................................................................... 458
Appendix A Instruction Set ...............................................................................459

A.1 Instruction List.................................................................................................................. 459
A.2 Operation Code Map......................................................................................................... 474
A.3 Number of Execution States ............................................................................................. 477
A.4 Combinations of Instructions and Addressing Modes ...................................................... 488
Rev. 3.00 Sep. 10, 2007 Page xviii of xxxii

Appendix B I/O Port Block Diagrams ...............................................................489
B.1 I/O Port Block Diagrams .................................................................................................. 489
B.2 Port States in Each Operating State .................................................................................. 513
Appendix C Product Code Lineup.....................................................................514
Appendix D Package Dimensions .....................................................................516
Main Revisions and Additions in this Edition .....................................................519
Index ....................................................................................................................525
Rev. 3.00 Sep. 10, 2007 Page xix of xxxii

Rev. 3.00 Sep. 10, 2007 Page xx of xxxii
Figures
Section 1 Overview
Figure 1.1 Block Diagram of H8/36079 Group and H8/36077 Group ........................................... 4
Figure 1.2 Pin Arrangement of H8/36079 Group and
H8/36077 Group (FP-64K, FP-64A) ............................................................................ 5
Section 2 CPU
Figure 2.1 Memory Map............................................................................................................... 11
Figure 2.2 CPU Registers ............................................................................................................. 12
Figure 2.3 Usage of General Registers ......................................................................................... 13
Figure 2.4 Relationship between Stack Pointer and Stack Area ................................................... 14
Figure 2.5 General Register Data Formats (1) .............................................................................. 16
Figure 2.5 General Register Data Formats (2) .............................................................................. 17
Figure 2.6 Memory Data Formats................................................................................................. 18
Figure 2.7 Instruction Formats...................................................................................................... 29
Figure 2.8 Branch Address Specification in Memory Indirect Mode ........................................... 33
Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 36
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)..................................... 37
Figure 2.11 CPU Operation States................................................................................................ 38
Figure 2.12 State Transitions ........................................................................................................ 39
Figure 2.13 Example of Timer Configuration with Two Registers
Allocated to Same Address ....................................................................................... 40
Section 3 Exception Handling
Figure 3.1 Reset Sequence............................................................................................................ 57
Figure 3.2 Stack Status after Exception Handling ........................................................................ 59
Figure 3.3 Interrupt Sequence....................................................................................................... 61
Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure .............. 62
Section 4 Address Break
Figure 4.1 Block Diagram of Address Break................................................................................ 63
Figure 4.2 Address Break Interrupt Operation Example (1)......................................................... 68
Figure 4.2 Address Break Interrupt Operation Example (2)......................................................... 69
Section 5 Clock Pulse Generator
Figure 5.1 Block Diagram of Clock Pulse Generator ................................................................... 71
Figure 5.2 State Transition of System Clock ................................................................................ 79
Figure 5.3 Flowchart of Clock Switching with Backup Function Enabled................................... 80
Figure 5.4 Flowchart of Clock Switching with Backup Function Disabled (1)
(From On-Chip Oscillator Clock to External Clock) ................................................. 81
Rev. 3.00 Sep. 10, 2007 Page xxi of xxxii

(From External Clock to On-Chip Oscillator Clock).................................................. 82
Figure 5.6 Timing Chart of Switching from On-Chip Oscillator Clock to
External Clock............................................................................................................ 83
Figure 5.7 Timing Chart to Switch from External Clock to On-Chip
Oscillator Clock .......................................................................................................... 84
Figure 5.8 External Oscillation Backup Timing ........................................................................... 85
Figure 5.9 Example of Trimming Flow for On-Chip Oscillator Clock ........................................ 86
Figure 5.10 Timing Chart of Trimming of On-Chip Oscillator Frequency .................................. 87
Figure 5.11 Block Diagram of External Clock Oscillator ............................................................ 88
Figure 5.12 Example of Connection to Crystal Resonator ........................................................... 88
Figure 5.13 Equivalent Circuit of Crystal Resonator.................................................................... 89
Figure 5.14 Example of Connection to Ceramic Resonator ......................................................... 89
Figure 5.15 Example of External Clock Input .............................................................................. 89
Figure 5.16 Block Diagram of Subclock Oscillator...................................................................... 90
Figure 5.17 Typical Connection to 32.768-kHz Crystal Resonator.............................................. 90
Figure 5.18 Equivalent Circuit of 32.768-kHz Crystal Resonator................................................ 90
Figure 5.19 Pin Connection when not Using Subclock ................................................................ 91
Figure 5.20 Example of Incorrect Board Design .......................................................................... 92
Section 6 Power-Down Modes
Figure 6.1 Mode Transition Diagram ......................................................................................... 100
Section 7 ROM
Figure 7.1 Flash Memory Block Configuration (1) (H8/36079GF and H8/36079LF) ............... 108
Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode .......................... 120
Figure 7.3 Program/Program-Verify Flowchart ......................................................................... 122
Figure 7.4 Erase/Erase-Verify Flowchart ................................................................................... 125
Section 9 I/O Ports
Figure 9.1 Port 1 Pin Configuration............................................................................................ 131
Figure 9.8 Port B Pin Configuration........................................................................................... 161
Figure 9.9 Port C Pin Configuration........................................................................................... 165
Rev. 3.00 Sep. 10, 2007 Page xxii of xxxii

Section 10 Realtime Clock (RTC)
Figure 10.1 Block Diagram of RTC ........................................................................................... 167
Figure 10.2 Definition of Time Expression ................................................................................ 173
Figure 10.3 Initial Setting Procedure .......................................................................................... 176
Figure 10.4 Example: Reading of Inaccurate Time Data............................................................ 177
Section 11 Timer B1
Figure 11.1 Block Diagram of Timer B1.................................................................................... 179
Section 12 Timer V
Figure 12.1 Block Diagram of Timer V...................................................................................... 186
Figure 12.2 Increment Timing with Internal Clock .................................................................... 193
Figure 12.3 Increment Timing with External Clock ................................................................... 193
Figure 12.4 OVF Set Timing ...................................................................................................... 193
Figure 12.5 CMFA and CMFB Set Timing ................................................................................ 194
Figure 12.6 TMOV Output Timing ............................................................................................ 194
Figure 12.7 Clear Timing by Compare Match ............................................................................ 194
Figure 12.8 Clear Timing by TMRIV Input ............................................................................... 195
Figure 12.9 Pulse Output Example ............................................................................................. 195
Figure 12.10 Example of Pulse Output Synchronized to TRGV Input....................................... 196
Figure 12.11 Contention between TCNTV Write and Clear ...................................................... 197
Figure 12.12 Contention between TCORA Write and Compare Match ..................................... 198
Figure 12.13 Internal Clock Switching and TCNTV Operation ................................................. 198
Section 13 Timer Z
Figure 13.1 Timer Z Block Diagram .......................................................................................... 201
Figure 13.2 Timer Z (Channel 0) Block Diagram ...................................................................... 202
Figure 13.3 Timer Z (Channel 1) Block Diagram ...................................................................... 203
Figure 13.4 Example of Outputs in Reset Synchronous PWM Mode and
Complementary PWM Mode.................................................................................. 210
Figure 13.5 Accessing Operation of 16-Bit Register
(between CPU and TCNT (16 bits)) ....................................................................... 222
Figure 13.6 Accessing Operation of 8-Bit Register
(between CPU and TSTR (8 bits)) .......................................................................... 222
Figure 13.7 Example of Counter Operation Setting Procedure .................................................. 223
Figure 13.8 Free-Running Counter Operation ............................................................................ 224
Figure 13.9 Periodic Counter Operation..................................................................................... 225
Figure 13.10 Count Timing at Internal Clock Operation ............................................................ 225
Figure 13.11 Count Timing at External Clock Operation (Both Edges Detected)...................... 226
Figure 13.12 Example of Setting Procedure for Waveform Output
by Compare Match................................................................................................ 227
Figure 13.13 Example of 0 Output/1 Output Operation ............................................................. 228
Rev. 3.00 Sep. 10, 2007 Page xxiii of xxxii

Figure 13.14 Example of Toggle Output Operation ................................................................... 228
Figure 13.15 Output Compare Timing ....................................................................................... 229
Figure 13.16 Example of Input Capture Operation Setting Procedure ....................................... 230
Figure 13.17 Example of Input Capture Operation .................................................................... 231
Figure 13.18 Input Capture Signal Timing ................................................................................. 232
Figure 13.19 Example of Synchronous Operation Setting Procedure ........................................ 233
Figure 13.20 Example of Synchronous Operation...................................................................... 234
Figure 13.21 Example of PWM Mode Setting Procedure .......................................................... 235
Figure 13.22 Example of PWM Mode Operation (1) ................................................................. 236
Figure 13.26 Example of Reset Synchronous PWM Mode Setting Procedure........................... 241
Figure 13.27 Example of Reset Synchronous PWM Mode Operation
(OLS0 = OLS1 = 1) .............................................................................................. 242
Figure 13.28 Example of Reset Synchronous PWM Mode Operation
(OLS0 = OLS1 = 0) .............................................................................................. 243
Figure 13.29 Example of Complementary PWM Mode Setting Procedure................................ 245
Figure 13.30 Canceling Procedure of Complementary PWM Mode.......................................... 246
Figure 13.31 Example of Complementary PWM Mode Operation (1)....................................... 247
Figure 13.32 (1) Example of Complementary PWM Mode Operation
(TPSC2 = TPSC1 = TPSC0 = 0) (2)............................................................... 249
(TPSC2 = TPSC1 = TPSC0 ≠ 0) (3) ............................................................... 250
Figure 13.33 Timing of Overshooting ........................................................................................ 251
Figure 13.34 Timing of Undershooting ...................................................................................... 251
Figure 13.35 Compare Match Buffer Operation......................................................................... 254
Figure 13.36 Input Capture Buffer Operation............................................................................. 255
Figure 13.37 Example of Buffer Operation Setting Procedure................................................... 255
Figure 13.38 Example of Buffer Operation (1)
(Buffer Operation for Output Compare Register) ................................................. 256
Figure 13.39 Example of Compare Match Timing for Buffer Operation ................................... 257
(Buffer Operation for Input Capture Register) ..................................................... 258
Figure 13.41 Input Capture Timing of Buffer Operation............................................................ 259
Figure 13.42 Buffer Operation (3)
(Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1) ........... 260
(Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1) ........... 261
Figure 13.44 Example of Output Disable Timing of Timer Z by Writing to TOER .................. 262
Rev. 3.00 Sep. 10, 2007 Page xxiv of xxxii

Figure 13.45 Example of Output Disable Timing of Timer Z by External Trigger .................... 263
Figure 13.46 Example of Output Inverse Timing of Timer Z by Writing to TFCR ................... 264
Figure 13.47 Example of Output Inverse Timing of Timer Z by Writing to POCR ................... 264
Figure 13.48 IMF Flag Set Timing when Compare Match Occurs ............................................ 265
Figure 13.49 IMF Flag Set Timing at Input Capture .................................................................. 266
Figure 13.50 OVF Flag Set Timing ............................................................................................ 266
Figure 13.51 Status Flag Clearing Timing.................................................................................. 267
Figure 13.52 Contention between TCNT Write and Clear Operations....................................... 268
Figure 13.53 Contention between TCNT Write and Increment Operations ............................... 269
Figure 13.54 Contention between GR Write and Compare Match ............................................. 269
Figure 13.55 Contention between TCNT Write and Overflow................................................... 270
Figure 13.56 Contention between GR Read and Input Capture.................................................. 271
Figure 13.57 Contention between Count Clearing and Increment Operations
by Input Capture................................................................................................... 272
Figure 13.58 Contention between GR Write and Input Capture................................................. 273
Figure 13.59 When Compare Match and Bit Manipulation Instruction to TOCR
Occur at the Same Timing .................................................................................... 274
Section 14 Watchdog Timer
Figure 14.1 Block Diagram of Watchdog Timer ........................................................................ 275
Figure 14.2 Watchdog Timer Operation Example...................................................................... 279
Section 15 14-BIt PWM
Figure 15.1 Block Diagram of 14-Bit PWM .............................................................................. 281
Figure 15.2 Waveform Output by 14-Bit PWM ......................................................................... 284
Section 16 Serial Communication Interface 3 (SCI3)
Figure 16.1 Block Diagram of SCI3 ........................................................................................... 287
Figure 16.2 Data Format in Asynchronous Communication ...................................................... 303
Figure 16.3 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)............. 303
Figure 16.4 Sample SCI3 Initialization Flowchart ..................................................................... 304
Figure 16.5 Example of SCI3 Transmission in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)........................................................................... 305
Figure 16.6 Sample Serial Transmission Data Flowchart (Asynchronous Mode) ...................... 306
Figure 16.7 Example of SCI3 Reception in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)........................................................................... 307
Figure 16.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (1)...................... 309
Figure 16.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (2)...................... 310
Figure 16.9 Data Format in Clock Synchronous Communication .............................................. 311
Figure 16.10 Example of SCI3 Transmission in Clock Synchronous Mode .............................. 312
Figure 16.11 Sample Serial Transmission Flowchart (Clock Synchronous Mode) .................... 313
Rev. 3.00 Sep. 10, 2007 Page xxv of xxxii

Figure 16.12 Example of SCI3 Reception in Clock Synchronous Mode.................................... 314
Figure 16.13 Sample Serial Reception Flowchart (Clock Synchronous Mode) ......................... 315
Figure 16.14 Sample Flowchart of Simultaneous Serial Transmit and
Receive Operations (Clock Synchronous Mode) .................................................. 317
Figure 16.15 Example of Inter-Processor Communication Using Multiprocessor
Format (Transmission of Data H'AA to Receiving Station A)............................. 319
Figure 16.16 Sample Multiprocessor Serial Transmission Flowchart ........................................ 320
Figure 16.17 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 322
Figure 16.17 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 323
Figure 16.18 Example of SCI3 Reception Using Multiprocessor Format
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ............................. 324
Figure 16.19 Receive Data Sampling Timing in Asynchronous Mode ...................................... 327
Section 17 I2C Bus Interface 2 (IIC2)
Figure 17.1 Block Diagram of I2C Bus Interface 2..................................................................... 330
Figure 17.2 External Circuit Connections of I/O Pins ................................................................ 331
Figure 17.3 I2C Bus Formats ...................................................................................................... 345
Figure 17.4 I2C Bus Timing........................................................................................................ 345
Figure 17.5 Master Transmit Mode Operation Timing (1) ......................................................... 347
Figure 17.6 Master Transmit Mode Operation Timing (2) ......................................................... 347
Figure 17.7 Master Receive Mode Operation Timing (1) .......................................................... 349
Figure 17.8 Master Receive Mode Operation Timing (2) .......................................................... 350
Figure 17.9 Slave Transmit Mode Operation Timing (1) ........................................................... 351
Figure 17.10 Slave Transmit Mode Operation Timing (2) ......................................................... 352
Figure 17.11 Slave Receive Mode Operation Timing (1)........................................................... 353
Figure 17.12 Slave Receive Mode Operation Timing (2)........................................................... 353
Figure 17.13 Clock Synchronous Serial Transfer Format .......................................................... 354
Figure 17.14 Transmit Mode Operation Timing......................................................................... 355
Figure 17.15 Receive Mode Operation Timing .......................................................................... 356
Figure 17.16 Block Diagram of Noise Filter .............................................................................. 357
Figure 17.17 Sample Flowchart for Master Transmit Mode....................................................... 358
Figure 17.18 Sample Flowchart for Master Receive Mode ........................................................ 359
Figure 17.19 Sample Flowchart for Slave Transmit Mode......................................................... 360
Figure 17.20 Sample Flowchart for Slave Receive Mode .......................................................... 361
Figure 17.21 The Timing of the Bit Synchronous Circuit .......................................................... 363
Section 18 A/D Converter
Figure 18.1 Block Diagram of A/D Converter ........................................................................... 368
Figure 18.2 A/D Conversion Timing .......................................................................................... 374
Figure 18.3 External Trigger Input Timing ................................................................................ 375
Figure 18.4 A/D Conversion Accuracy Definitions (1) .............................................................. 377
Rev. 3.00 Sep. 10, 2007 Page xxvi of xxxii

Figure 18.5 A/D Conversion Accuracy Definitions (2) .............................................................. 377
Figure 18.6 Analog Input Circuit Example................................................................................. 378
Section 19 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits
Figure 19.1 Block Diagram around BGR ................................................................................... 380
Figure 19.2 Block Diagram of Power-On Reset Circuit and Low-Voltage
Detection Circuit..................................................................................................... 381
Figure 19.3 Operational Timing of Power-On Reset Circuit ...................................................... 387
Figure 19.4 Operating Timing of LVDR Circuit ........................................................................ 388
Figure 19.5 Operational Timing of LVDI Circuit....................................................................... 389
Figure 19.6 Operational Timing of LVDI Circuit
(When Compared Voltage is Input through ExtU and ExtD Pins) ......................... 391
Figure 19.7 Timing of Setting Bits in Reset Source Decision Register ...................................... 392
Section 20 Power Supply Circuit
Figure 20.1 Power Supply Connection of 5.0-V-Specification Microcontrollers....................... 393
Figure 20.2 Power Supply Connection of 3.3-V-Specification Microcontrollers....................... 394
Section 22 Electrical Characteristics
Figure 22.1 System Clock Input Timing..................................................................................... 455
Figure 22.2 RES Low Width Timing.......................................................................................... 455
Figure 22.3 Input Timing............................................................................................................ 455
Figure 22.4 I2C Bus Interface Input/Output Timing ................................................................... 456
Figure 22.5 SCK3 Input Clock Timing....................................................................................... 456
Figure 22.6 SCI Input/Output Timing in Clock Synchronous Mode.......................................... 457
Figure 22.7 Output Load Circuit................................................................................................. 458
Appendix
Figure B.1 Port 1 Block Diagram (P17) ..................................................................................... 489
Figure B.2 Port 1 Block Diagram (P14, P16) ............................................................................. 490
Figure B.7 Port 2 Block Diagram (P24, P23) ............................................................................. 495
Figure B.10 Port 2 Block Diagram (P20) ................................................................................... 498
Figure B.11 Port 3 Block Diagram (P37 to P30) ........................................................................ 499
Figure B.12 Port 5 Block Diagram (P57, P56) ........................................................................... 500
Rev. 3.00 Sep. 10, 2007 Page xxvii of xxxii

Figure B.23 Port B Block Diagram (PB7 and PB6) ................................................................... 510
Figure B.24 Port B Block Diagram (PB5 to PB0) ...................................................................... 510
Figure B.25 Port B Block Diagram (PC1) .................................................................................. 511
Figure B.26 Port B Block Diagram (PC0) .................................................................................. 512
Figure D.1 FP-64K Package Dimensions ................................................................................... 516
Figure D.2 FP-64A Package Dimensions ................................................................................... 517
Rev. 3.00 Sep. 10, 2007 Page xxviii of xxxii

Tables
Section 1 Overview
Table 1.1 Pin Functions ............................................................................................................ 6
Section 2 CPU
Table 2.1 Operation Notation ................................................................................................. 19
Table 2.2 Data Transfer Instructions....................................................................................... 20
Table 2.3 Arithmetic Operations Instructions (1) ................................................................... 21
Table 2.3 Arithmetic Operations Instructions (2) ................................................................... 22
Table 2.4 Logic Operations Instructions................................................................................. 23
Table 2.5 Shift Instructions..................................................................................................... 23
Table 2.6 Bit Manipulation Instructions (1)............................................................................ 24
Table 2.6 Bit Manipulation Instructions (2)............................................................................ 25
Table 2.7 Branch Instructions ................................................................................................. 26
Table 2.8 System Control Instructions.................................................................................... 27
Table 2.9 Block Data Transfer Instructions ............................................................................ 28
Table 2.10 Addressing Modes .................................................................................................. 30
Table 2.11 Absolute Address Access Ranges ........................................................................... 32
Table 2.12 Effective Address Calculation (1)........................................................................... 34
Table 2.12 Effective Address Calculation (2)........................................................................... 35
Table 3.1 Exception Sources and Vector Address .................................................................. 46
Table 3.2 Interrupt Wait States ............................................................................................... 60
Table 4.1 Access and Data Bus Used ..................................................................................... 66
Table 5.1 Crystal Resonator Parameters ................................................................................. 89
Table 6.1 Operating Frequency and Waiting Time................................................................. 96
Table 6.2 Transition Mode after SLEEP Instruction Execution and Transition Mode
due to Interrupt...................................................................................................... 101
Table 6.3 Internal State in Each Operating Mode................................................................. 102
Section 7 ROM
Table 7.1 Setting Programming Modes ................................................................................ 117
Table 7.2 Boot Mode Operation ........................................................................................... 119
Rev. 3.00 Sep. 10, 2007 Page xxix of xxxii

Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit
Rate is Possible ..................................................................................................... 120
Table 7.4 Reprogram Data Computation Table .................................................................... 123
Table 7.5 Additional-Program Data Computation Table ...................................................... 123
Table 7.6 Programming Time ............................................................................................... 123
Table 7.7 Flash Memory Operating States............................................................................ 128
Table 10.1 Pin Configuration.................................................................................................. 168
Table 10.2 Interrupt Sources................................................................................................... 178
Section 11 Timer B1
Table 11.2 Timer B1 Operating Modes .................................................................................. 183
Section 12 Timer V
Table 12.2 Clock Signals to Input to TCNTV and Counting Conditions ............................... 189
Section 13 Timer Z
Table 13.1 Timer Z Functions ................................................................................................ 200
Table 13.3 Initial Output Level of FTIOB0 Pin...................................................................... 235
Table 13.4 Output Pins in Reset Synchronous PWM Mode ................................................... 240
Table 13.5 Register Settings in Reset Synchronous PWM Mode........................................... 240
Table 13.6 Output Pins in Complementary PWM Mode........................................................ 244
Table 13.7 Register Settings in Complementary PWM Mode................................................ 244
Table 13.8 Register Combinations in Buffer Operation ......................................................... 254
Section 15 14-Bit PWM
Table 16.1 Channel Configuration.......................................................................................... 286
Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 297
Table 16.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 300
Table 16.5 Examples of BRR Settings for Various Bit Rates
(Clock Synchronous Mode) (1) ............................................................................ 301
Table 16.5 Examples of BRR Settings for Various Bit Rates
(Clock Synchronous Mode) (2) ............................................................................ 302
Rev. 3.00 Sep. 10, 2007 Page xxx of xxxii

Table 16.6 SSR Status Flags and Receive Data Handling ...................................................... 308
Table 16.7 SCI3 Interrupt Requests........................................................................................ 325
Table 17.1 I2C Bus Interface Pins ........................................................................................... 331
Table 17.2 Transfer Rate......................................................................................................... 334
Table 17.3 Interrupt Requests ................................................................................................. 362
Table 17.4 Time for Monitoring SCL ..................................................................................... 363
Table 18.2 Analog Input Channels and Corresponding ADDR Registers .............................. 370
Table 18.3 A/D Conversion Time (Single Mode)................................................................... 375
Table 19.1 LVDCR Settings and Select Functions ................................................................. 383
Table 19.2 Deciding Reset Source.......................................................................................... 392
Table 22.1 Absolute Maximum Ratings ................................................................................. 415
Table 22.2 DC Characteristics (1)........................................................................................... 419
Table 22.2 DC Characteristics (2)........................................................................................... 424
Table 22.3 AC Characteristics ................................................................................................ 425
Table 22.4 I2C Bus Interface Timing ...................................................................................... 428
Table 22.5 Serial Communication Interface (SCI) Timing..................................................... 429
Table 22.6 A/D Converter Characteristics .............................................................................. 430
Table 22.7 Watchdog Timer Characteristics........................................................................... 431
Table 22.8 Flash Memory Characteristics .............................................................................. 432
Table 22.9 Power-Supply-Voltage Detection Circuit Characteristics..................................... 434
Table 22.10 LVDI External Input Voltage Detection Circuit Characteristics ...................... 434
Table 22.11 Power-On Reset Circuit Characteristics............................................................ 435
Table 22.12 DC Characteristics (1)....................................................................................... 438
Table 22.12 DC Characteristics (2)....................................................................................... 443
Table 22.13 AC Characteristics ............................................................................................ 444
Table 22.14 I2C Bus Interface Timing .................................................................................. 447
Table 22.15 Serial Communication Interface (SCI) Timing ................................................. 448
Table 22.16 A/D Converter Characteristics .......................................................................... 449
Table 22.17 Watchdog Timer Characteristics....................................................................... 450
Table 22.18 Flash Memory Characteristics .......................................................................... 451
Table 22.19 Power-Supply-Voltage Detection Circuit Characteristics................................. 453
Table 22.20 LVDI External Input Voltage Detection Circuit Characteristics ...................... 453
Table 22.21 Power-On Reset Circuit Characteristics............................................................ 454
Rev. 3.00 Sep. 10, 2007 Page xxxi of xxxii

Appendix
Table A.1 Instruction Set ....................................................................................................... 461
Table A.2 Operation Code Map (1) ....................................................................................... 474
Table A.3 Number of Cycles in Each Instruction.................................................................. 478
Table A.4 Number of Cycles in Each Instruction.................................................................. 479
Table A.5 Combinations of Instructions and Addressing Modes .......................................... 488
Rev. 3.00 Sep. 10, 2007 Page xxxii of xxxii

Section 1 Overview
Section 1 Overview
1.1 Features
• High-speed H8/300H CPU with an internal 16-bit architecture
 Upwardly compatible with H8/300 CPU at the object level
 Sixteen 16-bit general registers
 62 basic instructions
• Various peripheral functions
 RTC (can be used as a free running counter)
 Timer B1 (8-bit timer)
 Timer V (8-bit timer)
 Timer Z (16-bit timer)
 14-bit PWM
 Watchdog timer
 SCI (asynchronous or clock synchronous serial communication interface) × 2 channels
 I C bus interface (conforms to the I C bus interface format that is advocated by Philips
2 2
Electronics)
 10-bit A/D converter
 POR/LVD (power-on reset & low-voltage detection circuit)
 On-chip oscillator
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REJ09B0216-0300
Section 1 Overview
• On-chip memory
Product Classification Product Model ROM Size RAM Size Remarks
Flash memory version H8/36079 5.0-V model H8/36079GF HD64F36079G 128 Kbytes 6 Kbytes
TM
(F-ZTAT version) Group
3.3-V model H8/36079LF HD64F36079L
5.0-V model H8/36078GF HD64F36078G 96 Kbytes
3.3-V model H8/36078LF HD64F36078L
H8/36077 5.0-V model H8/36077GF HD64F36077G 56 Kbytes 4 Kbytes

Group
3.3-V model H8/36077LF HD64F36077L
5.0-V model H8/36074GF HD64F36074G 32 Kbytes
3.3-V model H8/36074LF HD64F36074L
• Operating voltage and maximum operating frequency
Operating Maximum
Voltage Operating
Product Classification Product Model Range Frequency Remarks
Flash memory version H8/36079 5.0-V model H8/36079GF HD64F36079G 4.5 V to 5.5 V 20.0 MHz
TM
(F-ZTAT version) Group
3.3-V model H8/36079LF HD64F36079L 3.0 V to 3.6 V 16.0 MHz
5.0-V model H8/36078GF HD64F36078G 4.5 V to 5.5 V 20.0 MHz
H8/36077 5.0-V model H8/36077GF HD64F36077G 4.5 V to 5.5 V 20.0 MHz

Group
5.0-V model H8/36074GF HD64F36074G 4.5 V to 5.5 V 20.0 MHz
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REJ09B0216-0300
Section 1 Overview
• CPU Operating mode and address space
CPU
Address Operating
Product Classification Product Model Space Mode Remarks
Flash memory version H8/36079 5.0-V model H8/36079GF HD64F36079G 16 Mbytes Advanced
TM
(F-ZTAT version) Group mode
3.3-V model H8/36079LF HD64F36079L
5.0-V model H8/36078GF HD64F36078G
3.3-V model H8/36078LF HD64F36078L
H8/36077 5.0-V model H8/36077GF HD64F36077G 64 Kbytes Normal

Group mode
3.3-V model H8/36077LF HD64F36077L
5.0-V model H8/36074GF HD64F36074G
3.3-V model H8/36074LF HD64F36074L
• General I/O ports

 I/O pins: 47 I/O pins, including 8 for large currents (IOL = 20 mA, @VOL = 1.5 V)
 Input-only pins: 8 (also used for analog input)
• I C bus interface (conforms to the I C bus interface format put forward by Philips Electronics)
2 2
• Supports various power-down modes

TM
Note: F-ZTAT is a trademark of Renesas Technology Corp.
• Compact package
Package Code Body Size Pin Pitch

LQFP-64 FP-64K 10.0 × 10.0 mm 0.5 mm
QFP-64 FP-64A 14.0 × 14.0 mm 0.8 mm
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REJ09B0216-0300
Section 1 Overview
1.2 Block Diagram
(OSC1)
(OSC2)
TEST
RES
NMI
VCC
VSS
VCL
X1
X2
External
Subclock On-chip CPU
clock
oscillator oscillator H8/300H
oscillator
P10/TMOW Data bus (lower)

P11/PWM
P12 P67/FTIOD1
Port 1
P14/IRQ0 P66/FTIOC1
P15/IRQ1/TMIB1 P65/FTIOB1
Port 6
RAM P64/FTIOA1
P16/IRQ2
P17/IRQ3/TRGV P63/FTIOD0
ROM
P62/FTIOC0
P20/SCK3 P61/FTIOB0
P21/RXD IIC2 P60/FTIOA0
Port 2
P22/TXD
P23 P76/TMOV
P24 RTC SCI3 P75/TMCIV
Port 7
P30 P74/TMRIV
P31 P72/TXD_2
P32 P71/RXD_2
14-bit PWM SCI3_2
P70/SCK3_2
Port 3
P33
P34
P35 Watchdog
Timer Z
P36 timer
P37 P87
Port 8
P86
P57/SCL Timer V Timer B1 P85
P56/SDA
P55/WKP5/ADTRG
Port 5
P54/WKP4
A/D converter POR&LVD
P53/WKP3
P52/WKP2
P51/WKP1
P50/WKP0 Data bus (upper)
Address bus
Port C Port B
AVCC
PC0/OSC1
PC1/OSC2/CLKOUT
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6/ExtD
PB7/AN7/ExtU
Figure 1.1 Block Diagram of H8/36079 Group and H8/36077 Group
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REJ09B0216-0300
Section 1 Overview
1.3 Pin Arrangement
P70/SCK3_2
P67/FTIOD1
P66/FTIOC1
P62/FTIOC0
P65/FTIOB1
P64/FTIOA1
P60/FTIOA0
P61/FTIOB0
P20/SCK3
P21/RXD
P22/TXD
NMI
P23
P87
P86
P85
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P71/RXD_2 49 32 P63/FTIOD0
P72/TXD_2 50 31 P24
P14/IRQ0 51 30 P76/TMOV
P15/IRQ1/TMIB1 52 29 P75/TMCIV
P16/IRQ2 53 28 P74/TMRIV
P17/IRQ3/TRGV 54 27 P57/SCL
P33 55 26 P56/SDA
H8/36079 Group
P32 56 25 P12
H8/36077 Group
P31 57 24 P11/PWM
Top View
P30 58 23 P10/TMOW
PB3/AN3 59 22 P55/WKP5/ADTRG
PB2/AN2 60 21 P54/WKP4
PB1/AN1 61 20 P53/WKP3
PB0/AN0 62 19 P52/WKP2
PB4/AN4 63 18 P37
PB5/AN5 64 17 P36
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PB6/AN6/ExtD
PB7/AN7/ExtU
AVcc
X2
X1
VCL
RES
TEST
Vss
PC1/OSC2/CLKOUT
PC0/OSC1
Vcc
P50/WKP0
P51/WKP1
P34
P35
Figure 1.2 Pin Arrangement of H8/36079 Group and H8/36077 Group

(FP-64K, FP-64A)
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REJ09B0216-0300
Section 1 Overview
1.4 Pin Functions

Table 1.1 Pin Functions
Pin No.
FP-64K
Type Symbol FP-64A I/O Functions
Power VCC 12 Input Power supply pin. Connect this pin to the
source pins system power supply.
VSS 9 Input Ground pin. Connect this pin to the system
power supply (0V).
AVCC 3 Input Analog power supply pin for the A/D converter.
When the A/D converter is not used, connect
this pin to the system power supply.
VCL 6 Input See section 20, Power Supply Circuit, for a
typical connection.
Clock pins OSC1 11 Input These pins connect with crystal or ceramic
resonator for the system clock, or can be used
OSC2/ 10 Output
CLKOUT to input an external clock. When the on-chip
oscillator is used, the system clock can be
output on OSC2 pin.
See section 5, Clock Pulse Generator, for a
typical connection.
X1 5 Input These pins connect with a 32.768 kHz crystal
resonator for the subclock. See section 5, Clock
X2 4 Output
Pulse Generator, for a typical connection.
System RES 7 Input Reset pin. The pull-up resistor (typ. 150 kΩ) is
control incorporated. When driven low, this LSI is reset.
TEST 8 Input Test pin. Connect this pin to Vss.
Interrupt NMI 35 Input Non-maskable interrupt request input pin. Be
pins sure to pull up by a resistor.
IRQ0 to 51 to 54 Input External interrupt request input pins. Can select
IRQ3 the rising or falling edge.
WKP0 to 13, 14, Input External interrupt request input pins. Can select
WKP5 19 to 22 the rising or falling edge.
RTC TMOW 23 Output This is an output pin for a divided clock.
Timer B1 TMIB1 52 Input External event input pin
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Section 1 Overview
Pin No.
FP-64K
Timer V TMOV 30 Output This is an output pin for a waveform generated
by the output compare function.
TMCIV 29 Input External event input pin
TMRIV 28 Input Counter reset input pin
TRGV 54 Input Counter start trigger input pin
Timer Z FTIOA0 36 I/O Output compare output/input capture
input/external clock input pin
FTIOB0 34 I/O Output compare output/input capture
input/PWM output pin
FTIOC0 33 I/O Output compare output/input capture
input/PWM sync output pin (at a reset,
complementary PWM mode)
FTIOD0 32 I/O Output compare output/input capture
input/PWM output pin
FTIOA1 37 I/O Output compare output/input capture
input/PWM output pin (at a reset,
complementary PWM mode)
FTIOB1 to 38 to 40 I/O Output compare output/input capture
FTIOD1 input/PWM output pin
14-bit PWM PWM 24 Output 14-bit PWM square wave output pin
2 2
I C bus SDA 26 I/O I C data I/O pin. Can directly drive a bus by
interface 2 NMOS open-drain output. When using this pin,
(IIC2) external pull-up resistor is required.
2
SCL 27 I/O I C clock I/O pin. Can directly drive a bus by
NMOS open-drain output. When using this pin,
external pull-up resistor is required.
Serial com- TXD, 46, 50 Output Transmit data output pin
munication TXD_2
interface 3
RXD, 45, 49 Input Receive data input pin
(SCI3) RXD_2
SCK3, 44, 48 I/O Clock I/O pin
SCK3_2
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REJ09B0216-0300
Section 1 Overview
Pin No.
FP-64K
A/D AN7 to AN0 2, 1 Input Analog input pin
converter 64, 63
59 to 62
ADTRG 22 Input A/D conversion start trigger input pin
I/O ports PB7 to PB0 2, 1 Input 8-bit input port
64, 63
59 to 62
PC1, PC0 10, 11 I/O 2-bit I/O port
P17 to P14, 54 to 51, I/O 7-bit I/O port
P12 to P10 25 to 23
P24 to P20 31, 47 to 44 I/O 5-bit I/O port
P37 to P30 18 to 15, I/O 8-bit I/O port
55 to 58
P57 to P50 27, 26 I/O 8-bit I/O port
22 to 19
14, 13
P67 to P60 40 to 37 I/O 8-bit I/O port
32 to 34, 36
P76 to P74, 30 to 28, I/O 6-bit I/O port
P72 to P70 50 to 48
P87 to P85 43 to 41 I/O 3-bit I/O port
Low-voltage ExtU, ExtD 2, 1 Input This pin is used to externally input the
detection detection voltage for the low-voltage detection
circuit circuit.
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REJ09B0216-0300
Section 2 CPU
Section 2 CPU
Microcontrollers of the H8/36079 Group and H8/36077 Group have an H8/300H CPU with an
internal 32-bit architecture that provides upward compatibility with the H8/300CPU. Products of
the H8/36079 Group support an advanced mode with a 16-Mbyte address space while those of the
H8/36077 Group support a normal mode with a 64-Kbyte address space.
• Upward compatibility with H8/300 CPUs

 Can execute object programs for H8/300 CPUs
 Additional eight 16-bit extended registers
 32-bit transfer and arithmetic and logic instructions are added
 Signed multiply and divide instructions are added.
• General-register architecture
 Sixteen 16-bit general registers also usable as sixteen 8-bit registers and eight 16-bit
registers, or eight 32-bit registers
• Sixty-two basic instructions
 8/16/32-bit data transfer and arithmetic and logic instructions
 Multiply and divide instructions
 Powerful bit-manipulation instructions
• Eight addressing modes
 Register direct [Rn]
 Register indirect [@ERn]
 Register indirect with displacement [@(d:16,ERn) or @(d:24,ERn)]
 Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
 Absolute address [@aa:8, @aa:16, @aa:24]
 Immediate [#xx:8, #xx:16, or #xx:32]
 Program-counter relative [@(d:8,PC) or @(d:16,PC)]
 Memory indirect [@@aa:8]
• Address space
 H8/36079 Group: 16 Mbytes
 H8/36077 Group: 64 Kbytes
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REJ09B0216-0300
Section 2 CPU
• High-speed operation
 All frequently-used instructions execute in one or two states
 8/16/32-bit register-register add/subtract: 2 state
 8 × 8-bit register-register multiply: 14 states
 16 ÷ 8-bit register-register divide: 14 states
 16 × 16-bit register-register multiply: 22 states
 32 ÷ 16-bit register-register divide: 22 states
• CPU operating mode
 H8/36079 Group: Advanced mode
 H8/36077 Group: Normal mode
• Power-down state
 Transition to power-down state by SLEEP instruction
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Section 2 CPU
2.1 Address Space and Memory Map

Figure 2.1 shows the memory map of the address space of H8/36079 Group and H8/36077 Group.
HD64F36079G HD64F36078G HD64F36077G HD64F36074G

HD64F36079L HD64F36078L HD64F36077L HD64F36074L
(Flash memory version) (Flash memory version) (Flash memory version) (Flash memory version)
H'000000 H'000000 H'0000 H'0000
H'00008B Interrupt vector H'00008B Interrupt vector H'0045 Interrupt vector H'0045 Interrupt vector
H'00008C H'00008C H'0046 H'0046
On-chip ROM
(32 kbytes)
On-chip ROM On-chip ROM On-chip ROM

(128 kbytes) (96 kbytes) (56 kbytes)
H'7FFF
H'01EFFF H'CFFF
H'01F000 H'D000 Not used
On-chip emulator On-chip emulator
firmware area firmware area
H'01FFFF (4 kbytes) H'017FFF H'DFFF (4 kbytes)
Not used Not used Not used
H'FFE000 H'FFE000 H'E800 H'E800
On-chip RAM On-chip RAM On-chip RAM On-chip RAM

(4 kbytes) (4 kbytes) (2 kbytes) (2 kbytes)
H'FFEFFF H'FFEFFF H'EFFF H'EFFF

Not used Not used Not used Not used
H'FFF700 H'FFF700 H'F700 H'F700
Internal I/O register Internal I/O register Internal I/O register Internal I/O register
H'FFF77F H'FFF77F H'F77F H'F77F
H'FFF780 (1-kbyte working area H'FFF780 (1-kbyte working area H'F780 (1-kbyte working area H'F780 (1-kbyte working area
for flash memory for flash memory for flash memory for flash memory
programming) programming) programming) programming)
H'FFFB7F On-chip RAM H'FFFB7F On-chip RAM H'FB7F On-chip RAM H'FB7F On-chip RAM
H'FFFB80 (2 kbytes) H'FFFB80 (2 kbytes) H'FB80 (2 kbytes) H'FB80 (2 kbytes)
(1-kbyte user area) (1-kbyte user area) (1-kbyte user area) (1-kbyte user area)
H'FFFF7F H'FFFF7F H'FF7F H'FF7F
H'FFFF80 H'FFFF80 H'FF80 H'FF80
Internal I/O register Internal I/O register Internal I/O register Internal I/O register
H'FFFFFF H'FFFFFF H'FFFF H'FFFF
Figure 2.1 Memory Map
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REJ09B0216-0300
Section 2 CPU
2.2 Register Configuration

The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers;
general registers and control registers. The control registers are a 24-bit program counter (PC), and
an 8-bit condition-code register (CCR).
General Registers (ERn)

15 0 7 0 7 0
ER0 E0 R0H R0L
ER1 E1 R1H R1L
ER2 E2 R2H R2L
ER3 E3 R3H R3L
ER4 E4 R4H R4L
ER5 E5 R5H R5L
ER6 E6 R6H R6L
ER7 E7 (SP) R7H R7L
Control Registers (CR)

23 0
PC
7 6 5 4 3 2 1 0
CCR I UI H U N Z V C
[Legend]
SP: Stack pointer H: Half-carry flag
PC: Program counter U: User bit
CCR: Condition-code register N: Negative flag
I: Interrupt mask bit Z: Zero flag
UI: User bit V: Overflow flag
C: Carry flag
Figure 2.2 CPU Registers
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REJ09B0216-0300
Section 2 CPU
2.2.1 General Registers
The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally
identical and can be used as both address registers and data registers. The general registers are
available for use as 32-, 16-, and 8-bit data registers. Figure 2.3 illustrates the usage of the general
registers. When the general registers are used as 32-bit registers or address registers, they are
designated by the letters ER (ER0 to ER7).
The ER registers are divided into 16-bit general registers designated by the letters E (E0 to E7)
and R (R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-
bit registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers are divided into 8-bit registers designated by the letters RH (R0H to R7H) and RL
(R0L to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8-bit
registers.
The usage of each register can be selected independently.
• Address registers • 16-bit registers • 8-bit registers

• 32-bit registers
E registers (extended registers)

(E0 to E7)
ER registers RH registers
(ER0 to ER7) (R0H to R7H)
R registers
(R0 to R7)
RL registers
(R0L to R7L)
Figure 2.3 Usage of General Registers
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.4 shows the
relationship between the stack pointer and the stack area.
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REJ09B0216-0300
Section 2 CPU
Empty area
SP (ER7)
Stack area
Figure 2.4 Relationship between Stack Pointer and Stack Area
2.2.2 Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched, the least significant PC bit is regarded as 0). The PC is initialized when the
start address is loaded by the vector address generated during reset exception-handling sequence.
2.2.3 Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. The I bit is initialized to 1
by reset exception-handling sequence, but other bits are not initialized.
Some instructions leave flag bits unchanged. Operations can be performed on the CCR bits by the
LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching
conditions for conditional branch (Bcc) instructions.
For the action of each instruction on the flag bits, see appendix A.1, Instruction List.
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Section 2 CPU
Initial
Bit Bit Name Value R/W Description
7 I 1 R/W Interrupt Mask Bit
Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set
to 1 at the start of an exception-handling sequence.
6 UI Undefined R/W User Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions.
5 H Undefined R/W Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B,
or NEG.B instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or
NEG.W instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 11, and cleared to 0
otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L
instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 27, and cleared to 0 otherwise.
4 U Undefined R/W User Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions.
3 N Undefined R/W Negative Flag
Stores the value of the most significant bit of data as a
sign bit.
2 Z Undefined R/W Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.
1 V Undefined R/W Overflow Flag
Set to 1 when an arithmetic overflow occurs, and
cleared to 0 at other times.
0 C Undefined R/W Carry Flag
Set to 1 when a carry occurs, and cleared to 0
otherwise. Used by:
• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions, to indicate a carry
The carry flag is also used as a bit accumulator by bit
manipulation instructions.
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Section 2 CPU
2.3 Data Formats

The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.
2.3.1 General Register Data Formats
Figure 2.5 shows the data formats in general registers.
Data Type General Register Data Format

7 0
RnH
1-bit data 7 6 5 4 3 2 1 0 Don't care
7 0
RnL Don't care 7 6 5 4 3 2 1 0
1-bit data
7 4 3 0
4-bit BCD data RnH Upper Lower Don't care
7 4 3 0
4-bit BCD data RnL Don't care Upper Lower
7 0
Byte data RnH Don't care
MSB LSB
7 0
Byte data RnL Don't care
MSB LSB
Figure 2.5 General Register Data Formats (1)
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REJ09B0216-0300
Section 2 CPU
Data Type General Data Format

Register
Word data Rn
15 0
Word data En MSB LSB
15 0
MSB LSB
Longword ERn
data 31 16 15 0
MSB LSB
[Legend]
ERn: General register ER
En: General register E
Rn: General register R
RnH: General register RH
RnL: General register RL
MSB: Most significant bit
LSB: Least significant bit
Figure 2.5 General Register Data Formats (2)
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REJ09B0216-0300
Section 2 CPU
2.3.2 Memory Data Formats
Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and
longword data in memory, however word or longword data must begin at an even address. If an
attempt is made to access word or longword data at an odd address, an address error does not
occur, however the least significant bit of the address is regarded as 0, so access begins the
preceding address. This also applies to instruction fetches.
When ER7 (SP) is used as an address register to access the stack area, the operand size should be
word or longword.
Data Type Address Data Format
7 0
1-bit data Address L 7 6 5 4 3 2 1 0
Byte data Address L MSB LSB
Word data Address 2M MSB
Address 2M+1 LSB
Longword data Address 2N MSB

Address 2N+1
Address 2N+2
Address 2N+3 LSB
Figure 2.6 Memory Data Formats
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REJ09B0216-0300
Section 2 CPU
2.4 Instruction Set
2.4.1 Table of Instructions Classified by Function
The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each
functional category. The notation used in tables 2.2 to 2.9 is defined below.
Table 2.1 Operation Notation
Symbol Description
Rd General register (destination)*
Rs General register (source)*
Rn General register*
ERn General register (32-bit register or address register)
(EAd) Destination operand
(EAs) Source operand
CCR Condition-code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (overflow) flag in CCR
C C (carry) flag in CCR
PC Program counter
SP Stack pointer
#IMM Immediate data
disp Displacement
+ Addition
– Subtraction
× Multiplication
÷ Division
∧ Logical AND
∨ Logical OR
⊕ Logical XOR
→ Move
∼ NOT (logical complement)
:3/:8/:16/:24 3-, 8-, 16-, or 24-bit length
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REJ09B0216-0300
Section 2 CPU
Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers/address register (ER0 to ER7).
Table 2.2 Data Transfer Instructions
Instruction Size* Function

MOV B/W/L (EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.
MOVFPE B (EAs) → Rd
Cannot be used in this LSI.
MOVTPE B Rs → (EAs)
Cannot be used in this LSI.
POP W/L @SP+ → Rn
Pops a general register from the stack. POP.W Rn is identical to
MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.
PUSH W/L Rn → @–SP
Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP.
Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword
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Table 2.3 Arithmetic Operations Instructions (1)

ADD B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd
SUB Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register (immediate byte data
cannot be subtracted from byte data in a general register. Use the
SUBX or ADD instruction.)
ADDX B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
SUBX Performs addition or subtraction with carry on byte data in two general
registers, or on immediate data and data in a general register.
INC B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd
DEC Increments or decrements a general register by 1 or 2. (Byte operands
can be incremented or decremented by 1 only.)
ADDS L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
SUBS Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.
DAA B Rd (decimal adjust) → Rd
DAS Decimal-adjusts an addition or subtraction result in a general register by
referring to the CCR to produce 4-bit BCD data.
MULXU B/W Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers: either
8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
MULXS B/W Rd × Rs → Rd
Performs signed multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
DIVXU B/W Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either 16
bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits →
16-bit quotient and 16-bit remainder.
B: Byte
W: Word
L: Longword
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Table 2.3 Arithmetic Operations Instructions (2)

DIVXS B/W Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits
÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder.
CMP B/W/L Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general
register or with immediate data, and sets CCR bits according to the
result.
NEG B/W/L 0 – Rd → Rd
Takes the two's complement (arithmetic complement) of data in a
general register.
EXTU W/L Rd (zero extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by padding with zeros on the
left.
EXTS W/L Rd (sign extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by extending the sign bit.
B: Byte
W: Word
L: Longword
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Table 2.4 Logic Operations Instructions

AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT B/W/L ∼(Rd) → (Rd)
Takes the one's complement (logical complement) of general register
contents.
B: Byte
W: Word
L: Longword
Table 2.5 Shift Instructions

SHAL B/W/L Rd (shift) → Rd
SHAR Performs an arithmetic shift on general register contents.
SHLL B/W/L Rd (shift) → Rd
SHLR Performs a logical shift on general register contents.
ROTL B/W/L Rd (rotate) → Rd
ROTR Rotates general register contents.
ROTXL B/W/L Rd (rotate) → Rd
ROTXR Rotates general register contents through the carry flag.
B: Byte
W: Word
L: Longword
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Table 2.6 Bit Manipulation Instructions (1)

BSET B 1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory operand to 1. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BCLR B 0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0. The
bit number is specified by 3-bit immediate data or the lower three bits of
a general register.
BNOT B ∼(<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BTST B ∼(<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand and sets
or clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower three bits of a general register.
BAND B C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIAND B C ∧ ¬ (<bit-No.> of <EAd>) → C
ANDs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BOR B C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general register or memory
BIOR B C ∨ ∼(<bit-No.> of <EAd>) → C
ORs the carry flag with the inverse of a specified bit in a general register
or memory operand and stores the result in the carry flag.
B: Byte
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Table 2.6 Bit Manipulation Instructions (2)

BXOR B C ⊕ (<bit-No.> of <EAd>) → C
XORs the carry flag with a specified bit in a general register or memory
BIXOR B C ⊕ ∼(<bit-No.> of <EAd>) → C
XORs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
BLD B (<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to the
carry flag.
BILD B ∼(<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
BST B C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or
memory operand.
BIST B ∼C → (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a
general register or memory operand.
B: Byte
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Table 2.7 Branch Instructions
Instruction Size Function

Bcc*  Branches to a specified address if a specified condition is true. The
branching conditions are listed below.
Mnemonic Description Condition
BRA(BT) Always (true) Always
BRN(BF) Never (false) Never
BHI High C∨Z=0
BLS Low or same C∨Z=1
BCC(BHS) Carry clear C=0
(high or same)
BCS(BLO) Carry set (low) C=1
BNE Not equal Z=0
BEQ Equal Z=1
BVC Overflow clear V=0
BVS Overflow set V=1
BPL Plus N=0
BMI Minus N=1
BGE Greater or equal N⊕V=0
BLT Less than N⊕V=1
BGT Greater than Z∨(N ⊕ V) = 0
BLE Less or equal Z∨(N ⊕ V) = 1
JMP  Branches unconditionally to a specified address.

BSR  Branches to a subroutine at a specified address.
JSR  Branches to a subroutine at a specified address.
RTS  Returns from a subroutine
Note: * Bcc is the general name for conditional branch instructions.
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Table 2.8 System Control Instructions

TRAPA  Starts trap-instruction exception handling.
RTE  Returns from an exception-handling routine.
SLEEP  Causes a transition to a power-down state.
LDC B/W (EAs) → CCR
Moves the source operand contents to the CCR. The CCR size is one
byte, but in transfer from memory, data is read by word access.
STC B/W CCR → (EAd)
Transfers the CCR contents to a destination location. The condition
code register size is one byte, but in transfer to memory, data is written
by word access.
ANDC B CCR ∧ #IMM → CCR
Logically ANDs the CCR with immediate data.
ORC B CCR ∨ #IMM → CCR
Logically ORs the CCR with immediate data.
XORC B CCR ⊕ #IMM → CCR
Logically XORs the CCR with immediate data.
NOP  PC + 2 → PC
Only increments the program counter.
B: Byte
W: Word
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Table 2.9 Block Data Transfer Instructions
Instruction Size Function

EEPMOV.B  if R4L ≠ 0 then
Repeat @ER5+ → @ER6+,
R4L–1 → R4L
Until R4L = 0
else next;
EEPMOV.W  if R4 ≠ 0 then
Repeat @ER5+ → @ER6+,
R4–1 → R4
Until R4 = 0
else next;
Transfers a data block. Starting from the address set in ER5, transfers
data for the number of bytes set in R4L or R4 to the address location set
in ER6.
Execution of the next instruction begins as soon as the transfer is
completed.
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2.4.2 Basic Instruction Formats
H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an

operation field (op), a register field (r), an effective address extension (EA), and a condition field
(cc).
Figure 2.7 shows examples of instruction formats.
• Operation Field
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.
• Register Field
Specifies a general register. Address registers are specified by 3 bits, and data registers by 3
bits or 4 bits. Some instructions have two register fields. Some have no register field.
• Effective Address Extension
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A24-bit
address or displacement is treated as a 32-bit data in which the first 8 bits are 0 (H'00).
• Condition Field
Specifies the branching condition of Bcc instructions.
(1) Operation field only
op NOP, RTS, etc.
(2) Operation field and register fields
op rn rm ADD.B Rn, Rm, etc.
(3) Operation field, register fields, and effective address extension
op rn rm
MOV.B @(d:16, Rn), Rm
EA(disp)
(4) Operation field, effective address extension, and condition field
op cc EA(disp) BRA d:8
Figure 2.7 Instruction Formats
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2.5 Addressing Modes and Effective Address Calculation
2.5.1 Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses
a subset of these addressing modes. Addressing modes that can be used differ depending on the
instruction. For details, refer to appendix A.4, Combinations of Instructions and Addressing
Modes.
Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer
instructions can use all addressing modes except program-counter relative and memory indirect.
Bit-manipulation instructions use register direct, register indirect, or the absolute addressing mode
(@aa:8) to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions)
or immediate (3-bit) addressing mode to specify a bit number in the operand.
Table 2.10 Addressing Modes
No. Addressing Mode Symbol

1 Register direct Rn
2 Register indirect @ERn
3 Register indirect with displacement @(d:16,ERn)/@(d:24,ERn)
4 Register indirect with post-increment @ERn+
Register indirect with pre-decrement @–ERn
5 Absolute address @aa:8/@aa:16/@aa:24
6 Immediate #xx:8/#xx:16/#xx:32
7 Program-counter relative @(d:8,PC)/@(d:16,PC)
8 Memory indirect @@aa:8
(1) Register DirectRn
The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the
operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7
can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
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(2) Register Indirect@ERn
The register field of the instruction code specifies an address register (ERn), the lower 24 bits of
which contain the address of the operand on memory.
(3) Register Indirect with Displacement@(d:16, ERn) or @(d:24, ERn)
A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn)
specified by the register field of the instruction, and the lower 24 bits of the sum the address of a
memory operand. A 16-bit displacement is sign-extended when added.
(4) Register Indirect with Post-Increment or Pre-Decrement@ERn+ or @-ERn
(a) Register indirect with post-increment@ERn+
The register field of the instruction code specifies an address register (ERn) the lower 24 bits
of which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is
added to the address register contents (32 bits) and the sum is stored in the address register.
The value added is 1 for byte access, 2 for word access, or 4 for longword access. For the word
or longword access, the register value should be even.
(b) Register indirect with pre-decrement@-ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instruction code, and the lower 24 bits of the result is the address of a memory operand.
The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for
word access, or 4 for longword access. For the word or longword access, the register value
should be even.
(5) Absolute Address@aa:8, @aa:16, @aa:24
The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24)
For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit
absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the
entire address space.
Table 2.11 shows the access ranges of absolute addresses according to the modes of operation of
each product group.
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Table 2.11 Absolute Address Access Ranges
Absolute Address Normal Mode Advanced Mode

8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF
16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF
H'FF8000 to H'FFFFFF
24 bits (@aa:24) H'0000 to H'FFFF H'000000 to H'FFFFFF
(6) Immediate#xx:8, #xx:16, or #xx:32
The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an
operand.
The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit
number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a
vector address.
(7) Program-Counter Relative@(d:8, PC) or @(d:16, PC)
This mode is used in the BSR instruction. An 8-bit or 16-bit displacement contained in the
instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. The
PC value to which the displacement is added is the address of the first byte of the next instruction,
so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768
bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an
even number.
(8) Memory Indirect@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand. This memory operand contains a branch address.
The memory operand is accessed by longword access. The first byte of the memory operand is
ignored, generating a 24-bit branch address. Figure 2.8 shows how to specify branch address for in
memory indirect mode. The upper bits of the absolute address are all assumed to be 0, so the
address range is 0 to 255 (H'0000 to H'00FF).
Note that the first part of the address range is also the exception vector area.
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Specified Dummy
by @aa:8
Branch address
Figure 2.8 Branch Address Specification in Memory Indirect Mode
2.5.2 Effective Address Calculation
Table 2.12 indicates how effective addresses are calculated in each addressing mode. For
operation in normal mode, the upper 8 bits of the effective address are ignored in order to generate
a 16-bit effective address. For operation in advanced mode, the 24-bit result of effective address
calculation is generated as the address.
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Table 2.12 Effective Address Calculation (1)
No Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)
1 Register direct(Rn)
Operand is general register contents.
op rm rn
2 Register indirect(@ERn) 31 0 23 0
General register contents
op r
3 Register indirect with displacement

@(d:16,ERn) or @(d:24,ERn) 31 0
23 0
op r disp
31 0
Sign extension disp
4 Register indirect with post-increment or

pre-decrement 31 0 23 0
•Register indirect with post-increment @ERn+
op r 1, 2, or 4
•Register indirect with pre-decrement @-ERn 31 0

23 0
op r 1, 2, or 4
The value to be added or subtracted is 1 when the

operand is byte size, 2 for word size, and 4 for
longword size.
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Table 2.12 Effective Address Calculation (2)
No Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)
5 Absolute address
@aa:8 23 8 7 0
op abs H'FFFF
@aa:16 23 16 15 0
op abs Sign extension
@aa:24
op 23 0
abs
6 Immediate
#xx:8/#xx:16/#xx:32
Operand is immediate data.
op IMM
7 Program-counter relative 23 0
@(d:8,PC) @(d:16,PC) PC contents
op disp 23 0
Sign
extension disp
23 0
8 Memory indirect @@aa:8
23 8 7 0
op abs
H'0000 abs
15 0 23 16 15 0
Memory contents H'00
[Legend]
r, rm,rn : Register field
op : Operation field
disp : Displacement
IMM : Immediate data
abs : Absolute address
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2.6 Basic Bus Cycle

CPU operation is synchronized by a system clock (φ) or a subclock (φSUB). The period from a rising
edge of φ or φSUB to the next rising edge is called one state. A bus cycle consists of two states or
three states. The cycle differs depending on whether access is to on-chip memory or to on-chip
peripheral modules.
2.6.1 Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2.9 shows the on-chip memory access cycle.
Bus cycle
T1 state T2 state
ø or ø SUB
Internal address bus Address
Internal read signal
Internal data bus

Read data
(read access)
Internal write signal
Internal data bus

Write data
(write access)
Figure 2.9 On-Chip Memory Access Cycle
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2.6.2 On-Chip Peripheral Modules
On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits
or 16 bits depending on the register. For description on the data bus width and number of
accessing states of each register, refer to section 21.1, Register Addresses (Address Order).
Registers with 16-bit data bus width can be accessed by word size only. Registers with 8-bit data
bus width can be accessed by byte or word size. When a register with 8-bit data bus width is
accessed by word size, a bus cycle occurs twice. In two-state access, the operation timing is the
same as that for on-chip memory.
Figure 2.10 shows the operation timing in the case of three-state access to an on-chip peripheral
module.
Bus cycle
T1 state T2 state T3 state
φ or φ SUB
Internal Address
address bus
Internal
read signal
Internal
data bus Read data
(read access)
Internal
write signal
Internal
data bus Write data
(write access)
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)
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2.7 CPU States

There are four CPU states: the reset state, program execution state, program halt state, and
exception-handling state. The program execution state includes active mode and subactive mode.
For the program halt state, there are a sleep mode, standby mode, and sub-sleep mode. These
states are shown in figure 2.11. Figure 2.12 shows the state transitions. For details on program
execution state and program halt state, refer to section 6, Power-Down Modes. For details on
exception processing, refer to section 3, Exception Handling.
CPU state Reset state
The CPU is initialized

Program Active
execution state (high speed) mode
The CPU executes successive program
instructions at high speed,
synchronized by the system clock
Subactive mode
The CPU executes

successive program
instructions at reduced
speed, synchronized
by the subclock
Power-down
modes
Program halt state Sleep mode
A state in which some

or all of the chip
Standby mode
functions are stopped
to conserve power
Subsleep mode
Exception-
handling state
A transient state in which the CPU changes
the processing flow due to a reset or an interrupt
Figure 2.11 CPU Operation States
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Reset cleared
Reset state Exception-handling state
Reset occurs
Reset Interrupt
occurs source
Reset Interrupt Exception-
occurs source handling
complete
Program halt state Program execution state

SLEEP instruction executed
Figure 2.12 State Transitions
2.8 Usage Notes
2.8.1 Notes on Data Access to Empty Areas
The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip
I/O registers areas available to the user. When data is transferred from CPU to empty areas, the
transferred data will be lost. This action may also cause the CPU to malfunction. When data is
transferred from an empty area to CPU, the contents of the data cannot be guaranteed.
2.8.2 EEPMOV Instruction
EEPMOV is a block-transfer instruction and transfers the number of bytes indicated by R4L and
starting at the address indicated by R5 to the address indicated by R6. In products for normal-
mode operation, set R4L and R6 so that the final address at the destination for transfer (value of
R6 + R4L) does not exceed H'FFFF (the value of R6 must not change from H'FFFF to H'0000
during execution). In products for advanced-mode operation, set R4L and R6 so that the final
address at the destination for transfer (value of R6 + R4L) does not exceed H'FFFFFF (the value
of R6 must not change from H'FFFFFF to H'000000 during execution).
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2.8.3 Bit-Manipulation Instruction
The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in
byte units, manipulate the data of the target bit, and write data to the same address again in byte
units. Special care is required when using these instructions in cases where two registers are
assigned to the same address, or when a bit is directly manipulated for a port or a register
containing a write-only bit, because this may rewrite data of a bit other than the bit to be
manipulated.
(1) Bit Manipulation for Two Registers Assigned to the Same Address
Example 1: Bit manipulation for the timer load register and timer counter
(Applicable for timer B1 in the H8/36079 Group and H8/36077 Group.)
Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same
address. When a bit-manipulation instruction accesses the timer load register and timer counter of
a reloadable timer, since these two registers share the same address, the following operations takes
place.
1. Data is read in byte units.

2. The CPU sets or resets the bit to be manipulated with the bit-manipulation instruction.
3. The written data is written again in byte units to the timer load register.
The timer is counting, so the value read is not necessarily the same as the value in the timer load
register. As a result, bits other than the intended bit in the timer counter may be modified and the
modified value may be written to the timer load register.
Read
Count clock Timer counter
Reload
Write
Timer load register
Internal data bus
Figure 2.13 Example of Timer Configuration with Two Registers

Allocated to Same Address
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Example 2: The BSET instruction is executed for port 5.
P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at
P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level
signal at P50 with a BSET instruction is shown below.
• Prior to executing BSET instruction

P57 P56 P55 P54 P53 P52 P51 P50
Input/output Input Input Output Output Output Output Output Output
Pin state Low High Low Low Low Low Low Low
level level level level level level level level
PCR5 0 0 1 1 1 1 1 1
PDR5 1 0 0 0 0 0 0 0
• BSET instruction executed instruction

BSET #0, @PDR5 The BSET instruction is executed for port 5.
• After executing BSET instruction

P57 P56 P55 P54 P53 P52 P51 P50
Pin state Low High Low Low Low Low Low High
PCR5 0 0 1 1 1 1 1 1
PDR5 0 1 0 0 0 0 0 1
• Description on operation
1. When the BSET instruction is executed, first the CPU reads port 5.
Since P57 and P56 are input pins, the CPU reads the pin states (low-level and high-level
input).
P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a
value of H'80, but the value read by the CPU is H'40.
2. Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41.
3. Finally, the CPU writes H'41 to PDR5, completing execution of BSET instruction.
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Section 2 CPU
As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level
signal. However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem,
store a copy of the PDR5 data in a work area in memory. Perform the bit manipulation on the
data in the work area, then write this data to PDR5.
• Prior to executing BSET instruction

MOV.B #80, R0L The PDR5 value (H'80) is written to a work area in
MOV.B R0L, @RAM0 memory (RAM0) as well as to PDR5.
MOV.B R0L, @PDR5
P57 P56 P55 P54 P53 P52 P51 P50

PCR5 0 0 1 1 1 1 1 1
PDR5 1 0 0 0 0 0 0 0
RAM0 1 0 0 0 0 0 0 0
• BSET instruction executed

BSET #0, @RAM0 The BSET instruction is executed designating the PDR5
work area (RAM0).
• After executing BSET instruction

MOV.B @RAM0, R0L The work area (RAM0) value is written to PDR5.
MOV.B R0L, @PDR5
P57 P56 P55 P54 P53 P52 P51 P50

PCR5 0 0 1 1 1 1 1 1
PDR5 1 0 0 0 0 0 0 1
RAM0 1 0 0 0 0 0 0 1
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Section 2 CPU
(2) Bit manipulation in a register containing a write-only bit
Example 3: BCLR instruction executed designating port 5 control register PCR5
P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at
P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as
an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be
input to this input pin.
• Prior to executing BCLR instruction

P57 P56 P55 P54 P53 P52 P51 P50
PCR5 0 0 1 1 1 1 1 1
PDR5 1 0 0 0 0 0 0 0
• BCLR instruction executed

BCLR #0, @PCR5 The BCLR instruction is executed for PCR5.
• After executing BCLR instruction

P57 P56 P55 P54 P53 P52 P51 P50
Input/output Output Output Output Output Output Output Output Input
PCR5 1 1 1 1 1 1 1 0
PDR5 1 0 0 0 0 0 0 0
• Description on operation
1. When the BCLR instruction is executed, first the CPU reads PCR5. Since PCR5 is a write-only
register, the CPU reads a value of H'FF, even though the PCR5 value is actually H'3F.
2. Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE.
3. Finally, H'FE is written to PCR5 and BCLR instruction execution ends.
As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However,
bits 7 and 6 in PCR5 change to 1, so that P57 and P56 change from input pins to output pins.
To prevent this problem, store a copy of the PDR5 data in a work area in memory and
manipulate data of the bit in the work area, then write this data to PDR5.
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Section 2 CPU
• Prior to executing BCLR instruction

MOV.B #3F, R0L The PCR5 value (H'3F) is written to a work area in
MOV.B R0L, @RAM0 memory (RAM0) as well as to PCR5.
MOV.B R0L, @PCR5
P57 P56 P55 P54 P53 P52 P51 P50

PCR5 0 0 1 1 1 1 1 1
PDR5 1 0 0 0 0 0 0 0
RAM0 0 0 1 1 1 1 1 1
• BCLR instruction executed

BCLR #0, @RAM0 The BCLR instructions executed for the PCR5 work area
(RAM0).
• After executing BCLR instruction

MOV.B @RAM0, R0L The work area (RAM0) value is written to PCR5.
MOV.B R0L, @PCR5
P57 P56 P55 P54 P53 P52 P51 P50

PCR5 0 0 1 1 1 1 1 0
PDR5 1 0 0 0 0 0 0 0
RAM0 0 0 1 1 1 1 1 0
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Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts.
• Reset
A reset has the highest exception priority. Exception handling starts as soon as the reset is
cleared by the RES pin. The chip is also reset when the watchdog timer overflows, and
exception handling starts. Exception handling is the same as exception handling by the RES
pin.
• Trap Instruction
Exception handling starts when a trap instruction (TRAPA) is executed. The TRAPA
instruction generates a vector address corresponding to a vector number from 0 to 3, as
specified in the instruction code. Exception handling can be executed at all times in the
program execution state, regardless of the setting of the I bit in CCR.
• Interrupts
External interrupts other than NMI and internal interrupts other than address break are masked
by the I bit in CCR, and kept masked while the I bit is set to 1. Exception handling starts when
the current instruction or exception handling ends, if an interrupt request has been issued.
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3.1 Exception Sources and Vector Address

Table 3.1 shows the vector addresses and priority of each exception handling. When more than
one interrupt is requested, handling is performed from the interrupt with the highest priority.
Table 3.1 Exception Sources and Vector Address
Vector
Relative Module Exception Sources Number Normal Mode Advanced Mode Priority
RES pin Reset 0 H'0000 to H'0001 H'000000 to H'000003 High
Watchdog timer
 Reserved for system use 1 to 6 H'0002 to H'000D H'000004 to H'00001B
External interrupt NMI 7 H'000E to H'000F H'00001C to H'00001F

pin
CPU Trap instruction #0 8 H'0010 to H'0011 H'000020 to H'000023
Trap instruction #1 9 H'0012 to H'0013 H'000024 to H'000027
Trap instruction #2 10 H'0014 to H'0015 H'000028 to H'00002B
Trap instruction #3 11 H'0016 to H'0017 H'00002C to H'00002F
Address break Break conditions satisfied 12 H'0018 to H'0019 H'000030 to H'000033
CPU Direct transition by 13 H'001A to H'001B H'000034 to H'000037

executing the SLEEP
instruction
External interrupt IRQ0 14 H'001C to H'001D H'000038 to H'00003B
pin Low-voltage detection
interrupt
IRQ1 15 H'001E to H'001F H'00003C to H'00003F
IRQ2 16 H'0020 to H'0021 H'000040 to H'000043
IRQ3 17 H'0022 to H'0023 H'000044 to H'000047
WKP 18 H'0024 to H'0025 H'000048 to H'00004B
RTC Overflow 19 H'0026 to H'0027 H'00004C to H'0004F

Low
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Vector
Relative Module Exception Sources Number Normal Mode Advanced Mode Priority
 Reserved for system use 20 H'0028 to H'0029 H'000050 to H'000057 High
Timer V Timer V compare match 22 H'002C to H'002D H'000058 to H'00005B
A
Timer V compare match
B
Timer V overflow
SCI3 SCI3 receive data full 23 H'002E to H'002F H'00005C to H'00005F
SCI3 transmit data empty
SCI3 transmit end
SCI3 receive error
IIC2 Transmit data empty 24 H'0030 to H'0031 H'000060 to H'000063
Transmit end
Receive data full
Arbitration lost/Overrun
error
NACK detection
Stop conditions detected
A/D converter A/D conversion end 25 H'0032 to H'0033 H'000064 to H'000067
Timer Z Compare match/input 26 H'0034 to H'0035 H'000068 to H'00006B
capture A0 to D0
Timer Z overflow
Compare match/input 27 H'0036 to H'0037 H'00006C to H'00006F
capture A1 to D1
Timer Z overflow
Timer Z underflow
 Reserved for system use 28 H'0038 to H'0039 H'000070 to H'000073
Timer B1 Timer B1 overflow 29 H'003A to H'003B H'000074 to H'000077
 Reserved for system use 30, 31 H'003C to H'003F H'000078 to H'00007F
SCI3_2 Receive data full 32 H'0040 to H'0041 H'000080 to H'000083
Transmit data empty
Transmit end
Receive error
 Reserved for system use 33 H'0042 to H'0043 H'000084 to H'000087
Clock source Clock source switching 34 H'0044 to H'0045 H'000088 to H'00008B
switching (from external clock to
on-chip oscillator) Low
Note: * A low-voltage detection interrupt is enabled only in the product with an on-chip power-
on reset and low-voltage detection circuit.
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3.2 Register Descriptions

Interrupts are controlled by the following registers.
• Interrupt edge select register 1 (IEGR1)

• Interrupt edge select register 2 (IEGR2)
• Interrupt enable register 1 (IENR1)
• Interrupt enable register 2 (IENR2)
• Interrupt flag register 1 (IRR1)
• Interrupt flag register 2 (IRR2)
• Wakeup interrupt flag register (IWPR)
3.2.1 Interrupt Edge Select Register 1 (IEGR1)
IEGR1 selects the direction of an edge that generates interrupt requests of pins NMI and IRQ3 to
IRQ0.
Initial
7 NMIEG 0 R/W NMI Edge Select
0: Falling edge of NMI pin input is detected
1: Rising edge of NMI pin input is detected
6 to 4  All 1  Reserved
These bits are always read as 1.
3 IEG3 0 R/W IRQ3 Edge Select
0: Falling edge of IRQ3 pin input is detected
1: Rising edge of IRQ3 pin input is detected
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3.2.2 Interrupt Edge Select Register 2 (IEGR2)
IEGR2 selects the direction of an edge that generates interrupt requests of the pins ADTRG and
WKP5 to WKP0.
Initial
7, 6  All 1  Reserved
5 WPEG5 0 R/W WKP5 Edge Select
0: Falling edge of WKP5(ADTRG) pin input is detected
1: Rising edge of WKP5(ADTRG) pin input is detected
0: Falling edge of WKP4 pin input is detected
1: Rising edge of WKP4 pin input is detected
1 WPEG1 0 R/W WKP1Edge Select
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3.2.3 Interrupt Enable Register 1 (IENR1)
IENR1 enables direct transition interrupts, RTC interrupts, and external pin interrupts.
Initial
7 IENDT 0 R/W Direct Transfer Interrupt Enable
When this bit is set to 1, direct transition interrupt
requests are enabled.
6 IENTA 0 R/W RTC Interrupt Enable
When this bit is set to 1, RTC interrupt requests are
enabled.
5 IENWP 0 R/W Wakeup Interrupt Enable
This bit is an enable bit, which is common to the pins
WKP5 to WKP0. When the bit is set to 1, interrupt
4  1  Reserved
This bit is always read as 1.
3 IEN3 0 R/W IRQ3 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ3 pin
are enabled.
are enabled.
are enabled.
are enabled.
When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in
an interrupt flag register, always do so while interrupts are masked (I = 1). If the above clear
operations are performed while I = 0, and as a result a conflict arises between the clear instruction
and an interrupt request, exception handling for the interrupt will be executed after the clear
instruction has been executed.
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3.2.4 Interrupt Enable Register 2 (IENR2)
IENR2 enables, timer B1 overflow interrupts.
Initial
5 IENTB1 0 R/W Timer B1 Interrupt Enable
When this bit is set to 1, timer B1 overflow interrupt
When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in
an interrupt flag register, always do so while interrupts are masked (I = 1). If the above clear
operations are performed while I = 0, and as a result a conflict arises between the clear instruction
and an interrupt request, exception handling for the interrupt will be executed after the clear
instruction has been executed.
3.2.5 Interrupt Flag Register 1 (IRR1)
IRR1 is a status flag register for direct transition interrupts, RTC interrupts, and IRQ3 to IRQ0
interrupt requests.
Initial
7 IRRDT 0 R/W Direct Transfer Interrupt Request Flag
[Setting condition]
When a direct transfer is made by executing a SLEEP
instruction while DTON in SYSCR2 is set to 1.
[Clearing condition]
When IRRDT is cleared by writing 0
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Initial
6 IRRTA 0 R/W RTC Interrupt Request Flag
[Setting condition]
When the RTC counter value overflows
When IRRTA is cleared by writing 0
3 IRRI3 0 R/W IRQ3 Interrupt Request Flag
[Setting condition]
When IRQ3 pin is designated for interrupt input and the
designated signal edge is detected.
When IRRI3 is cleared by writing 0
[Setting condition]
[Setting condition]
0 IRRl0 0 R/W IRQ0 Interrupt Request Flag
[Setting condition]
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3.2.6 Interrupt Flag Register 2 (IRR2)
IRR2 is a status flag register for timer B1 overflow interrupts.
Initial
5 IRRTB1 0 R/W Timer B1 Interrupt Request flag
[Setting condition]
When the timer B1 counter value overflows
When IRRTB1 is cleared by writing 0
3.2.7 Wakeup Interrupt Flag Register (IWPR)
IWPR is a status flag register for WKP5 to WKP0 interrupt requests.
Initial
5 IWPF5 0 R/W WKP5 Interrupt Request Flag
[Setting condition]
When WKP5 pin is designated for interrupt input and the
When IWPF5 is cleared by writing 0.
[Setting condition]
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Initial
[Setting condition]
[Setting condition]
[Setting condition]
[Setting condition]
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3.3 Reset Exception Handling

When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of
the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure
that this LSI is reset at power-up, hold the RES pin low until the clock pulse generator output
stabilizes. To reset the chip during operation, hold the RES pin low for at least 10 system clock
cycles. When the RES pin goes high after being held low for the necessary time, this LSI starts
reset exception handling. The reset exception handling sequence is shown in figure 3.1. However,
for the reset exception handling sequence of the product with on-chip power-on reset circuit, refer
to section 19, Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits.
The reset exception handling sequence is as follows:
1. Set the I bit in the condition code register (CCR) to 1.

2. The CPU generates a reset exception handling vector address, the data in that address is sent to
the program counter (PC) as the start address, and program execution starts from that address.
The reset exception handling vector address is H'0000 to H'0001 for normal mode operation
and H'000000 to H'000003 in advanced mode operation.
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3.4 Interrupt Exception Handling
3.4.1 External Interrupts
As the external interrupts, there are NMI, IRQ3 to IRQ0, and WKP5 to WKP0 interrupts.
(1) NMI Interrupt
NMI interrupt is requested by input signal edge to pin NMI. This interrupt is detected by either
rising edge sensing or falling edge sensing, depending on the setting of bit NMIEG in IEGR1.
NMI is the highest-priority interrupt, and can always be accepted without depending on the I
bit value in CCR.
(2) IRQ3 to IRQ0 Interrupts
IRQ3 to IRQ0 interrupts are requested by input signals to pins IRQ3 to IRQ0. These four
interrupts are given different vector addresses, and are detected individually by either rising
edge sensing or falling edge sensing, depending on the settings of bits IEG3 to IEG0 in IEGR1.
When pins IRQ3 to IRQ0 are designated for interrupt input in PMR1 and the designated signal
edge is input, the corresponding bit in IRR1 is set to 1, requesting the CPU of an interrupt.
These interrupts can be masked by setting bits IEN3 to IEN0 in IENR1.
(3) WKP5 to WKP0 Interrupts
WKP5 to WKP0 interrupts are requested by input signals to pins WKP5 to WKP0. These six
interrupts have the same vector addresses, and are detected individually by either rising edge
sensing or falling edge sensing, depending on the settings of bits WPEG5 to WPEG0 in
IEGR2.
When pins WKP5 to WKP0 are designated for interrupt input in PMR5 and the designated
signal edge is input, the corresponding bit in IWPR is set to 1, requesting the CPU of an
interrupt. These interrupts can be masked by setting bit IENWP in IENR1.
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Normal mode operation

Reset cleared Initial program
Internal instruction
Vector fetch processing prefetch
RES
Internal address bus (1) (2)
Internal data bus

(2) (3)
(16 bits)
(1) Reset exception handling vector address (H'0000)

(2) Program start address
(3) Initial program instruction
Advanced mode operation

Reset cleared
Initial program
Internal instruction
Vector fetch processing prefetch
RES
Internal address bus (1) (3) (5)
Internal data bus

(16 bits) (2) (4) (6)
(1), (3) Reset exception handling vector address ((1) = H'000000 (3) = H'000002)
(2), (4) Start address (contents of reset exception handling vector address)
(5) Start address
(6) Initial program instruction
Figure 3.1 Reset Sequence
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3.4.2 Internal Interrupts
Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to
enable or disable the interrupt. For RTC interrupt requests and direct transfer interrupt requests
generated by execution of a SLEEP instruction, this function is included in IRR1, IRR2, IENR1,
and IENR2.
When an on-chip peripheral module requests an interrupt, the corresponding interrupt request
status flag is set to 1, requesting the CPU of an interrupt. These interrupts can be masked by
writing 0 to clear the corresponding enable bit.
3.4.3 Interrupt Handling Sequence
Interrupts are controlled by an interrupt controller.
Interrupt operation is described as follows.
1. If an interrupt occurs while the NMI or interrupt enable bit is set to 1, an interrupt request
signal is sent to the interrupt controller.
2. When multiple interrupt requests are generated, the interrupt controller requests to the CPU for
the interrupt handling with the highest priority at that time according to table 3.1. Other
interrupt requests are held pending.
3. The CPU accepts the NMI and address break without depending on the I bit value. Other
interrupt requests are accepted, if the I bit is cleared to 0 in CCR; if the I bit is set to 1, the
interrupt request is held pending.
4. If the CPU accepts the interrupt after processing of the current instruction is completed,
interrupt exception handling will begin. First, both PC and CCR are pushed onto the stack. The
state of the stack at this time is shown in figure 3.2. The PC value pushed onto the stack is the
address of the first instruction to be executed upon return from interrupt handling.
5. Then, the I bit of CCR is set to 1, masking further interrupts excluding the NMI and address
break. Upon return from interrupt handling, the values of I bit and other bits in CCR will be
restored and returned to the values prior to the start of interrupt exception handling.
6. Next, the CPU generates the vector address corresponding to the accepted interrupt, and
transfers the address to PC as a start address of the interrupt handling-routine. Then a program
starts executing from the address indicated in PC.
Figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip ROM and
the stack area is in the on-chip RAM.
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SP - 4 SP (R7) CCR
SP - 3 SP + 1 CCR*
SP - 2 SP + 2 PCH
SP - 1 SP + 3 PCL
SP (R7) SP + 4 Even address
Stack area
Prior to start of interrupt After completion of interrupt

exception handling PC and CCR exception handling
saved to stack
SP - 4 SP (R7) CCR
SP - 3 SP + 1 PCE
SP - 2 SP + 2 PCH
SP - 1 SP + 3 PCL
SP (R7) SP + 4 Even address
Stack area
Prior to start of interrupt After completion of interrupt

exception handling PC and CCR exception handling
[Legend] saved to stack
PCE: Bits 23 to 16 of program counter (PC)
PCH: Bits 15 to 8 of program counter (PC)
PCL: Bits 7 to 0 of program counter (PC)
CCR: Condition code register
SP: Stack pointer
Notes: 1. PC shows the address of the first instruction to be executed upon return from the interrupt handling routine.
2. Register contents must always be saved and restored in word units, starting from an even-numbered address.
* Ignored when returning from the interrupt handling routine.
Figure 3.2 Stack Status after Exception Handling
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3.4.4 Interrupt Response Time
Table 3.2 shows the number of wait states after an interrupt request flag is set until the first
instruction of the interrupt handling-routine is executed.
Table 3.2 Interrupt Wait States
Item States Total

1
Waiting time for completion of executing instruction* 1 to 23 15 to 37
2
Saving of PC and CCR to stack 4 (17 to 39)*
2
Vector fetch 2 (4)*
Instruction fetch 4
Internal processing 4
Notes: 1. Not including EEPMOV instruction.
2. The value in parentheses is the number of states in advance mode.
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Interrupt is accepted
Interrupt level
decision and wait Instruction Internal Internal Prefetch instruction of
Stack access Vector fetch processing interrupt handling routine
for end of instruction prefetch processing
Interrupt
request signal
Internal
address bus (1) (3) (5) (6) (8) (9)
Internal
read signal
Internal
write signal
Internal data (2) (4) (1) (7) (9) (10)
bus (16 bits)
(1) Instruction prefetch address (Instruction is not executed. (7) CCR

Address is saved as PC contents, becoming return address.) (8) Vector address
(2), (4) Instruction code (Instruction is not executed.) (9) Start address of interrupt handling routine (contents of vector)
(3) Instruction prefetch address (Instruction is not executed.) (10) First instruction of interrupt handling routine.
(5) SP - 2
(6) SP - 4
Interrupt is accepted
Interrupt level
Instruction Internal Internal Prefetch instruction of
decision and wait Stack access Vector fetch
prefetch processing processing interrupt handling routine
for end of instruction
Interrupt
request signal
Internal
address bus (1) (3) (5) (7) (9) (11) (13)
Internal
read signal
Internal High level

write signal
Internal (14)
(2) (4) (6) (8) (10) (12)
data bus
(1) Instruction prefetch address (Instruction is not executed. (6), (8) Saved PC and CCR
Address is saved as PC contents, becoming return address.) (9), (11) Vector address
(2), (4) Instruction code (Instruction is not executed.) (10), (12) Start address of interrupt handling routine (contents of vector)
(3) Instruction prefetch address (Instruction is not executed.) (13) Start address of interrupt handling routine ((13), (10), (12))
(5) SP - 2 (14) First instruction of interrupt handling routine.
(7) SP - 4
Figure 3.3 Interrupt Sequence
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3.5 Usage Notes
3.5.1 Interrupts after Reset
If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.W #xx: 16, SP).
3.5.2 Notes on Stack Area Use
When word data is accessed, the least significant bit of the address is regarded as 0. Access to the
stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd
address. Use PUSH Rn (MOV.W Rn, @–SP) or POP Rn (MOV.W @SP+, Rn) to save or restore
register values.
3.5.3 Notes on Rewriting Port Mode Registers
When a port mode register is rewritten to switch the functions of external interrupt pins, IRQ3 to
IRQ0, and WKP5 to WKP0, the interrupt request flag may be set to 1.
When switching a pin function, mask the interrupt before setting the bit in the port mode register.
After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the
interrupt request flag from 1 to 0.
Figure 3.4 shows a port mode register setting and interrupt request flag clearing procedure.
Interrupts masked. (Another possibility

CCR I bit ← 1 is to disable the relevant interrupt in
interrupt enable register 1.)
Set port mode register bit

After setting the port mode register bit,
first execute at least one instruction
Execute NOP instruction (e.g., NOP), then clear the interrupt
request flag to 0.
Clear interrupt request flag to 0
CCR I bit ← 0 Interrupt mask cleared
Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure
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The address break simplifies on-board program debugging. It requests an address break interrupt
when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR.
Break conditions that can be set include instruction execution at a specific address and a
combination of access and data at a specific address. With the address break function, the
execution start point of a program containing a bug is detected and execution is branched to the
correcting program. Figure 4.1 shows a block diagram of the address break.
Internal address bus
Comparator
BARE* BARH BARL
Internal data bus

Interrupt ABRKCR
generation
control circuit ABRKSR
BDRH BDRL
Comparator
Interrupt
[Legend]
BARE*, BARH, BARL: Break address registers
BDRH, BDRL: Break data registers
ABRKCR: Address break control register
ABRKSR: Address break status register
Note: * Only provided for microcontrollers that support advanced mode.
Figure 4.1 Block Diagram of Address Break
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Address break has the following registers.
• Address break control register (ABRKCR)

• Address break status register (ABRKSR)
• Break address register (BARH, BARL)
• Break data register (BDRH, BDRL)
4.1.1 Address Break Control Register (ABRKCR)
ABRKCR sets address break conditions.
Initial
7 RTINTE 1 R/W RTE Interrupt Enable
When this bit is 0, the interrupt immediately after
executing RTE is masked and then one instruction must
be executed. When this bit is 1, the interrupt is not
masked.
6 CSEL1 0 R/W Condition Select 1 and 0
5 CSEL0 0 R/W These bits set address break conditions.
00: Instruction execution cycle
01: CPU data read cycle
10: CPU data write cycle
11: CPU data read/write cycle
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Initial
4 ACMP2 0 R/W Address Compare Condition Select 2 to 0
3 ACMP1 0 R/W These bits set the comparison condition between the
2 ACMP0 0 R/W address set in BAR and the internal address bus.
Normal mode
000: Compares 16-bit addresses
001: Compares the higher-order 12 bits of the addresses
1XX: Reserved (setting prohibited)
Advanced mode
000: Compares 24-bit addresses
1XX: Reserved (setting prohibited)
1 DCMP1 0 R/W Data Compare Condition Select 1 and 0
0 DCMP0 0 R/W These bits set the comparison condition between the data
set in BDR and the internal data bus.
00: No data comparison
01: Compares lower 8-bit data between BDRL and data
bus
10: Compares upper 8-bit data between BDRH and data
bus
11: Compares 16-bit data between BDR and data bus
[Legend] X: Don't care.
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When an address break is set in the data read cycle or data write cycle, the data bus used will
depend on the combination of the byte/word access and address. Table 4.1 shows the access and
data bus used. When an I/O register space with an 8-bit data bus width is accessed in word size, a
byte access is generated twice. For details on data widths of each register, see section 21.1,
Register Addresses (Address Order).
Table 4.1 Access and Data Bus Used
Word Access Byte Access

Even Address Odd Address Even Address Odd Address
ROM space Upper 8 bits Lower 8 bits Upper 8 bits Upper 8 bits
RAM space Upper 8 bits Lower 8 bits Upper 8 bits Upper 8 bits
I/O register with 8-bit data Upper 8 bits Upper 8 bits Upper 8 bits Upper 8 bits
bus width
I/O register with 16-bit data Upper 8 bits Lower 8 bits  
bus width
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4.1.2 Address Break Status Register (ABRKSR)
ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit.
Initial
7 ABIF 0 R/W Address Break Interrupt Flag
[Setting condition]
When the condition set in ABRKCR is satisfied
When 0 is written after ABIF=1 is read
6 ABIE 0 R/W Address Break Interrupt Enable
When this bit is 1, an address break interrupt request is
enabled.
4.1.3 Break Address Registers (BARE, BARH, BARL)
Settings of the address where an address-break interrupt is to be generated are made in the break
address registers (BAR: BARE*, BARH and BARL). For microcontrollers that support normal-
mode operation, BAR is a 16-bit readable/writable register with initial value H'FFFF. For
microcontrollers that support advanced-mode operation, BAR is a 24-bit readable/writable register
with the initial value H'FFFFFF. When setting an instruction execution cycle as the address break
condition, set BAR to the address of the first byte of the instruction.
Note: * BARE is only provided for microcontrollers that support advanced-mode operation.
4.1.4 Break Data Registers (BDRH, BDRL)
BDRH and BDRL are 16-bit read/write registers that set the data for generating an address break
interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is compared with the lower 8-
bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is used for
even and odd addresses in the data transmission. Therefore, comparison data must be set in BDRH
for byte access. For word access, the data bus used depends on the address. See section 4.1.1,
Address Break Control Register (ABRKCR), for details. The initial value of this register is
undefined.
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4.2 Operation
When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an
interrupt request to the CPU. The ABIF bit in ABRKSR is set to 1 by the combination of the
address set in BAR, the data set in BDR, and the conditions set in ABRKCR. When the interrupt
request is accepted, interrupt exception handling starts after the instruction being executed ends.
The address break interrupt is not masked by the I bit in CCR of the CPU.
Figures 4.2 show the operation examples of the address break interrupt setting.
When the address break is specified in instruction execution cycle
Register setting Program

• ABRKCR = H'80 0258 NOP
• BAR = H'025A * 025A NOP
025C MOV.W @H'025A,R0
Underline indicates the address
0260 NOP
to be stacked.
0262 NOP
: :
NOP NOP MOV MOV

instruc- instruc- instruc- instruc-
tion tion tion 1 tion 2 Internal
prefetch prefetch prefetch prefetch processing Stack save
Address
bus 0258 025A 025C 025E SP-2 SP-4
Interrupt
request
Interrupt acceptance
Figure 4.2 Address Break Interrupt Operation Example (1)
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When the address break is specified in the data read cycle
Register setting Program

• ABRKCR = H'A0 0258 NOP
• BAR = H'025A 025A NOP
* 025C MOV.W @H'025A,R0
0260 NOP Underline indicates the address
0262 NOP to be stacked.
: :
MOV MOV NOP MOV NOP Next

instruc- instruc- instruc- instruc- instruc- instru-
tion 1 tion 2 tion tion tion ction Internal Stack
prefetch prefetch prefetch execution prefetch prefetch processing save
Address
bus 025C 025E 0260 025A 0262 0264 SP-2
Interrupt
request
Interrupt acceptance
Figure 4.2 Address Break Interrupt Operation Example (2)
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The clock pulse generator (CPG) consists of a system clock generating circuitry, a subclock
generating circuitry, and two prescalers. The system clock generating circuitry includes an
external clock oscillator, a duty correction circuit, an on-chip oscillator, an RC clock divider, a
clock select circuit, and a system clock divider. The subclock generating circuitry includes a
subclock oscillator, and a subclock divider. The CPG can function as a clock generating circuitry
itself or in combination with an external oscillator. Figure 5.1 shows a block diagram of the clock
pulse generator.
OSC1 External φOSC Duty φOSC φ

clock correction
OSC2 oscillator circuit φ/8
Clock φ System φ/16 φ
ROSC select clock
circuit divider φ/32
On-chip ROSC RC clock ROSC/2 φRC
φ/64 φ/2
Prescaler S to
oscillator divider ROSC/4 (13 bits) φ/8192
System clock generating circuitry
φW/2
X1 Subclock φW Subclock φW/4
φSUB
oscillator (fW)
X2 divider φW/8
φW/8
Prescaler W
to
(5 bits) φW/128
Subclock generating circuitry
Figure 5.1 Block Diagram of Clock Pulse Generator
The system clock (φ) and subclock (φSUB) are basic clocks on which the CPU and on-chip
peripheral modules operate. The system clock is divided into from φ/2 to φ/8192 by prescaler S.
The subclock is divided into from φW/8 to φW/128 by prescaler W. These divided clocks are
supplied to respective peripheral modules.
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5.1 Features
• Choice of two clock sources
On-chip oscillator clock
Clock by an external oscillator output
• Choice of two types of RC oscillation frequency by the user software
16 MHz
20 MHz
• Frequency trimming
Since the initial frequency of the on-chip oscillator in the flash memory version is within the
range of two frequencies shown above, it is normally unnecessary to trim the frequency. It is,
however, still possible to adjust it by rewriting the trimming registers.
• Backup of the external oscillation halt
This system detects the external oscillator halt. If detected, the system clock source is
automatically switched to the on-chip oscillator clock.
• Interrupt can be requested to the CPU when the system clock is switched from the external
clock to the on-chip oscillator clock.

The CPG has the following registers.
• RC control register (RCCR)

• RC trimming data protect register (RCTRMDPR)
• RC trimming data register (RCTRMDR)
• Clock control/status register (CKCSR)
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5.2.1 RC Control Register (RCCR)
RCCR controls the on-chip oscillator.
Initial
7 RCSTP 0 R/W On-Chip Oscillator Standby
The on-chip oscillator standby state is entered by setting
this bit to 1.
6 FSEL 1 R/W Frequency Select for On-chip Oscillator
0: 16 MHz
1: 20 MHz
5 VCLSEL 0 R/W Power Supply Select for On-chip Oscillator
0: Selects VBGR
1: Selects VCL
When the VCL power is selected, the accuracy of the on-
chip oscillator frequency cannot be guaranteed.
1 RCPSC1 1 R/W Division Ratio Select for On-chip Oscillator
0 RCPSC0 0 R/W The division ratio of ROSC changes right after rewriting this
bit.
These bits can be written to only when the CKSTA bit in
CKCSR is 0.
0x: ROSC (not divided)
10: ROSC/2
11: ROSC/4
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5.2.2 RC Trimming Data Protect Register (RCTRMDPR)
RCTRMDPR controls RCTRMDPR itself and writing to RCTRMDR. Use the MOV instruction to
rewrite this register. Bit manipulation instruction cannot change the settings.
Initial
7 WRI 1 W Write Inhibit
Only when writing 0 to this bit, this register can be written
to. This bit is always read as 1.
6 PRWE 0 R/W Protect Information Write Enable
Bits 5 and 4 can be written to when this bit is set to 1.
[Setting condition]
• When writing 0 to the WRI bit and writing 1 to the
PRWE bit
[Clearing conditions]
• Reset
PRWE bit
5 LOCKDW 0 R/W Trimming Data Register Lock Down
The RC trimming data register (RCTRMDR) cannot be
written to when this bit is set to 1. Once this bit is set to 1,
this register cannot be written to until a reset is input even
if 0 is written to this bit.
[Setting condition]
LOCKDW bit while the PRWE bit is 1
• Reset
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Initial
4 TRMDRWE 0 R/W Trimming Data Register Write Enable
This register can be written to when the LOCKDW bit is 0
and this bit is 1.
[Setting condition]
• When writing 0 to the WRI bit while writing 1 to the
TRMDRWE bit while the PRWE bit is 1
• Reset
TRMDRWE bit while the PRWE bit is 1
5.2.3 RC Trimming Data Register (RCTRMDR)
RCTRMDR stores the trimming data of the on-chip oscillator frequency (FSEL = 1, 20 MHz).
Initial
7 TRMD7 (0)* R/W Trimming Data (FSEL = 1, 20 MHz)
6 TRMD6 (0)* R/W The trimming data is loaded from the flash memory to this
5 TRMD5 (0)* R/W register right after a reset.
4 TRMD4 (0)* R/W The on-chip oscillator clock (FSEL = 1, 20 MHz) can be
trimmed by changing these bits.
3 TRMD3 (0)* R/W
The frequency of the on-chip oscillator clock changes
2 TRMD2 (0)* R/W right after writing these bits. These bits are initialized to
1 TRMD1 (0)* R/W H'00.
0 TRMD0 (0)* R/W Changes in frequency are shown below (bit TRMD7 is a
sign bit).
(Min.) H'80 ← … ← H'FF ← … ← H'00 → … →H'01 → …
→ H'7F (Max.)
Note: * These values are initialized to the trimming data loaded from the flash memory.
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5.2.4 Clock Control/Status Register (CKCSR)
CKCSR selects the port C function, controls switching the system clocks, and indicates the system
clock state.
Initial
7 PMRC1 0 R/W Port C Function Select 1 and 2
6 PMRC0 0 R/W PMRC1 PMRC0 PC1 PC0
0 0 I/O I/O
1 0 CLKOUT I/O
0 1 (Open) OSC1 (external
clock input)
1 1 OSC2 OSC1
5 OSCBAKE 0 R/W External Clock Backup Enable

0: External clock backup disabled
1: External clock backup enabled
The external oscillation detecting circuit is enabled when
this bit is 1. When the external oscillator halt is detected
while this LSI operates on the external input signal, the
system clock source is automatically switched to the on-
chip oscillator regardless of the value of bit 4 in this
register.
Note: The external oscillation detecting circuit operates
on the on-chip oscillator clock. When this bit is set
to 1, do not set the on-chip oscillator to the standby
mode by the RCSTP bit in RCCR.
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Initial
4 OSCSEL 0 R/W LSI Operating Clock Select
• When OSCBAKE = 0
This bit is used to forcibly select the system clock of this
LSI.
0: The on-chip oscillator clock selected as the system
clock source
1: The external input selected as the system clock source
This bit is used to switch the on-chip oscillator clock to the
external clock. While this LSI is operating on the on-chip
oscillator clock, setting this bit to 1 switches the system
clocks to the external clock.
[Setting condition]
• When 1 is written to this bit while CKSWIF = 0
• When 0 is written to this bit
• When the external oscillator halt is detected while
OSCBAKE = 1
3 CKSWIE 0 R/W Clock Switching Interrupt Enable
Setting this bit to 1 enables the clock switching interrupt
request.
2 CKSWIF 0 R/W Clock Switching Interrupt Request Flag
[Setting condition]
• When the external clock is switched to the on-chip
oscillator clock as the system clock source
• When writing 0 after reading as 1
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Initial
1 OSCHLT 1 R External Oscillator Halt Detecting Flag
This bit indicates the checking result of the external
oscillator state.
0: External oscillator is running
1: External oscillator is halted.
This bit is non-deterministic; always read as 1.
0 CKSTA 0 R LSI Operating Clock Status
0: This LSI operates on the on-chip oscillator clock.
1: This LSI operates on the external clock.
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5.3 System Clock Select Operation

Figure 5.2 shows the state transition of the system clock.
LSI operates on on-chip oscillator clock
Reset release On-chip oscillator: Operated

Reset state
External oscillator: Halted
Switching to
* external clock
Oscillator halted
On-chip oscillator: Halted On-chip oscillator: Operated
External oscillator: Operated External oscillator: Operated
Oscillator operated
LSI operates on external oscillator
Note: * Conditions for the state transition are as follows:

• When the external oscillator halt is detected while the backup function is enabled
• When the external clock is switched to the on-chip oscillator clock by user software
while the backup function is disabled
Figure 5.2 State Transition of System Clock
5.3.1 Clock Control Operation
The LSI system clock is generated by the on-chip oscillator clock after a reset. The system clock
sources are switched from the on-chip oscillator to the external clock by the user software. Figure
5.3 shows the flowchart to switch clocks with the external clock backup function enabled. Figures
5.4 and 5.5 show the flowcharts to switch clocks with the external clock backup function disabled.
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[1] External oscillation starts to be enabled when pins

PC1 and PC0 are specified as external clock pins.
Write 0 to bit PMRC1 to input the external clock.
Start (reset) [2] The external oscillator halt detecting circuit is
enabled when the external oscillation backup
function is enabled. Since this detecting circuit
operates on the on-chip oscillator clock, do not set
the on-chip oscillator to standby mode by using the
Write 1 to PMRC0 in CKCSR [1] RCSTP bit in RCCR.
Write 1 to PMRC1 in CKCSR [3] An interrupt to switch from the on-chip oscillator
clock to the external oscillator is enabled.
[4] After writing 1 to the OSCSEL bit, this LSI waits
until the oscillation of the external oscillator settles.
Write 1 to OSCBAKE in CKCSR [2] The correspondence between Nwait, which is the
number of wait cycles for oscillation settling, and
Nstby, which is the number of wait cycles for
oscillation settling when returning from standby
mode, is as follows:
Clear CKSWIF in CKCSR to 0 Nstby ≤ Nwait ≤ 2 × Nstby
Nstby is set by bits STS[2:0] in SYSCR1. For
details, see section 6.1.1, System Control Register
1 (SYSCR1).
Write 1 to CKSWIE in CKCSR [3] [5] While waiting for external oscillation settling, this
LSI is not halted but continues to operate on the on-
chip oscillator clock. Read the CKSTA bit in CKCSR
to ensure whether or not clocks are switched. When
the oscillation settles, this LSI switches the system
Write 1 to OSCSEL in CKCSR [4] clocks to the external clock. If the external oscillator
is halted, then set the clock switching interrupt
request flag.
[6] If this LSI detects the external oscillator halt, it
switches the system clocks to the on-chip oscillator
[5]
clock, and sets the clock switching interrupt request
Switched to No flag.
external clock? (CKSTA in
CKCSR is 1) External
oscillator halt LSI operates on
Yes is detected* on-chip oscillator clock
[6] Exception handling

LSI operates on external clock for clock switching
External oscillator
halt is detected*
Note: * To prevent the LSI from malfunctioning at the external oscillation halt, switching the clock source along
with the watchdog timer is highly recommended.
Figure 5.3 Flowchart of Clock Switching with Backup Function Enabled
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[1] External oscillation starts to be enabled when
Start (reset) pins PC1 and PC0 are specified as external
clock pins. Write 0 to bit PMRC1 to input the
external clock.
[2] After writing 1 to the OSCSEL bit, this LSI

Write 1 to PMRC0 in CKCSR [1] waits until the oscillation of the external
Write 1 to PMRC1 in CKCSR oscillator settles. The correspondence
between Nwait, which is the number of wait
cycles for oscillation settling, and Nstby,
which is the number of wait cycles for
oscillation settling when returning from
Write 0 to CKSWIF in CKCSR
standby mode, is as follows:
Nstby ≤ Nwait ≤ 2 × Nstby
Nstby is set by bits STS[2:0] in SYSCR1. For
details, see section 6.1.1, System Control
Write 1 to OSCSEL in CKCSR [2] Register 1 (SYSCR1).
[3] While the system is waiting for the external

oscillation settling, this LSI is not halted but
continues to operate on the on-chip oscillator
[3] clock. Read the value of the CKSTA bit in
Switched to No CKCSR to ensure that the system clocks are
external clock? (CKSTA in switched.
CKCSR is 1)
Yes
LSI operates on external oscillator
(From On-Chip Oscillator Clock to External Clock)
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LSI operates on
external clock
[1] When 0 is written to the OSCSEL bit, this LSI
Start switches from the external clock to the on-chip
(LSI operates on external clock) oscillator clock after a φ stop duration. The φ halt
duration here is the duration while the φRC clock
rises seven times after the OSCSEL bit becomes
0.
Write 0 to OSCBAKE in CKCSR
[2] Writing 0 to PMRC0 disables the external
oscillation input.
Write 1 to CKSWIE in CKCSR

if necessary
Write 0 to OSCSEL in CKCSR [1]
LSI operates on
on-chip oscillator clock
When CKSWIE = 1
Exception handling
for clock switching
Write 0 to PMRC0 in CKCSR [2]

if necessary
LSI operates on
on-chip oscillator clock
(From External Clock to On-Chip Oscillator Clock)
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5.3.2 Clock Switching Timing
The timing for switching clocks are shown in figures 5.6 to 5.8.
φOSC
φRC
OSCSEL
PHISTOP
(Internal signal)
CKSTA
On-chip oscillator clock operation φ halt* External clock operation

Wait for external
oscillation settling
Nwait
[Legend]
φOSC: External clock
φRC: On-chip oscillator clock
φ: System clock
OSCSEL: Bit 4 in CKCSR
PHISTOP: System clock stop control signal
CKSTA: Bit 0 in CKCSR
Note: * The φ halt duration is the duration from the timing when the φ clock stops to the first
rising edge of the φOSC clock after seven clock cycles of the φRC clock have elapsed.
Figure 5.6 Timing Chart of Switching from On-Chip Oscillator Clock to External Clock
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φOSC
φRC
OSCSEL
PHISTOP
(Internal signal)
CKSTA
CKSWIF
On-chip oscillator
External RC clock operation φ halt*
clock operation
[Legend]
φ: System clock
OSCSEL: Bit 4 in CKCSR
CKSWIF: Bit 2 in CKCSR
Note: * The φ halt duration is the duration from the timing when the φ clock stops to the
seventh rising edge of the φRC clock.
Figure 5.7 Timing Chart to Switch from External Clock to On-Chip Oscillator Clock
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External clock halt
φOSC
φRC
OSCHLT
PHISTOP
(Internal signal)
CKSTA
CKSWIF
φOSC halt On-chip oscillator
External clock operation φ halt*2 clock operation
detected*1
Tchk
[Legend]
φ: System clock
OSCHLT: Bit 1 in CKCSR
CKSWIF: Bit 2 in CKCSR
Notes: 1. 44 × φRC ≤ Tchk ≤ 48 × φRC
2. The φ halt duration is the duration from the timing when the φ clock stops to the
seventh rising edge of the φRC clock.
Figure 5.8 External Oscillation Backup Timing
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5.4 Trimming of On-Chip Oscillator Frequency

Users can trim the on-chip oscillator clock, supplying the external reference pulses with the input
capture function in internal timer Z. An example of trimming flow and a timing chart are shown in
figures 5.9 and 5.10, respectively. Because RCTRMDR is initialized by a reset, when users have
trimmed the frequencies, some operations after a reset are necessary, such as trimming it again or
saving the trimming value in an external device for later reloading.
Start
Setting timer Z
GRA: Input capture
GRC: Buffer of GRA
Set RCTRMDR to H'00
Input reference pulses to

pin P60/FTIOA0
Capture 1
Capture 2 Modify RCTRMDR*
Frequency calculation
Within No
desired frequency
range?
Yes
End
Note: * Comparing the difference between the measured frequency and the desired frequency,
individual bits of RCTRMDR are decided from the MSB bit by bit.
Figure 5.9 Example of Trimming Flow for On-Chip Oscillator Clock
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φRC
FTIOA0 input
capture input
tA (µs)
Timer Z M+α
M−1 M M+1
TCNT
GRA_0 N M M+α
GRC_0 N M
Capture 1 Capture 2
Figure 5.10 Timing Chart of Trimming of On-Chip Oscillator Frequency
The on-chip oscillator frequency is gained by the expression below. Since the input-capture input
is sampled by the φRC clock, the calculated result may include a sampling error of ±1 cycle of the
φRC clock.
(M + α) − M
φRC = (MHz)
tA
φRC: Frequency of on-chip oscillator (MHz)

tA: Period of reference clock (µs)
M: Timer Z counter value
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5.5 External Oscillators

There are two methods to supply external clock pulses into this LSI: connecting a crystal or
ceramic resonator, and an external clock. Oscillation pins OSC1 and OSC2 are common with
general ports PC0 and PC1, respectively. To set pins PC0 and PC1 as crystal resonator or external
clock input ports, refer to section 5.2.4, Clock Control/Status Register (CKCSR).
Figure 5.11 shows a block diagram of an external clock oscillator.
OSC2
600 kΩ*2
LPM*1
OSC1
Notes: 1. LPM: Power-down mode (standby mode, subactive mode, or subsleep mode)
2. Values here are reference values.
Figure 5.11 Block Diagram of External Clock Oscillator
5.5.1 Connecting Crystal Resonator
Figure 5.12 shows an example of connecting a crystal resonator. An AT-cut parallel-resonance

crystal resonator should be used. Figure 5.13 shows the equivalent circuit of a crystal resonator. A
resonator having the characteristics given in table 5.1 should be used.
C1
PC0/OSC1
C2
C1 = C 2 = 10 to 22 pF
PC1/OSC2/CLKOUT
Figure 5.12 Example of Connection to Crystal Resonator
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LS RS
CS
PC0/OSC1 PC1/OSC2/CLKOUT
CO
Figure 5.13 Equivalent Circuit of Crystal Resonator
Table 5.1 Crystal Resonator Parameters
Frequency (MHz) 4 8 10 16 20
RS (Max.) 120 Ω 80 Ω 60 Ω 50 Ω 40 Ω
CO (Max.) 70 pF
5.5.2 Connecting Ceramic Resonator
Figure 5.14 shows an example of connecting a ceramic resonator.
C1
PC0/OSC1
C2
C1 = C 2 = 5 to 30 pF
PC1/OSC2/CLKOUT
Figure 5.14 Example of Connection to Ceramic Resonator
5.5.3 Inputting External Clock
To use the external clock, input the external clock on pin OSC1. Figure 5.15 shows an example of
connection. The duty cycle of the external clock signal must range from 45 to 55%.
PC0/OSC1 External clock input
PC1/OSC2/CLKOUT Open
Figure 5.15 Example of External Clock Input
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5.6 Subclock Oscillator

Figure 5.16 shows a block diagram of the subclock oscillator.
X2
8 MΩ
X1
Note : Resistance here is a reference value.
Figure 5.16 Block Diagram of Subclock Oscillator
5.6.1 Connecting 32.768-kHz Crystal Resonator
Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystal
resonator, as shown in figure 5.17. Figure 5.18 shows the equivalent circuit of the 32.768-kHz
crystal resonator.
C1
X1
C2
X2
C1 = C 2 = 15 pF (typ.)
Figure 5.17 Typical Connection to 32.768-kHz Crystal Resonator
LS CS RS
X1 X2
CO
CO = 1.5 pF (typ.)
RS = 14 kΩ (typ.)
fW = 32.768 kHz
Note: Values here are reference values.
Figure 5.18 Equivalent Circuit of 32.768-kHz Crystal Resonator
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5.6.2 Pin Connection when Not Using Subclock
When the subclock is not used, connect pin X1 to VCL or VSS and leave pin X2 open, as shown
in figure 5.19.
VCL or VSS
X1
X2 Open
Figure 5.19 Pin Connection when not Using Subclock
5.7 Prescaler
5.7.1 Prescaler S
Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. The outputs, which are
divided clocks, are used as internal clocks by the on-chip peripheral modules. Prescaler S is
initialized to H'0000 by a reset, and starts counting on exit from the reset state. In standby mode
and subsleep mode, the external clock oscillator stops. Prescaler S also stops and is initialized to
H'0000. It cannot be read from or written to by the CPU.
The outputs from prescaler S are shared by the on-chip peripheral modules. The division ratio can
be set separately for each on-chip peripheral module. In active mode and sleep mode, the clock
input to prescaler S is a system clock with the division ratio specified by bits MA2 to MA0 in
SYSCR2.
5.7.2 Prescaler W
Prescaler W is a 5-bit counter using a 32.768-kHz signal divided by 4 as its input clock. The
divided output is used for clock time base operation of the RTC. Prescaler W is initialized to H'00
by a reset, and starts counting on exit from the reset state. Even in standby mode, subactive mode,
or subsleep mode, prescaler W continues functioning.
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5.8 Usage Notes
5.8.1 Note on Resonators
Resonator characteristics are closely related to board design and should be carefully evaluated by
the user, referring to the examples shown in this section. Resonator circuit parameters will differ
depending on the resonator element, stray capacitance of the PCB, and other factors. Suitable
values should be determined in consultation with the resonator element manufacturer. Design the
circuit so that the resonator element never receives voltages exceeding its maximum rating.
5.8.2 Notes on Board Design
When using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as
close as possible to pins OSC1 and OSC2. Other signal lines should be routed away from the
oscillator circuit to prevent induction from interfering with correct oscillation (see figure 5.20).
Prohibited Signal A Signal B
C1
PC0/OSC1
C2
PC1/OSC2/CLKOUT
Figure 5.20 Example of Incorrect Board Design
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REJ09B0216-0300

This LSI has six modes of operation after a reset. These include a normal active mode and four
power-down modes, in which power consumption is significantly reduced. Module standby mode
reduces power consumption by selectively halting on-chip module functions.
• Active mode
The CPU and all on-chip peripheral modules are operable on the system clock. The system
clock frequency can be selected from φosc, φosc/8, φosc/16, φosc/32, and φosc/64.
• Subactive mode
The CPU and all on-chip peripheral modules are operable on the subclock. The subclock
frequency can be selected from φw/2, φw/4, and φw/8.
• Sleep mode
The CPU halts. On-chip peripheral modules are operable on the system clock.
• Subsleep mode
The CPU halts. On-chip peripheral modules are operable on the subclock.
• Standby mode
The CPU and all on-chip peripheral modules halt. When the clock time-base function is
selected, the RTC is operable.
• Module standby mode
Independent of the above modes, power consumption can be reduced by halting on-chip
peripheral modules that are not used in module units.
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The registers related to power-down modes are listed below.
• System control register 1 (SYSCR1)

• System control register 2 (SYSCR2)
• Module standby control register 1 (MSTCR1)
• Module standby control register 2 (MSTCR2)
6.1.1 System Control Register 1 (SYSCR1)
SYSCR1 controls the power-down modes, as well as SYSCR2.
Initial
7 SSBY 0 R/W Software Standby
This bit selects the mode to transit after the execution of
the SLEEP instruction.
0: Enters sleep mode or subsleep mode.
1: Enters standby mode.
For details, see table 6.2.
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Initial
6 STS2 0 R/W Standby Timer Select 2 to 0
5 STS1 0 R/W These bits set the wait time from when the external clock
4 STS0 0 R/W oscillator starts functioning until the clock is supplied, in
shifting from standby mode, subactive mode, or subsleep
mode, to active mode or sleep mode. During the wait
time, this LSI automatically selects the on-chip oscillator
clock as its system clock and counts the number of wait
states. Select a wait time of 6.5 ms (oscillation
stabilization time) or longer, depending on the operating
frequency. Table 6.1 shows the relationship between the
STS2 to STS0 values and the wait time.
When using an external clock, set the wait time to be
100 µs or longer.
These bits also set the wait states for external oscillation
stabilization when system clock is switched from the on-
chip oscillator clock to the external clock by user
software.
The relationship between Nwait (number of wait states for
oscillation stabilization) and Nstby (number of wait states
for recovering to the standby mode) is as follows.
Nstby ≤ Nwait ≤ 2 × Nstby
3 NESEL 0 R/W Noise Elimination Sampling Frequency Select
The subclock pulse generator generates the watch clock
signal (φW) and the external clock pulse generator
generates the oscillator clock (φOSC). This bit selects the
sampling frequency of the oscillator clock when the watch
clock signal (φW) is sampled. When φOSC= 4 to 20 MHz,
clear NESEL to 0.
0: Sampling rate is φOSC/16
1: Sampling rate is φOSC/4
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Table 6.1 Operating Frequency and Waiting Time
Bit Name Operating Frequency

STS2 STS1 STS0 Waiting Time 20 MHz 16 MHz 10 MHz 8 MHz 5 MHz 4 MHz
0 0 0 8,192 states 0.4 0.5 0.8 1.0 1.6 2.0
1 16,384 states 0.8 1.0 1.6 2.0 3.3 4.1
1 0 32,768 states 1.6 2.0 3.3 4.1 6.6 8.2
1 65,536 states 3.3 4.1 6.6 8.2 13.1 16.4
1 0 0 131,072 states 6.6 8.2 13.1 16.4 26.2 32.8
1 1,024 states 0.05 0.06 0.10 0.13 0.20 0.26
1 0 128 states 0.00 0.00 0.01 0.02 0.03 0.03
1 16 states 0.00 0.00 0.00 0.00 0.00 0.00
Note: Time unit is ms.
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6.1.2 System Control Register 2 (SYSCR2)
SYSCR2 controls the power-down modes, as well as SYSCR1.
Initial
7 SMSEL 0 R/W Sleep Mode Selection
6 LSON 0 R/W Low Speed on Flag
5 DTON 0 R/W Direct Transfer on Flag
These bits select the mode to enter after the execution of
a SLEEP instruction, as well as bit SSBY of SYSCR1.
For details, see table 6.2.
4 MA2 0 R/W Active Mode Clock Select 2 to 0
3 MA1 0 R/W These bits select the operating clock frequency in active
2 MA0 0 R/W and sleep modes. The operating clock frequency
changes to the set frequency after the SLEEP instruction
is executed.
0XX: φOSC
100: φOSC/8
101: φOSC/16
110: φOSC/32
111: φOSC/64
1 SA1 0 R/W Subactive Mode Clock Select 1 and 0
0 SA0 0 R/W These bits select the operating clock frequency in
subactive and subsleep modes. The operating clock
frequency changes to the set frequency after the SLEEP
instruction is executed.
00: φW/8
01: φW/4
1X: φW/2
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6.1.3 Module Standby Control Register 1 (MSTCR1)
MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units.
Initial
6 MSTIIC 0 R/W IIC2 Module Standby
IIC2 enters standby mode when this bit is set to 1
5 MSTS3 0 R/W SCI3 Module Standby
SCI3 enters standby mode when this bit is set to 1
4 MSTAD 0 R/W A/D Converter Module Standby
A/D converter enters standby mode when this bit is set
to 1
3 MSTWD 0 R/W Watchdog Timer Module Standby
Watchdog timer enters standby mode when this bit is set
to 1.When the internal oscillator is selected for the
watchdog timer clock, the watchdog timer operates
regardless of the setting of this bit
1 MSTTV 0 R/W Timer V Module Standby
Timer V enters standby mode when this bit is set to 1
0 MSTTA 0 R/W RTC Module Standby
RTC enters standby mode when this bit is set to 1
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6.1.4 Module Standby Control Register 2 (MSTCR2)
MSTCR2 allows the on-chip peripheral modules to enter a standby state in module units.
Initial
7 MSTS3_2 0 R/W SCI3_2 Module Standby
SCI3_2 enters standby mode when this bit is set to1
4 MSTTB1 0 R/W Timer B1 Module Standby
Timer B1 enters standby mode when this bit is set to1
1 MSTTZ 0 R/W Timer Z Module Standby
Timer Z enters standby mode when this bit is set to1
0 MSTPWM 0 R/W PWM Module Standby
PWM enters standby mode when this bit is set to1
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6.2 Mode Transitions and States of LSI

Figure 6.1 shows the possible transitions among these operating modes. A transition is made from
the program execution state to the program halt state by executing a SLEEP instruction. Interrupts
allow for returning from the program halt state to the program execution state. A direct transition
between active mode and subactive mode, which are both program execution states, can be made
without halting the program. The operating frequency can also be changed in the same modes by
making a transition directly from active mode to active mode, and from subactive mode to
subactive mode. RES input enables transitions from a mode to the reset state. Table 6.2 shows the
transition conditions of each mode after the SLEEP instruction is executed and a mode to return
by an interrupt. Table 6.3 shows the internal states of the LSI in each mode.
Reset state
Program halt state Program execution state Program halt state

Direct transition
interrupt
SLEEP SLEEP
instruction instruction
Standby mode Active mode Sleep mode
Interrupt Interrupt
SLEEP
instruction
Direct Direct Interrupt

transition transition
interrupt interrupt
SLEEP
instruction
SLEEP
Interrupt
instruction
SLEEP
instruction
Subactive Subsleep mode
mode
Interrupt
Direct transition
interrupt
Notes: 1. To make a transition to another mode by an interrupt, make sure interrupt handling is after the interrupt
is accepted.
2. Details on the mode transition conditions are given in table 6.2.
Figure 6.1 Mode Transition Diagram
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Table 6.2 Transition Mode after SLEEP Instruction Execution and Transition Mode due
to Interrupt
Transition Mode after

SLEEP Instruction Transition Mode due to
DTON SSBY SMSEL LSON Execution Interrupt
0 0 0 0 Sleep mode Active mode
1 Subactive mode
1 0 Subsleep mode Active mode
1 Subactive mode
1 X X Standby mode Active mode
1 X 0* 0 Active mode 
(direct transition)
X X 1 Subactive mode 
(direct transition)
X: Don’t care.
Note: * When a state transition is performed while SMSEL is 1, timer V, SCI3, SCI3_2 and the
A/D converter are reset, and all registers are set to their initial values. To use these
functions after entering active mode, reset the registers.
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Table 6.3 Internal State in Each Operating Mode
Subactive Subsleep Standby

Function Active Mode Sleep Mode Mode Mode Mode
External clock oscillator Functioning Functioning Halted Halted Halted
Subclock oscillator Functioning Functioning Functioning Functioning Functioning
CPU Instructions Functioning Halted Functioning Halted Halted
operations
Registers Functioning Retained Functioning Retained Retained
RAM Functioning Retained Functioning Retained Retained
IO ports Functioning Retained Functioning Retained Register
contents are
retained, but
output is the
high-impedance
state.
External IRQ3 to IRQ0 Functioning Functioning Functioning Functioning Functioning
interrupts
WKP5 to Functioning Functioning Functioning Functioning Functioning
WKP0
Peripheral RTC Functioning Functioning Functioning if the timekeeping time-base
functions function is selected, and retained if not selected
Timer V Functioning Functioning Reset Reset Reset
Watchdog Functioning Functioning Retained (functioning if the internal oscillator is
timer selected as a count clock*)
SCI3, SCI3_2 Functioning Functioning Reset Reset Reset
IIC2 Functioning Functioning Retained* Retained Retained
Timer B1 Functioning Functioning Retained* Retained Retained
Timer Z Functioning Functioning Retained (the counter increments according to
subclocks if the internal clock (φ) is selected as
a count clock*)
A/D converter Functioning Functioning Reset Reset Reset
LVD Functioning Functioning Functioning Functioning Functioning
Note: * Registers can be read or written in subactive mode.
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6.2.1 Sleep Mode
In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock
frequency set by the MA2, MA1, and MA0 bits in SYSCR2. CPU register contents are retained.
When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts.
Sleep mode is not cleared if the I bit of the condition code register (CCR) is set to 1 or the
requested interrupt is disabled in the interrupt enable register. After sleep mode is cleared, a
transition is made to active mode when the LSON bit in SYSCR2 is 0, and a transition is made to
subactive mode when the bit is 1.
When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared.
6.2.2 Standby Mode
In standby mode, the external clock oscillator is halted, and operation of the CPU and on-chip
peripheral modules is halted. However, as long as the rated voltage is supplied, the contents of
CPU registers, on-chip RAM, and some on-chip peripheral module registers are retained. On-chip
RAM contents will be retained as long as the voltage set by the RAM data retention voltage is
provided. The I/O ports go to the high-impedance state.
Standby mode is cleared by an interrupt. When an interrupt is requested, the on-chip oscillator
starts functioning. The external oscillator also starts functioning when used. After the time set by
the STS2 to STS0 bits in SYSCR1 has elapsed, standby mode is cleared and the CPU starts
interrupt exception handling. Standby mode is not cleared if the I bit in the condition code register
(CCR) is set to 1 or the requested interrupt is disabled by the interrupt enable bit.
When the RES pin is driven low in standby mode, the on-chip oscillator starts functioning. Once
the oscillator starts, the system clock is supplied to the entire chip. The RES pin must be kept low
for the rated period set by the power-on reset circuit, until the oscillator stabilizes. If the RES pin
is driven high after the oscillator has stabilized, the internal reset signal is cleared and the CPU
starts reset exception handling.
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6.2.3 Subsleep Mode
In subsleep mode, operation of the CPU and on-chip peripheral modules other than RTC is halted.
As long as a required voltage is applied, the contents of CPU registers, the on-chip RAM, and
some registers of the on-chip peripheral modules are retained. I/O ports keep the same states as
before the transition.
Subsleep mode is cleared by an interrupt. When an interrupt is requested, subsleep mode is cleared
and interrupt exception handling starts. Subsleep mode is not cleared if the I bit of CCR is set to 1
or the requested interrupt is disabled in the interrupt enable register. After subsleep mode is
cleared, a transition is made to active mode when the LSON bit in SYSCR2 is 0, and a transition is
made to subactive mode when the bit is 1. After the time set in bits STS2 to STS0 in SYSCR1 has
elapsed, a transition is made to active mode.
6.2.4 Subactive Mode
The operating frequency of subactive mode is selected from φW/2, φW/4, and φW/8 by the SA1 and
SA0 bits in SYSCR2. After the SLEEP instruction is executed, the operating frequency changes to
the frequency which is set before the execution.
When the SLEEP instruction is executed in subactive mode, a transition to sleep mode, subsleep
mode, standby mode, active mode, or subactive mode is made, depending on the combination of
SYSCR1 and SYSCR2.
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6.3 Operating Frequency in Active Mode

Operation in active mode is clocked at the frequency designated by the MA2, MA1, and MA0 bits
in SYSCR2. The operating frequency changes to the set frequency after SLEEP instruction
execution.
6.4 Direct Transition

The CPU can execute programs in two modes: active and subactive modes. A direct transition is a
transition between these two modes without stopping program execution. A direct transition can
be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1. The direct
transition also enables operating frequency modification in active or subactive mode. After the
mode transition, direct transition interrupt exception handling starts.
If the direct transition interrupt is disabled in interrupt enable register 1, a transition is made
instead to sleep or subsleep mode. Note that if a direct transition is attempted while the I bit in
CCR is set to 1, sleep or subsleep mode will be entered, and the resulting mode cannot be cleared
by means of an interrupt.
6.4.1 Direct Transition from Active Mode to Subactive Mode
The time from the start of SLEEP instruction execution to the end of interrupt exception handling
(the direct transition time) is calculated by equation (1).
Direct transition time = {(number of SLEEP instruction execution states) + (number of internal
processing states)}× (tcyc before transition) + (number of interrupt exception handling states) ×
(tsubcyc after transition) (1)
Example
Direct transition time = (2 + 1) × tosc + 14 × 8tw = 3tosc + 112tw
(when the CPU operating clock of φosc → φw/8 is selected)
Legend
tosc: OSC clock cycle time
tw: Watch clock cycle time
tcyc: System clock (φ) cycle time
tsubcyc: Subclock (φSUB) cycle time
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6.4.2 Direct Transition from Subactive Mode to Active Mode
The time from the start of SLEEP instruction execution to the end of interrupt exception handling
(the direct transition time) is calculated by equation (2).
Direct transition time = {(number of SLEEP instruction execution states) + (number of internal
processing states)} × (tsubcyc before transition) + {(waiting time set in bits STS2 to STS0) +
(number of interrupt exception handling states)} × (tcyc after transition) (2)
Example
Direct transition time = (2 + 1) × 8tw + (8192 + 14) × tosc = 24tw + 8206tosc
(when the CPU operating clock of φw/8 → φosc and a waiting time of 8192 states are selected)
Legend
tosc: OSC clock cycle time
tw: Watch clock cycle time
tcyc: System clock (φ) cycle time
tsubcyc: Subclock (φSUB) cycle time
6.5 Module Standby Function

The module-standby function can be set to any peripheral module. In module standby mode, the
clock supply to modules stops to enter the power-down mode. Module standby mode enables each
on-chip peripheral module to enter the standby state by setting a bit that corresponds to each
module to 1 and cancels the mode by clearing the bit to 0.
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Section 7 ROM
Section 7 ROM
The features of the flash memory built into this LSI are summarized below.
• Programming/erase methods
 The flash memory is programmed 128 bytes at a time. Erase is performed in single-block
units. To erase the entire flash memory, each block must be erased in turn.
• Reprogramming capability
 The flash memory can be reprogrammed up to 1,000 times (Min.).
• On-board programming
 On-board programming/erasing can be done in boot mode, in which the boot program built
into the chip is started to erase or program of the entire flash memory. In normal user
program mode, individual blocks can be erased or programmed.
• Programmer mode
 Flash memory can be programmed/erased in programmer mode using a PROM
programmer, as well as in on-board programming mode.
• Automatic bit rate adjustment
 For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match
the transfer bit rate of the host.
• Programming/erasing protection
 Sets software protection against flash memory programming/erasing.
• Power-down mode
 Operation of the power supply circuit can be partly halted in subactive mode. As a result,
flash memory can be read with low power consumption.
7.1 Block Configuration

Figure 7.1 shows the block configuration of flash memory of each product model. The thick lines
indicate erasing units, the narrow lines indicate programming units, and the values are addresses.
Erasing is performed in erasing units shown in these figures. Programming is performed in 128-
byte units starting from an address with lower eight bits H'00 or H'80.
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Section 7 ROM
H8/36079GF
H8/36079LF
H'000000 H'000001 H'000002 Programming unit: 128 bytes H'00007F
Erase unit: 1 Kbyte

H'000380 H'000381 H'000382 H'0003FF
Erase unit: 1 Kbyte

H'000780 H'000781 H'000782 H'0007FF
Erase unit: 1 Kbyte

H'000B80 H'000B81 H'000B82 H'000BFF
H'000C00 H'000C01 H'000C02 Programming unit: 128 bytes H'000C7F
Erase unit: 1 Kbyte

H'000F80 H'000F81 H'000F82 H'000FFF
Erase unit: 28 Kbytes

H'007F80 H'007F81 H'007F82 H'007FFF

H'00FF80 H'00FF81 H'00FF82 H'00FFFF
H'017F80 H'017F81 H'017F82 H'017FFF
Figure 7.1 Flash Memory Block Configuration (1)

(H8/36079GF and H8/36079LF)
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Section 7 ROM
H8/36078GF
H8/36078LF
Erase unit: 1 Kbyte

H'000380 H'000381 H'000382 H'0003FF
Erase unit: 1 Kbyte

H'000780 H'000781 H'000782 H'0007FF
Erase unit: 1 Kbyte

H'000B80 H'000B81 H'000B82 H'000BFF
Erase unit: 1 Kbyte

H'000F80 H'000F81 H'000F82 H'000FFF

H'007F80 H'007F81 H'007F82 H'007FFF

H'017F80 H'017F81 H'017F82 H'017FFF

(H8/36078GF and H8/36078LF)
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Section 7 ROM
H8/36077GF
H8/36077LF
Erase unit: 1 Kbyte

H'0380 H'0381 H'0382 H'03FF

H'0780 H'0781 H'0782 Programming unit: 128 bytes H'07FF
H'0800 H'0801 H'0802 H'087F

H'0B80 H'0B81 H'0B82 H'0BFF

H'0F80 H'0F81 H'0F82 H'0FFF

H'7F80 H'7F81 H'7F82 H'7FFF
H'BF80 H'BF81 H'BF82 H'BFFF
H'C000 H'C001 H'C002 Programming unit: 128 bytes H'C07F
H'DF80 H'DF81 H'DF82 H'DFFF

(H8/36077GF and H8/36077LF)
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Section 7 ROM
H8/36074GF
H8/36074LF
Erase unit: 1 Kbyte

H'0380 H'0381 H'0382 H'03FF
Erase unit: 1 Kbyte

H'0780 H'0781 H'0782 H'07FF
Erase unit: 1 Kbyte

H'0B80 H'0B81 H'0B82 H'0BFF
Erase unit: 1 Kbyte
H'0F80 H'0F81 H'0F82 H'0FFF

H'7F80 H'7F81 H'7F82 H'7FFF

(H8/36074GF and H8/36074LF)
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REJ09B0216-0300
Section 7 ROM

The flash memory has the following registers.
• Flash memory control register 1 (FLMCR1)

• Flash memory control register 2 (FLMCR2)
• Erase block register 1 (EBR1)
• Flash memory power control register (FLPWCR)
• Flash memory enable register (FENR)
7.2.1 Flash Memory Control Register 1 (FLMCR1)
FLMCR1 is a register that makes the flash memory change to program mode, program-verify
mode, erase mode, or erase-verify mode. For details on register setting, refer to section 7.4, Flash
Memory Programming/Erasing.
Initial
6 SWE 0 R/W Software Write Enable
When this bit is set to 1, flash memory
programming/erasing is enabled. When this bit is cleared
to 0, other FLMCR1 register bits and all EBR1 bits cannot
be set.
5 ESU 0 R/W Erase Setup
When this bit is set to 1, the flash memory changes to the
erase setup state. When it is cleared to 0, the erase setup
state is cancelled. Set this bit to 1 before setting the E bit
to 1 in FLMCR1.
4 PSU 0 R/W Program Setup
When this bit is set to 1, the flash memory changes to the
program setup state. When it is cleared to 0, the program
setup state is cancelled. Set this bit to 1 before setting the
P bit in FLMCR1.
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Section 7 ROM
Initial
3 EV 0 R/W Erase-Verify
When this bit is set to 1, the flash memory changes to
erase-verify mode. When it is cleared to 0, erase-verify
mode is cancelled.
2 PV 0 R/W Program-Verify
When this bit is set to 1, the flash memory changes to
program-verify mode. When it is cleared to 0, program-
verify mode is cancelled.
1 E 0 R/W Erase
When this bit is set to 1 while SWE=1 and ESU=1, the
flash memory changes to erase mode. When it is cleared
to 0, erase mode is cancelled.
0 P 0 R/W Program
When this bit is set to 1 while SWE=1 and PSU=1, the
flash memory changes to program mode. When it is
cleared to 0, program mode is cancelled.
7.2.2 Flash Memory Control Register 2 (FLMCR2)
FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a
read-only register, and should not be written to.
Initial
7 FLER 0 R Flash Memory Error
Indicates that an error has occurred during an operation
on flash memory (programming or erasing). When FLER
is set to 1, flash memory goes to the error-protection
state.
See section 7.5.3, Error Protection, for details.
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Section 7 ROM
7.2.3 Erase Block Register 1 (EBR1)
EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit
in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to
be automatically cleared to 0.
(1) H8/36079GF and H8/36079LF
Initial
7 EB7 0 R/W When this bit is set to 1, 32 Kbytes of H'018000 to H'01FFFF will be erased.
6 EB6 0 R/W When this bit is set to 1, 32 Kbytes of H'010000 to H'017FFF will be erased.
5 EB5 0 R/W When this bit is set to 1, H'008000 to H'00FFFF 32 Kbytes of H'010000 to
H'017FFF will be erased.
3 EB3 0 R/W When this bit is set to 1, 1 Kbyte of H'000C00 to H'000FFF will be erased.
2 EB2 0 R/W When this bit is set to 1, 1 Kbyte of H'000800 to H'000BFF will be erased.
1 EB1 0 R/W When this bit is set to 1, 1 Kbyte of H'000400 to H'0007FF will be erased.
(2) H8/36078GF and H8/36078LF
Initial
7  0  Reserved. Although this bit is readable/writable, do not set this bit to 1.
5 EB5 0 R/W When this bit is set to 1, 32 Kbytes of H'008000 to H'00FFFF will be erased.
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Section 7 ROM
(3) H8/36077GF and H8/36077LF
Initial
7  0  Reserved. This bit is always read as 0.
6 EB6 0 R/W When this bit is set to 1, 8 Kbytes of H'C000 to H'DFFF will be erased.
5 EB5 0 R/W When this bit is set to 1, 16 Kbytes of H'8000 to H'BFFF will be erased.
(4) H8/36074GF and H8/36074LF
Initial
7  0  Reserved. This bit is always read as 0.
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REJ09B0216-0300
Section 7 ROM
7.2.4 Flash Memory Power Control Register (FLPWCR)
FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI
switches to subactive mode. There are two modes: mode in which operation of the power supply
circuit of flash memory is partly halted in power-down mode and flash memory can be read, and
mode in which even if a transition is made to subactive mode, operation of the power supply
circuit of flash memory is retained and flash memory can be read.
Initial
7 PDWND 0 R/W Power-Down Disable
When this bit is 0 and a transition is made to subactive
mode, the flash memory enters the power-down mode.
When this bit is 1, the flash memory remains in the
normal mode even after a transition is made to subactive
mode.
7.2.5 Flash Memory Enable Register (FENR)
Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers,
FLMCR1, FLMCR2, EBR1, and FLPWCR.
Initial
7 FLSHE 0 R/W Flash Memory Control Register Enable
Flash memory control registers can be accessed when
this bit is set to 1. Flash memory control registers cannot
be accessed when this bit is set to 0.
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Section 7 ROM
7.3 On-Board Programming Modes

There are two modes for programming/erasing of the flash memory; boot mode, which enables on-
board programming/erasing, and programmer mode, in which programming/erasing is performed
with a PROM programmer. On-board programming/erasing can also be performed in user
program mode. At reset-start in reset mode, this LSI changes to a mode depending on the TEST
pin settings, NMI pin settings, and input level of each port, as shown in table 7.1. The input level
of each pin must be defined four states before the reset ends.
When changing to boot mode, the boot program built into this LSI is initiated. The boot program
transfers the programming control program from the externally connected host to on-chip RAM
via SCI3. After erasing the entire flash memory, the programming control program is executed.
This can be used for programming initial values in the on-board state or for a forcible return when
programming/erasing can no longer be done in user program mode. In user program mode,
individual blocks can be erased and programmed by branching to the user program/erase control
program prepared by the user.
Table 7.1 Setting Programming Modes
TEST NMI P85 PB0 PB1 PB2 LSI State after Reset End
0 1 x x x x User Mode
0 0 1 x x x Boot Mode
1 x x 0 0 0 Programmer Mode
[Legend] x: Don't care.
7.3.1 Boot Mode
Table 7.2 shows the boot mode operations between reset end and branching to the programming
control program.
1. When boot mode is used, the flash memory programming control program must be prepared in
the host beforehand. Prepare a programming control program in accordance with the
description in section 7.4, Flash Memory Programming/Erasing.
2. SCI3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop
bit, and no parity.
3. When the boot program is initiated, the chip measures the low-level period of asynchronous
SCI communication data (H'00) transmitted continuously from the host. The chip then
calculates the bit rate of transmission from the host, and adjusts the SCI3 bit rate to match that
of the host. The reset should end with the RxD pin high. The RxD and TxD pins should be
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Section 7 ROM
pulled up on the board if necessary. After the reset is complete, it takes approximately 100
states before the chip is ready to measure the low-level period.
4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the
completion of bit rate adjustment. The host should confirm that this adjustment end indication
(H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could
not be performed normally, initiate boot mode again by a reset. Depending on the host's
transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between
the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit rate
and system clock frequency of this LSI within the ranges listed in table 7.3.
5. In boot mode, a part of the on-chip RAM area is used by the boot program. The area H'FFF780
to H'FFFEEF for microcontrollers supporting advanced mode or H'F780 to H'FEEF for
microcontrollers supporting normal mode, is the area to which the programming control
program is transferred from the host. The boot program area cannot be used until the execution
state in boot mode switches to the programming control program.
6. Before branching to the programming control program, the chip terminates transfer operations
by SCI3 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value
remains set in BRR. Therefore, the programming control program can still use it for transfer of
program data or verify data with the host. The TxD pin is high (PCR22 = 1, P22 = 1). The
contents of the CPU general registers are undefined immediately after branching to the
programming control program. These registers must be initialized at the beginning of the
programming control program, as the stack pointer (SP), in particular, is used implicitly in
subroutine calls, etc.
7. Boot mode can be cleared by a reset. End the reset after driving the reset pin low, waiting at
least 20 states, and then setting the NMI pin. Boot mode is also cleared when a WDT overflow
occurs.
8. Do not change the TEST pin and NMI pin input levels in boot mode.
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Section 7 ROM
Table 7.2 Boot Mode Operation
Host Operation Communication Contents LSI Operation

Item
Processing Contents Processing Contents

Boot mode initiation
Branches to boot program at reset-start.
Boot program initiation
Continuously transmits data H'00 H'00, H'00 . . . H'00

at specified bit rate. • Measures low-level period of receive data
Bit rate adjustment
H'00.
• Calculates bit rate and sets BRR in SCI3.
H'00 • Transmits data H'00 to host as adjustment
Transmits data H'55 when data H'00
is received error-free. end indication.
H'55
H'55 reception.
Flash memory erase
H'FF
Boot program Checks flash memory data, erases all flash
erase error memory blocks in case of written data
existing, and transmits data H'AA to host.
(If erase could not be done, transmits data
H'AA
H'AA reception H'FF to host and aborts operation.)
Transfer of number of bytes of
programming control program
Upper bytes, lower bytes

Transmits number of bytes (N) of Echobacks the 2-byte data
programming control program to be Echoback received to host.
transferred as 2-byte data
(low-order byte following high-order
byte)
H'XX Echobacks received data to host and also

Transmits 1-byte of programming transfers it to RAM.
Echoback
control program (repeated for N times) (repeated for N times)
H'AA
H'AA reception Transmits data H'AA to host.
Branches to programming control program

transferred to on-chip RAM and starts
execution.
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Section 7 ROM
Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is
Possible
Host Bit Rate System Clock Frequency Range of LSI

9,600 bps 10 MHz
4,800 bps
7.3.2 Programming/Erasing in User Program Mode
On-board programming/erasing of an individual flash memory block can also be performed in user
program mode by branching to a user program/erase control program. The user must set branching
conditions and provide on-board means of supplying programming data. The flash memory must
contain the user program/erase control program or a program that provides the user program/erase
control program from external memory. As the flash memory itself cannot be read during
programming/erasing, transfer the user program/erase control program to on-chip RAM, as in boot
mode. Figure 7.2 shows a sample procedure for programming/erasing in user program mode.
Prepare a user program/erase control program in accordance with the description in section 7.4,
Flash Memory Programming/Erasing.
Reset-start
No
Program/erase?
Yes
Transfer user program/erase control Branch to flash memory application

program to RAM program
Branch to user program/erase control

program in RAM
Execute user program/erase control

program (flash memory rewrite)
Branch to flash memory application

program
Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode
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Section 7 ROM
7.4 Flash Memory Programming/Erasing

A software method using the CPU is employed to program and erase flash memory in the on-
board programming modes. Depending on the FLMCR1 setting, the flash memory operates in one
of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify
mode. The programming control program in boot mode and the user program/erase control
program in user program mode use these operating modes in combination to perform
programming/erasing. Flash memory programming and erasing should be performed in
accordance with the descriptions in section 7.4.1, Program/Program-Verify and section 7.4.2,
Erase/Erase-Verify, respectively.
7.4.1 Program/Program-Verify
When writing data or programs to the flash memory, the program/program-verify flowchart shown
in figure 7.3 should be followed. Performing programming operations according to this flowchart
will enable data or programs to be written to the flash memory without subjecting the chip to
voltage stress or sacrificing program data reliability.
1. Programming must be done to an empty address. Do not reprogram an address to which

programming has already been performed.
2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be
performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the
extra addresses.
3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128-
byte reprogramming data area, and a 128-byte additional-programming data area. Perform
reprogramming data computation according to table 7.4, and additional programming data
computation according to table 7.5.
4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or
additional-programming data area to the flash memory. The program address and 128-byte
data are latched in the flash memory. The lower 8 bits of the start address in the flash memory
destination area must be H'00 or H'80.
5. The time during which the P bit is set to 1 is the programming time. Table 7.6 shows the
allowable programming times.
6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
An overflow cycle of approximately 6.6 ms is allowed.
7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 2 bits
are B'00. Verify data can be read in words or in longwords from the address to which a dummy
write was performed.
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8. The maximum number of repetitions of the program/program-verify sequence of the same bit
is 1,000.
Write pulse application subroutine
Apply Write Pulse START
Set SWE bit in FLMCR1

WDT enable
Wait 1 µs
Set PSU bit in FLMCR1
Store 128-byte program data in program
Wait 50 µs
* data area and reprogram data area
n= 1
Set P bit in FLMCR1
m= 0
Wait (Wait time=programming time)
Write 128-byte data in RAM reprogram
Clear P bit in FLMCR1 data area consecutively to flash memory
Wait 5 µs Apply Write pulse
Clear PSU bit in FLMCR1 Set PV bit in FLMCR1
Wait 4 µs
Wait 5 µs
Set block start address as
Disable WDT verify address
n←n+1
End Sub H'FF dummy write to verify address
Wait 2 µs *
Read verify data
Increment address
Verify data = No
write data?
m=1
Yes
No
n≤6?
Yes
Additional-programming data computation
Reprogram data computation
128-byte
data verification completed?
No
Yes
Clear PV bit in FLMCR1
Wait 2 µs
No
n ≤ 6?
Yes
Successively write 128-byte data from additional-
programming data area in RAM to flash memory
Sub-Routine-Call
Apply Write Pulse
No Yes
m= 0 ? n ≤ 1000 ?
Yes No
Clear SWE bit in FLMCR1 Clear SWE bit in FLMCR1
Wait 100 µs Wait 100 µs
End of programming Programming failure
Note: *The RTS instruction must not be used during the following 1. and 2. periods.
1. A period between 128-byte data programming to flash memory and the P bit clearing
2. A period between dummy writing of H'FF to a verify address and verify data reading
Figure 7.3 Program/Program-Verify Flowchart
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Section 7 ROM
Table 7.4 Reprogram Data Computation Table
Program Data Verify Data Reprogram Data Comments

0 0 1 Programming completed
0 1 0 Reprogram bit
1 0 1 
1 1 1 Remains in erased state
Table 7.5 Additional-Program Data Computation Table
Additional-Program
Reprogram Data Verify Data Data Comments
0 0 0 Additional-program bit
0 1 1 No additional programming
Table 7.6 Programming Time
n Programming In Additional
(Number of Writes) Time Programming Comments
1 to 6 30 10
7 to 1,000 200 
Note: Time shown in µs.
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Section 7 ROM
7.4.2 Erase/Erase-Verify
When erasing flash memory, the erase/erase-verify flowchart shown in figure 7.4 should be
followed.
1. Prewriting (setting erase block data to all 0s) is not necessary.

2. Erasing is performed in block units. Make only a single-bit specification in the erase block
register (EBR1). To erase multiple blocks, each block must be erased in turn.
3. The time during which the E bit is set to 1 is the flash memory erase time.
4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. An
overflow cycle of approximately 19.8 ms is allowed.
5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two
bits are B'00. Verify data can be read in longwords from the address to which a dummy write
was performed.
6. If the read data is not erased successfully, set erase mode again, and repeat the erase/erase-
verify sequence as before. The maximum number of repetitions of the erase/erase-verify
sequence is 100.
7.4.3 Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including the NMI interrupt, are disabled while flash memory is being programmed
or erased, or while the boot program is executing, for the following three reasons:
1. Interrupt during programming/erasing may cause a violation of the programming or erasing

algorithm, with the result that normal operation cannot be assured.
2. If interrupt exception handling starts before the vector address is written or during
programming/erasing, a correct vector cannot be fetched and the CPU malfunctions.
3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be
carried out.
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Section 7 ROM
Erase start
SWE bit ← 1
Wait 1 µs
n←1
Set EBR1
Enable WDT
ESU bit ← 1
Wait 100 µs
E bit ← 1
Wait 10 ms
E bit ← 0
Wait 10 µs
ESU bit ← 10
10 µs
Disable WDT
EV bit ← 1
Wait 20 µs
Set block start address as verify address
H'FF dummy write to verify address
Wait 2 µs *
n←n+1
Read verify data
No
Increment address Verify data + all 1s ?
Yes
No
Last address of block ?
Yes
EV bit ← 0 EV bit ← 0
Wait 4 µs Wait 4µs
No Yes
All erase block erased ? n ≤100 ?
No
Yes
Yes
SWE bit ← 0 SWE bit ← 0
Wait 100 µs Wait 100 µs
End of erasing Erase failure
Note: *The RTS instruction must not be used during a period between dummy writing of H'FF to a verify address and verify data reading.
Figure 7.4 Erase/Erase-Verify Flowchart
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Section 7 ROM
7.5 Program/Erase Protection

There are three kinds of flash memory program/erase protection; hardware protection, software
protection, and error protection.
7.5.1 Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly

disabled or aborted because of a transition to reset, subactive mode, subsleep mode, or standby
mode. Flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2),
and erase block register 1 (EBR1) are initialized. In a reset via the RES pin, the reset state is not
entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of
a reset during operation, hold the RES pin low for the RES pulse width specified in the AC
Characteristics section.
7.5.2 Software Protection
Software protection can be implemented against programming/erasing of all flash memory blocks
by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P or E bit
in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase block
register 1 (EBR1), erase protection can be set for individual blocks. When EBR1 is set to H'00,
erase protection is set for all blocks.
7.5.3 Error Protection
In error protection, an error is detected when CPU runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is forcibly aborted. Aborting the program/erase
operation prevents damage to the flash memory due to overprogramming or overerasing.
When the following errors are detected during programming/erasing of flash memory, the FLER
bit in FLMCR2 is set to 1, and the error protection state is entered.
• When the flash memory of the relevant address area is read during programming/erasing
(including vector read and instruction fetch)
• Immediately after exception handling excluding a reset during programming/erasing
• When a SLEEP instruction is executed during programming/erasing
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The FLMCR1, FLMCR2, and EBR1 settings are retained, however program mode or erase mode
is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-
entered by re-setting the P or E bit. However, PV and EV bit settings are retained, and a transition
can be made to verify mode. Error protection can be cleared only by a reset.
7.6 Programmer Mode

In programmer mode, a PROM programmer can be used to perform programming/erasing via a
socket adapter, just as a discrete flash memory. Use a PROM programmer that supports the MCU
device type with the on-chip 128-kbyte flash memory (FZTAT64V5).
7.7 Power-Down States for Flash Memory

In user mode, the flash memory will operate in either of the following states:
• Normal operating mode

The flash memory can be read and written to at high speed.
• Power-down operating mode
The power supply circuit of flash memory can be partly halted. As a result, flash memory can
be read with low power consumption.
• Standby mode
All flash memory circuits are halted.
Table 7.7 shows the correspondence between the operating modes of this LSI and the flash
memory. In subactive mode, the flash memory can be set to operate in power-down mode with the
PDWND bit in FLPWCR. When the flash memory returns to its normal operating state from
power-down mode or standby mode, a period to stabilize operation of the power supply circuits
that were stopped is needed. When the flash memory returns to its normal operating state, bits
STS2 to STS0 in SYSCR1 must be set to provide a wait time of at least 20 µs, even when the
external clock is being used.
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Section 7 ROM
Table 7.7 Flash Memory Operating States
Flash Memory Operating State

LSI Operating State PDWND = 0 (Initial Value) PDWND = 1
Active mode Normal operating mode Normal operating mode
Subactive mode Power-down mode Normal operating mode
Sleep mode Normal operating mode Normal operating mode
Subsleep mode Standby mode Standby mode
Standby mode Standby mode Standby mode
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Section 8 RAM
Section 8 RAM
Microcontrollers of the H8/36079 Group and H8/36077 Group have an on-chip high-speed static
RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the
CPU to both byte data and word data.
Product Classification RAM Size RAM Address

Flash memory H8/36079 5.0-V specification H8/36079GF 6 Kbytes H'FFE000 to H'FFEFFF,
version Group H'FFF780 to H'FFFF7F*1
3.3-V specification H8/36079LF
(F-ZTAT version)
5.0-V specification H8/36078GF
H8/36077 5.0-V specification H8/36077GF 4 Kbytes H'E800 to H'EFFF,
Group H'F780 to H'FF7F*2
5.0-V specification H8/36074GF
Notes: 1. When the E7 or E8 is used, area H'FFF780 to H'FFFB7F must not be accessed.
2. When the E7 or E8 is used, area H'F780 to H'FB7F must not be accessed.
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Section 8 RAM
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REJ09B0216-0300
Section 9 I/O Ports
Section 9 I/O Ports

This LSI has 47 general I/O ports and 8 general input-only ports. Port 6 is a large current port,
which can drive 20 mA (@VOL = 1.5 V) when a low level signal is output. Any of these ports can
become an input port immediately after a reset. They can also be used as I/O pins of the on-chip
peripheral modules or external interrupt input pins, and these functions can be switched depending
on the register settings. The registers for selecting these functions can be divided into two types:
those included in I/O ports and those included in each on-chip peripheral module. General I/O
ports are comprised of the port control register for controlling inputs/outputs and the port data
register for storing output data and can select inputs/outputs in bit units.
For functions in each port, see appendix B.1, I/O Port Block Diagrams. For the execution of bit-
manipulation instructions to the port control register and port data register, see section 2.8.3, Bit-
Manipulation Instruction.
9.1 Port 1
Port 1 is a general I/O port also functioning as IRQ interrupt input pins, an RTC output pin, a 14-
bit PWM output pin, a timer B1 input pin, and a timer V input pin. Figure 9.1 shows its pin
configuration.
P17/IRQ3/TRGV
P16/IRQ2
P15/IRQ1/TMIB1
Port 1
P14/IRQ0
P12
P11/PWM
P10/TMOW
Figure 9.1 Port 1 Pin Configuration
Port 1 has the following registers.
• Port mode register 1 (PMR1)

• Port control register 1 (PCR1)
• Port data register 1 (PDR1)
• Port pull-up control register 1 (PUCR1)
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Section 9 I/O Ports
9.1.1 Port Mode Register 1 (PMR1)
PMR1 switches the functions of pins in port 1 and port 2.
Initial
7 IRQ3 0 R/W This bit selects the function of pin P17/IRQ3/TRGV.
0: General I/O port
1: IRQ3/TRGV input pin
6 IRQ2 0 R/W This bit selects the function of pin P16/IRQ2.
0: General I/O port
1: IRQ2 input pin
5 IRQ1 0 R/W This bit selects the function of pin P15/IRQ1/TMIB1.
0: General I/O port
1: IRQ1/TMIB1 input pin
4 IRQ0 0 R/W This bit selects the function of pin P14/IRQ0.
0: General I/O port
1: IRQ0 input pin
3 TXD2 0 R/W This bit selects the function of pin P72/TXD_2.
0: General I/O port
1: TXD_2 output pin
2 PWM 0 R/W This bit selects the function of pin P11/PWM.
0: General I/O port
1: PWM output pin
1 TXD 0 R/W This bit selects the function of pin P22/TXD.
0: General I/O port
1: TXD output pin
0 TMOW 0 R/W This bit selects the function of pin P10/TMOW.
0: General I/O port
1: TMOW output pin
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Section 9 I/O Ports
9.1.2 Port Control Register 1 (PCR1)
PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1.
Initial
7 PCR17 0 W When the corresponding pin is designated in PMR1 as a
6 PCR16 0 W general I/O pin, setting a PCR1 bit to 1 makes the
corresponding pin an output port, while clearing the bit to
5 PCR15 0 W 0 makes the pin an input port.
4 PCR14 0 W Bit 3 is a reserved bit.
3   
2 PCR12 0 W
1 PCR11 0 W
0 PCR10 0 W
9.1.3 Port Data Register 1 (PDR1)
PDR1 is a general I/O port data register of port 1.
Initial
7 P17 0 R/W PDR1 stores output data for port 1 pins.
6 P16 0 R/W If PDR1 is read while PCR1 bits are set to 1, the value
5 P15 0 R/W stored in PDR1 are read. If PDR1 is read while PCR1 bits
are cleared to 0, the pin states are read regardless of the
4 P14 0 R/W value stored in PDR1.
3  1  Bit 3 is a reserved bit. This bit is always read as 1.
2 P12 0 R/W
1 P11 0 R/W
0 P10 0 R/W
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Section 9 I/O Ports
9.1.4 Port Pull-Up Control Register 1 (PUCR1)
PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports.
Initial
7 PUCR17 0 R/W Only bits for which PCR1 is cleared are valid. The pull-up
6 PUCR16 0 R/W MOS of P17 to P14 and P12 to P10 pins enter the on-
state when these bits are set to 1, while they enter the
5 PUCR15 0 R/W off-state when these bits are cleared to 0.
4 PUCR14 0 R/W Bit 3 is a reserved bit. This bit is always read as 1.
3  1 
2 PUCR12 0 R/W
1 PUCR11 0 R/W
0 PUCR10 0 R/W
9.1.5 Pin Functions
The correspondence between the register specification and the port functions is shown below.
P17/IRQ3/TRGV pin
Register PMR1 PCR1

Bit Name IRQ3 PCR17 Pin Function
Setting value 0 0 P17 input pin
1 P17 output pin
1 x IRQ3 input/TRGV input pin
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Section 9 I/O Ports
P16/IRQ2 pin
Register PMR1 PCR1

1 P16 output pin
1 x IRQ2 input pin
P15/IRQ1/TMIB1 pin
Register PMR1 PCR1

1 P15 output pin
1 x IRQ1 input/TMIB1 input pin
P14/IRQ0 pin
Register PMR1 PCR1

1 P14 output pin
1 x IRQ0 input pin
P12 pin
Register PCR1
Bit Name PCR12 Pin Function
Setting value 0 P12 input pin
1 P12 output pin
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Section 9 I/O Ports
P11/PWM pin
Register PMR1 PCR1

Bit Name PWM PCR11 Pin Function
1 P11 output pin
1 x PWM output pin
P10/TMOW pin
Register PMR1 PCR1

Bit Name TMOW PCR10 Pin Function
1 P10 output pin
1 x TMOW output pin
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Section 9 I/O Ports
9.2 Port 2
Port 2 is a general I/O port also functioning as SCI3 I/O pins. Each pin of the port 2 is shown in
figure 9.2. The register settings of PMR1and SCI3 have priority for functions of the pins for both
uses.
P24
P23
Port 2 P22/TXD
P21/RXD
P20/SCK3

Initial
7 to 5    Reserved
4 PCR24 0 W When each of the port 2 pins P24 to P20 functions as a
3 PCR23 0 W general I/O port, setting a PCR2 bit to 1 makes the
1 PCR21 0 W
0 PCR20 0 W
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Section 9 I/O Ports
Initial
2 P22 0 R/W stored in PDR2 is read. If PDR2 is read while PCR2 bits
0 P20 0 R/W
PMR3 selects the CMOS output or NMOS open-drain output for port 2.
Initial
4 POF24 0 R/W When the bit is set to 1, the corresponding pin is cut off
3 POF23 0 R/W by PMOS and it functions as the NMOS open-drain
output. When cleared to 0, the pin functions as the CMOS
output.
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Section 9 I/O Ports
9.2.4 Pin Functions
P24 pin
Register PCR2
Setting Value 0 P24 input pin
1 P24 output pin
P23 pin
Register PCR2
1 P23 output pin
P22/TXD pin
Register PMR1 PCR2

Bit Name TXD PCR22 Pin Function
Setting Value 0 0 P22 input pin
1 P22 output pin
1 x TXD output pin
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Section 9 I/O Ports
P21/RXD pin
Register SCR3 PCR2

Bit Name RE PCR21 Pin Function
1 P21 output pin
1 x RXD input pin
P20/SCK3 pin
Register SCR3 SMR PCR2

Bit Name CKE1 CKE0 COM PCR20 Pin Function
Setting Value 0 0 0 0 P20 input pin
1 P20 output pin
0 0 1 x SCK3 output pin
0 1 x x SCK3 output pin
1 x x x SCK3 input pin
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Section 9 I/O Ports
9.3 Port 3
Port 3 is a general I/O port. Each pin of the port 3 is shown in figure 9.3.
P37
P36
P35
Port 3 P34
P33
P32
P31
P30

Initial
7 PCR37 0 W Setting a PCR3 bit to 1 makes the corresponding pin an
6 PCR36 0 W output port, while clearing the bit to 0 makes the pin an
input port.
5 PCR35 0 W
4 PCR34 0 W
3 PCR33 0 W
2 PCR32 0 W
1 PCR31 0 W
0 PCR30 0 W
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Section 9 I/O Ports
Initial
3 P33 0 R/W
2 P32 0 R/W
1 P31 0 R/W
0 P30 0 R/W
9.3.3 Pin Functions
P37 pin
Register PCR3
1 P37 output pin
P36 pin
Register PCR3
1 P36 output pin
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Section 9 I/O Ports
P35 pin
Register PCR3
1 P35 output pin
P34 pin
Register PCR3
1 P34 output pin
P33 pin
Register PCR3
1 P33 output pin
P32 pin
Register PCR3
1 P32 output pin
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Section 9 I/O Ports
P31 pin
Register PCR3
1 P31 output pin
P30 pin
Register PCR3
1 P30 output pin
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Section 9 I/O Ports
9.4 Port 5
2
Port 5 is a general I/O port also functioning as an I C bus interface I/O pin, an A/D trigger input
pin, and wakeup interrupt input pin. Each pin of the port 5 is shown in figure 9.4. The register
2
setting of the I C bus interface register has priority for functions of the pins P57/SCL and
P56/SDA. Since the output buffer for pins P56 and P57 has the NMOS push-pull structure, it
differs from an output buffer with the CMOS structure in the high-level output characteristics (see
section 22, Electrical Characteristics).
P57/SCL
P56/SDA
P55/WKP5/ADTRG
P54/WKP4
Port 5
P53/WKP3
P52/WKP2
P51/WKP1
P50/WKP0

• Port pull-up control register 5 (PUCR5)
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REJ09B0216-0300
Section 9 I/O Ports
PMR5 switches the functions of pins in port 5.
Initial
7 POF57 0 R/W When the bit is set to 1, the corresponding pin is cut off
6 POF56 0 R/W by PMOS and it functions as the NMOS open-drain
output. When cleared to 0, the pin functions as the CMOS
output.
5 WKP5 0 R/W This bit selects the function of pin P55/WKP5/ADTRG.
0: General I/O port
1: WKP5/ADTRG input pin
4 WKP4 0 R/W This bit selects the function of pin P54/WKP4.
0: General I/O port
1: WKP4 input pin
0: General I/O port
1: WKP3 input pin
0: General I/O port
1: WKP2 input pin
0: General I/O port
1: WKP1 input pin
0: General I/O port
1: WKP0 input pin
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Section 9 I/O Ports
Initial
4 PCR54 0 W
3 PCR53 0 W
2 PCR52 0 W
1 PCR51 0 W
0 PCR50 0 W
Initial
7 P57 0 R/W Stores output data for port 5 pins.
3 P53 0 R/W
2 P52 0 R/W
1 P51 0 R/W
0 P50 0 R/W
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REJ09B0216-0300
Section 9 I/O Ports
9.4.4 Port Pull-Up Control Register 5 (PUCR5)
PUCR5 controls the pull-up MOS in bit units of the pins set as the input ports.
Initial
5 PUCR55 0 R/W Only bits for which PCR5 is cleared are valid. The pull-up
4 PUCR54 0 R/W MOS of the corresponding pins enter the on-state when
these bits are set to 1, while they enter the off-state when
3 PUCR53 0 R/W these bits are cleared to 0.
2 PUCR52 0 R/W
1 PUCR51 0 R/W
0 PUCR50 0 R/W
9.4.5 Pin Functions
P57/SCL pin
Register ICCR1 PCR5

Bit Name ICE PCR57 Pin Function
1 P57 output pin
1 x SCL I/O pin
SCL performs the NMOS open-drain output, that enables a direct bus drive.
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Section 9 I/O Ports
P56/SDA pin
Register ICCR1 PCR5

Bit Name ICE PCR56 Pin Function
1 P56 output pin
1 x SDA I/O pin
SDA performs the NMOS open-drain output that enables a direct bus drive.
P55/WKP5/ADTRG pin
Register PMR5 PCR5

Bit Name WKP5 PCR55 Pin Function
1 P55 output pin
1 x WKP5/ADTRG input pin
P54/WKP4 pin
Register PMR5 PCR5

1 P54 output pin
1 x WKP4 input pin
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Section 9 I/O Ports
P53/WKP3 pin
Register PMR5 PCR5

1 P53 output pin
1 x WKP3 input pin
P52/WKP2 pin
Register PMR5 PCR5

1 P52 output pin
1 x WKP2 input pin
P51/WKP1 pin
Register PMR5 PCR5

1 P51 output pin
1 x WKP1 input pin
P50/WKP0 pin
Register PMR5 PCR5

1 P50 output pin
1 x WKP0 input pin
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Section 9 I/O Ports
9.5 Port 6
Port 6 is a general I/O port also functioning as a timer Z I/O pin. Each pin of the port 6 is shown in
figure 9.5. The register setting of the timer Z has priority for functions of the pins for both uses.
P67/FTIOD1
P66/FTIOC1
P65/FTIOB1
Port 6 P64/FTIOA1
P63/FTIOD0
P62/FTIOC0
P61/FTIOB0
P60/FTIOA0

Initial
4 PCR64 0 W
3 PCR63 0 W
2 PCR62 0 W
1 PCR61 0 W
0 PCR60 0 W
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Section 9 I/O Ports
Initial
7 P67 0 R/W Stores output data for port 6 pins.
3 P63 0 R/W
2 P62 0 R/W
1 P61 0 R/W
0 P60 0 R/W
9.5.3 Pin Functions
P67/FTIOD1 pin
Register TOER TFCR TPMR TIORC1 PCR6

CMD1 and IOD2 to
Bit Name ED1 CMD0 PWMD1 IOD0 PCR67 Pin Function
Setting Value 1 00 0 000 or 0 P67 input/FTIOD1 input pin
1xx
1 P67 output pin
0 00 0 001 or x FTIOD1 output pin
01x
1 xxx
Other than x xxx
00
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Section 9 I/O Ports
P66/FTIOC1 pin

CMD1 and IOC2 to
Bit Name EC1 CMD0 PWMC1 IOC0 PCR66 Pin Function
Setting Value 1 00 0 000 or 0 P66 input/FTIOC1 input pin
1xx
1 P66 output pin
0 00 0 001 or x FTIOC1 output pin
01x
1 xxx
Other than x xxx
00
P65/FTIOB1 pin
Register TOER TFCR TPMR TIORA1 PCR6

CMD1 to IOB2 to
Bit Name EB1 CMD0 PWMB1 IOB0 PCR65 Pin Function
Setting Value 1 00 0 000 or 0 P65 input/FTIOB1 input pin
1xx
1 P65 output pin
0 00 0 001 or x FTIOB1 output pin
01x
1 xxx
Other than x xxx
00
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Section 9 I/O Ports
P64/FTIOA1 pin
Register TOER TFCR TIORA1 PCR6

CMD1 to IOA2 to
Bit Name EB1 CMD0 IOA0 PCR64 Pin Function
Setting Value 1 xx 000 or 0 P64 input/FTIOA1 input pin
1xx
1 P64 output pin
0 00 001 or x FTIOA1 output pin
01x
P63/FTIOD0 pin

CMD1 to IOD2 to
Bit Name ED0 CMD0 PWMD0 IOD0 PCR63 Pin Function
Setting Value 1 00 0 000 or 0 P63 input/FTIOD0 input pin
1xx
1 P63 output pin
0 00 0 001 or x FTIOD0 output pin
01x
1 xxx
Other than x xxx
00
P62/FTIOC0 pin

CMD1 to IOC2 to
Bit Name EC0 CMD0 PWMC0 IOC0 PCR62 Pin Function
Setting Value 1 00 0 000 or 0 P62 input/FTIOC0 input pin
1xx
1 P62 output pin
0 00 0 001 or x FTIOC0 output pin
01x
1 xxx
Other than x xxx
00
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Section 9 I/O Ports
P61/FTIOB0 pin
Register TOER TFCR TPMR TIORA0 PCR6

CMD1 to IOB2 to
Bit Name EB0 CMD0 PWMB0 IOB0 PCR61 Pin Function
Setting Value 1 00 0 000 or 0 P61 input/FTIOB0 input pin
1xx
1 P61 output pin
0 00 0 001 or x FTIOB0 output pin
01x
1 xxx
Other than x xxx
00
P60/FTIOA0 pin
Register TOER TFCR TFCR TIORA0 PCR6

CMD1 to IOA2 to
Bit Name EA0 CMD0 STCLK IOA0 PCR60 Pin Function
Setting Value 1 xx x 000 or 0 P60 input/FTIOA0 input pin
1xx
1 P60 output pin
0 00 0 001 or x FTIOA0 output pin
01x
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REJ09B0216-0300
Section 9 I/O Ports
9.6 Port 7
Port 7 is a general I/O port also functioning as a timer V I/O pin and SCI3_2 I/O pin. Each pin of
the port 7 is shown in figure 9.6. The register settings of the timer V and SCI3_2 have priority for
functions of the pins for both uses.
P76/TMOV
P75/TMCIV
P74/TMRIV
Port 7
P72/TXD_2
P71/RXD_2
P70/SCK3_2

Initial
7    When each of the port 7 pins P76 to P74 and P72 to P70
6 PCR76 0 W functions as a general I/O port, setting a PCR7 bit to 1
makes the corresponding pin an output port, while
5 PCR75 0 W clearing the bit to 0 makes the pin an input port.
4 PCR74 0 W Bits 7 and 3 are reserved bits.
3   
2 PCR72 0 W
1 PCR71 0 W
0 PCR70 0 W
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REJ09B0216-0300
Section 9 I/O Ports
Initial
7  1  Stores output data for port 7 pins.
3  1  Bits 7 and 3 are reserved bits. These bits are always read
2 P72 0 R/W as 1.
1 P71 0 R/W
0 P70 0 R/W
9.6.3 Pin Functions
P76/TMOV pin
Register TCSRV PCR7

Bit Name OS3 to OS0 PCR76 Pin Function
1 P76 output pin
Other than x TMOV output pin
the above
values
P75/TMCIV pin
Register PCR7
Setting Value 0 P75 input/TMCIV input pin
1 P75 output/TMCIV input pin
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REJ09B0216-0300
Section 9 I/O Ports
P74/TMRIV pin
Register PCR7
Setting Value 0 P74 input/TMRIV input pin
1 P74 output/TMRIV input pin
P72/TXD_2 pin
Register PMR1 PCR7

Bit Name TXD2 PCR72 Pin Function
1 P72 output pin
1 x TXD_2 output pin
P71/RXD_2 pin
Register SCR3_2 PCR7

Bit Name RE PCR71 Pin Function
1 P71 output pin
1 x RXD_2 input pin
P70/SCK3_2 pin
Register SCR3_2 SMR2 PCR7

Bit Name CKE1 CKE0 COM PCR70 Pin Function
Setting Value 0 0 0 0 P70 input pin
1 P70 output pin
0 0 1 x SCK3_2 output pin
0 1 x x SCK3_2 output pin
1 x x x SCK3_2 input pin
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REJ09B0216-0300
Section 9 I/O Ports
9.7 Port 8
Port 8 is a general I/O port. Each pin of the port 8 is shown in figure 9.7.
P87
Port 8 P86
P85

Initial

Initial
value stored in PDR8.
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Section 9 I/O Ports
9.7.3 Pin Functions
P87 pin
Register PCR8
1 P87 output pin
P86 pin
Register PCR8
1 P86 output pin
P85 pin
Register PCR8
1 P85 output pin
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REJ09B0216-0300
Section 9 I/O Ports
9.8 Port B
Port B is an input port also functioning as an A/D converter analog input pin. Each pin of the port
B is shown in figure 9.8.
PB7/AN7/ExtU
PB6/AN6/ExtD
PB5/AN5
PB4/AN4
Port B
PB3/AN3
PB2/AN2
PB1/AN1
PB0/AN0
Figure 9.8 Port B Pin Configuration
Port B has the following register.
• Port data register B (PDRB)
9.8.1 Port Data Register B (PDRB)
PDRB is a general input-only port data register of port B.
Initial
7 PB7  R The input value of each pin is read by reading this
6 PB6  R register.
5 PB5  R However, if a port B pin is designated as an analog input

channel by ADCSR in the A/D converter or as an external
4 PB4  R comparison voltage input pin by LVDCR in the low-
3 PB3  R voltage detection circuit, the corresponding bit is read
as 0.
2 PB2  R
1 PB1  R
0 PB0  R
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Section 9 I/O Ports
9.8.2 Pin Functions
PB0/AN0 pin
Register ADCSR
Bit Name SCAN CH2 CH1 CH0 Pin Function
Setting Value 0 0 0 0 AN0 input pin
1 x x
Other than above PB0 output pin
PB1/AN1 pin
Register ADCSR
1 0 1
1 x
PB2/AN2 pin
Register ADCSR
1 1 x
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REJ09B0216-0300
Section 9 I/O Ports
PB3/AN3 pin
Register ADCSR
1
PB4/AN4 pin
Register ADCSR
1 x x
PB5/AN5 pin
Register ADCSR
1 0 1
1 x
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Section 9 I/O Ports
PB6/AN6/ExtD pin
Register ADCSR LVDCR

Bit Name SCAN CH2 CH1 CH0 VDDII Pin Function
Setting Value 0 1 0 0 AN6 input/ExtD
input pin
1 x
0 0 1 AN6 input pin
1 x
Other than above 0 PB6 input/ExtD
input pin
1 PB6 input pin
PB7/AN7/ExtU pin
Register ADCSR LVDCR

Bit Name SCAN CH2 CH1 CH0 VDDII Pin Function
Setting Value 0 1 0 AN7 input/ExtU
input pin
1
0 1 AN7 input pin
1
Other than above 0 PB7 input/ExtU
input pin
1 PB7 input pin
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REJ09B0216-0300
Section 9 I/O Ports
9.9 Port C
Port C is a general I/O port also functioning as an external oscillation pin and clock output pin.
Each pin of the port C is shown in figure 9.9. The register setting of CKCSR has priority for
functions of the pins for both uses.
Port C PC1/OSC2/CLKOUT
PC0/OSC1
Figure 9.9 Port C Pin Configuration
Port C has the following registers.
• Port control register C (PCRC)

• Port data register C (PDRC)
9.9.1 Port Control Register C (PCRC)
PCRC selects inputs/outputs in bit units for pins to be used as general I/O ports of port C.
Initial
1 PCRC1 0 W When each of the port C pins, PC1 and PC0, functions as
0 PCRC0 0 W an general I/O port, setting a PCRC bit to 1 makes the
0 makes the pin an input port.
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REJ09B0216-0300
Section 9 I/O Ports
9.9.2 Port Data Register C (PDRC)
PDRC is a general I/O port data register of port C.
Initial
1 PC1 0 R/W These bits store output data for port C pins.
0 PC0 0 R/W If PDRC is read while PCRC bits are set to 1, the value
stored in PDRC is read. If PDRC is read while PCRC bits
value stored in PDRC.
9.9.3 Pin Functions
PC1/OSC2/CLKOUT pin
Register CKCSR PCRC

Bit Name PMRC1 PMRC0 PCRC1 Pin Function
Setting value 0 0 0 PC1 input pin
1 PC1 output pin
1 x Open
1 0 x CLKOUT output pin
1 x OSC2 oscillation pin
PC0/OSC1 pin
Register CKCSR PCRC

Bit Name PMRC0 PCRC0 Pin Function
Setting value 0 0 PC0 input pin
1 PC0 output pin
1 x OSC1 oscillation pin
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REJ09B0216-0300

The realtime clock (RTC) is a timer used to count time ranging from a second to a week. Figure
10.1 shows the block diagram of the RTC.
10.1 Features
• Counts seconds, minutes, hours, and day-of-week
• Start/stop function
• Reset function
• Readable/writable counter of seconds, minutes, hours, and day-of-week with BCD codes
• Periodic (seconds, minutes, hours, days, and weeks) interrupts
• 8-bit free running counter
• Selection of clock source
PSS RTCCSR
32-kHz
oscillator 1/4 RSECDR
circuit
RMINDR
Internal data bus

RHRDR
TMOW Clock count

control circuit RWKDR
RTCCR1
RTCCR2
Interrupt
Interrupt
[Legend] control circuit
RTCCSR: Clock source select register
RSECDR: Second date register/free running counter data register
RMINDR: Minute date register
RHRDR: Hour date register
RWKDR: Day-of-week date register
RTCCR1: RTC control register 1
RTCCR2: RTC control register 2
PSS: Prescaler S
Figure 10.1 Block Diagram of RTC
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10.2 Input/Output Pin

Table 10.1 shows the RTC input/output pin.
Table 10.1 Pin Configuration
Name Abbreviation I/O Function

Clock output TMOW Output RTC divided clock output
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REJ09B0216-0300

The RTC has the following registers.
• Second data register/free running counter data register (RSECDR)

• Minute data register (RMINDR)
• Hour data register (RHRDR)
• Day-of-week data register (RWKDR)
• RTC control register 1 (RTCCR1)
• RTC control register 2 (RTCCR2)
• Clock source select register (RTCCSR)
10.3.1 Second Data Register/Free Running Counter Data Register (RSECDR)
RSECDR counts the BCD-coded second value. The setting range is decimal 00 to 59. It is an 8-bit
read register used as a counter, when it operates as a free running counter. For more information
on reading seconds, minutes, hours, and day-of-week, see section 10.4.3, Data Reading Procedure.
Initial
7 BSY — R RTC Busy
This bit is set to 1 when the RTC is updating (operating)
the values of second, minute, hour, and day-of-week
data registers. When this bit is 0, the values of second,
minute, hour, and day-of-week data registers must be
adopted.
6 SC12 — R/W Counting Ten's Position of Seconds
5 SC11 — R/W Counts on 0 to 5 for 60-second counting.
4 SC10 — R/W
3 SC03 — R/W Counting One's Position of Seconds
2 SC02 — R/W Counts on 0 to 9 once per second. When a carry is
1 SC01 — R/W generated, 1 is added to the ten's position.
0 SC00 — R/W
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REJ09B0216-0300
10.3.2 Minute Data Register (RMINDR)
RMINDR counts the BCD-coded minute value on the carry generated once per minute by the
RSECDR counting. The setting range is decimal 00 to 59.
Initial
adopted.
6 MN12 — R/W Counting Ten's Position of Minutes
5 MN11 — R/W Counts on 0 to 5 for 60-minute counting.
4 MN10 — R/W
3 MN03 — R/W Counting One's Position of Minutes
2 MN02 — R/W Counts on 0 to 9 once per minute. When a carry is
1 MN01 — R/W generated, 1 is added to the ten's position.
0 MN00 — R/W
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REJ09B0216-0300
10.3.3 Hour Data Register (RHRDR)
RHRDR counts the BCD-coded hour value on the carry generated once per hour by RMINDR.
The setting range is either decimal 00 to 11 or 00 to 23 by the selection of the 12/24 bit in
RTCCR1.
Initial
adopted.
6 — 0 — Reserved
5 HR11 — R/W Counting Ten's Position of Hours
4 HR10 — R/W Counts on 0 to 2 for ten's position of hours.
3 HR03 — R/W Counting One's Position of Hours
2 HR02 — R/W Counts on 0 to 9 once per hour. When a carry is
1 HR01 — R/W generated, 1 is added to the ten's position.
0 HR00 — R/W
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REJ09B0216-0300
10.3.4 Day-of-Week Data Register (RWKDR)
RWKDR counts the BCD-coded day-of-week value on the carry generated once per day by
RHRDR. The setting range is decimal 0 to 6 using bits WK2 to WK0.
Initial
adopted.
6 to 3 — All 0 — Reserved
2 WK2 — R/W Day-of-Week Counting
1 WK1 — R/W Day-of-week is indicated with a binary code
0 WK0 — R/W 000: Sunday
001: Monday
010: Tuesday
011: Wednesday
100: Thursday
101: Friday
110: Saturday
111: Reserved (setting prohibited)
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10.3.5 RTC Control Register 1 (RTCCR1)
RTCCR1 controls start/stop and reset of the clock timer. For the definition of time expression, see
figure 10.2.
Initial
7 RUN — R/W RTC Operation Start
0: Stops RTC operation
1: Starts RTC operation
6 12/24 — R/W Operating Mode
0: RTC operates in 12-hour mode. RHRDR counts on 0
to 11.
1: RTC operates in 24-hour mode. RHRDR counts on 0
to 23.
5 PM — R/W a.m./p.m.
0: Indicates a.m. when RTC is in the 12-hour mode.
1: Indicates p.m. when RTC is in the 12-hour mode.
4 RST 0 R/W Reset
0: Normal operation
1: Resets registers and control circuits except RTCCSR
and this bit. Clear this bit to 0 after having been set to
1.
3 INT — R/W Interrupt Generation Timing
0: Generates a second, minute, hour, or day-of-week
periodic interrupt during RTC busy period.
1: Generates a second, minute, hour, or day-of-week
periodic interrupt immediately after completing RTC
busy period.
Noon
24-hour count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
12-hour count 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5
PM 0 (Morning) 1 (Afternoon)
24-hour count 18 19 20 21 22 23 0
12-hour count 6 7 8 9 10 11 0
PM 1 (Afternoon) 0
Figure 10.2 Definition of Time Expression
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10.3.6 RTC Control Register 2 (RTCCR2)
RTCCR2 controls RTC periodic interrupts of weeks, days, hours, minutes, and seconds. Enabling
interrupts of weeks, days, hours, minutes, and seconds sets the IRRTA flag to 1 in the interrupt
flag register 1 (IRR1) when an interrupt occurs. It also controls an overflow interrupt of a free
running counter when RTC operates as a free running counter.
Initial
7, 6 — All 0 — Reserved
5 FOIE — R/W Free Running Counter Overflow Interrupt Enable
0: Disables an overflow interrupt
1: Enables an overflow interrupt
4 WKIE — R/W Week Periodic Interrupt Enable
0: Disables a week periodic interrupt
1: Enables a week periodic interrupt
3 DYIE — R/W Day Periodic Interrupt Enable
0: Disables a day periodic interrupt
1: Enables a day periodic interrupt
2 HRIE — R/W Hour Periodic Interrupt Enable
0: Disables an hour periodic interrupt
1: Enables an hour periodic interrupt
1 MNIE — R/W Minute Periodic Interrupt Enable
0: Disables a minute periodic interrupt
1: Enables a minute periodic interrupt
0 SEIE — R/W Second Periodic Interrupt Enable
0: Disables a second periodic interrupt
1: Enables a second periodic interrupt
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REJ09B0216-0300
10.3.7 Clock Source Select Register (RTCCSR)
RTCCSR selects clock source. A free running counter controls start/stop of counter operation by
the RUN bit in RTCCR1. When a clock other than 32.768 kHz is selected, the RTC is disabled
and operates as an 8-bit free running counter. When the RTC operates as an 8-bit free running
counter, RSECDR enables counter values to be read. An interrupt can be generated by setting 1 to
the FOIE bit in RTCCR2 and enabling an overflow interrupt of the free running counter. A clock
in which the system clock is divided by 32, 16, 8, or 4 is output in active or sleep mode.
Initial
6 RCS6 0 R/W Clock Output Selection
5 RCS5 0 R/W Selects a clock output from the TMOW pin when setting
TMOW in PMR1 to 1.
00: φ/4
01: φ/8
10: φ/16
11: φ/32
3 RCS3 1 R/W Clock Source Selection
2 RCS2 0 R/W 0000: φ/8⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
1 RCS1 0 R/W 0001: φ/32⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0 RCS0 0 R/W 0010: φ/128⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0011: φ/256⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0100: φ/512⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0101: φ/2048⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
1XXX: 32.768 kHz⋅⋅⋅RTC operation
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10.4 Operation
10.4.1 Initial Settings of Registers after Power-On
The RTC registers that store second, minute, hour, and day-of week data are not reset by a RES
input. Therefore, all registers must be set to their initial values after power-on. Once the register
setting are made, the RTC provides an accurate time as long as power is supplied regardless of a
RES input.
10.4.2 Initial Setting Procedure
Figure 10.3 shows the procedure for the initial setting of the RTC. To set the RTC again, also
follow this procedure.
RUN in RTCCR1=0 RTC operation is stopped.
RST in RTCCR1=1
RTC registers and clock count
RST in RTCCR1=0 controller are reset.
Set RTCCSR, RSECDR,

RMINDR,RHRDR, Clock output and clock source are
RWKDR,12/24 in selected and second, minute, hour,
RTCCR1, and PM day-of-week,operating mode, and
a.m/p.m are set.
RUN in RTCCR1=1 RTC operation is started.
Figure 10.3 Initial Setting Procedure
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REJ09B0216-0300
10.4.3 Data Reading Procedure
When the seconds, minutes, hours, or day-of-week datum is updated while time data is being read,
the data obtained may not be correct, and so the time data must be read again. Figure 10.4 shows
an example in which correct data is not obtained. In this example, since only RSECDR is read
after data update, about 1-minute inconsistency occurs.
To avoid reading in this timing, the following processing must be performed.
1. Check the setting of the BSY bit, and when the BSY bit changes from 1 to 0, read from the
second, minute, hour, and day-of-week registers. When about 62.5 ms is passed after the BSY
bit is set to 1, the registers are updated, and the BSY bit is cleared to 0.
2. Making use of interrupts, read from the second, minute, hour, and day-of week registers after
the IRRTA flag in IRR1 is set to 1 and the BSY bit is confirmed to be 0.
3. Read from the second, minute, hour, and day-of week registers twice in a row, and if there is
no change in the read data, the read data is used.
Before update RWKDR = H'03, RHDDR = H'13, RMINDR = H'46, RSECDR = H'59
BSY bit = 0
(1) Day-of-week data register read H'03
Processing flow
(2) Hour data register read H'13

(3) Minute data register read H'46
BSY bit -> 1 (under data update)

After update RWKDR = H'03, RHDDR = H'13, RMINDR = H'47, RSECDR = H'00
BSY bit -> 0
(4) Second data register read H'00
Figure 10.4 Example: Reading of Inaccurate Time Data
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REJ09B0216-0300
10.5 Interrupt Sources

There are five kinds of RTC interrupts: week interrupts, day interrupts, hour interrupts, minute
interrupts, and second interrupts.
When using an interrupt, initiate the RTC last after other registers are set. Do not set multiple
interrupt enable bits in RTCCR2 simultaneously to 1.
When an interrupt request of the RTC occurs, the IRRTA flag in IRR1 is set to 1. When clearing
the flag, write 0.
Table 10.2 Interrupt Sources
Interrupt Name Interrupt Source Interrupt Enable Bit

Overflow interrupt Occurs when the free running counter is FOIE
overflowed.
Week periodic interrupt Occurs every week when the day-of-week WKIE
date register value becomes 0.
Day periodic interrupt Occurs every day when the day-of-week date DYIE
register is counted.
Hour periodic interrupt Occurs every hour when the hour date HRIE
Minute periodic interrupt Occurs every minute when the minute date MNIE
Second periodic interrupt Occurs every second when the second date SCIE
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REJ09B0216-0300
Section 11 Timer B1
Section 11 Timer B1
Timer B1 is an 8-bit timer that increments each time a clock pulse is input. This timer has two
operating modes, interval and auto reload. Figure 11.1 shows a block diagram of timer B1.
11.1 Features
• Selection of seven internal clock sources (φ/8192, φ/2048, φ/512, φ/256, φ/64, φ/16, and φ/4) or
an external clock (can be used to count external events).
• An interrupt is generated when the counter overflows.
TMB1
Internal data bus

φ PSS
TCB1
TMIB1
TLB1
[Legend]
TMB1: Timer mode register B1
TCB1: Timer counter B1 IRRTB1
TLB1: Timer load register B1
IRRTB1: Timer B1 interrupt request flag
PSS: Prescaler S
TMIB1: Timer B1 event input
Figure 11.1 Block Diagram of Timer B1
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Section 11 Timer B1

Table 11.1 shows the timer B1 pin configuration.

Timer B1 event input TMIB1 Input Event input to TCB1
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Section 11 Timer B1

The timer B1 has the following registers.
• Timer mode register B1 (TMB1)

• Timer counter B1 (TCB1)
• Timer load register B1 (TLB1)
11.3.1 Timer Mode Register B1 (TMB1)
TMB1 selects the auto-reload function and input clock.
Initial
7 TMB17 0 R/W Auto-reload function select
0: Interval timer function selected
1: Auto-reload function selected
2 TMB12 0 R/W Clock select
1 TMB11 0 R/W 000: Internal clock: φ/8192
0 TMB10 0 R/W 001: Internal clock: φ/2048
010: Internal clock: φ/512
111: External event (TMIB1): rising or falling edge*
Note: * The edge of the external event signal is selected
by bit IEG1 in the interrupt edge select register 1
(IEGR1). See section 3.2.1, Interrupt Edge
Select Register 1 (IEGR1), for details. Before
setting TMB12 to TMB10 to 1, IRQ1 in the port
mode register 1 (PMR1) should be set to 1.
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Section 11 Timer B1
11.3.2 Timer Counter B1 (TCB1)
TCB1 is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock
source for input to this counter is selected by bits TMB12 to TMB10 in TMB1. TCB1 values can
be read by the CPU at any time. When TCB1 overflows from H'FF to H'00 or to the value set in
TLB1, the IRRTB1 flag in IRR2 is set to 1. TCB1 is allocated to the same address as TLB1. TCB1
is initialized to H'00.
11.3.3 Timer Load Register B1 (TLB1)
TLB1 is an 8-bit write-only register for setting the reload value of TCB1. When a reload value is
set in TLB1, the same value is loaded into TCB1 as well, and TCB1 starts counting up from that
value. When TCB1 overflows during operation in auto-reload mode, the TLB1 value is loaded
into TCB1. Accordingly, overflow periods can be set within the range of 1 to 256 input clocks.
TLB1 is allocated to the same address as TCB1. TLB1 is initialized to H'00.
11.4 Operation
11.4.1 Interval Timer Operation
When bit TMB17 in TMB1 is cleared to 0, timer B1 functions as an 8-bit interval timer. Upon
reset, TCB1 is cleared to H'00 and bit TMB17 is cleared to 0, so up-counting and interval timing
resume immediately. The operating clock of timer B1 is selected from seven internal clock signals
output by prescaler S, or an external clock input at pin TMB1. The selection is made by bits
TMB12 to TMB10 in TMB1.
After the count value in TMB1 reaches H'FF, the next clock signal input causes timer B1 to
overflow, setting flag IRRTB1 in IRR2 to 1. If IENTB1 in IENR2 is 1, an interrupt is requested to
the CPU.
At overflow, TCB1 returns to H'00 and starts counting up again. During interval timer operation
(TMB17 = 0), when a value is set in TLB1, the same value is set in TCB1.
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Section 11 Timer B1
11.4.2 Auto-Reload Timer Operation
Setting bit TMB17 in TMB1 to 1 causes timer B1 to function as an 8-bit auto-reload timer. When
a reload value is set in TLB1, the same value is loaded into TCB1, becoming the value from which
TCB1 starts its count. After the count value in TCB1 reaches H'FF, the next clock signal input
causes timer B1 to overflow. The TLB1 value is then loaded into TCB1, and the count continues
from that value. The overflow period can be set within a range from 1 to 256 input clocks,
depending on the TLB1 value.
The clock sources and interrupts in auto-reload mode are the same as in interval mode. In auto-
reload mode (TMB17 = 1), when a new value is set in TLB1, the TLB1 value is also loaded into
TCB1.
11.4.3 Event Counter Operation
Timer B1 can operate as an event counter in which TMIB1 is set to an event input pin. External
event counting is selected by setting bits TMB12 to TMB10 in TMB1 to 1. TCB1 counts up at
rising or falling edge of an external event signal input at pin TMB1.
When timer B1 is used to count external event input, bit IRQ1 in PMR1 should be set to 1 and
IEN1 in IENR1 should be cleared to 0 to disable IRQ1 interrupt requests.
11.5 Timer B1 Operating Modes

Table 11.2 shows the timer B1 operating modes.
Table 11.2 Timer B1 Operating Modes
Operating Mode Reset Active Sleep Subactive Subsleep Standby

TCB1 Interval Reset Functions Functions Halted Halted Halted
Auto-reload Reset Functions Functions Halted Halted Halted
TMB1 Reset Functions Retained Retained Retained Retained
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Section 11 Timer B1
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REJ09B0216-0300
Section 12 Timer V
Section 12 Timer V
Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external events. Compare-
match signals with two registers can also be used to reset the counter, request an interrupt, or
output a pulse signal with an arbitrary duty cycle. Counting can be initiated by a trigger input at
the TRGV pin, enabling pulse output control to be synchronized to the trigger, with an arbitrary
delay from the trigger input. Figure 12.1 shows a block diagram of timer V.
12.1 Features
• Choice of seven clock signals is available.
Choice of six internal clock sources (φ/128, φ/64, φ/32, φ/16, φ/8, φ/4) or an external clock.
• Counter can be cleared by compare match A or B, or by an external reset signal. If the count
stop function is selected, the counter can be halted when cleared.
• Timer output is controlled by two independent compare match signals, enabling pulse output
with an arbitrary duty cycle, PWM output, and other applications.
• Three interrupt sources: compare match A, compare match B, timer overflow
• Counting can be initiated by trigger input at the TRGV pin. The rising edge, falling edge, or
both edges of the TRGV input can be selected.
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Section 12 Timer V
TCRV1
TCORB
Trigger
TRGV
control
Comparator
TMCIV Clock select TCNTV
Internal data bus

Comparator
φ PSS
TCORA
Clear
TMRIV TCRV0
control
Interrupt
request
control
Output
TMOV TCSRV
control
CMIA
[Legend] CMIB
TCORA: Time constant register A OVI
TCORB: Time constant register B
TCNTV: Timer counter V
TCSRV: Timer control/status register V
TCRV0: Timer control register V0
TCRV1: Timer control register V1
PSS: Prescaler S
CMIA: Compare-match interrupt A
CMIB: Compare-match interrupt B
OVI: Overflow interupt
Figure 12.1 Block Diagram of Timer V
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REJ09B0216-0300
Section 12 Timer V
12.2 Input/Output Pins

Table 12.1 shows the timer V pin configuration.

Timer V output TMOV Output Timer V waveform output
Timer V clock input TMCIV Input Clock input to TCNTV
Timer V reset input TMRIV Input External input to reset TCNTV
Trigger input TRGV Input Trigger input to initiate counting

Time V has the following registers.
• Timer counter V (TCNTV)

• Timer constant register A (TCORA)
• Timer constant register B (TCORB)
• Timer control register V0 (TCRV0)
• Timer control/status register V (TCSRV)
• Timer control register V1 (TCRV1)
12.3.1 Timer Counter V (TCNTV)
TCNTV is an 8-bit up-counter. The clock source is selected by bits CKS2 to CKS0 in timer
control register V0 (TCRV0). The TCNTV value can be read and written by the CPU at any time.
TCNTV can be cleared by an external reset input signal, or by compare match A or B. The
clearing signal is selected by bits CCLR1 and CCLR0 in TCRV0.
When TCNTV overflows, OVF is set to 1 in timer control/status register V (TCSRV).
TCNTV is initialized to H'00.
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REJ09B0216-0300
Section 12 Timer V
12.3.2 Time Constant Registers A and B (TCORA, TCORB)
TCORA and TCORB have the same function.
TCORA and TCORB are 8-bit read/write registers.
TCORA and TCNTV are compared at all times. When the TCORA and TCNTV contents match,
CMFA is set to 1 in TCSRV. If CMIEA is also set to 1 in TCRV0, a CPU interrupt is requested.
Note that they must not be compared during the T3 state of a TCORA write cycle.
Timer output from the TMOV pin can be controlled by the identifying signal (compare match A)
and the settings of bits OS3 to OS0 in TCSRV.
TCORA and TCORB are initialized to H'FF.
12.3.3 Timer Control Register V0 (TCRV0)
TCRV0 selects the input clock signals of TCNTV, specifies the clearing conditions of TCNTV,
and controls each interrupt request.
Initial
7 CMIEB 0 R/W Compare Match Interrupt Enable B
When this bit is set to 1, interrupt request from the CMFB
bit in TCSRV is enabled.
6 CMIEA 0 R/W Compare Match Interrupt Enable A
When this bit is set to 1, interrupt request from the CMFA
5 OVIE 0 R/W Timer Overflow Interrupt Enable
When this bit is set to 1, interrupt request from the OVF
4 CCLR1 0 R/W Counter Clear 1 and 0
3 CCLR0 0 R/W These bits specify the clearing conditions of TCNTV.
00: Clearing is disabled
01: Cleared by compare match A
10: Cleared by compare match B
11: Cleared on the rising edge of the TMRIV pin. The
operation of TCNTV after clearing depends on TRGE
in TCRV1.
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REJ09B0216-0300
Section 12 Timer V
Initial
2 CKS2 0 R/W Clock Select 2 to 0
1 CKS1 0 R/W These bits select clock signals to input to TCNTV and the
0 CKS0 0 R/W counting condition in combination with ICKS0 in TCRV1.
Refer to table 12.2.
Table 12.2 Clock Signals to Input to TCNTV and Counting Conditions
TCRV0 TCRV1
Bit 2 Bit 1 Bit 0 Bit 0
CKS2 CKS1 CKS0 ICKS0 Description
0 0 0  Clock input prohibited
1 0 Internal clock: counts on φ/4, falling edge
1 Internal clock: counts on φ/8, falling edge
1 0 0 Internal clock: counts on φ/16, falling edge
1 0 Internal clock: counts on φ/64, falling edge
1 0 0  Clock input prohibited
1  External clock: counts on rising edge
1 0  External clock: counts on falling edge
1  External clock: counts on rising and falling
edge
12.3.4 Timer Control/Status Register V (TCSRV)
TCSRV indicates the status flag and controls outputs by using a compare match.
Initial
7 CMFB 0 R/W Compare Match Flag B
Setting condition:
When the TCNTV value matches the TCORB value
Clearing condition:
After reading CMFB = 1, cleared by writing 0 to CMFB
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Section 12 Timer V
Initial
6 CMFA 0 R/W Compare Match Flag A
Setting condition:
When the TCNTV value matches the TCORA value
Clearing condition:
After reading CMFA = 1, cleared by writing 0 to CMFA
5 OVF 0 R/W Timer Overflow Flag
Setting condition:
When TCNTV overflows from H'FF to H'00
Clearing condition:
After reading OVF = 1, cleared by writing 0 to OVF
3 OS3 0 R/W Output Select 3 and 2
2 OS2 0 R/W These bits select an output method for the TMOV pin by
the compare match of TCORB and TCNTV.
00: No change
01: 0 output
10: 1 output
11: Output toggles
1 OS1 0 R/W Output Select 1 and 0
0 OS0 0 R/W These bits select an output method for the TMOV pin by
the compare match of TCORA and TCNTV.
00: No change
01: 0 output
10: 1 output
11: Output toggles
OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level
for compare match A. The two output levels can be controlled independently. After a reset, the
timer output is 0 until the first compare match.
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Section 12 Timer V
12.3.5 Timer Control Register V1 (TCRV1)
TCRV1 selects the edge at the TRGV pin, enables TRGV input, and selects the clock input to
TCNTV.
Initial
4 TVEG1 0 R/W TRGV Input Edge Select
3 TVEG0 0 R/W These bits select the TRGV input edge.
00: TRGV trigger input is prohibited
01: Rising edge is selected
10: Falling edge is selected
11: Rising and falling edges are both selected
2 TRGE 0 R/W TCNT starts counting up by the input of the edge which is
selected by TVEG1 and TVEG0.
0: Disables starting counting-up TCNTV by the input of
the TRGV pin and halting counting-up TCNTV when
TCNTV is cleared by a compare match.
1: Enables starting counting-up TCNTV by the input of
the TRGV pin and halting counting-up TCNTV when
TCNTV is cleared by a compare match.
0 ICKS0 0 R/W Internal Clock Select 0
This bit selects clock signals to input to TCNTV in
combination with CKS2 to CKS0 in TCRV0.
Refer to table 12.2.
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REJ09B0216-0300
Section 12 Timer V
12.4 Operation
12.4.1 Timer V Operation
1. According to table 12.2, six internal/external clock signals output by prescaler S can be
selected as the timer V operating clock signals. When the operating clock signal is selected,
TCNTV starts counting-up. Figure 12.2 shows the count timing with an internal clock signal
selected, and figure 12.3 shows the count timing with both edges of an external clock signal
selected.
2. When TCNTV overflows (changes from H'FF to H'00), the overflow flag (OVF) in TCRV0
will be set. The timing at this time is shown in figure 12.4. An interrupt request is sent to the
CPU when OVIE in TCRV0 is 1.
3. TCNTV is constantly compared with TCORA and TCORB. Compare match flag A or B
(CMFA or CMFB) is set to 1 when TCNTV matches TCORA or TCORB, respectively. The
compare-match signal is generated in the last state in which the values match. Figure 12.5
shows the timing. An interrupt request is generated for the CPU when CMIEA or CMIEB in
TCRV0 is 1.
4. When a compare match A or B is generated, the TMOV responds with the output value
selected by bits OS3 to OS0 in TCSRV. Figure 12.6 shows the timing when the output is
toggled by compare match A.
5. When CCLR1 or CCLR0 in TCRV0 is 01 or 10, TCNTV can be cleared by the corresponding
compare match. Figure 12.7 shows the timing.
6. When CCLR1 or CCLR0 in TCRV0 is 11, TCNTV can be cleared by the rising edge of the
input of TMRIV pin. A TMRIV input pulse-width of at least 1.5 system clocks is necessary.
Figure 12.8 shows the timing.
7. When a counter-clearing source is generated with TRGE in TCRV1 set to 1, the counting-up is
halted as soon as TCNTV is cleared. TCNTV resumes counting-up when the edge selected by
TVEG1 or TVEG0 in TCRV1 is input from the TGRV pin.
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REJ09B0216-0300
Section 12 Timer V
Internal clock
TCNTV input
clock
TCNTV N–1 N N+1
Figure 12.2 Increment Timing with Internal Clock
TMCIV
(External clock
input pin)
TCNTV input
clock
TCNTV N–1 N N+1
Figure 12.3 Increment Timing with External Clock
TCNTV H'FF H'00
Overflow signal
OVF
Figure 12.4 OVF Set Timing
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REJ09B0216-0300
Section 12 Timer V
TCNTV N N+1
TCORA or
TCORB N
Compare match
signal
CMFA or
CMFB
Figure 12.5 CMFA and CMFB Set Timing
Compare match
A signal
Timer V output
pin
Figure 12.6 TMOV Output Timing
Compare match
A signal
TCNTV N H'00
Figure 12.7 Clear Timing by Compare Match
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REJ09B0216-0300
Section 12 Timer V
TMRIV (External
counter reset
input pin)
TCNTV reset
signal
TCNTV N–1 N H'00
Figure 12.8 Clear Timing by TMRIV Input
12.5 Timer V Application Examples
12.5.1 Pulse Output with Arbitrary Duty Cycle
Figure 12.9 shows an example of output of pulses with an arbitrary duty cycle.
1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with
TCORA.
2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA
and to 0 at compare match with TCORB.
3. Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source.
4. With these settings, a waveform is output without further software intervention, with a period
determined by TCORA and a pulse width determined by TCORB.
TCNTV value
H'FF
Counter cleared
TCORA
TCORB
H'00 Time
TMOV
Figure 12.9 Pulse Output Example
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REJ09B0216-0300
Section 12 Timer V
12.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input
The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary
delay from the TRGV input, as shown in figure 12.10. To set up this output:
1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with
TCORB.
2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA
and to 0 at compare match with TCORB.
3. Set bits TVEG1 and TVEG0 in TCRV1 and set TRGE to select the falling edge of the TRGV
input.
4. Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source.
5. After these settings, a pulse waveform will be output without further software intervention,
with a delay determined by TCORA from the TRGV input, and a pulse width determined by
(TCORB – TCORA).
TCNTV value
H'FF
Counter cleared
TCORB
TCORA
H'00 Time
TRGV
TMOV
Compare match A Compare match A

Compare match B Compare match B
clears TCNTV and clears TCNTV and
halts count-up halts count-up
Figure 12.10 Example of Pulse Output Synchronized to TRGV Input
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REJ09B0216-0300
Section 12 Timer V
12.6 Usage Notes

The following types of contention or operation can occur in timer V operation.
1. Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear
signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 12.11, clearing
takes precedence and the write to the counter is not carried out. If counting-up is generated in
the T3 state of a TCNTV write cycle, writing takes precedence.
2. If a compare match is generated in the T3 state of a TCORA or TCORB write cycle, the write
to TCORA or TCORB takes precedence and the compare match signal is inhibited. Figure
12.12 shows the timing.
3. If compare matches A and B occur simultaneously, any conflict between the output selections
for compare match A and compare match B is resolved by the following priority: toggle output
> output 1 > output 0.
4. Depending on the timing, TCNTV may be incremented by a switch between different internal
clock sources. When TCNTV is internally clocked, an increment pulse is generated from the
falling edge of an internal clock signal, that is divided system clock (φ). Therefore, as shown in
figure 12.3 the switch is from a high clock signal to a low clock signal, the switchover is seen
as a falling edge, causing TCNTV to increment. TCNTV can also be incremented by a switch
between internal and external clocks.
TCNTV write cycle by CPU
T1 T2 T3
Address TCNTV address
Counter clear signal
TCNTV N H'00
Figure 12.11 Contention between TCNTV Write and Clear
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REJ09B0216-0300
Section 12 Timer V
TCORA write cycle by CPU
T1 T2 T3
Address TCORA address
TCNTV N N+1
TCORA N M
TCORA write data
Compare match signal

Inhibited
Figure 12.12 Contention between TCORA Write and Compare Match
Clock before
switching
Clock after
switching
Count clock
TCNTV N N+1 N+2
Write to CKS1 and CKS0
Figure 12.13 Internal Clock Switching and TCNTV Operation
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Section 13 Timer Z
Section 13 Timer Z
The timer Z has a 16-bit timer with two channels. Figures 13.1, 13.2, and 13.3 show the block
diagrams of entire timer Z, its channel 0, and its channel 1, respectively. For details on the timer Z
functions, refer to table 13.1.
13.1 Features
• Capability to process up to eight inputs/outputs
• Eight general registers (GR): four registers for each channel
 Independently assignable output compare or input capture functions
• Selection of five counter clock sources: four internal clocks (φ, φ/2, φ/4, and φ/8) and an
external clock
• Seven selectable operating modes
 Output compare function
Selection of 0 output, 1 output, or toggle output
 Input capture function
Rising edge, falling edge, or both edges
 Synchronous operation
Timer counters_0 and _1 (TCNT_0 and TCNT_1) can be written simultaneously.
Simultaneous clearing by compare match or input capture is possible.
 PWM mode
Up to six-phase PWM output can be provided with desired duty ratio.
 Reset synchronous PWM mode
Three-phase PWM output for normal and counter phases
 Complementary PWM mode
Three-phase PWM output for non-overlapped normal and counter phases
The A/D conversion start trigger can be set for PWM cycles.
 Buffer operation
The input capture register can be consisted of double buffers.
The output compare register can automatically be modified.
• High-speed access by the internal 16-bit bus
 16-bit TCNT and GR registers can be accessed in high speed by a 16-bit bus interface
• Any initial timer output value can be set
• Output of the timer is disabled by external trigger
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REJ09B0216-0300
Section 13 Timer Z
• Eleven interrupt sources

 Four compare match/input capture interrupts and an overflow interrupt are available for
each channel. An underflow interrupt can be set for channel 1.
Table 13.1 Timer Z Functions
Item Channel 0 Channel 1

Count clock Internal clocks: φ, φ/2, φ/4, φ/8
External clock: FTIOA0 (TCLK)
General registers GRA_0, GRB_0, GRC_0, GRD_0 GRA_1, GRB_1, GRC_1, GRD_1
(output compare/input
capture registers)
Buffer register GRC_0, GRD_0 GRC_1, GRD_1
I/O pins FTIOA0, FTIOB0, FTIOC0, FTIOA1, FTIOB1, FTIOC1,
FTIOD0 FTIOD1
Counter clearing function Compare match/input capture of Compare match/input capture of
GRA_0, GRB_0, GRC_0, or GRA_1, GRB_1, GRC_1, or
GRD_0 GRD_1
Compare 0 output Yes Yes
match output
1 output Yes Yes
output Yes Yes
Input capture function Yes Yes
Synchronous operation Yes Yes
PWM mode Yes Yes
Reset synchronous PWM Yes Yes
mode
Complementary PWM Yes Yes
mode
Buffer function Yes Yes
Interrupt sources Compare match/input capture A0 Compare match/input capture A1
to D0 to D1
Overflow Overflow
Underflow
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REJ09B0216-0300
Section 13 Timer Z
ITMZ0
FTIOA0 ITMZ1
FTIOB0
FTIOC0
FTIOD0
Control logic
FTIOA1
FTIOB1
FTIOC1
FTIOD1
φ, φ/2,
φ/4, φ/8
ADTRG
TSTR TMDR
Channel 0 Channel 1 TPMR TFCR
timer timer
TOER TOCR
Module data bus
[Legend]
TSTR: Timer start register (8 bits)
TMDR: Timer mode register (8 bits)
TPMR: Timer PWM mode register (8 bits)
TFCR: Timer function control register (8 bits)
TOER: Timer output master enable register (8 bits)
TOCR: Timer output control register (8 bits)
ADTRG: A/D conversion start trigger output signal
ITMZ0: Channel 0 interrupt
Figure 13.1 Timer Z Block Diagram
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REJ09B0216-0300
Section 13 Timer Z
FTIOA0
FTIOB0
φ, φ/2,
Clock select FTIOC0
φ/4, φ/8
FTIOD0
Control logic
ITMZ0
Comparator
TIORC_0
TIORA_0
POCR_0
TCNT_0
TIER_0
GRC_0
GRD_0
GRA_0
GRB_0
TCR_0
TSR_0
Module data bus
[Legend]
TCNT_0: Timer counter_0 (16 bits)
GRA_0, GRB_0, General registers A_0, B_0, C_0, and D_0 (input capture/output compare registers:
GRC_0, GRD_0: 16 bits × 4)
TCR_0: Timer control register_0 (8 bits)
TIORA_0: Timer I/O control register A_0 (8 bits)
TIORC_0: Timer I/O control register C_0 (8 bits)
TSR_0: Timer status register_0 (8 bits)
TIER_0: Timer interrupt enable register_0 (8 bits)
POCR_0: PWM mode output level control register_0 (8 bits)
Figure 13.2 Timer Z (Channel 0) Block Diagram
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REJ09B0216-0300
Section 13 Timer Z
FTIOA1
FTIOB1
φ, φ/2,
Clock select FTIOC1
φ/4, φ/8
FTIOD1
Control logic
ITMZ1
Comparator
TIORC_1
TIORA_1
POCR_1
TCNT_1
TIER_1
GRC_1
GRD_1
GRA_1
GRB_1
TCR_1
TSR_1
Module data bus
[Legend]
TCNT_1: Timer counter_1 (16 bits)
GRA_1, GRB_1, General registers A_1, B_1, C_1, and D_1 (input capture/output compare registers:
GRC_1, GRD_1: 16 bits × 4)
TCR_1: Timer control register_1 (8 bits)
TIORA_1: Timer I/O control register A_1 (8 bits)
TIORC_1: Timer I/O control register C_1 (8 bits)
TSR_1: Timer status register_1 (8 bits)
TIER_1: Timer interrupt enable register_1 (8 bits)
POCR_1: PWM mode output level control register_1 (8 bits)
Figure 13.3 Timer Z (Channel 1) Block Diagram
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REJ09B0216-0300
Section 13 Timer Z

Table 13.2 summarizes the timer Z pins.
Name Abbreviation Input/Output Function

Input capture/output FTIOA0 Input/output GRA_0 output compare output, GRA_0
compare A0 input capture input, or external clock
input (TCLK)
Input capture/output FTIOB0 Input/output GRB_0 output compare output, GRB_0
compare B0 input capture input, or PWM output
Input capture/output FTIOC0 Input/output GRC_0 output compare output, GRC_0
compare C0 input capture input, or PWM
synchronous output (in reset
synchronous PWM and complementary
PWM modes)
Input capture/output FTIOD0 Input/output GRD_0 output compare output, GRD_0
compare D0 input capture input, or PWM output
Input capture/output FTIOA1 Input/output GRA_1 output compare output, GRA_1
compare A1 input capture input, or PWM output (in
reset synchronous PWM and
complementary PWM modes)
Input capture/output FTIOB1 Input/output GRB_1 output compare output, GRB_1
compare B1 input capture input, or PWM output
Input capture/output FTIOC1 Input/output GRC_1 output compare output, GRC_1
compare C1 input capture input, or PWM output
Input capture/output FTIOD1 Input/output GRD_1 output compare output, GRD_1
compare D1 input capture input, or PWM output
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REJ09B0216-0300
Section 13 Timer Z

The timer Z has the following registers.
Common
• Timer start register (TSTR)
• Timer mode register (TMDR)
• Timer PWM mode register (TPMR)
• Timer function control register (TFCR)
• Timer output master enable register (TOER)
• Timer output control register (TOCR)
Channel 0
• Timer control register_0 (TCR_0)
• Timer I/O control register A_0 (TIORA_0)
• Timer I/O control register C_0 (TIORC_0)
• Timer status register_0 (TSR_0)
• Timer interrupt enable register_0 (TIER_0)
• PWM mode output level control register_0 (POCR_0)
• Timer counter_0 (TCNT_0)
• General register A_0 (GRA_0)
• General register B_0 (GRB_0)
• General register C_0 (GRC_0)
• General register D_0 (GRD_0)
Channel 1
• Timer control register_1 (TCR_1)
• Timer I/O control register A_1 (TIORA_1)
• Timer I/O control register C_1 (TIORC_1)
• Timer status register_1 (TSR_1)
• Timer interrupt enable register_1 (TIER_1)
• PWM mode output level control register_1 (POCR_1)
• Timer counter_1 (TCNT_1)
• General register A_1 (GRA_1)
• General register B_1 (GRB_1)
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REJ09B0216-0300
Section 13 Timer Z
• General register C_1 (GRC_1)

• General register D_1 (GRD_1)
13.3.1 Timer Start Register (TSTR)
TSTR selects the operation/stop for the TCNT counter.
Initial
These bits are always read as 1, and cannot be modified.
1 STR1 0 R/W Channel 1 Counter Start
0: TCNT_1 halts counting
1: TCNT_1 starts counting
0 STR0 0 R/W Channel 0 Counter Start
0: TCNT_0 halts counting
1: TCNT_0 starts counting
13.3.2 Timer Mode Register (TMDR)
TMDR selects buffer operation settings and synchronized operation.
Initial
7 BFD1 0 R/W Buffer Operation D1
0: GRD_1 operates normally
1: GRB_1 and GRD_1 are used together for buffer
operation
6 BFC1 0 R/W Buffer Operation C1
0: GRC_1 operates normally
1: GRA_1 and GRD_1 are used together for buffer
operation
5 BFD0 0 R/W Buffer Operation D0
0: GRD_0 operates normally
1: GRB_0 and GRD_0 are used together for buffer
operation
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REJ09B0216-0300
Section 13 Timer Z
Initial
4 BFC0 0 R/W Buffer Operation C0
0: GRC_0 operates normally
1: GRA_0 and GRC_0 are used together for buffer
operation
0 SYNC 0 R/W Timer Synchronization
0: TCNT_1 and TCNT_0 operate as a different timer
counter
1: TCNT_1 and TCNT_0 are synchronized
TCNT_1 and TCNT_0 can be pre-set or cleared
synchronously
13.3.3 Timer PWM Mode Register (TPMR)
TPMR sets the pin to enter PWM mode.
Initial
This bit is always read as 1, and cannot be modified.
6 PWMD1 0 R/W PWM Mode D1
0: FTIOD1 operates normally
1: FTIOD1 operates in PWM mode
5 PWMC1 0 R/W PWM Mode C1
0: FTIOC1 operates normally
1: FTIOC1 operates in PWM mode
4 PWMB1 0 R/W PWM Mode B1
0: FTIOB1 operates normally
1: FTIOB1 operates in PWM mode
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REJ09B0216-0300
Section 13 Timer Z
Initial
2 PWMD0 0 R/W PWM Mode D0
0: FTIOD0 operates normally
1: FTIOD0 operates in PWM mode
1 PWMC0 0 R/W PWM Mode C0
0: FTIOC0 operates normally
1: FTIOC0 operates in PWM mode
0 PWMB0 0 R/W PWM Mode B0
0: FTIOB0 operates normally
1: FTIOB0 operates in PWM mode
13.3.4 Timer Function Control Register (TFCR)
TFCR selects the settings and output levels for each operating mode.
Initial
6 STCLK 0 R/W External Clock Input Select
0: External clock input is disabled
1: External clock input is enabled
5 ADEG 0 R/W A/D Trigger Edge Select
A/D module should be set to start an A/D conversion by
the external trigger
0: A/D trigger at the crest in complementary PWM mode
1: A/D trigger at the trough in complementary PWM mode
4 ADTRG 0 R/W External Trigger Disable
0: A/D trigger for PWM cycles is disabled in
complementary PWM mode
1: A/D trigger for PWM cycles is enabled in
complementary PWM mode
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REJ09B0216-0300
Section 13 Timer Z
Initial
3 OLS1 0 R/W Output Level Select 1
Selects the counter-phase output levels in reset
synchronous PWM mode or complementary PWM mode.
0: Initial output is high and the active level is low.
1: Initial output is low and the active level is high.
2 OLS0 0 R/W Output Level Select 0
Selects the normal-phase output levels in reset
synchronous PWM mode or complementary PWM mode.
0: Initial output is high and the active level is low.
1: Initial output is low and the active level is high.
Figure 13.4 shows an example of outputs in reset
synchronous PWM mode and complementary PWM
mode when OLS1 = 0 and OLS0 = 0.
1 CMD1 0 R/W Combination Mode 1 and 0
0 CMD0 0 R/W 00: Channel 0 and channel 1 operate normally
01: Channel 0 and channel 1 are used together to
operate in reset synchronous PWM mode
operate in complementary PWM mode (transferred at
the trough)
operate in complementary PWM mode (transferred at
the crest)
Note: When reset synchronous PWM mode or
complementary PWM mode is selected by these
bits, this setting has the priority to the settings for
PWM mode by each bit in TPMR. Stop TCNT_0
and TCNT_1 before making settings for reset
synchronous PWM mode or complementary PWM
mode.
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REJ09B0216-0300
Section 13 Timer Z
TCNT_0
TCNT_1
Normal phase Normal phase Active level

Active level
Counter phase Initial
Counter phase
Initial output
output Active level
Active level
Reset synchronous PWM mode Complementary PWM mode
Note: Write H'00 to TOCR to start initial outputs after stopping the counter.
Figure 13.4 Example of Outputs in Reset Synchronous PWM Mode

and Complementary PWM Mode
13.3.5 Timer Output Master Enable Register (TOER)
TOER enables/disables the outputs for channel 0 and channel 1. When WKP4 is selected for
inputs, if a low level signal is input to WKP4, the bits in TOER are set to 1 to disable the output
for timer Z.
Initial
7 ED1 1 R/W Master Enable D1
0: FTIOD1 pin output is enabled according to the TPMR,
TFCR, and TIORC_1 settings
1: FTIOD1 pin output is disabled regardless of the TPMR,
TFCR, and TIORC_1 settings (FTIOD1 pin is operated
as an I/O port).
6 EC1 1 R/W Master Enable C1
0: FTIOC1 pin output is enabled according to the TPMR,
1: FTIOC1 pin output is disabled regardless of the TPMR,
TFCR, and TIORC_1 settings (FTIOC1 pin is operated
as an I/O port).
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REJ09B0216-0300
Section 13 Timer Z
Initial
5 EB1 1 R/W Master Enable B1
0: FTIOB1 pin output is enabled according to the TPMR,
TFCR, and TIORA_1 settings
1: FTIOB1 pin output is disabled regardless of the TPMR,
TFCR, and TIORA_1 settings (FTIOB1 pin is operated
as an I/O port).
4 EA1 1 R/W Master Enable A1
0: FTIOA1 pin output is enabled according to the TPMR,
1: FTIOA1 pin output is disabled regardless of the TPMR,
TFCR, and TIORA_1 settings (FTIOA1 pin is operated
as an I/O port).
3 ED0 1 R/W Master Enable D0
0: FTIOD0 pin output is enabled according to the TPMR,
1: FTIOD0 pin output is disabled regardless of the TPMR,
TFCR, and TIORC_0 settings (FTIOD0 pin is operated
as an I/O port).
2 EC0 1 R/W Master Enable C0
0: FTIOC0 pin output is enabled according to the TPMR,
1: FTIOC0 pin output is disabled regardless of the TPMR,
TFCR, and TIORC_0 settings (FTIOC0 pin is operated
as an I/O port).
1 EB0 1 R/W Master Enable B0
0: FTIOB0 pin output is enabled according to the TPMR,
1: FTIOB0 pin output is disabled regardless of the TPMR,
TFCR, and TIORA_0 settings (FTIOB0 pin is operated
as an I/O port).
0 EA0 1 R/W Master Enable A0
0: FTIOA0 pin output is enabled according to the TPMR,
1: FTIOA0 pin output is disabled regardless of the TPMR,
TFCR, and TIORA_0 settings (FTIOA0 pin is operated
as an I/O port).
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REJ09B0216-0300
Section 13 Timer Z
13.3.6 Timer Output Control Register (TOCR)
TOCR selects the initial outputs before the first occurrence of a compare match. Note that bits
OLS1 and OLS0 in TFCR set these initial outputs in reset synchronous PWM mode and
complementary PWM mode.
Initial
7 TOD1 0 R/W Output Level Select D1
0: 0 output at the FTIOD1 pin*
6 TOC1 0 R/W Output Level Select C1
0: 0 output at the FTIOC1 pin*
5 TOB1 0 R/W Output Level Select B1
0: 0 output at the FTIOB1 pin*
4 TOA1 0 R/W Output Level Select A1
0: 0 output at the FTIOA1 pin*
3 TOD0 0 R/W Output Level Select D0
2 TOC0 0 R/W Output Level Select C0
1 TOB0 0 R/W Output Level Select B0
0 TOA0 0 R/W Output Level Select A0
Note: * The change of the setting is immediately reflected in the output value.
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REJ09B0216-0300
Section 13 Timer Z
13.3.7 Timer Counter (TCNT)
The timer Z has two TCNT counters (TCNT_0 and TCNT_1), one for each channel. The TCNT
counters are 16-bit readable/writable registers that increment/decrement according to input clocks.
Input clocks can be selected by bits TPSC2 to TPSC0 in TCR. TCNT0 and TCNT 1
increment/decrement in complementary PWM mode, while they only increment in other modes.
The TCNT counters are initialized to H'0000 by compare matches with corresponding GRA, GRB,
GRC, or GRD, or input captures to GRA, GRB, GRC, or GRD (counter clearing function). When
the TCNT counters overflow, an OVF flag in TSR for the corresponding channel is set to 1. When
TCNT_1 underflows, an UDF flag in TSR is set to 1. The TCNT counters cannot be accessed in 8-
bit units; they must always be accessed as a 16-bit unit. TCNT is initialized to H'0000.
13.3.8 General Registers A, B, C, and D (GRA, GRB, GRC, and GRD)
GR are 16-bit registers. Timer Z has eight general registers (GR), four for each channel. The GR
registers are dual function 16-bit readable/writable registers, functioning as either output compare
or input capture registers. Functions can be switched by TIORA and TIORC.
The values in GR and TCNT are constantly compared with each other when the GR registers are
used as output compare registers. When the both values match, the IMFA to IMFD flags in TSR
are set to 1. Compare match outputs can be selected by TIORA and TIORC.
When the GR registers are used as input capture registers, the TCNT value is stored after detecting
external signals. At this point, IMFA to IMFD flags in the corresponding TSR are set to 1.
Detection edges for input capture signals can be selected by TIORA and TIORC.
When PWM mode, complementary PWM mode, or reset synchronous PWM mode is selected, the
values in TIORA and TIORC are ignored. Upon reset, the GR registers are set as output compare
registers (no output) and initialized to H'FFFF. The GR registers cannot be accessed in 8-bit units;
they must always be accessed as a 16-bit unit.
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REJ09B0216-0300
Section 13 Timer Z
13.3.9 Timer Control Register (TCR)
The TCR registers select a TCNT counter clock, an edge when an external clock is selected, and
counter clearing sources. Timer Z has a total of two TCR registers, one for each channel.
Initial
Bit Bit Name value R/W Description
7 CCLR2 0 R/W Counter Clear 2 to 0
6 CCLR1 0 R/W 000: Disables TCNT clearing
5 CCLR0 0 R/W 001: Clears TCNT by GRA compare match/input
1
capture*
010: Clears TCNT by GRB compare match/input
1
capture*
011: Synchronization clear; Clears TCNT in synchronous
2
with counter clearing of the other channel’s timer*
100: Disables TCNT clearing
101: Clears TCNT by GRC compare match/input
1
capture*
110: Clears TCNT by GRD compare match/input
1
capture*
111: Synchronization clear; Clears TCNT in synchronous
2
with counter clearing of the other channel’s timer*
4 CKEG1 0 R/W Clock Edge 1 and 0
3 CKEG0 0 R/W 00: Count at rising edge
01: Count at falling edge
1X: Count at both edges
2 TPSC2 0 R/W Time Prescaler 2 to 0
1 TPSC1 0 R/W 000: Internal clock: count by φ
0 TPSC0 0 R/W 001: Internal clock: count by φ/2
010: Internal clock: count by φ/4
011: Internal clock: count by φ/8
1XX: External clock: count by FTIOA0 (TCLK) pin input
Notes: 1. When GR functions as an output compare register, TCNT is cleared by compare match.
When GR functions as input capture, TCNT is cleared by input capture.
2. Synchronous operation is set by TMDR.
3. X: Don’t care
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REJ09B0216-0300
Section 13 Timer Z
13.3.10 Timer I/O Control Register (TIORA and TIORC)
The TIOR registers control the general registers (GR). Timer Z has four TIOR registers
(TIORA_0, TIORA_1, TIORC_0, and TIORC_1), two for each channel. In PWM mode including
complementary PWM mode and reset synchronous PWM mode, the settings of TIOR are invalid.
TIORA: TIORA selects whether GRA or GRB is used as an output compare register or an input
capture register. When an output compare register is selected, the output setting is selected. When
an input capture register is selected, an input edge of an input capture signal is selected. TIORA
also selects the function of FTIOA or FTIOB pin.
Initial
6 IOB2 0 R/W I/O Control B2 to B0
5 IOB1 0 R/W GRB is an output compare register:
4 IOB0 0 R/W 000: Disables pin output by compare match
001: 0 output by GRB compare match
010: 1 output by GRB compare match
011: Toggle output by GRB compare match
GRB is an input capture register:
100: Input capture to GRB at the rising edge
101: Input capture to GRB at the falling edge
11X: Input capture to GRB at both rising and falling edges
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REJ09B0216-0300
Section 13 Timer Z
Initial
2 IOA2 0 R/W I/O Control A2 to A0
1 IOA1 0 R/W GRA is an output compare register:
0 IOA0 0 R/W 000: Disables pin output by compare match
001: 0 output by GRA compare match
010: 1 output by GRA compare match
011: Toggle output by GRA compare match
GRA is an input capture register:
100: Input capture to GRA at the rising edge
101: Input capture to GRA at the falling edge
11X: Input capture to GRA at both rising and falling edges
TIORC: TIORC selects whether GRC or GRD is used as an output compare register or an input
capture register. When an output compare register is selected, the output setting is selected. When
an input capture register is selected, an input edge of an input capture signal is selected. TIORC
also selects the function of FTIOC or FTIOD pin.
Initial
6 IOD2 0 R/W I/O Control D2 to D0
5 IOD1 0 R/W GRD is an output compare register:
4 IOD0 0 R/W 000: Disables pin output by compare match
001: 0 output by GRD compare match
010: 1 output by GRD compare match
011: Toggle output by GRD compare match
GRD is an input capture register:
100: Input capture to GRD at the rising edge
101: Input capture to GRD at the falling edge
11X: Input capture to GRD at both rising and falling
edges
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REJ09B0216-0300
Section 13 Timer Z
Initial
2 IOC2 0 R/W I/O Control C2 to C0
1 IOC1 0 R/W GRC is an output compare register:
0 IOC0 0 R/W 000: Disables pin output by compare match
001: 0 output by GRC compare match
010: 1 output by GRC compare match
011: Toggle Output by GRC compare match
GRC is an input capture register:
100: Input capture to GRC at the rising edge
101: Input capture to GRC at the falling edge
11X: Input capture to GRC at both rising and falling
edges
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REJ09B0216-0300
Section 13 Timer Z
13.3.11 Timer Status Register (TSR)
TSR indicates generation of an overflow/underflow of TCNT and a compare match/input capture

of GRA, GRB, GRC, and GRD. These flags are interrupt sources. If an interrupt is enabled by a
corresponding bit in TIER, TSR requests an interrupt for the CPU. Timer Z has two TSR registers,
one for each channel.
Initial
5 UDF* 0 R/W Underflow Flag
[Setting condition]
• When TCNT_1 underflows
• When 0 is written to UDF after reading UDF = 1
4 OVF 0 R/W Overflow Flag
[Setting condition]
• When the TCNT value underflows
• When 0 is written to OVF after reading OVF = 1
3 IMFD 0 R/W Input Capture/Compare Match Flag D
[Setting conditions]
• When TCNT = GRD and GRD is functioning as output
compare register
• When TCNT value is transferred to GRD by input
capture signal and GRD is functioning as input
capture register
• When 0 is written to IMFD after reading IMFD = 1
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REJ09B0216-0300
Section 13 Timer Z
Initial
2 IMFC 0 R/W Input Capture/Compare Match Flag C
• When TCNT = GRC and GRC is functioning as output
compare register
• When TCNT value is transferred to GRC by input
capture signal and GRC is functioning as input
capture register
• When 0 is written to IMFC after reading IMFC = 1
1 IMFB 0 R/W Input Capture/Compare Match Flag B
• When TCNT = GRB and GRB is functioning as output
compare register
• When TCNT value is transferred to GRB by input
capture signal and GRB is functioning as input
capture register
• When 0 is written to IMFB after reading IMFB = 1
0 IMFA 0 R/W Input Capture/Compare Match Flag A
• When TCNT = GRA and GRA is functioning as output
compare register
• When TCNT value is transferred to GRA by input
capture signal and GRA is functioning as input
capture register
• When 0 is written to IMFA after reading IMFA = 1
Note: Bit 5 is not the UDF flag in TSR_0. It is a reserved bit. It is always read as 1.
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REJ09B0216-0300
Section 13 Timer Z
13.3.12 Timer Interrupt Enable Register (TIER)
TIER enables or disables interrupt requests for overflow or GR compare match/input capture.
Timer Z has two TIER registers, one for each channel.
Initial
4 OVIE 0 R/W Overflow Interrupt Enable
0: Interrupt requests (OVI) by OVF or UDF flag are
disabled
1: Interrupt requests (OVI) by OVF or UDF flag are
enabled
3 IMIED 0 R/W Input Capture/Compare Match Interrupt Enable D
0: Interrupt requests (IMID) by IMFD flag are disabled
1: Interrupt requests (IMID) by IMFD flag are enabled
2 IMIEC 0 R/W Input Capture/Compare Match Interrupt Enable C
0: Interrupt requests (IMIC) by IMFC flag are disabled
1: Interrupt requests (IMIC) by IMFC flag are enabled
1 IMIEB 0 R/W Input Capture/Compare Match Interrupt Enable B
0: Interrupt requests (IMIB) by IMFB flag are disabled
1: Interrupt requests (IMIB) by IMFB flag are enabled
0 IMIEA 0 R/W Input Capture/Compare Match Interrupt Enable A
0: Interrupt requests (IMIA) by IMFA flag are disabled
1: Interrupt requests (IMIA) by IMFA flag are enabled
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REJ09B0216-0300
Section 13 Timer Z
13.3.13 PWM Mode Output Level Control Register (POCR)
POCR control the active level in PWM mode. Timer Z has two POCR registers, one for each
channel.
Initial
2 POLD 0 R/W PWM Mode Output Level Control D
0: The output level of FTIOD is low-active
1: The output level of FTIOD is high-active
1 POLC 0 R/W PWM Mode Output Level Control C
0: The output level of FTIOC is low-active
1: The output level of FTIOC is high-active
0 POLB 0 R/W PWM Mode Output Level Control B
0: The output level of FTIOB is low-active
1: The output level of FTIOB is high-active
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Section 13 Timer Z
13.3.14 Interface with CPU
1. 16-bit register
TCNT and GR are 16-bit registers. Reading/writing in a 16-bit unit is enabled but disabled in
an 8-bit unit since the data bus with the CPU is 16-bit width. These registers must always be
accessed in a 16-bit unit. Figure 13.5 shows an example of accessing the 16-bit registers.
Internal data bus

H
C
P L Bus interface Module data bus
TCNTH TCNTL
Figure 13.5 Accessing Operation of 16-Bit Register (between CPU and TCNT (16 bits))
2. 8-bit register
Registers other than TCNT and GR are 8-bit registers that are connected internally with the
CPU in an 8-bit width. Figure 13.6 shows an example of accessing the 8-bit registers.
Internal data bus

H
C
P L Bus interface Module data bus
TSTR
Figure 13.6 Accessing Operation of 8-Bit Register (between CPU and TSTR (8 bits))
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Section 13 Timer Z
13.4 Operation
13.4.1 Counter Operation
When one of bits STR0 and STR1 in TSTR is set to 1, the TCNT counter for the corresponding
channel begins counting. TCNT can operate as a free-running counter, periodic counter, for
example. Figure 13.7 shows an example of the counter operation setting procedure.
Operation selection [1] Select the counter

clock with bits
TPSC2 to TPSC0 in
TCR. When an external
Select counter clock [1] clock is selected, select
the external clock edge
with bits CKEG1
and CKEG0 in TCR.
Periodic counter Free-running counter [2] For periodic counter
operation, select the
TCNT clearing
[2] source with bits
Select counter clearing source
CCLR2 to CCLR0 in
TCR.
[3] Designate the general
register selected in [2]
Select output compare register [3]
as an output compare
register by means of
TIOR.
[4] Set the periodic counter
Set period [4]
cycle in the general
register selected
in [2].
Start count operation [5] [5] Set the STR bit in TSTR
to 1 to start the counter
operation.
Figure 13.7 Example of Counter Operation Setting Procedure
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Section 13 Timer Z
1. Free-running count operation and periodic count operation

Immediately after a reset, the TCNT counters for channels 0 and 1 are all designated as free-
running counters. When the relevant bit in TSTR is set to 1, the corresponding TCNT counter
starts an increment operation as a free-running counter. When TCNT overflows, the OVF flag
in TSR is set to 1. If the value of the OVIE bit in the corresponding TIER is 1 at this point,
timer Z requests an interrupt. After overflow, TCNT starts an increment operation again from
H'0000.
Figure 13.8 illustrates free-running counter operation.
TCNT value
H'FFFF
H'0000 Time
STR0,
STR1
OVF
Figure 13.8 Free-Running Counter Operation
When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant
channel performs periodic count operation. The GR registers for setting the period are designated
as output compare registers, and counter clearing by compare match is selected by means of bits
CCLR1 and CCLR0 in TCR. After the settings have been made, TCNT starts an increment
operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count
value matches the value in GR, the IMFA, IMFB, IMFC, or IMFD flag in TSR is set to 1 and
TCNT is cleared to H'0000.
If the value of the corresponding IMIEA, IMIEB, IMIEC, or IMIED bit in TIER is 1 at this point,
the timer Z requests an interrupt. After a compare match, TCNT starts an increment operation
again from H'0000.
Figure 13.9 illustrates periodic counter operation.
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REJ09B0216-0300
Section 13 Timer Z
TCNT value
Counter cleared by GR compare match
GR value
H'0000 Time
STR
IMF
Figure 13.9 Periodic Counter Operation
2. TCNT count timing

A. Internal clock operation
A system clock (φ) or three types of clocks (φ/2, φ/4, or φ/8) that divides the system clock
can be selected by bits TPSC2 to TPSC0 in TCR.
Figure 13.10 illustrates this timing.
Internal clock
TCNT input
TCNT N-1 N N+1
Figure 13.10 Count Timing at Internal Clock Operation
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REJ09B0216-0300
Section 13 Timer Z
B. External clock operation

An external clock input pin (TCLK) can be selected by bits TPSC2 to TPSC0 in TCR, and
a detection edge can be selected by bits CKEG1 and CKEG0. To detect an external clock,
the rising edge, falling edge, or both edges can be selected. The pulse width of the external
clock needs two or more system clocks. Note that an external clock does not operate
correctly with the lower pulse width.
Figure 13.11 illustrates the detection timing of the rising and falling edges.
External clock input pin
TCNT input
TCNT N-1 N N+1
Figure 13.11 Count Timing at External Clock Operation (Both Edges Detected)
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REJ09B0216-0300
Section 13 Timer Z
13.4.2 Waveform Output by Compare Match
Timer Z can perform 0, 1, or toggle output from the corresponding FTIOA, FTIOB, FTIOC, or
FTIOD output pin using compare match A, B, C, or D.
Figure 13.12 shows an example of the setting procedure for waveform output by compare match.
Output selection [1] Select 0 output, 1 output, or toggle

output as a compare much output, by
means of TIOR. The initial values set in
TOCR are output unit the first compare
Select waveform output mode [1]
match occurs.
[2] Set the timing for compare match
generation in GRA/GRB/GRC/GRD.
Set output timing [2] [3] Enable or disable the timer output by
TOER.
[4] Set the STR bit in TSTR to 1 to start the
TCNT count operation.
Enable waveform output [3]
Start count operation [4]
<Waveform output>
Figure 13.12 Example of Setting Procedure for Waveform Output by Compare Match
1. Examples of waveform output operation

Figure 13.13 shows an example of 0 output/1 output.
In this example, TCNT has been designated as a free-running counter, and settings have been
made such that 0 is output by compare match A, and 1 is output by compare match B. When
the set level and the pin level coincide, the pin level does not change.
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Section 13 Timer Z
TCNT value
H'FFFF
H'0000 Time
FTIOB No change No change
FTIOA No change No change
Figure 13.13 Example of 0 Output/1 Output Operation
Figure 13.14 shows an example of toggle output.

In this example, TCNT has been designated as a periodic counter (with counter clearing on
compare match B), and settings have been made such that the output is toggled by both
compare match A and compare match B.
TCNT value
GRB
GRA
H'0000 Time
FTIOB Toggle output
FTIOA
Toggle output
Figure 13.14 Example of Toggle Output Operation
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REJ09B0216-0300
Section 13 Timer Z
2. Output compare timing

The compare match signal is generated in the last state in which TCNT and GR match (when
TCNT changes from the matching value to the next value). When the compare match signal is
generated, the output value selected in TIOR is output at the compare match output pin
(FTIOA, FTIOB, FTIOC, or FTIOD). When TCNT matches GR, the compare match signal is
generated only after the next TCNT input clock pulse is input.
Figure 13.15 shows an example of the output compare timing.
TCNT input
TCNT N N+1
GR N
Compare match
signal
FTIOA to FTIOD
Figure 13.15 Output Compare Timing
13.4.3 Input Capture Function
The TCNT value can be transferred to GR on detection of the input edge of the input
capture/output compare pin (FTIOA, FTIOB, FTIOC, or FTIOD). Rising edge, falling edge, or
both edges can be selected as the detected edge. When the input capture function is used, the pulse
width or period can be measured.
Figure 13.16 shows an example of the input capture operation setting procedure.
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Section 13 Timer Z
Input selection [1] Designate GR as an input capture

register by means of TIOR, and select
rising edge, falling edge, or both edges
as the input edge of the input capture
signal.
Select input edge of [2] Set the STR bit in TSTR to 1 to start the
[1] TCNT counter operation.
input capture
Start counter operation [2]
<Input capture operation>
Figure 13.16 Example of Input Capture Operation Setting Procedure
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REJ09B0216-0300
Section 13 Timer Z
1. Example of input capture operation

Figure 13.17 shows an example of input capture operation.
In this example, both rising and falling edges have been selected as the FTIOA pin input
capture input edge, the falling edge has been selected as the FTIOB pin input capture input
edge, and counter clearing by GRB input capture has been designated for TCNT.
TCNT value Counter cleared by FTIOB input (falling edge)
H'0180
H'0160
H'0005
H'0000
Time
FTIOB
FTIOA
GRA H'0005 H'0160
GRB H'0180
Figure 13.17 Example of Input Capture Operation
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REJ09B0216-0300
Section 13 Timer Z
2. Input capture signal timing

Input capture on the rising edge, falling edge, or both edges can be selected through settings in
TIOR. Figure 13.18 shows the timing when the rising edge is selected. The pulse width of the
input capture signal must be at least two system clock (φ) cycles.
Input capture input
Input capture signal
TCNT N
GR N
Figure 13.18 Input Capture Signal Timing
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REJ09B0216-0300
Section 13 Timer Z
13.4.4 Synchronous Operation
In synchronous operation, the values in a number of TCNT counters can be rewritten

simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared
simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous
operation enables GR to be increased with respect to a single time base.
Figure 13.19 shows an example of the synchronous operation setting procedure.
Synchronous operation
selection
Set synchronous
operation [1]
Synchronous presetting Synchronous clearing
Clearing No
source generation
Set TCNT [2] channel?
Yes
Select counter Select counter

[3] [4]
clearing source clearing source
Start counter operation [5] Start counter operation [5]
<Synchronous presetting> <Counter clearing> <Synchronous clearing>
[1] Set the SYNC bits in TMDR to 1.

[2] When a value is written to either of the TCNT counters, the same value is simultaneously written to the
other TCNT counter.
[3] Set bits CCLR1 and CCLR0 in TCR to specify counter clearing by compare match/input capture.
[4] Set bits CCLR1 and CCLR0 in TCR to designate synchronous clearing for the counter clearing source.
[5] Set the STR bit in TSTR to 1 to start the count operation.
Figure 13.19 Example of Synchronous Operation Setting Procedure
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REJ09B0216-0300
Section 13 Timer Z
Figure 13.20 shows an example of synchronous operation. In this example, synchronous operation
has been selected, FTIOB0 and FTIOB1 have been designated for PWM mode, GRA_0 compare
match has been set as the channel 0 counter clearing source, and synchronous clearing has been set
for the channel 1 counter clearing source. In addition, the same input clock has been set as the
counter input clock for channel 0 and channel 1. Two-phase PWM waveforms are output from
pins FTIOB0 and FTIOB1. At this time, synchronous presetting and synchronous operation by
GRA_0 compare match are performed by TCNT counters.
For details on PWM mode, see section 13.4.5, PWM Mode.
TCNT values
Synchronous clearing by GRA_0 compare match
GRA_0
GRA_1
GRB_0
GRB_1
H'0000 Time
FTIOB0
FTIOB1
Figure 13.20 Example of Synchronous Operation
13.4.5 PWM Mode
In PWM mode, PWM waveforms are output from the FTIOB, FTIOC, and FTIOD output pins
with GRA as a cycle register and GRB, GRC, and GRD as duty registers. The initial output level
of the corresponding pin depends on the setting values of TOCR and POCR. Table 13.3 shows an
example of the initial output level of the FTIOB0 pin.
The output level is determined by the POLB to POLD bits corresponding to POCR. When POLB
is 0, the FTIOB output pin is set to 0 by compare match B and set to 1 by compare match A.
When POLB is 1, the FTIOB output pin is set to 1 by compare match B and cleared to 0 by
compare match A. In PWM mode, maximum 6-phase PWM outputs are possible.
Figure 13.21 shows an example of the PWM mode setting procedure.
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REJ09B0216-0300
Section 13 Timer Z
Table 13.3 Initial Output Level of FTIOB0 Pin
TOB0 POLB Initial Output Level

0 0 1
0 1 0
1 0 0
1 1 1
PWM mode
[1] Select the counter clock with bits TPSC2

to TOSC0 in TCR. When an external
Select counter clock [1] clock is selected, select the external
clock edge with bits CKEG1 and CKEG0
in TCR.
Select counter clearing source [2] [2] Use bits CCLR1 and CCLR0 in TCR to
select the counter clearing source.
[3] Select the PWM mode with bits PWMB0
to PWMD0 and PWMB1 to PWMD1 in
Set PWM mode [3] TPMR.
[4] Set the initial output value with bits
TOB0 to TOD0 and TOB1 to TOD1 in
TOCR.
Set initial output level [4]
[5] Set the output level with bits POLB to
POLD in POCR.
[6] Set the cycle in GRA, and set the duty in
Select output level [5] the other GR.
[7] Enable or disable the timer output by
TOER.
[8] Set the STR bit in TSTR to 1 and start
Set GR [6] the counter operation.
<PWM mode>
Figure 13.21 Example of PWM Mode Setting Procedure
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REJ09B0216-0300
Section 13 Timer Z
Figure 13.22 shows an example of operation in PWM mode. The output signals go to 1 and TCNT
is reset at compare match A, and the output signals go to 0 at compare match B, C, and D (TOB,
TOC, and TOD = 0, POLB, POLC, and POLD = 0).
Counter cleared by GRA compare match

TCNT value
GRA
GRB
GRC
GRD
H'0000 Time
FTIOB
FTIOC
FTIOD
Figure 13.22 Example of PWM Mode Operation (1)
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REJ09B0216-0300
Section 13 Timer Z
Figure 13.23 shows another example of operation in PWM mode. The output signals go to 0 and
TCNT is reset at compare match A, and the output signals go to 1 at compare match B, C, and D
(TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 1).

TCNT value
GRA
GRB
GRC
GRD
H'0000 Time
FTIOB
FTIOC
FTIOD
Figures 13.24 (when TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 0) and 13.25 (when
TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 1) show examples of the output of PWM
waveforms with duty cycles of 0% and 100% in PWM mode.
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REJ09B0216-0300
Section 13 Timer Z
TCNT value
GRB rewritten
GRA
GRB
GRB rewritten
H'0000 Time
FTIOB 0% duty
When cycle register and duty register compare matches

occur simultaneously, duty register compare match has
TCNT value priority.
GRB rewritten
GRA
GRB rewritten
GRB rewritten
GRB
H'0000 Time
FTIOB 100% duty

priority.
TCNT value
GRB rewritten
GRB rewritten
GRA
GRB rewritten
GRB
H'0000 Time
FTIOB 100% duty 0% duty
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REJ09B0216-0300
Section 13 Timer Z
TCNT value GRB rewritten
GRA
GRB
GRB rewritten
H'0000 Time
FTIOB 0% duty

priority.
TCNT value
GRB rewritten
GRA
GRB rewritten
GRB rewritten
GRB
H'0000 Time
FTIOB 100% duty

priority.
TCNT value
GRB rewritten
GRB rewritten
GRA
GRB rewritten
GRB
H'0000 Time
FTIOB 100% duty 0% duty
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REJ09B0216-0300
Section 13 Timer Z
13.4.6 Reset Synchronous PWM Mode
Three normal- and counter-phase PWM waveforms are output by combining channels 0 and 1 that
one of changing points of waveforms will be common.
In reset synchronous PWM mode, the FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1 pins become
PWM-output pins automatically. TCNT_0 performs an increment operation. Tables 13.4 and
13.5 show the PWM-output pins used and the register settings, respectively.
Figure 13.26 shows the example of reset synchronous PWM mode setting procedure.
Table 13.4 Output Pins in Reset Synchronous PWM Mode
Channel Pin Name Input/Output Pin Function

0 FTIOC0 Output Toggle output in synchronous with PWM cycle
0 FTIOB0 Output PWM output 1
0 FTIOD0 Output PWM output 1 (counter-phase waveform of PWM
output 1)
1 FTIOA1 Output PWM output 2
1 FTIOC1 Output PWM output 2 (counter-phase waveform of PWM
output 2)
1 FTIOD1 Output PWM output 3 (counter-phase waveform of PWM
output 3)
Table 13.5 Register Settings in Reset Synchronous PWM Mode
Register Description
TCNT_0 Initial setting of H'0000
TCNT_1 Not used (independently operates)
GRA_0 Sets counter cycle of TCNT_0
GRB_0 Set a changing point of the PWM waveform output from pins FTIOB0 and
FTIOD0.
GRA_1 Set a changing point of the PWM waveform output from pins FTIOA1 and
FTIOC1.
FTIOD1.
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Section 13 Timer Z
Reset synchronous PWM mode
[1] Clear bit STR0 in TSTR to 0 and stop the

counter operation of TCNT_0. Set reset
[1] synchronous PWM mode after TCNT_0
Stop counter operation
stops.
[2] Select the counter clock with bits TPSC2
to TOSC0 in TCR. When an external
clock is selected, select the external clock
Select counter clock [2]
edge with bits CKEG1 and CKEG0 in
TCR.
[3] Use bits CCLR1 and CCLR0 in TCR to
select counter clearing source GRA_0.
Select counter clearing source [3]
[4] Select the reset synchronous PWM mode
with bits CMD1 and CMD0 in TFCR.
FTIOB0 to FTIOD0 and FTIOA1 to
FTIOD1 become PWM output pins
Set reset synchronous PWM mode [4] automatically.
[5] Set H'00 to TOCR.
[6] Set TCNT_0 as H'0000. TCNT1 does not
need to be set.
Initialize the output pin [5] [7] GRA_0 is a cycle register. Set a cycle for
GRA_0. Set the changing point timing of
the PWM output waveform for GRB_0,
GRA_1, and GRB_1.
Set TCNT [6] [8] Enable or disable the timer output by
TOER.
[9] Set the STR bit in TSTR to 1 and start the
counter operation.
Set GR [7]
<Reset synchronous PWM mode>
Figure 13.26 Example of Reset Synchronous PWM Mode Setting Procedure
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REJ09B0216-0300
Section 13 Timer Z
Figures 13.27 and 13.28 show examples of operation in reset synchronous PWM mode.

TCNT value
GRA_0
GRB_0
GRA_1
GRB_1
H'0000 Time
FTIOB0
FTIOD0
FTIOA1
FTIOC1
FTIOB1
FTIOD1
FTIOC0
Figure 13.27 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 1)
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REJ09B0216-0300
Section 13 Timer Z

TCNT value
GRA_0
GRB_0
GRA_1
GRB_1
H'0000 Time
FTIOB0
FTIOD0
FTIOA1
FTIOC1
FTIOB1
FTIOD1
FTIOC0
Figure 13.28 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 0)
In reset synchronous PWM mode, TCNT_0 and TCNT_1 perform increment and independent
operations, respectively. However, GRA_1 and GRB_1 are separated from TCNT_1. When a
compare match occurs between TCNT_0 and GRA_0, a counter is cleared and an increment
operation is restarted from H'0000.
The PWM pin outputs 0 or 1 whenever a compare match between GRB_0, GRA_1, GRB_1 and
TCNT_0 or counter clearing occur.
For details on operations when reset synchronous PWM mode and buffer operation are
simultaneously set, refer to section 13.4.8, Buffer Operation.
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REJ09B0216-0300
Section 13 Timer Z
13.4.7 Complementary PWM Mode
Three PWM waveforms for non-overlapped normal and counter phases are output by combining
channels 0 and 1.
In complementary PWM mode, the FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1 pins become
PWM-output pins automatically. TCNT_0 and TCNT_1 perform an increment or decrement
operation. Tables 13.6 and 13.7 show the output pins and register settings in complementary PWM
mode, respectively.
Figure 13.29 shows the example of complementary PWM mode setting procedure.
Table 13.6 Output Pins in Complementary PWM Mode
Channel Pin Name Input/Output Pin Function

0 FTIOC0 Output Toggle output in synchronous with PWM cycle
0 FTIOD0 Output PWM output 1 (counter-phase waveform non-
overlapped with PWM output 1)
1 FTIOA1 Output PWM output 2
1 FTIOC1 Output PWM output 2 (counter-phase waveform non-
1 FTIOD1 Output PWM output 3 (counter-phase waveform non-
Table 13.7 Register Settings in Complementary PWM Mode
Register Description
TCNT_0 Initial setting of non-overlapped periods (non-overlapped periods are differences
with TCNT_1)
TCNT_1 Initial setting of H'0000
GRA_0 Sets (upper limit value – 1) of TCNT_0
FTIOD0.
GRA_1 Set a changing point of the PWM waveform output from pins FTIOA1 and
FTIOC1.
FTIOD1.
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Section 13 Timer Z
Complementary PWM mode [1] Clear bits STR0 and STR1 in TSTR to 0,
and stop the counter operation of
TCNT_0. Stop TCNT_0 and TCNT_1 and
set complementary PWM mode.
Stop counter operation [1] [2] Write H'00 to TOCR.
[3] Use bits TPSC2 to TPSC0 in TCR to
select the same counter clock for channels
0 and 1. When an external clock is
Initialize output pin [2]
selected, select the edge of the external
clock by bits CKEG1 and CKEG0 in TCR.
Do not use bits CCLR1 and CCLR0 in
Select counter clock [3] TCR to clear the counter.
[4] Use bits CMD1 and CMD0 in TFCR to set
complementary PWM mode. FTIOB0 to
Set complementary FTIOD0 and FTIOA1 to FTIOD1
[4] automatically become PWM output pins.
PWM mode
[5] Set H'00 to TOCR.
[6] TCNT_1 must be H'0000. Set a non-
overlapped period to TCNT_0.
Initialize output pin [5]
[7] GRA_0 is a cycle register. Set the cycle to
GRA_0. Set the timing to change the
PWM output waveform to GRB_0, GRA_1,
Set TCNT [6] and GRB_1. Note that the timing must be
set within the range of compare match
carried out for TCNT_0 and TCNT_1.
Set GR [7] For GR settings, see 3. Setting GR Value
in Complementary PWM Mode in section
13.4.7, Complementary PWM Mode.
[8] Use TOER to enable or disable the timer
Enable waveform output [8] output.
[9] Set the STR0 and STR1 bits in TSTR to 1
to start the count operation.
<Complementary PWM mode>
Note: To re-enter complementary PWM mode, first, enter a mode other than the complementary
PWM mode. After that, repeat the setting procedures from step [1].
For settings of waveform outputs with a duty cycle of 0% and 100%, see the settings shown
in 2. Examples of Complementary PWM Mode Operation and 3. Setting GR Value in
Complementary PWM Mode in section 13.4.7, Complementary PWM Mode.
Figure 13.29 Example of Complementary PWM Mode Setting Procedure
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Section 13 Timer Z
1. Canceling Procedure of Complementary PWM Mode: Figure 13.30 shows the complementary
PWM mode canceling procedure.
Complementary PWM mode
[1] Clear bit CMD1 in TFCR to 0, and set

channels 0 and 1 to normal operation.
Stop counter operation [1] [2] After setting channels 0 and 1 to normal
operation, clear bits STR0 and STR1 in
TSTR to 0 and stop TCNT0 and TCNT1.
Cancel complementary
[2]
PWM mode
<Normal operation>
Figure 13.30 Canceling Procedure of Complementary PWM Mode
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REJ09B0216-0300
Section 13 Timer Z
2. Examples of Complementary PWM Mode Operation: Figure 13.31 shows an example of

complementary PWM mode operation. In complementary PWM mode, TCNT_0 and TCNT_1
perform an increment or decrement operation. When TCNT_0 and GRA_0 are compared and
their contents match, the counter is decremented, and when TCNT_1 underflows, the counter
is incremented. In GRA_0, GRA_1, and GRB_1, compare match is carried out in the order of
TCNT_0 → TCNT_1 → TCNT_1 → TCNT_0 and PWM waveform is output, during one
cycle of a up/down counter. In this mode, the initial setting will be TCNT_0 > TCNT_1.
TCNT_0 and GRA_0 are compared and their contents match

TCNT values
GRA_0
GRB_0
GRA_1
GRB_1
H'0000 Time
FTIOB0
FTIOD0
FTIOA1
FTIOC1
FTIOB1
FTIOD1
FTIOC0
Figure 13.31 Example of Complementary PWM Mode Operation (1)
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Section 13 Timer Z
Figure 13.32 (1) and (2) show examples of PWM waveform output with 0% duty and 100% duty
in complementary PWM mode (for one phase).
• TPSC2 = TPSC1 = TPSC0 = 0

Set GRB_0 to H'0000 or a value equal to or more than GRA_0. The waveform with a duty
cycle of 0% and 100% can be output. When buffer operation is used together, the duty cycles
can easily be changed, including the above settings, during operation. For details on buffer
operation, refer to section 13.4.8, Buffer Operation.
• Other than TPSC2 = TPSC1 = TPSC0 = 0
Set GRB_0 to satisfy the following expression: GRA_0 + 1 < GRB_0 < H'FFFF. The
waveform with a duty cycle of 0% and 100% can be output. For details on 0%- and 100%-duty
cycle waveform output, see 3.C., Outputting a waveform with a duty cycle of 0% and 100% in
section 13.4.7, Complementary PWM Mode.
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Section 13 Timer Z
TCNT values
GRA0
GRB0
H'0000 Time
FTIOB0
FTIOD0
0% duty
(a) When duty is 0%
TCNT values
GRA0
GRB0
H'0000 Time
FTIOB0
FTIOD0
100% duty
(b) When duty is 100%

(TPSC2 = TPSC1 = TPSC0 = 0) (2)
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Section 13 Timer Z
TCNT values
GRA0
GRB0
H'0000 Time
FTIOB0
FTIOD0
0% duty
(a) When duty is 0%
TCNT values
GRA0
GRB0
H'0000 Time
FTIOB0
FTIOD0
100% duty
(b) When duty is 100%

(TPSC2 = TPSC1 = TPSC0 ≠ 0) (3)
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Section 13 Timer Z
In complementary PWM mode, when the counter switches from up-counter to down-counter or
vice versa, TCNT_0 and TCNT_1 overshoots or undershoots, respectively. In this case, the
conditions to set the IMFA flag in channel 0 and the UDF flag in channel 1 differ from usual
settings. Also, the transfer conditions in buffer operation differ from usual settings. Such timings
are shown in figures 13.33 and 13.34.
TCNT N-1 N N+1 N N-1
GRA_0 N
IMFA
Set to 1
Flag is not set
Buffer transfer signal
GR
Transferred
to buffer Not transferred
to buffer
Figure 13.33 Timing of Overshooting
TCNT H'0001 H'0000 H'FFFF H'0000 H'0001
Flag is not set
UDF
Set to 1
Buffer transfer signal
GR
Transferred
to buffer
Not transferred
to buffer
Figure 13.34 Timing of Undershooting
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Section 13 Timer Z
When the counter is incremented or decremented, the IMFA flag of channel 0 is set to 1, and when
the register is underflowed, the UDF flag of channel 0 is set to 1. After buffer operation has been
designated for BR, BR is transferred to GR when the counter is incremented by compare match
A0 or when TCNT_1 is underflowed. If the φ or φ/2 clock is selected by TPSC2 to TPSC0 bits,
the OVF flag is not set to 1 at the timing that the counter value changes from H'FFFF to H'0000. If
the φ/4 or φ/8 clock is selected by TPSC2 to TPSC0 bits, the OVF flag is set to 1.
3. Setting GR Value in Complementary PWM Mode: To set the general register (GR) or modify
GR during operation in complementary PWM mode, refer to the following notes.
A. Initial value
a. When other than TPSC2 = TPSC1 = TPSC0 = 0, the GRA_0 value must be equal to
H'FFFC or less. When TPSC2 = TPSC1 = TPSC0 = 0, the GRA_0 value can be set to
H'FFFF or less.
b. H'0000 to T – 1 (T: Initial value of TCNT0) must not be set for the initial value.
c. GRA_0 – (T – 1) or more must not be set for the initial value.
d. When using buffer operation, the same values must be set in the buffer registers and
corresponding general registers.
B. Modifying the setting value
a. Writing to GR directly must be performed while the TCNT_1 and TCNT_0 values
should satisfy the following expression: H'0000 ≤ TCNT_1 < previous GR value, and
previous GR value < TCNT_0 ≤ GRA_0. Otherwise, a waveform is not output
correctly. For details on outputting a waveform with a duty cycle of 0% and 100%, see
C., Outputting a waveform with a duty cycle of 0% and 100%.
b. Do not write the following values to GR directly. When writing the values, a waveform
is not output correctly.
H'0000 ≤ GR ≤ T − 1 and GRA_0 − (T − 1) ≤ GR < GRA_0 when TPSC2 = TPSC1 =
TPSC0 = 0
H'0000 < GR ≤ T − 1 and GRA_0 − (T − 1) ≤ GR < GRA_0 + 1 when TPSC2 = TPSC1
= TPSC0 = 0
c. Do not change settings of GRA_0 during operation.
C. Outputting a waveform with a duty cycle of 0% and 100%
a. Buffer operation is not used and TPSC2 = TPSC1 = TPSC0 = 0
Write H'0000 or a value equal to or more than the GRA_0 value to GR directly at the
timing shown below.
• To output a 0%-duty cycle waveform, write a value equal to or more than the GRA_0
value while H'0000 ≤ TCNT_1 < previous GR value
• To output a 100%-duty cycle waveform, write H'0000 while previous GR value<
TCNT_0 ≤ GRA_0
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Section 13 Timer Z
To change duty cycles while a waveform with a duty cycle of 0% or 100% is being
output, make sure the following procedure.
• To change duty cycles while a 0%-duty cycle waveform is being output, write to GR
while H'0000 ≤ TCNT_1 < previous GR value
while previous GR value< TCNT_0 ≤ GRA_0
Note that changing from a 0%-duty cycle waveform to a 100%-duty cycle waveform
and vice versa is not possible.
b. Buffer operation is used and TPSC2 = TPSC1 = TPSC0 = 0
Write H'0000 or a value equal to or more than the GRA_0 value to the buffer register.
• To output a 0%-duty cycle waveform, write a value equal to or more than the GRA_0
value to the buffer register
• To output a 100%-duty cycle waveform, write H'0000 to the buffer register
For details on buffer operation, see section 13.4.8, Buffer Operation.
c. Buffer operation is not used and other than TPSC2 = TPSC1 = TPSC0 = 0
Write a value which satisfies GRA_0 + 1 < GR < H'FFFF to GR directly at the timing
shown below.
• To output a 0%-duty cycle waveform, write the value while H'0000 ≤ TCNT_1 <
previous GR value
• To output a 100%-duty cycle waveform, write the value while previous GR value<
TCNT_0 ≤ GRA_0
To change duty cycles while a waveform with a duty cycle of 0% and 100% is being
output, the following procedure must be followed.
while H'0000 ≤ TCNT_1 < previous GR value
while previous GR value< TCNT_0 ≤ GRA_0
Note that changing from a 0%-duty cycle waveform to a 100%-duty cycle waveform
and vice versa is not possible.
d. Buffer operation is used and other than TPSC2 = TPSC1 = TPSC0 = 0
Write a value which satisfies GRA_0 + 1 < GR < H'FFFF to the buffer register. A
waveform with a duty cycle of 0% can be output. However, a waveform with a duty
cycle of 100% cannot be output using the buffer operation. Also, the buffer operation
cannot be used to change duty cycles while a waveform with a duty cycle of 100% is
being output. For details on buffer operation, see section 13.4.8, Buffer Operation.
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Section 13 Timer Z
13.4.8 Buffer Operation
Buffer operation differs depending on whether GR has been designated for an input capture
register or an output compare register, or in reset synchronous PWM mode or complementary
PWM mode.
Table 13.8 shows the register combinations used in buffer operation.
Table 13.8 Register Combinations in Buffer Operation
General Register Buffer Register

GRA GRC
GRB GRD
1. When GR is an output compare register

When a compare match occurs, the value in the buffer register of the corresponding channel is
transferred to the general register.
This operation is illustrated in figure 13.35.
Compare match signal
General
Buffer register Comparator TCNT
register
Figure 13.35 Compare Match Buffer Operation
2. When GR is an input capture register

When an input capture occurs, the value in TCNT is transferred to the general register and the
value previously stored in the general register is transferred to the buffer register.
This operation is illustrated in figure 13.36.
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Section 13 Timer Z
Input capture
signal
General TCNT
Buffer register
register
Figure 13.36 Input Capture Buffer Operation
3. Complementary PWM Mode

When the counter switches from counting up to counting down or vice versa, the value of the
buffer register is transferred to the general register. Here, the value of the buffer register is
transferred to the general register in the following timing:
A. When TCNT_0 and GRA_0 are compared and their contents match
B. When TCNT_1 underflows
4. Reset Synchronous PWM Mode

The value of the buffer register is transferred from compare match A0 to the general register.
5. Example of Buffer Operation Setting Procedure
Figure 13.37 shows an example of the buffer operation setting procedure.
Buffer operation [1] Designate GR as an input capture register

or output compare register by means of
TIOR.
[2] Designate GR for buffer operation with bits
Select GR function [1] BFD1, BFC1, BFD0, or BFC0 in TMDR.
[3] Set the STR bit in TSTR to 1 to start the
count operation of TCNT.
Set buffer operation [2]
Start count operation [3]
<Buffer operation>
Figure 13.37 Example of Buffer Operation Setting Procedure
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REJ09B0216-0300
Section 13 Timer Z
6. Examples of Buffer Operation

Figure 13.38 shows an operation example in which GRA has been designated as an output
compare register, and buffer operation has been designated for GRA and GRC.
This is an example of TCNT operating as a periodic counter cleared by compare match B.
Pins FTIOA and FTIOB are set for toggle output by compare match A and B.
As buffer operation has been set, when compare match A occurs, the FTIOA pin performs
toggle outputs and the value in buffer register is simultaneously transferred to the general
register. This operation is repeated each time that compare match A occurs.
The timing to transfer data is shown in figure 13.39.
Counter is cleared by GBR compare match

TCNT value
GRB
H'0250
H'0200
H'0100
H'0000 Time
GRC H'0200 H'0100 H'0200
GRA H'0250 H'0200 H'0100 H'0200
FTIOB
FTIOA
Compare match A

(Buffer Operation for Output Compare Register)
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Section 13 Timer Z
TCNT n n+1
Compare match
signal
Buffer transfer
signal
GRC N
GRA n N
Figure 13.39 Example of Compare Match Timing for Buffer Operation
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Section 13 Timer Z
Figure 13.40 shows an operation example in which GRA has been designated as an input capture
register, and buffer operation has been designated for GRA and GRC.
Counter clearing by input capture B has been set for TCNT, and falling edges have been selected
as the FIOCB pin input capture input edge. And both rising and falling edges have been selected
as the FIOCA pin input capture input edge.
As buffer operation has been set, when the TCNT value is stored in GRA upon the occurrence of
input capture A, the value previously stored in GRA is simultaneously transferred to GRC. The
transfer timing is shown in figure 13.41.
Counter is cleared by the input capture B

TCNT value
H'0180
H'0160
H'0005
H'0000 Time
FTIOB
FTIOA
GRA H'0005 H'0160
GRC H'0005 H'0160
GRB H'0180
Input capture A

(Buffer Operation for Input Capture Register)
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Section 13 Timer Z
FTIO pin
Input capture
signal
TCNT n n+1 N N+1
GRA M n n N
GRC m M M n
Figure 13.41 Input Capture Timing of Buffer Operation
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REJ09B0216-0300
Section 13 Timer Z
Figures 13.42 and 13.43 show the operation examples when buffer operation has been designated
for GRB_0 and GRD_0 in complementary PWM mode. These are examples when a PWM
waveform of 0% duty is created by using the buffer operation and performing GRD_0 ≥ GRA_0.
Data is transferred from GRD_0 to GRB_0 according to the settings of CMD_0 and CMD_1 when
TCNT_0 and GRA_0 are compared and their contents match or when TCNT_1 underflows.
However, when GRD_0 ≥ GRA_0, data is transferred from GRD_0 to GRB_0 when TCNT_1
underflows regardless of the setting of CMD_0 and CMD_1. When GRD_0 = H'0000, data is
transferred from GRD_0 to GRB_0 when TCNT_0 and GRA_0 are compared and their contents
match regardless of the settings of CMD_0 and CMD_1.
TCNT values GRB_0 (When restored, data will be transferred

TCNT_0 to the saved location regardless of the
CMD1 and CMD0 values)
GRA_0
TCNT_1
H'0999
H'0000 Time
GRD_0 H'0999 H'1FFF H'0999
GRB_0 H'0999 H'0999 H'1FFF H'0999
FTIOB0
FTIOD0

(Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1)
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Section 13 Timer Z
GRB_0 (When restored, data will be transferred

TCNT values to the saved location regardless of the
TCNT_0 CMD1 and CMD0 values)
GRA_0
TCNT_1
H'0999
H'0000 Time
GRB_0
GRD_0 H'0999 H'0000 H'0999
GRB_0 H'0999 H'0000 H'0999
FTIOC0
FTIOD0

(Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1)
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Section 13 Timer Z
13.4.9 Timer Z Output Timing
The outputs of channels 0 and 1 can be disabled or inverted by the settings of TOER and TOCR
and the external level.
1. Output Disable/Enable Timing of Timer Z by TOER: Setting the master enable bit in TOER to
1 disables the output of timer Z. By setting the PCR and PDR of the corresponding I/O port
beforehand, any value can be output. Figure 13.44 shows the timing to enable or disable the
output of timer Z by TOER.
T1 T2
Address bus TOER address
TOER N H'FF
Timer Z I/O port

Timer output
output pin
Timer Z output I/O port
Figure 13.44 Example of Output Disable Timing of Timer Z by Writing to TOER
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Section 13 Timer Z
2. Output Disable Timing of Timer Z by External Trigger: When P54/WKP4 is set as a WKP4
input pin, and low level is input to WKP4, the master enable bit in TOER is set to 1 and the
output of timer Z will be disabled.
WKP4
TOER N H'FF
Timer Z I/O port

Timer Z output
output pin
Timer Z output I/O port
Figure 13.45 Example of Output Disable Timing of Timer Z by External Trigger
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Section 13 Timer Z
3. Output Inverse Timing by TFCR: The output level can be inverted by inverting the OLS1 and
OLS0 bits in TFCR in reset synchronous PWM mode or complementary PWM mode. Figure
T1 T2
Address bus TOER address
TFCR
Timer Z
output pin
Inverted
Figure 13.46 Example of Output Inverse Timing of Timer Z by Writing to TFCR
4. Output Inverse Timing by POCR: The output level can be inverted by inverting the POLD,
POLC, and POLB bits in POCR in PWM mode. Figure 13.47 shows the timing.
T1 T2
Address bus POCR address
TFCR
Timer Z
output pin
Inverted
Figure 13.47 Example of Output Inverse Timing of Timer Z by Writing to POCR
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Section 13 Timer Z
13.5 Interrupts
There are three kinds of timer Z interrupt sources; input capture/compare match, overflow, and
underflow. An interrupt is requested when the corresponding interrupt request flag is set to 1 while
the corresponding interrupt enable bit is set to 1.
13.5.1 Status Flag Set Timing
1. IMF Flag Set Timing: The IMF flag is set to 1 by the compare match signal that is generated
when the GR matches with the TCNT. The compare match signal is generated at the last state
of matching (timing to update the counter value when the GR and TCNT match). Therefore,
when the TCNT and GR matches, the compare match signal will not be generated until the
TCNT input clock is generated. Figure 13.48 shows the timing to set the IMF flag.
TCNT input clock
TCNT N N+1
GR N
Compare match
signal
IMF
ITMZ
Figure 13.48 IMF Flag Set Timing when Compare Match Occurs
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Section 13 Timer Z
2. IMF Flag Set Timing at Input Capture: When an input capture signal is generated, the IMF flag
is set to 1 and the value of TCNT is simultaneously transferred to corresponding GR. Figure
Input capture
signal
IMF
TCNT N
GR N
ITMZ
Figure 13.49 IMF Flag Set Timing at Input Capture
3. Overflow Flag (OVF) Set Timing: The overflow flag is set to 1 when the TCNT overflows.
Figure 13.50 shows the timing.
TCNT H'FFFF H'0000
Overflow
signal
OVF
ITMZ
Figure 13.50 OVF Flag Set Timing
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Section 13 Timer Z
13.5.2 Status Flag Clearing Timing
The status flag can be cleared by writing 0 after reading 1 from the CPU. Figure 13.51 shows the
timing in this case.
Address TSR address
WTSR
(internal write signal)
IMF, OVF
ITMZ
Figure 13.51 Status Flag Clearing Timing
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Section 13 Timer Z
13.6 Usage Notes

1. Contention between TCNT Write and Clear Operations: If a counter clear signal is generated
in the T2 state of a TCNT write cycle, TCNT clearing has priority and the TCNT write is not
performed. Figure 13.52 shows the timing in this case.
TCNT write cycle

T1 T2
TCNT address
WTCNT
TCNT N H'0000
Clearing has priority.
Figure 13.52 Contention between TCNT Write and Clear Operations
2. Contention between TCNT Write and Increment Operations: If increment is done in T2 state of
a TCNT write cycle, TCNT writing has priority. Figure 13.53 shows the timing in this case.
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Section 13 Timer Z
TCNT write cycle

T1 T2
TCNT address
WTCNT
TCNT input clock
TCNT N M
TCNT write data
Figure 13.53 Contention between TCNT Write and Increment Operations
3. Contention between GR Write and Compare Match: If a compare match occurs in the T2 state
of a GR write cycle, GR write has priority and the compare match signal is disabled. Figure
13.54 shows the timing in this case.
GR write cycle
T1 T2
GR address
WGR
TCNT N N+1
GR N M
GR write data
Compare match Disabled

signal
Figure 13.54 Contention between GR Write and Compare Match
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Section 13 Timer Z
4. Contention between TCNT Write and Overflow/Underflow: If overflow/underflow occurs in

the T2 state of a TCNT write cycle, TCNT write has priority without an increment operation.
At this time, the OVF flag is set to 1. Figure 13.55 shows the timing in this case.
TCNT write cycle

T1 T2
TCNT address
WTCNT
TCNT input clock
Overflow signal
TCNT H'FFFF M
TCNT write data
OVF
Figure 13.55 Contention between TCNT Write and Overflow
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Section 13 Timer Z
5. Contention between GR Read and Input Capture: If an input capture signal is generated in the
T1 state of a GR read cycle, the data that is read will be transferred before input capture
transfer. Figure 13.56 shows the timing in this case.
GR read cycle
T1 T2
GR address
Internal read
signal
Input capture
signal
GR X M
Internal data
bus X
Figure 13.56 Contention between GR Read and Input Capture
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Section 13 Timer Z
6. Contention between Count Clearing and Increment Operations by Input Capture: If an input
capture and increment signals are simultaneously generated, count clearing by the input
capture operation has priority without an increment operation. The TCNT contents before
clearing counter are transferred to GR. Figure 13.57 shows the timing in this case.
Input capture signal
TCNT input clock
TCNT N H'0000
GR N
Clearing has priority.
Figure 13.57 Contention between Count Clearing and Increment Operations

by Input Capture
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Section 13 Timer Z
7. Contention between GR Write and Input Capture: If an input capture signal is generated in the
T2 state of a GR write cycle, the input capture operation has priority and the write to GR is not
performed. Figure 13.58 shows the timing in this case.
GR write cycle
T1 T2
Address bus GR address
WGR
Input capture
signal
TCNT N
GR M
GR write data
Figure 13.58 Contention between GR Write and Input Capture
8. Notes on Setting Reset Synchronous PWM Mode/Complementary PWM Mode: When bits
CMD1 and CMD0 in TFCR are set, note the following:
A. Write bits CMD1 and CMD0 while TCNT_1 and TCNT_0 are halted.
B. Changing the settings of reset synchronous PWM mode to complementary PWM mode or
vice versa is disabled. Set reset synchronous PWM mode or complementary PWM mode
after the normal operation (bits CMD1 and CMD0 are cleared to 0) has been set.
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Section 13 Timer Z
9. Note on Writing to the TOA0 to TOD0 Bits and the TOA1 to TOD1 Bits in TOCR:
The TOA0 to TOD0 bits and the TOA1 to TOD1 bits in TOCR decide the value of the FTIO
pin, which is output until the first compare match occurs. Once a compare match occurs and
this compare match changes the values of FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1
output, the values of the FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 pin output and the
values read from the TOA0 to TOD0 and TOA1 to TOD1 bits may differ. Moreover, when the
writing to TOCR and the generation of the compare match A0 to D0 and A1 to D1 occur at the
same timing, the writing to TOCR has the priority. Thus, output change due to the compare
match is not reflected to the FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 pins. Therefore,
when bit manipulation instruction is used to write to TOCR, the values of the FTIOA0 to
FTIOD0 and FTIOA1 to FTIOD1 pin output may result in an unexpected result. When TOCR
is to be written to while compare match is operating, stop the counter once before accessing to
TOCR, read the port 6 state to reflect the values of FTIOA0 to FTIOD0 and FTIOA1 to
FTIOD1 output, to TOA0 to TOD0 and TOA1 to TOD1, and then restart the counter. Figure
13.59 shows an example when the compare match and the bit manipulation instruction to
TOCR occur at the same timing.
TOCR has been set to H'06. Compare match B0 and compare match C0 are used. The FTIOB0 pin is in the 1 output state,
and is set to the toggle output or the 0 output by compare match B0.
When BCLR#2, @TOCR is executed to clear the TOC0 bit (the FTIOC0 signal is low) and compare match B0 occurs
at the same timing as shown below, the H'02 writing to TOCR has priority and compare match B0 does not drive the FTIOB0 signal low;
the FTIOB0 signal remains high.
Bit 7 6 5 4 3 2 1 0
TOCR TOD1 TOC1 TOB1 TOA1 TOD0 TOC0 TOB0 TOA0
Set value 0 0 0 0 0 1 1 0
BCLR#2, @TOCR
(1) TOCR read operation: Read H'06
(2) Modify operation: Modify H'06 to H'02
(3) Write operation to TOCR: Write H'02
TOCR
write signal
Compare match
signal B0
FTIOB0 pin
Expected output
Remains high because the 1 writing to TOB has priority
Figure 13.59 When Compare Match and Bit Manipulation Instruction to TOCR
Occur at the Same Timing
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The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a
system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow.
The block diagram of the watchdog timer is shown in figure 14.1.
WDT dedicated CLK TCSRWD

internal oscillator
Internal data bus

φ PSS TCWD
TMWD
[Legend] Internal reset

TCSRWD: Timer control/status register WD signal
TCWD: Timer counter WD
PSS: Prescaler S
TMWD: Timer mode register WD
Figure 14.1 Block Diagram of Watchdog Timer
14.1 Features
• Selectable from nine counter input clocks.
Eight clock sources (φ/64, φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096, and φ/8192) or the
WDT dedicated internal oscillator can be selected as the timer-counter clock. When the WDT
dedicated internal oscillator is selected, it can operate as the watchdog timer in any operating
mode.
• Reset signal generated on counter overflow
An overflow period of 1 to 256 times the selected clock can be set.
• The watchdog timer is enabled in the initial state.
It starts operating after the reset state is canceled.
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The watchdog timer has the following registers.
• Timer control/status register WD (TCSRWD)

• Timer counter WD (TCWD)
• Timer mode register WD (TMWD)
14.2.1 Timer Control/Status Register WD (TCSRWD)
TCSRWD performs the TCSRWD and TCWD write control. TCSRWD also controls the
watchdog timer operation and indicates the operating state. TCSRWD must be rewritten by using
the MOV instruction. The bit manipulation instruction cannot be used to change the setting value.
Initial
7 B6WI 1 R/W Bit 6 Write Inhibit
The TCWE bit can be written only when the write value of
the B6WI bit is 0.
6 TCWE 0 R/W Timer Counter WD Write Enable
TCWD can be written when the TCWE bit is set to 1.
When writing data to this bit, the value for bit 7 must be 0.
The TCSRWE bit can be written only when the write
value of the B4WI bit is 0. This bit is always read as 1.
4 TCSRWE 0 R/W Timer Control/Status Register WD Write Enable
The WDON and WRST bits can be written when the
TCSRWE bit is set to 1.
When writing data to this bit, the value for bit 5 must be 0.
This bit can be written to the WDON bit only when the
write value of the B2WI bit is 0.
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Initial
2 WDON 1 R/W Watchdog Timer On
TCWD starts counting up when the WDON bit is set to 1
and halts when the WDON bit is cleared to 0. The
watchdog timer is enabled in the initial state. When the
watchdog timer is not used, clear the WDON bit to 0.
• Reset
• When 1 is written to the WDON bit and 0 is written to
the B2WI bit while the TCSRWE bit = 1
• When 0 is written to the WDON bit and 0 is written to
This bit can be written to the WRST bit only when the
write value of the B0WI bit is 0. This bit is always read as
1.
0 WRST 0 R/W Watchdog Timer Reset
[Setting condition]
• When TCWD overflows and an internal reset signal is
generated
• Reset by the RES pin
• When 0 is written to the WRST bit and 0 is written to
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14.2.2 Timer Counter WD (TCWD)
TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the
internal reset signal is generated and the WRST bit in TCSRWD is set to 1. TCWD is initialized to
H'00.
14.2.3 Timer Mode Register WD (TMWD)
TMWD selects the input clock.
Initial
3 CKS3 1 R/W Clock Select 3 to 0
2 CKS2 1 R/W Select the clock to be input to TCWD.
1 CKS1 1 R/W 1000: Internal clock: counts on φ/64
0 CKS0 1 R/W 1001: Internal clock: counts on φ/128
1010: Internal clock: counts on φ/256
1111: Internal clock: counts on φ8192
0XXX: WDT dedicated internal oscillator
For the overflow periods of the WDT dedicated internal
oscillator, see section 22, Electrical Characteristics.
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14.3 Operation
The watchdog timer is provided with an 8-bit counter. After the reset state is released, TCWD
starts counting up. When the TCWD count value overflows H'FF, an internal reset signal is
generated. The internal reset signal is output for a period of 256 φOSC clock cycles. As TCWD is a
writable counter, it starts counting from the value set in TCWD. An overflow period in the range
of 1 to 256 input clock cycles can therefore be set, according to the TCWD set value. When the
watchdog timer is not used, stop TCWD counting by writing 0 to B2WI and WDON
simultaneously while the TCSRWE bit in TCSRWD is set to 1. (To stop the watchdog timer, two
write accesses to TCSRWD are required.)
Figure 14.2 shows an example of watchdog timer operation.
Example: With 30-ms overflow period when φ = 4 MHz
4 × 106
× 30 × 10–3 = 14.6
8192
Therefore, 256 – 15 = 241 (H'F1) is set in TCW.
TCWD overflow
H'FF
H'F1
TCWD
count value
H'00
H'F1 written H'F1 written to TCWD Reset generated

to TCWD
Internal reset
signal
256 φOSC clock cycles
Figure 14.2 Watchdog Timer Operation Example
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The 14-bit PWM is a pulse division type PWM that can be used for electronic tuner control, etc.
Figure 15.1 shows a block diagram of the 14-bit PWM.
15.1 Features
• Choice of two conversion periods
A conversion period of 32768/φ with a minimum modulation width of 2/φ, or a conversion
period of 16384/φ with a minimum modulation width of 1/φ, can be selected.
• Pulse division method for less ripple
PWCR
Internal data bus

PWDRL
PWDRU
φ/4 PWM waveform

PWM
φ/2 generator
[Legend]
PWCR: PWM control register
PWDRL: PWM data register L
PWDRU: PWM data register U
PWM: PWM output pin
Figure 15.1 Block Diagram of 14-Bit PWM
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Table 15.1 shows the 14-bit PWM pin configuration.

14-bit PWM square-wave output PWM Output 14-bit PWM square-wave output pin
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The 14-bit PWM has the following registers.
• PWM control register (PWCR)

• PWM data register U (PWDRU)
• PWM data register L (PWDRL)
15.3.1 PWM Control Register (PWCR)
PWCR selects the conversion period.
Initial
0 PWCR0 0 R/W Clock Select
0: The input clock is φ/2 (tφ = 2/φ)
 The conversion period is 16384/φ, with a minimum
modulation width of 1/φ
1: The input clock is φ/4 (tφ = 4/φ)
 The conversion period is 32768/φ, with a minimum
modulation width of 2/φ
[Legend]
tφ: Period of PWM clock input
15.3.2 PWM Data Registers U and L (PWDRU, PWDRL)
PWDRU and PWDRL indicate high level width in one PWM waveform cycle. PWDRU and
PWDRL are 14-bit write-only registers, with the upper 6 bits assigned to PWDRU and the lower 8
bits to PWDRL. When read, all bits are always read as 1.
Both PWDRU and PWDRL are accessible only in bytes. Note that the operation is not guaranteed
if word access is performed. When 14-bit data is written in PWDRU and PWDRL, the contents
are latched in the PWM waveform generator and the PWM waveform generation data is updated.
When writing the 14-bit data, the order is as follows: PWDRL to PWDRU.
PWDRU and PWDRL are initialized to H'C000.
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15.4 Operation
When using the 14-bit PWM, set the registers in this sequence:
1. Set the PWM bit in the port mode register 1 (PMR1) to set the P11/PWM pin to function as a
PWM output pin.
2. Set the PWCR0 bit in PWCR to select a conversion period of either.
3. Set the output waveform data in PWDRU and PWDRL. Be sure to write byte data first to
PWDRL and then to PWDRU. When the data is written in PWDRU, the contents of these
registers are latched in the PWM waveform generator, and the PWM waveform generation
data is updated in synchronization with internal signals.
One conversion period consists of 64 pulses, as shown in figure 15.2. The total high-level width
during this period (TH) corresponds to the data in PWDRU and PWDRL. This relation can be
expressed as follows:
TH = (data value in PWDRU and PWDRL + 64) × tφ/2
where tφ is the period of PWM clock input: 2/φ (bit PWCR0 = 0) or 4/φ (bit PWCR0 = 1).
If the data value in PWDRU and PWDRL is from H'FFC0 to H'FFFF, the PWM output stays high.
When the data value is H'C000, TH is calculated as follows:
TH = 64 × tφ/2 = 32 tφ
Conversion period
t f1 t f2 t f63 t f64
t H1 t H2 t H3 t H63 t H64
T H = t H1 + t H2 + t H3 + ... + t H64
t f1 = t f2 = t f3 = ... = t f64
Figure 15.2 Waveform Output by 14-Bit PWM
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This LSI includes a serial communication interface 3 (SCI3), which has independent two channels.
The SCI3 can handle both asynchronous and clock synchronous serial communication. In
asynchronous mode, serial data communication can be carried out using standard asynchronous
communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an
Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial
communication between processors (multiprocessor communication function).
Table 16.1 shows the SCI3 channel configuration and figure 16.1 shows a block diagram of the
SCI3. Since pin functions are identical for each of the two channels (SCI3 and SCI3_2), separate
explanations are not given in this section.
16.1 Features
• Choice of asynchronous or clock synchronous serial communication mode
• Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously.
Double-buffering is used in both the transmitter and the receiver, enabling continuous
transmission and continuous reception of serial data.
• On-chip baud rate generator allows any bit rate to be selected
• External clock or on-chip baud rate generator can be selected as a transfer clock source.
• Six interrupt sources
Transmit-end, transmit-data-empty, receive-data-full, overrun error, framing error, and parity
error.
Asynchronous mode
• Data length: 7 or 8 bits

• Stop bit length: 1 or 2 bits
• Parity: Even, odd, or none
• Receive error detection: Parity, overrun, and framing errors
• Break detection: Break can be detected by reading the RxD pin level directly in the case of a
framing error
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Clock synchronous mode
• Data length: 8 bits

• Receive error detection: Overrun errors
Table 16.1 Channel Configuration
Channel Abbreviation Pin Register Register Address

Channel 1 SCI3* SCK3 SMR H'FFA8
RXD
BRR H'FFA9
TXD
SCR3 H'FFAA
TDR H'FFAB
SSR H'FFAC
RDR H'FFAD
RSR 
TSR 
Channel 2 SCI3_2 SCK3_2 SMR_2 H'F740
RXD_2
BRR_2 H'F741
TXD_2
SCR3_2 H'F742
TDR_2 H'F743
SSR_2 H'F744
RDR_2 H'F745
RSR_2 
TSR_2 
Note: * The channel 1 of the SCI3 is used in on-board programming mode by boot mode.
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External
clock Internal clock (φ/64, φ/16, φ/4, φ)
SCK3
Baud rate generator
BRC BRR
Clock
SMR
Internal data bus

Transmit/receive
control circuit SCR3
SSR
TXD TSR TDR
RXD RSR RDR
Interrupt request
[Legend] (TEI, TXI, RXI, ERI)
RSR: Receive shift register
RDR: Receive data register
TSR: Transmit shift register
TDR: Transmit data register
SMR: Serial mode register
SCR3: Serial control register 3
SSR: Serial status register
BRR: Bit rate register
BRC: Bit rate counter
Figure 16.1 Block Diagram of SCI3
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Table 16.2 shows the SCI3 pin configuration.
Pin Name Abbreviation I/O Function

SCI3 clock SCK3 I/O SCI3 clock input/output
SCI3 receive data input RXD Input SCI3 receive data input
SCI3 transmit data output TXD Output SCI3 transmit data output
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The SCI3 has the following registers for each channel.
• Receive shift register (RSR)

• Receive data register (RDR)
• Transmit shift register (TSR)
• Transmit data register (TDR)
• Serial mode register (SMR)
• Serial control register 3 (SCR3)
• Serial status register (SSR)
• Bit rate register (BRR)
16.3.1 Receive Shift Register (RSR)
RSR is a shift register that is used to receive serial data input from the RxD pin and convert it into
parallel data. When one frame of data has been received, it is transferred to RDR automatically.
RSR cannot be directly accessed by the CPU.
16.3.2 Receive Data Register (RDR)
RDR is an 8-bit register that stores received data. When the SCI3 has received one frame of serial
data, it transfers the received serial data from RSR to RDR, where it is stored. After this, RSR is
receive-enabled. As RSR and RDR function as a double buffer in this way, continuous receive
operations are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only
once. RDR cannot be written to by the CPU. RDR is initialized to H'00.
16.3.3 Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI3 first
transfers transmit data from TDR to TSR automatically, then sends the data that starts from the
LSB to the TXD pin. TSR cannot be directly accessed by the CPU.
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16.3.4 Transmit Data Register (TDR)
TDR is an 8-bit register that stores data for transmission. When the SCI3 detects that TSR is
empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-
buffered structure of TDR and TSR enables continuous serial transmission. If the next transmit
data has already been written to TDR during transmission of one-frame data, the SCI3 transfers
the written data to TSR to continue transmission. To achieve reliable serial transmission, write
transmit data to TDR only once after confirming that the TDRE bit in SSR is set to 1. TDR is
initialized to H'FF.
16.3.5 Serial Mode Register (SMR)
SMR is used to set the SCI3’s serial transfer format and select the baud rate generator clock
source.
Initial
7 COM 0 R/W Communication Mode
0: Asynchronous mode
1: Clock synchronous mode
6 CHR 0 R/W Character Length (enabled only in asynchronous mode)
0: Selects 8 bits as the data length.
1: Selects 7 bits as the data length.
5 PE 0 R/W Parity Enable (enabled only in asynchronous mode)
When this bit is set to 1, the parity bit is added to transmit
data before transmission, and the parity bit is checked in
reception.
4 PM 0 R/W Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
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Initial
3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode)
Selects the stop bit length in transmission.
0: 1 stop bit
1: 2 stop bits
For reception, only the first stop bit is checked, regardless
of the value in the bit. If the second stop bit is 0, it is
treated as the start bit of the next transmit character.
2 MP 0 R/W Multiprocessor Mode
When this bit is set to 1, the multiprocessor
communication function is enabled. The PE bit and PM
bit settings are invalid in multiprocessor mode. In clock
synchronous mode, clear this bit to 0.
1 CKS1 0 R/W Clock Select 0 and 1
0 CKS0 0 R/W These bits select the clock source for the baud rate
generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relationship between the bit rate register setting
and the baud rate, see section 16.3.8, Bit Rate Register
(BRR). n is the decimal representation of the value of n in
BRR (see section 16.3.8, Bit Rate Register (BRR)).
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16.3.6 Serial Control Register 3 (SCR3)
SCR3 is a register that enables or disables SCI3 transfer operations and interrupt requests, and is
also used to select the transfer clock source. For details on interrupt requests, refer to section 16.7,
Interrupts.
Initial
7 TIE 0 R/W Transmit Interrupt Enable
When this bit is set to 1, the TXI interrupt request is
enabled.
6 RIE 0 R/W Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests
are enabled.
5 TE 0 R/W Transmit Enable
When this bit s set to 1, transmission is enabled.
4 RE 0 R/W Receive Enable
When this bit is set to 1, reception is enabled.
3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when the
MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and OER status flags in SSR is disabled.
On receiving data in which the multiprocessor bit is 1, this
bit is automatically cleared and normal reception is
resumed. For details, refer to section 16.6, Multiprocessor
Communication Function.
2 TEIE 0 R/W Transmit End Interrupt Enable
When this bit is set to 1, TEI interrupt request is enabled.
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Initial
1 CKE1 0 R/W Clock Enable 0 and 1
0 CKE0 0 R/W Selects the clock source.
• Asynchronous mode
00: On-chip baud rate generator
01: On-chip baud rate generator
Outputs a clock of the same frequency as the bit rate
from the SCK3 pin.
10: External clock
Inputs a clock with a frequency 16 times the bit rate
from the SCK3 pin.
11:Reserved
• Clock synchronous mode
00: On-chip clock (SCK3 pin functions as clock output)
01: Reserved
10: External clock (SCK3 pin functions as clock input)
11: Reserved
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16.3.7 Serial Status Register (SSR)
SSR is a register containing status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared.
Initial
7 TDRE 1 R/W Transmit Data Register Empty
Indicates whether TDR contains transmit data.
• When the TE bit in SCR3 is 0
• When data is transferred from TDR to TSR
• When 0 is written to TDRE after reading TDRE = 1
• When the transmit data is written to TDR
6 RDRF 0 R/W Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
• When serial reception ends normally and receive data
is transferred from RSR to RDR
• When 0 is written to RDRF after reading RDRF = 1
• When data is read from RDR
5 OER 0 R/W Overrun Error
[Setting condition]
• When an overrun error occurs in reception
• When 0 is written to OER after reading OER = 1
4 FER 0 R/W Framing Error
[Setting condition]
• When a framing error occurs in reception
• When 0 is written to FER after reading FER = 1
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Initial
3 PER 0 R/W Parity Error
[Setting condition]
• When a parity error is detected during reception
• When 0 is written to PER after reading PER = 1
2 TEND 1 R Transmit End
• When the TE bit in SCR3 is 0
• When TDRE = 1 at transmission of the last bit of a 1-
frame serial transmit character
• When 0 is written to TDRE after reading TDRE = 1
• When the transmit data is written to TDR
1 MPBR 0 R Multiprocessor Bit Receive
MPBR stores the multiprocessor bit in the receive
character data. When the RE bit in SCR3 is cleared to 0,
its state is retained.
0 MPBT 0 R/W Multiprocessor Bit Transfer
MPBT stores the multiprocessor bit to be added to the
transmit character data.
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16.3.8 Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 16.3
shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of
SMR in asynchronous mode. Table 16.4 shows the maximum bit rate for each frequency in
asynchronous mode. The values shown in both tables 16.3 and 16.4 are values in active (high-
speed) mode. Table 16.5 shows the relationship between the N setting in BRR and the n setting in
bits CKS1 and CKS0 of SMR in clock synchronous mode. The values shown in table 16.5 are
values in active (high-speed) mode. The N setting in BRR and error for other operating
frequencies and bit rates can be obtained by the following formulas:
[Asynchronous Mode]
φ
N= × 106 – 1
64 × 22n–1 × B
 φ × 106 
Error (%) =  – 1 × 100
(N + 1) × B × 64 × 22n–1 
[Clock Synchronous Mode]
φ
N= × 106 – 1
8 × 22n–1 × B
[Legend]
B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n: CSK1 and CSK0 settings in SMR (0 ≤ n ≤ 3)
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Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
Operating Frequency φ (MHz)

2 2.097152 2.4576 3
Bit Rate Error Error Error Error
(bits/s) n N (%) n N (%) n N (%) n N (%)
110 1 141 0.03 1 148 –0.04 1 174 –0.26 1 212 0.03
150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16
300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16
600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16
1200 0 51 0.16 0 54 –0.70 0 63 0.00 0 77 0.16
2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16
4800 0 12 0.16 0 13 –2.48 0 15 0.00 0 19 –2.34
9600 0 6 –6.99 0 6 –2.48 0 7 0.00 0 9 –2.34
19200 0 2 8.51 0 2 13.78 0 3 0.00 0 4 –2.34
31250 0 1 0.00 0 1 4.86 0 1 22.88 0 2 0.00
38400 0 1 –18.62 0 1 –14.67 0 1 0.00 — — —

3.6864 4 4.9152 5
(bits/s) n N (%) n N (%) n N (%) n N (%)
110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 –0.25
150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16
300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16
600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16
1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16
2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16
4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 –1.36
9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73
19200 0 5 0.00 0 6 –6.99 0 7 0.00 0 7 1.73
31250 — — — 0 3 0.00 0 4 –1.70 0 4 0.00
38400 0 2 0.00 0 2 8.51 0 3 0.00 0 3 1.73
[Legend]
: A setting is available but error occurs
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6 6.144 7.3728
Bit Rate Error Error Error
(bit/s) n N (%) n N (%) n N (%)
110 2 106 –0.44 2 108 0.08 2 130 –0.07
150 2 77 0.16 2 79 0.00 2 95 0.00
300 1 155 0.16 1 159 0.00 1 191 0.00
600 1 77 0.16 1 79 0.00 1 95 0.00
1200 0 155 0.16 0 159 0.00 0 191 0.00
2400 0 77 0.16 0 79 0.00 0 95 0.00
4800 0 38 0.16 0 39 0.00 0 47 0.00
9600 0 19 –2.34 0 19 0.00 0 23 0.00
19200 0 9 –2.34 0 9 0.00 0 11 0.00
31250 0 5 0.00 0 5 2.40 0 6 5.33
38400 0 4 –2.34 0 4 0.00 0 5 0.00

8 9.8304 10 12
(bit/s) n N (%) n N (%) n N (%) n N (%)
110 2 141 0.03 2 174 –0.26 2 177 –0.25 2 212 0.03
150 2 103 0.16 2 127 0.00 2 129 0.16 2 155 0.16
300 1 207 0.16 1 255 0.00 2 64 0.16 2 77 0.16
600 1 103 0.16 1 127 0.00 1 129 0.16 1 155 0.16
1200 0 207 0.16 0 255 0.00 1 64 0.16 1 77 0.16
2400 0 103 0.16 0 127 0.00 0 129 0.16 0 155 0.16
4800 0 51 0.16 0 63 0.00 0 64 0.16 0 77 0.16
9600 0 25 0.16 0 31 0.00 0 32 –1.36 0 38 0.16
19200 0 12 0.16 0 15 0.00 0 15 1.73 0 19 –2.34
31250 0 7 0.00 0 9 –1.70 0 9 0.00 0 11 0.00
38400 0 6 -6.99 0 7 0.00 0 7 1.73 0 9 –2.34
[Legend]
: A setting is available but error occurs.
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12.288 14 14.7456 16
(bit/s) n N (%) n N (%) n N (%) n N (%)
110 2 217 0.08 2 248 –0.17 3 64 0.70 3 70 0.03
150 2 159 0.00 2 181 0.16 2 191 0.00 2 207 0.16
300 2 79 0.00 2 90 0.16 2 95 0.00 2 103 0.16
600 1 159 0.00 1 181 0.16 1 191 0.00 1 207 0.16
1200 1 79 0.00 1 90 0.16 1 95 0.00 1 103 0.16
2400 0 159 0.00 0 181 0.16 0 191 0.00 0 207 0.16
4800 0 79 0.00 0 90 0.16 0 95 0.00 0 103 0.16
9600 0 39 0.00 0 45 –0.93 0 47 0.00 0 51 0.16
19200 0 19 0.00 0 22 –0.93 0 23 0.00 0 25 0.16
31250 0 11 2.40 0 13 0.00 0 14 –1.70 0 15 0.00
38400 0 9 0.00 — — — 0 11 0.00 0 12 0.16

18 20
Bit Rate Error Error
(bit/s) n N (%) n N (%)
110 3 79 –0.12 3 88 –0.25
150 2 233 0.16 3 64 0.16
300 2 116 0.16 2 129 0.16
600 1 233 0.16 2 64 0.16
1200 1 116 0.16 1 129 0.16
2400 0 233 0.16 1 64 0.16
4800 0 116 0.16 0 129 0.16
9600 0 58 –0.96 0 64 0.16
19200 0 28 1.02 0 32 –1.36
31250 0 17 0.00 0 19 0.00
38400 0 14 –2.34 0 15 1.73
[Legend]
—: A setting is available but error occurs.
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Table 16.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
Maximum Bit Maximum Bit

φ (MHz) Rate (bit/s) n N φ (MHz) Rate (bit/s) n N
2 62500 0 0 8 250000 0 0
2.097152 65536 0 0 9.8304 307200 0 0
2.4576 76800 0 0 10 312500 0 0
3 93750 0 0 12 375000 0 0
3.6864 115200 0 0 12.288 384000 0 0
4 125000 0 0 14 437500 0 0
4.9152 153600 0 0 14.7456 460800 0 0
5 156250 0 0 16 500000 0 0
6 187500 0 0 17.2032 537600 0 0
6.144 192000 0 0 18 562500 0 0
7.3728 230400 0 0 20 625000 0 0
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Table 16.5 Examples of BRR Settings for Various Bit Rates (Clock Synchronous Mode) (1)

2 4 8 10 16
Bit Rate
(bit/s) n N n N n N n N n N
110 3 70 — — — — — —
250 2 124 2 249 3 124 — — 3 249
500 1 249 2 124 2 249 — — 3 124
1k 1 124 1 249 2 124 — — 2 249
2.5k 0 199 1 99 1 199 1 249 2 99
5k 0 99 0 199 1 99 1 124 1 199
10k 0 49 0 99 0 199 0 249 1 99
25k 0 19 0 39 0 79 0 99 0 159
50k 0 9 0 19 0 39 0 49 0 79
100k 0 4 0 9 0 19 0 24 0 39
250k 0 1 0 3 0 7 0 9 0 15
500k 0 0* 0 1 0 3 0 4 0 7
1M 0 0* 0 1 — — 0 3
2M 0 0* — — 0 1
2.5M 0 0* — —
4M 0 0*
[Legend]
Blank: No setting is available.
*: Continuous transfer is not possible.
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Table 16.5 Examples of BRR Settings for Various Bit Rates (Clock Synchronous Mode) (2)

18 20
Bit Rate
(bit/s) n N n N
110 — — — —
250 — — — —
500 3 140 3 155
1k 3 69 3 77
2.5k 2 112 2 124
5k 1 224 1 249
10k 1 112 1 124
25k 0 179 0 199
50k 0 89 0 99
100k 0 44 0 49
250k 0 17 0 19
500k 0 8 0 9
1M 0 4 0 4
2M — — — —
2.5M — — 0 1
4M — — — —
[Legend]
Blank: No setting is available.
*: Continuous transfer is not possible.
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16.4 Operation in Asynchronous Mode

Figure 16.2 shows the general format for asynchronous serial communication. One character (or
frame) consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or
low level), and finally stop bits (high level). Inside the SCI3, the transmitter and receiver are
independent units, enabling full-duplex. Both the transmitter and the receiver also have a double-
buffered structure, so data can be read or written during transmission or reception, enabling
continuous data transfer.
LSB MSB 1
Serial Start Parity Mark state
Transmit/receive data Stop bit
data bit bit
1 bit 7 or 8 bits 1 bit 1 or

or none 2 bits
One unit of transfer data (character or frame)
Figure 16.2 Data Format in Asynchronous Communication
16.4.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK3 pin can be selected as the SCI3’s serial clock, according to the setting of the COM bit in
SMR and the CKE0 and CKE1 bits in SCR3. When an external clock is input at the SCK3 pin, the
clock frequency should be 16 times the bit rate used.
When the SCI3 is operated on an internal clock, the clock can be output from the SCK3 pin. The
frequency of the clock output in this case is equal to the bit rate, and the phase is such that the
rising edge of the clock is in the middle of the transmit data, as shown in figure 16.3.
Clock
Serial data 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
1 character (frame)
Figure 16.3 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)
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16.4.2 SCI3 Initialization
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR3 to 0,
then initialize the SCI3 as described below. When the operating mode, or transfer format, is
changed for example, the TE and RE bits must be cleared to 0 before making the change using the
following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing
the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and OER flags, or the
contents of RDR. When the external clock is used in asynchronous mode, the clock must be
supplied even during initialization.
[1] Set the clock selection in SCR3.

Start initialization Be sure to clear bits RIE, TIE, TEIE, and
MPIE, and bits TE and RE, to 0.
When the clock output is selected in

Clear TE and RE bits in SCR3 to 0
asynchronous mode, clock is output
immediately after CKE1 and CKE0
[1]
Set CKE1 and CKE0 bits in SCR3 settings are made. When the clock
output is selected at reception in clocked
synchronous mode, clock is output
Set data transfer format in SMR [2] immediately after CKE1, CKE0, and RE
are set to 1.
Set value in BRR [3] [2] Set the data transfer format in SMR.
Wait [3] Write a value corresponding to the bit

rate to BRR. Not necessary if an
No external clock is used.
1-bit interval elapsed?
[4] Wait at least one bit interval, then set the
TE bit or RE bit in SCR3 to 1. RE
Yes
settings enable the RXD pin to be used.
For transmission, set the TXD bit in
Set TE and RE bits in PMR1 to 1 to enable the TXD output pin
SCR3 to 1, and set RIE, TIE, TEIE, [4] to be used. Also set the RIE, TIE, TEIE,
and MPIE bits. For transmit (TE=1),
also set the TxD bit in PMR1. and MPIE bits, depending on whether
interrupts are required. In asynchronous
mode, the bits are marked at
<Initialization completion> transmission and idled at reception to
wait for the start bit.
Figure 16.4 Sample SCI3 Initialization Flowchart
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16.4.3 Data Transmission
Figure 16.5 shows an example of operation for transmission in asynchronous mode. In

transmission, the SCI3 operates as described below.
1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that
data has been written to TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI3 sets the TDRE flag to 1 and starts
transmission. If the TIE bit is set to 1 at this time, a TXI interrupt request is generated.
Continuous transmission is possible because the TXI interrupt routine writes next transmit data
to TDR before transmission of the current transmit data has been completed.
3. The SCI3 checks the TDRE flag at the timing for sending the stop bit.
4. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
serial transmission of the next frame is started.
5. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark
state” is entered, in which 1 is output. If the TEIE bit in SCR3 is set to 1 at this time, a TEI
interrupt request is generated.
6. Figure 16.6 shows a sample flowchart for transmission in asynchronous mode.
Start Transmit Parity Stop Start Transmit Parity Stop Mark

bit data bit bit bit data bit bit state
Serial 1 0 D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1 1
data
1 frame 1 frame
TDRE
TEND
LSI TXI interrupt TDRE flag TXI interrupt request generated TEI interrupt request
operation request cleared to 0 generated
generated
User Data written
processing to TDR
Figure 16.5 Example of SCI3 Transmission in Asynchronous Mode

(8-Bit Data, Parity, One Stop Bit)
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Start transmission [1] Read SSR and check that the

TDRE flag is set to 1, then write
transmit data to TDR. When data is
[1] Read TDRE flag in SSR
written to TDR, the TDRE flag is
automaticaly cleared to 0.
No [2] To continue serial transmission,
TDRE = 1 read 1 from the TDRE flag to
confirm that writing is possible,
Yes then write data to TDR. When data
is written to TDR, the TDRE flag is
Write transmit data to TDR automaticaly cleared to 0.
[3] To output a break in serial
transmission, after setting PCR to 1
and PDR to 0, clear TxD in PMR1
Yes
[2] All data transmitted? to 0, then clear the TE bit in SCR3
to 0.
No
Read TEND flag in SSR
No
TEND = 1
Yes
No
[3] Break output?
Yes
Clear PDR to 0 and

set PCR to 1
Clear TE bit in SCR3 to 0
<End>
Figure 16.6 Sample Serial Transmission Data Flowchart (Asynchronous Mode)
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16.4.4 Serial Data Reception
Figure 16.7 shows an example of operation for reception in asynchronous mode. In serial
reception, the SCI3 operates as described below.
1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs
internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this time, an
ERI interrupt request is generated. Receive data is not transferred to RDR.
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated.
4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive
data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt
request is generated.
5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is
generated. Continuous reception is possible because the RXI interrupt routine reads the receive
data transferred to RDR before reception of the next receive data has been completed.
Start Receive Parity Stop Start Receive Parity Stop Mark state
bit data bit bit bit data bit bit (idle state)
Serial 1 0 D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 0 1
data
1 frame 1 frame
RDRF
FER
LSI RXI request RDRF 0 stop bit ERI request in

operation cleared to 0 detected response to
framing error
User RDR data read Framing error

processing processing
Figure 16.7 Example of SCI3 Reception in Asynchronous Mode

(8-Bit Data, Parity, One Stop Bit)
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Table 16.6 shows the states of the SSR status flags and receive data handling when a receive error
is detected. If a receive error is detected, the RDRF flag retains its state before receiving data.
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 16.8 shows a sample flow chart
for serial data reception.
Table 16.6 SSR Status Flags and Receive Data Handling
SSR Status Flag

RDRF* OER FER PER Receive Data Receive Error Type
1 1 0 0 Lost Overrun error
0 0 1 0 Transferred to RDR Framing error
0 0 0 1 Transferred to RDR Parity error
1 1 1 0 Lost Overrun error + framing error
1 1 0 1 Lost Overrun error + parity error
0 0 1 1 Transferred to RDR Framing error + parity error
1 1 1 1 Lost Overrun error + framing error +
parity error
Note: * The RDRF flag retains the state it had before data reception.
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Start reception
[1] Read the OER, PER, and FER flags in
SSR to identify the error. If a receive
error occurs, performs the appropriate
error processing.
Read OER, PER, and
[1] [2] Read SSR and check that RDRF = 1,
FER flags in SSR
then read the receive data in RDR.
The RDRF flag is cleared automatically.
Yes [3] To continue serial reception, before the
OER+PER+FER = 1 stop bit for the current frame is
[4]
received, read the RDRF flag and read
No Error processing RDR.
The RDRF flag is cleared automatically.
(Continued on next page) [4] If a receive error occurs, read the OER,
[2] PER, and FER flags in SSR to identify
Read RDRF flag in SSR the error. After performing the
appropriate error processing, ensure
No that the OER, PER, and FER flags are
RDRF = 1
all cleared to 0. Reception cannot be
resumed if any of these flags are set to
Yes
1. In the case of a framing error, a
break can be detected by reading the
Read receive data in RDR value of the input port corresponding to
the RxD pin.
Yes
All data received? [3]
(A) No
Clear RE bit in SCR3 to 0
<End>
Figure 16.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (1)
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[4]
Error processing
No
OER = 1
Yes
Overrun error processing
No
FER = 1
Yes
Yes
Break?
No
Framing error processing
No
PER = 1
Yes
Parity error processing
(A)
Clear OER, PER, and

FER flags in SSR to 0
<End>
Figure 16.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (2)
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16.5 Operation in Clock Synchronous Mode

Figure 16.9 shows the general format for clock synchronous communication. In clock synchronous
mode, data is transmitted or received synchronous with clock pulses. A single character in the
transmit data consists of the 8-bit data starting from the LSB. In clock synchronous serial
communication, data on the transmission line is output from one falling edge of the
synchronization clock to the next. In clock synchronous mode, the SCI3 receives data in
synchronous with the rising edge of the synchronization clock. After 8-bit data is output, the
transmission line holds the MSB state. In clock synchronous mode, no parity or multiprocessor bit
is added. Inside the SCI3, the transmitter and receiver are independent units, enabling full-duplex
communication through the use of a common clock. Both the transmitter and the receiver also
have a double-buffered structure, so data can be read or written during transmission or reception,
enabling continuous data transfer.
8 bits
One unit of transfer data (character or frame)

* *
Synchronization
clock
LSB MSB
Serial data Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Don’t care Don’t care
Note: * High except in continuous transfer
Figure 16.9 Data Format in Clock Synchronous Communication
16.5.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external
synchronization clock input at the SCK3 pin can be selected, according to the setting of the COM
bit in SMR and CKE0 and CKE1 bits in SCR3. When the SCI3 is operated on an internal clock,
the synchronization clock is output from the SCK3 pin. Eight synchronization clock pulses are
output in the transfer of one character, and when no transfer is performed the clock is fixed high.
16.5.2 SCI3 Initialization
Before transmitting and receiving data, the SCI3 should be initialized as described in a sample
flowchart in figure 16.4.
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16.5.3 Serial Data Transmission
Figure 16.10 shows an example of SCI3 operation for transmission in clock synchronous mode.
In serial transmission, the SCI3 operates as described below.
1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI3 recognizes that data
has been written to TDR, and transfers the data from TDR to TSR.
2. The SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR3 is set to 1 at
this time, a transmit data empty interrupt (TXI) is generated.
3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock
mode has been specified, and synchronized with the input clock when use of an external clock
has been specified. Serial data is transmitted sequentially from the LSB (bit 0), from the TxD
pin.
4. The SCI3 checks the TDRE flag at the timing for sending the MSB (bit 7).
5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
of the next frame is started.
6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains
the output state of the last bit. If the TEIE bit in SCR3 is set to 1 at this time, a TEI interrupt
request is generated.
7. The SCK3 pin is fixed high at the end of transmission.
Figure 16.11 shows a sample flow chart for serial data transmission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (OER, FER, or PER) is set to 1.
Make sure that the receive error flags are cleared to 0 before starting transmission.
Serial
clock
Serial
Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
data
1 frame 1 frame
TDRE
TEND
LSI TXI interrupt TDRE flag TXI interrupt request generated TEI interrupt request
operation request cleared generated
generated to 0
User Data written
processing to TDR
Figure 16.10 Example of SCI3 Transmission in Clock Synchronous Mode
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Start transmission [1] Read SSR and check that the TDRE flag is
set to 1, then write transmit data to TDR.
When data is written to TDR, the TDRE flag
[1] Read TDRE flag in SSR
is automatically cleared to 0 and clocks are
output to start the data transmission.
No [2] To continue serial transmission, be sure to
TDRE = 1 read 1 from the TDRE flag to confirm that
writing is possible, then write data to TDR.
Yes When data is written to TDR, the TDRE flag
is automatically cleared to 0.
Write transmit data to TDR
Yes
[2] All data transmitted?
No
No
TEND = 1
Yes
<End>
Figure 16.11 Sample Serial Transmission Flowchart (Clock Synchronous Mode)
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16.5.4 Serial Data Reception (Clock Synchronous Mode)
Figure 16.12 shows an example of SCI3 operation for reception in clock synchronous mode. In
serial reception, the SCI3 operates as described below.
1. The SCI3 performs internal initialization synchronous with a synchronization clock input or
output, starts receiving data.
2. The SCI3 stores the receive data in RSR.
3. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
in SSR is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this
time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the
RDRF flag remains to be set to 1.
4. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is
generated.
Serial
clock
Serial
Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
data
1 frame 1 frame
RDRF
OER
LSI RXI interrupt RDRF flag RXI interrupt request generated ERI interrupt request
operation request cleared generated by
generated to 0 overrun error
User RDR data read RDR data has Overrun error

processing not been read processing
(RDRF = 1)
Figure 16.12 Example of SCI3 Reception in Clock Synchronous Mode
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Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 16.13 shows a sample flow
chart for serial data reception.
Start reception
[1] Read the OER flag in SSR to determine if
there is an error. If an overrun error has
Read OER flag in SSR [1] occurred, execute overrun error processing.
[2] Read SSR and check that the RDRF flag is
set to 1, then read the receive data in RDR.
Yes
OER = 1 When data is read from RDR, the RDRF
[4] flag is automatically cleared to 0.
No [3] To continue serial reception, before the
Error processing
MSB (bit 7) of the current frame is received,
(Continued below) reading the RDRF flag and reading RDR
should be finished. When data is read from
Read RDRF flag in SSR [2] RDR, the RDRF flag is automatically
cleared to 0.
[4] If an overrun error occurs, read the OER
No
RDRF = 1 flag in SSR, and after performing the
appropriate error processing, clear the OER
flag to 0. Reception cannot be resumed if
Yes
the OER flag is set to 1.
Read receive data in RDR
Yes
No
<End>
[4] Error processing
Clear OER flag in SSR to 0
<End>
Figure 16.13 Sample Serial Reception Flowchart (Clock Synchronous Mode)
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16.5.5 Simultaneous Serial Data Transmission and Reception
Figure 16.14 shows a sample flowchart for simultaneous serial transmit and receive operations.
The following procedure should be used for simultaneous serial data transmit and receive
operations. To switch from transmit mode to simultaneous transmit and receive mode, after
checking that the SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear
TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive
mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished
reception, clear RE to 0. Then after checking that the RDRF and receive error flags (OER, FER,
and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction.
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Start transmission/reception [1] Read SSR and check that the TDRE
flag is set to 1, then write transmit
data to TDR.
Read TDRE flag in SSR [1] When data is written to TDR, the
TDRE flag is automatically cleared to
0.
No
TDRE = 1 [2] Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR.
Yes
When data is read from RDR, the
RDRF flag is automatically cleared to
Write transmit data to TDR 0.
[3] To continue serial transmission/
reception, before the MSB (bit 7) of
the current frame is received, finish
Read OER flag in SSR reading the RDRF flag, reading RDR.
Also, before the MSB (bit 7) of the
current frame is transmitted, read 1
Yes from the TDRE flag to confirm that
OER = 1
[4] writing is possible. Then write data to
TDR.
No Error processing
When data is written to TDR, the
TDRE flag is automatically cleared to
0. When data is read from RDR, the
Read RDRF flag in SSR [2]
RDRF flag is automatically cleared to
0.
No [4] If an overrun error occurs, read the
RDRF = 1 OER flag in SSR, and after
performing the appropriate error
Yes processing, clear the OER flag to 0.
Transmission/reception cannot be
resumed if the OER flag is set to 1.
Read receive data in RDR For overrun error processing, see
figure 16.13.
Yes
No
Clear TE and RE bits in SCR to 0
<End>
Figure 16.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
(Clock Synchronous Mode)
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16.6 Multiprocessor Communication Function

Use of the multiprocessor communication function enables data transfer between a number of
processors sharing communication lines by asynchronous serial communication using the
multiprocessor format, in which a multiprocessor bit is added to the transfer data. When
multiprocessor communication is performed, each receiving station is addressed by a unique ID
code. The serial communication cycle consists of two component cycles; an ID transmission cycle
that specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to
differentiate between the ID transmission cycle and the data transmission cycle. If the
multiprocessor bit is 1, the cycle is an ID transmission cycle; if the multiprocessor bit is 0, the
cycle is a data transmission cycle. Figure 16.15 shows an example of inter-processor
communication using the multiprocessor format. The transmitting station first sends the ID code
of the receiving station with which it wants to perform serial communication as data with a 1
multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added.
When data with a 1 multiprocessor bit is received, the receiving station compares that data with its
own ID. The station whose ID matches then receives the data sent next. Stations whose IDs do not
match continue to skip data until data with a 1 multiprocessor bit is again received.
The SCI3 uses the MPIE bit in SCR3 to implement this function. When the MPIE bit is set to 1,
transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags,
RDRF, FER, and OER, to 1, are inhibited until data with a 1 multiprocessor bit is received. On
reception of a receive character with a 1 multiprocessor bit, the MPBR bit in SSR is set to 1 and
the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR3 is
set to 1 at this time, an RXI interrupt is generated.
When the multiprocessor format is selected, the parity bit setting is rendered invalid. All other bit
settings are the same as those in normal asynchronous mode. The clock used for multiprocessor
communication is the same as that in normal asynchronous mode.
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Transmitting
station
Serial transmission line
Receiving Receiving Receiving Receiving

station A station B station C station D
(ID = 01) (ID = 02) (ID = 03) (ID = 04)
Serial
H'01 H'AA
data
(MPB = 1) (MPB = 0)
ID transmission cycle = Data transmission cycle =

receiving station Data transmission to
specification receiving station specified by ID
Legend
MPB: Multiprocessor bit
Figure 16.15 Example of Inter-Processor Communication Using Multiprocessor Format

(Transmission of Data H'AA to Receiving Station A)
16.6.1 Multiprocessor Serial Data Transmission
Figure 16.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI3 operations are the same
as those in asynchronous mode.
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Start transmission
[1] Read SSR and check that the TDRE
flag is set to 1, set the MPBT bit in
[1] Read TDRE flag in SSR SSR to 0 or 1, then write transmit
data to TDR. When data is written to
TDR, the TDRE flag is automatically
No
TDRE = 1 cleared to 0.
[2] To continue serial transmission, be
Yes sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR. When data is
Set MPBT bit in SSR
written to TDR, the TDRE flag is
automatically cleared to 0.
[3] To output a break in serial
Write transmit data to TDR transmission, set the port PCR to 1,
clear PDR to 0, then clear the TE bit
in SCR3 to 0.
Yes
[2] All data transmitted?
No
No
TEND = 1
Yes
No
[3] Break output?
Yes
Clear PDR to 0 and set PCR to 1
<End>
Figure 16.16 Sample Multiprocessor Serial Transmission Flowchart
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16.6.2 Multiprocessor Serial Data Reception
Figure 16.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data
with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is
generated at this time. All other SCI3 operations are the same as those in asynchronous mode.
Figure 16.18 shows an example of SCI3 operation for multiprocessor format reception.
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Start reception [1] Set the MPIE bit in SCR3 to 1.

[2] Read OER and FER in SSR to check for
errors. Receive error processing is performed
Set MPIE bit in SCR3 to 1 [1] in cases where a receive error occurs.
[3] Read SSR and check that the RDRF flag is
Read OER and FER flags in SSR [2]
set to 1, then read the receive data in RDR
and compare it with this station’s ID.
Yes
FER+OER = 1 If the data is not this station’s ID, set the MPIE
bit to 1 again.
When data is read from RDR, the RDRF flag
No
is automatically cleared to 0.
Read RDRF flag in SSR [3] [4] Read SSR and check that the RDRF flag is
set to 1, then read the data in RDR.
No [5] If a receive error occurs, read the OER and
RDRF = 1
FER flags in SSR to identify the error. After
performing the appropriate error processing,
Yes ensure that the OER and FER flags are all
Read receive data in RDR cleared to 0.
Reception cannot be resumed if either of
No these flags is set to 1.
This station’s ID? In the case of a framing error, a break can be
detected by reading the RxD pin value.
Yes
Read OER and FER flags in SSR
Yes
FER+OER = 1
No
Read RDRF flag in SSR [4]
No
RDRF = 1 [5]
Error processing
Yes
(Continued on
Read receive data in RDR next page)
Yes
All data received?
No
[A]
<End>
Figure 16.17 Sample Multiprocessor Serial Reception Flowchart (1)
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[5] Error processing
No
OER = 1
Yes
No
FER = 1
Yes
Yes
Break?
No [A]
Framing error processing
Clear OER, and

FER flags in SSR to 0
<End>
Figure 16.17 Sample Multiprocessor Serial Reception Flowchart (2)
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Start Receive Stop Start Receive data Stop Mark state

bit data (ID1) MPB bit bit (Data1) MPB bit (idle state)
Serial 1 0 D0 D1 D7 1 1 0 D0 D1 D7 0 1 1
data
1 frame 1 frame
MPIE
RDRF
RDR ID1
value
LSI RXI interrupt RDRF flag RXI interrupt request

operation request cleared is not generated, and
MPIE cleared to 0 RDR retains its state
to 0
User RDR data read When data is not
processing this station's ID,
MPIE is set to 1
again
(a) When data does not match this receiver's ID
Start Receive Stop Start Receive data Stop Mark state

bit data (ID2) MPB bit bit (Data2) MPB bit (idle state)
Serial 1 0 D0 D1 D7 1 1 0 D0 D1 D7 0 1 1
data
1 frame 1 frame
MPIE
RDRF
RDR ID1 ID2 Data2

value
LSI RXI interrupt RDRF flag RXI interrupt RDRF flag

operation request cleared request cleared
MPIE cleared to 0 to 0
to 0
User RDR data read When data is RDR data read
processing this station's MPIE set to 1
ID, reception again
is continued
(b) When data matches this receiver's ID
Figure 16.18 Example of SCI3 Reception Using Multiprocessor Format

(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
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16.7 Interrupts
SCI3 creates the following six interrupt requests: transmission end, transmit data empty, receive
data full, and receive errors (overrun error, framing error, and parity error). Table 16.7 shows the
interrupt sources.
Table 16.7 SCI3 Interrupt Requests
Interrupt Requests Abbreviation Interrupt Sources

Receive Data Full RXI Setting RDRF in SSR
Transmit Data Empty TXI Setting TDRE in SSR
Transmission End TEI Setting TEND in SSR
Receive Error ERI Setting OER, FER, and PER in SSR
The initial value of the TDRE flag in SSR is 1. Thus, when the TIE bit in SCR3 is set to 1 before
transferring the transmit data to TDR, a TXI interrupt request is generated even if the transmit data
is not ready. The initial value of the TEND flag in SSR is 1. Thus, when the TEIE bit in SCR3 is
set to 1 before transferring the transmit data to TDR, a TEI interrupt request is generated even if
the transmit data has not been sent. It is possible to make use of the most of these interrupt
requests efficiently by transferring the transmit data to TDR in the interrupt routine. To prevent the
generation of these interrupt requests (TXI and TEI), set the enable bits (TIE and TEIE) that
correspond to these interrupt requests to 1, after transferring the transmit data to TDR.
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16.8 Usage Notes
16.8.1 Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RxD pin value
directly. In a break, the input from the RxD pin becomes all 0s, setting the FER flag, and possibly
the PER flag. Note that as the SCI3 continues the receive operation after receiving a break, even if
the FER flag is cleared to 0, it will be set to 1 again.
16.8.2 Mark State and Break Sending
When the TXD or TXD2 bit in PMR1 is 1, the TxD pin is used as an I/O port whose direction
(input or output) and level are determined by PCR and PDR. This can be used to set the TxD pin
to mark state (high level) or send a break during serial data transmission. To maintain the
communication line at mark state until TE is set to 1, set both PCR and PDR to 1, and then set the
TXD bit to 1. At this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin.
To send a break during serial transmission, first set PCR to 1 and clear PDR to 0, and then set the
TXD bit to 1. At this point, the TxD pin becomes an I/O port regardless of the current
transmission state, and 0 is output from the TxD pin.
16.8.3 Receive Error Flags and Transmit Operations (Clock Synchronous Mode Only)
Transmission cannot be started when a receive error flag (OER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared
to 0.
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16.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the
transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock,
and performs internal synchronization. Receive data is latched internally at the rising edge of the
8th pulse of the basic clock as shown in figure 16.19. Thus, the reception margin in asynchronous
mode is given by formula (1) below.
 1 D – 0.5 
M = (0.5 – )– – (L – 0.5) F × 100(%)
 2N N 
... Formula (1)
[Legend]
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in
formula (1), the reception margin can be given by the formula.
M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed for in
system design.
16 clocks
8 clocks
0 7 15 0 7 15 0
Internal basic
clock
Receive data Start bit D0 D1

(RxD)
Synchronization
sampling timing
Data sampling
timing
Figure 16.19 Receive Data Sampling Timing in Asynchronous Mode
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2
Section 17 I C Bus Interface 2 (IIC2)
2 2
The I C bus interface 2 conforms to and provides a subset of the Philips I C bus (inter-IC bus)
2
interface functions. The register configuration that controls the I C bus differs partly from the
Philips configuration, however.
2
Figure 17.1 shows a block diagram of the I C bus interface 2.
Figure 17.2 shows an example of I/O pin connections to external circuits.
17.1 Features
• Selection of I C format or clock synchronous serial format
2
• Continuous transmission/reception
Since the shift register, transmit data register, and receive data register are independent from
each other, the continuous transmission/reception can be performed.
2
I C bus format
• Start and stop conditions generated automatically in master mode
• Selection of acknowledge output levels when receiving
• Automatic loading of acknowledge bit when transmitting
• Bit synchronization/wait function
In master mode, the state of SCL is monitored per bit, and the timing is synchronized
automatically.
If transmission/reception is not yet possible, set the SCL to low until preparations are
completed.
• Six interrupt sources
Transmit data empty (including slave-address match), transmit end, receive data full (including
slave-address match), arbitration lost, NACK detection, and stop condition detection
• Direct bus drive
Two pins, SCL and SDA pins, function as NMOS open-drain outputs when the bus drive
function is selected.
Clock synchronous format
• Four interrupt sources
Transmit-data-empty, transmit-end, receive-data-full, and overrun error
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Transfer clock
generation
circuit
Transmission/ ICCR1
reception
Output control circuit
SCL ICCR2
control
ICMR
Noise canceler
Internal data bus

ICDRT
SAR
Output ICDRS
SDA
control
Noise canceler Address

comparator
ICDRR
Bus state
decision circuit
Arbitration
decision circuit ICSR
ICIER
Interrupt
[Legend] Interrupt request
generator
2
ICCR1: I C bus control register 1
ICCR2: I2C bus control register 2
ICMR: I2C bus mode register
ICSR: I2C bus status register
ICIER: I2C bus interrupt enable register
ICDRT: I2C bus transmit data register
ICDRR: I2C bus receive data register
ICDRS: I2C bus shift register
SAR: Slave address register
2
Figure 17.1 Block Diagram of I C Bus Interface 2
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Vcc Vcc
SCL SCL
SCL in
SCL out
SDA SDA
SDA in
SDA out
SCL
SCL
SDA
SDA
(Master)
SCL in SCL in
SCL out SCL out
SDA in SDA in
SDA out SDA out
(Slave 1) (Slave 2)
Figure 17.2 External Circuit Connections of I/O Pins

2
Table 17.1 summarizes the input/output pins used by the I C bus interface 2.
2
Table 17.1 I C Bus Interface Pins

Serial clock SCL I/O IIC serial clock input/output
Serial data SDA I/O IIC serial data input/output
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2
The I C bus interface 2 has the following registers:
• I C bus control register 1 (ICCR1)

2
• I C bus control register 2 (ICCR2)

2
• I C bus mode register (ICMR)

2
• I C bus interrupt enable register (ICIER)

2
• I C bus status register (ICSR)

2
• I C bus slave address register (SAR)

2
• I C bus transmit data register (ICDRT)

2
• I C bus receive data register (ICDRR)

2
• I C bus shift register (ICDRS)

2
2
17.3.1 I C Bus Control Register 1 (ICCR1)
2
ICCR1 enables or disables the I C bus interface 2, controls transmission or reception, and selects
master or slave mode, transmission or reception, and transfer clock frequency in master mode.
Initial
2
7 ICE 0 R/W I C Bus Interface Enable
0: This module is halted. (SCL and SDA pins are set to
port function.)
1: This bit is enabled for transfer operations. (SCL and
SDA pins are bus drive state.)
6 RCVD 0 R/W Reception Disable
This bit enables or disables the next operation when TRS
is 0 and ICDRR is read.
0: Enables next reception
1: Disables next reception
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Initial
5 MST 0 R/W Master/Slave Select
4 TRS 0 R/W Transmit/Receive Select
2
In master mode with the I C bus format, when arbitration
is lost, MST and TRS are both reset by hardware,
causing a transition to slave receive mode. Modification
of the TRS bit should be made between transfer frames.
After data receive has been started in slave receive
mode, when the first seven bits of the receive data agree
with the slave address that is set to SAR and the eighth
bit is 1, TRS is automatically set to 1. If an overrun error
occurs in master mode with the clock synchronous serial
format, MST is cleared to 0 and slave receive mode is
entered.
Operating modes are described below according to MST
and TRS combination. When clock synchronous serial
format is selected and MST is 1, clock is output.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
3 CKS3 0 R/W Transfer Clock Select 3 to 0
2 CKS2 0 R/W These bits should be set according to the necessary
1 CKS1 0 R/W transfer rate (see table 17.2) in master mode. In slave
mode, these bits are used for reservation of the setup
0 CKS0 0 R/W time in transmit mode. The time is 10 tcyc when CKS3 = 0
and 20 tcyc when CKS3 = 1.
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Table 17.2 Transfer Rate
Bit 3 Bit 2 Bit 1 Bit 0 Transfer Rate

CKS3 CKS2 CKS1 CKS0 Clock φ = 5 MHz φ = 8 MHz φ = 10 MHz φ = 16 MHz φ = 20 MHz
0 0 0 0 φ/28 179 kHz 286 kHz 357 kHz 571 kHz 714 kHz
1 φ/40 125 kHz 200 kHz 250 kHz 400 kHz 500 kHz
1 0 φ/48 104 kHz 167 kHz 208 kHz 333 kHz 417 kHz
1 φ/64 78.1 kHz 125 kHz 156 kHz 250 kHz 313 kHz
1 0 0 φ/80 62.5 kHz 100 kHz 125 kHz 200 kHz 250 kHz
1 φ/100 50.0 kHz 80.0 kHz 100 kHz 160 kHz 200 kHz
1 0 φ/112 44.6 kHz 71.4 kHz 89.3 kHz 143 kHz 179 kHz
1 φ/128 39.1 kHz 62.5 kHz 78.1 kHz 125 kHz 156 kHz
1 0 0 0 φ/56 89.3 kHz 143 kHz 179 kHz 286 kHz 357 kHz
1 φ/80 62.5 kHz 100 kHz 125 kHz 200 kHz 250 kHz
1 0 φ/96 52.1 kHz 83.3 kHz 104 kHz 167 kHz 208 kHz
1 φ/128 39.1 kHz 62.5 kHz 78.1 kHz 125 kHz 156 kHz
1 0 0 φ/160 31.3 kHz 50.0 kHz 62.5 kHz 100 kHz 125 kHz
1 φ/200 25.0 kHz 40.0 kHz 50.0 kHz 80.0 kHz 100 kHz
1 0 φ/224 22.3 kHz 35.7 kHz 44.6 kHz 71.4 kHz 89.3 kHz
1 φ/256 19.5 kHz 31.3 kHz 39.1 kHz 62.5 kHz 78.1 kHz
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2
17.3.2 I C Bus Control Register 2 (ICCR2)
ICCR1 issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls
2
reset in the control part of the I C bus interface 2.
Initial
7 BBSY 0 R/W Bus Busy
2
This bit enables to confirm whether the I C bus is
occupied or released and to issue start/stop conditions in
master mode. With the clock synchronous serial format,
2
this bit has no meaning. With the I C bus format, this bit is
set to 1 when the SDA level changes from high to low
under the condition of SCL = high, assuming that the start
condition has been issued. This bit is cleared to 0 when
the SDA level changes from low to high under the
condition of SCL = high, assuming that the stop condition
has been issued. Write 1 to BBSY and 0 to SCP to issue
a start condition. Follow this procedure when also re-
transmitting a start condition. Write 0 in BBSY and 0 in
SCP to issue a stop condition. To issue start/stop
conditions, use the MOV instruction.
6 SCP 1 W Start/Stop Issue Condition Disable
The SCP bit controls the issue of start/stop conditions in
master mode.
To issue a start condition, write 1 in BBSY and 0 in SCP.
A retransmit start condition is issued in the same way. To
issue a stop condition, write 0 in BBSY and 0 in SCP.
This bit is always read as 1. If 1 is written, the data is not
stored.
5 SDAO 1 R/W SDA Output Value Control
This bit is used with SDAOP when modifying output level
of SDA. This bit should not be manipulated during
transfer.
0: When reading, SDA pin outputs low.
When writing, SDA pin is changed to output low.
1: When reading, SDA pin outputs high.
When writing, SDA pin is changed to output Hi-Z
(outputs high by external pull-up resistance).
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Initial
4 SDAOP 1 R/W SDAO Write Protect
This bit controls change of output level of the SDA pin by
modifying the SDAO bit. To change the output level, clear
SDAO and SDAOP to 0 or set SDAO to 1 and clear
SDAOP to 0 by the MOV instruction. This bit is always
read as 1.
3 SCLO 1 R This bit monitors SCL output level. When SCLO is 1, SCL
pin outputs high. When SCLO is 0, SCL pin outputs low.
1 IICRST 0 R/W IIC Control Part Reset
2
This bit resets the control part except for I C registers. If
this bit is set to 1 when hang-up occurs because of
2 2
communication failure during I C operation, I C control
part can be reset without setting ports and initializing
registers.
2
17.3.3 I C Bus Mode Register (ICMR)
ICMR selects whether the MSB or LSB is transferred first, performs master mode wait control,
and selects the transfer bit count.
Initial
7 MLS 0 R/W MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
2
Set this bit to 0 when the I C bus format is used.
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Initial
6 WAIT 0 R/W Wait Insertion Bit
2
In master mode with the I C bus format, this bit selects
whether to insert a wait after data transfer except the
acknowledge bit. When WAIT is set to 1, after the fall of
the clock for the final data bit, low period is extended for
two transfer clocks. If WAIT is cleared to 0, data and
acknowledge bits are transferred consecutively with no
wait inserted.
2
The setting of this bit is invalid in slave mode with the I C
bus format or with the clock synchronous serial format.
3 BCWP 1 R/W BC Write Protect
This bit controls the BC2 to BC0 modifications. When
modifying BC2 to BC0, this bit should be cleared to 0 and
use the MOV instruction. In clock synchronous serial
mode, BC should not be modified.
0: When writing, values of BC2 to BC0 are set.
1: When reading, 1 is always read.
When writing, settings of BC2 to BC0 are invalid.
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Initial
2 BC2 0 R/W Bit Counter 2 to 0
1 BC1 0 R/W These bits specify the number of bits to be transferred
0 BC0 0 R/W next. When read, the remaining number of transfer bits is
2
indicated. With the I C bus format, the data is transferred
with one addition acknowledge bit. Bit BC2 to BC0
settings should be made during an interval between
transfer frames. If bits BC2 to BC0 are set to a value
other than 000, the setting should be made while the SCL
pin is low. The value returns to 000 at the end of a data
transfer, including the acknowledge bit. With the clock
synchronous serial format, these bits should not be
modified.
2
I C Bus Format Clock Synchronous Serial Format
000: 9 bits 000: 8 bits
001: 2 bits 001: 1 bits
010: 3 bits 010: 2 bits
011: 4 bits 011: 3 bits
100: 5 bits 100: 4 bits
101: 6 bits 101: 5 bits
110: 7 bits 110: 6 bits
111: 8 bits 111: 7 bits
2
17.3.4 I C Bus Interrupt Enable Register (ICIER)
ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be
transferred, and confirms acknowledge bits to be received.
Initial
7 TIE 0 R/W Transmit Interrupt Enable
When the TDRE bit in ICSR is set to 1, this bit enables or
disables the transmit data empty interrupt (TXI).
0: Transmit data empty interrupt request (TXI) is disabled.
1: Transmit data empty interrupt request (TXI) is enabled.
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Initial
6 TEIE 0 R/W Transmit End Interrupt Enable
This bit enables or disables the transmit end interrupt
(TEI) at the rising of the ninth clock while the TDRE bit in
ICSR is 1. TEI can be canceled by clearing the TEND bit
or the TEIE bit to 0.
0: Transmit end interrupt request (TEI) is disabled.
1: Transmit end interrupt request (TEI) is enabled.
5 RIE 0 R/W Receive Interrupt Enable
This bit enables or disables the receive data full interrupt
request (RXI) and the overrun error interrupt request
(ERI) with the clock synchronous format, when a receive
data is transferred from ICDRS to ICDRR and the RDRF
bit in ICSR is set to 1. RXI can be canceled by clearing
the RDRF or RIE bit to 0.
0: Receive data full interrupt request (RXI) and overrun
error interrupt request (ERI) with the clock
synchronous format are disabled.
1: Receive data full interrupt request (RXI) and overrun
error interrupt request (ERI) with the clock
synchronous format are enabled.
4 NAKIE 0 R/W NACK Receive Interrupt Enable
This bit enables or disables the NACK receive interrupt
request (NAKI) and the overrun error (setting of the OVE
bit in ICSR) interrupt request (ERI) with the clock
synchronous format, when the NACKF and AL bits in
ICSR are set to 1. NAKI can be canceled by clearing the
NACKF, OVE, or NAKIE bit to 0.
0: NACK receive interrupt request (NAKI) is disabled.
1: NACK receive interrupt request (NAKI) is enabled.
3 STIE 0 R/W Stop Condition Detection Interrupt Enable
0: Stop condition detection interrupt request (STPI) is
disabled.
1: Stop condition detection interrupt request (STPI) is
enabled.
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Initial
2 ACKE 0 R/W Acknowledge Bit Judgment Select
0: The value of the receive acknowledge bit is ignored,
and continuous transfer is performed.
1: If the receive acknowledge bit is 1, continuous transfer
is halted.
1 ACKBR 0 R Receive Acknowledge
In transmit mode, this bit stores the acknowledge data
that are returned by the receive device. This bit cannot be
modified.
0: Receive acknowledge = 0
1: Receive acknowledge = 1
0 ACKBT 0 R/W Transmit Acknowledge
In receive mode, this bit specifies the bit to be sent at the
acknowledge timing.
0: 0 is sent at the acknowledge timing.
1: 1 is sent at the acknowledge timing.
2
17.3.5 I C Bus Status Register (ICSR)
ICSR performs confirmation of interrupt request flags and status.
Initial
7 TDRE 0 R/W Transmit Data Register Empty
• When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
• When TRS is set
• When a start condition (including re-transfer) has
been issued
• When transmit mode is entered from receive mode in
slave mode
• When 0 is written in TDRE after reading TDRE = 1
• When data is written to ICDRT with an instruction
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Initial
6 TEND 0 R/W Transmit End
•
2
When the ninth clock of SCL rises with the I C bus
format while the TDRE flag is 1
• When the final bit of transmit frame is sent with the
clock synchronous serial format
• When 0 is written in TEND after reading TEND = 1
• When data is written to ICDRT with an instruction
5 RDRF 0 R/W Receive Data Register Full
[Setting condition]
• When a receive data is transferred from ICDRS to
ICDRR
• When 0 is written in RDRF after reading RDRF = 1
• When ICDRR is read with an instruction
4 NACKF 0 R/W No Acknowledge Detection Flag
[Setting condition]
• When no acknowledge is detected from the receive
device in transmission while the ACKE bit in ICIER is
1
• When 0 is written in NACKF after reading NACKF = 1
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Initial
3 STOP 0 R/W Stop Condition Detection Flag
• In master mode, when a stop condition is detected
after frame transfer
• In slave mode, when a stop condition is detected after
the following events:
 A general call is invoked
 A start condition is detected
 The first byte in the slave address matches the
address set in the SAR
• When 0 is written in STOP after reading STOP = 1
2 AL/OVE 0 R/W Arbitration Lost Flag/Overrun Error Flag
This flag indicates that arbitration was lost in master
2
mode with the I C bus format and that the final bit has
been received while RDRF = 1 with the clock
synchronous format.
When two or more master devices attempt to seize the
2
bus at nearly the same time, if the I C bus interface
detects data differing from the data it sent, it sets AL to 1
to indicate that the bus has been taken by another
master.
• If the internal SDA and SDA pin disagree at the rise of
SCL in master transmit mode
• When the SDA pin outputs high in master mode while
a start condition is detected
• When the final bit is received with the clock
synchronous format while RDRF = 1
• When 0 is written in AL/OVE after reading AL/OVE=1
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Initial
1 AAS 0 R/W Slave Address Recognition Flag
In slave receive mode, this flag is set to 1 if the first frame
following a start condition matches bits SVA6 to SVA0 in
SAR.
• When the slave address is detected in slave receive
mode
• When the general call address is detected in slave
receive mode.
• When 0 is written in AAS after reading AAS=1
0 ADZ 0 R/W General Call Address Recognition Flag
2
This bit is valid in I C bus format slave receive mode.
[Setting condition]
• When the general call address is detected in slave
receive mode
• When 0 is written in ADZ after reading ADZ=1
17.3.6 Slave Address Register (SAR)
SAR selects the communication format and sets the slave address. When the chip is in slave mode
2
with the I C bus format, if the upper 7 bits of SAR match the upper 7 bits of the first frame
received after a start condition, the chip operates as the slave device.
Initial
7 to 1 SVA6 to All 0 R/W Slave Address 6 to 0
SVA0 These bits set a unique address in bits SVA6 to SVA0,
differing form the addresses of other slave devices
2
connected to the I C bus.
0 FS 0 R/W Format Select
2
0: I C bus format is selected.
1: Clock synchronous serial format is selected.
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2
17.3.7 I C Bus Transmit Data Register (ICDRT)
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the
space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to
ICDRS and starts transferring data. If the next transfer data is written to ICDRT during
transferring data of ICDRS, continuous transfer is possible. If the MLS bit of ICMR is set to 1
and when the data is written to ICDRT, the MSB/LSB inverted data is read. The initial value of
ICDRT is H’FF.
2
17.3.8 I C Bus Receive Data Register (ICDRR)
ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR
transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a
receive-only register, therefore the CPU cannot write to this register. The initial value of ICDRR
is H’FF.
2
17.3.9 I C Bus Shift Register (ICDRS)
ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from
ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from
ICDRS to ICDRR after data of one byte is received. This register cannot be read directly from the
CPU.
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17.4 Operation
2 2
The I C bus interface can communicate either in I C bus mode or clock synchronous serial mode
by setting FS in SAR.
2
17.4.1 I C Bus Format
2 2
Figure 17.3 shows the I C bus formats. Figure 17.4 shows the I C bus timing. The first frame
following a start condition always consists of 8 bits.
(a) I2C bus format (FS = 0)
S SLA R/W A DATA A A/A P

1 7 1 1 n 1 1 1
n: Transfer bit count
(n = 1 to 8)
1 m
m: Transfer frame count
(m ≥ 1)
(b) I2C bus format (Start condition retransmission, FS = 0)
S SLA R/W A DATA A/A S SLA R/W A DATA A/A P

1 7 1 1 n1 1 1 7 1 1 n2 1 1
1 m1 1 m2
n1 and n2: Transfer bit count (n1 and n2 = 1 to 8)

m1 and m2: Transfer frame count (m1 and m2 ≥ 1)
2
Figure 17.3 I C Bus Formats
SDA
SCL 1-7 8 9 1-7 8 9 1-7 8 9
S SLA R/W A DATA A DATA A P
2
Figure 17.4 I C Bus Timing
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[Legend]
S: Start condition. The master device drives SDA from high to low while SCL is high.
SLA: Slave address
R/W: Indicates the direction of data transfer: from the slave device to the master device when
R/W is 1, or from the master device to the slave device when R/W is 0.
A: Acknowledge. The receive device drives SDA to low.
DATA: Transfer data
P: Stop condition. The master device drives SDA from low to high while SCL is high.
17.4.2 Master Transmit Operation
In master transmit mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. For master transmit mode operation timing, refer to
figures 17.5 and 17.6. The transmission procedure and operations in master transmit mode are
described below.
1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
bits in ICCR1 to 1. (Initial setting)
2. Read the BBSY flag in ICCR2 to confirm that the bus is free. Set the MST and TRS bits in
ICCR1 to select master transmit mode. Then, write 1 to BBSY and 0 to SCP using MOV
instruction. (Start condition issued) This generates the start condition.
3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte data
show the slave address and R/W) to ICDRT. At this time, TDRE is automatically cleared to 0,
and data is transferred from ICDRT to ICDRS. TDRE is set again.
4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1
at the rise of the 9th transmit clock pulse. Read the ACKBR bit in ICIER, and confirm that the
slave device has been selected. Then, write second byte data to ICDRT. When ACKBR is 1,
the slave device has not been acknowledged, so issue the stop condition. To issue the stop
condition, write 0 to BBSY and SCP using MOV instruction. SCL is fixed low until the
transmit data is prepared or the stop condition is issued.
5. The transmit data after the second byte is written to ICDRT every time TDRE is set.
6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last
byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR = 1) from the
receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or
NACKF.
7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.
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SCL
(Master output) 1 2 3 4 5 6 7 8 9 1 2
SDA
(Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6
Slave address R/W

SDA
(Slave output) A
TDRE
TEND
ICDRT Address + R/W Data 1 Data 2
ICDRS Address + R/W Data 1
User [2] Instruction of start [4] Write data to ICDRT (second byte)
processing condition issuance
[3] Write data to ICDRT (first byte) [5] Write data to ICDRT (third byte)
Figure 17.5 Master Transmit Mode Operation Timing (1)
SCL
(Master output) 9 1 2 3 4 5 6 7 8 9
SDA
(Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SDA
A A/A
(Slave output)
TDRE
TEND
ICDRT Data n
ICDRS Data n
User [5] Write data to ICDRT [6] Issue stop condition. Clear TEND.
processing
[7] Set slave receive mode
Figure 17.6 Master Transmit Mode Operation Timing (2)
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17.4.3 Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data from the slave
device, and returns an acknowledge signal. For master receive mode operation timing, refer to
figures 17.7 and 17.8. The reception procedure and operations in master receive mode are shown
below.
1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master
transmit mode to master receive mode. Then, clear the TDRE bit to 0.
2. When ICDRR is read (dummy data read), reception is started, and the receive clock is output,
and data received, in synchronization with the internal clock. The master device outputs the
level specified by ACKBT in ICIER to SDA, at the 9th receive clock pulse.
3. After the reception of first frame data is completed, the RDRF bit in ICST is set to 1 at the rise
of 9th receive clock pulse. At this time, the receive data is read by reading ICDRR, and RDRF
is cleared to 0.
4. The continuous reception is performed by reading ICDRR every time RDRF is set. If 8th
receive clock pulse falls after reading ICDRR by the other processing while RDRF is 1, SCL is
fixed low until ICDRR is read.
5. If next frame is the last receive data, set the RCVD bit in ICCR1 to 1 before reading ICDRR.
This enables the issuance of the stop condition after the next reception.
6. When the RDRF bit is set to 1 at rise of the 9th receive clock pulse, issue the stage condition.
7. When the STOP bit in ICSR is set to 1, read ICDRR. Then clear the RCVD bit to 0.
8. The operation returns to the slave receive mode.
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Master transmit mode Master receive mode

SCL
(Master output) 9 1 2 3 4 5 6 7 8 9 1
SDA
(Master output) A
SDA
A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7
(Slave output)
TDRE
TEND
TRS
RDRF
ICDRS Data 1
ICDRR Data 1
User [3] Read ICDRR

processing [1] Clear TDRE after clearing [2] Read ICDRR (dummy read)
TEND and TRS
Figure 17.7 Master Receive Mode Operation Timing (1)
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SCL
(Master output) 9 1 2 3 4 5 6 7 8 9
SDA
(Master output) A A/A
SDA
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
(Slave output)
RDRF
RCVD
ICDRS Data n-1 Data n
ICDRR Data n-1 Data n
User
processing [5] Read ICDRR after setting RCVD [7] Read ICDRR, [6] Issue stop
and clear RCVD condition [8] Set slave
receive mode
Figure 17.8 Master Receive Mode Operation Timing (2)
17.4.4 Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal. For slave transmit mode operation timing,
refer to figures 17.9 and 17.10.
The transmission procedure and operations in slave transmit mode are described below.
bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive
mode, and wait until the slave address matches.
2. When the slave address matches in the first frame following detection of the start condition,
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS and ICSR bits in ICCR1 are
set to 1, and the mode changes to slave transmit mode automatically. The continuous
transmission is performed by writing transmit data to ICDRT every time TDRE is set.
3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1,
with TDRE = 1. When TEND is set, clear TEND.
4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is free.
5. Clear TDRE.
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Slave receive mode Slave transmit mode

SCL
(Master output) 9 1 2 3 4 5 6 7 8 9 1
SDA
A
(Master output)
SCL
(Slave output)
SDA
A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7
(Slave output)
TDRE
TEND
TRS
ICDRT Data 1 Data 2 Data 3
ICDRS Data 1 Data 2
ICDRR
User
[2] Write data to ICDRT (data 1) [2] Write data to ICDRT (data 2) [2] Write data to ICDRT (data 3)
processing
Figure 17.9 Slave Transmit Mode Operation Timing (1)
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Slave receive
mode
Slave transmit mode
SCL
(Master output) 9 1 2 3 4 5 6 7 8 9
SDA
(Master output)
A A
SCL
(Slave output)
SDA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(Slave output)
TDRE
TEND
TRS
ICDRT
ICDRS Data n
ICDRR
User
processing [3] Clear TEND [4] Read ICDRR (dummy read) [5] Clear TDRE
after clearing TRS
Figure 17.10 Slave Transmit Mode Operation Timing (2)
17.4.5 Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. For slave receive mode operation timing, refer to
figures 17.11 and 17.12. The reception procedure and operations in slave receive mode are
described below.
bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive
mode, and wait until the slave address matches.
2. When the slave address matches in the first frame following detection of the start condition,
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the
read data show the slave address and R/W, it is not used.)
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3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is
fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be
returned to the master device, is reflected to the next transmit frame.
4. The last byte data is read by reading ICDRR.
SCL
(Master output) 9 1 2 3 4 5 6 7 8 9 1
SDA
(Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7
SCL
(Slave output)
SDA
A A
(Slave output)
RDRF
ICDRS Data 1 Data 2
ICDRR Data 1
User
processing
[2] Read ICDRR (dummy read) [2] Read ICDRR
Figure 17.11 Slave Receive Mode Operation Timing (1)
SCL
(Master output) 9 1 2 3 4 5 6 7 8 9
SDA
(Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SCL
(Slave output)
SDA
A A
(Slave output)
RDRF
ICDRS Data 1 Data 2
ICDRR Data 1
User
processing [3] Set ACKBT [3] Read ICDRR [4] Read ICDRR
Figure 17.12 Slave Receive Mode Operation Timing (2)
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17.4.6 Clock Synchronous Serial Format
This module can be operated with the clock synchronous serial format, by setting the FS bit in
SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When
MST is 0, the external clock input is selected.
Data Transfer Format
Figure 17.13 shows the clock synchronous serial transfer format.
The transfer data is output from the rise to the fall of the SCL clock, and the data at the rising edge
of the SCL clock is guaranteed. The MLS bit in ICMR sets the order of data transfer, in either the
MSB first or LSB first. The output level of SDA can be changed during the transfer wait, by the
SDAO bit in ICCR2.
SCL
SDA Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Figure 17.13 Clock Synchronous Serial Transfer Format
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Transmit Operation
In transmit mode, transmit data is output from SDA, in synchronization with the fall of the transfer
clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For
transmit mode operation timing, refer to figure 17.14. The transmission procedure and operations
in transmit mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial
setting)
2. Set the TRS bit in ICCR1 to select the transmit mode. Then, TDRE in ICSR is set.
3. Confirm that TDRE has been set. Then, write the transmit data to ICDRT. The data is
transferred from ICDRT to ICDRS, and TDRE is set automatically. The continuous
transmission is performed by writing data to ICDRT every time TDRE is set. When changing
from transmit mode to receive mode, clear TRS while TDRE is 1.
SCL 1 2 7 8 1 7 8 1
SDA Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0

Bit 0 Bit 1
(Output)
TRS
TDRE
ICDRT Data 1 Data 2 Data 3
ICDRS Data 1 Data 2 Data 3
User
processing [3] Write data [3] Write data [3] Write data [3] Write data
to ICDRT to ICDRT to ICDRT to ICDRT
[2] Set TRS
Figure 17.14 Transmit Mode Operation Timing
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Receive Operation
In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when
MST in ICCR1 is 1, and is input when MST is 0. For receive mode operation timing, refer to
figure 17.15. The reception procedure and operations in receive mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial
setting)
2. When the transfer clock is output, set MST to 1 to start outputting the receive clock.
3. When the receive operation is completed, data is transferred from ICDRS to ICDRR and
RDRF in ICSR is set. When MST = 1, the next byte can be received, so the clock is
continually output. The continuous reception is performed by reading ICDRR every time
RDRF is set. When the 8th clock is risen while RDRF is 1, the overrun is detected and
AL/OVE in ICSR is set. At this time, the previous reception data is retained in ICDRR.
4. To stop receiving when MST = 1, set RCVD in ICCR1 to 1, then read ICDRR. Then, SCL is
fixed high after receiving the next byte data.
SCL 1 2 7 8 1 7 8 1 2
SDA
Bit 0 Bit 1 Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0 Bit 1
(Input)
MST
TRS
RDRF
ICDRS Data 1 Data 2 Data 3
ICDRR Data 1 Data 2
User
processing [2] Set MST [3] Read ICDRR [3] Read ICDRR
(when outputting the clock)
Figure 17.15 Receive Mode Operation Timing
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17.4.7 Noise Filter
The signal levels on the SCL and SDA pins are internally latched via the noise filter. Figure 17.16
shows a block diagram of the noise filter circuit.
The noise filter consists of two cascaded latches and a match detector. The SCL (or SDA) input
signal is sampled on the system clock. When both outputs of the latches match, its level is output
to other blocks by the match detector. If they do not match, the previous value is held.
Sampling clock
C C
SCL or SDA Internal
D Q D Q
input signal Match detector SCL or SDA
Latch Latch signal
System clock
cycle
Sampling
clock
Figure 17.16 Block Diagram of Noise Filter
17.4.8 Example of Use

2
Flowcharts in respective modes that use the I C bus interface are shown in figures 17.17 to 17.20.
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Start
Initialize [1] Test the status of the SCL and SDA lines.
Read BBSY in ICCR2

[2] Set master transmit mode.
No [1]
BBSY=0 ?
[3] Issue the start candition.
Yes
Set MST and TRS [4] Set the first byte (slave address + R/W) of transmit data.
[2]
in ICCR1 to 1.
Write 1 to BBSY [3] [5] Wait for 1 byte to be transmitted.

and 0 to SCP.
Write transmit data [4] [6] Test the acknowledge transferred from the specified slave device.
in ICDRT
[7] Set the second and subsequent bytes (except for the final byte) of transmit data.
Read TEND in ICSR
No [5] [8] Wait for ICDRT empty.

TEND=1 ?
Yes [9] Set the last byte of transmit data.

Read ACKBR in ICIER
[6] [10] Wait for last byte to be transmitted.
No
ACKBR=0 ?
[11] Clear the TEND flag.
Yes
Transmit No
Mater receive mode
mode?
Yes
[7] [12] Clear the STOP flag.
Write transmit data in ICDRT
[13] Issue the stop condition.

Read TDRE in ICSR
No [8]
TDRE=1 ? [14] Wait for the creation of stop condition.
Yes
[15] Set slave receive mode. Clear TDRE.
No
Last byte?
[9]
Yes
Write transmit data in ICDRT
Read TEND in ICSR
No [10]
TEND=1 ?
Yes
Clear TEND in ICSR [11]
Clear STOP in ICSR [12]
Write 0 to BBSY
[13]
and SCP
Read STOP in ICSR
[14]
No
STOP=1 ?
Yes
Set MST to 1 and TRS
to 0 in ICCR1
[15]
Clear TDRE in ICSR
End
Figure 17.17 Sample Flowchart for Master Transmit Mode
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Mater receive mode

[1] Clear TEND, select master receive mode, and then clear TDRE.*
Clear TEND in ICSR
[2] Set acknowledge to the transmit device.*
Clear TRS in ICCR1 to 0 [1]
Clear TDRE in ICSR [3] Dummy-read ICDDR.*
Clear ACKBT in ICIER to 0 [2] [4] Wait for 1 byte to be received
[5] Check whether it is the (last receive - 1).

Dummy-read ICDRR [3]
[6] Read the receive data last.

Read RDRF in ICSR
No [7] Set acknowledge of the final byte. Disable continuous reception (RCVD = 1).
[4]
RDRF=1 ?
[8] Read the (final byte - 1) of receive data.
Yes
Last receive Yes [9] Wait for the last byte to be receive.
[5]
- 1?
No [10] Clear the STOP flag.
Read ICDRR [6]
[11] Issue the stop condition.
[12] Wait for the creation of stop condition.

Set ACKBT in ICIER to 1
[13] Read the last byte of receive data.
[7]
Set RCVD in ICCR1 to 1 [14] Clear RCVD.
Read ICDRR [8] [15] Set slave receive mode.
Read RDRF in ICSR
No [9]
RDRF=1 ?
Yes
Clear STOP in ICSR. [10]
Write 0 to BBSY
[11]
and SCP
Read STOP in ICSR
No [12]
STOP=1 ?
Yes
Read ICDRR [13]
Clear RCVD in ICCR1 to 0 [14]
Clear MST in ICCR1 to 0 [15]
End Note: Do not activate an interrupt during the execution of steps [1] to [3].
Supplementary explanation: When one byte is received, steps [2] to [6] are
skipped after step [1], before jumping to step [7].
The step [8] is dummy-read in ICDRR.
Figure 17.18 Sample Flowchart for Master Receive Mode
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Slave transmit mode [1] Clear the AAS flag.
Clear AAS in ICSR [1] [2] Set transmit data for ICDRT (except for the last data).
[3] Wait for ICDRT empty.

Write transmit data
[2]
in ICDRT
[4] Set the last byte of transmit data.
Read TDRE in ICSR [5] Wait for the last byte to be transmitted.
[3]
No [6] Clear the TEND flag .
TDRE=1 ?
Yes [7] Set slave receive mode.

No Last
byte? [8] Dummy-read ICDRR to release the SCL line.
Yes [4]
[9] Clear the TDRE flag.
Write transmit data
in ICDRT
Read TEND in ICSR

[5]
No
TEND=1 ?
Yes
Clear TEND in ICSR [6]
Clear TRS in ICCR1 to 0 [7]
Dummy read ICDRR [8]
Clear TDRE in ICSR [9]
End
Figure 17.19 Sample Flowchart for Slave Transmit Mode
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Slave receive mode

[1] Clear the AAS flag.
Clear AAS in ICSR [1]
[2] Set acknowledge to the transmit device.
Clear ACKBT in ICIER to 0 [2]
[3] Dummy-read ICDRR.
Dummy-read ICDRR [3]

[4] Wait for 1 byte to be received.
Read RDRF in ICSR [5] Check whether it is the (last receive - 1).
No [4] [6] Read the receive data.
RDRF=1 ?
[7] Set acknowledge of the last byte.
Yes
Last receive Yes [8] Read the (last byte - 1) of receive data.
[5]
- 1?
No [9] Wait the last byte to be received.
Read ICDRR [6]
[10] Read for the last byte of receive data.
Set ACKBT in ICIER to 1 [7]
Read ICDRR [8]
Read RDRF in ICSR
No [9]
RDRF=1 ?
Yes
Read ICDRR [10]
End
Supplementary explanation: When one byte is received, steps [2] to [6] are skipped after step [1],
before jumping to step [7]. The step [8] is dummy-read in ICDRR.
Figure 17.20 Sample Flowchart for Slave Receive Mode
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17.5 Interrupt Request

There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK receive, STOP recognition, and arbitration lost/overrun error. Table 17.3 shows the
contents of each interrupt request.
Table 17.3 Interrupt Requests
Clock Synchronous
2
Interrupt Request Abbreviation Interrupt Condition I C Mode Mode
Transmit Data Empty TXI (TDRE=1) • (TIE=1) { {
Transmit End TEI (TEND=1) • (TEIE=1) { {
Receive Data Full RXI (RDRF=1) • (RIE=1) { {
STOP Recognition STPI (STOP=1) • (STIE=1) { ×

NACK Receive NAKI {(NACKF=1)+(AL=1)} • { ×
(NAKIE=1)
Arbitration { {
Lost/Overrun Error
When interrupt conditions described in table 17.3 are 1 and the I bit in CCR is 0, the CPU
executes an interrupt exception processing. Interrupt sources should be cleared in the exception
processing. TDRE and TEND are automatically cleared to 0 by writing the transmit data to
ICDRT. RDRF are automatically cleared to 0 by reading ICDRR. TDRE is set to 1 again at the
same time when transmit data is written to ICDRT. When TDRE is cleared to 0, then an excessive
data of one byte may be transmitted.
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17.6 Bit Synchronous Circuit

In master mode, this module has a possibility that high level period may be short in the two states
described below.
• When SCL is driven to low by the slave device

• When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pull-
up resistance)
Therefore, it monitors SCL and communicates by bit with synchronization.
Figure 17.21 shows the timing of the bit synchronous circuit and table 17.4 shows the time when
SCL output changes from low to Hi-Z then SCL is monitored.
SCL monitor
timing reference
clock
SCL VIH
Internal SCL
Figure 17.21 The Timing of the Bit Synchronous Circuit
Table 17.4 Time for Monitoring SCL
CKS3 CKS2 Time for Monitoring SCL

0 0 7.5 tcyc
1 19.5 tcyc
1 0 17.5 tcyc
1 41.5 tcyc
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17.7 Usage Notes
17.7.1 Issue (Retransmission) of Start/Stop Conditions
In master mode, when the start/stop conditions are issued (retransmitted) at the specific timing
under the following condition 1 or 2, such conditions may not be output successfully. To avoid
this, issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed. Check
2
the SCLO bit in the I C control register 2 (IICR2) to confirm the fall of the ninth clock.
1. When the rising of SCL falls behind the time specified in section 17.6, Bit Synchronous
Circuit, by the load of the SCL bus (load capacitance or pull-up resistance)
2. When the bit synchronous circuit is activated by extending the low period of eighth and ninth
clocks, that is driven by the slave device
2
17.7.2 WAIT Setting in I C Bus Mode Register (ICMR)
If the WAIT bit is set to 1, and the SCL signal is driven low for two or more transfer clocks by the
slave device at the eighth and ninth clocks, the high period of ninth clock may be shortened. To
avoid this, set the WAIT bit in ICMR to 0.
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17.7.3 Restriction in Use of Multi-Master
(1) Restriction on Setting Transfer Rate

2
In multi-master usage when I C transfer rate setting of this LSI is lower than those of the other
masters, unexpected length of SCL may occasionally be output. To avoid this, the specified value
must be greater than or equal to the value produced by multiplying the fastest transfer rate among
the other masters by 1/1.8. For example, when the transfer rate of the fastest bus master among the
2
other bus masters is 400 kbps, the transfer rate of the I C of this LSI must be set to at least
223 kbps (= 400/1.8).
(2) Restriction on Use of Bit Manipulation Instructions to Set MST and TRS
When master transmission is selected by consecutively manipulating the MST and TRS bits in
multi-master usage, an arbitration loss during execution of the bit-manipulation instruction for
TRS leads to the contradictory situation where AL in ICSR is 1 in master transmit mode (MST =
1, TRS = 1).
Ways to avoid this effect are listed below.
• Use the MOV instruction to set MST and TRS in multi-master usage.
• When arbitration is lost, confirm that MST = 0 and TRS = 0. If the setting of MST = 0 and
TRS = 0 is not confirmed, set MST = 0 and TRS = 0 again.
17.7.4 Continuous Data Reception in Master Receive Mode
In master receive mode, when SCL is fixed low on the falling edge of the 8th clock while the
RDRF bit is set to 1 and ICDRR is read around the falling edge of the 8th clock, the clock is only
fixed low in the 8th clock of the next round of data reception. The SCL is then released from its
fixed state without reading ICDRR and the 9th clock is output. As a result, some receive data is
lost.
Ways to avoid this phenomenon are listed below.
• Read ICDRR in master receive mode before the rising edge of the 8th clock.
• Set RCVD to 1 in master receive mode and perform communication in units of one byte.
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This LSI includes a successive approximation type 10-bit A/D converter that allows up to eight
analog input channels to be selected. The block diagram of the A/D converter is shown in figure
18.1.
18.1 Features
• 10-bit resolution
• Eight input channels
• Conversion time: at least 3.5 µs per channel (at 20-MHz operation)
• Two operating modes
 Single mode: Single-channel A/D conversion
 Scan mode: Continuous A/D conversion on 1 to 4 channels
• Four data registers
 Conversion results are held in a data register for each channel
• Sample-and-hold function
• Two conversion start methods
 Software
 External trigger signal
• Interrupt request
 An A/D conversion end interrupt request (ADI) can be generated
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Module data bus Internal data bus
Bus interface
Successive approximations
AVCC
A A A A A A
register
D D D D D D
10-bit D/A D D D D C C
R R R R S R
A B C D R
AN0
AN1 +
Analog multiplexer
AN2 Control circuit

AN3 Comparator
AN4
AN5 Sample-and- ADI
AN6 hold circuit interrupt
AN7
ADTRG
[Legend]
ADCR: A/D control register
ADCSR: A/D control/status register
ADDRA: A/D data register A
ADDRB: A/D data register B
ADDRC: A/D data register C
ADDRD: A/D data register D
Figure 18.1 Block Diagram of A/D Converter
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Table 18.1 summarizes the input pins used by the A/D converter. The 8 analog input pins are
divided into two groups; analog input pins 0 to 3 (AN0 to AN3) comprising group 0, analog input
pins 4 to 7 (AN4 to AN7) comprising group 1. The AVcc pin is the power supply pin for the
analog block in the A/D converter.
Pin Name Abbreviation I/O Function

Analog power supply pin AVCC Input Analog block power supply
Analog input pin 0 AN0 Input Group 0 analog input
Analog input pin 1 AN1 Input
Analog input pin 4 AN4 Input Group 1 analog input
A/D external trigger input pin ADTRG Input External trigger input for starting
A/D conversion
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The A/D converter has the following registers.
• A/D data register A (ADDRA)

• A/D data register B (ADDRB)
• A/D data register C (ADDRC)
• A/D data register D (ADDRD)
• A/D control/status register (ADCSR)
• A/D control register (ADCR)
18.3.1 A/D Data Registers A to D (ADDRA to ADDRD)
There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of
A/D conversion. The ADDR registers, which store a conversion result for each analog input
channel, are shown in table 18.2.
The converted 10-bit data is stored in bits 15 to 6. The lower 6 bits are always read as 0.
The data bus width between the CPU and the A/D converter is 8 bits. The upper byte can be read
directly from the CPU, however the lower byte should be read via a temporary register. The
temporary register contents are transferred from the ADDR when the upper byte data is read.
When reading ADDR, read the upper byte first then the lower one, or read in word units. The
ADDR is initialized to H'0000.
Table 18.2 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel

Group 0 Group 1 A/D Data Register to Be Stored Results of A/D Conversion
AN0 AN4 ADDRA
AN1 AN5 ADDRB
AN2 AN6 ADDRC
AN3 AN7 ADDRD
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18.3.2 A/D Control/Status Register (ADCSR)
ADCSR consists of the control bits and conversion end status bits of the A/D converter.
Initial
7 ADF 0 R/W A/D End Flag
• When A/D conversion ends in single mode
• When A/D conversion ends once on all the channels
selected in scan mode
• When 0 is written after reading ADF = 1
6 ADIE 0 R/W A/D Interrupt Enable
A/D conversion end interrupt request (ADI) is enabled by
ADF when this bit is set to 1
5 ADST 0 R/W A/D Start
Setting this bit to 1 starts A/D conversion. In single mode,
this bit is cleared to 0 automatically when conversion on
the specified channel is complete. In scan mode,
conversion continues sequentially on the specified
channels until this bit is cleared to 0 by software, a reset, or
a transition to standby mode.
4 SCAN 0 R/W Scan Mode
Selects single mode or scan mode as the A/D conversion
operating mode.
0: Single mode
1: Scan mode
3 CKS 0 R/W Clock Select
Selects the A/D conversions time.
0: Conversion time = 134 states (max.)
1: Conversion time = 70 states (max.)
Clear the ADST bit to 0 before switching the conversion
time.
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Initial
2 CH2 0 R/W Channel Select 2 to 0
1 CH1 0 R/W Select analog input channels.
0 CH0 0 R/W When SCAN = 0 When SCAN = 1
000: AN0 000: AN0
001: AN1 001: AN0 and AN1
010: AN2 010: AN0 to AN2
011: AN3 011: AN0 to AN3
100: AN4 100: AN4
101: AN5 101: AN4 and AN5
110: AN6 110: AN4 to AN6
111: AN7 111: AN4 to AN7
18.3.3 A/D Control Register (ADCR)
ADCR enables A/D conversion started by an external trigger signal.
Initial
7 TRGE 0 R/W Trigger Enable
A/D conversion is started at the falling edge and the rising
edge of the external trigger signal (ADTRG) when this bit is
set to 1.
The selection between the falling edge and rising edge of
the external trigger pin (ADTRG) conforms to the WPEG5
bit in the interrupt edge select register 2 (IEGR2)
0 — 0 R/W Reserved
Do not set this bit to 1, though the bit is readable/writable.
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18.4 Operation
The A/D converter operates by successive approximation with 10-bit resolution. It has two
operating modes; single mode and scan mode. When changing the operating mode or analog input
channel, in order to prevent incorrect operation, first clear the bit ADST in ADCSR to 0. The
ADST bit can be set at the same time as the operating mode or analog input channel is changed.
18.4.1 Single Mode
In single mode, A/D conversion is performed once for the analog input of the specified single
channel as follows:
1. A/D conversion is started when the ADST bit in ADCSR is set to 1, according to software or
external trigger input.
2. When A/D conversion is completed, the result is transferred to the corresponding A/D data
register of the channel.
3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at
this time, an ADI interrupt request is generated.
4. The ADST bit remains set to 1 during A/D conversion. When A/D conversion ends, the ADST
bit is automatically cleared to 0 and the A/D converter enters the wait state.
18.4.2 Scan Mode
In scan mode, A/D conversion is performed sequentially for the analog input of the specified
channels (four channels maximum) as follows:
1. When the ADST bit in ADCSR is set to 1 by software or external trigger input, A/D
conversion starts on the first channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1).
2. When A/D conversion for each channel is completed, the result is sequentially transferred to
the A/D data register corresponding to each channel.
3. When conversion of all the selected channels is completed, the ADF flag in ADCSR is set to 1.
If the ADIE bit is set to 1 at this time, an ADI interrupt requested is generated. A/D conversion
starts again on the first channel in the group.
4. The ADST bit is not automatically cleared to 0. Steps [2] and [3] are repeated as long as the
ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops.
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18.4.3 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (tD) has passed after the ADST bit is set to 1, then
starts conversion. Figure 18.2 shows the A/D conversion timing. Table 18.3 shows the A/D
conversion time.
As indicated in figure 18.2, the A/D conversion time includes tD and the input sampling time. The
length of tD varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 18.3.
In scan mode, the values given in table 18.3 apply to the first conversion time. In the second and
subsequent conversions, the conversion time is 128 states (fixed) when CKS = 0 and 66 states
(fixed) when CKS = 1.
(1)
Address (2)
Write signal
Input sampling
timing
ADF
tD tSPL
tCONV
[Legend]
(1): ADCSR write cycle
(2): ADCSR address
tD: A/D conversion start delay time
tSPL: Input sampling time
tCONV: A/D conversion time
Figure 18.2 A/D Conversion Timing
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Table 18.3 A/D Conversion Time (Single Mode)
CKS = 0 CKS = 1
Item Symbol Min. Typ. Max. Min. Typ. Max.
A/D conversion start delay time tD 6 — 9 4 — 5
Input sampling time tSPL — 31 — — 15 —
A/D conversion time tCONV 131 — 134 69 — 70
Note: All values represent the number of states.
18.4.4 External Trigger Input Timing
A/D conversion can also be started by an external trigger input. When the TRGE bit in ADCR is
set to 1, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG input
pin sets the ADST bit in ADCSR to 1, starting A/D conversion. Other operations, in both single
and scan modes, are the same as when the bit ADST has been set to 1 by software. Figure 18.3
shows the timing.
ADTRG
Internal trigger signal
ADST
A/D conversion
Figure 18.3 External Trigger Input Timing
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18.5 A/D Conversion Accuracy Definitions

This LSI's A/D conversion accuracy definitions are given below.
• Resolution
The number of A/D converter digital output codes
• Quantization error
The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 18.4).
• Offset error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from the minimum voltage value 0000000000 to 0000000001
(see figure 18.5).
• Full-scale error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from 1111111110 to 1111111111 (see figure 18.5).
• Nonlinearity error
The deviation from the ideal A/D conversion characteristic as the voltage changes from zero to
full scale. This does not include the offset error, full-scale error, or quantization error.
• Absolute accuracy
The deviation between the digital value and the analog input value. Includes offset error, full-
scale error, quantization error, and nonlinearity error.
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Digital output
Ideal A/D conversion

111 characteristic
110
101
100
011
010 Quantization error
001
000
1 2 3 4 5 6 7 FS
8 8 8 8 8 8 8
Analog
input voltage
Figure 18.4 A/D Conversion Accuracy Definitions (1)
Digital output Full-scale error
Ideal A/D conversion

characteristic
Nonlinearity
error
Actual A/D conversion

characteristic
FS
Analog
Offset error input voltage
Figure 18.5 A/D Conversion Accuracy Definitions (2)
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18.6 Usage Notes
18.6.1 Permissible Signal Source Impedance
This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal
for which the signal source impedance is 5 kΩ or less. This specification is provided to enable the
A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time;
if the sensor output impedance exceeds 5 kΩ, charging may be insufficient and it may not be
possible to guarantee A/D conversion accuracy. However, for A/D conversion in single mode with
a large capacitance provided externally, the input load will essentially comprise only the internal
input resistance of 10 kΩ, and the signal source impedance is ignored. However, as a low-pass
filter effect is obtained in this case, it may not be possible to follow an analog signal with a large
differential coefficient (e.g., 5 mV/µs or greater) (see figure 18.6). When converting a high-speed
analog signal or converting in scan mode, a low-impedance buffer should be inserted.
18.6.2 Influences on Absolute Accuracy
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely
affect absolute accuracy. Be sure to make the connection to an electrically stable GND.
Care is also required to ensure that filter circuits do not interfere with digital signals or act as
antennas on the mounting board.
This LSI A/D converter

Sensor output equivalent circuit
impedance
up to 5 kΩ 10 kΩ
Sensor input
Low-pass Cin = 20 pF
filter 15 pF
C to 0.1 µF
Figure 18.6 Analog Input Circuit Example
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Section 19 Band-Gap Circuit, Power-On Reset, and

Low-Voltage Detection Circuits
This LSI can include a band-gap circuit (BGR, band-gap regulator), a power-on reset circuit and
low-voltage detection circuit.
BGR supplies a reference voltage to the on-chip oscillator and low-voltage detection circuit.
Figure 19.1 shows the block diagram of how BGR is allocated.
The low-voltage detection (LVD) circuit consists of two circuits: LVDI (interrupt by low voltage
detection) and LVDR (reset by low voltage detection) circuits.
This circuit is used to prevent abnormal operation (program runaway) from occurring due to the
power supply voltage fall and to recreate the state before the power supply voltage fall when the
power supply voltage rises again.
Even if the power supply voltage falls, the unstable state when the power supply voltage falls
below the guaranteed operating voltage can be removed by entering standby mode when
exceeding the guaranteed operating voltage and during normal operation. Thus, system stability
can be improved. If the power supply voltage falls more, the reset state is automatically entered. If
the power supply voltage rises again, the reset state is held for a specified period, then active mode
is automatically entered.
Figure 19.2 is a block diagram of the power-on reset circuit and the low-voltage detection circuit.
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19.1 Features
• BGR circuit
Supplies stable reference voltage covering the entire operating voltage range and the operating
temperature range.
• Power-on reset circuit
Uses an external capacitor to generate an internal reset signal when power is first supplied.
• Low-voltage detection circuit
LVDR: Monitors the power-supply voltage, and generates an internal reset signal when the
voltage falls below a given value.
LVDI: Monitors the power-supply voltage, and generates an interrupt when the voltage falls
below or rises above respective given values.
Two detection levels for reset generation voltage are available: when only the LVDR circuit is
used, or when the LVDI and LVDR circuits are both used.
• Reset source decision
The source of a reset can be decided by reading the reset source decision register in the reset
exception handler.
VCLSEL
Vcc VCL
Step-down circuit
On-chip
oscillator
VBGR RCSTP
BGR
LVD (low-voltage
detection circuit)
[Legend]
Vcc: Power supply
VCL: Internal power supply generated from Vcc by the step-down circuit
VBGR: Reference voltage from BGR
VCLSEL: Select signal for the source of the on-chip oscillator power supply
RCSTP: On-chip oscillator stop signal
Figure 19.1 Block Diagram around BGR
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φ CK OVF
PSS
R
150 kΩ
R
RES Internal
Noise filter Q reset signal
circuit S
CRES Power-on reset circuit
Noise filter
circuit
External
power
supply LVDCR
Vreset LVDRES
Ladder
Internal data bus

Vcc VintU
network VintD
ExtD
LVDINT Interrupt LVDSR
control
circuit
ExtU
Interrupt request
VDDII
VBGR
[Legend]
PSS: Prescaler S
LVDCR: Low-voltage-detection control register
LVDSR: Low-voltage-detection status register
VBGR: Reference voltage from BGR
ExtD: Compared voltage for falling external input voltage
ExtU: Compared voltage for rising external input voltage
VDDII: Bit 5 in LVDCR
Figure 19.2 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit
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The low-voltage detection circuit has the following registers.
• Low-voltage-detection control register (LVDCR)

• Low-voltage-detection status register (LVDSR)
• Reset source decision register (LVDRF)
19.2.1 Low-Voltage-Detection Control Register (LVDCR)
LVDCR selects the compared voltage of the LVDI circuit, sets the detection levels for the LVDR
circuit, enables or disables the LVDR circuit, and enables or disables generation of an interrupt
when the power-supply voltage rises above or falls below the respective levels.
Table 19.1 shows the relationship between the LVDCR settings and functions to be selected.
LVDCR should be set according to table 19.1.
Initial
These bits are always read as 1 and cannot be modified.
1
5 VDDII 1* R/W LVDR External Compared Voltage Input Inhibit
0: Use external voltage as LVDI compared voltage
1: Use internal voltage as LVDI compared voltage
This bit is always read as 1 and cannot be modified.
2
3 LVDSEL* 1 R/W LVDR Detection Level Select
0: Reset detection voltage is 2.3 V (Typ.)
1: Reset detection voltage is 3.6 V (Typ.)
When the falling or rising voltage detection interrupt is
used, the reset detection voltage of 2.3 V (Typ.) should
be used. When only a reset detection interrupt is used,
reset detection voltage of 3.6 V (Typ.) should be used.
This bit is always read as 1 and cannot be modified.
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Initial
1 LVDDE 0 R/W Voltage-Fall-Interrupt Enable
0: Interrupt on the power-supply voltage falling disabled
1: Interrupt on the power-supply voltage falling enabled
0 LVDUE 0 R/W Voltage-Rise-Interrupt Enable
0: Interrupt on the power-supply voltage rising disabled
1: Interrupt on the power-supply voltage rising enabled
Notes: 1. Not initialized by an LVDR but initialized by a power-on reset or a watchdog timer reset.
2. For 3.3-V-specification models, this bit 3 of this register is a reserved bit (initial value is
0) and the reset detection voltage is 2.3 V (typ.).
Table 19.1 LVDCR Settings and Select Functions
LVDCR Settings Select Functions

Low-Voltage- Low-Voltage-
Power-On Detection Fall Detection Rise
VDDII LVDSEL LVDDE LVDUE Reset LVDR Interrupt Interrupt
* 1 0 0 √ √  
* 0 1 0 √ √ √ 
* 0 1 1 √ √ √ √
Note: * Set these bits if necessary.
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19.2.2 Low-Voltage-Detection Status Register (LVDSR)
LVDSR indicates whether the power-supply voltage falls below or rises above the respective
given values.
Initial
These bits are always read as 1 and cannot be modified.
1 LVDDF 0* R/W LVD Power-Supply Voltage Fall Flag
[Setting condition]
• When the power-supply voltage falls below Vint (D)
(Typ. = 3.7 V)
• When writing 0 to this bit after reading it as 1
0 LVDUF 0* R/W LVD Power-Supply Voltage Rise Flag
[Setting condition]
• When the power supply voltage falls below Vint (D)
while the LVDUE bit in LVDCR is set to 1 and then
rises above Vint (U) (Typ. = 4.0 V) before falling
below Vreset1 (Typ. = 2.3 V)
• When writing 0 to this bit after reading it as 1
Note: * Initialized by an LVDR.
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19.2.3 Reset Source Decision Register (LVDRF)
LVDSR indicates sources of resets.
Initial
The read value is undefined and these bits cannot be
modified.
1
1 PRST * R/W POR/LVDR Detection
• When a power-on reset has occurred
• When an LVDR has occurred
When writing 0
2
0 WRST * R/W WDT Reset Detection
[Setting condition]
• When a reset by the WDT has occurred
• When a power-on reset has occurred
• When an LVDR has occurred
• When an reset signal input on the external pin has
asserted
• When writing 0
Notes: 1. The initial value depends on the condition when the PRST bit is set or cleared.
2. The initial value depends on the condition when the WRST bit is set or cleared.
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19.3 Operations
19.3.1 Power-On Reset Circuit
Figure 19.3 shows the timing of the operation of the power-on reset circuit. As the power-supply
voltage rises, the capacitor which is externally connected to the RES pin is gradually charged via
the internal pull-up resistor (Typ. 150 kΩ). While the RES signal is driven low, the prescaler S and
the entire chip retains the reset state. When the level on the RES signal reaches the specified value,
the prescaler S is released from its reset state and it starts counting. The OVF signal is generated to
release the internal reset signal after the prescaler S has counted 131,072 cycles of the φ clock. The
noise filter circuit which removes noise with less than 400 ns (Typ.) is included to prevent the
incorrect operation of this LSI caused by noise on the RES signal.
To achieve stable operation of this LSI, the power supply needs to rise to its full level and settles
within the specified time. The maximum time required for the power supply to rise and settle
(tPWON) is determined by the oscillation frequency (fOSC) and capacitance which is connected to RES
pin (CRES). Where tPWON is assumed to be the time required to reach 90 % of the full level of the
power supply, the power supply circuit should be designed to satisfy the following formula.
tPWON (ms) ≤ 90 × CRES (µF) + 162/fOSC (MHz)
(tPWON ≤ 3000 ms, CRES ≥ 0.22 µF, and fOSC = 10 in 2-MHz to 10-MHz operation)
Note that the power supply voltage (Vcc) must fall below Vpor = 100 mV to remove charge on the
RES pin. After that, it can be risen. To remove charge on the RES pin, it is recommended that the
diode should be placed to Vcc. If the power supply voltage (Vcc) rises from the point above Vpor,
a power-on reset may not occur.
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tPWON
Vcc
Vpor
Vss
RES
Vss
PSS-reset
signal
OVF
Internal reset
signal 131,072 cycles
PSS counter starts Reset released
Figure 19.3 Operational Timing of Power-On Reset Circuit
19.3.2 Low-Voltage Detection Circuit
LVDR (Reset by Low Voltage Detection) Circuit:
Figure 19.4 shows the timing of the operation of the LVDR circuit. The LVDR circuit is kept
enabled during the LSI's operation.
When the power-supply voltage falls below the Vreset voltage (the value selected by the LVDSEL
bit: Typ. = 2.3 V or 3.6 V), the LVDR circuit clears the LVDRES signal to 0, and resets prescaler
S. The low-voltage detection reset state remains in place until a power-on reset is generated. When
the power-supply voltage rises above the Vreset voltage (Typ. = 3.6 V) regardless of LVDSEL bit
setting) again, the LVDR circuit sets the LVDRES signal to 1 and prescaler S starts counting.
When 131,072 clock (φ) cycles have been counted, the internal reset signal is released. In this
case, the LVDSEL bit in LVDCR is initialized (the Vreset voltage: Typ. = 3.6 V) though the
VDDII bit is not initialized.
If the power supply voltage (Vcc) falls below Vpor = 100 mV, a power-on reset occurs.
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VCC
Vreset
VLVDRmin
VSS
LVDRES
PSS-reset
signal
OVF
Internal reset
signal 131,072 cycles
PSS counter starts Reset released
Figure 19.4 Operating Timing of LVDR Circuit
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Low Voltage Detection Interrupt (LVDI) Circuit

(When Internally Generated Voltage is used for Detection):
Figure 19.5 shows the timing of the operation of the LVDI circuit.
The LVDI circuit is enabled after a power-on reset, however, the interrupt request is disabled. To
enable the LVDI, the LVDDF bit and LVDUF bit in LVDSR must be cleared to 0 and then the
LVDDE bit or LVDUE bit in LVDCR must be set to 1. After that, the output settings of ports
must be made.
When the power-supply voltage falls below Vint (D) (Typ. = 3.7 V) voltage, the LVDI circuit
clears the LVDINT signal to 0 and sets the LVDDF bit to 1. If the LVDDE bit is 1 at this time, an
IRQ0 interrupt request is generated. In this case, the necessary data must be saved in the external
EEPROM and a transition to standby mode or subsleep mode must be made. Until this processing
is completed, the power supply voltage must be higher than the lower limit of the guaranteed
operating voltage.
When the power-supply voltage does not fall below the Vreset1 (Typ. = 2.3 V) voltage and rises
above the Vint (U) (Typ. = 4.0 V) voltage, the LVDI circuit sets the LVDINT signal to 1. If the
LVDUE bit is 1 at this time, the LVDUF bit in LVDSR is set to 1 and an IRQ0 interrupt request is
simultaneously generated.
If the power supply voltage (Vcc) falls below the Vreset1 (Typ. = 2.3 V) voltage, this LSI enters
low voltage detection reset operation (when LVDRE = 1).
Vint (U)
Vcc
Vint (D)
Vreset1
VSS
LVDINT
LVDDE
LVDDF
LVDUE
LVDUF
IRQ0 interrupt generated IRQ0 interrupt generated
Figure 19.5 Operational Timing of LVDI Circuit
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Low Voltage Detection Interrupt (LVDI) Circuit

(When Voltages Input via ExtU and ExtD Pins are used for Detection):
Figure 19.6 shows the timing of the LVDI circuit. The LVDI circuit is enabled after a power-on
reset, however, the interrupt request is disabled. To enable the LVDI, the LVDDF and LVDUF
bits in LVDSR must be cleared to 0 and the LVDDE or LVDUE bit in LVDCR must be set to 1.
When using external compared voltage, write 0 to the VDDII bit in LVDCR, and wait for 50 µs
(tLVDON) given by a software timer until the detection circuit has settled. Then clear the LVDDF and
LVDUF bits to 0 and set the LVDDE or LVDUE bit to 1. After that, the output settings of ports
must be made. The initial value of the external compared voltages input on the ExtU and ExtD
pins must be higher than the Vexd voltage.
When the external comparison voltage of ExtD pin falls below the Vexd (D) (Typ. = 1.15 V)
voltage, the LVDI clears the LVDINT signal to 0 and sets the LVDDF bit in LVDSR to 1. If the
LVDDE bit is 1 at this time, an IRQ0 interrupt request is generated. In this case, the necessary
data must be saved in the external EEPROM, and a transition to standby mode or subsleep mode
must be made. Until this processing is completed, the power supply voltage must be higher than
the lower limit of the guaranteed operating voltage.
When the power-supply voltage does not fall below the Vreset1 (Typ. = 2.3 V) voltage and the
input voltage of the ExtU pin rises above Vexd (Typ. = 1.15 V) voltage, the LVDI circuit sets the
LVDINT signal to 1. If the LVDUE bit is 1 at this time, the LVDUF bit in LVDSR is set to 1 and
an IRQ0 interrupt request is generated.
If the power supply voltage falls below the Vreset1 (Typ. = 2.3 V) voltage, this LSI enters low-
voltage detection reset operation. When the voltages input on the ExtU and ExtD pins are used as
the compared voltage, ensure to use the LVDR (reset detection voltage: Typ. = 2.3 V) circuit.
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External power
supply voltage
ExtD input voltage
(1)
ExtU input voltage
(2) Vexd
(3)
(4)
Vreset1
VSS
LVDINT
LVDDE
LVDDF
LVDUE
LVDUF
IRQ0 interrupt IRQ0 interrupt

generated generated
Figure 19.6 Operational Timing of LVDI Circuit (When Compared Voltage is Input
through ExtU and ExtD Pins)
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19.3.3 Deciding Reset Source
The source of a reset can be decided by reading the reset source decision register (LVDRF) in the
reset exception handler (see table 19.2). After that, writing 0 to the bit can clear the flag and can be
ready to decide the next reset source.
Figure 19.7 shows a timing of setting the bits in the register.
Table 19.2 Deciding Reset Source
LVDRF
PRST WRST Reset Source
1 0 Power-on reset or LVDR occurred
0 0 Reset signal input on external reset pin
0 1 WDT reset occurred
Power supply voltage
Internal reset signal
Set by Set by temporary drop of

power-on reset power supply voltage
Read and Read and

cleared cleared
(0 is written) (0 is written)
PRST bit
Set by
WDT reset
Read and
cleared
(0 is written)
WRST bit
Figure 19.7 Timing of Setting Bits in Reset Source Decision Register
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This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the
internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the
voltage of the power supply connected to the external V pin. As a result, the current consumed
CC
when an external power supply is used at 3.0 V or above can be held down to virtually the same
low level as when used at approximately 3.0 V.
20.1 Power Supply Connection of 5.0-V-Specification Microcontrollers

Connect the external power supply to the V pin, and connect a capacitor of approximately 0.1 µF
CC
between V and V , as shown in figure 20.1. The internal step-down circuit is made effective
CL SS
simply by adding this external circuit. In the external circuit interface, the external power supply
voltage connected to V and the GND potential connected to V are the reference levels. For
CC SS
example, for port input/output levels, the V level is the reference for the high level, and the V
CC SS
level is that for the low level. The A/D converter analog power supply is not affected by the
internal step-down circuit.
VCC VCC = 4.5 to 5.5 V
Step-down circuit
VCL
Internal Stabilization
Internal capacitor (approx. 0.1 µF)
power
logic
supply
VSS
Figure 20.1 Power Supply Connection of 5.0-V-Specification Microcontrollers
PSCKT00A_000020020200 Rev. 3.00 Sep. 10, 2007 Page 393 of 528

REJ09B0216-0300
20.2 Power Supply Connection of 3.3-V-Specification Microcontrollers

Connect the external power supply to the V and V pins as shown in figure 20.2. The power
CL SS
supply voltage must be within a range of 3.0 to 3.6 V. Otherwise, correct operation is not
guaranteed.
VCC VCC = 3.0 to 3.6 V
Step-down circuit
VCL
Internal
Internal
power
logic
supply
VSS
Figure 20.2 Power Supply Connection of 3.3-V-Specification Microcontrollers
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REJ09B0216-0300
Section 21 List of Registers

The register list gives information on the on-chip I/O register addresses, how the register bits are
configured, and the register states in each operating mode. The information is given as shown
below.
1. Register addresses (address order)

• The register addresses listed in the table are the address values (16 bits) in the 64-Kbyte
address space. The value of the sixteen higher-order bits of address values (24 bits) in the 16-
Mbyte address space is H'FF.
• Registers are listed from the lower allocation addresses.
• The symbol  in the register-name column represents a reserved address or range of reserved
addresses.
Do not attempt to access reserved addresses.
• When the register address is 16-bit wide, the address of the upper byte is given in the list.
• Registers are classified by functional modules.
• The data bus width is indicated.
• The number of access states is indicated.
2. Register bits
• Bit configurations of the registers are described in the same order as the register addresses.
• Reserved bits are indicated by  in the bit name column.
• When registers consist of 16 bits, bits are described from the MSB side.
3. Register states in each operating mode

• Register states are described in the same order as the register addresses.
• The register states described here are for the basic operating modes. If there is a specific reset
for an on-chip peripheral module, refer to the section on that on-chip peripheral module.
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REJ09B0216-0300
21.1 Register Addresses (Address Order)

The data-bus width column indicates the number of bits. The access-state column shows the
number of states of the selected basic clock that is required for access to the register.
Note: Access to undefined or reserved addresses should not take place. Correct operation of the
access itself or later operations is not guaranteed when such a register is accessed.
Data
Abbre- Module Bus Access
Register viation Bit No Address Name Width State
   H'F000   
to
H'F6FF
Timer control register_0 TCR_0 8 H'F700 Timer Z 8 2
Timer I/O control register A_0 TIORA_0 8 H'F701 Timer Z 8 2
Timer I/O control register C_0 TIORC_0 8 H'F702 Timer Z 8 2
Timer status register_0 TSR_0 8 H'F703 Timer Z 8 2
Timer interrupt enable register_0 TIER_0 8 H'F704 Timer Z 8 2
PWM mode output level control POCR_0 8 H'F705 Timer Z 8 2
register_0
Timer counter_0 TCNT_0 16 H'F706 Timer Z 16 2
General register A_0 GRA_0 16 H'F708 Timer Z 16 2
General register B_0 GRB_0 16 H'F70A Timer Z 16 2
General register C_0 GRC_0 16 H'F70C Timer Z 16 2
General register D_0 GRD_0 16 H'F70E Timer Z 16 2
Timer control register_1 TCR_1 8 H'F710 Timer Z 8 2
Timer I/O control register A_1 TIORA_1 8 H'F711 Timer Z 8 2
Timer I/O control register C_1 TIORC_1 8 H'F712 Timer Z 8 2
Timer status register_1 TSR_1 8 H'F713 Timer Z 8 2
Timer interrupt enable register_1 TIER_1 8 H'F714 Timer Z 8 2
PWM mode output level control POCR_1 8 H'F715 Timer Z 8 2
register_1
Timer counter_1 TCNT_1 16 H'F716 Timer Z 16 2
General register A_1 GRA_1 16 H'F718 Timer Z 16 2
General register B_1 GRB_1 16 H'F71A Timer Z 16 2
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REJ09B0216-0300
Data
General register C_1 GRC_1 16 H'F71C Timer Z 16 2
General register D_1 GRD_1 16 H'F71E Timer Z 16 2
Timer start register TSTR 8 H'F720 Timer Z 8 2
Timer mode register TMDR 8 H'F721 Timer Z 8 2
Timer PWM mode register TPMR 8 H'F722 Timer Z 8 2
Timer Z, for common use TFCR 8 H'F723 Timer Z 8 2
Timer output master enable TOER 8 H'F724 Timer Z 8 2
register
Timer output control register TOCR 8 H'F725 Timer Z 8 2
   H'F726, Timer Z  
H'F727
Second data register/free running RSECDR 8 H'F728 RTC 8 2
counter data register
Minute data register RMINDR 8 H'F729 RTC 8 2
Hour data register RHRDR 8 H'F72A RTC 8 2
Day-of-week data register RWKDR 8 H'F72B RTC 8 2
RTC control register 1 RTCCR1 8 H'F72C RTC 8 2
RTC control register 2 RTCCR2 8 H'F72D RTC 8 2
   H'F72E RTC  
Clock source select register RTCCSR 8 H'F72F RTC 8 2
1
Low-voltage-detection control LVDCR 8 H'F730 LVDC* 8 2
register
1
Low-voltage-detection status LVDSR 8 H'F731 LVDC* 8 2
register
1
Reset source decision register LVDRF 8 H'F732 LVDC* 8 2
   H'F733   
Clock control/status register CKCSR 8 H'F734 CPG 8 2
RC control register RCCR 8 H'F735 On-chip 8 2
oscillator
RC trimming data protect register RCTRMDPR 8 H'F736 On-chip 8 2
oscillator
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REJ09B0216-0300
Data
RC trimming data register RCTRMDR 8 H'F737 On-chip 8 2
oscillator
   H'F738 to   
H'F73F
Serial mode register_2 SMR_2 8 H'F740 SCI3_2 8 3
Bit rate register_2 BRR_2 8 H'F741 SCI3_2 8 3
Serial control register 3_2 SCR3_2 8 H'F742 SCI3_2 8 3
Transmit data register_2 TDR_2 8 H'F743 SCI3_2 8 3
Serial status register_2 SSR_2 8 H'F744 SCI3_2 8 3
Receive data register_2 RDR_2 8 H'F745 SCI3_2 8 3
   H'F746, SCI3_2  
H'F747
I2C bus control register 1 ICCR1 8 H'F748 IIC2 8 2
I2C bus control register 2 ICCR2 8 H'F749 IIC2 8 2
I2C bus mode register ICMR 8 H'F74A IIC2 8 2
I2C bus interrupt enable register ICIER 8 H'F74B IIC2 8 2
I2C status register ICSR 8 H'F74C IIC2 8 2
Slave address register SAR 8 H'F74D IIC2 8 2
I2C bus transmit data register ICDRT 8 H'F74E IIC2 8 2
I2C bus receive data register ICDRR 8 H'F74F IIC2 8 2
   H'F750 to   
H'F75F
Timer mode register B1 TMB1 8 H'F760 Timer B1 8 2
Timer counter B1 TCB1 8 H'F761 Timer B1 8 2
Timer load register B1 TLB1 8 H'F761 Timer B1 8 2
   H'F762 to   
H'FF8F
Flash memory control register 1 FLMCR1 8 H'FF90 ROM 8 2
Flash memory control register 2 FLMCR2 8 H'FF91 ROM 8 2
Flash memory power control FLPWCR 8 H'FF92 ROM 8 2
register
Rev. 3.00 Sep. 10, 2007 Page 398 of 528

REJ09B0216-0300
Data
Erase block register 1 EBR1 8 H'FF93 ROM 8 2
   H'FF94 to ROM  
H'FF9A
Flash memory enable register FENR 8 H'FF9B ROM 8 2
   H'FF9C to ROM  
H'FF9F
Timer control register V0 TCRV0 8 H'FFA0 Timer V 8 3
Timer control/status register V TCSRV 8 H'FFA1 Timer V 8 3
Time constant register A TCORA 8 H'FFA2 Timer V 8 3
Time constant register B TCORB 8 H'FFA3 Timer V 8 3
Timer counter V TCNTV 8 H'FFA4 Timer V 8 3
Timer control register V1 TCRV1 8 H'FFA5 Timer V 8 3
   H'FFA6,   
H'FFA7
Serial mode register SMR 8 H'FFA8 SCI3 8 3
Bit rate register BRR 8 H'FFA9 SCI3 8 3
Serial control register 3 SCR3 8 H'FFAA SCI3 8 3
Transmit data register TDR 8 H'FFAB SCI3 8 3
Serial status register SSR 8 H'FFAC SCI3 8 3
Receive data register RDR 8 H'FFAD SCI3 8 3
   H'FFAE, SCI3  
H'FFAF
A/D data register ADDRA 16 H'FFB0 A/D 8 3
converter
A/D data register ADDRB 16 H'FFB2 A/D 8 3
converter
A/D data register ADDRC 16 H'FFB4 A/D 8 3
converter
A/D data register ADDRD 16 H'FFB6 A/D 8 3
converter
A/D control/status register ADCSR 8 H'FFB8 A/D 8 3
converter
Rev. 3.00 Sep. 10, 2007 Page 399 of 528

REJ09B0216-0300
Data
A/D control register ADCR 8 H'FFB9 A/D 8 3
converter
   H'FFBA,   
H'FFBB
PWM data register L PWDRL 8 H'FFBC 14-bit PWM 8 2
PWM data register U PWDRU 8 H'FFBD 14-bit PWM 8 2
PWM control register PWCR 8 H'FFBE 14-bit PWM 8 2
   H'FFBF 14-bit PWM  
1
Timer control/status register WD TCSRWD 8 H'FFC0 WDT* 8 2
1
Timer counter WD TCWD 8 H'FFC1 WDT* 8 2
1
Timer mode register WD TMWD 8 H'FFC2 WDT* 8 2
    
1
H'FFC3 WDT*
   H'FFC4   
to
H'FFC7
Address break control register ABRKCR 8 H'FFC8 Address break 8 2
Address break status register ABRKSR 8 H'FFC9 Address break 8 2
Break address register H BARH 8 H'FFCA Address break 8 2
Break address register L BARL 8 H'FFCB Address break 8 2
Break data register H BDRH 8 H'FFCC Address break 8 2
Break data register L BDRL 8 H'FFCD Address break 8 2
   H'FFCE   
2
Break address register E* BARE 8 H'FFCF Address break 8 2
Port pull-up control register 1 PUCR1 8 H'FFD0 I/O port 8 2
Port pull-up control register 5 PUCR5 8 H'FFD1 I/O port 8 2
   H'FFD2, I/O port  
H'FFD3
Port data register 1 PDR1 8 H'FFD4 I/O port 8 2
   H'FFD7 I/O port  
Rev. 3.00 Sep. 10, 2007 Page 400 of 528

REJ09B0216-0300
Data
Port data register 7 PDR7 8 H'FFDA I/O port 8 2
Port data register 8 PDR8 8 H'FFDB I/O port 8 2
   H'FFDC I/O port  
Port data register B PDRB 8 H'FFDD I/O port 8 2
Port data register C PDRC 8 H'FFDE I/O port 8 2
   H'FFDF I/O port  
Port mode register 1 PMR1 8 H'FFE0 I/O port 8 2
   H'FFD3 I/O port  
Port control register 1 PCR1 8 H'FFE4 I/O port 8 2
   H'FFE7 I/O port  
Port control register 7 PCR7 8 H'FFEA I/O port 8 2
Port control register 8 PCR8 8 H'FFEB I/O port 8 2
   H'FFEC, I/O port  
H'FFED
Port control register C PCRC 8 H'FFEE I/O port 8 2
   H'FFEF I/O port  
System control register 1 SYSCR1 8 H'FFF0 Low power 8 2
System control register 2 SYSCR2 8 H'FFF1 Low power 8 2
Interrupt edge select register 1 IEGR1 8 H'FFF2 Interrupt 8 2
Interrupt edge select register 2 IEGR2 8 H'FFF3 Interrupt 8 2
Interrupt enable register 1 IENR1 8 H'FFF4 Interrupt 8 2
Interrupt enable register 2 IENR2 8 H'FFF5 Interrupt 8 2
Interrupt flag register 1 IRR1 8 H'FFF6 Interrupt 8 2
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REJ09B0216-0300
Data
Interrupt flag register 2 IRR2 8 H'FFF7 Interrupt 8 2
Wakeup interrupt flag register IWPR 8 H'FFF8 Interrupt 8 2
Module standby control register 1 MSTCR1 8 H'FFF9 Low power 8 2
Module standby control register 2 MSTCR2 8 H'FFFA Low power 8 2
   H'FFEB Low power  
   H'FFFC   
to
H'FFFF
Notes: 1. WDT: Watchdog timer
2. Only provided for microcontrollers that supports advanced mode.
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REJ09B0216-0300
21.2 Register Bits

The addresses and bit names of the registers in the on-chip peripheral modules are listed below.
The 16-bit register is indicated in two rows, 8 bits for each row.
Register Module
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name
         
TCR_0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Timer Z
TIORA_0  IOB2 IOB1 IOB0  IOA2 IOA1 IOA0
TIORC_0  IOD2 IOD1 IOD0  IOC2 IOC1 IOC0
TSR_0    OVF IMFD IMFC IMFB IMFA
TIER_0    OVIE IMIED IMIEC IMIEB IMIEA
POCR_0      POLD POLC POLB
TCNT_0 TCNT0H7 TCNT0H6 TCNT0H5 TCNT0H4 TCNT0H3 TCNT0H2 TCNT0H1 TCNT0H0
TCNT0L7 TCNT0L6 TCNT0L5 TCNT0L4 TCNT0L3 TCNT0L2 TCNT0L1 TCNT0L0
GRA_0 GRA0H7 GRA0H6 GRA0H5 GRA0H4 GRA0H3 GRA0H2 GRA0H1 GRA0H0
GRA0L7 GRA0L6 GRA0L5 GRA0L4 GRA0L3 GRA0L2 GRA0L1 GRA0L0
GRB_0 GRB0H7 GRB0H6 GRB0H5 GRB0H4 GRB0H3 GRB0H2 GRB0H1 GRB0H0
GRB0L7 GRB0L6 GRB0L5 GRB0L4 GRB0L3 GRB0L2 GRB0L1 GRB0L0
GRC_0 GRC0H7 GRC0H6 GRC0H5 GRC0H4 GRC0H3 GRC0H2 GRC0H1 GRC0H0
GRC0L7 GRC0L6 GRC0L5 GRC0L4 GRC0L3 GRC0L2 GRC0L1 GRC0L0
GRD_0 GRD0H7 GRD0H6 GRD0H5 GRD0H4 GRD0H3 GRD0H2 GRD0H1 GRD0H0
GRD0L7 GRD0L6 GRD0L5 GRD0L4 GRD0L3 GRD0L2 GRD0L1 GRD0L0
TCR_1 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
TIORA_1  IOB2 IOB1 IOB0  IOA2 IOA1 IOA0
TIORC_1  IOD2 IOD1 IOD0  IOC2 IOC1 IOC0
TSR_1   UDF OVF IMFD IMFC IMFB IMFA
TIER_1    OVIE IMIED IMIEC IMIEB IMIEA
POCR_1      POLD POLC POLB
TCNT_1 TCNT1H7 TCNT1H6 TCNT1H5 TCNT1H4 TCNT1H3 TCNT1H2 TCNT1H1 TCNT1H0
TCNT1L7 TCNT1L6 TCNT1L5 TCNT1L4 TCNT1L3 TCNT1L2 TCNT1L1 TCNT1L0
GRA_1 GRA1H7 GRA1H6 GRA1H5 GRA1H4 GRA1H3 GRA1H2 GRA1H1 GRA1H0
GRA1L7 GRA1L6 GRA1L5 GRA1L4 GRA1L3 GRA1L2 GRA1L1 GRA1L0
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Register Module
GRB_1 GRB1H7 GRB1H6 GRB1H5 GRB1H4 GRB1H3 GRB1H2 GRB1H1 GRB1H0 Timer Z
GRB1L7 GRB1L6 GRB1L5 GRB1L4 GRB1L3 GRB1L2 GRB1L1 GRB1L0
GRC_1 GRC1H7 GRC1H6 GRC1H5 GRC1H4 GRC1H3 GRC1H2 GRC1H1 GRC1H0
GRC1L7 GRC1L6 GRC1L5 GRC1L4 GRC1L3 GRC1L2 GRC1L1 GRC1L0
GRD_1 GRD1H7 GRD1H6 GRD1H5 GRD1H4 GRD1H3 GRD1H2 GRD1H1 GRD1H0
GRD1L7 GRD1L6 GRD1L5 GRD1L4 GRD1L3 GRD1L2 GRD1L1 GRD1L0
TSTR       STR1 STR0
TMDR BFD1 BFC1 BFD0 BFC0    SYNC
TPMR  PWMD1 PWMC1 PWMB1  PWMD0 PWMC0 PWMB0
TFCR  STCLK ADEG ADTRG OLS1 OLS0 CMD1 CMD0
TOER ED1 EC1 EB1 EA1 ED0 EC0 EB0 EA0
TOCR TOD1 TOC1 TOB1 TOA1 TOD0 TOC0 TOB0 TOA0
RSECDR BSY SC12 SC11 SC10 SC03 SC02 SC01 SC00 RTC
RMINDR BSY MN12 MN11 MN10 MN03 MN02 MN01 MN00
RHRDR BSY  HR11 HR10 HR03 HR02 HR01 HR00
RWKDR BSY     WK2 WK1 WK0
RTCCR1 RUN 12/24 PM RST INT   
RTCCR2   FOIE WKIE DYIE HRIE MNIE SEIE
RTCCSR  RCS6 RCS5  RCS3 RCS2 RCS1 RCS0
LVDCR   VDDII  LVDSEL* 1

 LVDDE LVDUE LVDC
LVDSR       LVDDF LVDUF
LVDRF       PRST WRST
         
CKCSR PMRC1 PMRC0 OSCBAKE OSCSEL CKSWIE CKSWIF OSCHLT CKSTA CPG
RCCR RCSTP FSEL VCLSEL    RCPSC1 RCPSC0 On-chip

oscillator
RCTRMDPR WRI PRWE LOCKDW TRMDRWE    
RCTRMDR TRMD7 TRMD6 TRMD5 TRMD4 TRMD3 TRMD2 TRMD1 TRMD0
         
SMR_2 COM CHR PE PM STOP MP CKS1 CKS0 SCI3_2
BRR_2 BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0
SCR3_2 TIE RIE TE RE MPIE TEIE CKE1 CKE0
Rev. 3.00 Sep. 10, 2007 Page 404 of 528

REJ09B0216-0300
Register Module
TDR_2 TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 SCI3_2
SSR_2 TDRE RDRF OER FER PER TEND MPBR MPBT
RDR_2 RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0
ICCR1 ICE RCVD MST TRS CKS3 CKS2 CKS1 CKS0 IIC2
ICCR2 BBSY SCP SDAO SDAOP SCLO  IICRST 
ICMR MLS WAIT   BCWP BC2 BC1 BC0
ICIER TIE TEIE RIE NAKIE STIE ACKE ACKBR ACKBT
ICSR TDRE TEND RDRF NACKF STOP AL/OVE AAS ADZ
SAR SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS
ICDRT ICDRT7 ICDRT6 ICDRT5 ICDRT4 ICDRT3 ICDRT2 ICDRT1 ICDRT0
ICDRR ICDRR7 ICDRR6 ICDRR5 ICDRR4 ICDRR3 ICDRR2 ICDRR1 ICDRR0
         
TMB1 TMB17     TMB12 TMB11 TMB10 Timer B1
TCB1 TCB17 TCB16 TCB15 TCB14 TCB13 TCB12 TCB11 TCB10
TLB1 TLB17 TLB16 TLB15 TLB14 TLB13 TLB12 TLB11 TLB10
         
FLMCR1  SWE ESU PSU EV PV E P ROM
FLMCR2 FLER       
FLPWCR PDWND       
1
EBR1* EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0
FENR FLSHE       
TCRV0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Timer V
TCSRV CMFB CMFA OVF  OS3 OS2 OS1 OS0
TCORA TCORA7 TCORA6 TCORA5 TCORA4 TCORA3 TCORA2 TCORA1 TCORA0
TCORB TCORB7 TCORB6 TCORB5 TCORB4 TCORB3 TCORB2 TCORB1 TCORB0
TCNTV TCNTV7 TCNTV6 TCNTV5 TCNTV4 TCNTV3 TCNTV2 TCNTV1 TCNTV0
TCRV1    TVEG1 TVEG0 TRGE  ICKS0
         
SMR COM CHR PE PM STOP MP CKS1 CKS0 SCI3
BRR BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0
SCR3 TIE RIE TE RE MPIE TEIE CKE1 CKE0
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REJ09B0216-0300
Register Module
TDR TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 SCI3
SSR TDRE RDRF OER FER PER TEND MPBR MPBT
RDR RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0
ADDRA AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A/D
converter
AD1 AD0      
ADDRB AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
AD1 AD0      
ADDRC AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
AD1 AD0      
ADDRD AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
AD1 AD0      
ADCSR ADF ADIE ADST SCAN CKS CH2 CH1 CH0
ADCR TRGE       
         
PWDRL PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 14-bit
PWM
PWDRU   PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0
PWCR        PWCR0
TCSRWD B6WI TCWE B4WI TCSRWE B2WI WDON B0WI WRST WDT*2
TCWD TCWD7 TCWD6 TCWD5 TCWD4 TCWD3 TCWD2 TCWD1 TCWD0
TMWD     CKS3 CKS2 CKS1 CKS0
         
ABRKCR RTINTE CSEL1 CSEL0 ACMP2 ACMP1 ACMP0 DCMP1 DCMP0 Address
break
ABRKSR ABIF ABIE      
BARH BARH7 BARH6 BARH5 BARH4 BARH3 BARH2 BARH1 BARH0
BARL BARL7 BARL6 BARL5 BARL4 BARL3 BARL2 BARL1 BARL0
BDRH BDRH7 BDRH6 BDRH5 BDRH4 BDRH3 BDRH2 BDRH1 BDRH0
BDRL BDRL7 BDRL6 BDRL5 BDRL4 BDRL3 BDRL2 BDRL1 BDRL0

3
BARE* BDRE7 BDRE6 BDRE5 BDRE4 BDRE3 BDRE2 BDRE1 BDRE0
PUCR1 PUCR17 PUCR16 PUCR15 PUCR14  PUCR12 PUCR11 PUCR10 I/O port
PUCR5   PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50
PDR1 P17 P16 P15 P14  P12 P11 P10
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REJ09B0216-0300
Register Module
PDR2    P24 P23 P22 P21 P20 I/O port
PDR3 P37 P36 P35 P34 P33 P32 P31 P30
PDR5 P57 P56 P55 P54 P53 P52 P51 P50
PDR6 P67 P66 P65 P64 P63 P62 P61 P60
PDR7  P76 P75 P74  P72 P71 P70
PDR8 P87 P86 P85     
PDRB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
PDRC       PC1 PC0
PMR1 IRQ3 IRQ2 IRQ1 IRQ0 TXD2 PWM TXD TMOW
PMR5 POF57 POF56 WKP5 WKP4 WKP3 WKP2 WKP1 WKP0
PMR3    POF24 POF23   
PCR1 PCR17 PCR16 PCR15 PCR14  PCR12 PCR11 PCR10
PCR2    PCR24 PCR23 PCR22 PCR21 PCR20
PCR3 PCR37 PCR36 PCR35 PCR34 PCR33 PCR32 PCR31 PCR30
PCR7  PCR76 PCR75 PCR74  PCR72 PCR71 PCR70
PCR8 PCR87 PCR86 PCR85     
PCRC       PCRC1 PCRC0
SYSCR1 SSBY STS2 STS1 STS0 NESEL    Low power
SYSCR2 SMSEL LSON DTON MA2 MA1 MA0 SA1 SA0
IEGR1 NMIEG    IEG3 IEG2 IEG1 IEG0 Interrupt
IEGR2   WPEG5 WPEG4 WPEG3 WPEG2 WPEG1 WPEG0
IENR1 IENDT IENTA IENWP  IEN3 IEN2 IEN1 IEN0
IENR2   IENTB1     
IRR1 IRRDT IRRTA   IRRI3 IRRI2 IRRI1 IRRI0
IRR2   IRRTB1     
IWPR   IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0
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REJ09B0216-0300
Register Module
MSTCR1  MSTIIC MSTS3 MSTAD MSTWD  MSTTV MSTTA Low power
MSTCR2 MSTS3_2   MSTTB1   MSTTZ MSTPWM
         
Notes: 1. The LVDSEL bit is only provided for the 5.0-V specification products.
2. WDT: Watchdog timer
3. The BARE register is only provided for microcontrollers that support advanced mode.
4. The bit configuration of EBR1 differs according to products. For the bit configuration of
each product, see the list below.
• H8/36079G, H8/36079L
Register Module
EBR1 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 ROM
• H8/36078G, H8/36078L, H8/36077G, H8/36077L

Register Module
EBR1  EB6 EB5 EB4 EB3 EB2 EB1 EB0 ROM
• H8/36074G, H8/36074L
Register Module
EBR1    EB4 EB3 EB2 EB1 EB0 ROM
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21.3 Registers States in Each Operating Mode

Register
Name Reset Active Sleep Subactive Subsleep Standby Module
TCR_0 Initialized      Timer Z
TIORA_0 Initialized     
TIORC_0 Initialized     
TSR_0 Initialized     
TIER_0 Initialized     
POCR_0 Initialized     
TCNT_0 Initialized     
GRA_0 Initialized     
GRB_0 Initialized     
GRC_0 Initialized     
GRD_0 Initialized     
TCR_1 Initialized     
TIORA_1 Initialized     
TIORC_1 Initialized     
TSR_1 Initialized     
TIER_1 Initialized     
POCR_1 Initialized     
TCNT_1 Initialized     
GRA_1 Initialized     
GRB_1 Initialized     
GRC_1 Initialized     
GRD_1 Initialized     
TSTR Initialized     
TMDR Initialized     
TPMR Initialized     
TFCR Initialized     
TOER Initialized     
TOCR Initialized     
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Register
RSECDR       RTC
RMINDR      
RHRDR      
RWKDR      
RTCCR1      
RTCCR2      
RTCCSR Initialized     
    
1
LVDCR Initialized LVDC*
LVDSR Initialized     
LVDRF      
CKCSR Initialized      CPG
RCCR Initialized      On-chip

oscillator
RCTRMDPR Initialized     
RCTRMDR Initialized     
SMR_2 Initialized   Initialized Initialized Initialized SCI3_2
BRR_2 Initialized   Initialized Initialized Initialized
SCR3_2 Initialized   Initialized Initialized Initialized
TDR_2 Initialized   Initialized Initialized Initialized
SSR_2 Initialized   Initialized Initialized Initialized
RDR_2 Initialized   Initialized Initialized Initialized
ICCR1 Initialized      IIC2
ICCR2 Initialized     
ICMR Initialized     
ICIER Initialized     
ICSR Initialized     
SAR Initialized     
ICDRT Initialized     
ICDRR Initialized     
TMB1 Initialized      Timer B1
TCB1 Initialized     
TLB1 Initialized     
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Register
FLMCR1 Initialized   Initialized Initialized Initialized ROM
FLMCR2 Initialized     
FLPWCR Initialized     
EBR1 Initialized   Initialized Initialized Initialized
FENR Initialized     
TCRV0 Initialized   Initialized Initialized Initialized Timer V
TCSRV Initialized   Initialized Initialized Initialized
TCORA Initialized   Initialized Initialized Initialized
TCORB Initialized   Initialized Initialized Initialized
TCNTV Initialized   Initialized Initialized Initialized
TCRV1 Initialized   Initialized Initialized Initialized
SMR Initialized   Initialized Initialized Initialized SCI3
BRR Initialized   Initialized Initialized Initialized
SCR3 Initialized   Initialized Initialized Initialized
TDR Initialized   Initialized Initialized Initialized
SSR Initialized   Initialized Initialized Initialized
RDR Initialized   Initialized Initialized Initialized
ADDRA Initialized   Initialized Initialized Initialized A/D converter
ADDRB Initialized   Initialized Initialized Initialized
ADDRC Initialized   Initialized Initialized Initialized
ADDRD Initialized   Initialized Initialized Initialized
ADCSR Initialized   Initialized Initialized Initialized
ADCR Initialized   Initialized Initialized Initialized
PWDRL Initialized      14bit PWM
PWDRU Initialized     
PWCR Initialized     
TCSRWD Initialized      WDT*1
TCWD Initialized     
TMWD Initialized     
ABRKCR Initialized      Address break
ABRKSR Initialized     
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Register
BARH Initialized      Address break
BARL Initialized     
BDRH Initialized     
BDRL Initialized     
BARE* 2
Initialized     
PUCR1 Initialized      I/O port
PUCR5 Initialized     
PDR1 Initialized     
PDRB Initialized     
PDRC Initialized     
PMR1 Initialized     
PCR1 Initialized     
PCRC Initialized     
SYSCR1 Initialized      Low power
SYSCR2 Initialized     
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REJ09B0216-0300
Register
IEGR1 Initialized      Interrupt
IEGR2 Initialized     
IENR1 Initialized     
IENR2 Initialized     
IRR1 Initialized     
IRR2 Initialized     
IWPR Initialized     
MSTCR1 Initialized      Low power
MSTCR2 Initialized     
Notes:  is not initialized

1. WDT: Watchdog timer
2. The BARE register is only provided for microcontrollers that support advanced mode.
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REJ09B0216-0300
22.1 Absolute Maximum Ratings

Table 22.1 Absolute Maximum Ratings
Item Symbol Value Unit Note

Power supply voltage VCC –0.3 to +7.0 V *
Analog power supply voltage AVCC –0.3 to +7.0 V
Input voltage Ports other than ports VIN –0.3 to VCC +0.3 V
B and X1
Port B –0.3 to AVCC +0.3 V
X1 –0.3 to 4.3 V
Operating temperature Topr Regular specifications: °C
–20 to +75
Wide-range specifications: °C
–40 to +85
Storage temperature Tstg –55 to +125 °C
Notes: * Permanent damage may result if maximum ratings are exceeded. Normal operation
should be under the conditions specified in Electrical Characteristics. Exceeding these
values can result in incorrect operation and reduced reliability.
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REJ09B0216-0300
22.2 Electrical Characteristics (F-ZTAT™ 5.0-V Version)
22.2.1 Power Supply Voltage and Operating Ranges
(1) Power Supply Voltage and Oscillation Frequency Range
φOSC (MHz) φW (kHz)

20.0
32.768
4.0
4.5 5.5 VCC (V) 4.5 5.5 VCC (V)

• AVCC = 4.5 to 5.5 V • AVCC = 4.5 to 5.5 V
• Active mode • All operating modes
• Sleep mode
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(2) Power Supply Voltage and Operating Frequency Range
φ (MHz) φSUB (kHz)

20.0
16.384
8.192
4.0 4.096
4.5 5.5 VCC (V) 4.5 5.5 VCC (V)

• AVCC = 4.5 to 5.5 V • AVCC = 4.5 to 5.5 V
• Active mode • Subactive mode
• Sleep mode • Subsleep mode
(When MA2 in SYSCR2 = 0 )
φ (kHz)
2500
78.125
4.5 5.5 VCC (V)

• AVCC = 4.5 to 5.5 V
• Active mode
• Sleep mode
(When MA2 in SYSCR2 = 1 )
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REJ09B0216-0300
(3) Analog Power Supply Voltage and A/D Converter Accuracy Guaranteed Range
φ (MHz)
20.0
4.0
4.5 5.5 AVCC (V)
• VCC = 4.5 to 5.5 V

• Active mode
• Sleep mode
(4) Range of Power Supply Voltage and Oscillation Frequency when Low-Voltage
Detection Circuit is Used
φosc (MHz)
20.0
16.0
4.0
Vcc (V)
3.0 4.5 5.5
Operation guaranteed range

Operation guaranteed range except
A/D conversion accuracy
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REJ09B0216-0300
22.2.2 DC Characteristics
Table 22.2 DC Characteristics (1)
VCC = 4.5 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C/–40 to +85°C, unless otherwise indicated.
Values
Item Symbol Applicable Pins Test Condition Min. Typ. Max. Unit Notes
Input high VIH RES, NMI, VCC × 0.8 — VCC + 0.3 V
voltage WKP0 to WKP5,
IRQ0 to IRQ3,
ADTRG, TMIB1,
TMRIV,
TMCIV, FTIOA0
to FTIOD0,
FTIOA1 to
FTIOD1, SCK3,
SCK3_2, TRGV
RXD, RXD_2, VCC × 0.7 — VCC + 0.3 V
SCL, SDA,
P10 to P12,
P14 to P17,
P20 to P24,
P30 to P37,
P50 to P57,
P60 to P67,
P70 to P72
P74 to P76,
P85 to P87,
PC0, PC1
PB0 to PB7 AVCC = 4.5 to 5.5 V AVCC × 0.7 — AVCC + 0.3 V
OSC1 VCC – 0.5 — VCC + 0.3 V
Input low VIL RES, NMI, –0.3 — VCC × 0.2 V
IRQ0 to IRQ3,
ADTRG, TMIB1,
TMRIV,
TMCIV, FTIOA0
to FTIOD0,
FTIOA1 to
FTIOD1, SCK3,
SCK3_2, TRGV
Note: Connect the TEST pin to Vss.
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Values
Input low VIL RXD, RXD_2, –0.3 — VCC × 0.3 V
voltage SCL, SDA,
P10 to P12,
P14 to P17,
P20 to P24,
P30 to P37,
P50 to P57,
P60 to P67,
P70 to P72,
P74 to P76,
P85 to P87,
PC0, PC1
PB0 to PB7 AVCC = 4.5 to 5.5 V –0.3 — AVCC × 0.3 V
OSC1 –0.3 — 0.5 V
Output VOH P10 to P12, –IOH = 1.5 mA VCC – 1.0 — — V
high P14 to P17,
voltage P20 to P24,
P30 to P37,
P50 to P55, –IOH = 0.1 mA VCC – 0.5 — —
P60 to P67,
P70 to P72,
P74 to P76,
P85 to P87,
PC0, PC1
P56, P57 –IOH = 0.1 mA VCC – 2.5 — — V
Output VOL P10 to P12, IOL = 1.6 mA — — 0.6 V
low P14 to P17,
voltage P20 to P24,
P30 to P37,
P50 to P57, IOL = 0.4 mA — — 0.4
P70 to P72,
P74 to P76,
P85 to P87
PC0, PC1
P60 to P67 IOL = 20.0 mA — — 1.5 V
IOL = 10.0 mA — — 1.0
IOL = 1.6 mA — — 0.4
IOL = 0.4 mA — — 0.4
SCL, SDA IOL = 6.0 mA — — 0.6
IOL = 3.0 mA — — 0.4
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Values
Item Symbol Applicable Pins Test Condition Min Typ Max Unit Notes
Input/ | IIL | OSC1, TMIB1, VIN = 0.5 V to — — 1.0 µA
output RES, NMI, (VCC – 0.5 V)
leakage WKP0 to WKP5,
current IRQ0 to IRQ3,
ADTRG, TRGV,
TMRIV, TMCIV,
FTIOA0 to
FTIOD0, FTIOA1
to FTIOD1 RXD,
SCK3, RXD_2,
SCK3_2, SCL,
SDA
P10 to P12, VIN = 0.5 V to — — 1.0 µA
P14 to P17, (VCC – 0.5 V)
P20 to P24,
P30 to P37,
P50 to P57,
P60 to P67,
P70 to P72,
P74 to P76,
P85 to P87,
PC0, PC1
PB0 to PB7 VIN = 0.5 V to — — 1.0 µA
(AVCC – 0.5 V)
Pull-up –Ip P10 to P12, VCC = 5.0 V, 50.0 — 300.0 µA
MOS P14 to P17, VIN = 0.0 V
current P50 to P55
Input Cin All input pins f = 4 MHz, — — 15.0 pF
capaci- except power VIN = 0.0 V,
tance supply pins Ta = 25°C
Active IOPE1 VCC Active mode 1 — 19.0 28.0 mA *
mode VCC = 5.0 V,
supply fOSC = 20 MHz
current Active mode 1 — 11.0 — *
VCC = 5.0 V, Reference
fOSC = 10 MHz value
IOPE2 VCC Active mode 2 — 3.0 5.5 mA *
VCC = 5.0 V,
fOSC = 20 MHz
Active mode 2 — 2.5 — *
fOSC = 10 MHz value
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Values
Sleep ISLEEP1 VCC Sleep mode 1 — 12.0 20.0 mA *
mode VCC = 5.0 V,
current Sleep mode 1 — 6.5 — *
fOSC = 10 MHz value
ISLEEP2 VCC Sleep mode 2 — 2.5 4.0 mA *
VCC = 5.0 V,
fOSC = 20 MHz
Sleep mode 2 — 2.2 — *
fOSC = 10 MHz value
Subactive ISUB VCC VCC = 5.0 V — 95.0 145.0 µA *
mode 32-kHz crystal
supply resonator
current (φSUB = φW/2)
VCC = 5.0 V — 85.0 — *
32-kHz crystal Reference
resonator value
(φSUB = φW/8)
Subsleep ISUBSP VCC VCC = 5.0 V — 85.0 140.0 µA *
mode 32-kHz crystal
supply resonator
Standby ISTBY VCC 32-kHz crystal — — 135.0 µA *
mode resonator not
supply used
current
RAM data VRAM VCC 2.0 — — V
retention
voltage
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Note: * Pin states during supply current measurement are given below (excluding current in the
pull-up MOS transistors and output buffers).
Mode RES Pin Internal State Other Pins Oscillator Pins
Active mode 1 VCC Operates VCC Main clock:
ceramic or crystal
resonator, and on-chip
oscillator
Active mode 2 Operates Subclock:
(φOSC/64) Pin X1 = VSS
Sleep mode 1 VCC Only timers operate VCC
Sleep mode 2 Only timers operate
(φOSC/64)
Subactive mode VCC Operates VCC Main clock:
ceramic or crystal
oscillator
Subsleep mode VCC Only timers operate VCC Subclock:
crystal resonator
Standby mode VCC CPU and timers VCC Main clock:
both stop ceramic or crystal
oscillator
Subclock:
Pin X1 = VSS
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VCC = 4.5 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C/–40 to +85°C, unless otherwise indicated.
Applicable Values
Item Symbol Pins Test Condition Min. Typ. Max. Unit
Permissible output IOL Output pins — — 2.0 mA
low current (per pin) except port 6,
SCL, and SDA
Port 6 — — 20.0
Permissible output ∑IOL Output pins — — 40.0 mA
low current (total) except port 6,
SCL, and SDA
Port 6, SCL, and — — 80.0
SDA
Permissible output –IOH All output pins — — 5.0 mA
high current (per pin)
Permissible output –∑IOH All output pins — — 50.0 mA
high current (total)
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REJ09B0216-0300
22.2.3 AC Characteristics
Table 22.3 AC Characteristics
VCC = 4.5 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75°C/-40 to +85°C, unless otherwise indicated.
Values
Applicable Reference
Item Symbol Pins Test Condition Min. Typ. Max. Unit Figure
System clock fOSC OSC1, OSC2 4.0 — 20.0 MHz *1
oscillation
frequency
System clock (φ) tcyc 1 — 64 tOSC *2
cycle time — — 12.8 µs
Subclock fW X1, X2 — 32.768 — kHz
oscillation
frequency
Watch clock (φW) tW X1, X2 — 30.5 — µs
cycle time
Subclock (φSUB) tsubcyc 2 — 8 tW *2
cycle time
Instruction cycle 2 — — tcyc
time tsubcyc
Oscillation trc OSC1, — — 10.0 ms
stabilization time OSC2
(crystal resonator)
(ceramic resonator)
Oscillation trc — — 500 µs
stabilization time
(on-chip oscillator)
Oscillation trcx X1, X2 — — 2.0 s
stabilization time
External clock high tCPH OSC1 20.0 — — ns Figure 22.1
width
External clock low tCPL OSC1 20.0 — — ns
width
External clock rise tCPr OSC1 — — 10.0 ns
time — — 15.0
External clock fall tCPf OSC1 — — 10.0 ns
time — — 15.0
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Values
RES pin low tREL RES At power-on and in trc — — ms Figure 22.2
width modes other than
those below
In active mode and 2500 — — ns
sleep mode
Input pin high tIH NMI, TMIB1, 2 — — tcyc Figure 22.3
width IRQ0 to IRQ3, tsubcyc
WKP0 to
WKP5,
TMCIV,
TMRIV,
TRGV,
ADTRG,
FTIOA0 to
FTIOD0,
FTIOA1 to
FTIOD1
Input pin low tIL NMI, TMIB1, 2 — — tcyc
width IRQ0 to IRQ3, tsubcyc
WKP0 to
WKP5,
TMCIV,
TMRIV,
TRGV,
ADTRG,
FTIOA0 to
FTIOD0,
FTIOA1 to
FTIOD1
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Values
On-chip oscillator fRC Vcc = 5.0 V, 19.70 20.0 20.30 MHz
oscillation Ta = 25°C,
frequency FSEL = 1,
VCLSEL = 0
FSEL = 1, 19.40 20.0 20.60
Ta = -20 to +75°C,
VCLSEL = 0
FSEL = 1, 19.20 20.00 20.80
Ta = -40 to +85°C,
VCLSEL = 0
Vcc = 5.0 V, 15.76 16.0 16.24
Ta = 25°C,
FSEL = 0,
VCLSEL = 0
FSEL = 0, 15.52 16.0 16.48
Ta = -20 to +75°C,
VCLSEL = 0
FSEL = 0, 15.36 16.0 16.64
Ta = -40 to +85°C,
VCLSEL = 0
Notes: 1. When an external clock is input, the minimum frequency of the external clock oscillator
is 4.0 MHz.
2. Determined by MA2 to MA0, SA1, and SA0 in system control register 2 (SYSCR2).
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2
Table 22.4 I C Bus Interface Timing
Values
Test Reference
Item Symbol Condition Min. Typ. Max. Unit Figure
SCL input cycle time tSCL 12tcyc + 600 — — ns Figure 22.4
SCL input high width tSCLH 3tcyc + 300 — — ns
SCL input low width tSCLL 5tcyc + 300 — — ns
SCL and SDA input tSf — — 300 ns
fall time
SCL and SDA input tSP — — 1tcyc ns
spike pulse removal
time
SDA input bus-free tBUF 5tcyc — — ns
time
Start condition input tSTAH 3tcyc — — ns
hold time
Repeated start tSTAS 3tcyc — — ns
condition input setup
time
Setup time for stop tSTOS 3tcyc — — ns
condition input
Data-input setup time tSDAS 1tcyc+20 — — ns
Data-input hold time tSDAH 0 — — ns
Capacitive load of cb 0 — 400 pF
SCL and SDA
SCL and SDA output tSf — — 250 ns
fall time
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Table 22.5 Serial Communication Interface (SCI) Timing
Values
Input Asynchro- tScyc SCK3 4 — — tcyc Figure 22.5
clock nous
cycle Clock 6 — —
synchro-
nous
Input clock pulse tSCKW SCK3 0.4 — 0.6 tScyc
width
Transmit data delay tTXD TXD — — 1 tcyc Figure 22.6
time (clock
synchronous)
Receive data setup tRXS RXD 50.0 — — ns
time (clock
synchronous)
Receive data hold tRXH RXD 50.0 — — ns
time (clock
synchronous)
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22.2.4 A/D Converter Characteristics
Table 22.6 A/D Converter Characteristics
Values
Applicable Test Reference
Item Symbol Pins Condition Min. Typ. Max. Unit Figure
Analog power supply AVCC AVCC 4.5 VCC 5.5 V *1
voltage
Analog input voltage AVIN AN0 to VSS – 0.3 — AVCC + 0.3 V
AN7
Analog power supply AIOPE AVCC AVCC = 5.0 V — — 2.0 mA
current fOSC =
20 MHz
AISTOP1 AVCC — 50 — µA *2
Reference
value
AISTOP2 AVCC — — 5.0 µA *3
Analog input CAIN AN0 to — — 30.0 pF
capacitance AN7
Permissible signal RAIN AN0 to — — 5.0 kΩ
source impedance AN7
Resolution 10 10 10 bit
(data length)
Conversion time AVCC = 4.5 to 70 — — tcyc
(single mode) 5.5 V
Nonlinearity error — — ±7.5 LSB
Offset error — — ±7.5 LSB
Full-scale error — — ±7.5 LSB
Quantization error — — ±0.5 LSB
Absolute accuracy — — ±8.0 LSB
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Values
(single mode) 5.5 V
Notes: 1. Set AVCC = VCC when the A/D converter is not used.
2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle.
3. AISTOP2 is the current at reset and in standby, subactive, and subsleep modes while the
A/D converter is idle.
22.2.5 Watchdog Timer Characteristics
Table 22.7 Watchdog Timer Characteristics
Values
On-chip tOVF 0.2 0.4 — s *
oscillator
overflow
time
Note: * Time until an internal reset is generated after the counter counts from 0 to 255 when the
on-chip oscillator is selected
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22.2.6 Flash Memory Characteristics
Table 22.8 Flash Memory Characteristics
Values
Test
Item Symbol Condition Min. Typ. Max. Unit
Programming time (per 128 bytes)*1*2*4 tP — 7.0 200.0 ms
Erase time (per block) *1*3*6 tE — 10.0 20.0 ms
Reprogramming count NWEC 1000 10000 — Times
Programming Wait time after setting SWE x 1 — — µs
bit*1
Wait time after setting PSU y 50 — — µs
bit*1
Wait time after setting P bit z1 1≤n≤6 28 30 32 µs
1
** 4
z2 7 ≤ n ≤ 1000 198 200 202 µs
z3 Additional- 8 10 12 µs
programming
Wait time after clearing P α 5 — — µs
bit*1
Wait time after clearing PSU β 5 — — µs
bit*1
Wait time after setting PV γ 4 — — µs
bit*1
Wait time after dummy ε 2 — — µs
write*1
Wait time after clearing PV η 2 — — µs
bit*1
Wait time after clearing SWE θ 100 — — µs
bit*1
Maximum programming N — — 1000 Times
count *1*4*5
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Values
Test
Erasing Wait time after setting SWE x 1 — — µs
bit*1
Wait time after setting ESU y 100 — — µs
bit*1
Wait time after setting E z 10 — 100 ms
bit*1*6
Wait time after clearing E α 10 — — µs
bit*1
Wait time after clearing ESU β 10 — — µs
bit*1
Wait time after setting EV γ 20 — — µs
bit*1
Wait time after ε 2 — — µs
dummy write*1
Wait time after clearing EV η 4 — — µs
bit*1
bit*1
Maximum erase count *1*6*7 N — — 120 Times
Notes: 1. Make the time settings in accordance with the program/erase algorithms.
2. The programming time for 128 bytes. (Indicates the total time for which the P bit in flash
memory control register 1 (FLMCR1) is set. The program-verify time is not included.)
3. The time required to erase one block. (Indicates the time for which the E bit in flash
memory control register 1 (FLMCR1) is set. The erase-verify time is not included.)
4. Programming time maximum value (tP(max.)) = wait time after P bit setting (z) ×
maximum programming count (N)
5. Set the maximum programming count (N) according to the actual set values of z1, z2,
and z3 so that it does not exceed the programming time maximum value (tP(max.)). The
wait time after setting P bit (z1, z2) should be changed as follows according to the value
of the programming count (n).
Programming count (n)
1≤n≤6 z1 = 30 µs
7 ≤ n ≤ 1000 z2 = 200 µs
6. Erase time maximum value (tE(max.)) = wait time after E bit setting (z) × maximum
erase count (N)
7. Set the maximum erase count (N) according to the actual set value of (z) so that it does
not exceed the erase time maximum value (tE(max.)).
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22.2.7 Power-Supply-Voltage Detection Circuit Characteristics
Table 22.9 Power-Supply-Voltage Detection Circuit Characteristics
VSS = 0.0 V, Ta = -20 to +75°C/-40 to +85°C, unless otherwise indicated.
Values
Test
Power-supply falling detection Vint (D) LVDSEL = 0 3.4 3.7 — V
voltage
Power-supply rising detection Vint (U) LVDSEL = 0 — 4.0 4.4 V
voltage
1
Reset detection voltage 1* Vreset1 LVDSEL = 0 — 2.3 2.6 V
2
Reset detection voltage 2* Vreset2 LVDSEL = 1 3.3 3.6 3.9 V
Lower-limit voltage of LVDR VLVDRmin 1.0 — — V
operation
Notes: 1. This voltage should be used when the falling and rising voltage detection function is
used.
2. Select the low-voltage reset 2 when only the low-voltage detection reset is used.
22.2.8 LVDI External Input Voltage Detection Circuit Characteristics
Table 22.10 LVDI External Input Voltage Detection Circuit Characteristics
Vcc = 4.5 to 5.5 V, AVcc = 4.5 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75°C/-40 to +85°C
Values
Test
ExtD/ExtU input detection voltage Vexd 1.0 1.15 1.30 V
ExtD/ExtU input voltage range VextD/VextU VextD > VextU −0.3  Lower V
voltage
of AVcc
+ 0.3 or
Vcc +
0.3
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22.2.9 Power-On Reset Circuit Characteristics
Table 22.11 Power-On Reset Circuit Characteristics
Values
Test
Item Symbol Condition Min. Typ. Max Unit
Pull-up resistance of RES pin RRES 100 150 — kΩ
Power-on reset start voltage* Vpor — — 100 mV
Note: * The power-supply voltage (Vcc) must fall below Vpor = 100 mV and then rise after
charge of the RES pin is removed completely. In order to remove charge of the RES
pin, it is recommended that the diode be placed in the Vcc side. If the power-supply
voltage (Vcc) rises from the point over 100 mV, a power-on reset may not occur.
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22.3 Electrical Characteristics (F-ZTAT™ 3.3-V Version)
22.3.1 Power Supply Voltage and Operating Ranges
(1) Power Supply Voltage and Oscillation Frequency Range
φosc (MHz) φw (kHz)

16.0
32.768
4.0
3.0 3.6 VCC (V) 3.0 3.6 VCC (V)
• AVCC = 3.0 to 3.6 V • AVCC = 3.0 to 3.6 V

• Active mode • All operating modes
• Sleep mode
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(2) Power Supply Voltage and Operating Frequency Range
φ (MHz) φSUB (kHz)

16.0
16.384
8.192
4.0 4.096
3.0 3.6 VCC (V) 3.0 3.6 VCC (V)

• AVCC = 3.0 to 3.6 V • AVCC = 3.0 to 3.6 V
• Active mode • Subactive mode
• Sleep mode • Subsleep mode
(When MA2 in SYSCR2 = 0)
φ (kHz)
2500
78.125
3.0 3.6 VCC (V)

• AVCC = 3.0 to 3.6 V
• Active mode
• Sleep mode
(When MA2 in SYSCR2 = 1)
(3) Analog Power Supply Voltage and A/D Converter Accuracy Guaranteed Range
φ (MHz)
16.0
4.0
3.0 3.6 AVCC (V)
• VCC = 3.0 to 3.6 V

• Active mode
• Sleep mode
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22.3.2 DC Characteristics
Values
Input high VIH RES, NMI, VCC × 0.9 — VCC + 0.3 V
IRQ0 to IRQ3,
ADTRG, TMIB1,
TMRIV,
TMCIV, FTIOA0
to FTIOD0,
FTIOA1 to
FTIOD1, SCK3,
SCK3_2, TRGV
RXD, RXD_2, VCC × 0.8 — VCC + 0.3 V
SCL, SDA,
P10 to P12,
P14 to P17,
P20 to P24,
P30 to P37,
P50 to P57,
P60 to P67,
P70 to P72
P74 to P76,
P85 to P87,
PC0, PC1
PB0 to PB7 AVCC = 3.0 to 3.6 V AVCC × 0.8 — AVCC + 0.3 V
OSC1 VCC – 0.3 — VCC + 0.3 V
Input low VIL RES, NMI, –0.3 — VCC × 0.1 V
IRQ0 to IRQ3,
ADTRG, TMIB1,
TMRIV,
TMCIV, FTIOA0
to FTIOD0,
FTIOA1 to
FTIOD1, SCK3,
SCK3_2, TRGV
Note: Connect the TEST pin to Vss.
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Values
Input low VIL RXD, RXD_2, –0.3 — VCC × 0.2 V
voltage SCL, SDA,
P10 to P12,
P14 to P17,
P20 to P24,
P30 to P37,
P50 to P57,
P60 to P67,
P70 to P72,
P74 to P76,
P85 to P87,
PC0, PC1
PB0 to PB7 AVCC = 3.0 to 3.6 V –0.3 — AVCC × 0.2 V
OSC1 –0.3 — 0.3 V
Output VOH P10 to P12, –IOH = 1.5 mA VCC – 1.0 — — V
high P14 to P17,
voltage P20 to P24,
P30 to P37,
P50 to P55, –IOH = 0.1 mA VCC – 0.5 — —
P60 to P67,
P70 to P72,
P74 to P76,
P85 to P87,
PC0, PC1
P56, P57 –IOH = 0.1 mA VCC – 2.0 — — V
Output VOL P10 to P12, IOL = 1.6 mA — — 0.6 V
low P14 to P17,
voltage P20 to P24,
P30 to P37,
P50 to P57, IOL = 0.4 mA — — 0.4
P70 to P72,
P74 to P76,
P85 to P87
PC0, PC1
P60 to P67 IOL = 20.0 mA — — 1.5 V
IOL = 10.0 mA — — 1.0
IOL = 1.6 mA — — 0.4
IOL = 0.4 mA — — 0.4
SCL, SDA IOL = 6.0 mA — — 0.6
IOL = 3.0 mA — — 0.4
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Values
Item Symbol Applicable Pins Test Condition Min Typ Max Unit Notes
Input/ | IIL | OSC1, TMIB1, VIN = 0.5 V to — — 1.0 µA
output RES, NMI, (VCC – 0.5 V)
leakage WKP0 to WKP5,
current IRQ0 to IRQ3,
ADTRG, TRGV,
TMRIV, TMCIV,
FTIOA0 to
FTIOD0, FTIOA1
to FTIOD1 RXD,
SCK3, RXD_2,
SCK3_2, SCL,
SDA
P10 to P12, VIN = 0.5 V to — — 1.0 µA
P14 to P17, (VCC – 0.5 V)
P20 to P24,
P30 to P37,
P50 to P57,
P60 to P67,
P70 to P72,
P74 to P76,
P85 to P87,
PC0, PC1
PB0 to PB7 VIN = 0.5 V to — — 1.0 µA
(AVCC – 0.5 V)
Pull-up –Ip P10 to P12, VCC = 3.3 V, — 60.0 — µA
MOS P14 to P17, VIN = 0.0 V
current P50 to P55
Input Cin All input pins f = 4 MHz, — — 15.0 pF
capaci- except power VIN = 0.0 V,
tance supply pins Ta = 25°C
Active IOPE1 VCC Active mode 1 — 15.0 22.0 mA *
mode VCC = 3.3 V,
current fOSC = 16 MHz
consump- Active mode 1 — 11.0 — *
tion VCC = 3.3 V, Reference
fOSC = 10 MHz value
IOPE2 VCC Active mode 2 — 2.8 4.0 mA *
VCC = 3.3 V,
fOSC = 16 MHz
Active mode 2 — 2.5 — *
fOSC = 10 MHz value
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Values
Sleep ISLEEP1 VCC Sleep mode 1 — 9.0 14.0 mA *
mode VCC = 3.3 V,
current Sleep mode 1 — 6.5 — *
fOSC = 10 MHz value
ISLEEP2 VCC Sleep mode 2 — 2.2 3.5 mA *
VCC = 3.3 V,
fOSC = 16 MHz
Sleep mode 2 — 2.0 — *
fOSC = 10 MHz value
Subactive ISUB VCC VCC = 3.3 V — 95.0 145.0 µA *
mode 32-kHz crystal
supply resonator
VCC = 3.3 V — 85.0 — *
32-kHz crystal Reference
resonator value
(φSUB = φW/8)
Subsleep ISUBSP VCC VCC = 3.3 V — 85.0 140.0 µA *
mode 32-kHz crystal
supply resonator
Standby ISTBY VCC 32-kHz crystal — — 135.0 µA *
mode resonator not
supply used
current
RAM data VRAM VCC 2.0 — — V
retention
voltage
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Note: * Pin states during supply current measurement are given below (excluding current in the
pull-up MOS transistors and output buffers).
Mode RES Pin Internal State Other Pins Oscillator Pins
Active mode 1 VCC Operates VCC Main clock:
ceramic or crystal
oscillator
Active mode 2 Operates Subclock:
(φOSC/64) Pin X1 = VSS
Sleep mode 1 VCC Only timers operate VCC
Sleep mode 2 Only timers operate
(φOSC/64)
Subactive mode VCC Operates VCC Main clock:
ceramic or crystal
oscillator
Subsleep mode VCC Only timers operate VCC Subclock:
crystal resonator
Standby mode VCC CPU and timers VCC Main clock:
both stop ceramic or crystal
oscillator
Subclock:
Pin X1 = VSS
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Applicable Values
Item Symbol Pins Test Condition Min. Typ. Max. Unit
Permissible output IOL Output pins — — 2.0 mA
low current (per pin) except port 6,
SCL, and SDA
Port 6 — — 20.0
Permissible output ∑IOL Output pins — — 40.0 mA
low current (total) except port 6,
SCL, and SDA
Port 6, SCL, and — — 80.0
SDA
Permissible output –IOH All output pins — — 5.0 mA
high current (per pin)
Permissible output –∑IOH All output pins — — 50.0 mA
high current (total)
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22.3.3 AC Characteristics
Table 22.13 AC Characteristics
Values
System clock fOSC OSC1, 4.0 — 16.0 MHz *1
oscillation OSC2
frequency
System clock (φ) tcyc 1 — 64 tOSC *2
cycle time — — 12.8 µs
Subclock fW X1, X2 — 32.768 — kHz
oscillation
frequency
Watch clock (φW) tW X1, X2 — 30.5 — µs
cycle time
Subclock (φSUB) tsubcyc 2 — 8 tW *2
cycle time
Instruction cycle 2 — — tcyc
time tsubcyc
(crystal resonator)
(ceramic resonator)
Oscillation trc — — 500 µs
stabilization time
(on-chip oscillator)
Oscillation trcx X1, X2 — — 2.0 s
stabilization time
External clock high tCPH OSC1 23.8 — — ns Figure 22.1
width
External clock low tCPL OSC1 23.8 — — ns
width
External clock rise tCPr OSC1 — — 15.0 ns
time
External clock fall tCPf OSC1 — — 15.0 ns
time
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Values
RES pin low tREL RES At power-on and in trc — — ms Figure 22.2
width modes other than
those below
In active mode and 2500 — — ns
sleep mode
Input pin high tIH NMI, TMIB1, 2 — — tcyc Figure 22.3
width IRQ0 to tsubcyc
IRQ3,
WKP0 to
WKP5,
TMCIV,
TMRIV,
TRGV,
ADTRG,
FTIOA0 to
FTIOD0,
FTIOA1 to
FTIOD1
Input pin low tIL NMI, TMIB1, 2 — — tcyc
width IRQ0 to tsubcyc
IRQ3,
WKP0 to
WKP5,
TMCIV,
TMRIV,
TRGV,
ADTRG,
FTIOA0 to
FTIOD0,
FTIOA1 to
FTIOD1
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Values
On-chip oscillator fRC Vcc = 3.3 V 19.70 20.00 20.30 MHz
oscillation Ta = 25°C
frequency FSEL= 1
VCLSEL= 0
FSEL = 1, 19.40 20.00 20.60
Ta = -20 to +75°C,
VCLSEL = 0
FSEL = 1, 19.2 20.0 20.8
Ta = -40 to 85°C,
VCLSEL = 0
Vcc = 3.3 V, 15.76 16.00 16.24
Ta = 25°C,
FSEL = 0,
VCLSEL = 0
FSEL = 0, 15.52 16.0 16.48
Ta = -20 to +75°C
VCLSEL = 0
FSEL = 0, 15.36 16.0 16.64
Ta = -40 to +85°C,
VCLSEL = 0
Notes: 1. When an external clock is input, the minimum frequency of the external clock oscillator
is 4.0 MHz.
2. Determined by MA2 to MA0, SA1, and SA0 in system control register 2 (SYSCR2).
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2
Table 22.14 I C Bus Interface Timing
Values
Test Reference
Item Symbol Condition Min. Typ. Max. Unit Figure
SCL input cycle time tSCL 12tcyc + 600 — — ns Figure 22.4
SCL input high width tSCLH 3tcyc + 300 — — ns
SCL input low width tSCLL 5tcyc + 300 — — ns
SCL and SDA input tSf — — 300 ns
fall time
SCL and SDA input tSP — — 1tcyc ns
spike pulse removal
time
SDA input bus-free tBUF 5tcyc — — ns
time
Start condition input tSTAH 3tcyc — — ns
hold time
Repeated start tSTAS 3tcyc — — ns
condition input setup
time
Setup time for stop tSTOS 3tcyc — — ns
condition input
Data-input setup time tSDAS 1tcyc+20 — — ns
Data-input hold time tSDAH 0 — — ns
Capacitive load of cb 0 — 400 pF
SCL and SDA
SCL and SDA output tSf — — 250 ns
fall time
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Table 22.15 Serial Communication Interface (SCI) Timing
Values
Input Asynchro- tScyc SCK3 4 — — tcyc Figure 22.5
clock nous
cycle Clock 6 — —
synchro-
nous
Input clock pulse tSCKW SCK3 0.4 — 0.6 tScyc
width
Transmit data delay tTXD TXD — — 1 tcyc Figure 22.6
time (clock
synchronous)
Receive data setup tRXS RXD 50.0 — — ns
time (clock
synchronous)
Receive data hold tRXH RXD 50.0 — — ns
time (clock
synchronous)
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22.3.4 A/D Converter Characteristics
Table 22.16 A/D Converter Characteristics
Values
Analog power supply AVCC AVCC 3.0 VCC 3.6 V *1
voltage
Analog input voltage AVIN AN0 to VSS – 0.3 — AVCC + 0.3 V
AN7
Analog power supply AIOPE AVCC AVCC = 3.6 V — — 2.0 mA
current fOSC =
16 MHz
AISTOP1 AVCC — 50 — µA *2
Reference
value
AISTOP2 AVCC — — 5.0 µA *3
Analog input CAIN AN0 to — — 30.0 pF
capacitance AN7
Permissible signal RAIN AN0 to — — 5.0 kΩ
source impedance AN7
Resolution 10 10 10 bit
(data length)
(single mode) 3.6 V
Notes: 1. Set AVCC = VCC when the A/D converter is not used.
2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle.
3. AISTOP2 is the current at reset and in standby, subactive, and subsleep modes while the
A/D converter is idle.
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22.3.5 Watchdog Timer Characteristics
Table 22.17 Watchdog Timer Characteristics
Values
On-chip tOVF 0.2 0.4 — s *
oscillator
overflow
time
Note: * Time until an internal reset is generated after the counter counts from 0 to 255 when the
on-chip oscillator is selected
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22.3.6 Flash Memory Characteristics
Table 22.18 Flash Memory Characteristics
Values
Test
Programming time (per 128 bytes)*1*2*4 tP — 7.0 200.0 ms
Erase time (per block) *1*3*6 tE — 10.0 20.0 ms
Reprogramming count NWEC 1000 10000 — Times
Programming Wait time after setting SWE x 1 — — µs
bit*1
Wait time after setting PSU y 50 — — µs
bit*1
Wait time after setting P bit z1 1≤n≤6 28 30 32 µs
1
** 4
z2 7 ≤ n ≤ 1000 198 200 202 µs
z3 Additional- 8 10 12 µs
programming
Wait time after clearing P α 5 — — µs
bit*1
Wait time after clearing PSU β 5 — — µs
bit*1
Wait time after setting PV γ 4 — — µs
bit*1
Wait time after dummy ε 2 — — µs
write*1
Wait time after clearing PV η 2 — — µs
bit*1
bit*1
Maximum programming N — — 1000 Times
count *1*4*5
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Values
Test
Erasing Wait time after setting SWE x 1 — — µs
bit*1
Wait time after setting ESU y 100 — — µs
bit*1
Wait time after setting E z 10 — 100 ms
bit*1*6
Wait time after clearing E α 10 — — µs
bit*1
Wait time after clearing ESU β 10 — — µs
bit*1
Wait time after setting EV γ 20 — — µs
bit*1
Wait time after ε 2 — — µs
dummy write*1
Wait time after clearing EV η 4 — — µs
bit*1
bit*1
Maximum erase count *1*6*7 N — — 120 Times
Notes: 1. Make the time settings in accordance with the program/erase algorithms.
2. The programming time for 128 bytes. (Indicates the total time for which the P bit in flash
memory control register 1 (FLMCR1) is set. The program-verify time is not included.)
3. The time required to erase one block. (Indicates the time for which the E bit in flash
memory control register 1 (FLMCR1) is set. The erase-verify time is not included.)
4. Programming time maximum value (tP(max.)) = wait time after P bit setting (z) ×
maximum programming count (N)
5. Set the maximum programming count (N) according to the actual set values of z1, z2,
and z3 so that it does not exceed the programming time maximum value (tP(max.)). The
wait time after setting P bit (z1, z2) should be changed as follows according to the value
of the programming count (n).
Programming count (n)
1≤n≤6 z1 = 30 µs
7 ≤ n ≤ 1000 z2 = 200 µs
6. Erase time maximum value (tE(max.)) = wait time after E bit setting (z) × maximum
erase count (N)
7. Set the maximum erase count (N) according to the actual set value of (z) so that it does
not exceed the erase time maximum value (tE(max.)).
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22.3.7 Power-Supply-Voltage Detection Circuit Characteristics
Table 22.19 Power-Supply-Voltage Detection Circuit Characteristics
Values
Item Symbol Min. Typ. Max. Unit
Power-supply falling detection Vint (D) 2.8 2.9 3.05 V
voltage
Power-supply rising detection Vint (U) 2.9 3.0 3.15 V
voltage
Reset detection voltage 1* Vreset1 — 2.3 2.6 V
Lower-limit voltage of LVDR VLVDRmin 1.0 — — V
operation
Note: * This voltage should be used when the falling and rising voltage detection function is
used.
22.3.8 LVDI External Input Voltage Detection Circuit Characteristics
Table 22.20 LVDI External Input Voltage Detection Circuit Characteristics
Vcc = 3.0 to 3.6 V, AVcc = 3.0 to 3.6 V, VSS = 0.0 V, Ta = -20 to +75°C/-40 to +85°C
Values
Test
ExtD/ExtU input detection voltage Vexd 0.95 1.15 1.35 V
ExtD/ExtU input voltage range VextD/VextU VextD > VextU −0.3  Lower V
voltage
of AVcc
+ 0.3 or
Vcc +
0.3
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22.3.9 Power-On Reset Circuit Characteristics
Table 22.21 Power-On Reset Circuit Characteristics
Values
Test
Item Symbol Condition Min. Typ. Max Unit
Pull-up resistance of RES pin RRES 100 150 — kΩ
Power-on reset start voltage* Vpor — — 100 mV
Note: * The power-supply voltage (Vcc) must fall below Vpor = 100 mV and then rise after
charge of the RES pin is removed completely. In order to remove charge of the RES
pin, it is recommended that the diode be placed in the Vcc side. If the power-supply
voltage (Vcc) rises from the point over 100 mV, a power-on reset may not occur.
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22.4 Operation Timing
t OSC
VIH
OSC1
VIL
t CPH t CPL
t CPr t CPf
Figure 22.1 System Clock Input Timing
VCC VCC × 0.7
OSC1
tREL
RES VIL
VIL
tREL
Figure 22.2 RES Low Width Timing
NMI
IRQ0 to IRQ3 VIH
WKP0 to WKP5
ADTRG VIL
FTIOA0 to FTIOD0,
FTIOA1 to FTIOD1,
TMCIV, TMRIV t IL t IH
TRGV
Figure 22.3 Input Timing
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REJ09B0216-0300
VIH
SDA
VIL
tBUF
tSTAH tSCLH tSP tSTOS
tSTAS
SCL
P* S* Sr* P*
tSCLL
tSf tSr tSDAS
tSCL
tSDAH
Note: * S, P, and Sr represent the following:

S: Start condition
P: Stop condition
Sr: Retransmission start condition
2
Figure 22.4 I C Bus Interface Input/Output Timing
t SCKW
SCK3
t Scyc
Figure 22.5 SCK3 Input Clock Timing
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REJ09B0216-0300
t Scyc
VIH or VOH *
SCK3 VIL or VOL *
t TXD
*
TXD VOH
(transmit data) *
VOL
t RXS
t RXH
RXD
(receive data)
Note: * Output timing reference levels

Output high: V OH= 2.0 V
Output low: V OL= 0.8 V
Load conditions are shown in figure 22.7.
Figure 22.6 SCI Input/Output Timing in Clock Synchronous Mode
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22.5 Output Load Condition
VCC
2.4 kΩ
LSI output pin
30 pF 12 k Ω
Figure 22.7 Output Load Circuit
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Appendix
Appendix A Instruction Set
A.1 Instruction List

Condition Code
Symbol Description
Rd General destination register
Rs General source register
Rn General register
ERd General destination register (address register or 32-bit register)
ERs General source register (address register or 32-bit register)
ERn General register (32-bit register)
(EAd) Destination operand
(EAs) Source operand
PC Program counter
SP Stack pointer
CCR Condition-code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (overflow) flag in CCR
C C (carry) flag in CCR
disp Displacement
→ Transfer from the operand on the left to the operand on the right, or transition from
the state on the left to the state on the right
+ Addition of the operands on both sides
– Subtraction of the operand on the right from the operand on the left
× Multiplication of the operands on both sides
÷ Division of the operand on the left by the operand on the right
∧ Logical AND of the operands on both sides
∨ Logical OR of the operands on both sides
⊕ Logical exclusive OR of the operands on both sides
¬ NOT (logical complement)
( ), < > Contents of operand
Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers
(R0 to R7 and E0 to E7).
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Appendix
Condition Code Notation (cont)
Symbol Description
Changed according to execution result
↔
* Undetermined (no guaranteed value)

0 Cleared to 0
1 Set to 1
— Not affected by execution of the instruction
∆ Varies depending on conditions, described in notes
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Appendix
Table A.1 Instruction Set
1. Data Transfer Instructions

Addressing Mode and No. of
Instruction Length (bytes) States*1
@–ERn/@ERn+
Condition Code
Operand Size
Mnemonic Operation
@(d, ERn)
Advanced
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
—
I H N Z V C
#xx:8 → Rd8
↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔
MOV MOV.B #xx:8, Rd B 2 — — 0 — 2
MOV.B Rs, Rd B 2 Rs8 → Rd8 — — 0 — 2
MOV.B @ERs, Rd B 2 @ERs → Rd8 — — 0 — 4
MOV.B @(d:16, ERs), Rd B 4 @(d:16, ERs) → Rd8 — — 0 — 6
MOV.B @(d:24, ERs), Rd B 8 @(d:24, ERs) → Rd8 — — 0 — 10
MOV.B @ERs+, Rd B 2 @ERs → Rd8 — — 0 — 6
ERs32+1 → ERs32
@aa:8 → Rd8
↔ ↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔ ↔
MOV.B @aa:8, Rd B 2 — — 0 — 4
MOV.B @aa:16, Rd B 4 @aa:16 → Rd8 — — 0 — 6
MOV.B @aa:24, Rd B 6 @aa:24 → Rd8 — — 0 — 8
MOV.B Rs, @ERd B 2 Rs8 → @ERd — — 0 — 4
MOV.B Rs, @(d:16, ERd) B 4 Rs8 → @(d:16, ERd) — — 0 — 6
MOV.B Rs, @(d:24, ERd) B 8 Rs8 → @(d:24, ERd) — — 0 — 10
MOV.B Rs, @–ERd B 2 ERd32–1 → ERd32 — — 0 — 6
Rs8 → @ERd
Rs8 → @aa:8
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
MOV.B Rs, @aa:8 B 2 — — 0 — 4
MOV.B Rs, @aa:16 B 4 Rs8 → @aa:16 — — 0 — 6
MOV.B Rs, @aa:24 B 6 Rs8 → @aa:24 — — 0 — 8
MOV.W #xx:16, Rd W 4 #xx:16 → Rd16 — — 0 — 4
MOV.W Rs, Rd W 2 Rs16 → Rd16 — — 0 — 2
MOV.W @ERs, Rd W 2 @ERs → Rd16 — — 0 — 4
MOV.W @(d:16, ERs), Rd W 4 @(d:16, ERs) → Rd16 — — 0 — 6
MOV.W @(d:24, ERs), Rd W 8 @(d:24, ERs) → Rd16 — — 0 — 10
MOV.W @ERs+, Rd W 2 @ERs → Rd16 — — 0 — 6
ERs32+2 → @ERd32
@aa:16 → Rd16
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
MOV.W @aa:16, Rd W 4 — — 0 — 6
MOV.W @aa:24, Rd W 6 @aa:24 → Rd16 — — 0 — 8
MOV.W Rs, @ERd W 2 Rs16 → @ERd — — 0 — 4
MOV.W Rs, @(d:16, ERd) W 4 Rs16 → @(d:16, ERd) — — 0 — 6
MOV.W Rs, @(d:24, ERd) W 8 Rs16 → @(d:24, ERd) — — 0 — 10
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Appendix

@–ERn/@ERn+
Condition Code
Operand Size
Mnemonic Operation
@(d, ERn)
Advanced
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
—
I H N Z V C
ERd32–2 → ERd32
↔
↔
MOV MOV.W Rs, @–ERd W 2 — — 0 — 6
Rs16 → @ERd
Rs16 → @aa:16
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
MOV.W Rs, @aa:16 W 4 — — 0 — 6
MOV.W Rs, @aa:24 W 6 Rs16 → @aa:24 — — 0 — 8
MOV.L #xx:32, Rd L 6 #xx:32 → Rd32 — — 0 — 6
MOV.L ERs, ERd L 2 ERs32 → ERd32 — — 0 — 2
MOV.L @ERs, ERd L 4 @ERs → ERd32 — — 0 — 8
MOV.L @(d:16, ERs), ERd L 6 @(d:16, ERs) → ERd32 — — 0 — 10
MOV.L @(d:24, ERs), ERd L 10 @(d:24, ERs) → ERd32 — — 0 — 14
MOV.L @ERs+, ERd L 4 @ERs → ERd32 — — 0 — 10
ERs32+4 → ERs32
@aa:16 → ERd32
↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔
MOV.L @aa:16, ERd L 6 — — 0 — 10
MOV.L @aa:24, ERd L 8 @aa:24 → ERd32 — — 0 — 12
MOV.L ERs, @ERd L 4 ERs32 → @ERd — — 0 — 8
MOV.L ERs, @(d:16, ERd) L 6 ERs32 → @(d:16, ERd) — — 0 — 10
MOV.L ERs, @(d:24, ERd) L 10 ERs32 → @(d:24, ERd) — — 0 — 14
MOV.L ERs, @–ERd L 4 ERd32–4 → ERd32 — — 0 — 10
ERs32 → @ERd
ERs32 → @aa:16
↔ ↔ ↔
↔ ↔ ↔
MOV.L ERs, @aa:16 L 6 — — 0 — 10
MOV.L ERs, @aa:24 L 8 ERs32 → @aa:24 — — 0 — 12
POP POP.W Rn W 2 @SP → Rn16 — — 0 — 6
SP+2 → SP
4 @SP → ERn32
↔
POP.L ERn L — — ↔ 0 — 10
SP+4 → SP
2 SP–2 → SP
↔
↔
PUSH PUSH.W Rn W — — 0 — 6
Rn16 → @SP
4 SP–4 → SP
↔
↔
PUSH.L ERn L — — 0 — 10
ERn32 → @SP
MOVFPE MOVFPE @aa:16, Rd B 4 Cannot be used in Cannot be used in

this LSI this LSI
MOVTPE MOVTPE Rs, @aa:16 B 4 Cannot be used in Cannot be used in

this LSI this LSI
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Appendix
2. Arithmetic Instructions
@–ERn/@ERn+
Condition Code
Operand Size
Mnemonic Operation
@(d, ERn)
Advanced
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
—
I H N Z V C
Rd8+#xx:8 → Rd8
↔ ↔
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
ADD ADD.B #xx:8, Rd B 2 — 2
ADD.B Rs, Rd B 2 Rd8+Rs8 → Rd8 — 2
ADD.W #xx:16, Rd W 4 Rd16+#xx:16 → Rd16 — (1) 4
ADD.W Rs, Rd W 2 Rd16+Rs16 → Rd16 — (1) 2
ADD.L #xx:32, ERd L 6 ERd32+#xx:32 → — (2) 6
ERd32
ERd32+ERs32 →
↔
↔
↔
↔
ADD.L ERs, ERd L 2 — (2) 2
ERd32
Rd8+#xx:8 +C → Rd8
↔ ↔
↔ ↔
↔ ↔
↔ ↔
ADDX ADDX.B #xx:8, Rd B 2 — (3) 2
ADDX.B Rs, Rd B 2 Rd8+Rs8 +C → Rd8 — (3) 2
ADDS ADDS.L #1, ERd L 2 ERd32+1 → ERd32 — — — — — — 2
ADDS.L #2, ERd L 2 ERd32+2 → ERd32 — — — — — — 2
ADDS.L #4, ERd L 2 ERd32+4 → ERd32 — — — — — — 2
Rd8+1 → Rd8
↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
INC INC.B Rd B 2 — — — 2
INC.W #1, Rd W 2 Rd16+1 → Rd16 — — — 2
INC.W #2, Rd W 2 Rd16+2 → Rd16 — — — 2
INC.L #1, ERd L 2 ERd32+1 → ERd32 — — — 2
INC.L #2, ERd L 2 ERd32+2 → ERd32 — — — 2
↔
DAA DAA Rd B 2 Rd8 decimal adjust — * * 2
→ Rd8
Rd8–Rs8 → Rd8
↔
↔ ↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔ ↔
SUB SUB.B Rs, Rd B 2 — 2
SUB.W #xx:16, Rd W 4 Rd16–#xx:16 → Rd16 — (1) 4
SUB.W Rs, Rd W 2 Rd16–Rs16 → Rd16 — (1) 2
SUB.L #xx:32, ERd L 6 ERd32–#xx:32 → ERd32 — (2) 6
SUB.L ERs, ERd L 2 ERd32–ERs32 → ERd32 — (2) 2
Rd8–#xx:8–C → Rd8
↔ ↔
SUBX SUBX.B #xx:8, Rd B 2 — (3) 2

SUBX.B Rs, Rd B 2 Rd8–Rs8–C → Rd8 — (3) 2
SUBS SUBS.L #1, ERd L 2 ERd32–1 → ERd32 — — — — — — 2
SUBS.L #2, ERd L 2 ERd32–2 → ERd32 — — — — — — 2
SUBS.L #4, ERd L 2 ERd32–4 → ERd32 — — — — — — 2
Rd8–1 → Rd8
↔ ↔ ↔
↔ ↔ ↔
↔ ↔ ↔
DEC DEC.B Rd B 2 — — — 2
DEC.W #1, Rd W 2 Rd16–1 → Rd16 — — — 2
DEC.W #2, Rd W 2 Rd16–2 → Rd16 — — — 2
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Appendix

@–ERn/@ERn+
Condition Code
Operand Size
Mnemonic Operation
@(d, ERn)
Advanced
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
—
I H N Z V C
ERd32–1 → ERd32
↔ ↔ ↔
↔ ↔ ↔
↔ ↔
DEC DEC.L #1, ERd L 2 — — — 2
DEC.L #2, ERd L 2 ERd32–2 → ERd32 — — — 2
DAS DAS.Rd B 2 Rd8 decimal adjust — * * — 2
→ Rd8
MULXU MULXU. B Rs, Rd B 2 Rd8 × Rs8 → Rd16 — — — — — — 14

(unsigned multiplication)
MULXU. W Rs, ERd W 2 Rd16 × Rs16 → ERd32 — — — — — — 22
(unsigned multiplication)
Rd8 × Rs8 → Rd16
↔
↔
MULXS MULXS. B Rs, Rd B 4 — — — — 16
(signed multiplication)
Rd16 × Rs16 → ERd32
↔
↔
MULXS. W Rs, ERd W 4 — — — — 24
(signed multiplication)
DIVXU DIVXU. B Rs, Rd B 2 Rd16 ÷ Rs8 → Rd16 — — (6) (7) — — 14

(RdH: remainder,
RdL: quotient)
(unsigned division)
DIVXU. W Rs, ERd W 2 ERd32 ÷ Rs16 → ERd32 — — (6) (7) — — 22

(Ed: remainder,
Rd: quotient)
(unsigned division)
DIVXS DIVXS. B Rs, Rd B 4 Rd16 ÷ Rs8 → Rd16 — — (8) (7) — — 16

(RdH: remainder,
RdL: quotient)
(signed division)
DIVXS. W Rs, ERd W 4 ERd32 ÷ Rs16 → ERd32 — — (8) (7) — — 24

(Ed: remainder,
Rd: quotient)
(signed division)
↔ ↔
↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔
CMP CMP.B #xx:8, Rd B 2 Rd8–#xx:8 — 2

CMP.B Rs, Rd B 2 Rd8–Rs8 — 2
CMP.W #xx:16, Rd W 4 Rd16–#xx:16 — (1) 4
CMP.W Rs, Rd W 2 Rd16–Rs16 — (1) 2
CMP.L #xx:32, ERd L 6 ERd32–#xx:32 — (2) 4
CMP.L ERs, ERd L 2 ERd32–ERs32 — (2) 2
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Appendix

@–ERn/@ERn+
Condition Code
Operand Size
Mnemonic Operation
@(d, ERn)
Advanced
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
—
I H N Z V C
0–Rd8 → Rd8
↔ ↔ ↔
↔ ↔ ↔
↔ ↔ ↔ ↔
↔ ↔ ↔
↔ ↔ ↔
NEG NEG.B Rd B 2 — 2
NEG.W Rd W 2 0–Rd16 → Rd16 — 2
NEG.L ERd L 2 0–ERd32 → ERd32 — 2
EXTU EXTU.W Rd W 2 0 → (<bits 15 to 8> — — 0 0 — 2
of Rd16)
0 → (<bits 31 to 16>
↔
EXTU.L ERd L 2 — — 0 0 — 2
of ERd32)
(<bit 7> of Rd16) →
↔
↔
EXTS EXTS.W Rd W 2 — — 0 — 2
(<bits 15 to 8> of Rd16)
(<bit 15> of ERd32) →
↔
↔
EXTS.L ERd L 2 — — 0 — 2
(<bits 31 to 16> of
ERd32)
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Appendix
3. Logic Instructions
@–ERn/@ERn+
Condition Code
Operand Size
Mnemonic Operation
@(d, ERn)
Advanced
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
—
I H N Z V C
Rd8∧#xx:8 → Rd8
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
AND AND.B #xx:8, Rd B 2 — — 0 — 2
AND.B Rs, Rd B 2 Rd8∧Rs8 → Rd8 — — 0 — 2
AND.W #xx:16, Rd W 4 Rd16∧#xx:16 → Rd16 — — 0 — 4
AND.W Rs, Rd W 2 Rd16∧Rs16 → Rd16 — — 0 — 2
AND.L #xx:32, ERd L 6 ERd32∧#xx:32 → ERd32 — — 0 — 6
AND.L ERs, ERd L 4 ERd32∧ERs32 → ERd32 — — 0 — 4
OR OR.B #xx:8, Rd B 2 Rd8⁄#xx:8 → Rd8 — — 0 — 2
OR.B Rs, Rd B 2 Rd8⁄Rs8 → Rd8 — — 0 — 2
OR.W #xx:16, Rd W 4 Rd16⁄#xx:16 → Rd16 — — 0 — 4
OR.W Rs, Rd W 2 Rd16⁄Rs16 → Rd16 — — 0 — 2
OR.L #xx:32, ERd L 6 ERd32⁄#xx:32 → ERd32 — — 0 — 6
OR.L ERs, ERd L 4 ERd32⁄ERs32 → ERd32 — — 0 — 4
XOR XOR.B #xx:8, Rd B 2 Rd8⊕#xx:8 → Rd8 — — 0 — 2
XOR.B Rs, Rd B 2 Rd8⊕Rs8 → Rd8 — — 0 — 2
XOR.W #xx:16, Rd W 4 Rd16⊕#xx:16 → Rd16 — — 0 — 4
XOR.W Rs, Rd W 2 Rd16⊕Rs16 → Rd16 — — 0 — 2
XOR.L #xx:32, ERd L 6 ERd32⊕#xx:32 → ERd32 — — 0 — 6
XOR.L ERs, ERd L 4 ERd32⊕ERs32 → ERd32 — — 0 — 4
NOT NOT.B Rd B 2 ¬ Rd8 → Rd8 — — 0 — 2
NOT.W Rd W 2 ¬ Rd16 → Rd16 — — 0 — 2
NOT.L ERd L 2 ¬ Rd32 → Rd32 — — 0 — 2
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Appendix
4. Shift Instructions
@–ERn/@ERn+
Condition Code
Operand Size
Mnemonic Operation
@(d, ERn)
Advanced
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
—
I H N Z V C
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
SHAL SHAL.B Rd B 2 — — 2
C 0
SHAL.W Rd W 2 — — 2
SHAL.L ERd L 2 MSB LSB — — 2
SHAR SHAR.B Rd B 2 — — 0 2
C
SHAR.W Rd W 2 — — 0 2
SHAR.L ERd L 2 MSB LSB — — 0 2
SHLL SHLL.B Rd B 2 — — 0 2
C 0
SHLL.W Rd W 2 — — 0 2
SHLL.L ERd L 2 MSB LSB — — 0 2
SHLR SHLR.B Rd B 2 — — 0 2
0 C
SHLR.W Rd W 2 — — 0 2
SHLR.L ERd L 2 MSB LSB — — 0 2
ROTXL ROTXL.B Rd B 2 — — 0 2
C
ROTXL.W Rd W 2 — — 0 2
ROTXL.L ERd L 2 MSB LSB — — 0 2
ROTXR ROTXR.B Rd B 2 — — 0 2
C
ROTXR.W Rd W 2 — — 0 2
ROTXR.L ERd L 2 MSB LSB — — 0 2
ROTL ROTL.B Rd B 2 — — 0 2
C
ROTL.W Rd W 2 — — 0 2
ROTL.L ERd L 2 MSB LSB — — 0 2
ROTR ROTR.B Rd B 2 — — 0 2
C
ROTR.W Rd W 2 — — 0 2
ROTR.L ERd L 2 MSB LSB — — 0 2
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Appendix
5. Bit-Manipulation Instructions
@–ERn/@ERn+
Condition Code
Operand Size
Mnemonic Operation
@(d, ERn)
Advanced
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
—
I H N Z V C
BSET BSET #xx:3, Rd B 2 (#xx:3 of Rd8) ← 1 — — — — — — 2

BSET #xx:3, @ERd B 4 (#xx:3 of @ERd) ← 1 — — — — — — 8
BSET #xx:3, @aa:8 B 4 (#xx:3 of @aa:8) ← 1 — — — — — — 8
BSET Rn, Rd B 2 (Rn8 of Rd8) ← 1 — — — — — — 2
BSET Rn, @ERd B 4 (Rn8 of @ERd) ← 1 — — — — — — 8
BSET Rn, @aa:8 B 4 (Rn8 of @aa:8) ← 1 — — — — — — 8
BCLR BCLR #xx:3, Rd B 2 (#xx:3 of Rd8) ← 0 — — — — — — 2
BCLR #xx:3, @ERd B 4 (#xx:3 of @ERd) ← 0 — — — — — — 8
BCLR #xx:3, @aa:8 B 4 (#xx:3 of @aa:8) ← 0 — — — — — — 8
BCLR Rn, Rd B 2 (Rn8 of Rd8) ← 0 — — — — — — 2
BCLR Rn, @ERd B 4 (Rn8 of @ERd) ← 0 — — — — — — 8
BCLR Rn, @aa:8 B 4 (Rn8 of @aa:8) ← 0 — — — — — — 8
BNOT BNOT #xx:3, Rd B 2 (#xx:3 of Rd8) ← — — — — — — 2
¬ (#xx:3 of Rd8)
BNOT #xx:3, @ERd B 4 (#xx:3 of @ERd) ← — — — — — — 8
¬ (#xx:3 of @ERd)
BNOT #xx:3, @aa:8 B 4 (#xx:3 of @aa:8) ← — — — — — — 8
¬ (#xx:3 of @aa:8)
BNOT Rn, Rd B 2 (Rn8 of Rd8) ← — — — — — — 2
¬ (Rn8 of Rd8)
BNOT Rn, @ERd B 4 (Rn8 of @ERd) ← — — — — — — 8
¬ (Rn8 of @ERd)
BNOT Rn, @aa:8 B 4 (Rn8 of @aa:8) ← — — — — — — 8
¬ (Rn8 of @aa:8)
¬ (#xx:3 of Rd8) → Z
↔ ↔ ↔ ↔ ↔ ↔
BTST BTST #xx:3, Rd B 2 — — — — — 2

BTST #xx:3, @ERd B 4 ¬ (#xx:3 of @ERd) → Z — — — — — 6
BTST #xx:3, @aa:8 B 4 ¬ (#xx:3 of @aa:8) → Z — — — — — 6
BTST Rn, Rd B 2 ¬ (Rn8 of @Rd8) → Z — — — — — 2
BTST Rn, @ERd B 4 ¬ (Rn8 of @ERd) → Z — — — — — 6
BTST Rn, @aa:8 B 4 ¬ (Rn8 of @aa:8) → Z — — — — — 6
(#xx:3 of Rd8) → C
↔
BLD BLD #xx:3, Rd B 2 — — — — — 2
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Appendix

@–ERn/@ERn+
Condition Code
Operand Size
Mnemonic Operation
@(d, ERn)
Advanced
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
—
I H N Z V C
(#xx:3 of @ERd) → C
↔ ↔ ↔ ↔ ↔
BLD BLD #xx:3, @ERd B 4 — — — — — 6
BLD #xx:3, @aa:8 B 4 (#xx:3 of @aa:8) → C — — — — — 6
BILD BILD #xx:3, Rd B 2 ¬ (#xx:3 of Rd8) → C — — — — — 2
BILD #xx:3, @ERd B 4 ¬ (#xx:3 of @ERd) → C — — — — — 6
BILD #xx:3, @aa:8 B 4 ¬ (#xx:3 of @aa:8) → C — — — — — 6
BST BST #xx:3, Rd B 2 C → (#xx:3 of Rd8) — — — — — — 2
BST #xx:3, @ERd B 4 C → (#xx:3 of @ERd24) — — — — — — 8
BST #xx:3, @aa:8 B 4 C → (#xx:3 of @aa:8) — — — — — — 8
BIST BIST #xx:3, Rd B 2 ¬ C → (#xx:3 of Rd8) — — — — — — 2
BIST #xx:3, @ERd B 4 ¬ C → (#xx:3 of @ERd24) — — — — — — 8
BIST #xx:3, @aa:8 B 4 ¬ C → (#xx:3 of @aa:8) — — — — — — 8
C∧(#xx:3 of Rd8) → C
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
BAND BAND #xx:3, Rd B 2 — — — — — 2
BAND #xx:3, @ERd B 4 C∧(#xx:3 of @ERd24) → C — — — — — 6
BAND #xx:3, @aa:8 B 4 C∧(#xx:3 of @aa:8) → C — — — — — 6
BIAND BIAND #xx:3, Rd B 2 C∧ ¬ (#xx:3 of Rd8) → C — — — — — 2
BIAND #xx:3, @ERd B 4 C∧ ¬ (#xx:3 of @ERd24) → C — — — — — 6
BIAND #xx:3, @aa:8 B 4 C∧ ¬ (#xx:3 of @aa:8) → C — — — — — 6
BOR BOR #xx:3, Rd B 2 C∨(#xx:3 of Rd8) → C — — — — — 2
BOR #xx:3, @ERd B 4 C∨(#xx:3 of @ERd24) → C — — — — — 6
BOR #xx:3, @aa:8 B 4 C∨(#xx:3 of @aa:8) → C — — — — — 6
BIOR BIOR #xx:3, Rd B 2 C∨ ¬ (#xx:3 of Rd8) → C — — — — — 2
BIOR #xx:3, @ERd B 4 C∨ ¬ (#xx:3 of @ERd24) → C — — — — — 6
BIOR #xx:3, @aa:8 B 4 C∨ ¬ (#xx:3 of @aa:8) → C — — — — — 6
BXOR BXOR #xx:3, Rd B 2 C⊕(#xx:3 of Rd8) → C — — — — — 2
BXOR #xx:3, @ERd B 4 C⊕(#xx:3 of @ERd24) → C — — — — — 6
BXOR #xx:3, @aa:8 B 4 C⊕(#xx:3 of @aa:8) → C — — — — — 6
BIXOR BIXOR #xx:3, Rd B 2 C⊕ ¬ (#xx:3 of Rd8) → C — — — — — 2
BIXOR #xx:3, @ERd B 4 C⊕ ¬ (#xx:3 of @ERd24) → C — — — — — 6
BIXOR #xx:3, @aa:8 B 4 C⊕ ¬ (#xx:3 of @aa:8) → C — — — — — 6
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Appendix
6. Branching Instructions
@–ERn/@ERn+
Condition Code
Operand Size
Mnemonic Operation
@(d, ERn)
Advanced
@(d, PC)
Normal
@@aa
@ERn
@aa
Branch
#xx
Rn
—
Condition I H N Z V C
Bcc BRA d:8 (BT d:8) — 2 If condition Always — — — — — — 4

BRA d:16 (BT d:16) — 4 is true then — — — — — — 6
PC ← PC+d
BRN d:8 (BF d:8) — 2 Never — — — — — — 4
else next;
BRN d:16 (BF d:16) — 4 — — — — — — 6
BHI d:8 — 2 C∨ Z = 0 — — — — — — 4
BHI d:16 — 4 — — — — — — 6
BLS d:8 — 2 C∨ Z = 1 — — — — — — 4
BLS d:16 — 4 — — — — — — 6
BCC d:8 (BHS d:8) — 2 C=0 — — — — — — 4
BCC d:16 (BHS d:16) — 4 — — — — — — 6
BCS d:8 (BLO d:8) — 2 C=1 — — — — — — 4
BCS d:16 (BLO d:16) — 4 — — — — — — 6
BNE d:8 — 2 Z=0 — — — — — — 4
BNE d:16 — 4 — — — — — — 6
BEQ d:8 — 2 Z=1 — — — — — — 4
BEQ d:16 — 4 — — — — — — 6
BVC d:8 — 2 V=0 — — — — — — 4
BVC d:16 — 4 — — — — — — 6
BVS d:8 — 2 V=1 — — — — — — 4
BVS d:16 — 4 — — — — — — 6
BPL d:8 — 2 N=0 — — — — — — 4
BPL d:16 — 4 — — — — — — 6
BMI d:8 — 2 N=1 — — — — — — 4
BMI d:16 — 4 — — — — — — 6
BGE d:8 — 2 N⊕V = 0 — — — — — — 4
BGE d:16 — 4 — — — — — — 6
BLT d:8 — 2 N⊕V = 1 — — — — — — 4
BLT d:16 — 4 — — — — — — 6
BGT d:8 — 2 Z∨ (N⊕V) = 0 — — — — — — 4
BGT d:16 — 4 — — — — — — 6
BLE d:8 — 2 Z∨ (N⊕V) = 1 — — — — — — 4
BLE d:16 — 4 — — — — — — 6
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Appendix

@–ERn/@ERn+
Condition Code
Operand Size
Mnemonic Operation
@(d, ERn)
Advanced
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
—
I H N Z V C
JMP JMP @ERn — 2 PC ← ERn — — — — — — 4

JMP @aa:24 — 4 PC ← aa:24 — — — — — — 6
JMP @@aa:8 — 2 PC ← @aa:8 — — — — — — 8 10
BSR BSR d:8 — 2 PC → @–SP — — — — — — 6 8
PC ← PC+d:8
BSR d:16 — 4 PC → @–SP — — — — — — 8 10
PC ← PC+d:16
JSR JSR @ERn — 2 PC → @–SP — — — — — — 6 8
PC ← ERn
JSR @aa:24 — 4 PC → @–SP — — — — — — 8 10
PC ← aa:24
JSR @@aa:8 — 2 PC → @–SP — — — — — — 8 12
PC ← @aa:8
RTS RTS — 2 PC ← @SP+ — — — — — — 8 10
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Appendix
7. System Control Instructions

@–ERn/@ERn+
Condition Code
Operand Size
Mnemonic Operation
@(d, ERn)
Advanced
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
—
I H N Z V C
TRAPA TRAPA #x:2 — 2 PC → @–SP 1 — — — — — 14 16

CCR → @–SP
<vector> → PC
CCR ← @SP+
↔
↔
↔
↔
↔
↔
RTE RTE — 10
PC ← @SP+
SLEEP SLEEP — Transition to power- — — — — — — 2
down state
#xx:8 → CCR
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
LDC LDC #xx:8, CCR B 2 2
LDC Rs, CCR B 2 Rs8 → CCR 2
LDC @ERs, CCR W 4 @ERs → CCR 6
LDC @(d:16, ERs), CCR W 6 @(d:16, ERs) → CCR 8
LDC @(d:24, ERs), CCR W 10 @(d:24, ERs) → CCR 12
LDC @ERs+, CCR W 4 @ERs → CCR 8
↔
↔
↔
↔
↔
↔
ERs32+2 → ERs32
@aa:16 → CCR
↔ ↔
↔ ↔
↔ ↔
↔ ↔
↔ ↔
↔ ↔
LDC @aa:16, CCR W 6 8
LDC @aa:24, CCR W 8 @aa:24 → CCR 10
STC STC CCR, Rd B 2 CCR → Rd8 — — — — — — 2
STC CCR, @ERd W 4 CCR → @ERd — — — — — — 6
STC CCR, @(d:16, ERd) W 6 CCR → @(d:16, ERd) — — — — — — 8
STC CCR, @(d:24, ERd) W 10 CCR → @(d:24, ERd) — — — — — — 12
STC CCR, @–ERd W 4 ERd32–2 → ERd32 — — — — — — 8
CCR → @ERd
STC CCR, @aa:16 W 6 CCR → @aa:16 — — — — — — 8
STC CCR, @aa:24 W 8 CCR → @aa:24 — — — — — — 10
CCR∧#xx:8 → CCR
↔ ↔ ↔
↔ ↔ ↔
↔ ↔ ↔
↔ ↔ ↔
↔ ↔ ↔
↔ ↔ ↔
ANDC ANDC #xx:8, CCR B 2 2

ORC ORC #xx:8, CCR B 2 CCR∨#xx:8 → CCR 2
XORC XORC #xx:8, CCR B 2 CCR⊕#xx:8 → CCR 2
NOP NOP — 2 PC ← PC+2 — — — — — — 2
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Appendix
8. Block Transfer Instructions

@–ERn/@ERn+
Condition Code
Operand Size
Mnemonic Operation
@(d, ERn)
Advanced
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
—
I H N Z V C
EEPMOV EEPMOV. B — 4 if R4L ≠ 0 then — — — — — — 8+

repeat @R5 → @R6 4n*2
R5+1 → R5
R6+1 → R6
R4L–1 → R4L
until R4L=0
else next
EEPMOV. W — 4 if R4 ≠ 0 then — — — — — — 8+
repeat @R5 → @R6 4n*2
R5+1 → R5
R6+1 → R6
R4–1 → R4
until R4=0
else next
Notes: 1. The number of states in cases where the instruction code and its operands are located
in on-chip memory is shown here. For other cases see appendix A.3, Number of
Execution States.
2. n is the value set in register R4L or R4.
(1) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0.
(2) Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0.
(3) Retains its previous value when the result is zero; otherwise cleared to 0.
(4) Set to 1 when the adjustment produces a carry; otherwise retains its previous value.
(5) The number of states required for execution of an instruction that transfers data in
synchronization with the E clock is variable.
(6) Set to 1 when the divisor is negative; otherwise cleared to 0.
(7) Set to 1 when the divisor is zero; otherwise cleared to 0.
(8) Set to 1 when the quotient is negative; otherwise cleared to 0.
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A.2
Appendix
Instruction code: 1st byte 2nd byte Instruction when most significant bit of BH is 0. Table A.2
AH AL BH BL
Instruction when most significant bit of BH is 1.
REJ09B0216-0300
AL
0 1 2 3 4 5 6 7 8 9 A B C D E F
AH
Table A.2 Table A.2 Table A.2 Table A.2

0 NOP STC LDC ORC XORC ANDC LDC ADD MOV ADDX
(2) (2) (2) (2)
Table A.2 Table A.2 Table A.2 Table A.2 Table A.2 Table A.2 Table A.2 Table A.2
1 OR.B XOR.B AND.B SUB CMP SUBX
(2) (2) (2) (2) (2) (2) (2) (2)
2
MOV.B
Operation Code Map
Rev. 3.00 Sep. 10, 2007 Page 474 of 528

Operation Code Map (1)
4 BRA BRN BHI BLS BCC BCS BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE
Table A.2
5 MULXU DIVXU MULXU DIVXU RTS BSR RTE TRAPA JMP BSR JSR
(2)
BST
6 OR XOR AND MOV
BIST
BSET BNOT BCLR BTST
BOR BXOR BAND BLD Table A.2 Table A.2 Table A.2
7 MOV EEPMOV
BIOR BIXOR BIAND BILD (2) (2) (3)
8 ADD
9 ADDX
A CMP
B SUBX
C OR
D XOR
E AND
F MOV
Table A.2
Instruction code: 1st byte 2nd byte

AH AL BH BL
BH
0 1 2 3 4 5 6 7 8 9 A B C D E F
AH AL
Table A.2 Table A.2 Table A.2
01 MOV LDC/STC SLEEP
(3) (3) (3)
0A INC ADD
0B ADDS INC INC ADDS INC INC
0F DAA MOV
10 SHLL SHLL SHAL SHAL
11 SHLR SHLR SHAR SHAR
12 ROTXL ROTXL ROTL ROTL
13 ROTXR ROTXR ROTR ROTR
17 NOT NOT EXTU EXTU NEG NEG EXTS EXTS
1A DEC SUB
1B SUBS DEC DEC SUB DEC DEC
1F DAS CMP
58 BRA BRN BHI BLS BCC BCS BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE
79 MOV ADD CMP SUB OR XOR AND
7A MOV ADD CMP SUB OR XOR AND

Appendix
REJ09B0216-0300
Rev. 3.00 Sep. 10, 2007 Page 475 of 528
Appendix
Table A.2
Instruction code: 1st byte 2nd byte 3rd byte 4th byte Instruction when most significant bit of DH is 0.
REJ09B0216-0300
AH AL BH BL CH CL DH DL
Instruction when most significant bit of DH is 1.
CL
AH 0 1 2 3 4 5 6 7 8 9 A B C D E F
ALBH
BLCH
LDC LDC LDC LDC
01406
STC STC STC STC
01C05 MULXS MULXS
Rev. 3.00 Sep. 10, 2007 Page 476 of 528

01D05 DIVXS DIVXS
01F06 OR XOR AND
7Cr06 * 1 BTST
BOR BXOR BAND BLD

7Cr07 * 1 BTST
BIOR BIXOR BIAND BILD
BST
7Dr06 * 1 BSET BNOT BCLR
BIST
7Dr07 * 1 BSET BNOT BCLR
7Eaa6 * 2 BTST
BOR BXOR BAND BLD

7Eaa7 * 2 BTST
BIOR BIXOR BIAND BILD
BST
7Faa6 * 2 BSET BNOT BCLR
BIST
7Faa7 * 2 BSET BNOT BCLR
Notes: 1. r is the register designation field.

2. aa is the absolute address field.
Appendix
A.3 Number of Execution States

The status of execution for each instruction of the H8/300H CPU and the method of calculating
the number of states required for instruction execution are shown below. Table A.4 shows the
number of cycles of each type occurring in each instruction, such as instruction fetch and data
read/write. Table A.3 shows the number of states required for each cycle. The total number of
states required for execution of an instruction can be calculated by the following expression:
Execution states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed.
BSET #0, @FF00
From table A.4:

I = L = 2, J = K = M = N= 0
From table A.3:

SI = 2, SL = 2
Number of states required for execution = 2 × 2 + 2 × 2 = 8
When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and
on-chip RAM is used for stack area.
JSR @@ 30
From table A.4:

I = 2, J = K = 1, L=M=N=0
From table A.3:

SI = SJ = SK = 2
Number of states required for execution = 2 × 2 + 1 × 2+ 1 × 2 = 8
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Appendix
Table A.3 Number of Cycles in Each Instruction
Access Location
Execution Status
(Instruction Cycle) On-Chip Memory On-Chip Peripheral Module
Instruction fetch SI 2 —
Branch address read SJ
Stack operation SK
Byte data access SL 2 or 3*
Word data access SM 2 or 3*
Internal operation SN 1
Note: * Depends on which on-chip peripheral module is accessed. See section 21.1, Register
Addresses (Address Order).
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Appendix
Table A.4 Number of Cycles in Each Instruction

Instruction Branch Stack Byte Data Word Data Internal
Fetch Addr. Read Operation Access Access Operation
Instruction Mnemonic I J K L M N
ADD ADD.B #xx:8, Rd 1
ADD.B Rs, Rd 1
ADD.W #xx:16, Rd 2
ADD.W Rs, Rd 1
ADD.L #xx:32, ERd 3
ADD.L ERs, ERd 1
ADDS ADDS #1/2/4, ERd 1
ADDX ADDX #xx:8, Rd 1
ADDX Rs, Rd 1
AND AND.B #xx:8, Rd 1
AND.B Rs, Rd 1
AND.W #xx:16, Rd 2
AND.W Rs, Rd 1
AND.L #xx:32, ERd 3
AND.L ERs, ERd 2
ANDC ANDC #xx:8, CCR 1
BAND BAND #xx:3, Rd 1
BAND #xx:3, @ERd 2 1
BAND #xx:3, @aa:8 2 1
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Appendix

Bcc BRA d:8 (BT d:8) 2
BRN d:8 (BF d:8) 2
BHI d:8 2
BLS d:8 2
BCC d:8 (BHS d:8) 2
BCS d:8 (BLO d:8) 2
BNE d:8 2
BEQ d:8 2
BVC d:8 2
BVS d:8 2
BPL d:8 2
BMI d:8 2
BGE d:8 2
Bcc BLT d:8 2
BGT d:8 2
BLE d:8 2
BRA d:16(BT d:16) 2 2
BRN d:16(BF d:16) 2 2
BHI d:16 2 2
BLS d:16 2 2
BCC d:16(BHS d:16) 2 2
BCS d:16(BLO d:16) 2 2
BNE d:16 2 2
BEQ d:16 2 2
BVC d:16 2 2
BVS d:16 2 2
BPL d:16 2 2
BMI d:16 2 2
BGE d:16 2 2
BLT d:16 2 2
BGT d:16 2 2
BLE d:16 2 2
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Appendix

BCLR BCLR #xx:3, Rd 1
BCLR #xx:3, @ERd 2 2
BCLR #xx:3, @aa:8 2 2
BCLR Rn, Rd 1
BCLR Rn, @ERd 2 2
BCLR Rn, @aa:8 2 2
BIAND BIAND #xx:3, Rd 1
BIAND #xx:3, @ERd 2 1
BIAND #xx:3, @aa:8 2 1
BILD BILD #xx:3, Rd 1
BILD #xx:3, @ERd 2 1
BILD #xx:3, @aa:8 2 1
BIOR BIOR #xx:8, Rd 1
BIOR #xx:8, @ERd 2 1
BIOR #xx:8, @aa:8 2 1
BIST BIST #xx:3, Rd 1
BIST #xx:3, @ERd 2 2
BIST #xx:3, @aa:8 2 2
BIXOR BIXOR #xx:3, Rd 1
BIXOR #xx:3, @ERd 2 1
BIXOR #xx:3, @aa:8 2 1
BLD BLD #xx:3, Rd 1
BLD #xx:3, @ERd 2 1
BLD #xx:3, @aa:8 2 1
BNOT BNOT #xx:3, Rd 1
BNOT #xx:3, @ERd 2 2
BNOT #xx:3, @aa:8 2 2
BNOT Rn, Rd 1
BNOT Rn, @ERd 2 2
BNOT Rn, @aa:8 2 2
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Appendix

BOR BOR #xx:3, Rd 1
BOR #xx:3, @ERd 2 1
BOR #xx:3, @aa:8 2 1
BSET BSET #xx:3, Rd 1
BSET #xx:3, @ERd 2 2
BSET #xx:3, @aa:8 2 2
BSET Rn, Rd 1
BSET Rn, @ERd 2 2
BSET Rn, @aa:8 2 2
BSR BSR d:8 2 1
BSR d:16 2 1 2
BST BST #xx:3, Rd 1
BST #xx:3, @ERd 2 2
BST #xx:3, @aa:8 2 2
BTST BTST #xx:3, Rd 1
BTST #xx:3, @ERd 2 1
BTST #xx:3, @aa:8 2 1
BTST Rn, Rd 1
BTST Rn, @ERd 2 1
BTST Rn, @aa:8 2 1
BXOR BXOR #xx:3, Rd 1
BXOR #xx:3, @ERd 2 1
BXOR #xx:3, @aa:8 2 1
CMP CMP.B #xx:8, Rd 1
CMP.B Rs, Rd 1
CMP.W #xx:16, Rd 2
CMP.W Rs, Rd 1
CMP.L #xx:32, ERd 3
CMP.L ERs, ERd 1
DAA DAA Rd 1
DAS DAS Rd 1
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Appendix

DEC DEC.B Rd 1
DEC.W #1/2, Rd 1
DEC.L #1/2, ERd 1
DUVXS DIVXS.B Rs, Rd 2 12
DIVXS.W Rs, ERd 2 20
DIVXU DIVXU.B Rs, Rd 1 12
DIVXU.W Rs, ERd 1 20
EEPMOV EEPMOV.B 2 2n+2*1

1
EEPMOV.W 2 2n+2*
EXTS EXTS.W Rd 1
EXTS.L ERd 1
EXTU EXTU.W Rd 1
EXTU.L ERd 1
INC INC.B Rd 1
INC.W #1/2, Rd 1
INC.L #1/2, ERd 1
JMP JMP @ERn 2
JMP @aa:24 2 2
JMP @@aa:8 2 1 2
JSR JSR @ERn 2 1
JSR @aa:24 2 1 2
JSR @@aa:8 2 1 1
LDC LDC #xx:8, CCR 1
LDC Rs, CCR 1
LDC@ERs, CCR 2 1
LDC@(d:16, ERs), CCR 3 1
LDC@(d:24,ERs), CCR 5 1
LDC@ERs+, CCR 2 1 2
LDC@aa:16, CCR 3 1
LDC@aa:24, CCR 4 1
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Appendix

MOV MOV.B #xx:8, Rd 1
MOV.B Rs, Rd 1
MOV.B @ERs, Rd 1 1
MOV.B @(d:16, ERs), Rd 2 1
MOV.B @(d:24, ERs), Rd 4 1
MOV.B @ERs+, Rd 1 1 2
MOV.B @aa:8, Rd 1 1
MOV.B @aa:16, Rd 2 1
MOV.B @aa:24, Rd 3 1
MOV.B Rs, @Erd 1 1
MOV.B Rs, @(d:16, ERd) 2 1
MOV.B Rs, @(d:24, ERd) 4 1
MOV.B Rs, @-ERd 1 1 2
MOV.B Rs, @aa:8 1 1
MOV MOV.B Rs, @aa:16 2 1
MOV.B Rs, @aa:24 3 1
MOV.W #xx:16, Rd 2
MOV.W Rs, Rd 1
MOV.W @ERs, Rd 1 1
MOV.W @(d:16,ERs), Rd 2 1
MOV.W @(d:24,ERs), Rd 4 1
MOV.W @ERs+, Rd 1 1 2
MOV.W @aa:16, Rd 2 1
MOV.W @aa:24, Rd 3 1
MOV.W Rs, @ERd 1 1
MOV.W Rs, @(d:16,ERd) 2 1
MOV.W Rs, @(d:24,ERd) 4 1
Rev. 3.00 Sep. 10, 2007 Page 484 of 528

REJ09B0216-0300
Appendix

MOV MOV.W Rs, @-ERd 1 1 2
MOV.W Rs, @aa:16 2 1
MOV.W Rs, @aa:24 3 1
MOV.L #xx:32, ERd 3
MOV.L ERs, ERd 1
MOV.L @ERs, ERd 2 2
MOV.L @(d:16,ERs), ERd 3 2
MOV.L @(d:24,ERs), ERd 5 2
MOV.L @ERs+, ERd 2 2 2
MOV.L @aa:16, ERd 3 2
MOV.L @aa:24, ERd 4 2
MOV.L ERs,@ERd 2 2
MOV.L ERs, @(d:16,ERd) 3 2
MOV.L ERs, @(d:24,ERd) 5 2
MOV.L ERs, @-ERd 2 2 2
MOV.L ERs, @aa:16 3 2
MOV.L ERs, @aa:24 4 2

2
MOVFPE MOVFPE @aa:16, Rd* 2 1
2
MOVTPE MOVTPE Rs,@aa:16* 2 1
MULXS MULXS.B Rs, Rd 2 12
MULXS.W Rs, ERd 2 20
MULXU MULXU.B Rs, Rd 1 12
MULXU.W Rs, ERd 1 20
NEG NEG.B Rd 1
NEG.W Rd 1
NEG.L ERd 1
NOP NOP 1
NOT NOT.B Rd 1
NOT.W Rd 1
NOT.L ERd 1
Rev. 3.00 Sep. 10, 2007 Page 485 of 528

REJ09B0216-0300
Appendix

OR OR.B #xx:8, Rd 1
OR.B Rs, Rd 1
OR.W #xx:16, Rd 2
OR.W Rs, Rd 1
OR.L #xx:32, ERd 3
OR.L ERs, ERd 2
ORC ORC #xx:8, CCR 1
POP POP.W Rn 1 1 2
POP.L ERn 2 2 2
PUSH PUSH.W Rn 1 1 2
PUSH.L ERn 2 2 2
ROTL ROTL.B Rd 1
ROTL.W Rd 1
ROTL.L ERd 1
ROTR ROTR.B Rd 1
ROTR.W Rd 1
ROTR.L ERd 1
ROTXL ROTXL.B Rd 1
ROTXL.W Rd 1
ROTXL.L ERd 1
ROTXR ROTXR.B Rd 1
ROTXR.W Rd 1
ROTXR.L ERd 1
RTE RTE 2 2 2
RTS RTS 2 1 2
SHAL SHAL.B Rd 1
SHAL.W Rd 1
SHAL.L ERd 1
SHAR SHAR.B Rd 1
SHAR.W Rd 1
SHAR.L ERd 1
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REJ09B0216-0300
Appendix

SHLL SHLL.B Rd 1
SHLL.W Rd 1
SHLL.L ERd 1
SHLR SHLR.B Rd 1
SHLR.W Rd 1
SHLR.L ERd 1
SLEEP SLEEP 1
STC STC CCR, Rd 1
STC CCR, @ERd 2 1
STC CCR, @(d:16,ERd) 3 1
STC CCR, @(d:24,ERd) 5 1
STC CCR,@-ERd 2 1 2
STC CCR, @aa:16 3 1
STC CCR, @aa:24 4 1
SUB SUB.B Rs, Rd 1
SUB.W #xx:16, Rd 2
SUB.W Rs, Rd 1
SUB.L #xx:32, ERd 3
SUB.L ERs, ERd 1
SUBS SUBS #1/2/4, ERd 1
SUBX SUBX #xx:8, Rd 1
SUBX. Rs, Rd 1
TRAPA TRAPA #xx:2 2 1 2 4
XOR XOR.B #xx:8, Rd 1
XOR.B Rs, Rd 1
XOR.W #xx:16, Rd 2
XOR.W Rs, Rd 1
XOR.L #xx:32, ERd 3
XOR.L ERs, ERd 2
XORC XORC #xx:8, CCR 1
Notes: 1. n: Specified value in R4L and R4. The source and destination operands are accessed
n+1 times respectively.
2. Cannot be used in this LSI.
Rev. 3.00 Sep. 10, 2007 Page 487 of 528

REJ09B0216-0300
Appendix
A.4 Combinations of Instructions and Addressing Modes

Table A.5 Combinations of Instructions and Addressing Modes
Addressing Mode
@ERn+/@ERn
@(d:16.ERn)
@(d:24.ERn)
@(d:16.PC)
@(d:8.PC)
Functions Instructions
@@aa:8
@aa:16
@aa:24
@ERn
@aa:8
#xx
Rn
—
Data MOV BWL BWL BWL BWL BWL BWL B BWL BWL — — — —
transfer POP, PUSH — — — — — — — — — — — — WL
instructions
MOVFPE, — — — — — — — — — — — — —
MOVTPE
Arithmetic ADD, CMP BWL BWL — — — — — — — — — — —
operations SUB WL BWL — — — — — — — — — — —
ADDX, SUBX B B — — — — — — — — — — —
ADDS, SUBS — L — — — — — — — — — — —
INC, DEC — BWL — — — — — — — — — — —
DAA, DAS — B — — — — — — — — — — —
MULXU, — BW — — — — — — — — — — —
MULXS,
DIVXU,
DIVXS
NEG — BWL — — — — — — — — — — —
EXTU, EXTS — WL — — — — — — — — — — —
Logical AND, OR, XOR — BWL — — — — — — — — — — —
operations NOT — BWL — — — — — — — — — — —
Shift operations — BWL — — — — — — — — — — —
Bit manipulations — B B — — — B — — — — — —
Branching BCC, BSR — — — — — — — — — — — — —
instructions JMP, JSR — — — — — — — — — —
RTS — — — — — — — — — — —
System TRAPA — — — — — — — — — — — —
control RTE — — — — — — — — — — — —
instructions
SLEEP — — — — — — — — — — — —
LDC B B W W W W — W W — — —
STC — B W W W W — W W — — — —
ANDC, ORC, B — — — — — — — — — — — —
XORC
NOP — — — — — — — — — — — —
Block data transfer instructions — — — — — — — — — — — — BW
Rev. 3.00 Sep. 10, 2007 Page 488 of 528

REJ09B0216-0300
Appendix
Appendix B I/O Port Block Diagrams
B.1 I/O Port Block Diagrams

RES goes low in a reset, and SBY goes low at reset and in standby mode.
Internal data bus

RES SBY
PUCR
Pull-up MOS
PMR
PDR
PCR
IRQ
TRGV
[Legend]
PUCR: Port pull-up control register
PMR: Port mode register
PDR: Port data register
PCR: Port control register
Figure B.1 Port 1 Block Diagram (P17)
Rev. 3.00 Sep. 10, 2007 Page 489 of 528

REJ09B0216-0300
Appendix
Internal data bus

RES SBY
PUCR
Pull-up MOS
PMR
PDR
PCR
IRQ
[Legend]
Figure B.2 Port 1 Block Diagram (P14, P16)
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REJ09B0216-0300
Appendix
Internal data bus RES SBY
PUCR
Pull-up MOS
PMR
PDR
PCR
IRQ
TMIB1
[Legend]
PUCR : Port pull-up control register
PMR : Port mode register
PDR : Port data register
PCR : Port control register
Rev. 3.00 Sep. 10, 2007 Page 491 of 528

REJ09B0216-0300
Appendix
Internal data bus

RES SBY
PUCR
Pull-up MOS
PDR
PCR
[Legend]
Rev. 3.00 Sep. 10, 2007 Page 492 of 528

REJ09B0216-0300
Appendix
Internal data bus

RES SBY
PUCR
Pull-up MOS
PMR
PDR
PCR
14-bit PWM
PWM
[Legend]
Rev. 3.00 Sep. 10, 2007 Page 493 of 528

REJ09B0216-0300
Appendix
Internal data bus

RES SBY
PUCR
Pull-up MOS
PMR
PDR
PCR
RTC
TMOW
[Legend]
Rev. 3.00 Sep. 10, 2007 Page 494 of 528

REJ09B0216-0300
Appendix
Internal data bus

SBY
PMR
PDR
PCR
[Legend]
Rev. 3.00 Sep. 10, 2007 Page 495 of 528

REJ09B0216-0300
Appendix
Internal data bus

SBY
PMR
PDR
PCR
SCI3
TxD
[Legend]
Rev. 3.00 Sep. 10, 2007 Page 496 of 528

REJ09B0216-0300
Appendix
SBY
Internal data bus
PDR
PCR
SCI3
RE
RxD
[Legend]
Rev. 3.00 Sep. 10, 2007 Page 497 of 528

REJ09B0216-0300
Appendix
SBY
SCI3
SCKIE
SCKOE
Internal data bus
PDR
PCR
SCKO
SCKI
[Legend]
Rev. 3.00 Sep. 10, 2007 Page 498 of 528

REJ09B0216-0300
Appendix
Internal data bus

SBY
PDR
PCR
[Legend]
Figure B.11 Port 3 Block Diagram (P37 to P30)
Rev. 3.00 Sep. 10, 2007 Page 499 of 528

REJ09B0216-0300
Appendix
Internal data bus SBY
PMR
PDR
PCR
IIC2
ICE
SDAO/SCLO
SDAI/SCLI
[Legend]
Rev. 3.00 Sep. 10, 2007 Page 500 of 528

REJ09B0216-0300
Appendix
Internal data bus

RES SBY
PUCR
Pull-up MOS
PMR
PDR
PCR
WKP
ADTRG
[Legend]
Rev. 3.00 Sep. 10, 2007 Page 501 of 528

REJ09B0216-0300
Appendix
Internal data bus

RES SBY
PUCR
Pull-up MOS
PMR
PDR
PCR
WKP
[Legend]
Rev. 3.00 Sep. 10, 2007 Page 502 of 528

REJ09B0216-0300
Appendix
Internal data bus SBY
Timer Z
Output control
signals A to D
PDR
PCR
FTIOA to
FTIOD
[Legend]
Rev. 3.00 Sep. 10, 2007 Page 503 of 528

REJ09B0216-0300
Appendix
Internal data bus
SBY
Timer V
OS3
OS2
OS1
OS0
PDR
PCR
TMOV
[Legend]
Rev. 3.00 Sep. 10, 2007 Page 504 of 528

REJ09B0216-0300
Appendix
Internal data bus

SBY
PDR
PCR
Timer V
TMCIV
[Legend]
Rev. 3.00 Sep. 10, 2007 Page 505 of 528

REJ09B0216-0300
Appendix
Internal data bus

SBY
PDR
PCR
Timer V
TMRIV
[Legend]
Rev. 3.00 Sep. 10, 2007 Page 506 of 528

REJ09B0216-0300
Appendix
Internal data bus

SBY
PMR
PDR
PCR
SCI3_2
TxD
[Legend]
Rev. 3.00 Sep. 10, 2007 Page 507 of 528

REJ09B0216-0300
Appendix
SBY
Internal data bus
PDR
PCR
SCI3_2
RE
RxD
[Legend]
SBY
SCI3_2
SCKIE
SCKOE
Internal data bus
PDR
PCR
SCKO
SCKI
[Legend]
Rev. 3.00 Sep. 10, 2007 Page 508 of 528

REJ09B0216-0300
Appendix
Internal data bus

SBY
PDR
PCR
[Legend]
Rev. 3.00 Sep. 10, 2007 Page 509 of 528

REJ09B0216-0300
Appendix
Internal data bus
A/D converter
CH3 to CH0 DEC
SCAN
VIN
Low voltage
detection circuit
VDDII
ExtD, ExtU
Figure B.23 Port B Block Diagram (PB7 and PB6)
Internal data bus
A/D converter
SCAN DEC
CH3 to CH0
VIN
Figure B.24 Port B Block Diagram (PB5 to PB0)
Rev. 3.00 Sep. 10, 2007 Page 510 of 528

REJ09B0216-0300
Appendix
SBY
Internal data bus
CPG
PDR
PCR
PMRC1
PMRC0
XTALI
[Legend]
Figure B.25 Port B Block Diagram (PC1)
Rev. 3.00 Sep. 10, 2007 Page 511 of 528

REJ09B0216-0300
Appendix
SBY
Internal data bus
PDR
PCR
CPG
PMRC0
EXTALI
[Legend]
Figure B.26 Port B Block Diagram (PC0)
Rev. 3.00 Sep. 10, 2007 Page 512 of 528

REJ09B0216-0300
Appendix
B.2 Port States in Each Operating State

Port Reset Sleep Subsleep Standby Subactive Active
P17 to P14, High Retained Retained High Functioning Functioning
P12 to P10 impedance impedance*
P24 to P20 High Retained Retained High Functioning Functioning
impedance impedance
impedance impedance
impedance impedance*
impedance impedance
P76 to P74, High Retained Retained High Functioning Functioning
P72 to P70 impedance impedance
impedance impedance
PB7 to PB0 High High High High High High
impedance impedance impedance impedance impedance impedance
PC1 and PC0 High Retained Retained High Functioning Functioning
impedance impedance
Note: * High level output when the pull-up MOS is turned on.
Rev. 3.00 Sep. 10, 2007 Page 513 of 528

REJ09B0216-0300
Appendix
Appendix C Product Code Lineup

Product Classification
Package
Voltage Temperature (Package
1 2
Product Group Specification* Specification* Product Code*3 Model Marking Code)
Flash H8/36079 H8/36079GF 5.0 V Regular HD64F36079GH HD64F36079GH QFP-64

memory Group (FP-64A)
Wide range HD64F36079GHW HD64F36079GHW
version
Regular HD64F36079GFZ HD64F36079GFZ LQFP-64
(FP-64K)
Wide range HD64F36079GFZW HD64F36079GFZW
H8/36079LF 3.3 V Regular HD64F36079LH HD64F36079LH QFP-64

(FP-64A)
Wide range HD64F36079LHW HD64F36079LHW
Regular HD64F36079LFZ HD64F36079LFZ LQFP-64

(FP-64K)
Wide range HD64F36079LFZW HD64F36079LFZW
H8/36078GF 5.0 V Regular HD64F36078GH HD64F36078GH QFP-64

(FP-64A)

(FP-64K)

(FP-64A)

(FP-64K)
Rev. 3.00 Sep. 10, 2007 Page 514 of 528

REJ09B0216-0300
Appendix
Product Classification
Package
Voltage Temperature (Package
1 2 3
Product Group Specification* Specification* Product Code* Model Marking Code)
Flash H8/36077 H8/36077GF 5.0 V Regular HD64F36077GH HD64F36077GH QFP-64

memory Group (FP-64A)
version
(FP-64K)

(FP-64A)

(FP-64K)

(FP-64A)

(FP-64K)

(FP-64A)

(FP-64K)
Notes: 1. Operating voltage range: 4.5 to 5.5 V (5.0-V models), 3.0 to 3.6 V (3.3-V models)
2. Operating temperature range: Regular specifications: -20 to +75°C, wide-range
specifications: -40 to +85°C
3. The table includes products that are yet to be released. For details, please contact one
of our sales representatives.
Rev. 3.00 Sep. 10, 2007 Page 515 of 528

REJ09B0216-0300
JEITA Package Code RENESAS Code Previous Code MASS[Typ.]
P-LQFP64-10x10-0.50 PLQP0064KB-A 64P6Q-A / FP-64K / FP-64KV 0.3g
Appendix
REJ09B0216-0300
HD
*1
D
48 33
49 32 NOTE)
1. DIMENSIONS "*1" AND "*2"
Rev. 3.00 Sep. 10, 2007 Page 516 of 528

DO NOT INCLUDE MOLD FLASH.
bp 2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
b1
E
HE
c
c1
*2
Reference Dimension in Millimeters
Symbol
64 Min Nom Max
17 Terminal cross section
ZE
D 9.9 10.0 10.1
E 9.9 10.0 10.1
1 16
Index mark A2 1.4
ZD HD 11.8 12.0 12.2
HE 11.8 12.0 12.2
F A 1.7
A1 0.05 0.1 0.15
Figure D.1 FP-64K Package Dimensions

c
A
A2
bp 0.15 0.20 0.25

b1 0.18
c 0.09 0.145 0.20
Appendix D Package Dimensions
y
A1
*3 L c1 0.125
e bp
x L1 0° 8°
e 0.5
Detail F
x 0.08
y 0.08
ZD 1.25
ZE 1.25
L 0.35 0.5 0.65
L1 1.0
JEITA Package Code RENESAS Code Previous Code MASS[Typ.]
P-QFP64-14x14-0.80 PRQP0064GB-A FP-64A/FP-64AV 1.2g
HD NOTE)
*1
1. DIMENSIONS"*1"AND"*2"
D DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
48 33 INCLUDE TRIM OFFSET.
49 32
bp
b1
c1
c
E
HE
*2
Reference Dimension in Millimeters
Terminal cross section Symbol
Min Nom Max
ZE
D 14
17
64 E 14
A2 2.70
HD 16.9 17.2 17.5
1 16
HE 16.9 17.2 17.5
ZD
A 3.05
A2
A
c
F
A1 0.00 0.10 0.25
Figure D.2 FP-64A Package Dimensions

θ
bp 0.29 0.37 0.45
L
A1
b1 0.35
L1
c 0.12 0.17 0.22
Detail F c1 0.15
e *3
bp θ 0° 8°
y x M
e 0.8
x 0.15
y 0.10
ZD 1.0
ZE 1.0
L 0.5 0.8 1.1
L1 1.6
Appendix
REJ09B0216-0300
Rev. 3.00 Sep. 10, 2007 Page 517 of 528
Appendix
Rev. 3.00 Sep. 10, 2007 Page 518 of 528

REJ09B0216-0300
Main Revisions and Additions in this Edition
Item Page Revision (See Manual for Details)
Section 7 ROM 127 Amended
7.6 Programmer Mode In programmer mode, a PROM programmer can be
used to perform programming/erasing via a socket
adapter, just as a discrete flash memory. Use a PROM
programmer that supports the MCU device type with
the on-chip 128-kbyte flash memory (FZTAT64V5).
Section 16 Serial 299 Amended
Communication Interface 3 Operating Frequency ø (MHz)
(SCI3)
12.288 14
Table 16.3 Examples of BRR Bit Rate n N Error n N Error
Settings for Various Bit Rates (bit/s) (%) (%)
(Asynchronous Mode) (3)
Section 18 A/D Converter 368 Deleted

Figure 18.1 Block Diagram of
A/D Converter Ø/4
Control circuit
Ø/8
Section 21 List of Registers 405 Amended

Register
Name Bit 7 …
: : :
FLPWCR PDWND :
1
EBR1* EB7 :
Notes:
4. The bit configuration of EBR1 differs according to products. For the bit
configuration of each product, see the list below.
Rev. 3.00 Sep. 10, 2007 Page 519 of 528

REJ09B0216-0300
Section 21 List of Registers 408 Added
H8/3609G,H8/36079L
Register Module
Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Name
EBR1 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 ROM
H8/36078G,H8/36078L,H8/36077G,H8/36077L
Register Module
EBR1 – EB6 EB5 EB4 EB3 EB2 EB1 EB0 ROM
H8/36074G,H8/36074L
Register Module
EBR1 – – – EB4 EB3 EB2 EB1 EB0 ROM
Section 22 Electrical 415 to The wide temperature range of Ta = –40 to +85°C is

Characteristics 458 added to the conditions.
Table 22.3 AC Characteristics 427 Amended
Values
Item Test Condition Min. Typ. Min.
On-chip Vcc = 5.0 V 19.70 20.0 20.30

oscillator Ta = 25°C
oscillation FSEL= 1
frequency VCLSEL= 0
FSEL = 1, 19.40 20.0 20.60

Ta = -20 to +75°C,
VCLSEL = 0
FSEL = 1, 19.20 20.00 20.80

Ta = -40 to +85°C,
VCLSEL = 0
Vcc = 5.0 V, 15.76 16.0 16.24

Ta = 25°C,
FSEL = 0,
VCLSEL = 0
FSEL = 0, 15.52 16.0 16.48

Ta = -20 to +75°C,
VCLSEL = 0
FSEL = 0, 15.36 16.0 16.64

Ta = -40 to +85°C,
VCLSEL = 0
Rev. 3.00 Sep. 10, 2007 Page 520 of 528

REJ09B0216-0300
Table 22.6 A/D Converter 431 Amended
Characteristics Values
Item Min Typ Max
Conversion time 134 — —

(Single mode)
Nonlinearity error – — ±3.5
Offset error – — ±3.5
Full-scale error – — ±3.5
Quantization error – — ±0.5
Absolute accuracy – — ±4.0
Table 22.9 Power-Supply- 434 Amended

Voltage Detection Circuit Values
Characteristics
Item Min Typ Max
2
Reset detection voltage 2* 3.3 3.6 3.9
Table 22.12 440 Amended

DC Characteristics (1) Values
Item Symbol Min Typ Max
: : : : : :
Pull-up MOS current –IP — 60.0 —
Amended
Values
Item Symbol Min Typ Max
: : : : : :
Active mode current : : : : :

consumption
IOPE2 — 2.8 4.0
— 2.5 —
Rev. 3.00 Sep. 10, 2007 Page 521 of 528

REJ09B0216-0300
Table 22.13 446 Amended
AC Characteristics Values
Item Test Condition Min. Typ. Min.
On-chip Vcc = 3.3 V 19.70 20.00 20.30

oscillator Ta = 25°C
oscillation FSEL= 1
frequency VCLSEL= 0
FSEL = 1, 19.40 20.00 20.60

Ta = -20 to +75°C,
VCLSEL = 0
FSEL = 1, 19.2 20.0 20.8

Ta = -40 to +85°C,
VCLSEL = 0
Vcc = 3.3 V, 15.76 16.00 16.24

Ta = 25°C,
FSEL = 0,
VCLSEL = 0
FSEL = 0, 15.36 16.0 16.64

Ta = -20 to +75°C,
VCLSEL = 0
FSEL = 0, 15.52 16.0 16.48

Ta = -40 to +85°C,
VCLSEL = 0
Table 22.19 Power-Supply- 453 Amended

Voltage Detection Circuit Values
Characteristics
Item Min. Min. Min.
Power-supply falling 2.8 2.9 3.05

detection voltage
Power-supply rising 2.9 3.0 3.15

detection voltage
Rev. 3.00 Sep. 10, 2007 Page 522 of 528

REJ09B0216-0300
Appendix C 515 Amended
Product Code Lineup Product Classification Product Code*3 Model Marking Package
(Package
Product Group Voltage Temperature
Code)
Specificat Specification
ion*1 *2
H8/36079 H8/36079GF 5.0 V Regular HD64F36079GH HD64F36079GH QFP-64
Group (FP-64A)
(FP-64K)
(FP-64A)
(FP-64K)
(FP-64A)
(FP-64K)
(FP-64A)
(FP-64K)
Rev. 3.00 Sep. 10, 2007 Page 523 of 528

REJ09B0216-0300
Appendix C 516 Amended
Product Code Lineup Product Classification Product Code*3 Model Marking Package
(Package
Product Voltage
Code)
Group Specification
*1
H8/36077 H8/36077GF 5.0 V Regular HD64F36077GH HD64F36077GH QFP-64
Group (FP-64A)
(FP-64K)
(FP-64A)
(FP-64K)
(FP-64A)
(FP-64K)
(FP-64A)
(FP-64K)
Rev. 3.00 Sep. 10, 2007 Page 524 of 528

REJ09B0216-0300
Index
Numerics D
14-bit PWM ............................................ 281 Data reading procedure ........................... 177
Data transfer instructions .......................... 20
A
A/D converter ......................................... 367 E
Absolute address....................................... 31 Effective address ....................................... 33
Acknowledge .......................................... 346 Effective address extension....................... 29
Address break ........................................... 63 Erase/erase-verify ................................... 124
Addressing modes..................................... 30 Erasing units ........................................... 107
Arithmetic operations instructions............ 21 Error protection....................................... 126
Asynchronous mode ............................... 303 Event counter operation .......................... 183
Auto-reload timer operation.................... 183 Exception handling ................................... 45
B F
Bit manipulation instructions.................... 24 Flash memory.......................................... 107
Bit rate .................................................... 296 Framing error .......................................... 307
Bit synchronous circuit ........................... 363
Block data transfer instructions ................ 28
Boot mode............................................... 117 G
Boot program.......................................... 117 General registers ....................................... 13
Branch instructions ................................... 26
Break....................................................... 326
Buffer operation...................................... 254 H
Hardware protection................................ 126
C
Clock synchronous mode........................ 311 I
Clock synchronous serial format ............ 354
I/O port block diagrams .......................... 489
Complementary PWM mode .................. 244
I/O ports .................................................. 131
Condition field .......................................... 29
I2C bus format ......................................... 345
Condition-code register (CCR)................. 14
I2C bus interface 2 (IIC2)........................ 329
CPU ............................................................ 9
Immediate ................................................. 32
Initial setting procedure .......................... 176
Input capture function ............................. 229
Instruction set............................................ 19
Rev. 3.00 Sep. 10, 2007 Page 525 of 528

REJ09B0216-0300
Internal interrupts ..................................... 58 P
Internal power supply Package ....................................................... 3
step-down circuit .................................... 393 Package dimensions ................................ 516
Interrupt mask bit...................................... 15 Parity error .............................................. 307
Interrupt response time ............................. 60 Pin arrangement .......................................... 5
Interval timer operation .......................... 182 Power-down modes................................... 93
IRQ3 to IRQ0 interrupts ........................... 56 Power-down states .................................. 127
Power-on reset ........................................ 379
Power-on reset circuit ............................. 386
L Product code lineup ................................ 514
Large current ports...................................... 3 Program counter (PC) ............................... 14
Logic operations instructions.................... 23 Program/program-verify ......................... 121
Low-voltage detection circuit ................. 379 Program-counter relative .......................... 32
LVDI (interrupt by low voltage detect) Programmer mode................................... 127
circuit.............................................. 389, 390 Programming units.................................. 107
LVDR (reset by low voltage detect) Programming/erasing in
circuit...................................................... 387 user program mode ................................. 120
PWM mode ............................................. 234
M
Memory indirect ....................................... 32 R
Memory map ............................................ 11 Realtime clock (RTC) ............................. 167
Module standby function ........................ 106 Register direct ........................................... 30
Multiprocessor communication Register field............................................. 29
function................................................... 318 Register indirect ........................................ 31
Register indirect with displacement .......... 31
Register indirect with post-increment ....... 31
N Register indirect with pre-decrement ........ 31
NMI interrupt............................................ 56 Register settings ...................................... 284
Noise canceler ........................................ 357 Registers
ABRKCR ...................... 64, 400, 406, 411
ABRKSR ...................... 67, 400, 406, 411
ADCR ......................... 372, 400, 406, 411
O
ADCSR ....................... 371, 399, 406, 411
On-board programming modes............... 117
ADDRA ...................... 370, 399, 406, 411
Operation field.......................................... 29
ADDRB ...................... 370, 399, 406, 411
Overrun error .......................................... 307
ADDRC ...................... 370, 399, 406, 411
ADDRD ...................... 370, 399, 406, 411
BARE............................ 67, 400, 406, 412
BARH ........................... 67, 400, 406, 412
Rev. 3.00 Sep. 10, 2007 Page 526 of 528

REJ09B0216-0300
BARL............................ 67, 400, 406, 412 PCR8 ........................... 159, 401, 407, 412
BDRH ........................... 67, 400, 406, 412 PCRC .......................... 165, 401, 407, 412
BDRL............................ 67, 400, 406, 412 PDR1........................... 133, 400, 406, 412
BRR ............................ 296, 399, 405, 411 PDR2........................... 138, 400, 407, 412
CKCSR ......................... 76, 397, 404, 410 PDR3........................... 142, 400, 407, 412
EBR1 .......................... 114, 399, 405, 411 PDR5........................... 147, 400, 407, 412
FENR .......................... 116, 399, 405, 411 PDR6........................... 152, 401, 407, 412
FLMCR1..................... 112, 398, 405, 411 PDR7........................... 157, 401, 407, 412
FLMCR2..................... 113, 398, 405, 411 PDR8........................... 159, 401, 407, 412
FLPWCR .................... 116, 398, 405, 411 PDRB .......................... 161, 401, 407, 412
GRA............................ 213, 396, 403, 409 PDRC .......................... 166, 401, 407, 412
GRB ............................ 213, 396, 403, 409 PMR1 .......................... 132, 401, 407, 412
GRC ............................ 213, 396, 403, 409 PMR3 .......................... 138, 401, 407, 412
GRD............................ 213, 396, 403, 409 PMR5 .......................... 146, 401, 407, 412
ICCR1......................... 332, 398, 405, 410 POCR .......................... 221, 396, 403, 409
ICCR2......................... 335, 398, 405, 410 PUCR1 ........................ 134, 400, 406, 412
ICDRR ........................ 344, 398, 405, 410 PUCR5 ........................ 148, 400, 406, 412
ICDRS ................................................ 344 PWCR ......................... 283, 400, 406, 411
ICDRT ........................ 344, 398, 405, 410 PWDRL ...................... 283, 400, 406, 411
ICIER.......................... 338, 398, 405, 410 PWDRU ...................... 283, 400, 406, 411
ICMR .......................... 336, 398, 405, 410 RCCR............................ 73, 397, 404, 410
ICSR ........................... 340, 398, 405, 410 RCTRMDPR................. 74, 397, 404, 410
IEGR1........................... 48, 401, 407, 413 RCTRMDR ................... 75, 398, 404, 410
IEGR2........................... 49, 401, 407, 413 RDR ............................ 289, 399, 406, 411
IENR1........................... 50, 401, 407, 413 RHRDR....................... 171, 397, 404, 410
IENR2........................... 51, 401, 407, 413 RMINDR..................... 170, 397, 404, 410
IRR1 ............................. 51, 401, 407, 413 RSECDR ..................... 169, 397, 404, 410
IRR2 ............................. 53, 402, 407, 413 RSR..................................................... 289
IWPR ............................ 53, 402, 407, 413 RTCCR1 ..................... 173, 397, 404, 410
LVDCR....................... 382, 397, 404, 410 RTCCR2 ..................... 174, 397, 404, 410
LVDRF ....................... 385, 397, 404, 410 RTCCSR ..................... 175, 397, 404, 410
LVDSR ....................... 384, 397, 404, 410 RWKDR...................... 172, 397, 404, 410
MSTCR1....................... 98, 402, 408, 413 SAR............................. 343, 398, 405, 410
MSTCR2....................... 99, 402, 408, 413 SCR3 ........................... 292, 399, 405, 411
PCR1........................... 133, 401, 407, 412 SMR ............................ 290, 399, 405, 411
PCR2........................... 137, 401, 407, 412 SSR ............................. 294, 399, 406, 411
PCR3........................... 141, 401, 407, 412 SYSCR1........................ 94, 401, 407, 412
PCR5........................... 147, 401, 407, 412 SYSCR2........................ 97, 401, 407, 412
PCR6........................... 151, 401, 407, 412 TCB1........................... 182, 398, 405, 410
PCR7........................... 156, 401, 407, 412 TCNT .......................... 213, 396, 403, 409
Rev. 3.00 Sep. 10, 2007 Page 527 of 528

REJ09B0216-0300
TCNTV........................187, 399, 405, 411 Slave address........................................... 346
TCORA........................188, 399, 405, 411 Sleep mode.............................................. 103
TCORB........................188, 399, 405, 411 Software protection................................. 126
TCR .............................214, 396, 403, 409 Stack pointer (SP) ..................................... 14
TCRV0 ........................188, 399, 405, 411 Stack status ............................................... 59
TCRV1 ........................191, 399, 405, 411 Standby mode ......................................... 103
TCSRV ........................189, 399, 405, 411 Start condition......................................... 346
TCSRWD ....................276, 400, 406, 411 Stop condition ......................................... 346
TCWD .........................278, 400, 406, 411 Subactive mode....................................... 104
TDR .............................290, 399, 406, 411 Subsleep mode ........................................ 104
TFCR ...........................208, 397, 404, 409 Synchronous operation............................ 233
TIER ............................220, 396, 403, 409 System clocks ........................................... 71
TIORA.........................215, 396, 403, 409 System control instructions....................... 27
TIORC .........................216, 396, 403, 409 System prescaler S .................................... 91
TLB1............................182, 398, 405, 410
TMB1 ..........................181, 398, 405, 410
TMDR..........................206, 397, 404, 409 T
TMWD ........................278, 400, 406, 411 Timer B1 ................................................. 179
TOCR ..........................212, 397, 404, 409 Timer V................................................... 185
TOER...........................210, 397, 404, 409 Timer Z ................................................... 199
TPMR ..........................207, 397, 404, 409 Transfer rate............................................ 334
TSR..............................218, 396, 403, 409 Trap instruction......................................... 45
TSTR ...........................206, 397, 404, 409
Reset exception handling.......................... 55
Reset synchronous PWM mode.............. 240 V
Vector address........................................... 46
S
Sample-and-hold circuit ......................... 374 W
Scan mode .............................................. 373
Watchdog timer....................................... 275
Serial communication
Waveform output .................................... 284
interface 3 (SCI3) ................................... 285
Waveform output by compare match...... 227
Shift instructions....................................... 23
WKP5 to WKP0 interrupts ....................... 56
Single mode ............................................ 373
Rev. 3.00 Sep. 10, 2007 Page 528 of 528

REJ09B0216-0300
Renesas 16-Bit Single-Chip Microcomputer
Hardware Manual
H8/36079 Group, H8/36077 Group
Publication Date: Rev.1.00, Sep. 16, 2005

Rev.3.00, Sep. 10, 2007
Published by: Sales Strategic Planning Div.
Renesas Technology Corp.
Edited by: Customer Support Department
Global Strategic Communication Div.
Renesas Solutions Corp.
 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.

Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
RENESAS SALES OFFICES http://www.renesas.com

Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.

450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
Colophon 6.0
H8/36079 Group, H8/36077 Group
Hardware Manual

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REJ09B0216-0300

The revision list can be viewed directly by

The revision list summarizes the locations of

Renesas 16-Bit Single-Chip Microcomputer

Rev. 3.00 Sep. 10, 2007 Page iii of xxxii

2. Treatment of Unused Input Pins

3. Processing before Initialization

4. Prohibition of Access to Undefined or Reserved Addresses

Rev. 3.00 Sep. 10, 2007 Page iv of xxxii

1. General Precautions on Handling of Product

Rev. 3.00 Sep. 10, 2007 Page v of xxxii

Notes on reading this manual:

• In order to understand the overall functions of the chip

Rev. 3.00 Sep. 10, 2007 Page vi of xxxii

Rev. 3.00 Sep. 10, 2007 Page vii of xxxii

Document Title Document No.

User's manuals for development tools:

Document Title Document No.

Document Title Document No.

Rev. 3.00 Sep. 10, 2007 Page viii of xxxii

Section 3 Exception Handling ...............................................................................45

Rev. 3.00 Sep. 10, 2007 Page ix of xxxii

Section 4 Address Break .......................................................................................63

Section 5 Clock Pulse Generator ...........................................................................71

Rev. 3.00 Sep. 10, 2007 Page x of xxxii

Section 6 Power-Down Modes ..............................................................................93

Section 7 ROM ....................................................................................................107

Rev. 3.00 Sep. 10, 2007 Page xi of xxxii

Section 8 RAM ....................................................................................................129

Section 9 I/O Ports...............................................................................................131

Rev. 3.00 Sep. 10, 2007 Page xii of xxxii

Section 10 Realtime Clock (RTC) .......................................................................167

Section 11 Timer B1 ............................................................................................179

Rev. 3.00 Sep. 10, 2007 Page xiii of xxxii

Section 13 Timer Z..............................................................................................199

Rev. 3.00 Sep. 10, 2007 Page xiv of xxxii

Section 14 Watchdog Timer ................................................................................275

Section 15 14-Bit PWM.......................................................................................281

Section 16 Serial Communication Interface 3 (SCI3) .........................................285

Rev. 3.00 Sep. 10, 2007 Page xv of xxxii

Section 17 I2C Bus Interface 2 (IIC2)..................................................................329

Rev. 3.00 Sep. 10, 2007 Page xvi of xxxii

Section 18 A/D Converter....................................................................................367

Section 19 Band-Gap Circuit, Power-On Reset, and

Rev. 3.00 Sep. 10, 2007 Page xvii of xxxii

Section 21 List of Registers.................................................................................395

Section 22 Electrical Characteristics ...................................................................415

Appendix A Instruction Set ...............................................................................459

Rev. 3.00 Sep. 10, 2007 Page xviii of xxxii

Appendix C Product Code Lineup.....................................................................514

Appendix D Package Dimensions .....................................................................516

Main Revisions and Additions in this Edition .....................................................519

Rev. 3.00 Sep. 10, 2007 Page xix of xxxii

Rev. 3.00 Sep. 10, 2007 Page xxi of xxxii

Rev. 3.00 Sep. 10, 2007 Page xxii of xxxii

Rev. 3.00 Sep. 10, 2007 Page xxiii of xxxii

Rev. 3.00 Sep. 10, 2007 Page xxiv of xxxii

Rev. 3.00 Sep. 10, 2007 Page xxv of xxxii

Rev. 3.00 Sep. 10, 2007 Page xxvi of xxxii