Why Masking Is Needed: Scan Chain Masking in The Acompactor

Scan Chain Masking in the aCompactor
This section describes how and why scan chain masking is used in the compactor to ensure
accurate scan chain observations.
Why Masking is Needed
To facilitate compression, the tool inserts a compactor between the scan chain outputs and the
scan channel outputs. In this circuitry, one or more stages of XOR gates compact the response
from several chains into each channel output. Scan chains compacted into the same scan
channel are said to be in the same compactor group.
One common problem with different compactor strategies is handling of Xs (unknown values).
Scan cells can capture X values from un modeled blocks, memories, non-scan cells, and so forth.
Assume two scan chains are compacted into one channel. An X captured in Chain 1 will then
block the corresponding cell in Chain 2. If this X occurs in Chain 1 for all patterns, the value in
the corresponding cell in Chain 2 will never be measured. This is illustrated in Figure 9-32,
where the row in the middle shows the values measured on the channel output.
Figure 9-32. X-Blocking in the Compactor

The tool records an X in the pattern file in every position made unmeasurable as a result of the
actual occurrence of an X in the corresponding cell of a different scan chain in the same
compactor group. This is referred to as X blocking. The capture data for Chain 1 and Chain 2
that you would see in the ASCII pattern file for this example would look similar to Figure 9-33.
The Xs substituted by the tool for actual values, unmeasurable because of the compactor, are
shown in red.
Resolving X Blocking with Scan Chain Masking

The solution to this problem is a mechanism utilized in the EDT logic called “scan chain
masking.” This mechanism allows selection of individual scan chains on a per-pattern basis.
Two types of scan chain masking are used: 1-hot masking and flexible masking.
• With 1-hot masking, only one chain is observed via each scan channel's compaction
network. All the other chains in that compactor are masked so they produce a constant 0
to the input of the compactor. This allows observation of fault effects for the observed
chains even if there are Xs in the observation cycles for the other chains. 1-hot masking
patterns are only generated for a few ATPG cycles at points when the non-masking and
flexible masking algorithms fail to detect any significant number of faults.
• Flexible masking patterns allow multiple chains to be observed via each scan channel's
compaction network. Flexible masking is not fully non-masking; with fully nonmasking
patterns, none of the chains are masked so Xs in some cycles of some chains
can block the observation of the fault effects in some other chain. The Xpress compactor
observes all chains with known values and masks out those scan chains that contain X
values so they do not block observation of other chains. With Xpress flexible masking,
only a subset of the chains is masked to maximize the fault detection profile while
reducing the impact on pattern count. When a fault effect cannot be observed at the
channel output under any of the flexible masking configurations, the tool uses 1-hot
masking to guarantee the detection of such faults.
Figure 9-34 shows how scan chain masking would work for the example of the preceding
section. For one pattern, only the values of Chain 2 are measured on the scan channel output.
This way, the Xs in Chain 1 will not block values in Chain 2. Similar patterns would then also
be produced where Chain 2 is disabled while the values of Chain 1 are observed on the scan
channel output.
Special Topics
Figure 9-34. Example of Scan Chain Masking
When using scan chain masking, the tool records the actual measured value for each cell in the
unmasked, selected scan chain in a compactor group. The tool masks the rest of the scan chains
in the group, which means the tool changes the values to all Xs. With masking, the capture data
for Chain 1 and Chain 2 that you would see in the ASCII pattern file would look similar to
Figure 9-35, assuming Chain 2 is to be observed and Chain 1 is masked. The values the tool
changed to X for the masked chain are shown in red.
Figure 9-35. Handling of Scan Chain Masking
Following is part of the transcript from a pattern generation run for a simple design where
masked patterns were used to improve test coverage. The design has three scan chains, each
containing three scan cells. One of the scan chain pins is shared with a functional pin, contrary
to recommended practice, in order to illustrate the negative impact such sharing has on test
coverage.
EDT Logic and Chain Testing

In addition to performing DRC verification of the EDT logic, the tool saves, as part of the
pattern set, an EDT logic and chain test. This test consists of several scan patterns that verify
correct operation of the EDT logic and the scan chains when faults are added on the core or on
the entire design. This test is necessary because the EDT logic is not the standard scan-based
circuitry that traditional chain test patterns are designed for. The EDT logic and chain test helps
in debugging simulation mismatches and guarantees very high test coverage of the EDT logic.
You can use the following equation to predict the number of additional chain test patterns the
tool generates to test the EDT logic. (In this equation, ceil indicates the ceiling function that
rounds a fraction to the next highest integer.) Note, this equation provides a lower bound; the
actual number may be higher.
166 Tessent® TestKompress® User's Manual, v2016.3
Generating/Verifying Test Patterns
September 2016
How it Works
To better understand the enhanced chain test, you need to understand how the masking logic in
the compactor works. Included in every EDT pattern are mask codes that are uncompressed and
shifted into a mask shift register as the pattern data is shifted into the scan chains. Once a
pattern’s mask codes are in the mask shift register, they are parallel loaded into a hold register
that places the bit values on the inputs to a decoder. Figure 7-3 shows a conceptual view of the
decoder circuitry for a six chains/one channel configuration.
The decoder basically has a classic binary decoder within it and some OR gates. The classic
decoder decodes its n inputs to one-hot out of 2n outputs. The 2n outputs fall into one of two
groups: the “used” group or the “unused” group. (Unless the number of scan chains exactly
equals 2n, there will always be one or more unused outputs.)
Figure 7-3. Example Decoder Circuitry for Six Scan Chains and One Channel
Each output in the used group is AND’d with one scan chain output. For a masked pattern, the
decoder typically places a high on one of the used outputs, enabling one AND gate to pass its
chain’s output for observation.
The decoder also has a single bit control input provided by the edt_mask signal. Unused outputs
of the classic decoder are OR’d together and the result is OR’d with this control bit. If any of the
OR’d signals is high, the output of the OR function is high and indicates the pattern is a
nonGenerating/ Verifying Test Patterns.
masking pattern. This OR output is OR’d with each used output, so that, for a non-masking
pattern, all the AND gates will pass their chain’s outputs for observation.
The code scanned into the mask shift register for each channel of a multiple channel design
determines the chain(s) observed for each channel. If the code scanned in for a channel is a
nonmasking
code, that channel’s chains are all observed. If a channel’s code is a masking code,
usually only one of the chains for that channel is observed. The chain test essentially tests for all
possible codes plus the edt_mask control bit.
Understanding Compactor Options

There are two compactors available in compressed ATPG:
Xpress
The Xpress compactor is the second generation compactor generated by default. The
Xpress compactor optimizes compression for all designs but is especially effective for
designs that generate X values. The Xpress compactor observes all chains with known
values and masks out scan chains that contain X values. This X handling results in fewer
test patterns being required for designs that generate X values.
Depending on the application, the EDT logic generated with the Xpress compactor
requires additional clocking cycles. The additional clocking cycles are determined by
the ratio of scan chains to output channels and are relatively few when compared with
the total shift cycles.
A mask code (prepended with a decoder mode bit) is generated with each test pattern to
determine which scan chains are masked or observed. The Xpress compactor determines which
chains to observe or mask using the mask code as follows:
1. Each test pattern is loaded into the decompressor through a mask shift register on the
input channel.
2. The mask code is appended (சேர்க்கப்பட்டிருக்கும்) to each test pattern and remains in the
mask shift register once the test pattern is completely loaded into the decompressor.
3. The mask code is then parallel-loaded into the mask hold register.
where the decoder mode bit determines whether the basic decoder or the XOR decoder is used
on the mask code.
o The basic decoder selects only one scan chain per compactor. The basic decoder is
selected when there is a very high rate of X values during scan testing or during
chain test to allow failing chains to be fully observed and easy to diagnose.
o The XOR decoder masks or observes multiple scan chains per compactor, depending
on the mask code. For example, if the mask code is all 1s, then all the scan chains are
observed.
4. The decoder output is shifted through a multiplexer, and each bit drives one input on the
masking AND gates in the compactor to either disable or enable the output, depending
on the decoder mode and bit value

Why Masking Is Needed: Scan Chain Masking in The Acompactor

Uploaded by

Copyright:

Available Formats

Why Masking Is Needed: Scan Chain Masking in The Acompactor

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Why Masking Is Needed: Scan Chain Masking in The Acompactor

Uploaded by

Copyright:

Available Formats

Scan Chain Masking in the aCompactor

Figure 9-32. X-Blocking in the Compactor

Resolving X Blocking with Scan Chain Masking

EDT Logic and Chain Testing

Understanding Compactor Options

You might also like