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    Hold and Setup Violation and SDF

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    Ilaiyaveni Iyandurai
    The document discusses the Standard Delay Format (SDF) file format. SDF stores timing data generated by EDA tools that can be used throughout the design process. It represents timing information like delays, timing checks, and timing constraints in a tool-independent way. SDF files can contain pre-layout timing data, path constraints, post-layout timing data, and more. The name of each SDF file is determined by the EDA tool that generates it.

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    Hold and Setup Violation and SDF

    Uploaded by

    Ilaiyaveni Iyandurai
    308 views2 pages
    The document discusses the Standard Delay Format (SDF) file format. SDF stores timing data generated by EDA tools that can be used throughout the design process. It represents timing information like delays, timing checks, and timing constraints in a tool-independent way. SDF files can contain pre-layout timing data, path constraints, post-layout timing data, and more. The name of each SDF file is determined by the EDA tool that generates it.

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    hold and setup violation and SDF

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    The document discusses the Standard Delay Format (SDF) file format. SDF stores timing data generated by EDA tools that can be used throughout the design process. It represents timing information like delays, timing checks, and timing constraints in a tool-independent way. SDF files can contain pre-layout timing data, path constraints, post-layout timing data, and more. The name of each SDF file is determined by the EDA tool that generates it.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    308 views2 pages

    Hold and Setup Violation and SDF

    Uploaded by

    Ilaiyaveni Iyandurai
    The document discusses the Standard Delay Format (SDF) file format. SDF stores timing data generated by EDA tools that can be used throughout the design process. It represents timing information like delays, timing checks, and timing constraints in a tool-independent way. SDF files can contain pre-layout timing data, path constraints, post-layout timing data, and more. The name of each SDF file is determined by the EDA tool that generates it.

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    Hi,

    First I will ans why hold violation come into picture?

    Look into basic definition of hold time and it's minimum amount of time data should be
    stable after the clock edge.

    It's just an English statement but let's try to understand what is logic behind that when u
    launch a data and once it reaches FF how does a FF will know that it's 1 or 0 (Plz refer
    internal structure of Dff for ref. Using 2*1 mux),so if u refer to FF structure of A FF using
    Mux u can see it's 2 mux connected I m not going in depth of structure now as a VLSI
    engineer u know very well that Any ckt is fundamentally made with help of Transistors
    only . So when u give any I/p to FF then I/p pin capacitance starts charging in a Linear
    manner( U are giving rectangular signal to A capacitance then o/p waveform will be
    ramp signal or triangular),

    And once it get charged fully then u can say it's holding 1 and if it has charger below Vil
    then it's 0 but what if it is in b/w Max threshold and min threshold then it's called
    Metastability and u loose your data bcoz u don't know if it is 1 or 0, that min amount of
    time req to charge ur cap ( i/p cap of CMOS used to finally build ur FF) fully is nothing
    but Hold time.

    So conclusion is that Hold check ensure

    SDF stands for Standard delay format.

    It gives information on the timing data extensively used in backend VLSI design flows.

    SDF gives information about

    1. Path delays
    2. Interconnect delays
    3. Timing constraints
    4. Tech parameters affecting delays
    5. Cell delays.
    6. SDF file is also used in the back annotation of delays in the gate level
    simulations for mimicking the exact Si behavior.

    What is Standard Delay Format (SDF)?

    SDF stands for the “Standard Delay Format”.

    It stores the timing data generated by EDA tools for use at any stage in the design
    process. It can be used anywhere in the flow as to import or export the timing
    information about design.

    The data in the SDF file is represented in tool independent way and can include:

    1. Delays: Module path delay, device delay, interconnects delay and port delay.
    2. Timing checks: Setup, hold, recovery, removal, skew, width, period and no
    change.
    3. Timing constraints: Path, skew, period, sum and diff.
    4. Timing environment: Intended operating timing environment.
    5. Incremental and absolute delays.
    6. Conditional and unconditional module path delays and timing checks.
    7. Design/Instance specific or type/library specific data.
    8. Scaling, environmental and technology parameters like, Process variations,
    temperature, voltage and wire load models.

    Throughout the design process, you can use several different sdf files. Some of these files
    can contain pre layout timing data. Others can contain path constraint or post layout
    timing data.

    The name of each sdf file is generated (determined) by EDA tool. There are no
    conventions for naming SDF files.

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