1

Design of a telescopic fully-differential OTA

Aseem Sayal, Student Member, IEEE, and Vipul Goyal

 pole deteriorate settling performances of operational amplifier,

Abstract— This paper deals with the design of a low power even though it does not noticeably affect the frequency
fully differential telescopic operational transconductance response. In addition, the design of common-mode feedback
amplifier to meet the required specifications. This circuit can be circuit has always been a difficulty in designing operational
used for various low power applications. A comprehensive circuit
designing and methodology approach analysis is performed and
amplifier,
shown. The functionality of the proposed circuit is verified In this paper, a two-stage telescopic cascade OTA is
through simulations in Cadence ADE Virtuoso environment designed employed common mode feedback which is a good
using 0.18𝜇m CMOS process model parameters. The solution to the output common-mode level shifting problem as
performance evaluation is performed and compared with well as stability of the common mode output voltage. The
analytical values to determine the correctness of circuit. The target is to design an operational Transconductance amplifier
performance is also compared with target design specifications
which can meet the required design specifications.
and all the specifications are met with a good margin.
This paper is organized as follows. Telescopic OTA circuit
Index Terms— Biasing, Common mode feedback (CMFB), design is described in section II. Section III presents the
Operational Transconductance amplifier (OTA), Telescopic design methodology approach and major tradeoff
architecture. considerations. Section IV describes the analysis of important
design parameters. Section V gives the simulation results to
verify the functionality of the designed circuit. The
I. INTRODUCTION performance of the circuit is described by Section VI. The
work is concluded in section VII.
T he operational transconductance amplifier (OTA) is the
block with the highest power consumption in analog
integrated circuits in many applications. Low power II. CIRCUIT DESIGN AND ITS DESCRIPTION
consumption is becoming more important in handset devices,
so it is a challenge to design a low power OTA. There is a This section provides the description of the designed OTA.
tradeoff between speed, power, and gain for an OTA design Compared with single-ended output operational amplifier,
because usually these parameters are contradicting parameters. fully differential amplifier employs two-stage topology, which
There are three kinds of OTAs: two stage OTAs, folded has a lot of advantages, for example no influence of common
cascode OTAs, and telescopic OTAs. The telescopic amplifier mode noise, more high linearity and reducing even harmonic
consumes the least power compared with the other two interference, so we employ the two-stages fully differential
amplifiers, so it is widely used in low power consumption telescopic cascode structure [5][6]. The first stage uses the
applications [1][ 2]. telescopic structure with cascade stages amplifier which
Besides low power applications, OTA is the core module of ensures the main high gain as to achieve specifications
the sample and hold circuit. The intrinsic MOS transistor gain required. However, there are five MOS transistors from the
is limited as transistors dimension is scaling down and power to the ground, and then they limit the output swing, so
operating voltage is reducing. Designing high-gain and high- the second stage employs common source topology to obtain
speed operational amplifier is becoming increasingly high output swing [7]. And in order to ensure amplifier have a
challenging. [3][4]. The main bottleneck is that there is a good frequency characteristics, Miller compensation capacitor
tradeoff between speed and gain, because high dc gain and nulling resistor are set between first-stage and second
demands a multistage design with long-channel devices, a low stage, the common-mode feedback circuit for every stage are
bias current levels; whereas the high-speed demands single designed to stabilize the common mode output voltage. The
stage design, short-channel devices, a high bias current levels. following sub-sections provide description on each of these.
But there have been several approaches to resolve this
conflict, gain-boosting technique is one of these approaches to
solve this problem in the condition that the auxiliary amplifier A. Telescopic two-stage OTA
is designed reasonably, otherwise, the introduction of zero-
Fig. 1. shows the fully differential double stage telescopic
A Sayal, was with Qualcomm. He is now with University of Texas, Austin, cascade architecture based OTA. The input stage deploys
TX 77005 USA. (e-mail: aseem.sayal@utexas.edu, website: aseemsayal.in). NMOS transistors and the first stage comprises of 5 and use
V. Goyal was with Texas Instruments. He is now with University of Texas,
Austin, TX 77005 USA. (e-mail: vipul.goyal@utexas.edu). markup styles. The node voltages and current in all the
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Fig. 2. CMFB loop

Fig. 1. Telescopic OTA architecture

branches are marked. The transistors MT1 and MT2 form the
input stage of telescopic OTA. Transistors MT2-MT6 are
deployed as cascade stages to amplify the gain of first stage
and increase the output impedance to shift dominant pole at
lower frequency. Transistors MT7 and MT8 are the active
PMOS loads. The tail current is passed from transistors MT9
and MT10, which is common feedback controlled to stabilize
the stage 2 output common mode voltage. The stage employs
common source PMOS transistors MT11, MT13 and NMOS
transistors MT12 and MT14 serving as active loads. The
PMOS input stage is chosen since; the first stage has 3 NMOS
transistors to ground and 2 PMOS transistors. So, it is difficult
to maintain voltages close to 0.6V-0.7V at the output of first
stage. Hence, PMOS input stage 2 is chosen to ensure that Fig. 3. Biasing Circuit
input common mode range is high. The miller capacitance and
nulling resistors are added to obtain optimum frequency current mirror for biasing transistors MT21, MT23, MT26,
response. MT28 and MT30. The transistors MT21-MT25 are deployed
to bias node voltage VBB1 which ensures minimum voltage
B. Common Mode Feedback Loop difference between transistors MT5-MT7 and MT6-MT8 to
drive them in saturation region. The transistor MT27 forms the
current mirror with the tail transistor to bias. The transistors
The common mode feedback loop is designed to stabilize
MT28 and MT29 are deployed to bias second stage active load
the common mode output voltage. The reference voltage of
transistors MT12 and MT14. To maintain minimum voltage
0.9V is obtained by voltage divider circuit. The differential
difference of VT +2VoV, the transistors MT30-MT33 is deployed
PMOS pair is deployed which adjusts the current based on the
which ensures reliable saturation region operation.
voltage difference between the two branches [8]-[10].
Accordingly, the current is fed to the the tail transistor MT10.
Fig. 2 shows the common mode feedback loop system. The
III. DESIGN METHODOLOGY
common mode loop gain is set by transistors MT16 and MT18.
The total current is drawn through transistor MT15 and is
divided based on differential voltages. Transistors MT17 and This section describes the design methodology and
MT19 forms the current mirror. approach adopted to design fully differential telescopic OTA.
The authors have followed a systematic approach to design the
circuit. The automated MATLAB utilities are developed for
C. Biasing Circuit evaluating parameters using gm/id methodology. Also, various
QA checks are incorporated to ensure that no contradicting
The biasing circuit is shown in Fig. 3. The transistors MT20 assumptions. The utility also determines major design
is connected with ideal grounded current source and is used as tradeoffs related to design specification to ensure optimum
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circuit design and serve as good reference point. This section obtained using long channel and gm/id approach. The results
is divided into 3 sub-sections, each discussing about the are sweeped across range of capacitance values to determine
design approach, automated utilities and checkers, and major the sweet spot. But, the authors have taken this automation as
tradeoffs being taken into consideration. a good reference point and the circuit fine optimization is done
based on simulation results.
A. Design Approach
C. Major Design tradeoffs consideration
The approach involves evaluation of major circuit
parameters using gm/id methodology. The authors have coded The circuit is designed keeping in consideration the design
the main equations in MATLAB environment to eliminate any tradeoffs. Table I lists down the major design decisions being
calculation errors. Also, this reduces design effort to lot of taken into consideration.
extent by providing a good starting point. The flow chart of
design approach is shown by Fig.4. The circuit parameters are TABLE I
calculated as a function of stage 1 input current. The approach DESIGN DECISIONS AND TRADEOFFS
involves 3 main stages – evaluation, checker and tradeoffs. At Decision Reason
the end of execution, a summary is obtained which proved to Telescopic architecture Power and output swing tradeoff
be very helpful. Once, the device parameters are decided, the PMOS second stage To improve input common mode range
circuit simulation is performed and sizing is tweaked to further CMFB loop Common mode stable and power tradeoff
improve the performance. The common efficient circuit 2 stage design To achieve high output swing
Fully differential Output swing and power tradeoff
design approaches are adopted as well. Stage 2 current Slewing rate
Miller cap + nulling res To increase the phase margin
Choice of Cc Noise, speed and power tradeoff
Choice of CL Slew, speed and noise tradeoff
Choice of C1 and C2 Speed and noise tradeoff
CMFB loop current Stability and CMFB loop gain
Choice of RZ Phase margin and power tradeoff
Summing with resistors Gain and power tradeoff
Biasing circuit Power and performance tradeoff

IV. DESIGN ANALYSIS

In this section, the analysis of major design parameters is
performed to analyze the circuit performance.

A. Gain Analysis

The open loop gain of a telescopic cascade two stage OTA

is product of gain of both the stages and is given by (1).

OverallGain  Gainstage1 * Gainstage 2 (1)

The stage 1 and stage 2 gains are given by (2) and (3)
respectively. The values of gmrn, gmrp, and other required
Fig. 4. Design approach flowchart parameters are calculated using gm/id methodology.

B. Automated Utilities & QA Checkers   

Gainstage1  g m1 *  rn1 *  g m3 rn 3   || rp 7 *  g m 5 rp 5   450.9 (2)

The automated utility is developed in MATLAB Gainstage 2  gm11 *(rp11| || rn12 ))  50.7 (3)
environment to ease the design process by eliminating any
calculation errors and saving design effort and time. The main
features include accurate calculation of widths and lengths OverallGain  450.9*50.7  87.18dB (4)
based on biasing conditions, checks to ensure that required
specifications are met and the assumptions considered for The transistors of the second stage are biased in such a way
biasing are met. In the approach, to ensure proper biasing and to maximize the output swing. The gm/id of transistors in
high power efficiency, the transistors are assumed to bias at telescopic stage and second stage are kept high, in range of
low over-drive voltages and accordingly expressions are 15-20 to save power by biasing them in weak overdrive
region.
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B. Frequency Analysis   kT  g m3    kT   g m5    (13)

  1     1   1      1.5473e  8
2
vntot
  CC  g m1    CLtot   g m 7   
The frequency analysis is performed to determine the closed
loop bandwidth, phase margin and stability of system. The
values of C1 and C2 as per specifications handout are kept as
vrms  2* vntot
2
 175.78uV (14)
0.5pf. The feedback factor is given by (5).

C2 0.5 p (5)
   0.491 V. SIMULATION RESULTS
C1  C2  Cgg1 0.5 p  0.5 p  18.47 f

where Cgg1  W1L1COX  18.47 fF (6) This section presents the simulation results of the designed
telescopic OTA employing CMFB. The simulations are
performed using 0.18µm CMOS process parameters in
The closed loop bandwidth is evaluated by (7). The
Cadence Virtuoso ADE environment. The supply voltage VDD
dominant pole is less than 1KHz and non-dominant pole sits at
frequency around 125MHz, evaluated in (8). The overall is 1.8V. As per the design specifications, the value of C1 and
phase margin of system is given by (9). C2 are kept equal, both at 0.5pf. The load capacitor value is set
at 1.2pf, which is higher than 1pf as per the specification. The
miller capacitance Cc is set at 1.3pf and nulling resistor Rz is
 g m1 0.491*641u (7) kept at 0.47kΩ, which is greater than 1/gm2. The transistors
fc    30.53MHz
2 CC 2 *1.3 pf aspect ratios are listed in Table II.
(8)
gm2 TABLE II
f p2   125.7 MHz
 C (C  (1   )C2 )  ASPECT RATIO OF MOSFETS IN OTA
2 *  Cgg 2  (CL  (1   )C2 )  gg 2 L 
 CC 
MOSFET W(µm)/L(µm)
MT1, MT2 7.2µm/0.18 µm
 f p2  1  125.7  (9) MT3, MT4 10.2µm/0.18 µm
PM  tan 1    tan    76.43
o
MT5, MT6, MT7, MT8, MT20 63.063µm/0.48µm
 c 
f  30.53 
MT9 9.6µm/0.48µm
MT10, MT17, MT19 2.4µm/0.48µm
MT11, MT13 360.8µm/0.18µm
C. Transient Analysis MT12, MT14 57.84µm/0.48µm
MT15 90µm/0.48µm
The transient analysis is performed to determine the settling MT16, MT18 100µm/0.18µm
MT21 1.576µm/0.48µm
time, static error and dynamic error of the system. The loop
MT22, MT25, MT27 0.724µm/0.48µm
gain of the OTA is expressed by (10). MT23, MT24, MT26 6.306µm/0.48µm
MT28, MT30 12.613µm/0.48µm
Loopgain(To )   (openloopDCgain)  0.491*22860.63  81dB (10) MT29 5.258µm/0.48µm
MT31 1.44µm/0.18µmm
MT32, MT33 0.48µm/0.18µm
The static error is inverse of the loop gain and is expressed
by (11). The settling time is also calculated for 0.08%
dynamic settling error time and is expressed by (12). The following sub-sections illustrate the simulation results
obtained in DC, AC, stability, transient, and noise analysis.
1 (11)
StaticError   0.00491%
Loopgain(To ) A. DC Analysis

1   C2  (12) The dc gain and offset analysis is performed and differential

ts  ln   dtotal 1      37.98ns
wc   C2  Cc  voltage Vd is swept for the complete output swing range. A
1000 point fine parametric sweep is performed to obtain input-
referred offset Voffset, differential-mode gain ADM) and output
D. Noise Analysis swing. The procedure is repeated for range of input common
mode voltages VCM. Fig. 5. shows the output range and 3dB
The noise analysis is performed to determine the noise due gain plot with the offset voltage. The offset voltage is 1.856pV
to first and second stage. The value of  is kept as 0.67. The and the ADM come out to be 86.61dB. The output swing from
other remaining parameters are determined using gm/id the analysis comes out to be [-1.357, 1.357]. The input
methodology. The noise at single ended output is given by common mode range is plotted in Fig. 6. The power
(13). The integrated noise for fully differential OTA will be dissipation of design is also evaluated by connecting no signal
twice of single ended configuration. The output rms noise to input and observing the current from VDD power rail.
voltage is expressed by (14).
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Fig. 7. Common mode rejection ratio

Fig. 5. Open loop DC gain and output swing

Fig. 8. Power Supply rejection ratio

Fig. 6. Input Common-mode range

B. AC Analysis

The AC analysis is performed to observe the CMRR and

PSRR response of the OTA. The CMRR value is obtained by
ADM - ACM. ADM is evaluated from DC analysis and ACM is
calculated from AC analysis by calculating the ac magnitude
at 1Hz. Similarly, PSRR is obtained by evaluating ADM - AVDD
where AVDD is obtained by calculating AC gain at 1Hz. The
values of CMRR and PSRR come out to be 110.45dB and
92.17dB respectively. Fig. 7. and Fig. 8. show the CMRR and
PSRR plots as function of frequency. Fig. 9. Magnitude and Phase response

C. Stability and Frequency Analysis

The stability analysis is performed for the OTA in closed

loop. Due to input configuration, signal is passed from a high
pass filter and extra pole and zero is introduced which can be
ignored. Fig. 9. shows the phase and loop gain plot. The loop
gain of the OTA is 80.32dB and phase margin is 76.80o. The
non-dominant pole is at 126.80MHz. The closed loop
bandwidth or closed loop unity gain frequency is 29.71MHz.

D. Transient Analysis Fig. 10. Settling Time going up

The transient analysis is performed to meet the settling time, for output going down and shown in Fig. 12. and Fig. 13.
dynamic and static error specification. Fig. 10. shows the Since the loop gain is quite high, the static error comes out to
transient response of the output going up. The zoomed version be very low, 0.005% whereas dynamic error comes out to be
of the plot is shown in Fig. 11. Similarly, the plots are shown 0.08% at settling time of 39.01ns.
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TABLE III
ANALYTICAL VS SIMULATED CHARACTERISTICS OF OTA

Calculated Simulated Error

Characteristics
Value Value (%)
OTA open-loop DC gain 87.18dB 86.61dB 0.65%
Closed loop bandwidth 30.53MHz 29.71MHz 2.68%
Loop Gain 81.18dB 80.32dB 0.98%
Phase Margin 76.43o 76.80o 0.48%
Static settling error 0.00492% 0.005% 0.20%
Settling Time 37.98ns 39.01ns 2.72%
Total output noise (rms) 175.78µ 176.12µ 0.19%
Fig. 11. Zoomed plot of settling time going up
TABLE IV
PERFORMANCE CHARACTERISTICS OF OTA

Target
Characteristics Result
Specification
C1 = C2 = 0.50pf, CL
Capacitive load (C1 = C2, CL ≥ 1pF)
= 1.20pf, Cc = 1.3pf
OTA open-loop DC small-signal gain 86.61dB
Static settling error ≤ 0.1% 0.005%
Dynamic settling error ≤ 0.1% 0.08%
Input referred offset < 10 µV 1.86pV
Minimum output swing [0.3V, 1.5V] [-1.36V, 1.36V]
Input common-mode range [0.69V, 1.63V]
Closed-loop unity gain frequency 29.71MHz
Fig. 12. Settling Time Going down Phase margin > 45o 76.80o
Settling Up < 40ns 39.01ns
Time Down < 40ns 39.01ns
CMRR at DC > 60dB 110.45dB
PSRR at DC > 60dB 92.17dB
Total output noise (rms value) ≤ 200µV 176.12µV
Total power consumption Minimize 733.10µW

The capacitor values are kept in range to meet the optimum

performance. The open loop DC small signal gain of OTA
comes out to be 86.61dB. Due to high loop gain, the static
settling error value comes out to much lesser than the target
Fig. 13. Zoomed plot of settling time going down value of 0.1%. Since the configuration is fully differential, the
input offset comes out to be 1.86pV and meets the
E. Noise Analysis specification by large margin. The output range also becomes
double and comes out to be ±1.357V. The input common
The noise analysis is performed to calculate the integrated mode range for this architecture comes out to be [0.69V,
noise for the fully differential OTA. The integrated noise 1.63V]. The closed loop unity gain frequency comes out to
comes out to be 3.108e-8 V2 for frequency range of 1KHz- be 29.71MHz with a low settling time of 39.01ns, lower than
10GHz. The output rms value of noise calculated from the the target specification. The circuit design is quite stable and
integrated noise comes out to be 176.12µV. phase margin comes out to be 76.25o. The output noise rms
value for both differential outputs comes out to be 176.12µV,
which is 12% lesser than the target value. The circuit is having
VI. PERFORMANCE EVALUATION high common mode rejection ratio (CMRR) and power supply
The performance of the designed circuit is presented in this rejection ratio (PSRR) with values of 110.45dB and 92.17dB
section. The simulated values obtained in section IV is respectively, making it suitable to use at front end of any
compared with the simulated values obtained in section V. circuit to suppress common mode and power supply noise.
The values are compared with the simulated values and % Besides meeting all the target specifications with a good
error is calculated to prove that simulated results match margin, the circuit power consumption is minimized and
closely with the calculated values. Table III lists the comes out to be 733.10µW. All these specifications, i.e. low
comparison of major design parameters. The results obtained power, low noise, high gain and input common mode range,
from the simulation are also compared with target high CMRR, PSRR, phase margin makes this circuit a good fit
specifications, and are summarized in Table IV. All the for various applications like sensor nodes, pipelined ADCs,
specifications are met with a good margin while optimizing signal conditioning etc.
the power to the optimum level.
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VII. CONCLUSION REFERENCES

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ACKNOWLEDGMENT [9] David Johns and Ken Martin, Analog Integrated Circuit Design, Wiley,
The authors are grateful to Prof. Nan Sun, University of 1996.
[10] Adel Sedra and Kenneth Smith, Microelectronic Circuits, Oxford, 2009.
Texas, Austin for giving an opportunity to improve our circuit
designing skills. The authors would also like to thank Julio
Acosta, Senior Design Manager, Texas Instruments and K.R.
Raghunandan, Design Engineer, Silicon Labs for their helpful
remarks. The authors also appreciate the help of teaching
assistants Shaolan Li and Yeonam Yoon in debugging issues.