The CMOS Inverter as a comparator in ADC designs

Ali TANGEL , Kyusun CHOI

1 2

Department of Electronics&Communication Engineering

1

University of Kocaeli, 41040 Izmit, Turkey

2
Department of Computer Science& Engineering
The Pennsylvania State University, University Park, PA16802 USA

Abstract--This paper introduces a single-ended non-offset- 3. It requires a separate 5V reference power supply
cancelled flash ADC architecture, the "Threshold Inverter voltage for analog part only due to poor power
Quantizer" (TIQ). The TIQ is based on a CMOS inverter supply rejection ratio.
cell, in which the voltage transfer characteristics (VTC) are 4. It has slight changes in linearity measures (DNL,
changed by systematic transistor sizing. As a result, a
INL) and the maximum analog input signal range
significant improvement of speed and reduction of area and
power consumption is achieved. due to process parameter variations. These problems
can easily be handled by front end signal
I. INTRODUCTION conditioning circuitry.
5. It requires a S/H at the analog input to increase the
Although the full-flash type A/D converter architecture is performance and to reduce the power consumption
the most attractive solution for high-speed A/D converter during metastable stage.
designs, from a power dissipation and area perspective it
is not efficient for the resolution of more than 8-bits. As The following sections include the simulation (0.8-
long as the resolution level is kept small, the comparator micron simulation only) and test (2-micron fabricated)
count will be reasonable, and its offsets are not critical. results for the TIQ approach.
Therefore the comparator structure is the most critical
part in full-flash type architectures. There are primarily II. THE TIQ STRUCTURE
three types of comparator structures used in A/D
converter designs in the literature. The differential The TIQ consists of two cascaded CMOS inverters as
amplifier type, dynamic (auto-zero), and the fully shown in Fig. 1 (a). The analog input signal quantization
differential latch-type comparators are commonly used level is set in the first stage by changing the voltage
structures in CMOS flash A/D converter designs [1], [2], transfer curve (VTC) by means of transistor sizing [5].
[3], [4]. Since the transistor channel length, L, is more effective
than the channel width, W, in controlling the performance
Some of the main problems of the conventional (fT a 1/L2), L is kept constant and only W is changed
comparator structures used in A/D designs can be listed during the design process.
as follows:
1. large transistor area for higher accuracy The second inverter stage is used for increased gain and
2. DC bias requirement logic level inversion so that the circuit behaves as an
3. charge injection errors internally set comparator circuit. The key point with the
4. metastability errors second stage is that the second stage must be exactly the
5. high power consumption same as the first stage to maintain the same DC threshold
6. resistor or capacitor array requirement levels, and to keep the linearity in balance for the voltage
rising and falling intervals of high frequency input
In this paper, however, a new approach, the Threshold signals.
Inverter Quantizer (TIQ), based on systematic transistor
sizing of a CMOS inverter in a full-flash scheme, It can be shown that the Vth point on the VTC of a
eliminates the resistor array implementation of CMOS inverter, which is shown in Fig. 1 (b), can
conventional comparator array flash designs. Therefore approximately be given by the following equation [6],[7]:
no static power consumption is required for quantizing
the analog input signal, making the idea very attractive Vdd -|Vtp|+Vtn Kn / Kp
for battery-powered applications. However there are five Vth =
main disadvantages of the TIQ approach: 1 + Kn / Kp
1. It is a single-ended structure.
2. It requires 2n -1 number of different area-sized where Vtn and Vtp are the threshold voltages for
quantizer designs. NMOS and PMOS devices, respectively; and
Kn = (W/L)n . mn Cox
Kp = (W/L)p . mp Cox. 4. Calculate the ideal threshold points for each
quantizer (Qn-m Qn+p) accordingly, assuming the
However due to non-ideal effects such as short channel midpoint value for Qn is in the center.
and narrow channel effects, the above equation cannot be 5. Run the HSPICE simulator to obtain the
practical for the design process, therefore higher level corresponding closest possible channel widths. Note
MOS transistor model equations are necessary. In this that for the quantizers of Qn+1 Qn+p), the so-called
study, the BSIM3 [8] model in which the effective PMOS side, (W/L)n is kept at minimum value, but
threshold voltages are re-calculated after the transistor only the channel widths of the PMOS transistors are
sizing processs to handle these non-ideal effects such as changed to minimize the current flow during the
narrow channel effects [8]. The HSPICE circuit transition of VTC (metastable region). This process
simulation is used to determine the proper transistor sizes is applied to the NMOS side in the opposite way.
together with a computer program automatically. 6. Lay out the entire circuit.
7. Replicate this entire quantizer block and complete
the interconnections to obtain the cascaded structure,
which will be the analog part of the entire A/D
Vdd Vo1,Vo2
converter.
Vo1 Vo2
One can easily conclude that the designer cannot achieve
Vin Vo1 Vo2 the desired theoretical ratios by having a minimum
sensitivity of only one lambda unit area change on the
layout and also due to possible errors during fabrication
process. Hence the analog input range and the linearity
measures (DNL and INL) are affected by these nonideal
Stage1 Stage2 Vth Vin factors. However the monotonicity of the converter is
expected to be maintained.
Fig. 1 (a) TIQ schematic (b) Voltage transfer curve (VTC)
III. RESULTS FOR TIQ4 DESIGNS THE
SIMULATION AND TEST
The design steps obtained from a computer program can
be explained by referring to Fig. 2 as follows: The design process explained above has been applied to
design the TIQ4 in two different technology, 2m
1. Design a minimum size inverter and verify the (fabricated) and 0.8m (simulation only) CMOS n-well.
threshold voltage value of the midpoint quantizer,
Fig.3 shows the DC simulation results for the TIQ4 in
Qn, using the HSPICE circuit simulator by
0.8m design. Simulation results include 0.27 LSB of DNL
substituting BSIM3 (Level 49) spice model test
and 0.18 LSB of INL for the design of TIQ4 in 2m CMOS
parameters obtained from a vendor for a specific
technology. Note that the channel length is kept at n-well technology, and 0.33 LSB of DNL and 0.22LSB
the minimum value during the entire design process. of INL in 0.8m CMOS n-well technology. These results
neglect additional linearity errors, which may occur in the
2. Estimate a safe analog input voltage range as follows: digital part of the complete converter. The largest
Analog range = Vdd - (VTN + | VTP|), where VTN transistor size in the TIQ4 is only (W/L)n= (24m/2m) in
and VTP are the threshold voltages for large NMOS the 2m design.
and PMOS devices, namely the VTHO value from the
model parameter data set used during the entire design In AC operation, by employing a S/H at the input, a
process. Nyquist sampling rate of 300 MHz for TIQ4 has
been

Wn increase Wn=Wp Wp increase

Qn-m Qn-1 Qn Qn+1 Qn+p

Fig. 2 Block diagram of the design process

3. Calculate the LSB value as follows:

LSB = Analog range/ 2n.
Fig. 3 TIQ4 (0.8m) threshold levels
 TABLE II. COMPLETE TIQ4 BASED ADC SUMMARY
(TEST RESULTS)

DNL 0.65 LSB

INL 0.34 LSB
Input Voltage Range 1.65Vpp
Static power dissipation 0.4mW
Active chip area 0.4mm2
Sampling rate 100 MHz
Technology 2-micron CMOS n-well
Power supply 5V
Fig. 4 TIQ4 (0.8m) AC operation for a 300MHz sampling rate

The layout photo for the complete ADC is shown in

achieved. This maximum sampling rate reduces to 100 Fig.6.
MHz for the 2m design. Simulation measurements are
taken under ideal sampling conditions. In fact, the S/H
circuit design is not included in this study. Fig. 4 shows
the AC operation at the maximum sampling rate for the
TIQ4. The DC and the AC results are also tabulated in
Table I.

TABLE I SIMULATION RESULTS FOR TIQ4

(ANALOG PART ONLY)

TIQ4(2m) TIQ4(0.8m)
DNL (LSB) 0.27 0.33
INL (LSB) 0.18 0.22
Sampling Rate (MHz) 100 300
Avg. Power (mW) 3.35 4.86
Chip area (mm2) 0.035 0.006 Fig.6 Layout photo of TIQ4 based ADC
Analog Range (Vpp) 1.72 2.7

Fig. 5 and Table II show the worst case linearity plots IV. THE DESIGN OF TIQ6 AND SIMULATION
(INL and DNL) and performance summary for the
RESULTS
fabricated four sample TIQ4 (in 2m n-well CMOS) chips,
respectively. In the design process explained previously, keeping the
0,75
one side transistors sizes at their minimum value
0,5
simplifies the design process and reduces the power
DNL(LSB)

0,25 consumption. However after substituting a typical process

0 parameter data set in Equation 1, one will see that the
-0,25 maximum resolution level that can be achieved is only 4-
-0,5 bits. This is because only one lambda-unit channel width
-0,75
change between mid-point quantizer (where Wn is equal
Code number to Wp) and its neighbors results in about 150 milivolts of
minimum achievable voltage step, namely the Least
(a) Significant Bit (LSB) value.

0,75 We next introduce a modification of the TIQ design

0,5 process, in which basically the both transistor channel
INL(LSB)

0,25 widths are allowed to change at the same time to obtain

0 the closest threshold point to the desired one. This leads
-0,25
to a maximum achievable resolution level of 8-bits. The
-0,5
new design methodology is obviously more complicated
-0,75
than the former one, and requires larger transistor sizes,
Code number and surely consumes more power. However the design
has automatically been done by a developed computer
optimization program [5]. Figs. 7 and 8 show the DC and
(b) AC simulation results of the TIQ6 design as an example.
Note that the TIQ6 has peak current of 15mA at
Fig.5 (a) Differential non-linearity plot (b) Integral non -linearity plot
maximum sampling rate.
 These simulation results show that the analog input range
is affected only by process parameter changes. However
the linearity measures are still in an acceptable range,
which keeps the converter monotonic. This is because a
converter is always monotonic as long as the INL is
maintained at less than 0.5 LSB [9].

The second important issue is of course the matching

properties on the wafer. Due to non uniform distribution
of the dopant atoms in the bulk, threshold voltage
Fig. 7 The TIQ6 threshold levels mismatch in both PMOS and NMOS devices of large and
small geometry must also be considered [10] . In fact,
according to the DC linearity test measures taken on four
different fabricated sample chips, matching non-idealities
are less important in this new approach as long as the
resolution is kept at small levels (currently less than 7-bit)
as shown in Fig.10, in which the maximum deviation of
threshold points due to mismatching is less than 20mV.

3,5

3
Threshold levels

Sample1
2,5
Sample2
Fig. 8 The TIQ6 AC operation for 200MHz sampling
2 Sample3
Sample4
V. ANALYSIS OF PROCESS PARAMETER 1,5
VARIATIONS
1
It seems that the main drawback with the TIQ approach is 0 5 10 15
that it is process parameter dependent. To analyze this Code number
effect the three critical size inverters (N-size maximum,
N and P-size minimum, and P-size maximum) are chosen
Fig. 10 TIQ4 matching test results over four sample chips
and simulated for six different 0.8m Spice parametric test
results obtained from the vendor. Fig. 9 shows the Finally, temperature effects have also been investigated,
random changes on the corresponding three different and the simulation result indicate a safe temperature
threshold points. The simulation results shows that the range of between -40 and 85 C [5]. The temperature
maximum deviation due to process parameters is in the effect becomes important for more than 7-bits resolution
range of 90mV, and occurs in the minimum size inverter. levels.
To analyze the effect of this change on the linearity VI. CONCLUSION
measures, the original design of TIQ6 has also been
simulated for the process parameters provided by a A new analog technique so called TIQ for FLASH type
vendor for six other Spice parametric test results without A/D converters has been developed and simulated in two
making any changes in the beginning TIQ6 layout. different technologies (0.8m and 2m CMOS n-well), and
also 3-bit and 4-bit versions of TIQ based A/D converters
have been fabricated in 2m CMOS n-well technology as a
supporting work for the new approach. Simulation and
test results show that this technique is much more area
and power efficient when compared to conventional
comparator-array structures of comparable performance
[2], [4], [11], [12], [13], [14], [15]. Traditional methods
have been applied to the remaining (digital) part of the
converter.

Fig. 9 Process parameter change

In conclusion, this proposed scheme has the following
advantages when compared to traditional comparator REFERENCES
based designs:
[1] A. Tukawa, A CMOS 8-Bit High-Speed A/D Converter IC,
1. There is very little static power consumption IEEE J.Solid-State Circuits, Vol. SC-20, pp. 775-779, June 1985
excluding the S/H at the input. This makes the idea [2] A. G. F. Dingwall, and V. Zazzu, An 8-MHz CMOS Subranging
very attractive for battery-powered applications. 8-Bit A/D Converter, IEEE J.Solid-State Circuits, Vol. SC-20,
pp. 1138-1143, Dec. 1985
2. If a S/H is employed at the input, the TIQ is a more
[3] T. Cho, and P. R. Gray, A 10b, 20Msample/s 35mW Pipeline
power and performance efficient method. A/D Converter IEEE J. Solid-State Circuits, Vol. 30, pp.166-171,
3. The TIQ doesnt require a resistor array March 1995.
implementation. [4] W. Song, H. Choi, S. Kwak, and B. Song, A 10-b 20-Msample/s
Low Power CMOS ADC, IEEE J. Solid-State Circuits, Vol. 30,
4. A significant amount of area reduction can be
pp. 514-520, May 1995.
obtained. [5] A. Tangel, VLSI Implementation of the Threshold Inverter
5. Monotonicity is always expected to be maintained. Quantization (TIQ) Technique for CMOS Flash A/D Converter
Applications PhD Dissertation, The Pennsylvania State
TIQ3 and TIQ4 can be used as a building block for semi- University, Aug. 1999.
[6] A. S. Sedra, and K. C. Smith, Microelectronic Circuits, Oxford
flash [2], pipeline [3], [4], [15],[16] or folding [11], [17] University Press, New York, 1998.
types of fast A/D converter architectures. As a result, [7] J. Segura, J. L. Rossello, J. Morra, and H. Sigg, A Variable
significant reductions of power and area can be achieved Threshold Voltage Inverter for CMOS Programmable Logic
Circuits, IEEE J. Solid-State Circuits, Vol. 33, pp. 1262-1265,
even higher than 8-bit resolution levels. It is also
Aug. 1998.
projected that a TIQ-based complete A/D converter [8] D.Foty, Mosfet Modeling with PSPICE, (Prentice Hall,1997).
library cell could be put on a microprocessor chip, [9] R. J. Van de Plassche, Integrated Analog to Digital and Digital to
leading to a more compact DSP VLSI integration. Analog Converters, Kluwer Academic Publishers, 1994.
[10] M.J.M Pelgrom, C.J.Duinmaijer, A.P.G. Welbers,Matching
Properties of MOS Transistors, IEEE J. Solid-State Circuits,
Vol.24, pp. 1433-1439, Oct. 1989.
[11] B. Nauta, and A. G. Venes, A 70-MS/s 110mW 8-b CMOS
Folding and Interpolating A/D Converter, IEEE J. Solid-State
Circuits, Vol. 30, pp. 1302-1308, Dec. 1995.
[12] G. M. Yin, F. Eynde, and W. Sansen, A High-Speed CMOS
Comparator with 8-b Resolution IEEE J. Solid-State Circuits,
Vol.27, pp. 208-211, Feb. 1992.
[13] J. Spalding, and D. Dalton, A 200Msample/s 6b Flash ADC in
0.6m m CMOS , IEEE International Solid-State Circuits
Conference, 1996, pp. 320-321
[14] C. L. Portmann, and T. H. Meng, Power-Efficient Metastability
Error Reduction in CMOS Flash A/D Converters, IEEE J. Solid-
State Circuits, Vol. 31, pp. 1132-1139, Aug. 1996.
[15] K. Nakamura, M. Hotta, L. R. Carley, and D. J. Allstot, An
85mW, 10-b, 40 Msample/s CMOS Parallel-Pipelined ADC,
IEEE J. Solid-State Circuits, Vol. 30, pp. 173-182, March 1995.
[16] D. W. Cline, and P. R. Gray, A Power Optimized 13-b 5
Msamples/s Pipelined Analog-to-Digital Converter in 1.2 mm
CMOS, IEEE J. Solid-State Circuits, Vol. 31, pp. 294-303,
March 1996.
[17] A. G. Venes, and R. J. Van de Plassche, An 80MHz, 80-mW, 8b
CMOS Folding A/D Converter with Distributed Track-and-Hold
Preprocessing, IEEE J. Solid-State Circuits, Vol. 31, pp. 1846-
1853, Dec. 1996.