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VHDL Code For Half Adder Using Three Modeling

The document describes three VHDL code implementations of a half-adder circuit: 1) a dataflow model that assigns sum and carry outputs directly using logical expressions, 2) a behavioral model that encapsulates the logic in a process, and 3) a structural model that instantiates XOR and AND components to compute the outputs.

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139 views

VHDL Code For Half Adder Using Three Modeling

The document describes three VHDL code implementations of a half-adder circuit: 1) a dataflow model that assigns sum and carry outputs directly using logical expressions, 2) a behavioral model that encapsulates the logic in a process, and 3) a structural model that instantiates XOR and AND components to compute the outputs.

Uploaded by

Keertana
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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VHDL Code for a Half-Adder

Logical Expression: Sum = A XOR B, Carry = A AND B

 Dataflow Modeling

Library ieee;
use ieee.std_logic_1164.all;

entity half_adder is
port(a,b:in bit;
sum, carry:out bit);
end half_adder;

architecture HA of half_adder is
begin
sum<= a xor b;
carry <= a and b;
end HA;

a) Behavioral Modeling

Library ieee;
use ieee.std_logic_1164.all;

entity half_adder is
port(a,b:in bit;
sum, carry:out bit);
end half_adder;

architecture HA of half_adder is
begin

process (a,b);
sum<= a xor b;
carry <= a and b;
end process;

end HA;

b) Structural modeling

Library ieee;
use ieee.std_logic_1164.all;

entity half_adder is
port(a,b:in bit;
sum, carry:out bit);
end half_adder;

architecture HA of half_adder is

component xor2
port(a, b: in bit;
y:out bit);
end component

component and2
port(a, b: in bit;
y:out bit);
end component

begin
o1: xor2 portmap(a,b,sum);
o2:and2 portmap(a,b,carry);

end HA

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