Application Note AN-45

LinkSwitch-CV Family
Design Guide

Introduction

The LinkSwitch™-CV family is a highly integrated monolithic a low cost bias circuit. This simplifies meeting harmonized
switching IC designed for off-line power supplies up to 17 W. energy efficiency standards.
Ideally suited for DVD player and Set-top box applications,
LinkSwitch-CV provides constant voltage without using an Basic Circuit Configuration
optocoupler or secondary feedback circuitry. ON/OFF control
optimizes efficiency across load and line, while meeting no-load The circuit shown in Figure 1 shows the basic configuration of a
and power supply efficiency standards. three output flyback power supply designed using LinkSwitch-CV.
Because of its high level integration, LinkSwitch-CV leaves far
Each member of the family has a high-voltage power MOSFET fewer design issues to be addressed externally, resulting in one
and its controller integrated onto the same die. Internal start-up common circuit configuration for all applications. For example
bias current is drawn from a high-voltage current source different output power levels may require different values for
connected to the DRAIN pin, eliminating the need for external some circuit components, but the circuit configuration stays
start-up components. The internal oscillator is frequency unchanged.
modulated (jitter) to reduce EMI. In addition, the ICs have
Scope
integrated functions that provide system-level protection. The
auto-restart function limits the dissipation in the MOSFET, the This application note is intended for engineers designing an
transformer and the output diode during overload, output isolated AC-DC flyback power supply using the LinkSwitch-CV
short-circuit and open-loop conditions, while the auto-recovering family of devices. It provides guidelines to enable an engineer to
hysteretic thermal shutdown function disables MOSFET switching quickly select key components and also complete a suitable
during a thermal fault. Power Integrations’ EcoSmart™ technology transformer design. To simplify the task this application note
enables supplies designed around the LinkSwitch-CV family refers directly to the PIXls design spreadsheet that is part of the
members to consume <200 mW of no-load power at 230 VAC PI Expert™ design software suite. The basic configuration used
without an external bias circuit and down to below <70 mW with in LinkSwitch-CV Flyback power supplies is shown in Figure 1.

L1
3.5 × 7.6 mm T1 D8
Ferrite Bead EEL19 UF4003 12 V, 0.1 A
1 6
C9
47 µF R8
R1 25 V 24 kΩ
5.1 kΩ 3 7 L3 1/8 W
D1 D2 1/8 W C3 10 µH
FR106 FR106 820 pF D7 SB540 5 V, 1.7 A
1 kV
11 C8 C10 R7
VR1
R10 C13 1000 µF 470 µF 510 Ω
1N5272B 10 V 10 V 1/8 W
8,9,10 47 Ω 270 pF
C11 R9 RTN
47 µF 39 kΩ
F1 R2 12 50 V 1/8 W
L 3.15 A 390 Ω
D9 -22 V, 15 mA
UF4003
D5 5
85 - 265 C1 C2 1N4007
VAC 22 µF 22 µF D6
400 V 400 V 1N4148
4
N RT1 RV1
10 Ω 275 V
2 R3
6.34 kΩ
D3 D4 LinkSwitch-CV 1%
1N4007 1N4007 U1
LNK626PG
D
FB

BP

R4 R5
S
6.2 kΩ 47 kΩ
1/8 W R6 C6
C4 C5 4.02 kΩ 10 µF
1 µF 680 pF 1% 50 V
L2
680 uH 50 V 50 V
PI-5205-102208

Figure 1. 7 W (10 W peak) Multiple Output Flyback Converter for DVD Applications with Primary Sensed Feedback.

www.power.com December 2017

 Application Note AN-45

In addition to this application note the reader may also find the Output Power Table
LinkSwitch-CV Design Example Report (DER-198) containing
230 VAC ±15% 85-265 VAC
the complete design and test data of the DVD power supply in
Figure 1. Further details on downloading PI Expert and updates Product 3 Peak or Peak or
Adapter1 Open Adapter1 Open
to this document can be found at www.power.com. Frame2 Frame2
LNK623PG/DG 6.5 W 9W 5.0 W 6W
Quick Start
LNK624PG/DG 7W 11 W 5.5 W 6.5 W
Readers who want to start immediately can use the following LNK625PG/DG 8W 13.5 W 6.5 W 8W
information to quickly design the transformer and select the LNK626PG 10.5 W 17 W 8.5 W 10 W
components for a first prototype. Only the information
described below needs to be entered into the PIXls spreadsheet, Table 2. Output Power Table. Based on 5 V Output.
other parameters will be automatically selected based on a Notes:
1. Minimum continuous power in a typical non-ventilated enclosed adapter
typical design. References to spreadsheet cell locations are measured at +50 °C ambient.
provided in square brackets [cell reference]. 2. Maximum practical continuous power in an open frame design with adequate
heat sinking, measured at 50 °C ambient (see Key Application Considerations
section for more information).
• Enter AC input voltage range VACMIN, VACMAX and minimum 3. Packages: P: DIP-8C, D: SO-8C.
line frequency fL [B3, B4, B5]
• Enter Nominal Output Voltage VO [B6], for multiple outputs
• VMIN and VMAX [D40] and [D41] show the minimum and
complete section shown in Figure 13
maximum DC voltages on the input bulk capacitors. It is
• Enter the output power value Po [B7]
calculated by using the AC input parameters [B3], [B4] and
• Enter efficiency estimate [B8] using Table 1 as guidance
the value of CIN [B11]. If a DC input voltage is used, you may
enter the values in cells [B40] and [B41]. Entering values in
Universal 100/115 VAC 230 VAC these cells will overwrite the calculated values.
(85 – 265 VAC) (85 – 132 VAC) (185 – 265 VAC) • The transformer’s feedback winding turns are shown in cell
Single Output (5 V) 0.76 0.76 0.78 [D44]. If necessary entering a different number in cell [B44]
Single Output (12 V) 0.80 0.80 0.82 will change the feedback voltage [D45].
• The feedback resistor values are shown in cells [D46] and
Multiple Output 0.66 0.66 0.68
[D47]. Enter a value in cell [B46] to change these values. It is
Table 1. Initial Efficiency Estimates for a New Design. not recommended to increase the value greater than 2.5 times
the default value. Doing so may activate the open loop
protection circuitry.
Adjust the number accordingly after measuring the efficiency of
• If an external bias circuit is desired to reduce no load input
the first prototype-board at peak load and VACMIN.
power below 200 mW, enter YES in cell [B54]. If not then
• Enter CIN input capacitance [B11]
enter NO.
• 3 µF/W for universal (85-265 VAC) or single (100/115 VAC) line
• If using a bias winding, the recommended bias voltage is
• Use 1 µF/W single 230 VAC for single (195-265 VAC) line
shown in cell [D55]. You may change this voltage by entering
• Note: After selecting the LinkSwitch-CV device (the step
a value in cell [B55]. It is not recommended to use a value
below), if the computed duty cycle [D59] is greater than
lower than 10 V. Cell [D56] shows the number of turns
54%, increase the input capacitance.
required for the bias winding. It is important to note that this
• Select LinkSwitch-CV device from the drop down list or enter
transformer winding must be AC stacked on top of the
directly [B15].
feedback winding (placed in series with the feedback winding).
• Use Table 2 for guidance, selecting a device based on
• Enter in cell [B70] the transformer’s primary inductance
output power, input voltage range and thermal environment
tolerance in percent. The default is 10%.
(open frame or enclosed adapter).
• Verify that the core’s gap LG [D77], the wire gauge AWG [D82]
• Enter VDS [B22], the on-state drain-source voltage drop. Use
and the primary’s winding current density CMA [D84] are
10 V if no better data available.
within acceptable limits.
• Enter the output rectifier’s forward voltage drop VD [B23]. Use
• Use resistor values RUPPER [D46] and RLOWER [D47] for feedback
0.5 for Schottky and 0.7 for PN diode.
resistors.
• Enter the core type from the drop down menu. If the desired
• Using PIVS1 [D115] and IO1 [D109] determine the proper
core is not listed, then you may enter a core’s characteristics AE,
output rectifier.
LE and AL ([B31] [B32] [B33]). Enter the bobbin width BW [B34].
• Using VMAX [D41] and IR [D63] determine the proper input filter
• If margin tape is desired, then enter the margin tape width in
capacitors.
[B35]. Note: This will reduce the winding width by two times
• Using VO1 [D108] and IRIPPLE1 [D114] determine the proper
the margin tape’s width.
output filter capacitor
• Enter the number of primary layers L [B36]. The maximum
• Using IAVG [D61] and the estimated peak reverse voltage,
recommended primary layers is 3.
determine the input rectifier diodes. In most cases 1N4007 is
• If necessary adjust the calculated number of secondary turns
ideal.
NS [B37] to change the core flux density (BM). Increasing NS
• Using IAVG [D61] determine the proper input filter inductor
will increase the primary turns and lower BM.
current rating.

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 AN-45 Application Note

• If necessary, the output voltage can be fine tuned. After the are provided in table 1. After measuring the efficiency of the
first prototype is built and running, enter the output voltage in first prototype-board at full load and both VACMIN and VACMAX if
cell [B49] when measured at full load. A fine tuned value for the measured efficiency is different than estimated then enter
RLOWER [D50] will be calculated to adjust the output voltage. the measured value and refine the transformer design.

Step-by-Step Design Procedure Power Supply Loss Allocation Factor, Z

This factor represents the proportion of losses between the
Step 1 – Enter Application Variables VACMIN, VACMAX,
primary and the secondary of the power supply. Z factor is used
fL , VO, Po, η, Z, tC, CIN

ENTER APPLICATION VARIABLES 5 V, 6 W Adapter Design

VACMIN 90 Volts Minimum AC Input Voltage
VACMAX 265 Volts Maximum AC Input Voltage
fL 50 Hertz AC Mains Frequency

VO 5.00 Volts Output Voltage

PO 6.00 Watts Output Power
n 0.72 Efficiency Estimate
Z 0.5 Loss Allocation Factor
tC 3 mSeconds Bridge Rectifier Conduction Time Estimate
CIN 16.80 uFarads Input Filter Capacitor

Figure 2. Application Variables Section of the Design Spreadsheet.

Determine the input voltage range from Table 3. together with the efficiency number to determine the actual power
that must be delivered by the power stage. For example losses in
Nominal Input Voltage (VAC) VACMIN VACMAX the input stage (EMI filter, rectification etc) are not processed by the
power stage (transferred through the transformer). Although they
100/115 85 132
reduce efficiency, the transformer design is not impacted.
230 195 265
Universal 85 265 Secondary Side Losses
Z=
Table 3. Standard Worldwide Input Line Voltage Ranges. Total Losses

Note: For designs that have a DC rather than an AC input, enter Start with a value of 0.5 if no other data is available.
the values for minimum and maximum DC input voltages, VMIN
and VMAX, directly into the grey override cell on the design Bridge Diode Conduction Time, tC (ms)
spreadsheet (see Figure 3). This is the duration of the incoming AC sine wave during which
the input diodes conduct, charging the input capacitance. This
Line Frequency, FL value is used in the calculation of the minimum voltage across
50 Hz for universal or single 100 VAC, 60 Hz for single 115 VAC the input capacitance at VAC(MIN). The actual value for tC can be
input. 50 Hz for single 230 VAC input. These values represent found by measuring the input current waveform on a prototype.
typical line frequencies rather than minimum. For most Use a value of 3 ms if no other data is available.
applications this gives adequate overall design margin. For
absolute worst case or based on the product specification Total Input Capacitance, CIN (mF)
reduce these numbers by 6% (47 Hz or 56 Hz). For half-wave Enter total input capacitance using table 4 for guidance.
rectification use FL /2. For DC input enter the voltage directly
into Cells [B40] and [B41]. Total Input Capacitance Per Watt Output Power (mF/W)
AC Input Voltage (VAC) Full Wave Rectification
Nominal Output voltage, VO (V)
100/115 3
Enter the nominal output voltage.
230 1
Output Power, PO (W) 85-265 3
Enter the output power. Table 4. Suggested Total Input Capacitance for Different Input Voltage Ranges.

Power Supply Efficiency, η The capacitance is used to calculate the minimum and
Enter the estimated efficiency of the complete power supply maximum DC voltage across the bulk capacitor and should be
measured at the output terminals under full load conditions and selected to keep the minimum DC input voltage, VMIN >70 V and
worst-case line (generally lowest input voltage). Initial values DMAX <54%.

DC INPUT VOLTAGE PARAMETERS

VMIN 96 Volts Minimum DC Input Voltage
VMAX 375 Volts Maximum DC Input Voltage

Figure 3. DC Input Voltage Parameters Section of the Design Spreadsheet.

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 Application Note AN-45

Step 2 – Enter LinkSwitch-CV Variables:

LinkSwitch-CV Device, VDS and VD.

Select a LinkSwitch-CV device based on the input voltage

range and output power using Table 2 for guidance.

Reflected Output Voltage, (VOR)

This parameter sets the turns ratio between primary and
secondary windings. For a given operating condition, a lower
VOR will reduce the peak drain voltage, increase the output
rectifier’s conduction time and reduce the output filter capacitor’s
ripple current. For a given primary inductance, a lower VOR will
reduce the maximum output power. It is recommended to use
the default VOR value for the first design iteration.

LinkSwitch-CV On State Drain to Source Voltage, VDS (V)

This parameter is the average ON state voltage developed
across the DRAIN and SOURCE pins of LinkSwitch-CV. By
default, if the grey override cell is left empty, a value of 10 V is
assumed. Use the default value if no better data is available. Figure 5. Continuous Conduction Mode Primary Current Waveforms, KP ≤1.

ENTER LinkSwitch-CV VARIABLES

LinkSwitch-CV LNK625P LNK625P Chosen LinkSwitch-CV device
ILIMITMIN 0.307 Amps LinkSwitch-CV Minimum Current Limit
ILIMITMAX 0.353 Amps LinkSwitch-CV Maximum Current Limit
fS 100000 Hertz LinkSwitch-CV Switching Frequency
I2FMIN 9801 A^2Hz LinkSwitch-CV Min I2F (power Coefficient)
I2FMAX 12741 A^2Hz LinkSwitch-CV Max I2F (power Coefficient)
VOR 90 Volts Reflected Output Voltage
VDS 10 Volts LinkSwitch-CV on-state Drain to Source Voltage
VD 0.5 Volts Output Winding Diode Forward Voltage Drop

DCON 5.04 us Output Diode conduction time

KP_TRANSIENT 1.04 Worst case ripple to peak current ratio. Maintain KP_TRANSIENT below 0.25

Figure 4. LinkSwitch-CV Parameters Section of Design Spreadsheet.

Output Diode Forward Voltage Drop, VD (V) By default, if the Core cell is left empty, the spreadsheet selects
Enter the average forward voltage drop of the (main) output the smallest core size that meets the peak flux density limit.
diode. Use 0.5 V for a Schottky diode or 0.7 V for a PN junction The user can change this selection and choose an alternate
diode if no better data is available. By default, a value of 0.5 V core from a list of commonly available cores (shown in Table 5).
is assumed. Enter the core type from the drop down menu. If the desired
core is not listed, then you may enter a core’s characteristics AE,
Output Diode Conduction Time, DCON (ms) LE and AL and the bobbin width BW.
This is the calculated diode conduction time of the output
diode. This value should always be greater than 3.1 ms, the For designs that require safety isolation between primary and
point at which the voltage on the FEEDBACK pin of secondary but are not using triple insulated wire. The width of
LinkSwitch-CV is sampled. the safety margin to be used on each side of the bobbin should
be entered for M. Typically for universal input designs a total
Ripple to Peak Drain Current Ratio, KP(TRANSIENT) margin of 6.2 mm would be required, and a value of 3.1 mm
KP is the calculated ratio of ripple to peak primary current. would be entered into the spreadsheet. For vertical bobbins the
KP(TRANSIENT) is the lowest value of KP that occurs between the margin may not be symmetrical, however if a total margin of 6.2
first and second switching cycles after a switching cycle has mm were required then 3.1 mm would still be entered even if the
been skipped. This value should be kept above a value of 0.25 physical margin were only on one side of the bobbin.
to prevent the current limit being triggered after leading edge
blanking. For designs using triple insulated wire it may still be necessary
to enter a small margin in order to meet the required safety
Step 3 – Choose Core and Bobbin Based on Output creepage distances. Typically many bobbins exist for each core
Power and Enter AE, LE, AL , BW, L size and each will have different mechanical spacing. Refer to
the bobbin data sheet or seek guidance from your safety expert
These symbols represent core effective cross-sectional area AE or transformer vendor to determine what specific margin is
(cm2), core effective path length LE (cm), core ungapped required. As the margin reduces the available area for the
effective inductance AL (nH/Turn2), bobbin width BW (mm) and windings, margin construction may not be suitable for small
number of primary layers L.

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 AN-45 Application Note

ENTER TRANSFORMER CORE/CONSTRUCTION VARIABLES

Core Type Auto EE16 Transformer Core size
Core EE16 P/N: PC40EE16-Z
Bobbin EE16_BOBBIN P/N: BE-16-118CPH
AE 0.192 cm^2 Core Effective Cross Sectional Area
LE 3.5 cm Core Effective Path Length
AL 1140 nH/T^2 Ungapped Core Effective Inductance
BW 8.5 mm Bobbin Physical Winding Width
M 0.00 mm Safety Margin Width (Half the Primary to Secondary Creepage Distance)
L 3 Number of Primary Layers
NS 7 Number of Secondary Turns

Figure 6. Transformer Core and Construction Variables Section of the Design Spreadsheet.

NS is the number of secondary turns. If left blank the lowest

Transformer Core Size
number of turns to meet an acceptable core flux density will be
EE10 EF16 calculated.
EF12.6 EF20
Step 4 – Feedback Variables
EE13 EF25
EE16 EFD15 The feedback parameters are calculated by the software. NFB is
EE19 EFD20 the number of turns for the feedback winding. The user can
change the value by entering the desired number in the shaded
EE22 EFD25
cell. VFLY is the flyback voltage on the feedback winding. This
EEL16 EFD30 voltage is used to regulate the output voltage. Resistors RUPPER
EE16W EI16 and RLOWER are the feedback resistors connected to the feedback
EEL19 EI19 winding and the FB pin of the LinkSwitch-CV device. You may
EEL22 EI22
enter another value in the shaded cell to change RUPPER and
RLOWER will be re-calculated. It is not recommended to increase
EE25 EI25
the value greater than 2.5 times the default value. Doing so
EEL25 may activate the open loop protection circuitry.
Table 5. List of Cores Provided in LinkSwitch-CV PIXls Spreadsheet.
After the first prototype is operating, the output voltage can be
core sizes. If after entering the margin more than 3 primary fine tuned for increased accuracy. Measure the output voltage
layers (L) are required, it is suggested that either a larger core at full load and enter the value in the Measured Output Voltage
be selected or switch to a zero margin design using triple cell. RLOWER_FINE will be calculated based on this measured value.
insulated wire. Use this value to replace the existing RLOWER in the prototype.

If your requirements require the use of margin tape, enter the Step 5 – Bias Winding Parameters
tape width in mm for M.
If an external bias circuit is desired to reduce no load input
Enter the number of primary layers (L). The maximum power below 200 mW, enter YES in shaded cell. If not, enter
recommended primary layers is 3. Larger number of layers NO. If using a bias winding, the recommended bias voltage is
increases leakage inductance which increases losses and shown in cell for VB. You may change this voltage by entering a
degrades output regulation. value in the shaded cell. It is not recommended to use a value

FEEDBACK VARIABLES
NFB 6.00 Feedback winding number of turns
VFLY 4.71 Volts Voltage on the Feedback winding when LinkSwitch-CV turns off
RUPPER 10.00 k-ohms Upper resistor of feedback network
RLOWER 7.50 k-ohms Lower resistor of feedback network
Fine Tuning Section
Measured Output Voltage 5.00 k-ohms Actual (Measured) Voltage at the output of power supply
RLOWER_FINE 7.50 k-ohms Adjusted (Fine tuned) value of lower resistor (RLOWER). Do not change value of RUPPER

Figure 7. Feedback Variables Section of the Design Spreadsheet.

Bias Winding Parameters

Add Bias winding YES YES Enter 'Yes' if you want to add a Bias winding
VB 10 Volts Bias Winding Voltage
Number of Bias winding turns. Bias winding is assumed to be AC stacked on top of the Feedback
NB 7 winding

Figure 8. Bias Winding Parameters Section of the Design Spreadsheet.

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 Application Note AN-45

lower than 10 V. NB is the number of turns required for the bias typical ALG value multiplied by 1+(LP(TOL)/100). This value is
winding. It is important to note that this transformer winding typically used by transformer vendors to purchase the cores
must be AC stacked on top of the feedback winding (placed in with the correct gap size.
series with the feedback winding).

CURRENT WAVEFORM SHAPE PARAMETERS

DMAX 0.51 Maximum Duty Cycle
IAVG 0.09 Amps Average Primary Current
IP 0.31 Amps Minimum Peak Primary Current
IR 0.27 Amps Primary Ripple Current
IRMS 0.13 Amps Primary RMS Current

Figure 9. Current Waveform Shape Parameters Section of the Design Spreadsheet.

Step 6 – Iterate Transformer Design and Generate Key Maximum Flux Density, BM (Gauss)
Transformer Design Parameters BM is the operating core flux density. A maximum value of 2500
(0.25 T) is recommended to minimize audible noise generation.
Iterate the design, making sure that no warnings are displayed. Values above this will depend on acceptability of audible noise
Any parameters outside the recommended range of values can levels. If using long cores, for example EEL16, the flux density may
be corrected by following the guidance given in the right hand need to be reduced even further to give acceptable levels.
column. Messages marked “!!! Info” provide guidance for
acceptable parameters that can be further optimized. Once all Peak Flux Density, BP (Gauss)
warnings have been cleared, use the transformer design BP is the maximum flux density at maximum device current limit
parameters to either wind a prototype transformer, or to send to and inductance tolerance. To prevent core saturation a
a vendor for obtaining samples. maximum value of 3100 Gauss (0.31 T) is recommend.

TRANSFORMER PRIMARY DESIGN PARAMETERS

LPMIN 1479 uHenries Minimum Primary Inductance
LP_TYP 1627 uHenries Typical (Nominal) Primary Inductance
LP_TOL 10 Tolerance of Primary inductance
NP 115 Primary Winding Number of Turns
ALG 124 nH/T^2 Gapped Core Effective Inductance

BM 2441 Gauss Maximum Flux Density, (BM<2500) Calculated at typical current limit and typical primary inductance
Peak Flux Density, (BP<3100) Calculated at maximum current limit and maximum primary
BP 2848 Gauss inductance
BAC 950 Gauss AC Flux Density for Core Loss Curves (0.5 X Peak to Peak)
ur 1654 Relative Permeability of Ungapped Core
LG 0.19 mm Gap Length (Lg > 0.1 mm)
BWE 25.5 mm Effective Bobbin Width
OD 0.22 mm Maximum Primary Wire Diameter including insulation
INS 0.04 mm Estimated Total Insulation Thickness (= 2 * film thickness)
DIA 0.18 mm Bare conductor diameter
AWG 34 AWG Primary Wire Gauge (Rounded to next smaller standard AWG value)

CM 40 Cmils Bare conductor effective area in circular mils

CMA 301 Cmils/Amp Primary Winding Current Capacity (200 < CMA < 500)

Figure 10. Transformer Primary Design Parameters Section of the Design

Spreadsheet.

Primary Inductance, LP(TYP), LP(MIN) (mH), LP(TOLERANCE), (%) Core Gap Length, LG (mm)
LP(MIN) represents the minimum primary inductance needed to LG is the estimated core gap length. Values below 0.1 mm are
deliver the nominal output power (PO). generally not recommended for center-leg gapped cores due to
the resultant increase in primary inductance tolerance. If you
As it is more common to specify the primary inductance to a require such a low value, consult with your transformer vendor
vendor as a nominal value with tolerance, the value for LP(TYP) is for guidance.
calculated via the expression
Maximum Primary Winding Wire Outside Diameter, OD (mm)
L P(TYP) = L P(MIN) # c1 + 100 m
L P(TOL)
This is the calculated maximum outside wire diameter to allow
the primary winding to fit into the number of specified layers.
where LP(TOL) is the entered percentage tolerance. If no value is When selecting the wire type use double-coated magnetic wire
entered, PIXls uses 10 by default, signifying LP(TOL) of ±10%. (rather than single-coated types) for improved reliability and
reduced primary capacitance (lower no-load input power).
Primary Winding Number of Turns, NP
This is the total number of primary winding turns. Primary Winding Wire Bare Conductor Diameter, DIA (mm)

Gapped Core Effective Inductance, ALG (nH/T2) Primary Winding Wire Gauge, AWG
This is the target core effective inductance at LP(MIN) for the This is the calculated conductor diameter rounded to the next
smallest standard American Wire Gauge size.

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 AN-45 Application Note

Primary Winding Bare Conductor Effective Area, CM(CMILS) Differential-mode EMI generation is a strong function of the
CM is the effective conductor area in circular mils. equivalent series resistance (ESR) of CIN2, as this capacitor
supplies the primary switching current. Selecting a lower ESR
Primary Winding Wire Current Capacity, CMA (CMILS/A) capacitor series for CIN2 than CIN1 can help reduce differential
CMA is the primary conductor area in circular mils (where 1 mil mode (low frequency) conducted EMI while optimizing the
= 1/1000th of an inch) per Amp. Values below the recommended overall cost of the two capacitors. Table 6 shows the input filter
minimum of 200 maybe acceptable if worst case winding schematic, gives a formula for selecting CIN1 + CIN2, and tells
temperature is verified. how to adjust the input capacitance for other input voltage ranges.

Step 7 – Selection of Input Stage

DIN1-4
The recommended input stage is shown in Table 6. It consists RF1
LIN1 +
of a fusible element, input rectification, and line filter network.
The fusible element can be either a fusible resistor or a fuse. If AC IN CIN1 CIN2
a fusible resistor is selected, use a flameproof type. Depending
on the differential line input surge requirements, a wire-wound LIN2
type may be required. Avoid using metal or carbon film types
as these can fail due to the inrush current when VACMAX is PI-5118-042308

applied repeatedly to the supply.

RF1: 4.7 W – 10 W, 1 W, Fusible, flameproof or fuse
LIN1: 470 mH – 2.2 mH, 0.05 A – 0.3 A
For designs using a Y-capacitor and a single inductor or
LIN2: Ferrite bead or 470 mH – 2.2 mH, 0.05 A – 0.3 A
inductor plus ferrite bead the inductor should be located on the
CIN1 + CIN2: ≥ 2 mF/WOUT, 400 V, 85 VAC - 265 VAC
opposite side to the Y-capacitor connection. For example with
: ≥ 2 mF/WOUT, 200 V, 100 VAC - 115 VAC
the Y-capacitor connected to positive of CIN2 the inductor
: ≥ 1 mF/WOUT, 400 V, 185 VAC - 265 VAC
should be in the location of LIN2 and ferrite bead LIN1 (if used).
DINX: 1N4007, 1 A, 1000 V
For designs with outputs ≤1 W, it is generally lower cost to use Table 6. Input Stage Recommendation
half-wave rectification; and >1 W, full-wave rectification. The
EMI immunity of half-wave rectified designs is improved by Step 8 – Selection of BYPASS Pin Capacitor, Bias
adding a second diode in the lower return rail. This provides Winding and Feedback Components
EMI gating (EMI currents only flow when the diode is
conducting) and doubles the differential surge immunity since BYPASS Pin Capacitor
the surge voltage is shared across two diodes. Use a 1 mF BYPASS pin capacitor (C4 in Figure 1) with a voltage
rating greater than 7 V. The capacitor’s dielectric material is not
Half-wave rectification may be unsuitable if the supply specification critical. However, the absolute minimum value (including tolerance
requires output electrostatic discharge (ESD) testing. During and temperature) should be ≥0.5 mF. The capacitor must be
such testing up to ±15 kV discharges of fixed energy are physically located close to the LinkSwitch-CV BYPASS pin.
applied to the secondary of the supply (with respect to the
primary). With half-wave rectification this voltage also appears Bias Winding Components
across the input diodes, and may cause failure. With full-wave The addition of a bias circuit decreases the no-load input power
rectification the diode stress is clamped to the voltage across from ~200 mW down to less than 70 mW. This may sufficiently
the input capacitance, preventing diode failure. increase efficiencies at lighter loads to allow lower cost components
while still meeting average efficiency requirements. For example
Conducted EMI filtering is provided by LIN1 and LIN2, which a PN-junction diode may replace a higher-cost Schottky-barrier
together with CIN1 and CIN2, form a pi (π) filter. A single inductor diode, or the output cable may be replaced by one constructed
is suitable for designs below 3 W or when EMI is measured with of smaller diameter wire (higher impedance).
the output of the supply floating (i.e. not connected to safety
earth ground). Although two inductors are generally required The power supply schematic shown in Figure 1 uses the bias
above 3 W, a ferrite bead may be sufficient, especially when the circuit. Diode D6, capacitor C6, and resistor R4 form the bias
output of the supply is floating. circuit. If the output voltage is less than 10 V, then an additional
transformer winding is needed, AC-stacked on top of the
Normally the total input capacitance is divided equally between feedback winding. This provides a high enough voltage to
the two input capacitors (CIN1 and CIN2). However, for lower supply the BYPASS pin even during low switching frequency
cost, two different capacitance values may be used. In this operation at no-load.
case select CIN1 as ≥1 mF (or as needed) to prevent overvoltage
of the capacitor during differential mode surge. Select the In Figure 1 the additional bias winding (from pin 5 to pin 4) is
second capacitor CIN2 to meet both an overall capacitance stacked on top of the feedback winding (pin 4 to pin 2). Diode
(CIN1 + CIN2) of ≥2 mF/W of output power, and 3 mF/W of output D6 rectifies the output and C6 is the filter capacitor. A 10 mF
power for highest low-line efficiency. capacitor is recommended to hold up the bias voltage during

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 Application Note AN-45

the low frequency operation at no-load. The capacitor type is Step 9 – Selection of Output Diode and Pre-load
not critical but its voltage rating should be above the maximum Output Rectifier Diode
value of VBIAS. The recommended current into the BYPASS pin
is equal to the IC supply current (~0.5 mA). The value of RBIAS The output rectifier diode should be either a fast or an ultrafast
(R4) is calculated according to recovery PN junction or Schottky-barrier type. Select a diode
with sufficient margin to the specified voltage rating (VR).
R BIAS = ]V BIAS - V BP g /IS 2 Typically VR ≥ 1.2 × PIVs, where PIVs is taken from the Voltage
Stress Parameters section of the spreadsheet. Once a
where VBIAS (10 V typical) is the voltage across C6, IS2 (0.5 mA prototype is completed use an oscilloscope to measure the
typical) is the IC supply current, and VBP (6.0 V typical) is the BP actual diode stress at VACMAX to confirm acceptable de-rating
pin voltage. The parameters IS2 and VBP are provided in the (typically 80%).
parameter table of the LinkSwitch-CV data sheet. Diode D6
can be any low-cost diode such as FR102, 1N4148, or Select the diode with the closest rating to ID ≥ 2 × IO, where ID is
BAV19/20/21. The diode voltage stress is given in the Voltage the diode’s rated current and IO is the output current. Take the
Stress Parameter section of the design spreadsheet. diode’s self-heating into consideration and use a larger diode, if
needed, to meet thermal or efficiency requirements.
If the feedback winding voltage (VFLY in the design spreadsheet)
is >10 V an additional winding is not required. In this case, Table 7 lists some of the suitable Schottky and ultrafast diodes
connect D6 directly to the feedback winding at pin 4 of the that may be used with LinkSwitch-CV circuits. As the output
transformer and eliminate the bias winding between pins 5 and 4. voltage is sampled at the switching frequency, a minimum
switching frequency is maintained at no-load to give acceptable
Feedback Pin Resistor Values transient load performance. Therefore, if the supply can
The values of RUPPER and RLOWER can be found in cells [D46] and operate unloaded, use a pre-load resistor to prevent the output
[D47] for the initial prototype build. In applications where a voltage from rising under very light (<~25 mA) or no-load
different feedback network impedance is required, a value can conditions (see resistor R7, R8 and R9 in Figure 1).
be entered for RUPPER, the software will calculate the value of
RLOWER. It is important to note that the FEEDBACK pin requires a For designs where output voltage regulation must be maintained
minimum of 150 mA of input current to detect that the feedback at zero load, start with a resistor value that represents a load of
network is present. If the current is less than 150 mA, the power approximately 25 mA at the nomimal output voltage. For
supply may not start properly. Resistors RUPPER and RLOWER example, for a 5 V output use a pre-load resistor value of 2 kW.
should be located as close to the FEEDBACK pin as possible.
After the first prototype is running, it may be necessary to adjust For designs where the output voltage can rise under no-load
the output voltage by adjusting the value of RLOWER. PIXls will conditions, select the pre-load resistor value such that the
calculate the proper value. Enter the measured output voltage in output voltage is within the maximum output voltage specification.
cell [B49] and PIXls will display the new value for RLOWER in cell [D50]. Limit the maximum voltage rise at no-load to <50% of the
normal output voltage to minimize increases in input power due
Capacitor C5 and R5 in figure 1 are used to eliminate the effects to increases in the primary clamp and bias winding dissipation.
of pulse grouping. Please see the section on pulse grouping in
the Tips for Designs section for more information. Since a pre-load resistor also increases the no-load losses,
where the specification allows, adjust the no-load voltage to
trade-off lower no-load input power with high no-load output
voltage as needed.

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 AN-45 Application Note

VR Range IF
Series Number Type Package Manufacturer
V A
1N5817 to 1N5819 Schottky 20-40 1 Leaded Vishay
SB120 to SB1100 Schottky 20-100 1 Leaded Vishay
11DQ50 to 11DQ60 Schottky 50-60 1 Leaded Vishay
1N5820 to 1N5822 Schottky 20-40 3 Leaded Vishay
MBR320 to MBR360 Schottky 20-60 3 Leaded Vishay
SS12 to SS16 Schottky 20-60 1 SMD Vishay
SS32 to SS36 Schottky 20-60 3 SMD Vishay
UF4002 to UF4006 Ultrafast 100-600 1 Leaded Vishay
UF5401 to UF5408 Ultrafast 100-800 3 Leaded Vishay
ES1A to ES1D Ultrafast 50-200 1 SMD Vishay
ES2A to ES2D Ultrafast 50-200 2 SMD Vishay
SL12 to SL23 Schottky (low VF) 20-30 1 SMD Vishay
SL22 to SL23 Schottky (low VF) 20-30 2 SMD Vishay
SL42 to SL44 Schottky (low VF) 20-30 4 SMD Vishay
Table 7. List of Suitable Diodes for LinkSwitch-CV Designs.

TRANSFORMER SECONDARY DESIGN PARAMETERS

Lumped parameters
ISP 5.02 Amps Peak Secondary Current
ISRMS 2.14 Amps Secondary RMS Current
IO 1.20 Amps Power Supply Output Current
IRIPPLE 1.78 Amps Output Capacitor RMS Ripple Current
CMS 429 Cmils Secondary Bare Conductor minimum circular mils
AWGS 23 AWG Secondary Wire Gauge (Rounded up to next larger standard AWG value)
DIAS 0.58 mm Secondary Minimum Bare Conductor Diameter
ODS 1.21 mm Secondary Maximum Outside Diameter for Triple Insulated Wire
INSS 0.32 mm Maximum Secondary Insulation Wall Thickness

Figure 11. Transformer Secondary Design Parameters Section of Design Spreadsheet.

VOLTAGE STRESS PARAMETERS

VDRAIN 584 Volts Maximum Drain Voltage Estimate (Includes Effect of Leakage Inductance)
PIVB 48 Volts Bias Diode Maximum Peak Inverse Voltage
PIVS 28 Volts Output Rectifier Maximum Peak Inverse Voltage

Figure 12. Voltage Stress Parameters Section of Design Spreadsheet.

Step 10 – Select Output Filter Capacitor frequency, DCON is the output diode conduction time and
VRIPPLE(MAX) is the maximum allowable output ripple voltage.
Select the capacitor voltage to be ≥1.2 × VO(MAX). Verify that the ripple current rating of the capacitor is above the
IRIPPLE value (from the Transformer Secondary Parameters
Select the initial capacitor choice using the maximum allowable section of the design spreadsheet). If not, select the smallest
equivalent series resistance (ESR) expression below: capacitance value that meets this requirement. Many capacitor
V RIPPLE(MAX) manufacturers provide factors that increase the ripple current
ESR MAX = rating as the capacitor operating temperature is reduced from
ISP
the data sheet maximum. This should be considered to ensure
Where VRIPPLE(MAX) is the maximum specified output ripple and that the capacitor is not oversized for cost reasons.
noise and ISP is the secondary peak current from the
Transformer Secondary Parameters section of the design To reduce the physical size of the output capacitor an output
spreadsheet. LC post filter can be used to reduce the ESR related switching
noise. In this case select either a 1 mH to 3.3 mH inductor with a
The absolute minimum capacitance (excluding the effect of current rating ≥IO or a ferrite bead for designs with IO<~500 mA.
ESR) is given by: The second capacitor is typically 100 mF or 220 mF with a low
IO(MAX) b - DCON l
1
FS ESR for good transient response. As the secondary ripple
COUT(MIN) = current does not pass through this capacitor there are no
V RIPPLE(MAX)
specific ESR or ripple current requirements.
Where IO(MAX) is the maximum output current, FS is switching

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 Application Note AN-45

TRANSFORMER SECONDARY DESIGN PARAMETERS (MULTIPLE OUTPUTS)

1st output
VO1 5 Volts Output Voltage (if unused, defaults to single output design)
IO1 1.200 Amps Output DC Current
PO1 6.00 Watts Output Power
VD1 0.5 Volts Output Diode Forward Voltage Drop
NS1 7.00 Output Winding Number of Turns

ISRMS1 2.14 Amps Output Winding RMS Current

IRIPPLE1 1.78 Amps Output Capacitor RMS Ripple Current
PIVS1 28 Volts Output Rectifier Maximum Peak Inverse Voltage
CMS1 429 Cmils Output Winding Bare Conductor minimum circular mils
AWGS1 23 AWG Wire Gauge (Rounded up to next larger standard AWG value)
DIAS1 0.58 mm Minimum Bare Conductor Diameter
ODS1 1.21 mm Maximum Outside Diameter for Triple Insulated Wire

2nd output
VO2 Volts Output Voltage
IO2 Amps Output DC Current
PO2 0.00 Watts Output Power
VD2 0.7 Volts Output Diode Forward Voltage Drop
NS2 0.89 Output Winding Number of Turns
ISRMS2 0.00 Amps Output Winding RMS Current
IRIPPLE2 0.00 Amps Output Capacitor RMS Ripple Current
PIVS2 3 Volts Output Rectifier Maximum Peak Inverse Voltage

CMS2 0 Cmils Output Winding Bare Conductor minimum circular mils

AWGS2 N/A AWG Wire Gauge (Rounded up to next larger standard AWG value)
DIAS2 N/A mm Minimum Bare Conductor Diameter
ODS2 N/A mm Maximum Outside Diameter for Triple Insulated Wire

3rd output
VO3 Volts Output Voltage
IO3 Amps Output DC Current
PO3 0.00 Watts Output Power
VD3 0.7 Volts Output Diode Forward Voltage Drop
NS3 0.89 Output Winding Number of Turns
ISRMS3 0.00 Amps Output Winding RMS Current
IRIPPLE3 0.00 Amps Output Capacitor RMS Ripple Current
PIVS3 3 Volts Output Rectifier Maximum Peak Inverse Voltage

CMS3 0 Cmils Output Winding Bare Conductor minimum circular mils

AWGS3 N/A AWG Wire Gauge (Rounded up to next larger standard AWG value)
DIAS3 N/A mm Minimum Bare Conductor Diameter
ODS3 N/A mm Maximum Outside Diameter for Triple Insulated Wire

Total power 6 Watts Total Output Power

Negative Output N/A If negative output exists enter Output number; eg: If VO2 is negative output, enter 2

Figure 13. Transformer Secondary Design Parameters for Multiple Outputs Section of Design Spreadsheet.

The output capacitor may also be split into two physical Resistor RC1 dampens high frequency leakage inductance
capacitors. Here the overall ripple current rating is equal to the ringing for reduced EMI. The value must be large enough to
sum of the ratings of each individual capacitor. dampen the ring in the required time but must not be too large
to cause the drain voltage to exceed 680 V.
Step 11 – Selection of Primary Clamp Components
If the primary leakage inductance is less than 125 mH, VR1 can
Two clamp arrangements, shown in Figure 14, are suitable for be eliminated and the value of RC2 increased. A value of
LinkSwitch-CV designs. Minimize the value of CC1 and 470 kW with an 820 pF capacitor is a recommended starting
maximize RC2 while maintaining the peak drain voltage to point. Verify that the peak drain voltage is less than 680 V
<680 V. Larger values of CC1 may cause higher output ripple under all line and load conditions. Verify the feedback winding
voltages due to the longer settling time of the clamp voltage settles to an acceptable limit for good line and load regulation.
impacting the sampled voltage on the feedback winding.
Effects of Fast vs. Slow Diodes in Clamp Circuit
The RCDZ circuit is preferred when the primary leakage A slow reverse recovery diode (>1 ms) reduces the feedback
inductance is greater than 125 mH to reduce drain voltage voltage ringing and improve output regulation. Using a fast diode
overshoot and/or ringing present on the feedback winding. (500 ns) increases the amplitude of ringing which can result in
increased output ripple. In Figure 15 the (larger) ring amplitude
For best output regulation, the feedback voltage must settle to when using a FR104 diode represents up to an 8% error in the
within 1% at 2.1 ms from the turn off of the primary MOSFET. sampled voltage over the time period 2.5 ms to 3.1 ms.
This requires careful selection of the clamp circuit components.
The voltage of VR1 is selected to be 10% to 20% above the VOR. Clampless Designs
This allows the clamp to limit the magnitude of the leakage Clampless designs rely solely on the drain node capacitance to
voltage spike at turn off but ensures the Zener is not conducting limit the leakage inductance induced peak drain-to-source
during the flyback period when the output diode is conducting. voltage. Therefore the maximum AC input line voltage, the
The value of RC2 should be the largest value that result in both value of VOR, the leakage inductance energy, (a function of
acceptable settling of the feedback pin voltage and peak drain leakage inductance and peak primary current), and the primary
voltage. Making RC2 too large will increase the discharge time winding capacitance determine the peak drain voltage. With no
of CC1, increase the peak drain voltage and degrade regulation.

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 AN-45 Application Note

Common Primary Clamp Configurations

RCD RCDZ (Zener Bleed)

RC2
RC2 CC1
CC1
DC2

RC1
RC1
DC1
DC1

PI-5107-110308 PI-5108-110308

DC1: 1N4007 / FR107, 1 A, 1000 V DC1: 1N4007 / FR107, 1 A, 1000 V

RC1: 100 W - 300 W, 1/4 W DC2: BZY97Cxxx (xxx = 1.1 to 1.2 × VOR)
CC1: 470 pF - 1000 pF RC1: 100 W - 300 W, 1/4 W
RC2: 330 kW - 680 kW, 1/2 W RC2: 5 kW - 100 kW, 1/2 W
CC1: 470 pF - 1000 pF
Figure 14. Primary Clamp Configurations Suitable for LinkSwitch-CV Designs.

significant dissipative element present, as is the case with an

external clamp, the longer duration of the leakage inductance
ringing can increase EMI.
RC2 CC1

The following requirements are recommended for a universal

input or 230 VAC only Clampless design:
RC1
1. Clampless designs should only be used for PO ≤5 W using a
VOR of ≤90 V DC1
2. For designs with PO ≤5 W, a two-layer primary must be used
to ensure adequate primary intra-winding capacitance in the
range of 25 pF to 50 pF. A bias winding must be added to
the transformer using a standard recovery rectifier diode
(1N4003 – 1N4007) to act as a clamp. This bias winding PI-5107-110308
may also be used to externally power the device by connect-
ing a resistor from the bias winding capacitor to the BYPASS
pin. This inhibits the internal high-voltage current source,
reducing device dissipation and no-load consumption.
3. For designs with PO >5 W, clampless designs are not practical
and an external clamp should be used.
4. Ensure that worst-case, high line, peak drain voltage is below
the BVDSS specification of the internal MOSFET and ideally
≤650 V to allow margin for design variation. The capacitance
of the transformer is much more critical in a clampless
design. Therefore ensure that testing is performed with
transformers at the minimum of the capacitance (or resonant
frequency) specification.

VOR (Reflected Output Voltage), is the secondary output plus

output diode forward voltage drop that is reflected to the
primary via the turns ratio of the transformer during the diode Black Trace: DC1 is a FR104
conduction time. The VOR adds to the DC bus voltage and the Gray Trace: DC1 is a 1N4007G
leakage spike to determine the peak drain voltage.
Figure 15. Effect of Clamp Diode Recovery Time of Feedback Pin Voltage.

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 Application Note AN-45

Example Transformer Winding Arrangement techniques. Shield windings improve conducted EMI
Including E-Shields™ performance and simplify the input filter stage by eliminating the
Once the PIXls spreadsheet design is complete all the necessary need for a common mode choke and reducing the value of or
information is available to create a transformer design. In this eliminating the Y-class capacitor connected between the
section some practical tips are presented on winding order and primary and secondary. Refer to Figures 16 and 17 to reference
the inclusion of Power Integrations proprietary E-Shield winding numbers (WDx).

5 6
WD2 = Primary WD7 = Secondary
200T 37AWG 13T 32AWG X3
3 7

5 11
WD3 = Bias WD5 = 5 V Secondary
10T 32AWG 10T 29AWG X3
4 9
WD4 = FB
10
9T 28 X3
WD6 = 22 V Secondary
2
WD1 = Cancelation 40T 33AWG
33T 31AWG 12
NC PI-5270-110308

Figure 16. Typical Transformer Electrical Schematic.

3 layers tape

7
WD7: 13T 32AWG X3
6

12
WD6: 40T 33AWG
10

9
WD5: 10T 29AWG X3
11
Teflon tubing
7 places
3 layers tape
4
2 WD4: 9T 28AWG X3

5
4
WD3: 10T 32AWG

1
67T 37AWG

WD2: 67T 37AWG

3
66T 37AWG
2
NC WD1: 33T 31AWG

PI-5271-110308
3.3 mm tape margin 6 mm tape margin

Figure 17. Typical Mechanical Construction of LinkSwitch-CV Transformer.

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 AN-45 Application Note

Core Cancelation Winding Bias Winding (optional)

The first layer is the Core Cancelation winding (WD1). The The bias winding is the third winding (WD3). This winding is
number of turns can be found by taking the primary turns NP spread evenly across the bobbin width. Since this winding
[D71] from PIXls and divide by the number of layers L [E36]. does not provide shielding, it is not required to fill the layer
Divide the result by 2 (NSHEILD = 1/2 *(NP/L)). This gives a starting without gaps. The number of turns NB are calculated in cell [D56].
value and may need to be adjusted to optimize the conducted
EMI emissions. Note that the start (black dot) of the Shield Feedback Winding
winding is on the opposite side of the bobbin from the start of The feedback winding is the fourth winding (WD4) on the
the primary winding. The finish end of the Shield winding is bobbin. From PIXls find the number of turns NFB [D44]. To help
floating. Use a gauge wire that will completely fill the bobbin reduce conducted EMI emissions, this winding must cover the
width. complete bobbin width. Usually a multi-filiar winding is used to
completely cover the bobbin width.
Primary Winding
The second winding (WD2) is the primary. From PIXls find the Secondary Winding
number of turns NP [D71], number of layers L [E36] and the wire The secondary windings begin on layer 5. The main output
gauge AWG [D82]. As shown in figure 17, the start of the primary (highest output power) should be placed on this layer. This
is on the opposite side of the bobbin from the Shield’s start. layer should fill the bobbin width.

Split Screen with Bottom Portion Zoom of Upper Trigger Point Split Screen with Bottom Portion Zoom of Upper Trigger Point
Top Trace: Drain Waveform (200 V/div) Top Trace: Drain Waveform (200 V/div)
Bottom Trace: Output Ripple Voltage (50 mV/div) Bottom Trace: Output Ripple Voltage (50 mV/div)

Figure 18. Not Pulse Grouping (<5 Consecutive Switching Cycles). Pulse Grouping (>5 Consecutive Switching Cycles).

5
D6
1N4148
4

2 R3
6.34 kΩ
LinkSwitch-CV 1%
U1
LNK626PG
D
FB

BP

R4 R5
S
6.2 kΩ 47 kΩ
1/8 W R6 C6
C4 C5 4.02 kΩ 10 µF
1 µF 680 pF 1% 50 V
50 V 50 V

PI-5268-110608

Figure 19. RC Network Across RBOTTOM to Reduce Pulse Grouping.

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 Application Note AN-45

Additional Secondary Windings voltages together with analog signals makes it especially
Any additional output windings are added after the main output important to follow good PCB design practice to ensure stable
winding. and trouble free operation of the power supply.

Tips for Designs When designing a board for the LinkSwitch-CV based power
supply, it is important to follow the following guidelines:
Pulse Grouping
Pulse grouping is defined as 6 or more consecutive pulses followed Primary-Side Connections
by two or more timing state changes. The effect of pulse grouping • Use a single point (Kelvin) connection at the negative terminal
is increased output voltage ripple. This is shown on the right of of the input filter capacitor for the LinkSwitch-CV SOURCE pin
Figure 18 where pulse grouping has caused an increase in the and bias winding return. This improves surge capabilities by
output ripple. returning surge currents from the bias winding directly to the
input filter capacitor.
To eliminate group pulsing verify that the feedback signal settles • The BYPASS pin capacitor should be located as close as
within 2.1 ms from the turn off of the internal MOSFET. A Zener possible to the SOURCE and BYPASS pins.
diode in the clamp circuit may be needed to achieve the desired • The copper area connected to the source pins provide the
settling time. If the settling time is unsatisfactory, then a RC LinkSwitch-CV heat sink. A rule of thumb estimate is that the
network across RLOWER (R6) of the feedback resistor is necessary. LinkSwitch-CV will dissipate 10% of the output power. Provide
enough copper area to keep the source pin temperature
The value of R (R5 in Figure 19) should be an order of magnitude below 110 °C.
greater than RLOWER and selected such that R×C = 32 ms where
C is C5 in Figure 19 . Secondary
• To minimize leakage inductance and EMI the area of the loop
Design Recommendations connecting the secondary winding, the output diode and the
output filter capacitor should be minimized. In addition,
Circuit Board Layout
sufficient copper area should be provided at the anode and
LinkSwitch-CV is a highly integrated power supply solution that
cathode terminal of the diode for heat sinking. A larger area is
integrates on a single die, both, the controller and the high
preferred at the quiet cathode terminal. A large anode area
voltage MOSFET. The presence of high switching currents and
can increase high frequency radiated EMI.

Primary Side Secondary Side

Drain trace area
miniminzed Output Filter
Input Filter Clamp Output
Rectifiers Capacitor
Capacitor Components Isolation Barrier

VR1 R2 C11
C1 Y1-
Copper area C3 Capacitor C12
L1 (optional)
maximized for T1 D9
heatsinking R10 C13

D7
R1
D5 L3
C2 C8
U1
D1 D3 S D
L2 Transformer
S BP R3
S
D4
D2 S JP1 C10
FB R4
C4 C9
D8 R8 R9
F1 RV1 C5 R7
R5
R6 C6 J2
RT1 D6
J1 1 6
ESD
spark gap
10 mil Bypass Feedback DC Outputs
AC
+
IN
- gap Capacitor Resistors close
close to device to device PI-5269-122408

Figure 20. PCB Layout Example of a Three Output Power Supply.

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 AN-45 Application Note

B+ B+

CLAMP CLAMP

Small
FEEDBACK
pin node
area
D D
FB FB

BP BP

S Minimize S Bias resistor

FEEDBACK
pin node
PRI RTN area PRI RTN
PI-5265-032713
PI-5266-032713

Bias currents Kelvin connection at Bias currents Kelvin connection at

return to bulk SOURCE pin, no power return to bulk SOURCE pin, no power
capacitor currents in signal traces capacitor currents in signal traces

Figure 21. Schematic Representation of Recommended Layout Figure 22. Schematic Representation of Recommended Layout
without External Bias. with External Bias.

B+

CLAMP
Drain trace in close
proximity of feedback trace
will couple noise into
feedback signal

Power currents
flow in signal D FB
source trace
BP

Trace S
impedance Isource
PRI RTN Line surge
Bias winding currents can
currents flow in flow through
ΔVS signal source traces device

Voltage drops across trace impedance PI-5267-111008

may cause degraded performance

Figure 23. Schematic Representation of Electrical Impact Due to Improper Layout.

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 Application Note AN-45

• A spark gap is formed by a PCB trace placed under the Quick Design Checklist
transformer along the isolation barrier between primary and
secondary sides of the layout. During ESD testing any arcing As with any power supply design, all LinkSwitch-CV designs
across the isolation barrier will preferentially occur between should be verified on the bench to make sure that component
this trace and the secondary. This safely directs the arc specifications are not exceeded under worst-case conditions.
discharge current to the AC input. A small additional gap is The following minimum set of tests is strongly recommended:
placed in this trace near the AC input. The gap electrically
isolates the primary side connected trace from the AC and 1. Maximum drain voltage – Verify that peak VDS does not
prevents any noise coupling into the AC input but forms a exceed 680 V at highest input voltage and maximum output
second low breakdown voltage spark gap during ESD testing. power.
2. Maximum drain current – At maximum ambient temperature,
Drain Clamp maximum input voltage and maximum output load, verify
LinkSwitch-CV senses the feedback winding on the primary drain current waveforms at start-up for any signs of trans-
side to regulate the output. It is important to note that the former saturation and excessive leading edge current spikes.
leakage inductance ring can affect the output regulation. A LinkSwitch-CV has a leading edge blanking time of 170 ns to
proper drain clamp is needed to eliminate the high frequency prevent premature termination of the ON-cycle. Verify that
ring. Figure 24 shows the desired waveform. Notice in Figure 25 the leading edge current spike is below the allowed current
the negative excursion due to the leakage inductance ring. This limit envelope for the drain current waveform at the end of
spike will reduce the output voltage regulation performance and the 170 ns blanking period.
can be improved by adjusting the damping resistor in series 3. Thermal check – At maximum output power, both minimum
with the clamp diode (RC1 in Figure 14). and maximum input voltage and maximum ambient tempera-
ture; verify that temperature specifications are not exceeded
for LinkSwitch-CV, transformer, output diodes and output
PI-5093-041408

capacitors. Enough thermal margin should be allowed for the

part-to-part variation of the RDS(ON) of LinkSwitch-CV, as
specified in the data sheet. The maximum source pin
An overshoot temperature is 110 °C.
is acceptable

Figure 24. Desired Drain Waveform.

PI-5094-042408

Negative ring may

increase output
ripple and/or
degrade output
regulation

Figure 25. Undesirable Drain Waveform.

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AN-45 Application Note

Notes

17
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 Revision Notes Date
A Initial Release. 11/08
B Revised Figure 20. 01/09
B Updated Figures 21 and 22. 03/27/13
C Updated with new PI style. 12/17

For the latest updates, visit our website: www.power.com

Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does
not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND
SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.

Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or
more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power
Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set forth at
http://www.power.com/ip.htm.

Life Support Policy

POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to
perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or
death to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of
the life support device or system, or to affect its safety or effectiveness.

The PI logo, TOPSwitch, TinySwitch, SENZero, SCALE, SCALE-iDriver, SCALE-iFlex, Qspeed, PeakSwitch, LYTSwitch, LinkZero, LinkSwitch,
InnoSwitch, HiperTFS, HiperPFS, HiperLCS, DPA-Switch, CAPZero, Clampless, EcoSmart, E-Shield, Filterfuse, FluxLink, StakFET, PI Expert and PI
FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©2017, Power Integrations, Inc.

Power Integrations Worldwide Sales Support Locations

World Headquarters Germany (AC-DC/LED Sales) Italy Singapore

5245 Hellyer Avenue Lindwurmstrasse 114 Via Milanese 20, 3rd. Fl. 51 Newton Road
San Jose, CA 95138, USA D-80337 München 20099 Sesto San Giovanni (MI) Italy #19-01/05 Goldhill Plaza
Main: +1-408-414-9200 Germany Phone: +39-024-550-8701 Singapore, 308900
Customer Service: Phone: +49-89-5527-39100 e-mail: eurosales@power.com Phone: +65-6358-2160
Worldwide: +1-65-635-64480 e-mail: eurosales@power.com e-mail: singaporesales@power.com
Japan
Americas: +1-408-414-9621
Germany (Gate Driver Sales) Yusen Shin-Yokohama 1-chome Bldg. Taiwan
e-mail: usasales@power.com
HellwegForum 1 1-7-9, Shin-Yokohama, Kohoku-ku 5F, No. 318, Nei Hu Rd., Sec. 1
China (Shanghai) 59469 Ense Yokohama-shi, Kanagawa Nei Hu Dist.
Rm 2410, Charity Plaza, No. 88 Germany 222-0033 Japan Taipei 11493, Taiwan R.O.C.
North Caoxi Road Tel: +49-2938-64-39990 Phone: +81-45-471-1021 Phone: +886-2-2659-4570
Shanghai, PRC 200030 e-mail: igbt-driver.sales@ e-mail: japansales@power.com e-mail: taiwansales@power.com
Phone: +86-21-6354-6323 power.com
Korea UK
e-mail: chinasales@power.com
India RM 602, 6FL Building 5, Suite 21
China (Shenzhen) #1, 14th Main Road Korea City Air Terminal B/D, 159-6 The Westbrook Centre
17/F, Hivac Building, No. 2, Keji Nan Vasanthanagar Samsung-Dong, Kangnam-Gu, Milton Road
8th Road, Nanshan District, Bangalore-560052 India Seoul, 135-728, Korea Cambridge
Shenzhen, China, 518057 Phone: +91-80-4113-8020 Phone: +82-2-2016-6610 CB4 1YG
Phone: +86-755-8672-8689 e-mail: indiasales@power.com e-mail: koreasales@power.com Phone: +44 (0) 7823-557484
e-mail: chinasales@power.com e-mail: eurosales@power.com