Curiosity Datasheet

PIC16(L)F1615/9
14/20-Pin, 8-Bit Flash Microcontroller
Description
PIC16(L)F1615/9 microcontrollers deliver on-chip features that are unique to the design for embedded control of small
motors and general purpose applications in 14/20-pin count packages. Features like 10-bit A/D, CCP, 24-bit SMT and
Zero-Cross Detection offer an excellent solution to the variety of applications. The product family also has a CRC+
memory scan and Windowed WDT to support safety-critical systems in home appliances, white goods and other end
equipment.
Core Features Digital Peripherals

• C Compiler Optimized RISC Architecture • Configurable Logic Cell (CLC):
• Only 49 Instructions - Four CLCs
• Operating Speed: - Integrated combinational and sequential logic
- DC – 32 MHz clock input • Complementary Waveform Generator (CWG):
- 125 ns minimum instruction cycle - Rising and falling edge dead-band control
• Interrupt Capability - Full-bridge, half-bridge, 1-channel drive
• 16-Level Deep Hardware Stack - Multiple signal sources
• One 8-Bit Timer • Two Capture/Compare/PWM (CCP) modules
• Four 16-bit Timers • PWM: Two 10-bit Pulse-Width Modulators
• Low Current Power-on Reset (POR) • Two Signal Measurement Timers (SMT):
• Configurable Power-up Timer (PWRT) - 24-bit timer/counter with prescaler
• Brown-out Reset (BOR) with Selectable Trip Point - Multiple gate and clock inputs
• Windowed Watchdog Timer (WWDT): • Angular Timer:
- Variable prescaler selection - Single pulse
- Variable window size selection - Multiple pulses with missing pulse recovery
- All sources configurable in hardware or • 8-Bit Timers (TMR2+HLT/4/6):
software - Up to 3 Timer2/4/6 with Hardware Limit Timer
(HLT)
Memory - Monitors Fault Conditions: Stall, Stop, etc.
• 8 KW Flash Program Memory - Multiple modes
• 1024 Bytes Data SRAM - 8-bit timer/counter with prescaler
• Direct, Indirect and Relative Addressing modes - 8-bit period register and postscaler
• High-Endurance Flash Data Memory (HEF): - Asynchronous H/W Reset sources
- 128 B of nonvolatile data storage • Math Accelerator with Proportional-Integral-
- 100K erase/write cycles Derivative (PID):
- Four operation modes
Operating Characteristics - Add and multiply
• Operating Voltage Range: - Simple multiplier
- 1.8V to 3.6V (PIC16LF1615/9) - Multiply and Accumulate
- 2.3V to 5.5V (PIC16F1615/9) - Programmable PID controller
• Temperature Range: • Cyclic Redundancy Check with Memory Scan
- Industrial: -40°C to 85°C (CRC/SCAN):
- Extended: -40°C to 125°C - Software configurable
• Serial Communications:
eXtreme Low-Power (XLP) Features - Enhanced USART (EUSART)
- SPI, I2C, RS-232, RS-485, LIN compatible
• Sleep mode: 50 nA @ 1.8V, typical - Auto-Baud Detect, Auto-Wake-up on start
• Watchdog Timer: 500 nA @ 1.8V, typical
• Operating Current:
- 8 uA @ 32 kHz, 1.8V, typical
- 32 uA/MHz @ 1.8V, typical
 2014-2017 Microchip Technology Inc. DS40001770D-page 1

PIC16(L)F1615/9
• Up to 17 I/O Pins and One Input-only Pin: Clocking Structure
- Individually programmable pull-ups
- Slew rate control • 16 MHz Internal Oscillator:
- Interrupt-on-change with edge-select - ±1% at calibration
- Two High Current Drive pins - Selectable frequency range from 32 MHz to
• Peripheral Pin Select (PPS): 31 kHz
- Enables pin mapping of digital I/O • 31 kHz Low-Power Internal Oscillator
• 4x Phase-Locked Loop (PLL):
- For up to 32 MHz internal operation
Intelligent Analog Peripherals
• External Oscillator Block with:
• 10-Bit Analog-to-Digital Converter (ADC): - Three external clock modes up to 32 MHz
- Up to 12 external channels - One crystal resonator mode up to 32 MHz
- Conversion available during Sleep • Fail-Safe Clock Monitor:
• Two Comparators (COMP): - Allows for safe shutdown if peripheral clock
- Low-Power/High-Speed mode stops
- Up to three external inverting inputs • Two-Speed Oscillator Start-up
- Fixed Voltage Reference at non-inverting • Oscillator Start-up Timer (OST)
input(s)
- Comparator outputs externally accessible
• 8-Bit Digital-to-Analog Converter (DAC):
- 8-bit resolution, rail-to-rail
- Positive Reference Selection
• Voltage Reference:
- Fixed Voltage Reference (FVR): 1.024V,
2.048V and 4.096V output levels
• Zero-Cross Detect (ZCD):
- Detect when AC signal on pin crosses
ground
• Two High-Current Drive Pins:
- 100mA @ 5V

 2014-2017 Microchip Technology Inc.
TABLE 1: PIC12/16(L)F161X FAMILY TYPES
Math Accelerator with PID
High-Current I/O 100mA

CRC with Memory Scan
Program Memory Flash
Program Memory Flash
High Endurance Flash
Windowed Watchdog
8-bit Timer with HLT
Zero-Cross Detect
Data Sheet Index
CCP/10-bit PWM
10-bit ADC (ch)
Angular Timer
Comparators
16-bit Timer
Data SRAM
24-bit SMT
EUSART
I/O Pins
I2C/SPI
(bytes)
(bytes)
Timer
CWG
CLC
PPS
(kB)
(W)
Device
PIC12(L)F1612 (A) 2048 3.5 256 256 6 4 1 0 Y 1 1 4 1 2/0 1 0 Y 0 0 N 0 0

PIC16(L)F1613 (A) 2048 3.5 256 256 12 4 1 0 Y 2 2 8 1 2/0 1 0 Y 0 0 N 0 0
PIC16(L)F1614 (B) 4096 7 512 128 12 4 3 1 Y 2 2 8 1 2/2 1 2 Y 1 2 Y 1 1
PIC16(L)F1615 (C) 8192 14 1024 1024 12 4 3 1 Y 2 2 8 1 2/2 1 4 Y 1 2 Y 1 1
PIC16(L)F1618 (B) 4096 7 512 128 18 4 3 1 Y 2 2 12 1 2/2 1 2 Y 1 2 Y 1 1
PIC16(L)F1619 (C) 8192 14 1024 1024 18 4 3 1 Y 2 2 12 1 2/2 1 4 Y 1 2 Y 1 1
Note 1: Debugging Methods: (I) – Integrated on Chip; E – using Emulation Product
Data Sheet Index:
A. DS40001737 PIC12(L)F1612/16(L)F1613 Data Sheet, 8/14-Pin, 8-bit Flash Microcontrollers
B. DS40001769 PIC16(L)F1614/8 Data Sheet, 14/20-Pin, 8-bit Flash Microcontrollers
C. DS40001770 PIC16(L)F1615/9 Data Sheet, 14/20-Pin, 8-bit Flash Microcontrollers
Note: For other small form-factor package availability and marking information, please visit
PIC16(L)F1615/9
http://www.microchip.com/packaging or contact your local sales office.
DS40001770D-page 3
PIC16(L)F1615/9
TABLE 2: PACKAGES
Packages PDIP SOIC DFN UDFN TSSOP QFN UQFN SSOP
PIC16(L)F1615    
PIC16(L)F1619     
Note: Pin details are subject to change.
PIN DIAGRAMS
14-pin PDIP, SOIOC, TSSOP

VDD 1 14 VSS
RA5 2 13 RA0/ICSPDAT
RA4 3 12 RA1/ICSPCLK
PIC16(L)F1615
MCLR/VPP/RA3 4 11 RA2
RC5 5 10 RC0
RC4 6 9 RC1
RC3 7 8 RC2
16-pin UQFN
VDD
Vss
NC
NC
16 15 14 13
RA5 1 12 RA0
PI
C
RA4
16
2 11 RA1
(L
RA3/MCLR/VPP
)
3 10 RA2
F1
61
RC5 4 9 RC0
5
5 6 7 8
RC3
RC1
RC4
RC2
20-pin PDIP, SOIC, SSOP
VDD 1 20 VSS
RA5 2 19 RA0
RA4 3 18 RA1
MCLR/VPP/RA3 4 17 RA2
PIC16(L)F1619
RC5 5 16 RC0
RC4 6 15 RC1
RC3 7 14 RC2
RC6 8 13 RB4
RC7 9 12 RB5
RB7 10 11 RB6

PIC16(L)F1615/9
20-pin QFN, UQFN
RA4
RA5
RA0
VDD
Vss
20 19 18 17 16
RA3/MCLR/VPP 1 15 RA1
9
RC5 2 14
61
RA2
RC4 3
F1
13 RC0
L)
RC3 4 12 RC1
(
RC6
16
5 11 RC2
C
PI
6 7 8 9 10
RC7
RB7
RB4
RB6
RB5

PIN ALLOCATION TABLES
TABLE 3: 14/16-PIN ALLOCATION TABLE (PIC16(L)F1615)

14-Pin PDIP, SOIC, TSSOP
High Current I/O

Angular Timer
16-Pin UQFN
Comparator
Reference
Interrupt
EUSART
Pull-up
Timers
MSSP
Basic
PWM
CWG
CCP
SMT
ZCD
CLC
A/D
I/O
RA0 13 12 AN0 DAC1OUT1 C1IN+ — — — — — — — — — — — IOC Y ICSPDAT

RA1 12 11 AN1 VREF+ C1IN0- — — — — — — — — — — — IOC Y ICSPCLK
C2IN0-
RA2 11 10 AN2 — — T0CKI(1) — CWG1IN(1) ZCD1IN — — — — — — — INT Y —
IOC
RA3 4 3 — — — T6IN(1) — — — — — SMTWIN2(1) — — — — IOC Y MCLR/VPP
RA4 3 2 AN3 — — T1G (1)
— — — — — SMTSIG1(1) — — — — IOC Y CLKOUT
RA5 2 1 — — — T1CKI(1) — — — — — SMTWIN1(1) — — — — IOC Y CLKIN
T2IN(1)
RC0 10 9 AN4 — C2IN+ T5CKI(1) — — — — — — — SCK(1,3) — — IOC Y —
(1) (1)
RC1 9 8 AN5 — C1IN1- T4IN(1) — — — — — SMTSIG2 — SDI — — IOC Y —
C2IN1-
RC2 8 7 AN6 — C1IN2- — — — — — — — — — — — IOC Y —
C2IN2-
RC3 7 6 AN7 — C1IN3- T5G(1) CCP2(1) — — CLCIN0(1) — — ATCC1(1) SS(1) — — IOC Y —
C2IN3-
PIC16(L)F1615/9
RC4 6 5 — — — T3G(1) — — — CLCIN1(1) CK(1) — ATCC2(1) — — HIC4 IOC Y —
RC5 5 4 — — — T3CKI (1)
CCP1 (1)
— — — RX(1,3) — ATIN(1) — — HIC5 IOC Y —
(1)
ATCC3
VDD 1 16 — — — — — — — — — — — — — — — — VDD
VSS 14 13 — — — — — — — — — — — — — — — — VSS
— — — — C1OUT — CCP1 CWG1A ZCD1OUT CLC1OUT DT(3) — — SDO PWM3OUT — — — —

DS40001770D-page 6
— — — — C2OUT — CCP2 CWG1B — CLC2OUT CK — — SCK(3) PWM4OUT — — — —

OUT(2)
— — — — — — — CWG1C — — TX — — — — — — — —
— — — — — — — CWG1D — — — — — — — — — — —
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
TABLE 4: 20-Pin PDIP, SOIC, SSOP 20-PIN ALLOCATION TABLE (PIC16(L)F1619)
High Current I/O

Angular Timer
20-Pin UQFN
Comparator
Reference
Interrupt
EUSART
Pull-up
Timers
MSSP
Basic
PWM
CWG
CCP
SMT
ZCD
CLC
A/D
I/O
RA0 19 16 AN0 DAC1OUT C1IN+ — — — — — — — — — — — IOC Y ICSPDAT

RA1 18 15 AN1 VREF+ C1IN0- — — — — — — — — — — — IOC Y ICSPCLK
C2IN0-
RA2 17 14 AN2 — — T0CKI(1) — CWG1IN(1) ZCD1IN — — — — — — — INT Y —
IOC
RA3 4 1 — — — T6IN(1) — — — — — SMTWIN2(1) — — — — IOC Y MCLR
VPP
RA4 3 20 AN3 — — T1G(1) — — — — — SMTSIG1(1) — — — — IOC Y CLKOUT
RA5 2 19 — — — T1CKI(1) — — — CLCIN3(1) — SMTWIN1(1) — — — — IOC Y CLKIN
T2IN(1)
RB4 13 10 AN10 — — — — — — — — — — SDI(1) — — IOC Y —
(1,3)
RB5 12 9 AN11 — — — — — — — RX — — — — — IOC Y —
RB6 11 8 — — — — — — — — — — — SCK(1,3) — — IOC Y —
RB7 10 7 — — — — — — — — CK(1) — — — — — IOC Y —
RC0 16 13 AN4 — C2IN+ T5CKI (1)
— — — — — — — — — — IOC Y —
RC1 15 12 AN5 — C1IN1- T4IN(1) — — — CLCIN2(2) — SMTSIG2(1) — — — — IOC Y —
C2IN1-
RC2 14 11 AN6 — C1IN2- — — — — — — — — — — — IOC Y —
PIC16(L)F1615/9
C2IN2-
RC3 7 4 AN7 — C1IN3- T5G(1) CCP2(1) — — CLCIN0(1) — — ATCC(1) — — — IOC Y —
C2IN3-
RC4 6 3 — — — T3G(1) — — — CLCIN1(1) — — — — — HIC4 IOC Y —
RC5 5 2 — — — T3CKI(1) CCP1(1) — — — — — ATIN(1) — — HIC5 IOC Y —
RC6 8 5 AN8 — — — — — — — — — — SS(1) — — IOC Y —
DS40001770D-page 7
RC7 9 6 AN9 — — — — — — — — — — — — — IOC Y —

VDD 1 18 — — — — — — — — — — — — — — — — —
VSS 20 17 — — — — — — — — — — — — — — — — —
TABLE 4: 20-PIN ALLOCATION TABLE (PIC16(L)F1619)
20-Pin PDIP, SOIC, SSOP
High Current I/O

Angular Timer
20-Pin UQFN
Comparator
Reference
EUSART
Interrupt
Pull-up
Timers
MSSP
Basic
PWM
CWG
CCP
SMT
ZCD
CLC
A/D
I/O
— — — — C1OUT — CCP1 CWG1A ZCD1OUT CLC1OUT DT(3) — — SDO PWM3OUT — — — —

— — — — C2OUT — CCP2 CWG1B — CLC2OUT CK — — SCK(3) PWM4OUT — — — —
OUT(2)
— — — — — — — CWG1C — CLC3OUT TX — — — — — — — —
— — — — — — — CWG1D — CLC4OUT — — — — — — — — —
PIC16(L)F1615/9
DS40001770D-page 8
PIC16(L)F1615/9
TABLE OF CONTENTS
Device Overview ................................................................................................................................................................................. 11

Enhanced Mid-Range CPU ................................................................................................................................................................. 19
Memory Organization .......................................................................................................................................................................... 21
Device Configuration ........................................................................................................................................................................... 66
Oscillator Module ................................................................................................................................................................................ 73
Resets ................................................................................................................................................................................................. 84
Interrupts ............................................................................................................................................................................................. 92
Power-Down Mode (Sleep) ............................................................................................................................................................... 109
Windowed Watchdog Timer (WDT) .................................................................................................................................................. 112
Flash Program Memory Control ........................................................................................................................................................ 120
Cyclic Redundancy Check (CRC) Module ........................................................................................................................................ 136
I/O Ports ............................................................................................................................................................................................ 148
Peripheral Pin Select (PPS) Module ................................................................................................................................................. 170
Interrupt-On-Change ......................................................................................................................................................................... 178
Fixed Voltage Reference (FVR) ........................................................................................................................................................ 184
Temperature Indicator Module .......................................................................................................................................................... 187
Analog-to-Digital Converter (ADC) Module ....................................................................................................................................... 189
8-bit Digital-to-Analog Converter (DAC1) Module ............................................................................................................................. 203
Comparator Module .......................................................................................................................................................................... 207
Zero-Cross Detection (ZCD) Module ................................................................................................................................................ 215
Timer0 Module .................................................................................................................................................................................. 221
Timer1/3/5 Module with Gate Control ............................................................................................................................................... 224
Timer2/4/6 Module ............................................................................................................................................................................ 235
Master Synchronous Serial Port (MSSP) Module ............................................................................................................................. 260
Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ........................................................................ 313
Capture/Compare/PWM Modules ..................................................................................................................................................... 345
Pulse-Width Modulation (PWM) Module ........................................................................................................................................... 359
Complementary Waveform Generator (CWG) Module ..................................................................................................................... 365
Signal Measurement Timer (SMT) .................................................................................................................................................... 391
Configurable Logic Cell (CLC) .......................................................................................................................................................... 437
Angular Timer (AT) Module ............................................................................................................................................................... 451
Math Accelerator with Proportional-Integral-Derivative (PID) Module ............................................................................................... 480
In-Circuit Serial Programming™ (ICSP™) ........................................................................................................................................ 496
Instruction Set Summary ................................................................................................................................................................... 498
Electrical Specifications .................................................................................................................................................................... 512
DC and AC Characteristics Graphs and Charts ................................................................................................................................ 536
Development Support ....................................................................................................................................................................... 555
Packaging Information ...................................................................................................................................................................... 559
Data Sheet Revision History ............................................................................................................................................................. 583

PIC16(L)F1615/9
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PIC16(L)F1615/9
1.0 DEVICE OVERVIEW
TABLE 1-1: DEVICE PERIPHERAL
The PIC16(L)F1615/9 are described within this data
SUMMARY
sheet. The block diagram of these devices are shown in
PIC16(L)F1615
PIC16(L)F1619
Figure 1-1, the available peripherals are shown in
Table 1-1, and the pin out descriptions are shown in
Tables 1-2 and 1-3. Peripheral
Analog-to-Digital Converter (ADC) ● ●

Complementary Wave Generator (CWG) ● ●
Cyclic Redundancy Check (CRC) ● ●
Digital-to-Analog Converter (DAC) ● ●
Enhanced Universal ● ●
Synchronous/Asynchronous
Receiver/Transmitter (EUSART)
Fixed Voltage Reference (FVR) ● ●
Temperature Indicator ● ●
Windowed Watchdog Timer (WDT) ● ●
Zero-Cross Detection (ZCD) ● ●
Capture/Compare/PWM (CCP) Modules
CCP1 ● ●
CCP2 ● ●
Comparators
C1 ● ●
C2 ● ●
Configurable Logic Cell (CLC)
CLC1 ● ●
CLC2 ● ●
CLC3 ● ●
CLC4 ● ●
Master Synchronous Serial Ports
MSSP1 ● ●
Pulse-Width Modulator (PWM)
PWM3 ● ●
PWM4 ● ●
Signal Measurement Timer (SMT)
SMT1 ● ●
SMT2 ● ●
Timers
Timer0 ● ●
Timer1 ● ●
Timer2 ● ●
Timer3 ● ●
Timer4 ● ●
Timer5 ● ●
Timer6 ● ●

PIC16(L)F1615/9
1.1 Register and Bit Naming 1.1.2.3 Bit Fields
Conventions Bit fields are two or more adjacent bits in the same
register. Bit fields adhere only to the short bit naming
1.1.1 REGISTER NAMES convention. For example, the three Least Significant
When there are multiple instances of the same bits of the COG1CON0 register contain the mode
peripheral in a device, the peripheral control registers control bits. The short name for this field is MD. There
will be depicted as the concatenation of a peripheral is no long bit name variant. Bit field access is only
identifier, peripheral instance, and control identifier. possible in C programs. The following example
The control registers section will show just one demonstrates a C program instruction for setting the
instance of all the register names with an ‘x’ in the place COG1 to the Push-Pull mode:
of the peripheral instance number. This naming COG1CON0bits.MD = 0x5;
convention may also be applied to peripherals when
Individual bits in a bit field can also be accessed with
there is only one instance of that peripheral in the
long and short bit names. Each bit is the field name
device to maintain compatibility with other devices in
appended with the number of the bit position within the
the family that contain more than one.
field. For example, the Most Significant mode bit has
1.1.2 BIT NAMES the short bit name MD2 and the long bit name is
G1MD2. The following two examples demonstrate
There are two variants for bit names: assembly program sequences for setting the COG1 to
• Short name: Bit function abbreviation Push-Pull mode:
• Long name: Peripheral abbreviation + short name Example 1:
MOVLW ~(1<<G1MD1)
1.1.2.1 Short Bit Names ANDWF COG1CON0,F
Short bit names are an abbreviation for the bit function. MOVLW 1<<G1MD2 | 1<<G1MD0
For example, some peripherals are enabled with the IORWF COG1CON0,F
EN bit. The bit names shown in the registers are the Example 2:
short name variant.
BSF COG1CON0,G1MD2
Short bit names are useful when accessing bits in C BCF COG1CON0,G1MD1
programs. The general format for accessing bits by the BSF COG1CON0,G1MD0
short name is RegisterNamebits.ShortName. For
example, the enable bit, EN, in the COG1CON0 regis- 1.1.3 REGISTER AND BIT NAMING
ter can be set in C programs with the instruction EXCEPTIONS
COG1CON0bits.EN = 1.
1.1.3.1 Status, Interrupt, and Mirror Bits
Short names are generally not useful in assembly
programs because the same name may be used by Status, interrupt enables, interrupt flags, and mirror bits
different peripherals in different bit positions. When this are contained in registers that span more than one
occurs, during the include file generation, all instances peripheral. In these cases, the bit name shown is
of that short bit name are appended with an underscore unique so there is no prefix or short name variant.
plus the name of the register in which the bit resides to
avoid naming contentions. 1.1.3.2 Legacy Peripherals
There are some peripherals that do not strictly adhere
1.1.2.2 Long Bit Names to these naming conventions. Peripherals that have
Long bit names are constructed by adding a peripheral existed for many years and are present in almost every
abbreviation prefix to the short name. The prefix is device are the exceptions. These exceptions were
unique to the peripheral, thereby making every long bit necessary to limit the adverse impact of the new
name unique. The long bit name for the COG1 enable conventions on legacy code. Peripherals that do
bit is the COG1 prefix, G1, appended with the enable adhere to the new convention will include a table in the
bit short name, EN, resulting in the unique bit name registers section indicating the long name prefix for
G1EN. each peripheral instance. Peripherals that fall into the
exception category will not have this table. These
Long bit names are useful in both C and assembly pro-
peripherals include, but are not limited to, the following:
grams. For example, in C the COG1CON0 enable bit
can be set with the G1EN = 1 instruction. In assembly, • EUSART
this bit can be set with the BSF COG1CON0,G1EN • MSSP
instruction.

FIGURE 1-1: PIC16(L)F1615/9 BLOCK DIAGRAM
PIC16(L)F1615/9
Rev. 10-000039H
Program 5/23/2014
Flash Memory
RAM
PORTA
CLKOUT
(4)
/OSC2 Timing PORTB
Generation
CPU
CLKIN/
OSC1 INTRC PORTC
Oscillator
(Note 3)
MCLR
Temp ADC
TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0 PWM4 PWM3 C2 C1 DAC FVR
Indicator 10-bit
CWG1 SMT2 SMT1 AT PID EUSART MSSP CLC4 CLC3 CLC2 CLC1 Scanner CRC ZCD1 CCP2 CCP1
Note 1: See applicable chapters for more information on peripherals.

2: See Table 1-1 for peripherals available on specific devices.
3: See Figure 2-1.
4: PIC16(L)F1619 only.
DS40001770D-page 13
PIC16(L)F1615/9
TABLE 1-2: PIC16(L)F1615 PINOUT DESCRIPTION

Input Output
Name Function Description
Type Type
RA0/AN0/C1IN+/DAC1OUT1/ RA0 TTL/ST CMOS/OD General purpose I/O.

ICSPDAT AN0 AN — ADC Channel input.
C1IN+ AN — Comparator positive input.
DAC1OUT1 — AN Digital-to-Analog Converter output.
ICSPDAT ST CMOS ICSP™ Data I/O.
RA1/AN1/VREF+/C1IN0-/C2IN0-/ RA1 TTL/ST CMOS/OD General purpose I/O.
ICSPCLK AN1 AN — ADC Channel input.
VREF+ AN — Voltage Reference input.
C1IN0- AN — Comparator negative input.
C2IN0- AN CMOS/OD Comparator negative input.
ICSPCLK ST — ICSP Programming Clock.
RA2/AN2/T0CKI(1)/CWG1IN(1) RA2 TTL/ST CMOS/OD General purpose I/O.
ZCD1IN/INT AN2 AN — ADC Channel input.
T0CKI TTL/ST — Timer0 clock input.
CWG1IN TTL/ST — CWG complementary input.
ZCD1IN AN — Zero-Cross Detect input.
INT TTL/ST — External interrupt.
RA3/VPP/T6IN(1)/SMTWIN2(1)/ RA3 TTL/ST — General purpose input with IOC and WPU.
MCLR VPP HV — Programming voltage.
T6IN TTL/ST — Timer6 input.
SMTWIN2 TTL/ST — SMT2 window input.
MCLR TTL/ST — Master Clear with internal pull-up.
RA4/AN3/T1G(1)/SMTSIG1(1)/ RA4 TTL/ST CMOS/OD General purpose I/O.
CLKOUT AN3 AN — ADC Channel input.
T1G TTL/ST — Timer1 Gate input.
SMTSIG1 TTL/ST — SMT1 signal input.
CLKOUT — CMOS FOSC/4 output.
RA5/CLKIN/T1CKI(1)/T2IN(1)/ RA5 TTL/ST CMOS/OD General purpose I/O.
SMTWIN1(1) CLKIN CMOS — External clock input (EC mode).
RC0/AN4/C2IN+/T5CKI(1)/ RC0 TTL/ST CMOS/OD General purpose I/O.
SCK(1) AN4 AN — ADC Channel input.
SCK ST CMOS SPI clock.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection
registers. See Register 13-1.

PIC16(L)F1615/9
TABLE 1-2: PIC16(L)F1615 PINOUT DESCRIPTION (CONTINUED)
Input Output
Type Type
RC1/AN5/C1IN1-/C2IN1-/ RC1 TTL/ST CMOS/OD General purpose I/O.
T4IN(1)/SMTSIG2(1)/SDI(1) AN5 AN — ADC Channel input.
SDI CMOS — SPI data input.
RC2/AN6/C1IN2-/C2IN2- RC2 TTL/ST CMOS/OD General purpose I/O.
AN6 AN — ADC Channel input.
RC3/AN7/C1IN3-/C2IN3-/T5G(1)/ RC3 TTL/ST — General purpose input with IOC and WPU.
CCP2(1)/CLCIN0(1)/ATCC(1)/SS AN7 AN — ADC Channel input.
T5G ST — Timer5 Gate input.
CCP2 TTL/ST CMOS/OD Capture/Compare/PWM2.
CLCIN0 ST — Configurable Logic Cell source input.
ATCC ST — Angular Timer Capture/Compare input.
SS ST — Slave Select input.
RC4/T3G(1)/CLCIN1(1)/CK(1)/ RC4 TTL/ST CMOS/OD General purpose I/O.
HIC4 T3G TTL/ST — Timer3 Gate input.
CK ST CMOS EUSART synchronous clock.
HIC4 TTL CMOS High current I/O.
(1) (1) (1)
RC5/T3CKI /CCP1 /RX / RC5 TTL/ST CMOS/OD General purpose I/O.
ATIN(1)/HIC5 T3CKI TTL/ST — Timer3 clock input.
RX ST — EUSART asynchronous input.
ATIN TTL/ST — Angular Timer clock input.

PIC16(L)F1615/9
Input Output
Type Type
OUT(2) C1OUT — CMOS Comparator output.
C2OUT — CMOS Comparator output.
CCP1 — CMOS Capture/Compare/PWM1 output.
PWM3OUT — CMOS PWM3 output.
CWG1A — CMOS Complementary Output Generator Output A.
CWG1B — CMOS Complementary Output Generator Output B.
CWG1C — CMOS Complementary Output Generator Output C.
CWG1D — CMOS Complementary Output Generator Output D.
SDO — CMOS SPI data output.
SCK — CMOS SPI clock output.
TX/CK CMOS EUSART asynchronous TX data/synchronous clock
—
output.
DT — CMOS EUSART synchronous data output.E
CLC1OUT — CMOS Configurable Logic Cell 1 source output.
ZCD1OUT — CMOS Zero-Cross Detect output.
VDD VDD Power — Positive supply.
VSS VSS Power — Ground reference.

PIC16(L)F1615/9
TABLE 1-3: PIC16(L)F1619 PINOUT DESCRIPTION

Input Output
Type Type
RA0/AN0/C1IN+/DAC1OUT/ RA0 TTL/ST CMOS/OD General purpose I/O.

ICSPDAT AN0 AN — ADC Channel input.
DAC1OUT — AN Digital-to-Analog Converter output.
ICSPDAT ST CMOS ICSP™ Data I/O.
RA1/AN1/VREF+/C1IN0-/C2IN0-/ RA1 TTL/ST CMOS/OD General purpose I/O.
ICSPCLK AN1 AN — ADC Channel input.
VREF+ AN — Voltage Reference input.
C2IN0- AN CMOS/OD Comparator negative input.
ICSPCLK ST ICSP Programming Clock.
RA2/AN2/T0CKI(1)/CWG1IN(1)/ RA2 TTL/ST CMOS/OD General purpose I/O.
ZCD1IN/INT AN2 AN — ADC Channel input.
CWG1IN TTL/ST — CWG complementary input.
ZCD1IN AN — Zero-Cross Detect input.
INT TTL/ST — External interrupt.
RA3/VPP/T6IN(1)/SMTWIN2(1)/ RA3 TTL/ST — General purpose input with IOC and WPU.
MCLR VPP HV — Programming voltage.
MCLR TTL/ST — Master Clear with internal pull-up.
RA4/AN3/T1G(1)/SMTSIG1(1)/ RA4 TTL/ST CMOS/OD General purpose I/O.
CLKOUT AN3 AN — ADC Channel input.
T1G TTL/ST — Timer1 Gate input.
CLKOUT — CMOS FOSC/4 output.
RA5/CLKIN/T1CKI(1)/T2IN(1)/ RA5 TTL/ST CMOS/OD General purpose I/O.
CLCIN3(1)/SMTWIN1 CLKIN CMOS — External clock input (EC mode).
(1)
RB4/AN10/SDI RB4 TTL/ST CMOS/OD General purpose I/O.
SDI CMOS — SPI data input.
RB5/AN11/RX(1, 3) RB5 TTL/ST CMOS/OD General purpose I/O.
RX ST — EUSART asynchronous input.
3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections.

PIC16(L)F1615/9
Input Output
Type Type
RB6/SCK(1, 3) RB6 TTL/ST CMOS/OD General purpose I/O.

SCK ST CMOS SPI clock.
RB7/CK(1) RB7 TTL/ST CMOS/OD General purpose I/O.
CK ST CMOS EUSART synchronous clock.
RC0/AN4/C2IN+/T5CKI(1) RC0 TTL/ST CMOS/OD General purpose I/O.
RC1/AN5/C1IN1-/C2IN1-/ RC1 TTL/ST CMOS/OD General purpose I/O.
T4IN(1)/CLCIN2(2)/SMTSIG2(1) AN5 AN — ADC Channel input.
RC2/AN6/C1IN2-/C2IN2- RC2 TTL/ST CMOS/OD General purpose I/O.
RC3/AN7/C1IN3-/C2IN3-/T5G(1)/ RC3 TTL/ST — General purpose input with IOC and WPU.
CCP2(1)/CLCIN0(1)/ATCC(1) AN7 AN — ADC Channel input.
CCP2 ST CMOS Capture/Compare/PWM2.
ATCC ST — Angular Timer Capture/Compare input.
RC4/T3G(1)/CLCIN1(1)/HIC4 RC4 TTL/ST CMOS/OD General purpose I/O.
RC5/T3CKI(1)/CCP1(1)/ATIN(1)/ RC5 TTL/ST CMOS/OD General purpose I/O.
HIC5 T3CKI TTL/ST — Timer3 clock input.
ATIN TTL/ST — Angular Timer clock input.
RC6/AN8/SS(1) RC6 TTL/ST CMOS/OD General purpose I/O.
SS ST — SPI slave select.
RC7/AN9 RC7 TTL/ST CMOS/OD General purpose I/O.

PIC16(L)F1615/9
Input Output
Type Type
OUT(2) C1OUT — CMOS Comparator output.
C2OUT — CMOS Comparator output.
CWG1A — CMOS Complementary Output Generator Output A.
CWG1B — CMOS Complementary Output Generator Output B.
CWG1C — CMOS Complementary Output Generator Output C.
CWG1D — CMOS Complementary Output Generator Output D.
SDO — CMOS SPI data output.
SCK — CMOS SPI clock output.
TX/CK CMOS EUSART asynchronous TX data/synchronous clock
—
output.
DT — CMOS EUSART synchronous data output.
ZCD1OUT — CMOS Zero-Cross Detect output.
VDD VDD Power — Positive supply.
VSS VSS Power — Ground reference.

PIC16(L)F1615/9
2.0 ENHANCED MID-RANGE CPU
This family of devices contain an enhanced mid-range
8-bit CPU core. The CPU has 49 instructions. Interrupt
capability includes automatic context saving. The
hardware stack is 16 levels deep and has Overflow and
Underflow Reset capability. Direct, Indirect, and
Relative Addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
program and data memory.
• Automatic Interrupt Context Saving
• 16-level Stack with Overflow and Underflow
• File Select Registers
• Instruction Set
FIGURE 2-1: CORE BLOCK DIAGRAM
Rev. 10-000055A
7/30/2013
15 Configuration
15 Data Bus 8
Program Counter
Flash
MUX
Program
Memory
16-Level Stack
RAM
(15-bit)
14
Program 12
Program Memory RAM Addr
Bus
Read (PMR)
Addr MUX
Instruction Reg
Indirect
Direct Addr 7 Addr
12
5 12
BSR Reg
15
FSR0 Reg
15 FSR1 Reg
STATUS Reg
8
3 MUX
Power-up
Instruction
Timer
Decode and
Power-on
Control
Reset ALU
8
Watchdog
CLKIN Timer
Timing
Generation Brown-out
CLKOUT Reset W Reg
Internal
Oscillator VDD VSS
Block

PIC16(L)F1615/9
2.1 Automatic Interrupt Context
Saving
During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 7.5 “Automatic Context Saving”,
for more information.
2.2 16-Level Stack with Overflow and

Underflow
These devices have a hardware stack memory 15 bits
wide and 16 words deep. A Stack Overflow or Under-
flow will set the appropriate bit (STKOVF or STKUNF)
in the PCON register, and if enabled, will cause a soft-
ware Reset. See section Section 3.5 “Stack” for more
details.
2.3 File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers and program memory,
which allows one Data Pointer for all memory. When an
FSR points to program memory, there is one additional
instruction cycle in instructions using INDF to allow the
data to be fetched. General purpose memory can now
also be addressed linearly, providing the ability to
access contiguous data larger than 80 bytes. There are
also new instructions to support the FSRs. See
Section 3.6 “Indirect Addressing” for more details.
2.4 Instruction Set

There are 49 instructions for the enhanced mid-range
CPU to support the features of the CPU. See Section
34.0 “Instruction Set Summary” for more details.

PIC16(L)F1615/9
3.0 MEMORY ORGANIZATION 3.2 High-Endurance Flash
This device has a 128-byte section of high-endurance
These devices contain the following types of memory:
Program Flash Memory (PFM) in lieu of data
• Program Memory EEPROM. This area is especially well suited for
- Configuration Words nonvolatile data storage that is expected to be
- Device ID updated frequently over the life of the end product.
- User ID See Section 10.2 “Flash Program Memory
- Flash Program Memory Overview” for more information on writing data to
• Data Memory PFM. See Section 3.2.1.2 “Indirect Read with FSR”
- Core Registers for more information about using the FSR registers to
- Special Function Registers read byte data stored in PFM.
- General Purpose RAM
- Common RAM
The following features are associated with access and
control of program memory and data memory:
• PCL and PCLATH
• Stack
• Indirect Addressing
3.1 Program Memory Organization

The enhanced mid-range core has a 15-bit program
counter capable of addressing a 32K x 14 program
memory space. Table 3-1 shows the memory sizes
implemented. Accessing a location above these
boundaries will cause a wrap-around within the
implemented memory space. The Reset vector is at
0000h and the interrupt vector is at 0004h (See
Figure 3-1).
High-Endurance Flash
Program Memory Space Last Program Memory
Device Memory Address
(Words) Address
Range(1)
PIC16(L)F1615/9 8,192 1FFFh 1F80h-1FFFh
Note 1: High-endurance Flash applies to low byte of each address in the range.

PIC16(L)F1615/9
FIGURE 3-1: PROGRAM MEMORY MAP 3.2.1 READING PROGRAM MEMORY AS
AND STACK FOR DATA
PIC16(L)F1615/9 There are two methods of accessing constants in
program memory. The first method is to use tables of
Rev. 10-000040B
7/30/2013
RETLW instructions. The second method is to set an
FSR to point to the program memory.
PC<14:0>
3.2.1.1 RETLW Instruction
CALL, CALLW
RETURN, RETLW
15 The RETLW instruction can be used to provide access
Interrupt, RETFIE to tables of constants. The recommended way to create
Stack Level 0 such a table is shown in Example 3-1.
Stack Level 1
EXAMPLE 3-1: RETLW INSTRUCTION
constants
BRW ;Add Index in W to
Stack Level 15 ;program counter to
;select data
0000h RETLW DATA0 ;Index0 data
Reset Vector
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3
Interrupt Vector 0004h
0005h
Page 0 my_function
07FFh ;… LOTS OF CODE…
0800h MOVLW DATA_INDEX
Page 1 call constants
On-chip
0FFFh ;… THE CONSTANT IS IN W
Program
Memory 1000h
Page 2 The BRW instruction makes this type of table very
17FFh simple to implement. If your code must remain portable
1800h with previous generations of microcontrollers, then the
Page 3
1FFFh BRW instruction is not available, so the older table read
2000h method must be used.
Rollover to Page 0
Rollover to Page 3 7FFFh

PIC16(L)F1615/9
3.2.1.2 Indirect Read with FSR
The program memory can be accessed as data by set-
ting bit 7 of the FSRxH register and reading the match-
ing INDFx register. The MOVIW instruction will place the
lower eight bits of the addressed word in the W register.
Writes to the program memory cannot be performed via
the INDF registers. Instructions that access the pro-
gram memory via the FSR require one extra instruction
cycle to complete. Example 3-2 demonstrates access-
ing the program memory via an FSR.
The HIGH operator will set bit<7> if a label points to a
location in program memory.
EXAMPLE 3-2: ACCESSING PROGRAM

MEMORY VIA FSR
constants
DW DATA0 ;First constant
DW DATA1 ;Second constant
DW DATA2
DW DATA3
my_function
;… LOTS OF CODE…
MOVLW DATA_INDEX
ADDLW LOW constants
MOVWF FSR1L
MOVLW HIGH constants;MSb sets
automatically
MOVWF FSR1H
BTFSC STATUS, C ;carry from ADDLW?
INCF FSR1h, f ;yes
MOVIW 0[FSR1]
;THE PROGRAM MEMORY IS IN W

PIC16(L)F1615/9
3.3 Data Memory Organization file registers) or indirectly via the two File Select
Registers (FSR). See Section 3.6 “Indirect
The data memory is partitioned in 32 memory banks Addressing” for more information.
with 128 bytes in a bank. Each bank consists of
(Figure 3-2): Data memory uses a 12-bit address. The upper five bits
of the address define the Bank address and the lower
• 12 core registers seven bits select the registers/RAM in that bank.
• 20 Special Function Registers (SFR)
• Up to 80 bytes of General Purpose RAM (GPR) 3.3.1 CORE REGISTERS
• 16 bytes of common RAM The core registers contain the registers that directly
The active bank is selected by writing the bank number affect the basic operation. The core registers occupy
into the Bank Select Register (BSR). Unimplemented the first 12 addresses of every data memory bank
memory will read as ‘0’. All data memory can be (addresses x00h/x80h through x0Bh/x8Bh). These
accessed either directly (via instructions that use the registers are listed below in Table 3-1. For detailed
TABLE 3-1: CORE REGISTERS
Addresses BANKx
x00h or x80h INDF0
x01h or x81h INDF1
x02h or x82h PCL
x03h or x83h STATUS
x04h or x84h FSR0L
x05h or x85h FSR0H
x06h or x86h FSR1L
x07h or x87h FSR1H
x08h or x88h BSR
x09h or x89h WREG
x0Ah or x8Ah PCLATH
x0Bh or x8Bh INTCON

PIC16(L)F1615/9
3.3.1.1 STATUS Register For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
The STATUS register, shown in Register 3-1, contains:
as ‘000u u1uu’ (where u = unchanged).
• the arithmetic status of the ALU
It is recommended, therefore, that only BCF, BSF,
• the Reset status SWAPF and MOVWF instructions are used to alter the
The STATUS register can be the destination for any STATUS register, because these instructions do not
instruction, like any other register. If the STATUS affect any Status bits. For other instructions not
register is the destination for an instruction that affects affecting any Status bits (Refer to Section
the Z, DC or C bits, then the write to these three bits is 34.0 “Instruction Set Summary”).
disabled. These bits are set or cleared according to the
Note 1: The C and DC bits operate as Borrow
device logic. Furthermore, the TO and PD bits are not
and Digit Borrow out bits, respectively, in
writable. Therefore, the result of an instruction with the
subtraction.
STATUS register as destination may be different than
intended.
REGISTER 3-1: STATUS: STATUS REGISTER
U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u
(1)
— — — TO PD Z DC C(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7-5 Unimplemented: Read as ‘0’

bit 4 TO: Time-Out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-Down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.

PIC16(L)F1615/9
3.3.2 SPECIAL FUNCTION REGISTER FIGURE 3-2: BANKED MEMORY
The Special Function Registers are registers used by PARTITIONING
the application to control the desired operation of
peripheral functions in the device. The Special Function
Rev. 10-000041A
7/30/2013
Registers occupy the 20 bytes after the core registers of

every data memory bank (addresses x0Ch/x8Ch 7-bit Bank Offset Memory Region
through x1Fh/x9Fh). The registers associated with the
operation of the peripherals are described in the appro- 00h
priate peripheral chapter of this data sheet. Core Registers
(12 bytes)
3.3.3 GENERAL PURPOSE RAM 0Bh
0Ch
There are up to 80 bytes of GPR in each data memory
Special Function Registers
bank. The Special Function Registers occupy the 20 (20 bytes maximum)
bytes after the core registers of every data memory 1Fh
bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).
20h
3.3.3.1 Linear Access to GPR
The general purpose RAM can be accessed in a non-
banked method via the FSRs. This can simplify access
to large memory structures. See Section 3.6.2 “Linear
Data Memory” for more information.
General Purpose RAM
3.3.4 COMMON RAM (80 bytes maximum)
There are 16 bytes of common RAM accessible from all
banks.
3.3.5 DEVICE MEMORY MAPS

The memory maps are shown in Table 3-2 through
Table 3-12. 6Fh
70h
Common RAM
(16 bytes)
7Fh

TABLE 3-2: PIC16(L)F1615 MEMORY MAP, BANK 0-7
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h 080h 100h 180h 200h 280h 300h 380h
Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers
(Table 3-1) (Table 3-1) (Table 3-1) (Table 3-1) (Table 3-1) (Table 3-1) (Table 3-1) (Table 3-1)
00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA
00Dh — 08Dh — 10Dh — 18Dh — 20Dh — 28Dh — 30Dh — 38Dh —
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh WPUC 28Eh ODCONC 30Eh SLRCONC 38Eh INLVLC
00Fh — 08Fh — 10Fh — 18Fh — 20Fh — 28Fh — 30Fh — 38Fh —
010h PIR1 090h PIE1 110h — 190h — 210h — 290h — 310h — 390h —
011h PIR2 091h PIE2 111h CM1CON0 191h PMADRL 211h SSP1BUF 291h CCPR1L 311h — 391h IOCAP
012h PIR3 092h PIE3 112h CM1CON1 192h PMADRH 212h SSP1ADD 292h CCPR1H 312h — 392h IOCAN
013h PIR4 093h PIE4 113h CM2CON0 193h PMDATL 213h SSP1MSK 293h CCP1CON 313h — 393h IOCAF
014h PIR5 094h PIE5 114h CM2CON1 194h PMDATH 214h SSP1STAT 294h CCP1CAP 314h — 394h —
015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h SSP1CON 295h — 315h — 395h —
016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSP1CON2 296h — 316h — 396h —
017h TMR1H 097h — 117h FVRCON 197h VREGCON 217h SSP1CON3 297h — 317h — 397h IOCCP
018h T1CON 098h OSCTUNE 118h DAC1CON0 198h — 218h — 298h CCPR2L 318h — 398h IOCCN
019h T1GCON 099h OSCCON 119h DAC1CON1 199h RC1REG 219h — 299h CCPR2H 319h — 399h IOCCF
01Ah TMR2 09Ah OSCSTAT 11Ah — 19Ah TX1REG 21Ah — 29Ah CCP2CON 31Ah — 39Ah —
01Bh PR2 09Bh ADRESL 11Bh — 19Bh SP1BRGL 21Bh — 29Bh CCP2CAP 31Bh — 39Bh —
01Ch T2CON 09Ch ADRESH 11Ch ZCD1CON 19Ch SP1BRGH 21Ch — 29Ch — 31Ch — 39Ch —
01Dh T2HLT 09Dh ADCON0 11Dh — 19Dh RC1STA 21Dh — 29Dh — 31Dh — 39Dh —
01Eh T2CLKCON 09Eh ADCON1 11Eh — 19Eh TX1STA 21Eh — 29Eh CCPTMRS 31Eh — 39Eh —
01Fh T2RST 09Fh ADCON2 11Fh — 19Fh BAUD1CON 21Fh — 29Fh — 31Fh — 39Fh —
020h 0A0h 120h 1A0h 220h 2A0h 320h 3A0h
General General General General General General General

Purpose Purpose Purpose Purpose Purpose Purpose Purpose
General Register Register Register Register Register Register Register
Purpose 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes
Register
PIC16(L)F1615/9
96 Bytes 0EFh 36Fh 3EFh
16Fh 1EFh 26Fh 2EFh
0F0h 170h 1F0h 270h 2F0h 370h 3F0h
Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM
(Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses
70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh)
07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh
Legend: = Unimplemented data memory locations, read as ‘0’.

DS40001770D-page 27
TABLE 3-3: PIC16(L)F1619 MEMORY MAP, BANK 0-7

000h 080h 100h 180h 200h 280h 300h 380h
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA
00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh ODCONB 30Dh SLRCONB 38Dh INLVLB
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh WPUC 28Eh ODCONC 30Eh SLRCONC 38Eh INLVLC
00Fh — 08Fh — 10Fh — 18Fh — 20Fh — 28Fh — 30Fh — 38Fh —
010h PIR1 090h PIE1 110h — 190h — 210h — 290h — 310h — 390h —
011h PIR2 091h PIE2 111h CM1CON0 191h PMADRL 211h SSP1BUF 291h CCP1RL 311h — 391h IOCAP
012h PIR3 092h PIE3 112h CM1CON1 192h PMADRH 212h SSP1ADD 292h CCP1RH 312h — 392h IOCAN
013h PIR4 093h PIE4 113h CM2CON0 193h PMDATL 213h SSP1MSK 293h CCP1CON 313h — 393h IOCAF
014h PIR5 094h PIE5 114h CM2CON1 194h PMDATH 214h SSP1STAT 294h CCP1CAP 314h — 394h IOCBP
015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h SSP1CON 295h — 315h — 395h IOCBN
016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSP1CON2 296h — 316h — 396h IOCBF
017h TMR1H 097h — 117h FVRCON 197h VREGCON 217h SSP1CON3 297h — 317h — 397h IOCCP
018h T1CON 098h OSCTUNE 118h DAC1CON0 198h — 218h — 298h CCP2RL 318h — 398h IOCCN
019h T1GCON 099h OSCCON 119h DAC1CON1 199h RC1REG 219h — 299h CCP2RH 319h — 399h IOCCF
01Ah TMR2 09Ah OSCSTAT 11Ah — 19Ah TX1REG 21Ah — 29Ah CCP2CON 31Ah — 39Ah —
01Bh PR2 09Bh ADRESL 11Bh — 19Bh SP1BRGL 21Bh — 29Bh CCP2CAP 31Bh — 39Bh —
01Ch T2CON 09Ch ADRESH 11Ch ZCD1CON 19Ch SP1BRGH 21Ch — 29Ch — 31Ch — 39Ch —
01Dh T2HLT 09Dh ADCON0 11Dh — 19Dh RC1STA 21Dh — 29Dh — 31Dh — 39Dh —
01Eh T2CLKCON 09Eh ADCON1 11Eh — 19Eh TX1STA 21Eh — 29Eh CCPTMRS 31Eh — 39Eh —
01Fh T2RST 09Fh ADCON2 11Fh — 19Fh BAUD1CON 21Fh — 29Fh — 31Fh — 39Fh —
020h 0A0h 120h 1A0h 220h 2A0h 320h 3A0h
General General General General General General General

Purpose Purpose Purpose Purpose Purpose Purpose Purpose
General Register Register Register Register Register Register Register
Purpose 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes
Register
96 Bytes
PIC16(L)F1615/9
0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh
0F0h Common RAM 170h Common RAM 1F0h Common RAM 270h Common RAM 2F0h Common RAM 370h Common RAM 3F0h Common RAM
(Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses
07Fh 0FFh 70h – 7Fh) 17Fh 70h – 7Fh) 1FFh 70h – 7Fh) 27Fh 70h – 7Fh) 2FFh 70h – 7Fh) 37Fh 70h – 7Fh) 3FFh 70h – 7Fh)

DS40001770D-page 28
TABLE 3-4: PIC16(L)F1615/9 MEMORY MAP, BANK 8-15

400h 480h 500h 580h 600h 680h 700h 780h
40Ch — 48Ch — 50Ch — 58Ch PID1SETL 60Ch PID1Z2L 68Ch — 70Ch — 78Ch —
40Dh — 48Dh — 50Dh — 58Dh PID1SETH 60Dh PID1Z2H 68Dh — 70Dh — 78Dh —
40Eh HDRVENC 48Eh — 50Eh — 58Eh PID1INL 60Eh PID1Z2U 68Eh — 70Eh — 78Eh —
40Fh — 48Fh — 50Fh — 58Fh PID1INH 60Fh PID1ACCLL 68Fh — 70Fh — 78Fh —
410h — 490h — 510h — 590h PID1K1L 610h PID1ACCLH 690h — 710h — 790h —
411h — 491h — 511h — 591h PID1K1H 611h PID1ACCHL 691h CWG1DBR 711h WDTCON0 791h CRCDATL
412h — 492h — 512h — 592h PID1K2L 612h PID1ACCHH 692h CWG1DBF 712h WDTCON1 792h CRCDATH
413h TMR4 493h TMR3L 513h — 593h PID1K2H 613h PID1ACCUL 693h CWG1AS0 713h WDTPSL 793h CRCACCL
414h PR4 494h TMR3H 514h — 594h PID1K3L 614h PID1CON 694h CWG1AS1 714h WDTPSH 794h CRCACCH
415h T4CON 495h T3CON 515h — 595h PID1K3H 615h — 695h CWG1OCON0 715h WDTTMR 795h CRCSHIFTL
416h T4HLT 496h T3GCON 516h — 596h PID1OUTLL 616h — 696h CWG1CON0 716h — 796h CRCSHIFTH
417h T4CLKCON 497h — 517h — 597h PID1OUTLH 617h PWM3DCL 697h CWG1CON1 717h — 797h CRCXORL
418h T4RST 498h — 518h — 598h PID1OUTHL 618h PWM3DCH 698h — 718h SCANLADRL 798h CRCXORH
419h — 499h — 519h — 599h PID1OUTHH 619h PWM3CON 699h CWG1CLKCON 719h SCANLADRH 799h CRCCON0
41Ah TMR6 49Ah TMR5L 51Ah — 59Ah PID1OUTUL 61Ah PWM4DCL 69Ah CWG1ISM 71Ah SCANHADRL 79Ah CRCCON1
41Bh PR6 49Bh TMR5H 51Bh — 59Bh PID1Z1L 61Bh PWM4DCH 69Bh — 71Bh SCANHADRH 79Bh —
41Ch T6CON 49Ch T5CON 51Ch — 59Ch PID1Z1H 61Ch PWM4CON 69Ch — 71Ch SCANCON0 79Ch —
41Dh T6HLT 49Dh T5GCON 51Dh — 59Dh PID1Z1U 61Dh — 69Dh — 71Dh SCANTRIG 79Dh —
41Eh T6CLKCON 49Eh — 51Eh — 59Eh — 61Eh — 69Eh — 71Eh — 79Eh —
41Fh T6RST 49Fh — 51Fh — 59Fh — 61Fh — 69Fh — 71Fh — 79Fh —
420h 4A0h 520h 5A0h 620h General Purpose 6A0h 720h 7A0h
Register
General General General General
64Fh 48 Bytes
Purpose Purpose Purpose Purpose Unimplemented Unimplemented Unimplemented
Register Register Register Register 640h Read as ‘0’ Read as ‘0’ Read as ‘0’
80 Bytes 80 Bytes 80 Bytes 80 Bytes Unimplemented
Read as ‘0’
46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh
470h 4F0h 570h 5F0h 670h 6F0h 770h 7F0h
Accesses Accesses Accesses Accesses Accesses Accesses Accesses Accesses
70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh
PIC16(L)F1615/9
47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh

DS40001770D-page 29

800h 880h 900h 980h A00h A80h B00h B80h
(Table 3-1 ) (Table 3-1) (Table 3-1) (Table 3-1) (Table 3-1) (Table 3-1) (Table 3-1) (Table 3-1)
80Bh 88Bh 90Bh 98Bh A0Bh A8Bh B0Bh B8Bh
80Ch AT1RESL 88Ch AT1CLK 90Ch 98Ch A0Ch A8Ch B0Ch B8Ch
80Dh AT1RESH 88Dh AT1SIG
80Eh AT1MISSL 88Eh AT1CSEL1
80Fh AT1MISSH 88Fh AT1CC1L
810h AT1PERL 890h AT1CC1H
811h AT1PERH 891h AT1CCON1
812h AT1PHSL 892h AT1CSEL2
813h AT1PHSH 893h AT1CC2L
814h AT1CON0 894h AT1CC2H
815h AT1CON1 895h AT1CCON2 Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented
816h AT1IR0 896h AT1CSEL2 Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’
817h AT1IE0 897h AT1CC3L
818h AT1IR1 898h AT1CC3H
819h AT1IE1 899h AT1CCON3
81Ah AT1STPTL 89Ah
81Bh AT1STPTH
81Ch AT1ERRL
81Dh AT1ERRH
86Fh 8EFh 96Fh 9EFh A6Fh AEFh B6Fh BEFh

870h 8F0h 970h 9F0h A70h AF0h B70h BF0h
87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh
PIC16(L)F1615/9
DS40001770D-page 30

C00h C80h D00h D80h E00h E80h F00h F80h
C0Bh C8Bh D0Bh D8Bh E0Bh E8Bh F0Bh F8Bh
C0Ch — C8Ch — D0Ch — D8Ch E0Ch E8Ch F0Ch F8Ch
C0Dh — C8Dh — D0Dh — D8Dh E0Dh E8Dh F0Dh F8Dh
C0Eh — C8Eh — D0Eh — D8Eh E0Eh E8Eh F0Eh F8Eh
C0Fh — C8Fh — D0Fh — D8Fh E0Fh E8Fh F0Fh F8Fh
C10h — C90h — D10h — D90h E10h E90h F10h F90h
C17h — C97h — D17h — D97h E17h E97h See Table 3-9 F17h F97h
See Table 3-7 for See Table 3-8 for See Table 3-12 See Table 3-12
C18h — C98h — D18h — D98h register mapping E18h register mapping E98h and Table 3-10 F18h for register map- F98h for register map-
C19h — C99h — D19h — D99h E19h E99h for register F19h F99h
details details ping details ping details
mapping details
C1Ah — C9Ah — D1Ah — D9Ah E1Ah E9Ah F1Ah F9Ah
C1Bh — C9Bh — D1Bh — D9Bh E1Bh E9Bh F1Bh F9Bh
C1Ch — C9Ch — D1Ch — D9Ch E1Ch E9Ch F1Ch F9Ch
C1Dh — C9Dh — D1Dh — D9Dh E1Dh E9Dh F1Dh F9Dh
C1Eh — C9Eh — D1Eh — D9Eh E1Eh E9Eh F1Eh F9Eh
C1Fh — C9Fh — D1Fh — D9Fh E1Fh E9Fh F1Fh F9Fh
C20h CA0h D20h DA0h E20h EA0h F20h FA0h
Unimplemented Unimplemented Unimplemented

Read as ‘0’ Read as ‘0’ Read as ‘0’
C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFh
PIC16(L)F1615/9
C70h CF0h D70h DF0h E70h EF0h F70h FF0h
CFFh CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh

DS40001770D-page 31
PIC16(L)F1615/9
TABLE 3-7: PIC16(L)F1615/9 MEMORY TABLE 3-8: PIC16(L)F1615/9 MEMORY
MAP, BANK 27 MAP, BANK 28
Bank 27
Bank 28
D8Ch SMT1TMRL
E0Ch ---
D8Dh SMT1TMRH
E0Dh ---
D8Eh SMT1TMRU ---
E0Eh
D8Fh SMT1CPRL
E0Fh PPSLOCK
D90h SMT1CPRH
E10h INTPPS
D91h SMT1CPRU
E11h T0CKIPPS
D92h SMT1CPWL
SMT1CPWH E12h T1CKIPPS
D93h
SMT1CPWU E13h T1GPPS
D94h
D95h SMT1PRL E14h CCP1PPS
D96h SMT1PRH E15h CCP2PPS
D97h SMT1PRU E16h ATINPPS
D98h SMT1CON0 E17h CWGINPPS
D99h SMT1CON1 E18h T2PPS
D9Ah SMT1STAT E19h T3CKIPPS
D9Bh SMT1CLK E1Ah T3GPPS
D9Ch SMT1SIG
E1Bh T4PPS
D9Dh SMT1WIN
E1Ch T5CKIPPS
D9Eh SMT2TMRL
E1Dh T5GPPS
D9Fh SMT2TMRH
E1Eh T6PPS
DA0h SMT2TMRU
SMT2CPRL E1Fh ATCC1PPS
DA1h
DA2h SMT2CPRH E20h SSPCLKPPS
DA3h SMT2CPRU E21h SSPDATPPS
DA4h SMT2CPWL E22h SSPSSPPS
DA5h SMT2CPWH E23h ATCC2PPS
DA6h SMT2CPWU E24h RXPPS
DA7h SMT2PRL E25h CKPPS
DA8h SMT2PRH SMT1SIGPPS
E26h
DA9h SMT2PRU SMT1WINPPS
E27h
DAAh SMT2CON0
E28h CLCIN0PPS
DABh SMT2CON1
E29h CLCIN1PPS
DACh SMT2STAT
E2Ah CLCIN2PPS
DADh SMT2CLK
SMT2SIG E2Bh CLCIN3PPS
DAEh
DAFh SMT2WIN E2Ch SMT2SIGPPS
DB0h E2Dh SMT2WINPPS
— E2Eh ATCC3PPS
DEFh E2Fh
—
Legend: = Unimplemented data memory locations, E6Fh
read as ‘0’.
Legend: = Unimplemented data memory locations,

read as ‘0’.

PIC16(L)F1615/9
TABLE 3-9: PIC16(L)F1615 MEMORY MAP, TABLE 3-10: PIC16(L)F1619 MEMORY MAP,
BANK 29 BANK 29
Bank 29 Bank 29
E8Ch --- E8Ch ---
E8Dh --- E8Dh ---
E8Eh --- E8Eh ---
E8Fh --- E8Fh ---
E90h RA0PPS E90h RA0PPS
E93h — E93h —
E96h --- E96h ---
E97h --- E97h ---
E98h --- E98h ---
E99h --- E99h ---
E9Ah --- E9Ah ---
E9Bh --- E9Bh ---
E9Ch --- E9Ch RB4PPS
E9Dh --- E9Dh RB5PPS
E9Eh --- E9Eh RB6PPS
E9Fh --- E9Fh RB7PPS
EA0h RC0PPS EA0h RC0PPS
EA6h
EA6h RC6PPS
—
EA7h RC7PPS
EEFh EA8h
—
EEFh

read as ‘0’.
read as ‘0’.

PIC16(L)F1615/9
TABLE 3-11: PIC16(L)F1615/9 MEMORY TABLE 3-12: PIC16(L)F1615/9 MEMORY
MAP, BANK 30 MAP, BANK 31
Bank 30 Bank 31
F0Ch --- F8Ch
F0Dh ---
Unimplemented
F0Eh --- Read as ‘0’
F0Fh CLCDATA
F10h CLC1CON FE3h
F11h CLC1POL FE4h STATUS_SHAD
CLC1SEL0 FE5h WREG_SHAD
F12h
CLC1SEL1 FE6h BSR_SHAD
F13h
FE7h PCLATH_SHAD
F14h CLC1SEL2
FE8h FSR0L_SHAD
F15h CLC1SEL3
FE9h FSR0H_SHAD
F16h CLC1GLS0
FEAh FSR1L_SHAD
F17h CLC1GLS1 FSR1H_SHAD
FEBh
F18h CLC1GLS2 —
FECh
F19h CLC1GLS3 FEDh STKPTR
F1Ah CLC2CON FEEh TOSL
F1Bh CLC2POL FEFh TOSH
F1Ch CLC2SEL0
F1Dh CLC2SEL1
F1Eh CLC2SEL2 Legend: = Unimplemented data memory locations,
read as ‘0’.
F1Fh CLC2SEL3
F20h CLC2GLS0
F21h CLC2GLS1
F22h CLC2GLS2
F23h CLC2GLS3
F24h CLC3CON
F25h CLC3POL
F26h CLC3SEL0
F27h CLC3SEL1
F28h CLC3SEL2
F29h CLC3SEL3
F2Ah CLC3GLS0
F2Bh CLC3GLS1
F2Ch CLC3GLS2
F2Dh CLC3GLS3
F2Eh CLC4CON
F2Fh CLC4POL
F30h CLC4SEL0
F31h CLC4SEL1
F32h CLC4SEL2
F33h CLC4SEL3
F34h CLC4GLS0
F35h CLC4GLS1
F36h CLC4GLS2
F37h CLC4GLS3
F38h
—
F6Fh

read as ‘0’.

PIC16(L)F1615/9
3.3.6 CORE FUNCTION REGISTERS
SUMMARY
The Core Function registers listed in Table 3-13 can
be addressed from any Bank.
TABLE 3-13: CORE FUNCTION REGISTERS SUMMARY

Value on Value on all
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Bank 0-31
x00h or Addressing this location uses contents of FSR0H/FSR0L to address data memory
INDF0 xxxx xxxx uuuu uuuu
x80h (not a physical register)
x01h or Addressing this location uses contents of FSR1H/FSR1L to address data memory
INDF1 xxxx xxxx uuuu uuuu
x81h (not a physical register)
x02h or
PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
x82h
x03h or
STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
x83h
x04h or
FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
x84h
x05h or
FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
x85h
x06h or
FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
x86h
x07h or
FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
x87h
x08h or
BSR — — — BSR<4:0> ---0 0000 ---0 0000
x88h
x09h or
WREG Working Register 0000 0000 uuuu uuuu
x89h
x0Ah or
PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
x8Ah
x0Bh or
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
x8Bh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.

TABLE 3-14: SPECIAL FUNCTION REGISTER SUMMARY

Bank 0
00Ch PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --xx xxxx
(4)
00Dh PORTB RB7 RB6 RB5 RB4 — — — — xxxx ---- xxxx ----
00Eh PORTC RC7(4) RC6(4) RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx xxxx xxxx
00Fh — Unimplemented — —
010h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
011h PIR2 OSFIF C2IF C1IF — BCL1IF TMR6IF TMR4IF CCP2IF -00- 0000 -00- 0000
012h PIR3 — — CWGIF ZCDIF CLC4IF CLC3IF CLC2IF CLC1IF --00 0000 --00 0000
013h PIR4 SCANIF CRCIF SMT2PWAIF SMT2PRAIF SMT2IF SMT1PWAIF SMT1PRAIF SMT1IF 0000 0000 0000 0000
014h PIR5 TMR3GIF TMR3IF TMR5GIF TMR5IF — AT1IF PID1EIF PID1DIF 0000 -000 0000 -000
015h TMR0 Holding Register for the 8-bit Timer0 Count xxxx xxxx uuuu uuuu
016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Count xxxx xxxx uuuu uuuu
017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Count xxxx xxxx uuuu uuuu
018h T1CON TMR1CS<1:0> T1CKPS<1:0> — T1SYNC — TMR1ON 0000 -0-0 uuuu -u-u
019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> 0000 0x00 uuuu uxuu
DONE
01Ah TMR2 Timer2 Module Register 0000 0000 0000 0000
01Bh PR2 Timer2 Period Register 1111 1111 1111 1111
01Ch T2CON ON CKPS<2:0> OUTPS<3:0> 0000 0000 0000 0000
01Dh T2HLT PSYNC CKPOL CKSYNC MODE<4:0> 0000 0000 0000 0000
01Eh T2CLKCON — — — — CS<3:0> ---- 0000 ---- 0000
PIC16(L)F1615/9
01Fh T2RST — — — — RSEL<3:0> ---- 0000 ---- 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’.
Note 1: PIC16F1615/9 only.
2: Unimplemented, read as ‘1’.
DS40001770D-page 36
TABLE 3-14: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Bank 1
08Ch TRISA — — TRISA5 TRISA4 —(2) TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
(4)
08Dh TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 1111 ----
08Eh TRISC TRISC7(4) TRISC6(4) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
090h — Unimplemented — —
090h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
091h PIE2 OSFIE C2IE C1IE — BCL1IE TMR6IE TMR4IE CCP2IE -00- 0000 -00- 0000
092h PIE3 — — CWGIE ZCDIE CLC4IE CLC3IE CLC2IE CLC1IE --00 0000 --00 0000
093h PIE4 SCANIE CRCIE SMT2PWAIE SMT2PRAIE SMT2IE SMT1PWAIE SMT1PRAIE SMT1IE 0000 0000 0000 0000
094h PIE5 TMR3GIE TMR3IE TMR5GIE TMR5IE — AT1IE PID1EIE PID1DIE 0000 -000 0000 -000
095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 1111 1111 1111 1111
096h PCON STKOVF STKUNF WDTWV RWDT RMCLR RI POR BOR 00-1 11qq qq-q qquu
— —
098h OSCTUNE TUN<5:0> --00 0000 --00 0000
099h OSCCON SPLLEN IRCF<3:0> — SCS<1:0> 0011 1-00 0011 1-00
09Ah OSCSTAT — PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS -000 0000 -qqq qqqq
09Bh ADRESL ADC Result Register Low xxxx xxxx uuuu uuuu
09Ch ADRESH ADC Result Register High xxxx xxxx uuuu uuuu
09Dh ADCON0 — CHS<4:0> GO/DONE ADON -000 0000 -000 0000
09Eh ADCON1 ADFM ADCS<2:0> — — ADPREF<1:0> 0000 --00 0000 --00
09Fh ADCON2 TRIGSEL<4:0> — — —
PIC16(L)F1615/9
0000 0--- 0000 0---
DS40001770D-page 37

Bank 2
10Ch LATA — — LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 --xx xxxx --uu uuuu
10Dh LATB(4) LATB7 LATB6 LATB5 LATB4 — — — — xxxx ---- uuuu ----
10Eh LATC LATC7(4) LATC6(4) LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx uuuu uuuu
111h CM1CON0 C1ON C1OUT — C1POL — C1SP C1HYS C1SYNC 00-0 -100 00-0 -100
112h CM1CON1 C1INTP C1INTN C1PCH<1:0> — C1NCH<2:0> 0000 -000 0000 -000
113h CM2CON0(4) C2ON C2OUT — C2POL — C2SP C2HYS C2SYNC 00-0 -100 00-0 -100
(4)
114h CM2CON1 C2INTP C2INTN C2PCH<1:0> — C2NCH<2:0> 0000 -000 0000 -000
115h CMOUT — — — — — — MC2OUT MC1OUT ---- --00 ---- --00
116h BORCON SBOREN BORFS — — — — — BORRDY 10-- ---q uu-- ---u
117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 0q00 0000 0q00 0000
118h DAC1CON0 DAC1EN — DAC1OE1 — DAC1PSS<1:0> — — 0-0- 00-- 0-0- 00--
119h DAC1CON1 DAC1R<7:0> 0000 0000 0000 0000
11Ah — Unimplemented — —
11Bh — Unimplemented — —
11Ch ZCD1CON ZCD1EN — ZCD1OUT ZCD1POL — — ZCD1INTP ZCD1INTN 0-00 --00 0-00 --00
11Dh — Unimplemented — —
11Eh — Unimplemented — —
PIC16(L)F1615/9
DS40001770D-page 38

Bank 3
18Ch ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 ---1 -111 ---1 -111
18Dh ANSELB(4) — — ANSB5 ANSB4 — — — — --11 ---- --11 ----
18Eh ANSELC ANSC7(4) ANSC6(4) — — ANSC3 ANSC2 ANSC1 ANSC0 11-- 1111 11-- 1111
191h PMADRL Flash Program Memory Address Register Low Byte 0000 0000 0000 0000
192h PMADRH —(2) Flash Program Memory Address Register High Byte 1000 0000 1000 0000
193h PMDATL Flash Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu
194h PMDATH — — Flash Program Memory Read Data Register High Byte --xx xxxx --uu uuuu
195h PMCON1 —(2) CFGS LWLO FREE WRERR WREN WR RD 1000 x000 1000 q000
196h PMCON2 Flash Program Memory Control Register 2 0000 0000 0000 0000
197h VREGCON(1) — — — — — — VREGPM Reserved ---- --01 ---- --01
199h RC1REG EUSART Receive Data Register 0000 0000 0000 0000
19Ah TX1REG EUSART Transmit Data Register 0000 0000 0000 0000
19Bh SP1BRGL Baud Rate Generator Data Register Low 0000 0000 0000 0000
19Ch SP1BRGH Baud Rate Generator Data Register High 0000 0000 0000 0000
19Dh RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19Eh TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
19Fh BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00
PIC16(L)F1615/9
DS40001770D-page 39

Bank 4
20Ch WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 --11 1111
20Dh WPUB(4) WPUB7 WPUB6 WPUB5 WPUB4 — — — — 1111 ---- 1111 ----
20Eh WPUC WPUC7(4) WPUC6(4) WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 1111 1111 111 1111
211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx xxxx xxxx
212h SSP1ADD ADD<7:0> 0000 0000 0000 0000
213h SSP1MSK MSK<7:0> 1111 1111 1111 1111
214h SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
215h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000
216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000
218h
to — Unimplemented — —
21Fh
PIC16(L)F1615/9
DS40001770D-page 40

Bank 5
28Ch ODCONA — — ODA5 ODA4 — ODA2 ODA1 ODA0 --00 -000 --00 -000
28Dh ODCONB(4) ODB7 ODB6 ODB5 ODB4 — — — — 0000 ---- 0000 ----
28Eh ODCONC ODC7(4) ODC6(4) ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 0000 0000 0000 0000
291h CCP1RL Capture/Compare/PWM 1 Register (LSB) xxxx xxxx uuuu uuuu
292h CCP1RH Capture/Compare/PWM 1 Register (MSB) xxxx xxxx uuuu uuuu
293h CCP1CON EN — OUT FMT MODE<3:0> 0000 0000 0000 0000
294h CCP1CAP — — — — — CTS<2:0> ---- -000 ---- -000
295h
— — Unimplemented — —
297h
298h CCP2RL Capture/Compare/PWM 2 Register (LSB) xxxx xxxx uuuu uuuu
299h CCP2RH Capture/Compare/PWM 2 Register (MSB) xxxx xxxx uuuu uuuu
29Ah CCP2CON EN — OUT FMT MODE<3:0> 0000 0000 0000 0000
29Bh CCP2CAP — — — — — CTS<2:0> ---- -000 ---- -000
29Ch — Unimplemented — —
29Eh CCPTMRS P4TSEL<1:0> P3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> 0000 0000 0000 0000
Bank 6
PIC16(L)F1615/9
30Ch SLRCONA — — SLRA5 SLRA4 — SLRA2 SLRA1 SLRA0 --11 -111 --11 -111
30Dh SLRCONB(4) SLRB7 SLRB6 SLRB5 SLRB4 — — — — 1111 ---- 1111 ----
30Eh SLRCONC SLRC7(4) SLRC6(4) SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 1111 1111 1111 1111
30Fh
— — Unimplemented — —
31Fh
DS40001770D-page 41


Bank 7
38Ch INLVLA — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 --11 1111 --11 1111
38Dh INLVLB(4) INLVLB7 INLVLB6 INLVLB5 INLVLB4 — — — — 1111 ---- 1111 ----
38Eh INLVLC INLVLC7(4) INLVLC6(4) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 1111 1111 1111 1111
391h IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 --00 0000 --00 0000
392h IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 --00 0000 --00 0000
393h IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 --00 0000 --00 0000
(4)
394h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 — — — — 0000 ---- 0000 ----
395h IOCBN(4) IOCBN7 IOCBN6 IOCBN5 IOCBN4 — — — — 0000 ---- 0000 ----
396h IOCBF(4) IOCBF7 IOCBF6 IOCBF5 IOCBF4 — — — — 0000 ---- 0000 ----
397h IOCCP IOCCP7(4) IOCCP6(4) IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 0000 0000 0000 0000
398h IOCCN IOCCN7(4) IOCCN6(4) IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 0000 0000 0000 0000
(4)
399h IOCCF IOCCF7 IOCCF6(4) IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 0000 0000 0000 0000
39Ah
39Fh
PIC16(L)F1615/9
DS40001770D-page 42

Bank 8
40Ch — Unimplemented — —
40Eh HIDRVC — — HIDC5 HIDC4 — — — — --00 ---- --00 ----
40Fh
412h
413h TMR4 Timer4 Module Register 0000 0000 0000 0000
414h PR4 Timer4 Period Register 1111 1111 1111 1111
415h T4CON ON CKPS<2:0> OUTPS<3:0> 0000 0000 0000 0000
416h T4HLT PSYNC CKPOL CKSYNC MODE<4:0> 0000 0000 0000 0000
417h T4CLKCON — — — — CS<3:0> ---- 0000 ---- 0000
418h T4RST — — — — RSEL<3:0> ---- 0000 ---- 0000
41Ah TMR6 Timer6 Module Register 0000 0000 0000 0000
41Bh PR6 Timer6 Period Register 1111 1111 1111 1111
41Ch T6CON ON CKPS<2:0> OUTPS<3:0> 0000 0000 0000 0000
41Dh T6HLT PSYNC CKPOL CKSYNC MODE<4:0> 0000 0000 0000 0000
41Eh T6CLKCON — — — — CS<3:0> ---- 0000 ---- 0000
41Fh T6RST — — — — RSEL<3:0> ---- 0000 ---- 0000
PIC16(L)F1615/9
DS40001770D-page 43

Bank 9
48Ch
492h
493h TMR3L Timer3 Module Register xxxx xxxx xxxx xxxx
494h TMR3H Timer3 Module Register xxxx xxxx xxxx xxxx
495h T3CON TMR3CS<1:0> T3CKPS<1:0> — T3SYNC — TMR3CON xxxx -x-x xxxx -x-x
496h T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/ T3GVAL T3GSS<1:0> xxxx xxxx xxxx xxxx
DONE
497h
499h
49Ah TMR5L Timer5 Module Register xxxx xxxx xxxx xxxx
49Bh TMR5H Timer5 Module Register xxxx xxxx xxxx xxxx
49Ch T5CON TMR5CS<1:0> T5CKPS<1:0> — T5SYNC — TMR5CON xxxx -x-x xxxx -x-x
49Dh T5GCON TMR5GE T5GPOL T5GTM T5GSPM T5GGO/ T5GVAL T5GSS<1:0> xxxx xxxx xxxx xxxx
DONE
Bank 10
50Ch
51Fh
PIC16(L)F1615/9
DS40001770D-page 44

Bank 11
58Ch PID1SELT SET<7:0> xxxx xxxx xxxx xxxx
58Dh PID1SETH SET<15:8> xxxx xxxx xxxx xxxx
58Eh PID1INL IN<7:0> 0000 0000 0000 0000
58Fh PID1INH IN<15:8> 0000 0000 0000 0000
590h PID1K1L K1<7:0> xxxx xxxx xxxx xxxx
591h PID1K1H K1<15:8> xxxx xxxx xxxx xxxx
596h PID1OUTLL OUT<7:0> 0000 0000 0000 0000
597h PID1OUTLH OUT<15:8> 0000 0000 0000 0000
598h PID1OUTHL OUT<23:16> 0000 0000 0000 0000
599h PID1OUTHH OUT<31:24> 0000 0000 0000 0000
59Ah PID1OUTU — — — — OUT<35:32> ---- 0000 ---- 0000
59Bh PID1Z1L Z1<7:0> 0000 0000 0000 0000
59Ch PID1Z1H Z1<15:8> 0000 0000 0000 0000
59Dh PID1Z1U — — — — — — — Z116 ---- ---0 ---- ---0
PIC16(L)F1615/9
DS40001770D-page 45

Bank 12
60Ch PID1Z2L Z2<7:0> 0000 0000 0000 0000
60Dh PID1Z2H Z2<15:8> 0000 0000 0000 0000
60Eh PID1Z2U — — — — — — — Z216 ---- ---0 ---- ---0
60Fh PID1ACCLL ACC<7:0> 0000 0000 0000 0000
610h PID1ACCLH ACC<15:8> 0000 0000 0000 0000
611h PID1ACCHL ACC<23:16> 0000 0000 0000 0000
612h PID1ACCHH ACC<31:24> 0000 0000 0000 0000
613h PID1ACCU — — — — — ACC<34:32> ---- -000 ---- -000
614h PID1CON EN BUSY — — — MODE<2:0> 00-- 0000 00-- 0000
617h PWM3DCL DC<1:0> — — — — — — xx-- ---- xx-- ----
618h PWM3DCH DC<9:2> xxxx xxxx xxxx xxxx
619h PWM3CON EN — OUT POL — — — — 0-x0 ---- 0-x0 ----
61Ah PWM4DCL DC<1:0> — — — — — — xx-- ---- xx-- ----
61Bh PWM4DCH DC<9:2> xxxx xxxx xxxx xxxx
61Ch PWM4CON EN — OUT POL — — — — 0-x0 ---- 0-x0 ----
61Dh
61Fh
PIC16(L)F1615/9
DS40001770D-page 46

Bank 13
68Ch
690h
691h CWG1DBR — — DBR<5:0> --00 0000 --00 0000
692h CWG1DBF — — DBF<5:0> --xx xxxx --xx xxxx
693h CWG1AS0 SHUTDOWN REN LSBD<1:0> LSAC<1:0> — — 0001 01-- 00001 01--
694h CWG1AS1 — TMR6AS TMR4AS TMR2AS — C2AS(4) C1AS INAS -000 -000 -000 -000
695h CWG1OCON0 OVRD OVRC OVRB OVRA STRD STRC STRB STRA 0000 0000 0000 0000
696h CWG1CON0 EN LD — — — MODE<2:0> 00-- -000 00-- -000
697h CWG1CON1 — — IN — POLD POLC POLB POLA --x- 0000 --x- 0000
699h CWG1CLKCON — — — — — — — CS ---- ---0 ---- --0
69Ah CWG1ISM — — — — IS<3:0> ---- 0000 ---- 0000
69Bh
6EFh
PIC16(L)F1615/9
DS40001770D-page 47

Bank 14
70Ch
710h
711h WDTCON0 — — WDTPS<4:0> SEN --qq qqqq --qq qqqq
712h WDTCON1 — WDTCS<2:0> — WINDOW<2:0> -qqq -qqq -qqq -qqq
713h WDTPSL PSCNT<7:0> 0000 0000 0000 0000
714h WDTPSH PSCNT<15:8> 0000 0000 0000 0000
715h WDTTMR WDTTMR<4:0> STATE PSCNT<17:16> 0000 0000 0000 0000
718h SCANLADRL LADR<7:0> 0000 0000 0000 0000
719h SCANLADRH LADR<15:8> 0000 0000 0000 0000
71Ah SCANHADRL HADR<7:0> 1111 1111 1111 1111
71Bh SCANHADRH HADR<15:8> 1111 1111 1111 1111
71Ch SCANCON0 EN SCANGO BUSY INVALID INTM — MODE<1:0> 0000 0-00 0000 0-00
71Dh SCANTRIG TSEL<3:0> ---- 0000 ---- 0000
PIC16(L)F1615/9
DS40001770D-page 48

Banks 15
78Ch
790h
791h CRCDATL DAT<7:0> xxxx xxxx xxxx xxxx
792h CRCDATH DAT<15:8> xxxx xxxx xxxx xxxx
793h CRCACCL ACC<7:0> 0000 0000 0000 0000
794h CRCACCH ACC<15:8> 0000 0000 0000 0000
795h CRCSHIFTL SHIFT<7:0> 0000 0000 0000 0000
796h CRCSHIFTH SHIFT<15:8> 0000 0000 0000 0000
797h CRCXORL XOR<7:1> — xxxx xxx- xxxx xxx-
798h CRCXORH XOR<15:8> xxxx xxxX xxxx xxxX
799h CRCCON0 EN CRCGO BUSY ACCM — — SHIFTM FULL 0000 --00 0000 -00
79Ah CRCCON1 DLEN<3:0> PLEN<3:0> 0000 0000 0000 0000
79Bh
79Fh
PIC16(L)F1615/9
DS40001770D-page 49

Bank 16
80Ch AT1RESL RES<7:0> xxxx xxxx xxxx xxxx
80Dh AT1RESH — — — — — — RES<9:8> ---- --xx ---- --xx
80Eh AT1MISSL MISS<7:0> xxxx xxxx xxxx xxxx
80Fh AT1MISSH MISS<15:8> xxxx xxxx xxxx xxxx
810h AT1PERL PER<7:0> xxxx xxxx xxxx xxxx
811h AT1PERH POV PER<14:8> xxxx xxxx xxxx xxxx
812h AT1PHSL PHS<7:0> xxxx xxxx xxxx xxxx
813h AT1PHSH — — — — — — PHS<9:8> ---- --xx ---- --xx
814h AT1CON0 EN PREC PS<1:0> POL — APMOD MODE 0x00 --00 0x00 -00
815h AT1CON1 — PHP — PRP — MPP ACCS VALID 0000 0000 0000 0000
816h AT1IR0 — — — — — PHSIF MISSIF PERIF ----000 ----000
817h AT1IE0 — — — — — PHSIE MISSIE PERIE ----000 ----000
818h AT1IR1 — — — — — CC3IF CC2IF CC1IF ----000 ----000
819h AT1IE1 — — — — — CC3IE CC2IE CC1IE ----000 ----000
81Ah AT1STPTL STPT<7:0> xxxx xxxx xxxx xxxx
81Bh AT1STPTH — STPT<14:8> -xxx xxxx -xxx xxxx
81Ch AT1ERRL ERR<7:0> xxxx xxxx xxxx xxxx
81Dh AT1ERRH ERR<15:8> xxxx xxxx xxxx xxxx
PIC16(L)F1615/9
DS40001770D-page 50

Bank 17
88Ch AT1CLK — — — — — — — CS0 ---- ---0 ---- ---0
88Dh AT1SIG — — — — — SSEL<2:0> ---- -000 ---- -000
88Eh AT1CSEL1 — — — — — CP1S<2:0> ---- -000 ---- -000
88Fh AT1CC1L CC1<7:0> 0000 0000 0000 0000
890h AT1CC1H — — — — — — CC1<9:8> ---- -000 ---- -000
891h AT1CCON1 CC1EN — — CC1POL CAP1P — — CC1MODE 0--0 0--0 0--0 0--0
892h AT1CSEL2 — — — — — CP2S<2:0> ---- -000 ---- -000
893h AT1CC2L CC2<7:0> 0000 0000 0000 0000
894h AT1CC2H — — — — — — CC2<9:8> ---- -000 ---- -000
896h AT1CSEL3 — — — — — CP3S<2:0> ---- -000 ---- -000
897h AT1CC1L CC3<7:0> 0000 0000 0000 0000
898h AT1CC1H — — — — — — CC3<9:8> ---- -000 ---- -000
89Ah
89Fh
Bank 18-26
x0Ch/ — Unimplemented — —
x8Ch
—
x1Fh/
PIC16(L)F1615/9
x9Fh
DS40001770D-page 51

Banks 27
D80h
D8Bh
D8Ch SMT1TMRL SMT1TMR<7:0> 0000 0000 0000 0000
D8Dh SMT1TMRH SMT1TMR<15:8> 0000 0000 0000 0000
D8Eh SMT1TMRU SMT1TMR<23:16> 0000 0000 0000 0000
D8Fh SMT1CPRL SMT1CPR<7:0> xxxx xxxx xxxx xxxx
D90h SMT1CPRH SMT1CPR<15:8> xxxx xxxx xxxx xxxx
D91h SMT1CPRU SMT1CPR<23:16> xxxx xxxx xxxx xxxx
D92h SMT1CPWL SMT1CPW<7:0> xxxx xxxx xxxx xxxx
D93h SMT1CPWH SMT1CPW<15:8> xxxx xxxx xxxx xxxx
D94h SMT1CPWU SMT1CPW<23:16> xxxx xxxx xxxx xxxx
D95h SMT1PRL SMT1PR<7:0> xxxx xxxx xxxx xxxx
D96h SMT1PRH SMT1PR<15:8> xxxx xxxx xxxx xxxx
D97h SMT1PRU SMT1PR<23:16> xxxx xxxx xxxx xxxx
D98h SMT1CON0 EN — STP WPOL SPOL CPOL SMT1PS<1:0> 0-00 0000 0-00 0000
D99h SMT1CON1 SMT1GO REPEAT — — MODE<3:0> 00-- 0000 00-- 0000
D9Ah SMT1STAT CPRUP CPWUP RST — — TS WS AS 000- -000 000- -000
D9Bh SMT1CLK — — — — — CSEL<2:0> ---- -000 ---- -000
D9Ch SMT1SIG — — — SSEL<4:0> ---0 0000 ---0 0000
D9Dh SMT1WIN — — — WSEL<4:0> ---0 0000 ---0 0000
PIC16(L)F1615/9
D9Eh SMT2TMRL SMT2TMR<7:0> 0000 0000 0000 0000
D9Fh SMT2TMRH SMT2TMR<15:8> 0000 0000 0000 0000
DA0h SMT2TMRU SMT2TMR<23:16> 0000 0000 0000 0000
DA1h SMT2CPRL SMT2CPR<7:0> xxxx xxxx xxxx xxxx
DA2h SMT2CPRH SMT2CPR<15:8> xxxx xxxx xxxx xxxx
DS40001770D-page 52
DA3h SMT2CPRU SMT2CPR<23:16> xxxx xxxx xxxx xxxx

DA4h SMT2CPWL SMT2CPW<7:0> xxxx xxxx xxxx xxxx

Bank 27 (Continued)
DA5h SMT2CPWH SMT2CPW<15:8> xxxx xxxx xxxx xxxx
DA6h SMT2CPWU SMT2CPW<23:16> xxxx xxxx xxxx xxxx
DA7h SMT2PRL SMT2PR<7:0> xxxx xxxx xxxx xxxx
DA8h SMT2PRH SMT2PR<15:8> xxxx xxxx xxxx xxxx
DA9h SMT2PRU SMT2PR<23:16> xxxx xxxx xxxx xxxx
DAAh SMT2CON0 EN — STP WPOL SPOL CPOL SMT2PS<1:0> 0-00 0000 0-00 0000
DABh SMT2CON1 SMT2GO REPEAT — — MODE<3:0> 00-- 0000 00-- 0000
DACh SMT2STAT CPRUP CPWUP RST — — TS WS AS 000- -000 000- -000
DADh SMT2CLK — — — — — CSEL<2:0> ---- -000 ---- -000
DAEh SMT2SIG — — — SSEL<4:0> ---0 0000 ---0 0000
DAFh SMT2WIN — — — WSEL<4:0> ---0 0000 ---0 0000
PIC16(L)F1615/9
DS40001770D-page 53

Banks 28
E0Ch — Unimplemented — —
to
E0Eh
E0Fh PPSLOCK — — — — — — — PPSLOCKED ---- ---0 ---- ---0
E10h INTPPS — — — INTPPS<4:0> ---0 0010 ---0 0010
E11h T0CKIPPS — — — T0CKIPPS<4:0> ---0 0010 ---0 0010
E13h T1GPPS — — — T1GPPS<4:0> ---0 0100 ---0 0100
E14h CCP1PPS — — — CCP1PPS<4:0> ---1 0101 ---1 0101
E15h CCP2PPS — — — CCP2PPS<4:0> ---1 0011 ---1 0011
E16h ATINPPS — — — ATINPPS<4:0> ---1 0101 ---1 0101
E17h CWGINPPS — — — CWGINPPS<4:0> ---0 0010 ---0 0010
E18h T2PPS — — — T2PPS<4:0> ---0 0101 ---0 0101
E1Ah T3GPPS — — — T3GPPS<4:0> ---1 0100 ---1 0100
E1Bh T4PPS — — — T4PPS<4:0> ---1 0001 ---1 0001
E1Ch T5CKIPPS — — — T5CKIPPS<4:0> ---1 0000 ---1 0000
E1Dh T5GPPS — — — T5GPPS<4:0> ---1 0011 ---1 0011
E1Eh T6PPS — — — T6PPS<4:0> ---0 0011 ---0 0011
E1Fh ATCC1PPS — — — ATCC1PPS<4:0> ---1 0011 ---1 0011
E20h SSPCLKPPS(3) — — — SSPCLKPPS<4:0> ---1 0000 ---1 0000
PIC16(L)F1615/9
E20h SSPCLKPPS(4) — — — SSPCLKPPS<4:0> ---1 0000 ---0 1110
(3)
E21h SSPDATPPS — — — SSPDATPPS<4:0> ---1 0001 ---1 0001
E21h SSPDATPPS(4) — — — SSPDATPPS<4:0> ---1 0001 ---0 1100
E22h SSPSSPPS(3) — — — SSPSSPPS<4:0> ---1 0011 ---1 0011
E22h SSPSSPPS(4) — — — SSPSSPPS<4:0> ---1 0110 ---1 0110
DS40001770D-page 54
E23h ATCC2PPS — — — ATCC2PPS<4:0> ---1 0100 ---1 0100


Banks 28 (Continued)
E24h RXPPS(3) — — — RXPPS<4:0> ---1 0101 ---1 0101
E24h RXPPS(4) — — — RXPPS<4:0> ---0 1101 ---0 1101
E25h CKPPS(3) — — — CKPPS<4:0> ---1 0100 ---1 0100
E25h CKPPS(4) — — — CKPPS<4:0> ---0 1111 ---0 1111
E26h SMT1SIGPPS — — — SMT1SIGPPS<4:0> ---0 0100 ---0 0100
E27h SMT1WINPPS — — — SMT1WINPPS<4:0> ---0 0101 ---0 0101
E28h CLCIN0PPS — — — CLCIN0PPS<4:0> ---1 0011 ---1 0011
E29h CLCIN1PPS — — — CLCIN1PPS<4:0> ---1 0100 ---1 0100
E2Ah CLCIN2PPS — — — CLCIN2PPS<4:0> ---1 0001 ---1 0001
E2Bh CLCIN3PPS — — — CLCIN3PPS<4:0> ---0 0101 ---0 0101
E2Ch SMT2SIGPPS — — — SMT2SIGPPS<4:0> ---1 0001 ---1 0001
E2Dh SMT2WINPPS — — — SMT2WINPPS<4:0> ---0 0011 ---0 0011
E2Eh ATCC3PPS — — — ATCC3PPS<4:0> ---1 0101 ---1 0101
E2Fh
E6Fh
PIC16(L)F1615/9
DS40001770D-page 55

Banks 29
E8Ch — Unimplemented — —
to
E8Fh
E90h RA0PPS — — — RA0PPS<4:0> ---0 0000 ---0 0000
E91h RA1PPS — — — RA1PPS<4:0> ---0 0000 ---0 0000
E92h RA2PPS — — — RA2PPS<4:0> ---0 0000 ---0 0000
E93h — Unimplemented — —
E94h RA4PPS — — — RA4PPS<4:0> ---0 0000 ---0 0000
E95h RA5PPS — — — RA5PPS<4:0> ---0 0000 ---0 0000
E96h — Unimplemented — —
to
E9Bh
E9Ch RB4PPS(4) — — — RB4PPS<4:0> ---0 0000 ---0 0000
E9Dh RB5PPS(4) — — — RB5PPS<4:0> ---0 0000 ---0 0000
E9Eh RB6PPS(4) — — — RB6PPS<4:0> ---0 0000 ---0 0000
E9Fh RB7PPS(4) — — — RB7PPS<4:0> ---0 0000 ---0 0000
EA0h RC0PPS — — — RC0PPS<4:0> ---0 0000 ---0 0000
EA1h RC1PPS — — — RC1PPS<4:0> ---0 0000 ---0 0000
EA2h RC2PPS — — — RC2PPS<4:0> ---0 0000 ---0 0000
EA3h RC3PPS — — — RC3PPS<4:0> ---0 0000 ---0 0000
EA4h RC4PPS — — — RC4PPS<4:0> ---0 0000 ---0 0000
EA5h RC5PPS — — — RC5PPS<4:0>
PIC16(L)F1615/9
---0 0000 ---0 0000
EA6h RC6PPS(4) — — — RC6PPS<4:0> ---0 0000 ---0 0000
EA7h RC7PPS(4) — — — RC7PPS<4:0> ---0 0000 ---0 0000
EA8h — Unimplemented — —
to
EEFh
DS40001770D-page 56

Banks 30
F0Ch — Unimplemented — —
to
F0Eh
F0Fh CLCDATA — — — — MLC4OUT MLC3OUT MLC2OUT MLC1OUT ---- 0000 ---- 0000
F10h CLC1CON LC1EN — LC1OUT LC1INTP LC1INTN LC1MODE<2:0> 0-x0 0000 0-x0 0000
F11h CLC1POL LC1POL — — — LC1G4POL LC1G3POL LC1G2POL LC1G1POL x--- xxxx x--- xxxx
F12h CLC1SEL0 — — LC1D1S<5:0> --xx xxxx --xx xxxx
F16h CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N xxxx xxxx xxxx xxxx
F1Ah CLC2CON LC2EN — LC2OUT LC2INTP LC2INTN LC2MODE<2:0> 0-x0 0000 0-x0 0000
F1Bh CLC2POL LC2POL — — — LC2G4POL LC2G3POL LC2G2POL LC2G1POL x--- xxxx x--- xxxx
F1Ch CLC2SEL0 — — LC2D1S<5:0> --xx xxxx --xx xxxx
F1Dh CLC2SEL1 — — LC2D2S<5:0> --xx xxxx --xx xxxx
F1Eh CLC2SEL2 — — LC2D3S<5:0> --xx xxxx --xx xxxx
F1Fh CLC2SEL3 — — LC2D4S<5:0> --xx xxxx --xx xxxx
PIC16(L)F1615/9
DS40001770D-page 57

Banks 30 (Continued)
F24h CLC3CON LC3EN — LC3OUT LC3INTP LC3INTN LC3MODE<2:0> 0-x0 0000 0-x0 0000
F25h CLC3POL LC3POL — — — LC3G4POL LC3G3POL LC3G2POL LC3G1POL x--- xxxx x--- xxxx
F2Ah CLC3GLS0 LC3G1D4T LC3G1D4N LC3G1D3T LC3G1D3N LC3G1D2T LC3G1D2N LC3G1D1T LC3G1D1N xxxx xxxx xxxx xxxx
F2Bh CLC3GLS1 LC3G2D4T LC3G2D4N LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N LC3G2D1T LC3G2D1N xxxx xxxx xxxx xxxx
F2Ch CLC3GLS2 LC3G3D4T LC3G3D4N LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N LC3G3D1T LC3G3D1N xxxx xxxx xxxx xxxx
F2Dh CLC3GLS3 LC3G4D4T LC3G4D4N LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N LC3G4D1T LC3G4D1N xxxx xxxx xxxx xxxx
F2Eh CLC4CON LC4EN — LC4OUT LC4INTP LC4INTN LC4MODE<2:0> 0-x0 0000 0-x0 0000
F2Fh CLC4POL LC4POL — — — LC4G4POL LC4G3POL LC4G2POL LC4G1POL x--- xxxx x--- xxxx
F38h
PIC16(L)F1615/9
F6Fh
DS40001770D-page 58
PIC16(L)F1615/9
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 B
Bank 31
F8Ch — Unimplemented
—
FE3h
FE4h STATUS_ — — — — — Z_SHAD DC_SHAD C_
SHAD
FE5h WREG_ Working Register Shadow
SHAD
FE6h BSR_ — — — Bank Select Register Shadow
SHAD
FE7h PCLATH_ — Program Counter Latch High Register Shadow
SHAD
FE8h FSR0L_ Indirect Data Memory Address 0 Low Pointer Shadow
SHAD
FE9h FSR0H_ Indirect Data Memory Address 0 High Pointer Shadow
SHAD
FEAh FSR1L_ Indirect Data Memory Address 1 Low Pointer Shadow
SHAD
FEBh FSR1H_ Indirect Data Memory Address 1 High Pointer Shadow
SHAD
FECh — Unimplemented
FEDh STKPTR — — — Current Stack Pointer
FEEh TOSL Top-of-Stack Low byte
FEFh TOSH — Top-of-Stack High byte
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented,

PIC16(L)F1615/9
3.4 PCL and PCLATH 3.4.2 COMPUTED GOTO
The Program Counter (PC) is 15 bits wide. The low byte A computed GOTO is accomplished by adding an offset to
comes from the PCL register, which is a readable and the program counter (ADDWF PCL). When performing a
writable register. The high byte (PC<14:8>) is not directly table read using a computed GOTO method, care should
readable or writable and comes from PCLATH. On any be exercised if the table location crosses a PCL memory
Reset, the PC is cleared. Figure 3-3 shows the five boundary (each 256-byte block). Refer to Application
situations for the loading of the PC. Note AN556, “Implementing a Table Read” (DS00556).
3.4.3 COMPUTED FUNCTION CALLS

FIGURE 3-3: LOADING OF PC IN
DIFFERENT SITUATIONS A computed function CALL allows programs to maintain
tables of functions and provide another way to execute
Rev. 10-000042A
7/30/2013 state machines or look-up tables. When performing a
table read using a computed function CALL, care
14 PCH PCL 0 Instruction should be exercised if the table location crosses a PCL
PC with PCL as memory boundary (each 256-byte block).
Destination
6
7
0
8 If using the CALL instruction, the PCH<2:0> and PCL
PCLATH ALU result registers are loaded with the operand of the CALL
instruction. PCH<6:3> is loaded with PCLATH<6:3>.
14 PCH PCL 0 GOTO,
The CALLW instruction enables computed calls by com-
PC
CALL bining PCLATH and W to form the destination address.
4 11
A computed CALLW is accomplished by loading the W
PCLATH
6 0 register with the desired address and executing CALLW.
OPCODE <10:0>
The PCL register is loaded with the value of W and
PCH is loaded with PCLATH.
14 PCH PCL 0
PC CALLW 3.4.4 BRANCHING
6
7
0 8 The branching instructions add an offset to the PC.
PCLATH W This allows relocatable code and code that crosses
page boundaries. There are two forms of branching,
BRW and BRA. The PC will have incremented to fetch
14 PCH PCL 0
PC BRW the next instruction in both cases. When using either
branching instruction, a PCL memory boundary may be
15 crossed.
PC + W
If using BRW, load the W register with the desired
14 PCH PCL 0 unsigned address and execute BRW. The entire PC will
PC BRA
be loaded with the address PC + 1 + W.
15 If using BRA, the entire PC will be loaded with PC + 1 +,
PC + OPCODE <8:0> the signed value of the operand of the BRA instruction.
3.4.1 MODIFYING PCL

Executing any instruction with the PCL register as the
destination simultaneously causes the Program
Counter PC<14:8> bits (PCH) to be replaced by the
contents of the PCLATH register. This allows the entire
contents of the program counter to be changed by
writing the desired upper seven bits to the PCLATH
register. When the lower eight bits are written to the
PCL register, all 15 bits of the program counter will
change to the values contained in the PCLATH register
and those being written to the PCL register.

PIC16(L)F1615/9
3.5 Stack 3.5.1 ACCESSING THE STACK
All devices have a 16-level x 15-bit wide hardware The stack is available through the TOSH, TOSL and
stack (refer to Figures 3-4 through 3-7). The stack STKPTR registers. STKPTR is the current value of the
space is not part of either program or data space. The Stack Pointer. TOSH:TOSL register pair points to the
PC is PUSHed onto the stack when CALL or CALLW TOP of the stack. Both registers are read/writable. TOS
instructions are executed or an interrupt causes a is split into TOSH and TOSL due to the 15-bit size of the
branch. The stack is POPed in the event of a RETURN, PC. To access the stack, adjust the value of STKPTR,
RETLW or a RETFIE instruction execution. PCLATH is which will position TOSH:TOSL, then read/write to
not affected by a PUSH or POP operation. TOSH:TOSL. STKPTR is five bits to allow detection of
overflow and underflow.
The stack operates as a circular buffer if the STVREN
bit is programmed to ‘0’ (Configuration Words). This Note: Care should be taken when modifying the
means that after the stack has been PUSHed sixteen STKPTR while interrupts are enabled.
times, the seventeenth PUSH overwrites the value that
During normal program operation, CALL, CALLW and
was stored from the first PUSH. The eighteenth PUSH
Interrupts will increment STKPTR while RETLW,
overwrites the second PUSH (and so on). The
RETURN, and RETFIE will decrement STKPTR. At any
STKOVF and STKUNF flag bits will be set on an Over-
time STKPTR can be inspected to see how much stack
flow/Underflow, regardless of whether the Reset is
is left. The STKPTR always points at the currently used
enabled.
place on the stack. Therefore, a CALL or CALLW will
Note 1: There are no instructions/mnemonics increment the STKPTR and then write the PC, and a
called PUSH or POP. These are actions return will unload the PC and then decrement the
that occur from the execution of the STKPTR.
CALL, CALLW, RETURN, RETLW and Reference Figure 3-4 through Figure 3-7 for examples
RETFIE instructions or the vectoring to of accessing the stack.
an interrupt address.
FIGURE 3-4: ACCESSING THE STACK EXAMPLE 1
Rev. 10-000043A
7/30/2013
Stack Reset Disabled

TOSH:TOSL 0x0F STKPTR = 0x1F
(STVREN = 0)
0x0E
0x0D
0x0C
0x0B
Initial Stack Configuration:
0x0A
0x09 After Reset, the stack is empty. The
empty stack is initialized so the Stack
0x08 Pointer is pointing at 0x1F. If the Stack
0x07 Overflow/Underflow Reset is enabled, the
TOSH/TOSL register will return ‘0’. If the
0x06 Stack Overflow/Underflow Reset is
0x05 disabled, the TOSH/TOSL register will
return the contents of stack address
0x04 0x0F.
0x03
0x02
0x01
0x00
Stack Reset Enabled
TOSH:TOSL 0x1F 0x0000 STKPTR = 0x1F
(STVREN = 1)

PIC16(L)F1615/9
Rev. 10-000043B
7/30/2013
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09 This figure shows the stack configuration
after the first CALL or a single interrupt.
0x08 If a RETURN instruction is executed, the
0x07 return address will be placed in the
Program Counter and the Stack Pointer
0x06 decremented to the empty state (0x1F).
0x05
0x04
0x03
0x02
0x01
TOSH:TOSL 0x00 Return Address STKPTR = 0x00
Rev. 10-000043C
7/30/2013
0x0F
0x0E
0x0D
0x0C
After seven CALLs or six CALLs and an
0x0B interrupt, the stack looks like the figure on
the left. A series of RETURN instructions will
0x0A
repeatedly place the return addresses into
0x09 the Program Counter and pop the stack.
0x08
0x07
0x05 Return Address

0x04 Return Address
0x03 Return Address
0x02 Return Address
0x01 Return Address
0x00 Return Address

PIC16(L)F1615/9
Rev. 10-000043D
7/30/2013
0x0F Return Address

0x0E Return Address
0x0D Return Address
0x0C Return Address
0x0B Return Address
0x0A Return Address When the stack is full, the next CALL or
0x09 Return Address an interrupt will set the Stack Pointer to
0x10. This is identical to address 0x00 so
0x08 Return Address the stack will wrap and overwrite the
0x07 Return Address return address at 0x00. If the Stack
Overflow/Underflow Reset is enabled, a
0x06 Return Address Reset will occur and location 0x00 will
0x05 Return Address not be overwritten.
0x04 Return Address

0x03 Return Address
0x02 Return Address
0x01 Return Address
3.5.2 OVERFLOW/UNDERFLOW RESET

If the STVREN bit in Configuration Words is
programmed to ‘1’, the device will be reset if the stack
is PUSHed beyond the sixteenth level or POPed
beyond the first level, setting the appropriate bits
(STKOVF or STKUNF, respectively) in the PCON
register.
3.6 Indirect Addressing

The INDFn registers are not physical registers. Any
instruction that accesses an INDFn register actually
accesses the register at the address specified by the
File Select Registers (FSR). If the FSRn address
specifies one of the two INDFn registers, the read will
return ‘0’ and the write will not occur (though Status bits
may be affected). The FSRn register value is created
by the pair FSRnH and FSRnL.
The FSR registers form a 16-bit address that allows an
addressing space with 65536 locations. These locations
are divided into three memory regions:
• Traditional Data Memory
• Linear Data Memory
• Program Flash Memory

PIC16(L)F1615/9
FIGURE 3-8: INDIRECT ADDRESSING
Rev. 10-000044A
7/30/2013
0x0000 0x0000
Traditional
Data Memory
0x0FFF 0x0FFF
0x1000
Reserved
0x1FFF
0x2000
Linear
Data Memory
0x29AF
0x29B0
Reserved
0x7FFF
FSR
0x8000 0x0000
Address
Range
Program
Flash Memory
0xFFFF 0x7FFF
Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits.

PIC16(L)F1615/9
3.6.1 TRADITIONAL DATA MEMORY
The traditional data memory is a region from FSR
address 0x000 to FSR address 0xFFF. The addresses
correspond to the absolute addresses of all SFR, GPR
and common registers.
FIGURE 3-9: TRADITIONAL DATA MEMORY MAP
Rev. 10-000056A
7/31/2013
Direct Addressing Indirect Addressing
From Opcode
4 BSR 0 6 0 7 FSRxH 0 7 FSRxL 0
0 0 0 0
Bank Select Location Select Bank Select Location Select
00000 00001 00010 11111

0x00
0x7F
Bank 0 Bank 1 Bank 2 Bank 31

PIC16(L)F1615/9
3.6.2 LINEAR DATA MEMORY 3.6.3 PROGRAM FLASH MEMORY
The linear data memory is the region from FSR To make constant data access easier, the entire
address 0x2000 to FSR address 0x29AF. This region is program Flash memory is mapped to the upper half of
a virtual region that points back to the 80-byte blocks of the FSR address space. When the MSb of FSRnH is
GPR memory in all the banks. set, the lower 15 bits are the address in program
Unimplemented memory reads as 0x00. Use of the memory which will be accessed through INDF. Only the
linear data memory region allows buffers to be larger lower eight bits of each memory location is accessible
than 80 bytes because incrementing the FSR beyond via INDF. Writing to the program Flash memory cannot
one bank will go directly to the GPR memory of the next be accomplished via the FSR/INDF interface. All
bank. instructions that access program Flash memory via the
FSR/INDF interface will require one additional
The 16 bytes of common memory are not included in instruction cycle to complete.
the linear data memory region.
FIGURE 3-11: PROGRAM FLASH
FIGURE 3-10: LINEAR DATA MEMORY MEMORY MAP
MAP
Rev. 10-000057A Rev. 10-000058A
7/31/2013 7/31/2013
7 FSRnH 0 7 FSRnL 0
7 FSRnH 0 7 FSRnL 0 1
0 0 1
Location Select
Location Select 0x8000
0x2000 0x0000
0x020
Bank 0
0x06F
0x0A0
Bank 1
0x0EF Program
Flash
0x120 Memory
Bank 2 (low 8 bits)
0x16F
0xF20
Bank 30 0x7FFF
0xF6F 0xFFFF
0x29AF

PIC16(L)F1615/9
4.0 DEVICE CONFIGURATION
Device configuration consists of Configuration Words,
Code Protection and Device ID.
4.1 Configuration Words

There are several Configuration Word bits that allow
different oscillator and memory protection options.
These are implemented as Configuration Word 1 at
8007h, Configuration Word 2 at 8008h, and
Configuration 3 at 8009h.
Note: The DEBUG bit in Configuration Words is
managed automatically by device
development tools including debuggers
and programmers. For normal device
operation, this bit should be maintained as
a ‘1’.

PIC16(L)F1615/9
4.2 Register Definitions: Configuration Words
REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1
FCMEN IESO CLKOUTEN BOREN<1:0>(1) —
bit 13 bit 8
R/P-1 R/P-1 R/P-1 U-1 U-1 R/P-1 R/P-1 R/P-1

CP(2) MCLRE PWRTE — — FOSC<2:0>
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase
bit 13 FCMEN: Fail Clock Monitor Enable bit

1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
bit 12 IESO: Internal/External Switch Over bit
1 = Internal/External Switch Over mode is enabled
0 = Internal/External Switch Over mode is disabled
bit 11 CLKOUTEN: Clock Out Enable bit
1 = CLKOUT function is disabled. I/O function on the CLKOUT pin
0 = CLKOUT function is enabled on the CLKOUT pin
bit 10-9 BOREN<1:0>: Brown-Out Reset Enable bits(1)
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit of the BORCON register
00 = BOR disabled
bit 8 Unimplemented: Read as ‘1’
bit 7 CP: Code Protection bit(2)
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
bit 6 MCLRE: MCLR/VPP Pin Function Select bit
If LVP bit = 1:
This bit is ignored.
If LVP bit = 0:
1 =MCLR/VPP pin function is MCLR; Weak pull-up enabled.
0 =MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of
WPUA3 bit.
bit 5 PWRTE: Power-Up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled

PIC16(L)F1615/9
REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1 (CONTINUED)
bit 2-0 FOSC<2:0>: Oscillator Selection bits
111 =ECH: External clock, High-Power mode: on CLKIN pin
110 =ECM: External clock, Medium-Power mode: on CLKIN pin
101 =ECL: External clock, Low-Power mode: on CLKIN pin
100 =INTOSC oscillator: I/O function on CLKIN pin
011 =Reserved
010 =HS: HS oscillator, high-speed crystal/resonator connected between OSC1 and OSC2 pins
001 =Reserved
000 =Reserved
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: Once enabled, code-protect can only be disabled by bulk erasing the device.

PIC16(L)F1615/9

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
LVP (1) DEBUG(3) LPBOR BORV(2) STVREN PLLEN
bit 13 bit 8
R/P-1 U-1 U-1 U-1 U-1 R/P-1 R/P-1 R/P-1

ZCD — — — — PPS1WAY WRT<1:0>
bit 7 bit 0
Legend:
bit 13 LVP: Low-Voltage Programming Enable bit(1)

1 = Low-voltage programming enabled
0 = High-voltage on MCLR must be used for programming
bit 12 DEBUG: In-Circuit Debugger Mode bit(3)
1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins
0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger
bit 11 LPBOR: Low-Power BOR Enable bit
1 = Low-Power Brown-out Reset is disabled
0 = Low-Power Brown-out Reset is enabled
bit 10 BORV: Brown-Out Reset Voltage Selection bit(2)
1 = Brown-out Reset voltage (VBOR), low trip point selected
0 = Brown-out Reset voltage (VBOR), high trip point selected
bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit
1 = Stack Overflow or Underflow will cause a Reset
0 = Stack Overflow or Underflow will not cause a Reset
bit 8 PLLEN: PLL Enable bit
1 = 4xPLL enabled
0 = 4xPLL disabled
bit 7 ZCD: ZCD Disable bit
1 = ZCD disabled. ZCD can be enabled by setting the ZCD1EN bit of ZCD1CON
0 = ZCD always enabled
bit 2 PPS1WAY: PPSLOCK Bit One-Way Set Enable bit
1 = The PPSLOCK bit can only be set once after an unlocking sequence is executed; once PPSLOCK
is set, all future changes to PPS registers are prevented
0 = The PPSLOCK bit can be set and cleared as needed (provided an unlocking sequence is executed)
bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits
8 kW Flash memory (PIC16(L)F1615/9):
11 = OFF - Write protection off
10 = BOOT - 000h to 01FFh write-protected, 200h to 1FFFh may be modified by PMCON control
01 = HALF - 000h to 0FFFh write-protected, 1000h to 1FFFh may be modified by PMCON control
00 = ALL - 000h to 1FFFh write-protected, no addresses may be modified by PMCON control
Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
2: See VBOR parameter for specific trip point voltages.
3: The DEBUG bit in Configuration Words is managed automatically by device development tools including
debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.

PIC16(L)F1615/9

R/P-0 R/P-0 R/P-1 R/P-1 R/P-1 R/P-1
WDTCCS<2:0> WDTCWS<2:0>
bit 13 bit 8
U-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

— WDTE<1:0> WDTCPS<4:0>
bit 7 bit 0
Legend:
bit 13-11 WDTCCS<2:0>: WDT Configuration Clock Select bits

111 =Software Control; WDT clock selected by CS<2:0>
110 =Reserved
•
•
•
010 =Reserved
001 =WDT reference clock is MFINTOSC, 31.25 kHz (default value)
000 =WDT reference clock is LFINTOSC, 31.00 kHz output
bit 10-8 WDTCWS<2:0>: WDT Configuration Window Select bits.
WINDOW at POR Software Keyed

WDTCWS
Window delay Window opening control of access
<2:0> Value
Percent of time Percent of time WINDOW? required?
111 111 n/a 100 Yes No Default fuse = 111

110 111 n/a 100
101 101 25 75
100 100 37.5 62.5
011 011 50 50 No Yes
010 010 62.5 37.5
001 001 75 25
000 000 87.5 12.5(1)

bit 6-5 WDTE<1:0>: Watchdog Timer Enable bits
11 =WDT enabled in all modes, the SEN bit in the WDTCON0 register is ignored
10 =WDT enabled while running and disabled in Sleep
01 =WDT controlled by the SEN bit in the WDTCON0 register
00 = WDT disabled

PIC16(L)F1615/9
REGISTER 4-3: CONFIG3: CONFIGURATION WORD 3 (CONTINUED)
bit 4-0 WDTCPS<4:0>: WDT Configuration Period Select bits
WDTPS at POR
Software
WDTCPS Typical control of
<4:0> Value Divider Ratio time out WDTPS
(FIN = 31 kHz)
Default
11111 01011 1:65536 216 2s Yes
fuse = 11111
10011 10011
... ... 1:32 25 1 ms No
11110 11110
10010 10010 1:8388608 223 256 s
10001 10001 1:4194304 222 128 s
10000 10000 1:2097152 221 64 s
01111 01111 1:1048576 220 32 s
01110 01110 1:524299 219 16 s
01101 01101 1:262144 218 8s
01100 01100 1:131072 217 4s
01011 01011 1:65536 216 2s
01010 01010 1:32768 215 1s
01001 01001 1:16384 214 512 ms No
01000 01000 1:8192 213 256 ms
00111 00111 1:4096 212 128 ms
00110 00110 1:2048 211 64 ms
00101 00101 1:1024 210 32 ms
00100 00100 1:512 29 16 ms
00011 00011 1:256 28 8 ms
00010 00010 1:128 27 4 ms
00001 00001 1:64 26 2 ms
00000 00000 1:32 25 1 ms
Note 1: A window delay of 12.5% is only available in Software Control mode via the WDTCON1 register.

PIC16(L)F1615/9
4.3 Code Protection
Code protection allows the device to be protected from
unauthorized access. Internal access to the program
memory is unaffected by any code protection setting.
4.3.1 PROGRAM MEMORY PROTECTION

The entire program memory space is protected from
external reads and writes by the CP bit in Configuration
Words. When CP = 0, external reads and writes of
program memory are inhibited and a read will return all
‘0’s. The CPU can continue to read program memory,
regardless of the protection bit settings. Writing the
program memory is dependent upon the write
protection setting. See Section 4.4 “Write
Protection” for more information.
4.4 Write Protection

Write protection allows the device to be protected from
unintended self-writes. Applications, such as boot
loader software, can be protected while allowing other
regions of the program memory to be modified.
The WRT<1:0> bits in Configuration Words define the
size of the program memory block that is protected.
4.5 User ID
Four memory locations (8000h-8003h) are designated as
ID locations where the user can store checksum or other
code identification numbers. These locations are
readable and writable during normal execution. See
Section 10.4 “User ID, Device ID and Configuration
Word Access” for more information on accessing these
memory locations. For more information on checksum
calculation, see the “PIC12(L)F1612/16(L)F161X
Memory Programming Specification” (DS40001720).

PIC16(L)F1615/9
4.6 Device ID and Revision ID
The 14-bit Device ID word is located at 8006h and the
14-bit Revision ID is located at 8005h. These locations
are read-only and cannot be erased or modified. See
Section 10.4 “User ID, Device ID and Configuration
Word Access” for more information on accessing
these memory locations.
Development tools, such as device programmers and
debuggers, may be used to read the Device ID and
Revision ID.
4.7 Register Definitions: Device ID
REGISTER 4-4: DEVID: DEVICE ID REGISTER

R R R R R R
DEV<13:8>
bit 13 bit 8
R R R R R R R R
DEV<7:0>
bit 7 bit 0
Legend:
R = Readable bit
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 13-0 DEV<13:0>: Device ID bits
Device DEVID<13:0> Values

PIC16F1615 11 0000 0111 1100 (307Ch)
PIC16LF1615 11 0000 0111 1110 (307Eh)
PIC16F1619 11 0000 0111 1101 (307Dh)
PIC16LF1619 11 0000 0111 1111 (307Fh)
REGISTER 4-5: REVID: REVISION ID REGISTER

R R R R R R
REV<13:8>
bit 13 bit 8
R R R R R R R R
REV<7:0>
bit 7 bit 0
Legend:
R = Readable bit
bit 13-0 REV<13:0>: Revision ID bits

PIC16(L)F1615/9
5.0 OSCILLATOR MODULE The oscillator module can be configured in one of the
following clock modes.
5.1 Overview 1. ECL – External Clock Low-Power mode
(0 MHz to 0.5 MHz)
The oscillator module has a wide variety of clock
2. ECM – External Clock Medium-Power mode
sources and selection features that allow it to be used
(0.5 MHz to 4 MHz)
in a wide range of applications while maximizing perfor-
mance and minimizing power consumption. Figure 5-1 3. ECH – External Clock High-Power mode
illustrates a block diagram of the oscillator module. (4 MHz to 32 MHz)
4. INTOSC – Internal oscillator (31 kHz to 32 MHz).
Clock sources can be supplied from external oscillators.
In addition, the system clock source can be supplied 5. HS – High Gain Crystal or Ceramic Resonator
from one of two internal oscillators and PLL circuits, with mode (4 MHz to 10 MHz)
a choice of speeds selectable via software. Additional Clock Source modes are selected by the FOSC<1:0>
clock features include: bits in the Configuration Words. The FOSC bits
• Selectable system clock source between external determine the type of oscillator that will be used when
or internal sources via software. the device is first powered.
• Two-Speed Start-up mode, which minimizes The ECH, ECM, and ECL Clock modes rely on an
latency between external oscillator start-up and external logic level signal as the device clock
code execution. source.The HS Clock mode requires an external crystal
• Fail-Safe Clock Monitor (FSCM) designed to or resonator to be connected to the device.
detect a failure of the external clock source (HS, The INTOSC internal oscillator block produces low,
ECH, ECM, or ECL modes) and switch medium, and high-frequency clock sources,
automatically to the internal oscillator. designated LFINTOSC, MFINTOSC and HFINTOSC.
• Oscillator Start-up Timer (OST) ensures stability (see Internal Oscillator Block, Figure 5-1). A wide
of crystal oscillator sources selection of device clock frequencies may be derived
from these three clock sources.

PIC16(L)F1615/9
FIGURE 5-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
Rev. 10-000155C
1/21/2015
FOSC<2:0>
CLKIN/ OSC1
3 Sleep
Primary
Oscillator
(OSC) 0 FOSC(1)
00
4x PLL(2) 1 to CPU and
Peripherals
CLKOUT/
OSC2 PLLEN
SPLLEN
INTOSC
1x
16 MHz
8 MHz
4 MHz 2
HFPLL HFINTOSC(1) 2 MHz SCS<1:0>

1 MHz
Prescaler
16 MHz
*500 kHz
MFINTOSC(1) *250 kHz

500 kHz
Oscillator *125 kHz
62.5 kHz
*31.25 kHz
*31 kHz
Internal Oscillator
Block 4
IRCF<3:0>
31 kHz LFINTOSC(1)
to WDT, PWRT, and
Oscillator other Peripherals
to Peripherals
600 kHz FRC(1) to ADC and
Oscillator other Peripherals
* Available with more than one IRCF selection
Note 1: See Section 5.2 “Clock Source Types”.

2: When FOSC<1:0> = 00, 4x PLL can only be used if IRCF<3:0> = 1110.

PIC16(L)F1615/9
5.2 Clock Source Types The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
Clock sources can be classified as external or internal. operation after a Power-On Reset (POR) or wake-up
External clock sources rely on external circuitry for the from Sleep. Because the PIC® MCU design is fully
clock source to function. Examples are: oscillator static, stopping the external clock input will have the
modules (ECH, ECM, ECL modes) and quartz crystal effect of limiting the device while leaving all data intact.
resonators or ceramic resonators (HS mode). Upon restarting the external clock, the device will
resume operation as if no time had elapsed.
Internal clock sources are contained within the oscilla-
tor module. The internal oscillator block has two inter-
nal oscillators and a dedicated Phase Lock Loop FIGURE 5-2: EXTERNAL CLOCK (EC)
(HFPLL) that are used to generate three internal sys- MODE OPERATION
tem clock sources: the 16 MHz High-Frequency Inter-
nal Oscillator (HFINTOSC), 500 kHz (MFINTOSC) and CLKIN
Clock from
the 31 kHz Low-Frequency Internal Oscillator Ext. System
(LFINTOSC). PIC® MCU
The system clock can be selected between external or
CLKOUT
internal clock sources via the System Clock Select FOSC/4 or I/O(1)
(SCS) bits in the OSCCON register. See
Section5.3 “Clock Switching” for additional informa-
Note 1: Output depends upon CLKOUTEN bit of the
tion. Configuration Words.
5.2.1 EXTERNAL CLOCK SOURCES

An external clock source can be used as the device 5.2.1.2 HS Mode
system clock by performing one of the following The HS mode supports the use of quartz crystal reso-
actions: nators or ceramic resonators connected to OSC1 and
• Program the FOSC<1:0> bits in the Configuration OSC2. Figure 5-3 and Figure 5-4 show typical circuits
Words to select an external clock source that will for quartz crystal and ceramic resonators, respectively.
be used as the default system clock upon a
device Reset. FIGURE 5-3: QUARTZ CRYSTAL
• Write the SCS<1:0> bits in the OSCCON register OPERATION (HS MODE)
to switch the system clock source to: Rev. 10-000059A
7/30/2013
- An external clock source determined by the

value of the FOSC bits.
PIC® MCU
See Section5.3 “Clock Switching”for more informa-
tion. OSC1/CLKIN
C1 To Internal
5.2.1.1 EC Mode Logic
Quartz
The External Clock (EC) mode allows an externally
Crystal RF(2) Sleep
generated logic level signal to be the system clock
source. When operating in this mode, an external clock
source is connected to the CLKIN input. CLKOUT is C2 RS(1)
OSC2/CLKOUT
available for general purpose I/O or CLKOUT. Figure 5-2
shows the pin connections for EC mode.
Note 1: A series resistor (Rs) may be required for
EC mode has three power modes to select from through quartz crystals with low drive level.
the FOSC bits in the Configuration Words:
2: The value of RF varies with the Oscillator mode
• ECH – High power, 4-20 MHz selected (typically between 2 MΩ and 10 MΩ).
• ECM – Medium power, 0.5-4 MHz
• ECL – Low power, 0-0.5 MHz

PIC16(L)F1615/9
FIGURE 5-4: CERAMIC RESONATOR
OPERATION (HS MODE)
Rev. 10-000060A
7/30/2013
Ceramic PIC® MCU

Resonator OSC1/CLKIN
C1 To Internal
Logic
RP(3) RF(2) Sleep
OSC2/CLKOUT
C2 RS(1)
Note 1: A series resistor (Rs) may be required for

ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode

selected (typically between 2 MΩ and 10 MΩ).
3. An additional parallel feedback resistor (RP)

may be required for proper ceramic resonator
operation.
5.2.1.3 Oscillator Start-up Timer (OST)

If the oscillator module is configured for HS modes, the
Oscillator Start-up Timer (OST) counts 1024
oscillations from OSC1. This occurs following a Power-
on Reset (POR) and when the Power-up Timer
(PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
increment and program execution is suspended. The
OST ensures that the oscillator circuit, using a quartz
crystal resonator or ceramic resonator, has started and
is providing a stable system clock to the oscillator
module.
In order to minimize latency between external oscillator
start-up and code execution, the Two-Speed Clock
Start-up mode can be selected (see Section5.4 “Two-
Speed Clock Start-up Mode”).

PIC16(L)F1615/9
5.2.2 INTERNAL CLOCK SOURCES 5.2.2.1 HFINTOSC
The device may be configured to use the internal oscil- The High-Frequency Internal Oscillator (HFINTOSC) is
lator block as the system clock by performing one of the a factory calibrated 16 MHz internal clock source. The
following actions: frequency of the HFINTOSC can be altered via
• Program the FOSC<1:0> bits in Configuration software using the OSCTUNE register (Register 5-3).
Words to select the INTOSC clock source, which The output of the HFINTOSC connects to a postscaler
will be used as the default system clock upon a and multiplexer (see Figure 5-1). One of multiple
device Reset. frequencies derived from the HFINTOSC can be
• Write the SCS<1:0> bits in the OSCCON register selected via software using the IRCF<3:0> bits of the
to switch the system clock source to the internal OSCCON register. See Section5.2.2.8 “Internal
oscillator during run-time. See Section5.3 “Clock Oscillator Clock Switch Timing” for more information.
Switching”for more information. The HFINTOSC is enabled by:
In INTOSC mode, CLKIN is available for general • Configure the IRCF<3:0> bits of the OSCCON
purpose I/O. CLKOUT is available for general purpose register for the desired HF frequency, and
I/O or CLKOUT. • FOSC<1:0> = 00, or
The function of the OSC2/CLKOUT pin is determined • Set the System Clock Source (SCS) bits of the
by the CLKOUTEN bit in Configuration Words. OSCCON register to ‘1x’.
The internal oscillator block has two independent A fast start-up oscillator allows internal circuits to power
oscillators and a dedicated Phase Lock Loop, HFPLL up and stabilize before switching to HFINTOSC.
that can produce one of three internal system clock
The High-Frequency Internal Oscillator Ready bit
sources.
(HFIOFR) of the OSCSTAT register indicates when the
1. The HFINTOSC (High-Frequency Internal HFINTOSC is running.
Oscillator) is factory calibrated and operates at
The High-Frequency Internal Oscillator Status Locked
16 MHz. The HFINTOSC source is generated
bit (HFIOFL) of the OSCSTAT register indicates when
from the 500 kHz MFINTOSC source and the
the HFINTOSC is running within 2% of its final value.
dedicated Phase Lock Loop, HFPLL. The
frequency of the HFINTOSC can be user- The High-Frequency Internal Oscillator Stable bit
adjusted via software using the OSCTUNE (HFIOFS) of the OSCSTAT register indicates when the
register (Register 5-3). HFINTOSC is running within 0.5% of its final value.
2. The MFINTOSC (Medium-Frequency Internal
Oscillator) is factory calibrated and operates at 5.2.2.2 MFINTOSC
500 kHz. The frequency of the MFINTOSC can The Medium-Frequency Internal Oscillator
be user-adjusted via software using the (MFINTOSC) is a factory calibrated 500 kHz internal
OSCTUNE register (Register 5-3). clock source. The frequency of the MFINTOSC can be
3. The LFINTOSC (Low-Frequency Internal altered via software using the OSCTUNE register
Oscillator) is uncalibrated and operates at (Register 5-3).
31 kHz. The output of the MFINTOSC connects to a postscaler
and multiplexer (see Figure 5-1). One of nine
frequencies derived from the MFINTOSC can be
selected via software using the IRCF<3:0> bits of the
OSCCON register. See Section5.2.2.8 “Internal
Oscillator Clock Switch Timing” for more information.
The MFINTOSC is enabled by:
• Configure the IRCF<3:0> bits of the OSCCON
register for the desired HF frequency, and
• FOSC<1:0> = 00, or
• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’
The Medium-Frequency Internal Oscillator Ready bit
(MFIOFR) of the OSCSTAT register indicates when the
MFINTOSC is running.

PIC16(L)F1615/9
5.2.2.3 Internal Oscillator Frequency 5.2.2.5 FRC
Adjustment The FRC clock is an uncalibrated, nominal 600 kHz
The 500 kHz internal oscillator is factory calibrated. peripheral clock source.
This internal oscillator can be adjusted in software by The FRC is automatically turned on by the peripherals
writing to the OSCTUNE register (Register 5-3). Since requesting the FRC clock.
the HFINTOSC and MFINTOSC clock sources are
derived from the 500 kHz internal oscillator a change in The FRC clock will continue to run during Sleep.
the OSCTUNE register value will apply to both.
5.2.2.6 Internal Oscillator Frequency
The default value of the OSCTUNE register is ‘0’. The Selection
value is a 6-bit two’s complement number. A value of
1Fh will provide an adjustment to the maximum The system clock speed can be selected via software
frequency. A value of 20h will provide an adjustment to using the Internal Oscillator Frequency Select bits
the minimum frequency. IRCF<3:0> of the OSCCON register.
When the OSCTUNE register is modified, the oscillator The postscaler outputs of the 16 MHz HFINTOSC, 500
frequency will begin shifting to the new frequency. Code kHz MFINTOSC, and 31 kHz LFINTOSC output
execution continues during this shift. There is no connect to a multiplexer (see Figure 5-1). The Internal
indication that the shift has occurred. Oscillator Frequency Select bits IRCF<3:0> of the
OSCCON register select the frequency output of the
OSCTUNE does not affect the LFINTOSC frequency. internal oscillators. One of the following frequencies
Operation of features that depend on the LFINTOSC can be selected via software:
clock source frequency, such as the Power-up Timer
(PWRT), Watchdog Timer (WDT), and peripherals, are - 16 MHz
not affected by the change in frequency. - 8 MHz
- 4 MHz
5.2.2.4 LFINTOSC - 2 MHz
The Low-Frequency Internal Oscillator (LFINTOSC) is - 1 MHz
an uncalibrated 31 kHz internal clock source. - 500 kHz (default after Reset)
The output of the LFINTOSC connects to a multiplexer - 250 kHz
(see Figure 5-1). Select 31 kHz, via software, using the - 125 kHz
IRCF<3:0> bits of the OSCCON register. See
- 62.5 kHz
Section5.2.2.8 “Internal Oscillator Clock Switch
Timing” for more information. The LFINTOSC is also - 31.25 kHz
the frequency for the Power-up Timer (PWRT), - 31 kHz (LFINTOSC)
Watchdog Timer (WDT) and Fail-Safe Clock Monitor Note: Following any Reset, the IRCF<3:0> bits
(FSCM). of the OSCCON register are set to ‘0111’
The LFINTOSC is enabled by selecting 31 kHz and the frequency selection is set to
(IRCF<3:0> bits of the OSCCON register = 000) as the 500 kHz. The user can modify the IRCF
system clock source (SCS bits of the OSCCON bits to select a different frequency.
register = 1x), or when any of the following are The IRCF<3:0> bits of the OSCCON register allow
enabled: duplicate selections for some frequencies. These dupli-
• Configure the IRCF<3:0> bits of the OSCCON cate choices can offer system design trade-offs. Lower
register for the desired LF frequency, and power consumption can be obtained when changing
• FOSC<1:0> = 00, or oscillator sources for a given frequency. Faster transi-
• Set the System Clock Source (SCS) bits of the tion times can be obtained between frequency changes
OSCCON register to ‘1x’ that use the same oscillator source.
Peripherals that use the LFINTOSC are:

• Power-up Timer (PWRT)
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor (FSCM)
The Low-Frequency Internal Oscillator Ready bit
(LFIOFR) of the OSCSTAT register indicates when the
LFINTOSC is running.

PIC16(L)F1615/9
5.2.2.7 32 MHz Internal Oscillator 5.2.2.8 Internal Oscillator Clock Switch
Frequency Selection Timing
The Internal Oscillator Block can be used with the When switching between the HFINTOSC, MFINTOSC
4x PLL associated with the External Oscillator Block to and the LFINTOSC, the new oscillator may already be
produce a 32 MHz internal system clock source. Either shut down to save power (see Figure 5-3). If this is the
the 8 or 16 MHz internal oscillator settings can be used, case, there is a delay after the IRCF<3:0> bits of the
with the 16 MHz being divided by two before being OSCCON register are modified before the frequency
input into the PLL. The following settings are required selection takes place. The OSCSTAT register will
to use the 32 MHz internal clock source: reflect the current active status of the HFINTOSC,
• The FOSC bits in Configuration Words must be MFINTOSC and LFINTOSC oscillators. The sequence
set to use the INTOSC source as the device of a frequency selection is as follows:
system clock (FOSC<1:0> = 00). 1. IRCF<3:0> bits of the OSCCON register are
• The SCS bits in the OSCCON register must be modified.
cleared to use the clock determined by 2. If the new clock is shut down, a clock start-up
FOSC<1:0> in Configuration Words delay is started.
(SCS<1:0> = 00). 3. Clock switch circuitry waits for a falling edge of
• The IRCF bits in the OSCCON register must be the current clock.
set to either the 16 MHz (IRCF<3:0> = 1111) or 4. The current clock is held low and the clock
the 8 MHz HFINTOSC (IRCF<3:0> = 1110). switch circuitry waits for a rising edge in the new
• The SPLLEN bit in the OSCCON register must be clock.
set to enable the 4x PLL, or the PLLEN bit of the 5. The new clock is now active.
Configuration Words must be programmed to a 6. The OSCSTAT register is updated as required.
‘1’.
7. Clock switch is complete.
Note: When using the PLLEN bit of the
See Figure 5-3 for more details.
Configuration Words, the 4x PLL cannot
be disabled by software and the 8/16 MHz If the internal oscillator speed is switched between two
HFINTOSC option will no longer be clocks of the same source, there is no start-up delay
available. before the new frequency is selected. Clock switching
time delays are shown in Table 5-1.
The 4x PLL is not available for use with the internal
oscillator when the SCS bits of the OSCCON register Start-up delay specifications are located in the
are set to ‘1x’. The SCS bits must be set to ‘00’ to use oscillator tables of Section35.0 “Electrical
the 4x PLL with the internal oscillator. Specifications”.

PIC16(L)F1615/9
FIGURE 5-5: INTERNAL OSCILLATOR SWITCH TIMING
HFINTOSC/ LFINTOSC (WDT disabled)

MFINTOSC
HFINTOSC/
MFINTOSC Start-up Time 2-cycle Sync Running
LFINTOSC
IRCF <3:0> 0 0
System Clock
HFINTOSC/ LFINTOSC (WDT enabled)

MFINTOSC
HFINTOSC/
MFINTOSC
2-cycle Sync Running
LFINTOSC
IRCF <3:0> 0 0
System Clock
LFINTOSC HFINTOSC/MFINTOSC
LFINTOSC turns off unless WDT is enabled
LFINTOSC
Start-up Time 2-cycle Sync Running
HFINTOSC/
MFINTOSC
IRCF <3:0> =0 0
System Clock

PIC16(L)F1615/9
5.3 Clock Switching 5.3.2 CLOCK SWITCHING BEFORE
SLEEP
The system clock source can be switched between
external and internal clock sources via software using When clock switching from an old clock to a new clock
the System Clock Select (SCS) bits of the OSCCON is requested just prior to entering Sleep mode, it is
register. The following clock sources can be selected necessary to confirm that the switch is complete before
using the SCS bits: the SLEEP instruction is executed. Failure to do so may
result in an incomplete switch and consequential loss of
• Default system oscillator determined by FOSC
the system clock altogether. Clock switching is
bits in Configuration Words
confirmed by monitoring the clock Status bits in the
• Internal Oscillator Block (INTOSC) OSCSTAT register. Switch confirmation can be
accomplished by sensing that the ready bit for the new
5.3.1 SYSTEM CLOCK SELECT (SCS)
clock is set or the ready bit for the old clock is cleared.
BITS For example, when switching between the internal
The System Clock Select (SCS) bits of the OSCCON oscillator with the PLL and the internal oscillator without
register selects the system clock source that is used for the PLL, monitor the PLLR bit. When PLLR is set, the
the CPU and peripherals. switch to 32 MHz operation is complete. Conversely,
• When the SCS bits of the OSCCON register = 00, when PLLR is cleared, the switch from 32 MHz
the system clock source is determined by value of operation to the selected internal clock is complete.
the FOSC<1:0> bits in the Configuration Words.
• When the SCS bits of the OSCCON register = 1x,
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<3:0>
bits of the OSCCON register. After a Reset, the
SCS bits of the OSCCON register are always
cleared.
When switching between clock sources, a delay is
required to allow the new clock to stabilize. These
oscillator delays are shown in Table 5-1.
TABLE 5-1: OSCILLATOR SWITCHING DELAYS

Switch From Switch To Frequency Oscillator Delay
LFINTOSC(1) 31 kHz
Sleep MFINTOSC(1) 31.25 kHz-500 kHz Oscillator Warm-up Delay (TWARM)(2)
HFINTOSC(1) 31.25 kHz-16 MHz
Sleep/POR EC(1) DC – 32 MHz 2 cycles
LFINTOSC EC(1) DC – 32 MHz 1 cycle of each
MFINTOSC(1) 31.25 kHz-500 kHz
Any clock source 2 s (approx.)
HFINTOSC(1) 31.25 kHz-16 MHz
Any clock source LFINTOSC(1) 31 kHz 1 cycle of each
PLL inactive PLL active 16-32 MHz 2 ms (approx.)
Note 1: PLL inactive.
2: See Section 35.0, Electrical Specifications.

PIC16(L)F1615/9
5.4 Two-Speed Clock Start-up Mode 5.4.1 TWO-SPEED START-UP MODE
CONFIGURATION
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external oscil- Two-Speed Start-up mode is configured by the following
lator start-up and code execution. In applications that settings:
make heavy use of the Sleep mode, Two-Speed Start-up • IESO (of the Configuration Words) = 1; Internal/
will remove the external oscillator start-up time from the External Switchover bit (Two-Speed Start-up
time spent awake and can reduce the overall power con- mode enabled).
sumption of the device. This mode allows the application • SCS (of the OSCCON register) = 00.
to wake-up from Sleep, perform a few instructions using
• FOSC<2:0> bits in the Configuration Words
the INTOSC internal oscillator block as the clock source
configured for HS mode.
and go back to Sleep without waiting for the external
oscillator to become stable. Two-Speed Start-up mode is entered after:
Two-Speed Start-up provides benefits when the oscillator • Power-On Reset (POR) and, if enabled, after
module is configured for HS modes. The Oscillator Start- Power-up Timer (PWRT) has expired, or
up Timer (OST) is enabled for these modes and must • Wake-up from Sleep.
count 1024 oscillations before the oscillator can be used
as the system clock source.
If the oscillator module is configured for any mode Note: When FSCM is enabled, Two-Speed Start-
other than HS mode, then Two-Speed Start-up is dis- up will automatically be enabled.
abled. This is because the external clock oscillator
does not require any stabilization time after POR or an 5.4.2 TWO-SPEED START-UP
exit from Sleep. SEQUENCE
If the OST count reaches 1024 before the device enters 1. Wake-up from Power-on Reset or Sleep.
Sleep mode, the OSTS bit of the OSCSTAT register is 2. Instructions begin execution by the internal
set and program execution switches to the external oscil- oscillator at the frequency set in the IRCF<3:0>
lator. However, the system may never operate from the bits of the OSCCON register.
external oscillator if the time spent awake is very short.
3. OST enabled to count 1024 clock cycles.
Note: Executing a SLEEP instruction will abort 4. OST timed out, wait for falling edge of the
the oscillator start-up time and will cause internal oscillator.
the OSTS bit of the OSCSTAT register to 5. OSTS is set.
remain clear. 6. System clock held low until the next falling edge
of new clock (HS mode).
7. System clock is switched to external clock
source.
5.4.3 CHECKING TWO-SPEED CLOCK

STATUS
Checking the state of the OSTS bit of the OSCSTAT
register will confirm if the CPU is running from the
external clock source, as defined by the FOSC<2:0>
bits in the Configuration Words, or the internal oscilla-
tor. See Table 5-2.
TABLE 5-2: OSCILLATOR SWITCHING DELAYS

Switch From Switch To Oscillator Delay
LFINTOSC 1 cycle of each clock source
HFINTOSC 2 s (approx.)
Any clock source ECH, ECM, ECL, EXTRC 2 cycles
HS 1024 Clock Cycles (OST)
Secondary Oscillator 1024 Secondary Oscillator Cycles

PIC16(L)F1615/9
FIGURE 5-6: TWO-SPEED START-UP
INTOSC
TOST
OSC1 0 1 1022 1023
OSC2
Program Counter PC - N PC PC + 1
System Clock

PIC16(L)F1615/9
5.5 Fail-Safe Clock Monitor 5.5.3 FAIL-SAFE CONDITION CLEARING
The Fail-Safe Clock Monitor (FSCM) allows the device When a Fail-Safe condition exists, the user must take
to continue operating should the external oscillator or the following actions to clear the condition before
external clock fail. If an oscillator mode is selected, the returning to normal operation with the external source.
FSCM can detect oscillator failure any time after the The next sections describe how to clear the Fail-Safe
Oscillator Start-up Timer (OST) has expired. When an condition for specific clock selections (FOSC bits) and
external clock mode is selected, the FSCM can detect clock switching modes (SCS bit settings).
failure as soon as the device is released from Reset.
FSCM is enabled by setting the FCMEN bit in the 5.5.3.1 External Oscillator with
Configuration Words. The FSCM is applicable to external SCS<1:0> = 00
oscillator modes (HS) and external clock modes (ECH, When a Fail-Safe condition occurs with the FOSC bits
ECM, ECL, EXTRC) and the Secondary Oscillator selecting external oscillator (FOSC<2:0> = HS) and the
(SOSC). clock switch has been selected to run from the FOSC
selection (SCS<1:0> = 00), the condition is cleared by
FIGURE 5-7: FSCM BLOCK DIAGRAM performing the following procedure.
Clock Monitor When SCS<1:0> = 00 (Running from FOSC selection)
Latch SCS<1:0> = 1x:
External
S Q
Clock Change the SCS bits in the OSCCON register
to select the internal oscillator block. This resets
the OST timer and allows it to operate again.
LFINTOSC
÷ 64 R Q OSFIF = 0:
Oscillator
Clear the OSFIF bit in the PIR2 register.
31 kHz 488 Hz
(~32 s) (~2 ms) SCS<1:0> = 00:
Change the SCS bits in the OSCCON register
Sample Clock Clock to select the FOSC Configuration Word clock
Failure selection. This will start the OST. The CPU will
Detected continue to operate from the internal oscillator
until the OST count is reached. When OST
expires, the clock module will switch to the
5.5.1 FAIL-SAFE DETECTION
external oscillator and the Fail-Safe condition
The FSCM module detects a failed oscillator by will be cleared.
monitoring falling clock edges and using LFINTOSC as a
If the Fail-Safe condition still exists, the OSFIF bit will
time base. See Figure 5-7. Detection of a failed oscillator
again be set by hardware.
will take 32 to 96 cycles of the LFINTOSC. Figure 5-10
shows a timing diagram of the FSCM module. 5.5.3.2 External Clock with SCS<1:0> = 00
5.5.2 FAIL-SAFE OPERATION When a Fail-Safe condition occurs with the FOSC bits
selecting external clock (FOSC<2:0> = ECH, ECM,
When the external clock fails, the FSCM switches the
ECL, EXTRC) and the clock switch has selected to run
CPU clock to an internal clock source and sets the OSFIF
from the FOSC selection (SCS<1:0> = 00), the condi-
bit of the PIR2 register. The internal clock source is
tion is cleared by performing the following procedure.
determined by the IRCF<3:0> bits in the OSCCON
register. When SCS<1:0> = 00 (Running from FOSC selection)
When the OSFIF bit is set, an interrupt will be generated, SCS<1:0> = 1x:
if the OSFIE bit in the PIE2 register is enabled. The user’s Change the SCS bits in the OSCCON register
firmware in the Interrupt Service Routine (ISR) can then to select the internal oscillator block. This resets
take steps to mitigate the problems that may arise from the OST timer and allows it to operate again.
the failed clock.
OSFIF = 0:
The system clock will continue to be sourced from the
Clear the OSFIF bit in the PIR2 register.
internal clock source until the Fail-Safe condition has
been cleared, see Section5.5.3 “Fail-Safe Condition SCS<1:0> = 00:
Clearing”.

PIC16(L)F1615/9
Change the SCS bits in the OSCCON register When the FSCM is used with external clocks, the OST
to select the FOSC Configuration Word clock is not used and the FSCM will be active as soon as the
selection. Since the OST is not applicable with Reset or wake-up has completed.
external clocks, the clock module will When the FSCM is enabled, the Two-Speed Start-up is
immediately switch to the external clock, and also enabled. Therefore, the device will always be exe-
the Fail-Safe condition will be cleared. cuting code while the OST is operating.
If the Fail-Safe condition still exists, the OSFIF bit will
Note: Due to the wide range of oscillator start-up
again be set by hardware.
times, the Fail-Safe circuit is not active
5.5.4 RESET OR WAKE-UP FROM SLEEP during oscillator start-up (i.e., after exiting
Reset or Sleep).
The FSCM is designed to detect external oscillator or
external clock failures.
When FSCM is used with an external oscillator, the
Oscillator Start-up Timer (OST) count must expire
before the FSCM becomes active. The OST is used
after waking up from Sleep and after any type of Reset.
FIGURE 5-8: FSCM TIMING DIAGRAM
Sample Clock
System Oscillator
Clock Failure
Output
Clock Monitor Output

(Q)
Failure
Detected
OSFIF
Test Test Test
Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.

PIC16(L)F1615/9
5.6 Register Definitions: Oscillator Control
REGISTER 5-1: OSCCON: OSCILLATOR CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 R/W-0/0 R/W-0/0
SPLLEN IRCF<3:0> — SCS<1:0>
bit 7 bit 0
Legend:
bit 7 SPLLEN: Software PLL Enable bit

If PLLEN in Configuration Words = 1:
SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements)
If PLLEN in Configuration Words = 0:
1 = 4x PLL Is enabled
0 = 4x PLL is disabled
bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits
1111 =16 MHz HF
1110 =8 MHz HF
1101 =4 MHz HF
1100 =2 MHz HF
1011 =1 MHz HF
1010 =500 kHz HF(1)
1001 =250 kHz HF(1)
1000 =125 kHz HF(1)
0111 =500 kHz MF (default upon Reset)
0110 =250 kHz MF
0101 =125 kHz MF
0100 =62.5 kHz MF
0011 =31.25 kHz HF(1)
0010 =31.25 kHz MF
000x =31 kHz LF
bit 1-0 SCS<1:0>: System Clock Select bits
1x = Internal oscillator block
01 = Reserved (defaults to internal oscillator block)
00 = Clock determined by FOSC<1:0> in Configuration Words.
Note 1: Duplicate frequency derived from HFINTOSC.

PIC16(L)F1615/9
REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER

U-0 R-0/q U-0 R-0/q R-0/q R-q/q R-0/q R-0/q
— PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional

bit 6 PLLR: 4x PLL Ready bit
1 = 4x PLL is ready
0 = 4x PLL is not ready
bit 5 OSTS: Oscillator Start-Up Timer Status bit
1 = Running from the clock defined by the FOSC<2:0> bits of the Configuration Words
0 = Running from an internal oscillator (FOSC<2:0> = 100)
bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit
1 = HFINTOSC is ready
0 = HFINTOSC is not ready
bit 3 HFIOFL: High-Frequency Internal Oscillator Locked bit
1 = HFINTOSC is at least 2% accurate
0 = HFINTOSC is not 2% accurate
bit 2 MFIOFR: Medium-Frequency Internal Oscillator Ready bit
1 = MFINTOSC is ready
0 = MFINTOSC is not ready
bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit
1 = LFINTOSC is ready
0 = LFINTOSC is not ready
bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit
1 = HFINTOSC is stable
0 = HFINTOSC is not stable

PIC16(L)F1615/9
REGISTER 5-3: OSCTUNE: OSCILLATOR TUNING REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — TUN<5:0>
bit 7 bit 0
Legend:

bit 5-0 TUN<5:0>: Frequency Tuning bits
100000 = Minimum frequency
•
•
•
111111 =
000000 = Oscillator module is running at the factory-calibrated frequency.
000001 =
•
•
•
011110 =
011111 = Maximum frequency
TABLE 5-3: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
OSCCON SPLLEN IRCF<3:0> — SCS<1:0> 81
OSCSTAT — PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 82
OSCTUNE — — TUN<5:0> 83
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
TABLE 5-4: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES

Register
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0
on Page
13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> —
CONFIG1 69
7:0 CP MCLRE PWRTE — — FOSC<2:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

PIC16(L)F1615/9
6.0 RESETS
There are multiple ways to reset this device:
• Power-On Reset (POR)
• Brown-Out Reset (BOR)
• Low-Power Brown-Out Reset (LPBOR)
• MCLR Reset
• WDT Reset
• RESET instruction
• Stack Overflow
• Stack Underflow
• Programming mode exit
To allow VDD to stabilize, an optional power-up timer
can be enabled to extend the Reset time after a BOR
or POR event.
A simplified block diagram of the On-chip Reset Circuit
is shown in Figure 6-1.
FIGURE 6-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

Rev. 10-000 006D
1/22/201 4
ICSP™ Programming Mode Exit

RESET Instruction
Stack Underflow
Stack Overflow
VPP /MCLR MCLRE

Sleep
WDT
Time-out WDT Device
Window Reset
Violation
Power-on
Reset
VDD BOR Active(1)
R
Brown-out Power-up
Reset Timer
LFINTOSC PWRTE
LPBOR
Reset
Note 1: See Table 6-1 for BOR active conditions.

PIC16(L)F1615/9
6.1 Power-On Reset (POR) 6.2 Brown-Out Reset (BOR)
The POR circuit holds the device in Reset until VDD has The BOR circuit holds the device in Reset when VDD
reached an acceptable level for minimum operation. reaches a selectable minimum level. Between the
Slow rising VDD, fast operating speeds or analog POR and BOR, complete voltage range coverage for
performance may require greater than minimum VDD. execution protection can be implemented.
The PWRT, BOR or MCLR features can be used to The Brown-out Reset module has four operating
extend the start-up period until all device operation modes controlled by the BOREN<1:0> bits in Configu-
conditions have been met. ration Words. The four operating modes are:
6.1.1 POWER-UP TIMER (PWRT) • BOR is always on
The Power-up Timer provides a nominal 64 ms time- • BOR is off when in Sleep
out on POR or Brown-out Reset. • BOR is controlled by software
The device is held in Reset as long as PWRT is active. • BOR is always off
The PWRT delay allows additional time for the VDD to Refer to Table 6-1 for more information.
rise to an acceptable level. The Power-up Timer is The Brown-out Reset voltage level is selectable by
enabled by clearing the PWRTE bit in Configuration configuring the BORV bit in Configuration Words.
Words.
A VDD noise rejection filter prevents the BOR from trig-
The Power-up Timer starts after the release of the POR gering on small events. If VDD falls below VBOR for a
and BOR. duration greater than parameter TBORDC, the device
For additional information, refer to Application Note will reset. See Figure 6-2 for more information.
AN607, “Power-up Trouble Shooting” (DS00607).
TABLE 6-1: BOR OPERATING MODES

Instruction Execution upon:
BOREN<1:0> SBOREN Device Mode BOR Mode
Release of POR or Wake-up from Sleep
11 X X Active Waits for BOR ready(1)

(BORRDY = 1)
Awake Active Waits for BOR ready
10 X (BORRDY = 1)
Sleep Disabled
1 Active Waits for BOR ready(1)
X
01 (BORRDY = 1)
0 X Disabled Begins immediately
(BORRDY = x)
00 X X Disabled
Note 1: In these specific cases, “release of POR” and “wake-up from Sleep,” there is no delay in start-up. The BOR
ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR
circuit is forced on by the BOREN<1:0> bits.
6.2.1 BOR IS ALWAYS ON BOR protection is not active during Sleep. The device
wake-up will be delayed until the BOR is ready.
When the BOREN bits of Configuration Words are pro-
grammed to ‘11’, the BOR is always on. The device
6.2.3 BOR CONTROLLED BY SOFTWARE
start-up will be delayed until the BOR is ready and VDD
is higher than the BOR threshold. When the BOREN bits of Configuration Words are
programmed to ‘01’, the BOR is controlled by the
BOR protection is active during Sleep. The BOR does
SBOREN bit of the BORCON register. The device
not delay wake-up from Sleep.
start-up is not delayed by the BOR ready condition or
the VDD level.
6.2.2 BOR IS OFF IN SLEEP
BOR protection begins as soon as the BOR circuit is
When the BOREN bits of Configuration Words are pro-
ready. The status of the BOR circuit is reflected in the
grammed to ‘10’, the BOR is on, except in Sleep. The
BORRDY bit of the BORCON register.
device start-up will be delayed until the BOR is ready
and VDD is higher than the BOR threshold. BOR protection is unchanged by Sleep.

PIC16(L)F1615/9
FIGURE 6-2: BROWN-OUT SITUATIONS
VDD VBOR
Internal
Reset TPWRT(1)
VDD VBOR
Internal < TPWRT

TPWRT(1)
Reset
VDD
VBOR
Internal
Reset TPWRT(1)
TPWRT
Note 1: delay only if PWRTE bit is programmed to ‘0’.
6.3 Register Definitions: BOR Control

REGISTER 6-1: BORCON: BROWN-OUT RESET CONTROL REGISTER
R/W-1/u R/W-0/u U-0 U-0 U-0 U-0 U-0 R-q/u
SBOREN BORFS — — — — — BORRDY
bit 7 bit 0
Legend:
bit 7 SBOREN: Software Brown-Out Reset Enable bit

If BOREN <1:0> in Configuration Words = 01:
1 = BOR Enabled
0 = BOR Disabled
If BOREN <1:0> in Configuration Words  01:
SBOREN is read/write, but has no effect on the BOR
bit 6 BORFS: Brown-Out Reset Fast Start bit(1)
If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control):
1 = Band gap is forced on always (covers sleep/wake-up/operating cases)
0 = Band gap operates normally, and may turn off
If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off)
BORFS is Read/Write, but has no effect.
bit 0 BORRDY: Brown-Out Reset Circuit Ready Status bit
1 = The Brown-out Reset circuit is active
0 = The Brown-out Reset circuit is inactive
Note 1: BOREN<1:0> bits are located in Configuration Words.

PIC16(L)F1615/9
6.4 Low-Power Brown-Out Reset 6.6 Watchdog Timer (WDT) Reset
(LPBOR) The Watchdog Timer generates a Reset if the firmware
The Low-Power Brown-Out Reset (LPBOR) operates does not issue a CLRWDT instruction within the time-out
like the BOR to detect low voltage conditions on the period and the window is open. The TO and PD bits in
VDD pin. When too low of a voltage is detected, the the STATUS register are changed to indicate a WDT
device is held in Reset. When this occurs, a register bit Reset caused by the timer overflowing, and WDTWV bit
(BOR) is changed to indicate that a BOR Reset has in the PCON register is changed to indicate a WDT
occurred. The BOR bit in PCON is used for both BOR Reset caused by a window violation. See
and the LPBOR. Refer to Register 6-2. Section9.0 “Windowed Watchdog Timer (WDT)” for
more information.
The LPBOR voltage threshold (VLPBOR) has a wider
tolerance than the BOR (VBOR), but requires much
less current (LPBOR current) to operate. The LPBOR 6.7 RESET Instruction
is intended for use when the BOR is configured as dis- A RESET instruction will cause a device Reset. The RI
abled (BOREN = 00) or disabled in Sleep mode bit in the PCON register will be set to ‘0’. See Table 6-4
(BOREN = 10). for default conditions after a RESET instruction has
Refer to Figure 6-1 to see how the LPBOR interacts occurred.
with other modules.
6.8 Stack Overflow/Underflow Reset
6.4.1 ENABLING LPBOR
The device can reset when the Stack Overflows or
The LPBOR is controlled by the LPBOR bit of
Underflows. The STKOVF or STKUNF bits of the PCON
Configuration Words. When the device is erased, the
register indicate the Reset condition. These Resets are
LPBOR module defaults to disabled.
enabled by setting the STVREN bit in Configuration
Words. See Section3.5.2 “Overflow/Underflow
6.5 MCLR Reset” for more information.
The MCLR is an optional external input that can reset
the device. The MCLR function is controlled by the 6.9 Programming Mode Exit
MCLRE bit of Configuration Words and the LVP bit of
Upon exit of Programming mode, the device will
Configuration Words (Table 6-2).
behave as if a POR had just occurred.
TABLE 6-2: MCLR CONFIGURATION 6.10 Power-Up Timer

MCLRE LVP MCLR The Power-up Timer optionally delays device execution
0 0 Disabled after a BOR or POR event. This timer is typically used to
allow VDD to stabilize before allowing the device to start
1 0 Enabled
running.
x 1 Enabled
The Power-up Timer is controlled by the PWRTE bit of
Configuration Words.
6.5.1 MCLR ENABLED
When MCLR is enabled and the pin is held low, the 6.11 Start-up Sequence
device is held in Reset. The MCLR pin is connected to
VDD through an internal weak pull-up. Upon the release of a POR or BOR, the following must
The device has a noise filter in the MCLR Reset path. occur before the device will begin executing:
The filter will detect and ignore small pulses. 1. Power-up Timer runs to completion (if enabled).
Note: A Reset does not drive the MCLR pin low. 2. MCLR must be released (if enabled).
The total time-out will vary based on oscillator configu-
6.5.2 MCLR DISABLED ration and Power-up Timer configuration. See
Section5.0 “Oscillator Module” for more information.
When MCLR is disabled, the pin functions as a general
purpose input and the internal weak pull-up is under The Power-up Timer runs independently of MCLR Reset.
software control. See Section12.1 “PORTA Regis- If MCLR is kept low long enough, the Power-up Timer will
ters” for more information. expire. Upon bringing MCLR high, the device will begin
execution after 10 FOSC cycles (see Figure 6-3). This is
useful for testing purposes or to synchronize more than
one device operating in parallel.

PIC16(L)F1615/9
FIGURE 6-3: RESET START-UP SEQUENCE
Rev. 10-000032A
7/30/2013
VDD
Internal POR
TPWRT
Power-up Timer
MCLR
Internal RESET
Int. Oscillator
FOSC
Begin Execution
code execution (1) code execution (1)
Internal Oscillator, PWRTEN = 0 Internal Oscillator, PWRTEN = 1
VDD
Internal POR
TPWRT
Power-up Timer
MCLR
Internal RESET
Ext. Clock (EC)
FOSC
Begin Execution
code execution (1) code execution (1)
External Clock (EC modes), PWRTEN = 0 External Clock (EC modes), PWRTEN = 1
VDD
Internal POR
TPWRT
Power-up Timer
MCLR
Internal RESET
TOST TOST
Osc Start-Up Timer
Ext. Oscillator
FOSC
Begin Execution
code code
execution (1) execution (1)
External Oscillators , PWRTEN = 0, IESO = 0 External Oscillators , PWRTEN = 1, IESO = 0
VDD
Internal POR
TPWRT
Power-up Timer
MCLR
Internal RESET
TOST TOST
Osc Start-Up Timer
Ext. Oscillator
Int. Oscillator
FOSC
Begin Execution code execution (1) code execution (1)
External Oscillators , PWRTEN = 0, IESO = 1 External Oscillators , PWRTEN = 1, IESO = 1
Note 1: Code execution begins 10 FOSC cycles after the FOSC clock is released.

PIC16(L)F1615/9
6.12 Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and
PCON registers are updated to indicate the cause of
the Reset. Table 6-3 and Table 6-4 show the Reset
conditions of these registers.
TABLE 6-3: RESET STATUS BITS AND THEIR SIGNIFICANCE

STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition
0 0 1 1 1 0 x 1 1 Power-on Reset
0 0 1 1 1 0 x 0 x Illegal, TO is set on POR
0 0 1 1 1 0 x x 0 Illegal, PD is set on POR
0 0 u 1 1 u 0 1 1 Brown-out Reset
u u 0 u u u u 0 u WDT Reset
u u u u u u u 0 0 WDT Wake-up from Sleep
u u u u u u u 1 0 Interrupt Wake-up from Sleep
u u u 0 u u u u u MCLR Reset during normal operation
u u u 0 u u u 1 0 MCLR Reset during Sleep
u u u u 0 u u u u RESET Instruction Executed
1 u u u u u u u u Stack Overflow Reset (STVREN = 1)
u 1 u u u u u u u Stack Underflow Reset (STVREN = 1)
TABLE 6-4: RESET CONDITION FOR SPECIAL REGISTERS

Program STATUS PCON
Condition
Counter Register Register
Power-on Reset 0000h ---1 1000 0011 110x
MCLR Reset during normal operation 0000h ---u uuuu uuuu 0uuu
MCLR Reset during Sleep 0000h ---1 0uuu uuuu 0uuu
WDT Reset 0000h ---0 uuuu uuu0 uuuu
WDT Wake-up from Sleep PC + 1 ---0 0uuu uuuu uuuu
Brown-out Reset 0000h ---1 1uuu 00uu 11u0
(1)
Interrupt Wake-up from Sleep PC + 1 ---1 0uuu uuuu uuuu
RESET Instruction Executed 0000h ---u uuuu uuuu u0uu
Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1uuu uuuu
Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1uu uuuu
WDT Window Violation 0000h ---1 uuuu uu0u uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1:When the wake-up is due to an interrupt and the Global Interrupt Enable bit (GIE) is set, the return address is
pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

PIC16(L)F1615/9
6.13 Power Control (PCON) Register
The Power Control (PCON) register contains flag bits
to differentiate between a:
• Power-On Reset (POR)
• Brown-Out Reset (BOR)
• Reset Instruction Reset (RI)
• MCLR Reset (RMCLR)
• Watchdog Timer Reset (RWDT)
• Stack Underflow Reset (STKUNF)
• Stack Overflow Reset (STKOVF)
The PCON register bits are shown in Register 6-2.
6.14 Register Definitions: Power Control
REGISTER 6-2: PCON: POWER CONTROL REGISTER

R/W/HS-0/q R/W/HS-0/q R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u
STKOVF STKUNF WDTWV RWDT RMCLR RI POR BOR
bit 7 bit 0
Legend:
HC = Bit is cleared by hardware HS = Bit is set by hardware
bit 7 STKOVF: Stack Overflow Flag bit

1 = A Stack Overflow occurred
0 = A Stack Overflow has not occurred or cleared by firmware
bit 6 STKUNF: Stack Underflow Flag bit
1 = A Stack Underflow occurred
0 = A Stack Underflow has not occurred or cleared by firmware
bit 5 WDTWV: WDT Window Violation Flag bit
1 = A WDT Window Violation Reset has not occurred or set by firmware
0 = A WDT Window Violation Reset has occurred (a CLRWDT instruction was executed either without
arming the window or outside the window (cleared by hardware)
bit 4 RWDT: Watchdog Timer Reset Flag bit
1 = A Watchdog Timer Reset has not occurred or set by firmware
0 = A Watchdog Timer Reset has occurred (cleared by hardware)
bit 3 RMCLR: MCLR Reset Flag bit
1 = A MCLR Reset has not occurred or set by firmware
0 = A MCLR Reset has occurred (cleared by hardware)
bit 2 RI: RESET Instruction Flag bit
1 = A RESET instruction has not been executed or set by firmware
0 = A RESET instruction has been executed (cleared by hardware)
bit 1 POR: Power-On Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-Out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs)

PIC16(L)F1615/9
TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS
Register
on Page
BORCON SBOREN BORFS — — — — — BORRDY 86

PCON STKOVF STKUNF WDTWV RWDT RMCLR RI POR BOR 90
STATUS — — — TO PD Z DC C 25
WDTCON0 — — WDTPS<4:0> SEN 116
Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
TABLE 6-6: SUMMARY OF CONFIGURATION WORD WITH RESETS

Register
on Page

CONFIG1 69
13:8 — — LVP DEBUG LPBOR BORV STVREN PLLEN
CONFIG2 68
7:0 ZCD — — — — PPS1WAY WRT<1:0>
13:8 — — WDTCCS<2:0> WDTCWS<2:0>
CONFIG3 69
7:0 — WDTE<1:0> WDTCPS<4:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.

PIC16(L)F1615/9
7.0 INTERRUPTS
The interrupt feature allows certain events to preempt
normal program flow. Firmware is used to determine
the source of the interrupt and act accordingly. Some
interrupts can be configured to wake the MCU from
Sleep mode.
This chapter contains the following information for
Interrupts:
• Operation
• Interrupt Latency
• Interrupts During Sleep
• INT Pin
• Automatic Context Saving
Many peripherals produce interrupts. Refer to the
corresponding chapters for details.
A block diagram of the interrupt logic is shown in
Figure 7-1.
FIGURE 7-1: Interrupt Logic

Rev. 10-000010A
1/13/2014
TMR0IF Wake-up
TMR0IE (If in Sleep mode)
INTF
Peripheral Interrupts INTE
(TMR1IF) PIR1<0>
IOCIF
(TMR1IE) PIE1<0> Interrupt
IOCIE to CPU
PEIE
PIRn<7>
GIE
PIEn<7>

PIC16(L)F1615/9
7.1 Operation 7.2 Interrupt Latency
Interrupts are disabled upon any device Reset. They Interrupt latency is defined as the time from when the
are enabled by setting the following bits: interrupt event occurs to the time code execution at the
• GIE bit of the INTCON register interrupt vector begins. The latency for synchronous
interrupts is three or four instruction cycles. For
• Interrupt Enable bit(s) for the specific interrupt
asynchronous interrupts, the latency is three to five
event(s)
instruction cycles, depending on when the interrupt
• PEIE bit of the INTCON register (if the Interrupt occurs. See Figure 7-2 and Figure 7-3 for more details.
Enable bit of the interrupt event is contained in the
PIE1, PIE2 and PIE3 registers)
The INTCON, PIR1, PIR2 and PIR3 registers record
individual interrupts via interrupt flag bits. Interrupt flag
bits will be set, regardless of the status of the GIE, PEIE
and individual interrupt enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
• Current prefetched instruction is flushed
• GIE bit is cleared
• Current Program Counter (PC) is pushed onto the
stack
• Critical registers are automatically saved to the
shadow registers (See “Section7.5 “Automatic
Context Saving”.”)
• PC is loaded with the interrupt vector 0004h
The firmware within the Interrupt Service Routine (ISR)
should determine the source of the interrupt by polling
the interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack, restoring the saved
context from the shadow registers and setting the GIE
bit.
For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.
Note 1: Individual interrupt flag bits are set,
regardless of the state of any other
enable bits.
2: All interrupts will be ignored while the GIE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.

PIC16(L)F1615/9
FIGURE 7-2: INTERRUPT LATENCY
Fosc
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKR Interrupt Sampled

during Q1
Interrupt
GIE
PC PC-1 PC PC+1 0004h 0005h
Execute 1-Cycle Instruction at PC Inst(PC) NOP NOP Inst(0004h)
Interrupt
GIE
PC+1/FSR New PC/

PC PC-1 PC 0004h 0005h
ADDR PC+1
Execute 2-Cycle Instruction at PC Inst(PC) NOP NOP Inst(0004h)
Interrupt
GIE
PC PC-1 PC FSR ADDR PC+1 PC+2 0004h 0005h
Execute 3-Cycle Instruction at PC INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h)
Interrupt
GIE
PC PC-1 PC FSR ADDR PC+1 PC+2 0004h 0005h
Execute 3-Cycle Instruction at PC INST(PC) NOP NOP NOP NOP Inst(0004h)

PIC16(L)F1615/9
FIGURE 7-3: INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
FOSC
CLKOUT
(3)
INT pin
(1)
(1)
INTF (4) Interrupt Latency (2)
GIE
INSTRUCTION FLOW
PC PC PC + 1 PC + 1 0004h 0005h
Instruction
Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h)
Instruction Forced NOP Forced NOP Inst (0004h)

Inst (PC – 1) Inst (PC)
Executed
Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: For minimum width of INT pulse, refer to AC specifications in Section35.0 “Electrical Specifications”.
4: INTF is enabled to be set any time during the Q4-Q1 cycles.

PIC16(L)F1615/9
7.3 Interrupts During Sleep
Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate Interrupt Enable bit(s) set
prior to entering Sleep.
On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEP instruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to Section8.0 “Power-
Down Mode (Sleep)” for more details.
7.4 INT Pin

The INT pin can be used to generate an asynchronous
edge-triggered interrupt. This interrupt is enabled by
setting the INTE bit of the INTCON register. The
INTEDG bit of the OPTION_REG register determines on
which edge the interrupt will occur. When the INTEDG
bit is set, the rising edge will cause the interrupt. When
the INTEDG bit is clear, the falling edge will cause the
interrupt. The INTF bit of the INTCON register will be set
when a valid edge appears on the INT pin. If the GIE and
INTE bits are also set, the processor will redirect
program execution to the interrupt vector.
7.5 Automatic Context Saving

Upon entering an interrupt, the return PC address is
saved on the stack. Additionally, the following registers
are automatically saved in the shadow registers:
• W register
• STATUS register (except for TO and PD)
• BSR register
• FSR registers
• PCLATH register
Upon exiting the Interrupt Service Routine, these regis-
ters are automatically restored. Any modifications to
these registers during the ISR will be lost. If modifica-
tions to any of these registers are desired, the corre-
sponding shadow register should be modified and the
value will be restored when exiting the ISR. The
shadow registers are available in Bank 31 and are
readable and writable. Depending on the user’s appli-
cation, other registers may also need to be saved.

PIC16(L)F1615/9
7.6 Register Definitions: Interrupt Control
REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0
GIE(1) PEIE(2) TMR0IE INTE IOCIE TMR0IF INTF IOCIF(3)
bit 7 bit 0
Legend:
bit 7 GIE: Global Interrupt Enable bit(1)

1 = Enables all active interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit(2)
1 = Enables all active peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4 INTE: INT External Interrupt Enable bit
1 = Enables the INT external interrupt
0 = Disables the INT external interrupt
bit 3 IOCIE: Interrupt-on-Change Enable bit
1 = Enables the interrupt-on-change
0 = Disables the interrupt-on-change
bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed
0 = TMR0 register did not overflow
bit 1 INTF: INT External Interrupt Flag bit
1 = The INT external interrupt occurred
0 = The INT external interrupt did not occur
bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit(3)
1 = When at least one of the interrupt-on-change pins changed state
0 = None of the interrupt-on-change pins have changed state
Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the Global Interrupt Enable bit, GIE of the INTCON register. User software should ensure the
appropriate interrupt flag bits are clear prior to enabling an interrupt.
2: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
3: The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCxF registers
have been cleared by software.

PIC16(L)F1615/9
REGISTER 7-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE
bit 7 bit 0
Legend:
bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit

1 = Enables the Timer1 gate acquisition interrupt
0 = Disables the Timer1 gate acquisition interrupt
bit 6 ADIE: Analog-to-Digital Converter (ADC) Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 5 RCIE: EUSART Receive Interrupt Enable bit
1 = Enables the EUSART receive interrupt
0 = Disables the EUSART receive interrupt
bit 4 TXIE: EUSART Transmit Interrupt Enable bit
1 = Enables the EUSART transmit interrupt
0 = Disables the EUSART transmit interrupt
bit 3 SSP1IE: Synchronous Serial Port (MSSP) Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt
1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt
Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

PIC16(L)F1615/9

R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
OSFIE C2IE C1IE — BCL1IE TMR6IE TMR4IE CCP2IE
bit 7 bit 0
Legend:
bit 7 OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enables the Oscillator Fail interrupt
0 = Disables the Oscillator Fail interrupt
bit 6 C2IE: Comparator C2 Interrupt Enable bit
1 = Enables the Comparator C2 interrupt
0 = Disables the Comparator C2 interrupt
bit 5 C1IE: Comparator C1 Interrupt Enable bit
1 = Enables the Comparator C1 interrupt
0 = Disables the Comparator C1 interrupt
bit 3 BCL1IE: MSSP Bus Collision Interrupt Enable bit
1 = Enables the MSSP Bus Collision Interrupt
0 = Disables the MSSP Bus Collision Interrupt
bit 0 CCP2IE: CCP2 Interrupt Enable bit
1 = The CCP2 interrupt is enabled
0 = The CCP2 interrupt is not enabled
Note 1: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.

PIC16(L)F1615/9

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — CWGIE ZCDIE CLC4IE CLC3IE CLC2IE CLC1IE
bit 7 bit 0
Legend:

bit 5 CWGIE: Complementary Waveform Generator (CWG) Interrupt Enable bit
1 = Enables the CWG interrupt
0 = Disables the CWG interrupt
bit 4 ZCDIE: Zero-Cross Detection (ZCD) Interrupt Enable bit
1 = Enables the ZCD interrupt
0 = Disables the ZCD interrupt
bit 3 CLC4IE: Configurable Logic Block 4 Interrupt Enable bit
1 = Enables the CLC 4 interrupt
0 = Disables the CLC 4 interrupt


PIC16(L)F1615/9

SCANIE CRCIE SMT2PWAIE SMT2PRAIE SMT2IE SMT1PWAIE SMT1PRAIE SMT1IE
bit 7 bit 0
Legend:
bit 7 SCANIE: Scanner Interrupt Enable bit

1 = Enables the scanner interrupt
0 = Disables the scanner interrupt
bit 6 CRCIE: CRC Interrupt Enable bit
1 = Enables the CRC interrupt
0 = Disables the CRC interrupt
bit 5 SMT2PWAIE: SMT2 Pulse Width Acquisition Interrupt Enable bit
1 = Enables the SMT2 acquisition interrupt
0 = Disables the SMT2 acquisition interrupt
bit 4 SMT2PRAIE: SMT2 Period Acquisition Interrupt Enable bit
bit 3 SMT2IE: SMT2 Match Interrupt Enable bit
1 = Enables the SMT2 period match interrupt
0 = Disables the SMT2 period match interrupt
bit 2 SMT1PWAIE: SMT1 Pulse Width Acquisition Interrupt Enable bit
bit 1 SMT1PRAIE: SMT1 Period Acquisition Interrupt Enable bit
bit 0 SMT1IE: SMT1 Match Interrupt Enable bit
1 = Enables the SMT1 period match interrupt
0 = Disables the SMT1 period match interrupt


PIC16(L)F1615/9

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
—
TMR3GIE TMR3IE TMR5GIE TMR5IE AT1IE PID1EIE PID1DIE
bit 7 bit 0
Legend:

1 = Enables the Timer3 Gate interrupt
0 = Disables the Timer3 Gate interrupt
1 = Enables the Timer5 Gate interrupt
0 = Disables the Timer5 Gate interrupt
bit 2 AT1IE: Angular Timer 1 Interrupt Enable bit
1 = Enables the Angular Timer 1 interrupt
0 = Disables the Angular Timer 1 interrupt
bit 1 PID1EIE: PID Error Interrupt Enable bit
1 = Enables the PID error interrupt
0 = Disables the PID error interrupt
bit 0 PID1DIE: PID Interrupt Enable bit
1 = Enables the PID interrupt
0 = Disables the PID interrupt


PIC16(L)F1615/9
REGISTER 7-7: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

TMR1GIE ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
Legend:
bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending
bit 6 ADIF: ADC Interrupt Flag bit
bit 5 RCIF: EUSART Receive Interrupt Flag bit
bit 4 TXIF: EUSART Transmit Interrupt Flag bit
bit 3 SSP1IF: Synchronous Serial Port (MSSP) Interrupt Flag bit
bit 2 CCP1IF: CCP1 Interrupt Flag bit
bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit
Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE of the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.

PIC16(L)F1615/9

R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
OSFIF C2IF C1IF — BCL1IF TMR6IF TMR4IF CCP2IF
bit 7 bit 0
Legend:
bit 7 OSFIF: Oscillator Fail Interrupt Flag bit

bit 6 C2IF: Comparator C2 Interrupt Flag bit
bit 5 C1IF: Comparator C1 Interrupt Flag bit
bit 3 BCL1IF: MSSP Bus Collision Interrupt Flag bit
bit 0 CCP2IF: CCP2 Interrupt Flag bit

Enable bit, GIE of the INTCON register.
User software should ensure the

PIC16(L)F1615/9

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — CWGIF ZCDIF CLC4IF CLC3IF CLC2IF CLC1IF
bit 7 bit 0
Legend:

bit 5 CWGIF: CWG Interrupt Flag bit
bit 4 ZCDIF: ZCD Interrupt Flag bit
bit 3 CLC4IF: Configurable Logic Block 4 Interrupt Flag bit


PIC16(L)F1615/9

SCANIF CRCIF SMT2PWAIF SMT2PRAIF SMT2IF SMT1PWAIF SMT1PRAIF SMT1IF
bit 7 bit 0
Legend:
bit 7 SCANIF: Scanner Interrupt Flag bit

bit 6 CRCIF: CRC Interrupt Flag bit
bit 5 SMT2PWAIF: SMT2 Pulse Width Acquisition Interrupt Flag bit
bit 4 SMT2PRAIF: SMT2 Period Acquisition Interrupt Flag bit
bit 3 SMT2IF: SMT2 Match Interrupt Flag bit
bit 2 SMT1PWAIF: SMT1 Pulse Width Acquisition Interrupt Flag bit
bit 1 SMT1PRAIF: SMT1 Period Acquisition Interrupt Flag bit
bit 0 SMT1IF: SMT1 Match Interrupt Flag bit


PIC16(L)F1615/9

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
—
TMR3GIF TMR3IF TMR5GIF TMR5IF AT1IF PID1EIF PID1DIF
bit 7 bit 0
Legend:

bit 2 AT1IF: Angular Timer 1 Interrupt Flag bit
bit 1 PID1EIF: PID Error Interrupt Flag bit
bit 0 PID1DIF: PID Interrupt Flag bit

Interrupt Enable bit, GIE of the INTCON
register. User software should ensure the

PIC16(L)F1615/9
TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Register
on Page
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 97

OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 223
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 98
PIE2 OSFIE C2IE C1IE — BCL1IE TMR6IE TMR4IE CCP2IE 107
PIE3 — — CWGIE ZCDIE CLC4IE CLC3IE CLC2IE CLC1IE 108
PIE4 SCANIE CRCIE SMT2PWAIE SMT2PRAIE SMT2IE SMT1PWAIE SMT1PRAIE SMT1IF 101
PIE5 TMR3GIE TMR3IE TMR5GIE TMR5IE — AT1IE PID1EIE PID1DIE 102
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 103
PIR2 OSFIF C2IF C1IF — BCL1IF TMR6IF TMR4IF CCP2IF 112
PIR3 — — CWGIF ZCDIF CLC4IF CLC3IF CLC2IF CLC1IF 113
PIR4 SCANIF CRCIF SMT2PWAIF SMT2PRAIF SMT2IF SMT1PWAIF SMT1PRAIF SMT1IF 106
PIR5 TMR3GIF TMR3IF TMR5GIF TMR5IF — AT1IF PID1EIF PID1DIF 107
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupts.

PIC16(L)F1615/9
8.0 POWER-DOWN MODE (SLEEP) The first three events will cause a device Reset. The
last three events are considered a continuation of pro-
The Power-Down mode is entered by executing a gram execution. To determine whether a device Reset
SLEEP instruction. or wake-up event occurred, refer to Section
Upon entering Sleep mode, the following conditions exist: 6.12 “Determining the Cause of a Reset”.
1. WDT will be cleared but keeps running, if When the SLEEP instruction is being executed, the next
enabled for operation during Sleep. instruction (PC + 1) is prefetched. For the device to
2. PD bit of the STATUS register is cleared. wake-up through an interrupt event, the corresponding
3. TO bit of the STATUS register is set. interrupt enable bit must be enabled. Wake-up will
occur regardless of the state of the GIE bit. If the GIE
4. CPU clock is disabled.
bit is disabled, the device continues execution at the
5. 31 kHz LFINTOSC is unaffected and peripherals
instruction after the SLEEP instruction. If the GIE bit is
that operate from it may continue operation in
enabled, the device executes the instruction after the
Sleep.
SLEEP instruction, the device will then call the Interrupt
6. Timer1 and peripherals that operate from Service Routine. In cases where the execution of the
Timer1 continue operation in Sleep when the instruction following SLEEP is not desirable, the user
Timer1 clock source selected is: should have a NOP after the SLEEP instruction.
• LFINTOSC
The WDT is cleared when the device wakes up from
• T1CKI
Sleep, regardless of the source of wake-up.
• Timer1 oscillator
7. ADC is unaffected, if the dedicated FRC oscillator 8.1.1 WAKE-UP USING INTERRUPTS
is selected.
When global interrupts are disabled (GIE cleared) and
8. I/O ports maintain the status they had before
any interrupt source has both its interrupt enable bit
SLEEP was executed (driving high, low or high-
and interrupt flag bit set, one of the following will occur:
impedance).
9. Resets other than WDT are not affected by • If the interrupt occurs before the execution of a
Sleep mode. SLEEP instruction
Refer to individual chapters for more details on - SLEEP instruction will execute as a NOP
peripheral operation during Sleep. - WDT and WDT prescaler will not be cleared
To minimize current consumption, the following - TO bit of the STATUS register will not be set
conditions should be considered: - PD bit of the STATUS register will not be
• I/O pins should not be floating cleared
• External circuitry sinking current from I/O pins • If the interrupt occurs during or after the execu-
• Internal circuitry sourcing current from I/O pins tion of a SLEEP instruction
• Current draw from pins with internal weak pull-ups - SLEEP instruction will be completely
• Modules using 31 kHz LFINTOSC executed
• CWG modules using HFINTOSC - Device will immediately wake-up from Sleep
I/O pins that are high-impedance inputs should be - WDT and WDT prescaler will be cleared
pulled to VDD or VSS externally to avoid switching - TO bit of the STATUS register will be set
currents caused by floating inputs. - PD bit of the STATUS register will be cleared
Examples of internal circuitry that might be sourcing Even if the flag bits were checked before executing a
current include the FVR module. See Section SLEEP instruction, it may be possible for flag bits to
15.0 “Fixed Voltage Reference (FVR)” for more become set before the SLEEP instruction completes. To
information on this module. determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
8.1 Wake-up from Sleep was executed as a NOP.
The device can wake-up from Sleep through one of the
following events:
1. External Reset input on MCLR pin, if enabled
2. BOR Reset, if enabled
3. POR Reset
4. Watchdog Timer, if enabled
5. Any external interrupt
6. Interrupts by peripherals capable of running
during Sleep (see individual peripheral for more
information)

PIC16(L)F1615/9
FIGURE 8-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKIN(1)
CLKOUT(2) T1OSC(3)
Interrupt flag Interrupt Latency (4)
GIE bit
(INTCON reg.) Processor in
Sleep
Instruction Flow
PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h
Instruction Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h)
Fetched Inst(PC) = Sleep
Instruction Sleep Inst(PC + 1) Forced NOP Forced NOP
Executed Inst(PC - 1) Inst(0004h)
Note 1: External clock. High, Medium, Low mode assumed.

2: CLKOUT is shown here for timing reference.
3: T1OSC; See Section 35.0 “Electrical Specifications”.
4: GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
8.2 Low-Power Sleep Mode 8.2.2 PERIPHERAL USAGE IN SLEEP

This device contains an internal Low Dropout (LDO) Some peripherals that can operate in Sleep mode will
voltage regulator, which allows the device I/O pins to not operate properly with the Low-Power Sleep mode
operate at voltages up to 5.5V while the internal device selected. The LDO will remain in the Normal-Power
logic operates at a lower voltage. The LDO and its mode when those peripherals are enabled. The Low-
associated reference circuitry must remain active when Power Sleep mode is intended for use with these
the device is in Sleep mode. peripherals:
Low-Power Sleep mode allows the user to optimize the • Brown-Out Reset (BOR)
operating current in Sleep. Low-Power Sleep mode can • Watchdog Timer (WDT)
be selected by setting the VREGPM bit of the • External interrupt pin/Interrupt-on-change pins
VREGCON register, putting the LDO and reference • Timer1 (with external clock source)
circuitry in a low-power state whenever the device is in
Sleep. The Complementary Waveform Generator (CWG) can
utilize the HFINTOSC oscillator as either a clock
8.2.1 SLEEP CURRENT VS. WAKE-UP source or as an input source. Under certain condi-
TIME tions, when the HFINTOSC is selected for use with the
CWG modules, the HFINTOSC will remain active
In the Default Operating mode, the LDO and reference during Sleep. This will have a direct effect on the
circuitry remain in the normal configuration while in Sleep mode current.
Sleep. The device is able to exit Sleep mode quickly
since all circuits remain active. In Low-Power Sleep Please refer to sections Section 28.11 “Operation
mode, when waking up from Sleep, an extra delay time During Sleep” for more information.
is required for these circuits to return to the normal con-
figuration and stabilize.
Note: The PIC16LF1615/9 does not have a con-
The Low-Power Sleep mode is beneficial for applica- figurable Low-Power Sleep mode.
tions that stay in Sleep mode for long periods of time. PIC16LF1615/9 is an unregulated device
The Normal mode is beneficial for applications that and is always in the lowest power state
need to wake from Sleep quickly and frequently. when in Sleep, with no wake-up time pen-
alty. This device has a lower maximum
VDD and I/O voltage than the
PIC16F1615/9. See Section
35.0 “Electrical Specifications” for
more information.

PIC16(L)F1615/9
8.3 Register Definitions: Voltage Regulator Control
REGISTER 8-1: VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1)

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1
— — — — — — VREGPM Reserved
bit 7 bit 0
Legend:

bit 1 VREGPM: Voltage Regulator Power Mode Selection bit
1 = Low-Power Sleep mode enabled in Sleep(2)
Draws lowest current in Sleep, slower wake-up
0 = Normal Power mode enabled in Sleep(2)
Draws higher current in Sleep, faster wake-up
bit 0 Reserved: Read as ‘1’. Maintain this bit set.

2: See Section 35.0 “Electrical Specifications”.
TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE

Register on
Page

IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 180
IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 180
IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 180
IOCCP IOCCP7(1) IOCCP6(1) IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 180
IOCCN IOCCN7(1) IOCCN6(1) IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 180
IOCCF IOCCF7(1) IOCCF6(1) IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 180
PIE4 SCANIE CRCIE SMT2PWAIE SMT2PRAIE SMT2IE SMT1PWAIE SMT1PRAIE SMT1IF 101
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-Down mode.
Note 1: PIC16(L)F1619 only.

PIC16(L)F1615/9
9.0 WINDOWED WATCHDOG
TIMER (WDT)
The Watchdog Timer (WDT) is a system timer that
generates a Reset if the firmware does not issue a
CLRWDT instruction within the time-out period. The
Watchdog Timer is typically used to recover the system
from unexpected events. The Windowed Watchdog
Timer (WDT) differs in that CLRWDT instructions are
only accepted when they are performed within a
specific window during the time-out period.
The WDT has the following features:
• Selectable clock source
• Multiple operating modes
- WDT is always on
- WDT is off when in Sleep
- WDT is controlled by software
- WDT is always off
• Configurable time-out period is from 1 ms to 256
seconds (nominal)
• Configurable window size from 12.5 to 100
percent of the time-out period
• Multiple Reset conditions
• Operation during Sleep

PIC16(L)F1615/9
FIGURE 9-1: WATCHDOG TIMER BLOCK DIAGRAM
Rev. 10-000 162A

1/2/201 4
WWDT
Armed
WDT
Window
Violation
Window Closed
Window
Comparator
CLRWDT Sizes
WINDOW
RESET
Reserved 111
Reserved 110
Reserved 101
R
Reserved 100 18-bit Prescale
Reserved 011 Counter
E
626& 010
MFINTOSC/16 001
LFINTOSC 000
CS
PS
R
5-bit Overflow
WDT Time-out
WDT Counter Latch
WDTE<1:0> = 01
SEN
WDTE<1:0> = 11
WDTE<1:0> = 10
Sleep

PIC16(L)F1615/9
9.1 Independent Clock Source 9.4 Watchdog Window
The WDT can derive its time base from either the 31 The Watchdog Timer has an optional Windowed mode
kHz LFINTOSC or 31.25 kHz MFINTOSC internal that is controlled by the WDTCWS<2:0> Configuration
oscillators, depending on the value of either the bits and WINDOW<2:0> bits of the WDTCON1 register.
WDTCCS<2:0> configuration bits or the WDTCS<2:0> In the Windowed mode, the CLRWDT instruction must
bits of WDTCON1. Time intervals in this chapter are occur within the allowed window of the WDT period.
based on a minimum nominal interval of 1 ms. See Any CLRWDT instruction that occurs outside of this win-
Section35.0 “Electrical Specifications” for dow will trigger a window violation and will cause a
LFINTOSC and MFINTOSC tolerances. WDT Reset, similar to a WDT time out. See Figure 9-2
for an example.
9.2 WDT Operating Modes The window size is controlled by the WDTCWS<2:0>
Configuration bits, or the WINDOW<2:0> bits of
The Watchdog Timer module has four operating modes
WDTCON1, if WDTCWS<2:0> = 111.
controlled by the WDTE<1:0> bits in Configuration
Words. See Table 9-1. In the event of a window violation, a Reset will be
generated and the WDTWV bit of the PCON register
9.2.1 WDT IS ALWAYS ON will be cleared. This bit is set by a POR or can be set in
When the WDTE bits of Configuration Words are set to firmware.
‘11’, the WDT is always on.
9.5 Clearing the WDT
WDT protection is active during Sleep.
The WDT is cleared when any of the following condi-
9.2.2 WDT IS OFF IN SLEEP tions occur:
When the WDTE bits of Configuration Words are set to • Any Reset
‘10’, the WDT is on, except in Sleep. • Valid CLRWDT instruction is executed
WDT protection is not active during Sleep. • Device enters Sleep
• Device wakes up from Sleep
9.2.3 WDT CONTROLLED BY SOFTWARE
• WDT is disabled
When the WDTE bits of Configuration Words are set to
• Oscillator Start-up Timer (OST) is running
‘01’, the WDT is controlled by the SEN bit of the
WDTCON0 register. • Any write to the WDTCON0 or WDTCON1 registers
WDT protection is unchanged by Sleep. See Table 9-1 9.5.1 CLRWDT CONSIDERATIONS
for more details. (WINDOWED MODE)
TABLE 9-1: WDT OPERATING MODES When in Windowed mode, the WDT must be armed
before a CLRWDT instruction will clear the timer. This is
Device WDT performed by reading the WDTCON0 register. Execut-
WDTE<1:0> SEN
Mode Mode ing a CLRWDT instruction without performing such an
arming action will trigger a window violation.
11 X X Active
See Table 9-2 for more information.
Awake Active
10 X
Sleep Disabled 9.6 Operation During Sleep
1 X Active When the device enters Sleep, the WDT is cleared. If
01 the WDT is enabled during Sleep, the WDT resumes
0 X Disabled
counting. When the device exits Sleep, the WDT is
00 X X Disabled cleared again.
The WDT remains clear until the OST, if enabled, com-
9.3 Time-Out Period pletes. See Section5.0 “Oscillator Module” for more
information on the OST.
The WDTPS bits of the WDTCON0 register set the
time-out period from 1 ms to 256 seconds (nominal). When a WDT time-out occurs while the device is in
After a Reset, the default time-out period is two Sleep, no Reset is generated. Instead, the device
seconds. wakes up and resumes operation. The TO and PD bits
in the STATUS register are changed to indicate the
event. The RWDT bit in the PCON register can also be
used. See Section3.0 “Memory Organization” for
more information.

PIC16(L)F1615/9
TABLE 9-2: WDT CLEARING CONDITIONS

Conditions WDT
WDTE<1:0> = 00
WDTE<1:0> = 01 and SEN = 0
WDTE<1:0> = 10 and enter Sleep
Cleared
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK
Change INTOSC divider (IRCF bits) Unaffected
FIGURE 9-2: WINDOW PERIOD AND DELAY
Rev. 10-000163A
8/15/2016
CLRWDT Instruction
(or other WDT Reset)
Window Period
Window Closed Window Open
Time-out Event
Window Delay
(window violation can occur)

PIC16(L)F1615/9
9.7 Register Definitions: Windowed Watchdog Timer Control
REGISTER 9-1: WDTCON0: WATCHDOG TIMER CONTROL REGISTER 0

U-0 U-0 R/W(3)-q/q(2) R/W(3)-q/q(2) R/W(3)-q/q(2) R/W(3)-q/q(2) R/W(3)-q/q(2) R/W-0/0
— — WDTPS<4:0>(1) SEN
bit 7 bit 0
Legend:

bit 5-1 WDTPS<4:0>: Watchdog Timer Prescale Select bits(1)
Bit Value = Prescale Rate
11111 = Reserved. Results in minimum interval (1:32)
•
•
•
10011 = Reserved. Results in minimum interval (1:32)
10010 = 1:8388608 (223) (Interval 256s nominal)

01011 = 1:65536 (Interval 2s nominal) (Reset value)
01010 = 1:32768 (Interval 1s nominal)
01001 = 1:16384 (Interval 512 ms nominal)
bit 0 SEN: Software Enable/Disable for Watchdog Timer bit
If WDTE<1:0> = 1x:
If WDTE<1:0> = 01:
1 = WDT is turned on
0 = WDT is turned off
If WDTE<1:0> = 00:
Note 1: Times are approximate. WDT time is based on 31 kHz LFINTOSC.

2: When WDTCPS <4:0> in CONFIG3 = 11111, the Reset value of WDTPS<4:0> is 01011. Otherwise, the
Reset value of WDTPS<4:0> is equal to WDTCPS<4:0> in CONFIG3.
3: When WDTCPS <4:0> in CONFIG3 ≠ 11111, these bits are read-only.

PIC16(L)F1615/9
REGISTER 9-2: WDTCON1: WATCHDOG TIMER CONTROL REGISTER 1

U-0 R/W(3)-q/q(1) R/W(3)-q/q(1) R/W(3)-q/q(1) U-0 R/W(4)-q/q(2) R/W(4)-q/q(2) R/W(4)-q/q(2)
— —
WDTCS<2:0> WINDOW<2:0>
bit 7 bit 0
Legend:

bit 6-4 WDTCS<2:0>: Watchdog Timer Clock Select bits
111 = Reserved
•
•
•
010 = Reserved
001 = MFINTOSC 31.25 kHz
000 = LFINTOSC 31 kHz
bit 2-0 WINDOW<2:0>: Watchdog Timer Window Select bits
Window delay Window opening

WINDOW<2:0>
Percent of time Percent of time
111 N/A 100
110 12.5 87.5
101 25 75
100 37.5 62.5
011 50 50
010 62.5 37.5
001 75 25
000 87.5 12.5
Note 1: If WDTCCS <2:0> in CONFIG3 = 111, the Reset value of WDTCS<2:0> is 000.
2: The Reset value of WINDOW<2:0> is determined by the value of WDTCWS<2:0> in the CONFIG3 register.
3: If WDTCCS<2:0> in CONFIG3 ≠ 111, these bits are read-only.
4: If WDTCWS<2:0> in CONFIG3 ≠ 111, these bits are read-only.

PIC16(L)F1615/9
REGISTER 9-3: WDTPSL: WDT PRESCALE SELECT LOW BYTE REGISTER (READ ONLY)
R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0
(1)
PSCNT<7:0>
bit 7 bit 0
Legend:
bit 7-0 PSCNT<7:0>: Prescale Select Low Byte bits(1)
Note 1: The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits of the WDTTMR
registers. PSCNT<17:0> is intended for debug operations and should be read during normal operation.
REGISTER 9-4: WDTPSH: WDT PRESCALE SELECT HIGH BYTE REGISTER (READ ONLY)
R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0
PSCNT<15:8>(1)
bit 7 bit 0
Legend:
bit 7-0 PSCNT<15:8>: Prescale Select High Byte bits(1)
REGISTER 9-5: WDTTMR: WDT TIMER REGISTER (READ ONLY)

R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0
WDTTMR<3:0> STATE PSCNT<17:16>(1)
bit 7 bit 0
Legend:
bit 7-3 WDTTMR<4:0>: Watchdog Timer Value

bit 2 STATE: WDT Armed Status bit
1 = WDT is armed
0 = WDT is not armed
bit 1-0 PSCNT<17:16>: Prescale Select Upper Byte bits(1)

PIC16(L)F1615/9
TABLE 9-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
Register
on Page
OSCCON SPLLEN IRCF<3:0> — SCS<1:0> 81
PCON STKOVF STKUNF WDTWV RWDT RMCLR RI POR BOR 90
WDTCON1 — WDTCS<2:0> — WINDOW<2:0> 116
WDTPSL PSCNT<7:0> 116
WDTPSH PSCNT<15:8> 116
WDTTMR — WDTTMR<4:0> STATE PSCNT<17:16> 116
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer.
TABLE 9-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER

Register
on Page

CONFIG1 69
13:8 — — WDTCCS<2:0> WDTCWS<2:0>
CONFIG3 69
7:0 — WDTE<1:0> WDTCPS<4:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.

PIC16(L)F1615/9
10.0 FLASH PROGRAM MEMORY Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
CONTROL software. They are cleared by hardware at completion
The Flash program memory is readable and writable of the read or write operation. The inability to clear the
during normal operation over the full VDD range. WR bit in software prevents the accidental, premature
Program memory is indirectly addressed using Special termination of a write operation.
Function Registers (SFRs). The SFRs used to access The WREN bit, when set, will allow a write operation to
program memory are: occur. On power-up, the WREN bit is clear. The
• PMCON1 WRERR bit is set when a write operation is interrupted
• PMCON2 by a Reset during normal operation. In these situations,
following Reset, the user can check the WRERR bit
• PMDATL
and execute the appropriate error handling routine.
• PMDATH
The PMCON2 register is a write-only register. Attempting
• PMADRL
to read the PMCON2 register will return all ‘0’s.
• PMADRH
To enable writes to the program memory, a specific
When accessing the program memory, the pattern (the unlock sequence), must be written to the
PMDATH:PMDATL register pair forms a 2-byte word PMCON2 register. The required unlock sequence
that holds the 14-bit data for read/write, and the prevents inadvertent writes to the program memory
PMADRH:PMADRL register pair forms a 2-byte word write latches and Flash program memory.
that holds the 15-bit address of the program memory
location being read.
10.2 Flash Program Memory Overview
The write time is controlled by an on-chip timer. The write/
erase voltages are generated by an on-chip charge pump It is important to understand the Flash program memory
rated to operate over the operating voltage range of the structure for erase and programming operations. Flash
device. program memory is arranged in rows. A row consists of
a fixed number of 14-bit program memory words. A row
The Flash program memory can be protected in two
is the minimum size that can be erased by user software.
ways; by code protection (CP bit in Configuration Words)
and write protection (WRT<1:0> bits in Configuration After a row has been erased, the user can reprogram
Words). all or a portion of this row. Data to be written into the
program memory row is written to 14-bit wide data write
Code protection (CP = 0)(1), disables access, reading
latches. These write latches are not directly accessible
and writing, to the Flash program memory via external
to the user, but may be loaded via sequential writes to
device programmers. Code protection does not affect
the PMDATH:PMDATL register pair.
the self-write and erase functionality. Code protection
can only be reset by a device programmer performing Note: If the user wants to modify only a portion
a Bulk Erase to the device, clearing all Flash program of a previously programmed row, then the
memory, Configuration bits and User IDs. contents of the entire row must be read
Write protection prohibits self-write and erase to a and saved in RAM prior to the erase.
portion or all of the Flash program memory, as defined Then, new data and retained data can be
by the bits WRT<1:0>. Write protection does not affect written into the write latches to reprogram
a device programmers ability to read, write or erase the the row of Flash program memory. How-
device. ever, any unprogrammed locations can be
written without first erasing the row. In this
Note 1: Code protection of the entire Flash case, it is not necessary to save and
program memory array is enabled by rewrite the other previously programmed
clearing the CP bit of Configuration Words. locations.
See Table 10-1 for Erase Row size and the number of
10.1 PMADRL and PMADRH Registers write latches for Flash program memory.
The PMADRH:PMADRL register pair can address up
to a maximum of 16K words of program memory. When TABLE 10-1: FLASH MEMORY
selecting a program address value, the MSB of the ORGANIZATION BY DEVICE
address is written to the PMADRH register and the LSB
Write
is written to the PMADRL register. Row Erase
Device Latches
(words)
(words)
10.1.1 PMCON1 AND PMCON2
REGISTERS PIC16(L)F1615
32 32
PMCON1 is the control register for Flash program PIC16(L)F1619
memory accesses.

PIC16(L)F1615/9
10.2.1 READING THE FLASH PROGRAM FIGURE 10-1: FLASH PROGRAM
MEMORY MEMORY READ
To read a program memory location, the user must: FLOWCHART
1. Write the desired address to the Rev. 10-000046A
7/30/2013
PMADRH:PMADRL register pair.

2. Clear the CFGS bit of the PMCON1 register. Start
3. Then, set control bit RD of the PMCON1 register. Read Operation
Once the read control bit is set, the program memory

Flash controller will use the second instruction cycle to
read the data. This causes the second instruction Select
immediately following the “BSF PMCON1,RD” instruction Program or Configuration Memory
(CFGS)
to be ignored. The data is available in the very next cycle,
in the PMDATH:PMDATL register pair; therefore, it can
be read as two bytes in the following instructions.
Select
PMDATH:PMDATL register pair will hold this value until Word Address
another read or until it is written to by the user. (PMADRH:PMADRL)
Note: The two instructions following a program

memory read are required to be NOPs.
Initiate Read operation
This prevents the user from executing a 2- (RD = 1)
cycle instruction on the next instruction
after the RD bit is set.
Instruction fetched ignored

NOP execution forced

NOP execution forced
Data read now in

PMDATH:PMDATL
End
Read Operation

PIC16(L)F1615/9
FIGURE 10-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Flash ADDR PC PC + 1 PMADRH,PMADRL PC +3

PC+3 PC + 4 PC + 5
Flash Data INSTR (PC) INSTR (PC + 1) PMDATH,PMDATL INSTR (PC + 3) INSTR (PC + 4)
INSTR(PC + 1) INSTR(PC + 2)
INSTR(PC - 1) BSF PMCON1,RD instruction ignored instruction ignored INSTR(PC + 3) INSTR(PC + 4)
executed here executed here Forced NOP Forced NOP executed here executed here
executed here executed here
RD bit
PMDATH
PMDATL
Register
EXAMPLE 10-1: FLASH PROGRAM MEMORY READ
* This code block will read 1 word of program

* memory at the memory address:
PROG_ADDR_HI: PROG_ADDR_LO
* data will be returned in the variables;
* PROG_DATA_HI, PROG_DATA_LO
BANKSEL PMADRL ; Select Bank for PMCON registers

MOVLW PROG_ADDR_LO ;
MOVWF PMADRL ; Store LSB of address
MOVLW PROG_ADDR_HI ;
MOVWF PMADRH ; Store MSB of address
BCF PMCON1,CFGS ; Do not select Configuration Space

BSF PMCON1,RD ; Initiate read
NOP ; Ignored (Figure 10-2)
NOP ; Ignored (Figure 10-2)
MOVF PMDATL,W ; Get LSB of word

MOVWF PROG_DATA_LO ; Store in user location
MOVF PMDATH,W ; Get MSB of word
MOVWF PROG_DATA_HI ; Store in user location

PIC16(L)F1615/9
10.2.2 FLASH MEMORY UNLOCK FIGURE 10-3: FLASH PROGRAM
SEQUENCE MEMORY UNLOCK
The unlock sequence is a mechanism that protects the SEQUENCE FLOWCHART
Flash program memory from unintended self-write pro- Rev. 10-000047A
gramming or erasing. The sequence must be executed

7/30/2013
and completed without interruption to successfully

complete any of the following operations:
Start
• Row Erase Unlock Sequence
• Load program memory write latches
• Write of program memory write latches to
program memory
Write 0x55 to
• Write of program memory write latches to User PMCON2
IDs
The unlock sequence consists of the following steps:
1. Write 55h to PMCON2 Write 0xAA to
PMCON2
2. Write AAh to PMCON2
3. Set the WR bit in PMCON1
4. NOP instruction Initiate
5. NOP instruction Write or Erase operation
(WR = 1)
Once the WR bit is set, the processor will always force
two NOP instructions. When an Erase Row or Program
Row operation is being performed, the processor will stall
internal operations (typical 2 ms), until the operation is NOP execution forced
complete and then resume with the next instruction.
When the operation is loading the program memory write
latches, the processor will always force the two NOP
instructions and continue uninterrupted with the next Instruction fetched ignored
instruction. NOP execution forced
Since the unlock sequence must not be interrupted,

global interrupts should be disabled prior to the unlock
sequence and re-enabled after the unlock sequence is End
completed. Unlock Sequence

PIC16(L)F1615/9
10.2.3 ERASING FLASH PROGRAM FIGURE 10-4: FLASH PROGRAM
MEMORY MEMORY ERASE
While executing code, program memory can only be FLOWCHART
erased by rows. To erase a row: Rev. 10-000048A
7/30/2013
1. Load the PMADRH:PMADRL register pair with

any address within the row to be erased.
Start
2. Clear the CFGS bit of the PMCON1 register. Erase Operation
3. Set the FREE and WREN bits of the PMCON1
register.
4. Write 55h, then AAh, to PMCON2 (Flash
programming unlock sequence). Disable Interrupts
(GIE = 0)
5. Set control bit WR of the PMCON1 register to
begin the erase operation.
See Example 10-2. Select
After the “BSF PMCON1,WR” instruction, the processor Program or Configuration Memory
(CFGS)
requires two cycles to set up the erase operation. The
user must place two NOP instructions immediately fol-
lowing the WR bit set instruction. The processor will
halt internal operations for the typical 2 ms erase time. Select Row Address
This is not Sleep mode as the clocks and peripherals (PMADRH:PMADRL)
will continue to run. After the erase cycle, the processor
will resume operation with the third instruction after the
PMCON1 write instruction.
Select Erase Operation
(FREE = 1)
Enable Write/Erase Operation

(WREN = 1)
Unlock Sequence
(See Note 1)
CPU stalls while

Erase operation completes
(2 ms typical)
Disable Write/Erase Operation

(WREN = 0)
Re-enable Interrupts
(GIE = 1)
End
Erase Operation
Note 1: See Figure 10-3.

PIC16(L)F1615/9
EXAMPLE 10-2: ERASING ONE ROW OF PROGRAM MEMORY
; This row erase routine assumes the following:
; 1. A valid address within the erase row is loaded in ADDRH:ADDRL
; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
BCF INTCON,GIE ; Disable ints so required sequences will execute properly

BANKSEL PMADRL
MOVF ADDRL,W ; Load lower 8 bits of erase address boundary
MOVWF PMADRL
MOVF ADDRH,W ; Load upper 6 bits of erase address boundary
MOVWF PMADRH
BCF PMCON1,CFGS ; Not configuration space
BSF PMCON1,FREE ; Specify an erase operation
BSF PMCON1,WREN ; Enable writes
MOVLW 55h ; Start of required sequence to initiate erase

MOVWF PMCON2 ; Write 55h
Sequence
Required
MOVLW AAh ;
MOVWF PMCON2 ; Write AAh
BSF PMCON1,WR ; Set WR bit to begin erase
NOP ; NOP instructions are forced as processor starts
NOP ; row erase of program memory.
;
; The processor stalls until the erase process is complete
; after erase processor continues with 3rd instruction
BCF PMCON1,WREN ; Disable writes

BSF INTCON,GIE ; Enable interrupts

PIC16(L)F1615/9
10.2.4 WRITING TO FLASH PROGRAM The following steps should be completed to load the
MEMORY write latches and program a row of program memory.
These steps are divided into two parts. First, each write
Program memory is programmed using the following
latch is loaded with data from the PMDATH:PMDATL
steps:
using the unlock sequence with LWLO = 1. When the
1. Load the address in PMADRH:PMADRL of the last word to be loaded into the write latch is ready, the
row to be programmed. LWLO bit is cleared and the unlock sequence
2. Load each write latch with data. executed. This initiates the programming operation,
3. Initiate a programming operation. writing all the latches into Flash program memory.
4. Repeat steps 1 through 3 until all data is written. Note: The special unlock sequence is required
Before writing to program memory, the word(s) to be to load a write latch with data or initiate a
written must be erased or previously unwritten. Pro- Flash programming operation. If the
gram memory can only be erased one row at a time. No unlock sequence is interrupted, writing to
automatic erase occurs upon the initiation of the write. the latches or program memory will not be
initiated.
Program memory can be written one or more words at
a time. The maximum number of words written at one 1. Set the WREN bit of the PMCON1 register.
time is equal to the number of write latches. See 2. Clear the CFGS bit of the PMCON1 register.
Figure 10-5 (row writes to program memory with 32 3. Set the LWLO bit of the PMCON1 register.
write latches) for more details. When the LWLO bit of the PMCON1 register is
The write latches are aligned to the Flash row address ‘1’, the write sequence will only load the write
boundary defined by the upper 11 bits of latches and will not initiate the write to Flash
PMADRH:PMADRL, (PMADRH<6:0>:PMADRL<7:4>) program memory.
with the lower four bits of PMADRL, (PMADRL<3:0>) 4. Load the PMADRH:PMADRL register pair with
determining the write latch being loaded. Write opera- the address of the location to be written.
tions do not cross these boundaries. At the completion 5. Load the PMDATH:PMDATL register pair with
of a program memory write operation, the data in the the program memory data to be written.
write latches is reset to contain 0x3FFF.
6. Execute the unlock sequence (Section
10.2.2 “Flash Memory Unlock Sequence”).
The write latch is now loaded.
7. Increment the PMADRH:PMADRL register pair
to point to the next location.
8. Repeat steps 5 through 7 until all but the last
write latch has been loaded.
9. Clear the LWLO bit of the PMCON1 register.
When the LWLO bit of the PMCON1 register is
‘0’, the write sequence will initiate the write to
Flash program memory.
10. Load the PMDATH:PMDATL register pair with
the program memory data to be written.
11. Execute the unlock sequence (Section
10.2.2 “Flash Memory Unlock Sequence”).
The entire program memory latch content is now
written to Flash program memory.
Note: The program memory write latches are
reset to the Blank state (0x3FFF) at the
completion of every write or erase
operation. As a result, it is not necessary
to load all the program memory write
latches. Unloaded latches will remain in
the blank state.
An example of the complete write sequence is shown in
Example 10-3. The initial address is loaded into the
PMADRH:PMADRL register pair; the data is loaded
using indirect addressing.

FIGURE 10-5: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES
Rev. 10-000004D
7 6 0 7 4 3 0 7 5 0 7 0 7/21/2014
PMADRH PMADRL - - PMDATH PMDATL

- rA r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 c3 c2 c1 c0 6 8
14
Program Memory Write Latches

11 4
14 14 14 14
Write Latch #0 Write Latch #1 Write Latch #30 Write Latch #31
00h 01h 1Eh 1Fh
PMADRL<3:0>
14 14 14 14
Row Addr Addr Addr Addr
000h 0000h 0001h 001Eh 001Fh

001h 0010h 0011h 003Eh 003Fh
002h 0020h 0021h 005Eh 005Fh
CFGS = 0
PIC16(L)F1615/9
7FEh 7FE0h 7FE1h 7FDEh 7FDFh
Row 7FFh 7FF0h 7FF1h 7FFEh 7FFFh
Address
PMADRH<6:0>: Decode Flash Program Memory
PMADRL<7:4>
DS40001770D-page 127
800h 8000h - 8003h 8004h 8005h 8006h 8007h – 8009h 800Ah - 801Fh
MASK/ DEVICE ID Configuration
USER ID 0 - 3 reserved reserved
CFGS = 1 REV ID Words
Configuration Memory
PIC16(L)F1615/9
FIGURE 10-6: FLASH PROGRAM MEMORY WRITE FLOWCHART
Rev. 10-000049A
7/30/2013
Start
Write Operation
Determine number of
words to be written into Enable Write/Erase
Program or Configuration Operation (WREN = 1)
Memory. The number of
words cannot exceed the
number of words per row
(word_cnt)
Load the value to write
(PMDATH:PMDATL)
Disable Interrupts
(GIE = 0)
Update the word counter Write Latches to Flash
(word_cnt--) (LWLO = 0)
Select
Program or Config.
Memory (CFGS)
Unlock Sequence
Last word to Yes (See Note 1)
write ?
Select Row Address
(PMADRH:PMADRL)
No
CPU stalls while Write
operation completes
Unlock Sequence (2 ms typical)
Select Write Operation (See Note 1)
(FREE = 0)
Load Write Latches Only No delay when writing to Disable Write/Erase

(LWLO = 1) Program Memory Latches Operation (WREN = 0)
Re-enable Interrupts
(GIE = 1)
Increment Address
(PMADRH:PMADRL++)
End
Write Operation

PIC16(L)F1615/9
EXAMPLE 10-3: WRITING TO FLASH PROGRAM MEMORY (32 WRITE LATCHES)
; This write routine assumes the following:
; 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR
; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,
; stored in little endian format
; 3. A valid starting address (the Least Significant bits = 00000) is loaded in ADDRH:ADDRL
; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
;
BCF INTCON,GIE ; Disable ints so required sequences will execute properly
BANKSEL PMADRH ; Bank 3
MOVF ADDRH,W ; Load initial address
MOVWF PMADRH ;
MOVF ADDRL,W ;
MOVWF PMADRL ;
MOVLW LOW DATA_ADDR ; Load initial data address
MOVWF FSR0L ;
MOVLW HIGH DATA_ADDR ; Load initial data address
MOVWF FSR0H ;
BCF PMCON1,CFGS ; Not configuration space
BSF PMCON1,WREN ; Enable writes
BSF PMCON1,LWLO ; Only Load Write Latches
LOOP
MOVIW FSR0++ ; Load first data byte into lower
MOVWF PMDATL ;
MOVIW FSR0++ ; Load second data byte into upper
MOVWF PMDATH ;
MOVF PMADRL,W ; Check if lower bits of address are '00000'

XORLW 0x1F ; Check if we're on the last of 32 addresses
ANDLW 0x1F ;
BTFSC STATUS,Z ; Exit if last of 32 words,
GOTO START_WRITE ;
MOVLW 55h ; Start of required write sequence:

MOVLW AAh ;
Sequence
Required

BSF PMCON1,WR ; Set WR bit to begin write
NOP ; NOP instructions are forced as processor
; loads program memory write latches
NOP ;
INCF PMADRL,F ; Still loading latches Increment address

GOTO LOOP ; Write next latches
START_WRITE
BCF PMCON1,LWLO ; No more loading latches - Actually start Flash program
; memory write
MOVLW 55h ; Start of required write sequence:

Sequence
MOVLW AAh ;
Required

BSF PMCON1,WR ; Set WR bit to begin write
NOP ; NOP instructions are forced as processor writes
; all the program memory write latches simultaneously
NOP ; to program memory.
; After NOPs, the processor
; stalls until the self-write process in complete
; after write processor continues with 3rd instruction
BCF PMCON1,WREN ; Disable writes
BSF INTCON,GIE ; Enable interrupts

PIC16(L)F1615/9
10.3 Modifying Flash Program Memory FIGURE 10-7: FLASH PROGRAM
MEMORY MODIFY
When modifying existing data in a program memory
FLOWCHART
row, and data within that row must be preserved, it must
first be read and saved in a RAM image. Program Rev. 10-000050A
memory is modified using the following steps: 7/30/2013
1. Load the starting address of the row to be

Start
modified.
Modify Operation
2. Read the existing data from the row into a RAM
image.
3. Modify the RAM image to contain the new data
to be written into program memory. Read Operation
(See Note 1)
4. Load the starting address of the row to be
rewritten.
5. Erase the program memory row.
6. Load the write latches with data from the RAM An image of the entire row
image. read must be stored in RAM
7. Initiate a programming operation.
Modify Image
The words to be modified are
changed in the RAM image
Erase Operation
(See Note 2)
Write Operation
Use RAM image
(See Note 3)
End
Modify Operation

2: See Figure 10-4.
3: See Figure 10-5.

PIC16(L)F1615/9
10.4 User ID, Device ID and
Configuration Word Access
Instead of accessing program memory, the User ID’s,
Device ID/Revision ID and Configuration Words can be
accessed when CFGS = 1 in the PMCON1 register.
This is the region that would be pointed to by
PC<15> = 1, but not all addresses are accessible.
Different access may exist for reads and writes. Refer
to Table 10-2.
When read access is initiated on an address outside
the parameters listed in Table 10-2, the
PMDATH:PMDATL register pair is cleared, reading
back ‘0’s.
TABLE 10-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)
Address Function Read Access Write Access
8000h-8003h User IDs Yes Yes
8006h/8005h Device ID/Revision ID Yes No
8007h-8009h Configuration Words 1, 2, and 3 Yes No
EXAMPLE 10-4: CONFIGURATION WORD AND DEVICE ID ACCESS

* This code block will read 1 word of program memory at the memory address:
* PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;
* PROG_DATA_HI, PROG_DATA_LO
BANKSEL PMADRL ; Select correct Bank

MOVLW PROG_ADDR_LO ;
MOVWF PMADRL ; Store LSB of address
CLRF PMADRH ; Clear MSB of address
BSF PMCON1,CFGS ; Select Configuration Space

BCF INTCON,GIE ; Disable interrupts
BSF PMCON1,RD ; Initiate read
NOP ; Executed (See Figure 10-2)
NOP ; Ignored (See Figure 10-2)
BSF INTCON,GIE ; Restore interrupts
MOVF PMDATL,W ; Get LSB of word

MOVWF PROG_DATA_LO ; Store in user location
MOVF PMDATH,W ; Get MSB of word
MOVWF PROG_DATA_HI ; Store in user location

PIC16(L)F1615/9
10.5 Write Verify
It is considered good programming practice to verify that
program memory writes agree with the intended value.
Since program memory is stored as a full page then the
stored program memory contents are compared with the
intended data stored in RAM after the last write is
complete.
FIGURE 10-8: FLASH PROGRAM

MEMORY VERIFY
FLOWCHART
Rev. 10-000051A
7/30/2013
Start
Verify Operation
This routine assumes that the last

row of data written was from an
image saved on RAM. This image
will be used to verify the data
currently stored in Flash Program
Memory
Read Operation
(See Note 1)
PMDAT = No
RAM image ?
Yes
Fail
Verify Operation
No
Last word ?
Yes
End
Verify Operation

PIC16(L)F1615/9
10.6 Register Definitions: Flash Program Memory Control
REGISTER 10-1: PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
PMDAT<7:0>
bit 7 bit 0
Legend:
bit 7-0 PMDAT<7:0>: Read/write value for Least Significant bits of program memory
REGISTER 10-2: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER

U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — PMDAT<13:8>
bit 7 bit 0
Legend:

bit 5-0 PMDAT<13:8>: Read/write value for Most Significant bits of program memory
REGISTER 10-3: PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER

PMADR<7:0>
bit 7 bit 0
Legend:
bit 7-0 PMADR<7:0>: Specifies the Least Significant bits for program memory address
REGISTER 10-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER

U-1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
—(1) PMADR<14:8>
bit 7 bit 0
Legend:

bit 6-0 PMADR<14:8>: Specifies the Most Significant bits for program memory address
Note 1: Unimplemented, read as ‘1’.

PIC16(L)F1615/9
REGISTER 10-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER

U-1 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W/HC-x/q(2) R/W-0/0 R/S/HC-0/0 R/S/HC-0/0
(1)
— CFGS LWLO FREE WRERR WREN WR RD
bit 7 bit 0
Legend:
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware

bit 6 CFGS: Configuration Select bit
1 = Access Configuration, User ID and Device ID Registers
0 = Access Flash program memory
bit 5 LWLO: Load Write Latches Only bit(3)
1 = Only the addressed program memory write latch is loaded/updated on the next WR command
0 = The addressed program memory write latch is loaded/updated and a write of all program memory write latches
will be initiated on the next WR command
bit 4 FREE: Program Flash Erase Enable bit
1 = Performs an erase operation on the next WR command (hardware cleared upon completion)
0 = Performs a write operation on the next WR command
bit 3 WRERR: Program/Erase Error Flag bit
1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically
on any set attempt (write ‘1’) of the WR bit)
0 = The program or erase operation completed normally
bit 2 WREN: Program/Erase Enable bit
1 = Allows program/erase cycles
0 = Inhibits programming/erasing of program Flash
bit 1 WR: Write Control bit
1 = Initiates a program Flash program/erase operation.
The operation is self-timed and the bit is cleared by hardware once operation is complete.
The WR bit can only be set (not cleared) in software.
0 = Program/erase operation to the Flash is complete and inactive
bit 0 RD: Read Control bit
1 = Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set
(not cleared) in software.
0 = Does not initiate a program Flash read
Note 1: Unimplemented bit, read as ‘1’.
2: The WRERR bit is automatically set by hardware when a program memory write or erase operation is started (WR = 1).
3: The LWLO bit is ignored during a program memory erase operation (FREE = 1).

PIC16(L)F1615/9
REGISTER 10-6: PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER

W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0
Program Memory Control Register 2
bit 7 bit 0
Legend:
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
bit 7-0 Flash Memory Unlock Pattern bits

To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the
PMCON1 register. The value written to this register is used to unlock the writes. There are specific
timing requirements on these writes.
TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY

Register on
Page
PMCON1 —(1) CFGS LWLO FREE WRERR WREN WR RD 134
PMCON2 Program Memory Control Register 2 135
PMADRL PMADRL<7:0> 133
(1)
PMADRH — PMADRH<6:0> 133
PMDATL PMDATL<7:0> 133
PMDATH — — PMDATH<5:0> 133
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.
TABLE 10-4: SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY

Register
on Page

CONFIG1 69
13:8 — — LVP DEBUG LPBOR BORV STVREN PLLEN
CONFIG2 68
7:0 ZCD — — — — PPS1WAY WRT<1:0>
13:8 — — WDTCCS<2:0> WDTCWS<2:0>
CONFIG3 69
7:0 — WDTE<1:0> WDTCPS<4:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.

PIC16(L)F1615/9
11.0 CYCLIC REDUNDANCY CHECK EXAMPLE 11-1:
(CRC) MODULE Rev. 10-000206A
1/8/2014
CRC-16-ANSI
The Cyclic Redundancy Check (CRC) module provides x16 + x15 + x2 + 1 (17 bits)
a software-configurable hardware-implemented CRC
checksum generator. This module includes the following Standard 16-bit representation = 0x8005
features: CRCXORH = 0b10000000
CRCXORL = 0b0000010- (1)
• Any standard CRC up to 16 bits can be used

Data Sequence:
• Configurable Polynomial 0x55, 0x66, 0x77, 0x88
• Any seed value up to 16 bits can be used DLEN = 0b0111
• Standard and reversed bit order available PLEN = 0b1111
• Augmented zeros can be added automatically or Data entered into the CRC:
by the user SHIFTM = 0:
• Memory scanner for fast CRC calculations on 01010101 01100110 01110111 10001000
program memory user data SHIFTM = 1:
• Software loadable data registers for calculating 10101010 01100110 11101110 00010001
CRC values not from the memory scanner Check Value (ACCM = 1):
SHIFTM = 0: 0x32D6
11.1 CRC Module Overview CRCACCH = 0b00110010
CRCACCL = 0b11010110
The CRC module provides a means for calculating a
check value of program memory. The CRC module is SHIFTM = 1: 0x6BA2
CRCACCH = 0b01101011
coupled with a memory scanner for faster CRC
CRCACCL = 0b10100010
calculations. The memory scanner can automatically
provide data to the CRC module. The CRC module can Note 1: Bit 0 is unimplemented. The LSb of any
also be operated by directly writing data to SFRs, with- CRC polynomial is always ‘1’ and will always
out using the scanner. be treated as a ‘1’ by the CRC for calculating
the CRC check value. This bit will be read in
software as a ‘0’.
11.2 CRC Functional Overview
The CRC module can be used to detect bit errors in the
Flash memory using the built-in memory scanner or
11.3 CRC Polynomial Implementation
through user input RAM. The CRC module can accept Any polynomial can be used. The polynomial and
up to a 16-bit polynomial with up to a 16-bit seed value. accumulator sizes are determined by the PLEN<3:0>
A CRC calculated check value (or checksum) will then bits. For an n-bit accumulator, PLEN = n-1 and the
be generated into the CRCACC<15:0> registers for corresponding polynomial is n+1 bits. Therefore, the
user storage. The CRC module uses an XOR shift reg- accumulator can be any size up to 16 bits with a
ister implementation to perform the polynomial division corresponding polynomial up to 17 bits. The MSb and
required for the CRC calculation. LSb of the polynomial are always ‘1’, which is forced by
hardware. All polynomial bits between the MSb and
LSb are specified by the CRCXOR registers. For
example, when using CRC-16-ANSI, the polynomial is
defined as X16+X15+X2+1. The X16 and X0 = 1 terms
are the MSb and LSb controlled by hardware. The X15
and X2 terms are specified by setting the
corresponding CRCXOR<15:0> bits with the value of
0x8004. The actual value is 0x8005 because the
hardware sets the LSb to 1. However, the LSb of the
CRCXORL register is unimplemented and always
reads as ‘0’. Please refer to Example 11-1.

PIC16(L)F1615/9
EXAMPLE 11-2: CRC LFSR EXAMPLE
Rev. 10-000207A
Linear Feedback Shift Register for CRC-16-ANSI 5/27/2014
x16 + x15 + x2 + 1
Data in
Augmentation Mode ON
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Data in
Augmentation Mode OFF
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
11.4 CRC Data Sources 11.5 CRC Check Value

Data can be input to the CRC module in two ways: The CRC check value will be located in the CRCACC
- User data using the CRCDAT registers registers after the CRC calculation has finished. The
check value will depend on two mode settings of the
- Flash using the Program Memory Scanner
CRCCON register: ACCM and SHIFTM. When the
To set the number of bits of data, up to 16 bits, the DLEN ACCM bit is set, the CRC module augments the data with
bits of CRCCON1 must be set accordingly. Only data a number of zeros equal to the length of the polynomial to
bits in CRCDATA registers up to DLEN will be used, align the final check value. When the ACCM bit is not set,
other data bits in CRCDATA registers will be ignored. the CRC will stop at the end of the data. A number of
Data is moved into the CRCSHIFT as an intermediate zeros equal to the length of the polynomial can then be
to calculate the check value located in the CRCACC entered into CRCDAT to find the same check value as
registers. Augmented mode. Alternatively, the expected check
value can be entered at this point to make the final result
The SHIFTM bit is used to determine the bit order of the equal 0.
data being shifted into the accumulator. If SHIFTM is
not set, the data will be shifted in MSb first. The value When the CRC check value is computed with the
of DLEN will determine the MSb. If SHIFTM bit is set, SHIFTM bit set (selecting LSb first), and the ACCM bit is
the data will be shifted into the accumulator in reversed set, then the final value in the CRCACC registers will be
order, LSb first. reversed such that the LSb will be in the MSb position and
vice versa. This is the expected check value in bit
The CRC module can be seeded with an initial value by reversed form. If you are creating a check value to be
setting the CRCACC<15:0> registers to the appropri- appended to a data stream, a bit reversal must be
ate value before beginning the CRC. performed on the final value to achieve the correct
checksum. The CRC can be used to do this reversal by
11.4.1 CRC FROM USER DATA
the following method:
To use the CRC module on data input from the user, the
• Save the CRCACC value in user RAM space
user must write the data to the CRCDAT registers. The
data from the CRCDAT registers will be latched into the • Clear the CRCACC registers
shift registers on any write to the CRCDATL register. • Clear the CRCXOR registers
11.4.2 CRC FROM FLASH • Write the saved CRCACC value to the CRCDAT input
To use the CRC module on data located in Flash The properly oriented check value will be in the
memory, the user can initialize the Program Memory CRCACC registers as the result.
Scanner as defined in Section 11.8, Program Mem-
ory Scan Configuration. 11.6 CRC Interrupt
The CRC will generate an interrupt when the BUSY bit
transitions from 1 to 0. The CRCIF interrupt flag bit of the
PIR4 register is set every time the BUSY bit transitions,
regardless of whether or not the CRC interrupt is enabled.
The CRCIF bit can only be cleared in software. The CRC
interrupt enable is the CRCIE bit of the PIE4 register.

PIC16(L)F1615/9
11.7 Configuring the CRC 11.8 Program Memory Scan
The following steps illustrate how to properly configure
Configuration
the CRC. If desired, the Program Memory Scan module may be
1. Determine if the automatic Program Memory used in conjunction with the CRC module to perform a
scan will be used with the Scanner or manual CRC calculation over a range of program memory
calculation through the SFR interface and per- addresses. In order to set up the Scanner to work with
form the actions specified in Section11.4 “CRC the CRC, perform the following steps:
Data Sources”, depending on which decision 1. Set the EN bit to enable the module. This can be
was made. performed at any point preceding the setting of
2. If desired, seed a starting CRC value into the the SCANGO bit, but if it gets disabled, all inter-
CRCACCH/L registers. nal states of the Scanner are reset (registers are
3. Program the CRCXORH/L registers with the unaffected).
desired generator polynomial. 2. Choose which memory access mode is to be
4. Program the DLEN<3:0> bits of the CRCCON1 used (see Section11.10 “Scanning Modes”)
register with the length of the data word - 1 (refer and set the MODE bits of the SCANCON0
to Example 11-1). This determines how many register appropriately.
times the shifter will shift into the accumulator for 3. Based on the memory access mode, set the
each data word. INTM bits of the SCANCON0 register to the
5. Program the PLEN<3:0> bits of the CRCCON1 appropriate interrupt mode (see
register with the length of the polynomial - 2 Section11.10.5 “Interrupt Interaction”)
(refer to Example 11-1). 4. Set the SCANLADRL/H and SCANHADRL/H
6. Determine whether shifting in trailing zeros is registers with the beginning and ending loca-
desired and set the ACCM bit of CRCCON0 reg- tions in memory that are to be scanned.
ister appropriately. 5. Begin the scan by setting the SCANGO bit in the
7. Likewise, determine whether the MSb or LSb SCANCON0 register. The scanner will wait
should be shifted first and write the SHIFTM bit (CRCGO must be set) for the signal from the
of CRCCON0 register appropriately. CRC that it is ready for the first Flash memory
8. Write the CRCGO bit of the CRCCON0 register location, then begin loading data into the CRC.
to begin the shifting process. It will continue to do so until it either hits the con-
figured end address or an address that is unim-
9a. If manual SFR entry is used, monitor the FULL bit
plemented on the device, at which point the
of CRCCON0 register. When FULL = 0, another
SCANGO bit will clear, Scanner functions will
word of data can be written to the CRCDATH/L
cease, and the SCANIF interrupt will be trig-
registers, keeping in mind that CRCDATH should
gered. Alternately, the SCANGO bit can be
be written first if the data has >8 bits, as the
cleared in software if desired.
shifter will begin upon the CRCDATL register
being written.
11.9 Scanner Interrupt
9b. If the scanner is used, the scanner will
automatically stuff words into the CRCDATH/L The scanner will trigger an interrupt when the
registers as needed, as long as the SCANGO bit SCANGO bit transitions from 1 to 0. The SCANIF inter-
is set. rupt flag of PIR4 is set when the last memory location
10a.If using the Flash memory scanner, monitor the is reached and the data is entered into the CRCDATA
SCANIF (or the SCANGO bit) for the scanner to registers. The SCANIF bit can only be cleared in soft-
finish pushing information into the CRCDATA ware. The SCAN interrupt enable is the SCANIE bit of
registers. After the scanner is completed, moni- the PIE4 register.
tor the CRCIF (or the BUSY bit) to determine
that the CRC has been completed and the check 11.10 Scanning Modes
value can be read from the CRCACC registers.
If both the interrupt flags are set (or both BUSY The memory scanner can scan in four modes: Burst,
and SCANGO bits are cleared), the completed Peek, Concurrent, and Triggered. These modes are
CRC calculation can be read from the controlled by the MODE bits of the SCANCON0 regis-
CRCACCH/L registers. ter. The four modes are summarized in Table 11-1.
10b.If manual entry is used, monitor the CRCIF (or
11.10.1 BURST MODE
BUSY bit) to determine when the CRCACC
registers will hold the check value. When MODE = 01, the scanner is in Burst mode. In
Burst mode, CPU operation is stalled beginning with the
operation after the one that sets the SCANGO bit, and
the scan begins, using the instruction clock to execute.

PIC16(L)F1615/9
The CPU is held until the scan stops. Note that because ately upon the SCANGO bit being set, it waits for a ris-
the CPU is not executing instructions, the SCANGO bit ing edge from a separate trigger clock, the source of
cannot be cleared in software, so the CPU will remain which is determined by the SCANTRIG register.
stalled until one of the hardware end-conditions occurs.
Burst mode has the highest throughput for the scanner, 11.10.4 PEEK MODE
but has the cost of stalling other execution while it When MODE = 10, the scanner is in Peek mode. Peek
occurs. mode waits for an instruction cycle in which the CPU
does not need to access the NVM (such as a branch
11.10.2 CONCURRENT MODE instruction) and uses that cycle to do its own NVM
When MODE = 00, the scanner is in Concurrent mode. access. This results in the lowest throughput for the NVM
Concurrent mode, like Burst mode, stalls the CPU access (and can take a much longer time to complete a
while performing accesses of memory. However, while scan than the other modes), but does so without any
Burst mode stalls until all accesses are complete, impact on execution times, unlike the other modes.
Concurrent mode allows the CPU to execute in
between access cycles.
11.10.3 TRIGGERED MODE

When MODE = 11, the scanner is in Triggered mode.
Triggered mode behaves identically to Concurrent
mode, except instead of beginning the scan immedi-
TABLE 11-1: SUMMARY OF SCANNER MODES

Description
MODE<1:0>
First Scan Access CPU Operation
As soon as possible CPU resumes execution following
11 Triggered Stalled during NVM access
following a trigger each access
CPU continues execution following
10 Peek At the first dead cycle Timing is unaffected
each access
CPU suspended until scan
01 Burst
completes
As soon as possible Stalled during NVM access
CPU resumes execution following
00 Concurrent
each access
11.10.5 INTERRUPT INTERACTION

The INTM bit of the SCANCON0 register controls the
scanner’s response to interrupts depending on which
mode the NVM scanner is in, as described in Table 11-
2.
TABLE 11-2: SCAN INTERRUPT MODES

MODE<1:0>
INTM
MODE == Burst MODE != Burst
Interrupt overrides SCANGO to pause the burst
Scanner suspended during interrupt response;
and the interrupt handler executes at full speed;
1 interrupt executes at full speed and scan
Scanner Burst resumes when interrupt
resumes when the interrupt is complete.
completes.
Interrupts do not override SCANGO, and the
Scanner accesses NVM during interrupt
scan (burst) operation will continue; interrupt
0 response. If MODE != Peak the interrupt handler
response will be delayed until scan completes
execution speed will be affected.
(latency will be increased).
In general, if INTM = 0, the scanner will take prece- response latency. If INTM = 1, the interrupt will take
dence over the interrupt, resulting in decreased inter- precedence and have a better speed, delaying the
rupt processing speed and/or increased interrupt memory scan.

PIC16(L)F1615/9
11.10.6 WDT INTERACTION 11.10.7 IN-CIRCUIT DEBUG (ICD)
Operation of the WDT is not affected by scanner activ- INTERACTION
ity. Hence, it is possible that long scans, particularly in The scanner freezes when an ICD halt occurs, and
Burst mode, may exceed the WDT time-out period and remains frozen until user-mode operation resumes.
result in an undesired device Reset. This should be The debugger may inspect the SCANCON0 and
considered when performing memory scans with an SCANLADR registers to determine the state of the
application that also utilizes WDT. scan.
The ICD interaction with each operating mode is
summarized in Table 11-3.
TABLE 11-3: ICD AND SCANNER INTERACTIONS

Scanner Operating Mode
ICD Halt Concurrent
Peek Burst
Triggered
If external halt is asserted during the
BSF(SCANCON.GO), ICD entry
If external halt is asserted during a occurs, and the burst is delayed until
scan cycle, the instruction (delayed ICD exit.
by scan) may or may not execute
before ICD entry, depending on Otherwise, the current NVM-access
External Halt external halt timing. cycle will complete, and then the
scanner will be interrupted for ICD
entry.
cycle immediately prior to the scan
burst, the burst is suspended and will
cycle, both scan and instruction
resume with ICD exit.
execution happen after the ICD exits.
Scan cycle occurs before ICD entry
PC If Scanner would peek an instruction
and instruction execution happens
Breakpoint that is not executed (because of ICD
after the ICD exits. If PCPB (or single step) is on
entry), the peek will occur after ICD
exit, when the instruction executes. The instruction with the dataBP BSF(SCANCON.GO), the ICD is
executes and ICD entry occurs entered before execution; execution
Data
immediately after. If scan is of the burst will occur at ICD exit, and
Breakpoint
requested during that cycle, the scan the burst will run to completion.
cycle is postponed until the ICD exits.
If a scan cycle is ready after the Note that the burst can be interrupted
debug instruction is executed, the by an external halt.
Single Step
scan will read PFM and then the ICD
is re-entered.
If SWBP replaces
BSF(SCANCON.GO), the ICD will be
SWBP and If scan would stall a SWBP, the scan entered; instruction execution will
ICDINST cycle occurs and the ICD is entered. occur at ICD exit (from ICDINSTR
register), and the burst will run to
completion.

PIC16(L)F1615/9
11.11 Register Definitions: CRC and Scanner Control
REGISTER 11-1: CRCCON0: CRC CONTROL REGISTER 0

R/W-0/0 R/W-0/0 R-0 R/W-0/0 U-0 U-0 R/W-0/0 R-0
EN CRCGO BUSY ACCM — — SHIFTM FULL
bit 7 bit 0
Legend:
bit 7 EN: CRC Enable bit

1 = CRC module is released from Reset
0 = CRC is disabled and consumes no operating current
bit 6 CRCGO: CRC Start bit
1 = Start CRC serial shifter
0 = CRC serial shifter turned off
bit 5 BUSY: CRC Busy bit
1 = Shifting in progress or pending
0 = All valid bits in shifter have been shifted into accumulator and EMPTY = 1
bit 4 ACCM: Accumulator Mode bit
1 = Data is augmented with zeros
0 = Data is not augmented with zeros
bit 1 SHIFTM: Shift Mode bit
1 = Shift right (LSb)
0 = Shift left (MSb)
bit 0 FULL: Data Path Full Indicator bit
1 = CRCDATH/L registers are full
0 = CRCDATH/L registers have shifted their data into the shifter
REGISTER 11-2: CRCCON1: CRC CONTROL REGISTER 1

DLEN<3:0> PLEN<3:0>
bit 7 bit 0
Legend:
bit 7-4 DLEN<3:0>: Data Length bits

Denotes the length of the data word -1 (See Example 11-1)
bit 3-0 PLEN<3:0>: Polynomial Length bits
Denotes the length of the polynomial -1 (See Example 11-1)

PIC16(L)F1615/9
REGISTER 11-3: CRCDATH: CRC DATA HIGH BYTE REGISTER

R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x
DAT<15:8>
bit 7 bit 0
Legend:
bit 7-0 DAT<15:8>: CRC Input/Output Data bits
REGISTER 11-4: CRCDATL: CRC DATA LOW BYTE REGISTER

R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x
DAT<7:0>
bit 7 bit 0
Legend:
bit 7-0 DAT<7:0>: CRC Input/Output Data bits

Writing to this register fills the shifter.
REGISTER 11-5: CRCACCH: CRC ACCUMULATOR HIGH BYTE REGISTER

ACC<15:8>
bit 7 bit 0
Legend:
bit 7-0 ACC<15:8>: CRC Accumulator Register bits

Writing to this register writes to the CRC accumulator register. Reading from
this register reads the CRC accumulator.
REGISTER 11-6: CRCACCL: CRC ACCUMULATOR LOW BYTE REGISTER

ACC<7:0>
bit 7 bit 0
Legend:
bit 7-0 ACC<7:0>: CRC Accumulator Register bits

Writing to this register writes to the CRC accumulator register through the CRC write bus. Reading from
this register reads the CRC accumulator.

PIC16(L)F1615/9
REGISTER 11-7: CRCSHIFTH: CRC SHIFT HIGH BYTE REGISTER

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
SHIFT<15:8>
bit 7 bit 0
Legend:
bit 7-0 SHIFT<15:8>: CRC Shifter Register bits

Reading from this register reads the CRC
Shifter.
REGISTER 11-8: CRCSHIFTL: CRC SHIFT LOW BYTE REGISTER

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
SHIFT<7:0>
bit 7 bit 0
Legend:
bit 7-0 SHIFT<7:0>: CRC Shifter Register bits

Reading from this register reads the CRC
Shifter.
REGISTER 11-9: CRCXORH: CRC XOR HIGH BYTE REGISTER

R/W R/W R/W R/W R/W R/W R/W R/W
XOR<15:8>
bit 7 bit 0
Legend:
bit 7-0 XOR<15:8>: XOR of Polynomial Term XN Enable bits
REGISTER 11-10: CRCXORL: CRC XOR LOW BYTE REGISTER

R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x U-0
XOR<7:1> —
bit 7 bit 0
Legend:
bit 7-1 XOR<7:1>: XOR of Polynomial Term XN Enable bits


PIC16(L)F1615/9
REGISTER 11-11: SCANCON0: SCANNER ACCESS CONTROL REGISTER 0

R/W-0/0 R/W/HC-0/0 R-0 R-0 R/W-0/0 U-0 R/W-0/0 R/W-0/0
EN(1) SCANGO(2, 3) BUSY(4) INVALID INTM — MODE<1:0>(5)
bit 7 bit 0
Legend:
bit 7 EN: Scanner Enable bit(1)

1 = Scanner is enabled
0 = Scanner is disabled, internal states are reset
bit 6 SCANGO: Scanner GO bit(2, 3)
1 = When the CRC sends a ready signal, NVM will be accessed according to MDx and data passed
to the client peripheral.
0 = Scanner operations will not occur
bit 5 BUSY: Scanner Busy Indicator bit(4)
1 = Scanner cycle is in process
0 = Scanner cycle is complete (or never started)
bit 4 INVALID: Scanner Abort signal bit
1 = SCANLADRL/H has incremented or contains an invalid address(6)
0 = SCANLADRL/H points to a valid address
bit 3 INTM: NVM Scanner Interrupt Management Mode Select bit
If MODE = 10:
This bit is ignored
If MODE = 01 (CPU is stalled until all data is transferred):
1 = SCANGO is overridden (to zero) during interrupt operation; scanner resumes after returning from
interrupt
0 = SCANGO is not affected by interrupts, the interrupt response will be affected
If MODE = 00 or 11:
1 = SCANGO is overridden (to zero) during interrupt operation; scan operations resume after returning
from interrupt
0 = Interrupts do not prevent NVM access
bit 1-0 MODE<1:0>: Memory Access Mode bits(5)
11 = Triggered mode
10 = Peek mode
01 = Burst mode
00 = Concurrent mode
Note 1: Setting EN = 0 (SCANCON0 register) does not affect any other register content.
2: This bit is cleared when LADR > HADR (and a data cycle is not occurring).
3: If INTM = 1, this bit is overridden (to zero, but not cleared) during an interrupt response.
4: BUSY = 1 when the NVM is being accessed, or when the CRC sends a ready signal.
5: See Table 11-1 for more detailed information.
6: An invalid address happens when the entire range of the PFM is scanned and completed, i.e., device
memory is 0x4000 and SCANHADR = 0x3FFF, after the last scan SCANLADR increments to 0x4000, the
address is invalid.

PIC16(L)F1615/9
REGISTER 11-12: SCANLADRH: SCAN LOW ADDRESS HIGH BYTE REGISTER

LADR<15:8>(1, 2)
bit 7 bit 0
Legend:
bit 7-0 LADR<15:8>: Scan Start/Current Address bits(1, 2)

Most Significant bits of the current address to be fetched from, value increments on each fetch of
memory.
Note 1: Registers SCANLADRH/L form a 16-bit value, but are not guarded for atomic or asynchronous access;
registers should only be read or written while SCANGO = 0 (SCANCON0 register).
2: While SCANGO = 1 (SCANCON0 register), writing to this register is ignored.
REGISTER 11-13: SCANLADRL: SCAN LOW ADDRESS LOW BYTE REGISTER

LADR<7:0>(1, 2)
bit 7 bit 0
Legend:
bit 7-0 LADR<7:0>: Scan Start/Current Address bits(1, 2)

Least Significant bits of the current address to be fetched from, value increments on each fetch of
memory
Note 1: Registers SCANLADRH/L form a 16-bit value, but are not guarded for atomic or asynchronous access;

PIC16(L)F1615/9
REGISTER 11-14: SCANHADRH: SCAN HIGH ADDRESS HIGH BYTE REGISTER

HADR<15:8>(1, 2)
bit 7 bit 0
Legend:
bit 7-0 HADR<15:8>: Scan End Address bits(1, 2)

Most Significant bits of the address at the end of the designated scan
Note 1: Registers SCANHADRH/L form a 16-bit value, but are not guarded for atomic or asynchronous access;
REGISTER 11-15: SCANHADRL: SCAN HIGH ADDRESS LOW BYTE REGISTER

(1, 2)
HADR<7:0>
bit 7 bit 0
Legend:
bit 7-0 HADR<7:0>: Scan End Address bits(1, 2)

Least Significant bits of the address at the end of the designated scan
Note 1: Registers SCANHADRH/L form a 16-bit value, but are not guarded for atomic or asynchronous access;

PIC16(L)F1615/9
REGISTER 11-16: SCANTRIG: SCAN TRIGGER SELECTION REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0
— — — — TSEL<3:0>
bit 7 bit 0
Legend:

bit 3-0 TSEL<3:0>: Scanner Data Trigger Input Selection bits
1111-1010 = Reserved
1001 = SMT2_Match
1000 = SMT1_Match
0111 = TMR0_Overflow
0011 = TMR6_postscaled
0000 = LFINTOSC
TABLE 11-4: SUMMARY OF REGISTERS ASSOCIATED WITH CRC

Register
on Page
CRCACCH ACC<15:8> 142
CRCACCL ACC<7:0> 142
CRCCON0 EN CRCGO BUSY ACCM — — SHIFTM FULL 141
CRCCON1 DLEN<3:0> PLEN<3:0> 141
CRCDATH DAT<15:8> 142
CRCDATL DAT<7:0> 142
CRCSHIFTH SHIFT<15:8> 143
CRCSHIFTL SHIFT<7:0> 143
CRCXORH XOR<15:8> 143
CRCXORL XOR<7:1> — 143
PIE4 SCANIE CRCIE SMT2PWAIE SMT2PRAIE SMT2IE SMT1PWAIE SMT1PRAIE SMT1IE 101
SCANCON0 EN SCANGO BUSY INVALID INTM — MODE<1:0> 144
SCANHADRH HADR<15:8> 146
SCANHADRL HADR<7:0> 146
SCANLADRH LADR<15:8> 145
SCANLADRL LADR<7:0> 145
SCANTRIG TSEL<3:0> 147
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the CRC module.
* Page provides register information.

PIC16(L)F1615/9
12.0 I/O PORTS FIGURE 12-1: GENERIC I/O PORT
OPERATION
Each port has six standard registers for its operation.
These registers are: Rev. 10-000052A
7/30/2013
• TRISx registers (data direction)

Read LATx
• PORTx registers (reads the levels on the pins of
the device)
TRISx
• LATx registers (output latch)
• INLVLx (input level control) D Q
• ODCONx registers (open-drain) Write LATx

Write PORTx VDD
• SLRCONx registers (slew rate) CK
Some ports may have one or more of the following

Data Register
additional registers. These registers are:
Data bus
• ANSELx (analog select)
I/O pin
• WPUx (weak pull-up) Read PORTx
In general, when a peripheral is enabled on a port pin, To digital peripherals
that pin cannot be used as a general purpose output.
ANSELx
However, the pin can still be read.
To analog peripherals
TABLE 12-1: PORT AVAILABILITY PER VSS
DEVICE
PORTA
PORTB
PORTC
Device
PIC16(L)F1619 ● ● ●
PIC16(L)F1615 ● ●
The Data Latch (LATx registers) is useful for read-
modify-write operations on the value that the I/O pins
are driving.
A write operation to the LATx register has the same
effect as a write to the corresponding PORTx register.
A read of the LATx register reads of the values held in
the I/O PORT latches, while a read of the PORTx
register reads the actual I/O pin value.
Ports that support analog inputs have an associated
ANSELx register. When an ANSEL bit is set, the digital
input buffer associated with that bit is disabled.
Disabling the input buffer prevents analog signal levels
on the pin between a logic high and low from causing
excessive current in the logic input circuitry. A
simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 12-1.

PIC16(L)F1615/9
12.1 PORTA Registers 12.1.5 INPUT THRESHOLD CONTROL
The INLVLA register (Register 12-8) controls the input
12.1.1 DATA REGISTER voltage threshold for each of the available PORTA input
PORTA is a 6-bit wide, bidirectional port. The pins. A selection between the Schmitt Trigger CMOS or
corresponding data direction register is TRISA the TTL Compatible thresholds is available. The input
(Register 12-2). Setting a TRISA bit (= 1) will make the threshold is important in determining the value of a
corresponding PORTA pin an input (i.e., disable the read of the PORTA register and also the level at which
output driver). Clearing a TRISA bit (= 0) will make the an interrupt-on-change occurs, if that feature is
corresponding PORTA pin an output (i.e., enables enabled. See 35.3 “DC Characteristics” for more
output driver and puts the contents of the output latch information on threshold levels.
on the selected pin). The exception is RA3, which is
Note: Changing the input threshold selection
input-only and its TRIS bit will always read as ‘1’.
should be performed while all peripheral
Example 12-1 shows how to initialize an I/O port.
modules are disabled. Changing the
Reading the PORTA register (Register 12-1) reads the threshold level during the time a module is
status of the pins, whereas writing to it will write to the active may inadvertently generate a tran-
PORT latch. All write operations are read-modify-write sition associated with an input pin, regard-
operations. Therefore, a write to a port implies that the less of the actual voltage level on that pin.
port pins are read, this value is modified and then
written to the PORT data latch (LATA). 12.1.6 ANALOG CONTROL
The ANSELA register (Register 12-4) is used to
12.1.2 DIRECTION CONTROL
configure the Input mode of an I/O pin to analog.
The TRISA register (Register 12-2) controls the Setting the appropriate ANSELA bit high will cause all
PORTA pin output drivers, even when they are being digital reads on the pin to be read as ‘0’ and allow
used as analog inputs. The user should ensure the bits analog functions on the pin to operate correctly.
in the TRISA register are maintained set when using
The state of the ANSELA bits has no effect on digital
them as analog inputs. I/O pins configured as analog
output functions. A pin with TRIS clear and ANSEL set
input always read ‘0’.
will still operate as a digital output, but the Input mode
12.1.3 OPEN-DRAIN CONTROL will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
The ODCONA register (Register 12-6) controls the affected port.
open-drain feature of the port. Open-drain operation is
independently selected for each pin. When an Note: The ANSELA bits default to the Analog
ODCONA bit is set, the corresponding port output mode after Reset. To use any pins as
becomes an open-drain driver capable of sinking digital general purpose or peripheral
current only. When an ODCONA bit is cleared, the inputs, the corresponding ANSEL bits
corresponding port output pin is the standard push-pull must be initialized to ‘0’ by user software.
drive capable of sourcing and sinking current.
EXAMPLE 12-1: INITIALIZING PORTA
12.1.4 SLEW RATE CONTROL BANKSEL PORTA ;
The SLRCONA register (Register 12-7) controls the CLRF PORTA ;Init PORTA
BANKSEL LATA ;Data Latch
slew rate option for each port pin. Slew rate control is
CLRF LATA ;
independently selectable for each port pin. When an BANKSEL ANSELA ;
SLRCONA bit is set, the corresponding port pin drive is CLRF ANSELA ;digital I/O
slew rate limited. When an SLRCONA bit is cleared, BANKSEL TRISA ;
The corresponding port pin drive slews at the maximum MOVLW B'00111000' ;Set RA<5:3> as inputs
rate possible. MOVWF TRISA ;and set RA<2:0> as
;outputs

PIC16(L)F1615/9
12.1.7 PORTA FUNCTIONS AND OUTPUT
PRIORITIES
Each pin defaults to the PORT latch data after Reset.
Other functions are selected with the peripheral pin
select logic. See Section13.0 “Peripheral Pin Select
(PPS) Module” for more information. Analog input
functions, such as ADC inputs, are not shown in the
peripheral pin select lists. These inputs are active when
the I/O pin is set for Analog mode using the ANSELA
register. Digital output functions may continue to
control the pin when in Analog mode.

PIC16(L)F1615/9
12.2 Register Definitions: PORTA
REGISTER 12-1: PORTA: PORTA REGISTER

U-0 U-0 R/W-x/x R/W-x/x R-x/x R/W-x/x R/W-x/x R/W-x/x
— — RA5 RA4 RA3 RA2 RA1 RA0
bit 7 bit 0
Legend:

bit 5-0 RA<5:0>: PORTA I/O Value bits(1)
1 = Port pin is > VIH
0 = Port pin is < VIL
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
REGISTER 12-2: TRISA: PORTA TRI-STATE REGISTER

U-0 U-0 R/W-1/1 R/W-1/1 U-1 R/W-1/1 R/W-1/1 R/W-1/1
— — TRISA5 TRISA4 —(1) TRISA2 TRISA1 TRISA0
bit 7 bit 0
Legend:

bit 5-4 TRISA<5:4>: PORTA Tri-State Control bit
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
bit 2-0 TRISA<2:0>: PORTA Tri-State Control bit
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output

PIC16(L)F1615/9
REGISTER 12-3: LATA: PORTA DATA LATCH REGISTER

— — LATA5 LATA4 LATA3 LATA2 LATA1 LATA0
bit 7 bit 0
Legend:

bit 5-0 LATA<5:0>: RA<5:0> Output Latch Value bits(1)
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
REGISTER 12-4: ANSELA: PORTA ANALOG SELECT REGISTER

U-0 U-0 U-0 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1
— — — ANSA4 — ANSA2 ANSA1 ANSA0
bit 7 bit 0
Legend:

bit 4 ANSA4: Analog Select between Analog or Digital Function on Pins RA4, respectively
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.
bit 2-0 ANSA<2:0>: Analog Select between Analog or Digital Function on Pins RA<2:0>, respectively
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.

PIC16(L)F1615/9
REGISTER 12-5: WPUA: WEAK PULL-UP PORTA REGISTER

U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
— — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0
bit 7 bit 0
Legend:

bit 5-0 WPUA<5:0>: Weak Pull-up Register bits(3)
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is configured as an output.
3: For the WPUA3 bit, when MCLRE = 1, weak pull-up is internally enabled, but not reported here.
REGISTER 12-6: ODCONA: PORTA OPEN-DRAIN CONTROL REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— — ODA5 ODA4 — ODA2 ODA1 ODA0
bit 7 bit 0
Legend:

bit 5-4 ODA<5:4>: PORTA Open-Drain Enable bits
For RA<5:4> pins, respectively
1 = Port pin operates as open-drain drive (sink current only)
0 = Port pin operates as standard push-pull drive (source and sink current)
bit 2-0 ODA<2:0>: PORTA Open-Drain Enable bits

PIC16(L)F1615/9
REGISTER 12-7: SLRCONA: PORTA SLEW RATE CONTROL REGISTER

U-0 U-0 R/W-1/1 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1
— — SLRA5 SLRA4 — SLRA2 SLRA1 SLRA0
bit 7 bit 0
Legend:

bit 5-4 SLRA<5:4>: PORTA Slew Rate Enable bits
1 = Port pin slew rate is limited
0 = Port pin slews at maximum rate
bit 2-0 SLRA<2:0>: PORTA Slew Rate Enable bits
REGISTER 12-8: INLVLA: PORTA INPUT LEVEL CONTROL REGISTER

U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
— — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0
bit 7 bit 0
Legend:

bit 5-0 INLVLA<5:0>: PORTA Input Level Select bits
1 = ST input used for PORT reads and interrupt-on-change
0 = TTL input used for PORT reads and interrupt-on-change

PIC16(L)F1615/9
TABLE 12-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Register
on Page
ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 152

INLVLA — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 154
LATA — — LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 152
ODCONA — — ODA5 ODA4 — ODA2 ODA1 ODA0 153
PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 151
SLRCONA — — SLRA5 SLRA4 — SLRA2 SLRA1 SLRA0 154
TRISA — — TRISA5 TRISA4 —(1) TRISA2 TRISA1 TRISA0 151
WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 153
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
TABLE 12-3: SUMMARY OF CONFIGURATION WORD WITH PORTA

Register
on Page

CONFIG1 69
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.

PIC16(L)F1615/9
12.3 PORTB Registers 12.3.5 INPUT THRESHOLD CONTROL
(PIC16(L)F1619 Only) The INLVLB register (Register 12-16) controls the input
voltage threshold for each of the available PORTB
12.3.1 DATA REGISTER input pins. A selection between the Schmitt Trigger
PORTB is a 4-bit wide, bidirectional port. The CMOS or the TTL Compatible thresholds is available.
corresponding data direction register is TRISB The input threshold is important in determining the
(Register 12-10). Setting a TRISB bit (= 1) will make value of a read of the PORTB register and also the level
the corresponding PORTB pin an input (i.e., disable the at which an interrupt-on-change occurs, if that feature
output driver). Clearing a TRISB bit (= 0) will make the is enabled. See 35.3 “DC Characteristics” for more
corresponding PORTB pin an output (i.e., enables information on threshold levels.
output driver and puts the contents of the output latch Note: Changing the input threshold selection
on the selected pin). Example 12-1 shows how to should be performed while all peripheral
initialize an I/O port. modules are disabled. Changing the
Reading the PORTB register (Register 12-9) reads the threshold level during the time a module is
status of the pins, whereas writing to it will write to the active may inadvertently generate a tran-
PORT latch. All write operations are read-modify-write sition associated with an input pin, regard-
operations. Therefore, a write to a port implies that the less of the actual voltage level on that pin.
port pins are read, this value is modified and then
written to the PORT data latch (LATB).
12.3.6 ANALOG CONTROL
The ANSELB register (Register 12-12) is used to
The TRISB register (Register 12-10) controls the configure the Input mode of an I/O pin to analog.
PORTB pin output drivers, even when they are being Setting the appropriate ANSELB bit high will cause all
used as analog inputs. The user should ensure the bits digital reads on the pin to be read as ‘0’ and allow
in the TRISB register are maintained set when using analog functions on the pin to operate correctly.
them as analog inputs. I/O pins configured as analog
input always read ‘0’. The state of the ANSELB bits has no effect on digital
output functions. A pin with TRIS clear and ANSEL set
12.3.3 OPEN-DRAIN CONTROL will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
The ODCONB register (Register 12-14) controls the
when executing read-modify-write instructions on the
open-drain feature of the port. Open-drain operation is
affected port.
independently selected for each pin. When an
ODCONB bit is set, the corresponding port output Note: The ANSELB bits default to the Analog
becomes an open-drain driver capable of sinking mode after Reset. To use any pins as
current only. When an ODCONB bit is cleared, the digital general purpose or peripheral
corresponding port output pin is the standard push-pull inputs, the corresponding ANSEL bits
drive capable of sourcing and sinking current. must be initialized to ‘0’ by user software.
12.3.4 SLEW RATE CONTROL

The SLRCONB register (Register 12-15) controls the
slew rate option for each port pin. Slew rate control is
independently selectable for each port pin. When an
SLRCONB bit is set, the corresponding port pin drive is
slew rate limited. When an SLRCONB bit is cleared,
The corresponding port pin drive slews at the maximum
rate possible.

PIC16(L)F1615/9
12.3.7 PORTB FUNCTIONS AND OUTPUT
PRIORITIES
the I/O pin is set for Analog mode using the ANSELB
register. Digital output functions continue to may
continue to control the pin when it is in Analog mode.

PIC16(L)F1615/9
12.4 Register Definitions: PORTB
REGISTER 12-9: PORTB: PORTB REGISTER

R/W-x/x R/W-x/x R/W-x/x R/W-x/x U-0 U-0 U-0 U-0
RB7 RB6 RB5 RB4 — — — —
bit 7 bit 0
Legend:
bit 7-4 RB<7:4>: PORTB I/O Value bits(1)

Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
return of actual I/O pin values.
REGISTER 12-10: TRISB: PORTB TRI-STATE REGISTER

R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0
TRISB7 TRISB6 TRISB5 TRISB4 — — — —
bit 7 bit 0
Legend:
bit 7-4 TRISB<7:4>: PORTB Tri-State Control bits

1 = PORTB pin configured as an input (tri-stated)
0 = PORTB pin configured as an output

PIC16(L)F1615/9
REGISTER 12-11: LATB: PORTB DATA LATCH REGISTER

R/W-x/u R/W-x/u R/W-x/u R/W-x/u U-0 U-0 U-0 U-0
LATB7 LATB6 LATB5 LATB4 — — — —
bit 7 bit 0
Legend:
bit 7-4 LATB<7:4>: RB<7:4> Output Latch Value bits(1)

Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
REGISTER 12-12: ANSELB: PORTB ANALOG SELECT REGISTER

U-0 U-0 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0
— — ANSB5 ANSB4 — — — —
bit 7 bit 0
Legend:

bit 5-4 ANSB<5:4>: Analog Select between Analog or Digital Function on Pins RB<5:4>, respectively
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

PIC16(L)F1615/9
REGISTER 12-13: WPUB: WEAK PULL-UP PORTB REGISTER(1),(2)

R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0
WPUB7 WPUB6 WPUB5 WPUB4 — — — —
bit 7 bit 0
Legend:
bit 7-4 WPUB<7:4>: Weak Pull-up Register bits

1 = Pull-up enabled
Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
REGISTER 12-14: ODCONB: PORTB OPEN-DRAIN CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0
ODB7 ODB6 ODB5 ODB4 — — — —
bit 7 bit 0
Legend:
bit 7-4 ODB<7:4>: PORTB Open-Drain Enable bits

For RB<7:4> pins, respectively

PIC16(L)F1615/9
REGISTER 12-15: SLRCONB: PORTB SLEW RATE CONTROL REGISTER

R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0
SLRB7 SLRB6 SLRB5 SLRB4 — — — —
bit 7 bit 0
Legend:
bit 7-4 SLRB<7:4>: PORTA Slew Rate Enable bits

REGISTER 12-16: INLVLB: PORTB INPUT LEVEL CONTROL REGISTER

R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0
INLVLB7 INLVLB6 INLVLB5 INLVLB4 — — — —
bit 7 bit 0
Legend:
bit 7-4 INLVLB<7:4>: PORTB Input Level Select bits

TABLE 12-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Register
on Page
ANSELB — — ANSB5 ANSB4 — — — — 159

INLVLB INLVLB7 INLVLB6 INLVLB5 INLVLB4 — — — — 161
LATB LATB7 LATB6 LATB5 LATB4 — — — — 159
ODCONB ODB7 ODB6 ODB5 ODB4 — — — — 160
PORTB RB7 RB6 RB5 RB4 — — — — 158
SLRCONB SLRB7 SLRB6 SLRB5 SLRB4 — — — — 161
TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 158
WPUB WPUB7 WPUB6 WPUB5 WPUB4 — — — — 160
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.

PIC16(L)F1615/9
TABLE 12-5: SUMMARY OF CONFIGURATION WORD WITH PORTB
Register
on Page
CONFIG1 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> — 69
7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTB.

PIC16(L)F1615/9
12.5 PORTC Registers 12.5.5 INPUT THRESHOLD CONTROL
The INLVLC register (Register 12-24) controls the input
12.5.1 DATA REGISTER
voltage threshold for each of the available PORTC
PORTC is an 8-bit wide, bidirectional port. The input pins. A selection between the Schmitt Trigger
corresponding data direction register is TRISC CMOS or the TTL Compatible thresholds is available.
(Register 12-18). Setting a TRISC bit (= 1) will make The input threshold is important in determining the
the corresponding PORTC pin an input (i.e., disable value of a read of the PORTC register and also the
the output driver). Clearing a TRISC bit (= 0) will make level at which an interrupt-on-change occurs, if that
the corresponding PORTC pin an output (i.e., enable feature is enabled. See 35.3 “DC Characteristics” for
the output driver and put the contents of the output more information on threshold levels.
latch on the selected pin). Example 12-1 shows how to
initialize an I/O port. Note: Changing the input threshold selection
should be performed while all peripheral
Reading the PORTC register (Register 12-17) reads the modules are disabled. Changing the
status of the pins, whereas writing to it will write to the threshold level during the time a module is
PORT latch. All write operations are read-modify-write active may inadvertently generate a tran-
operations. Therefore, a write to a port implies that the sition associated with an input pin, regard-
port pins are read, this value is modified and then written less of the actual voltage level on that pin.
to the PORT data latch (LATC).
12.5.6 ANALOG CONTROL
The ANSELC register (Register 12-20) is used to
The TRISC register (Register 12-18) controls the configure the Input mode of an I/O pin to analog.
PORTC pin output drivers, even when they are being Setting the appropriate ANSELC bit high will cause all
used as analog inputs. The user should ensure the bits in digital reads on the pin to be read as ‘0’ and allow
the TRISC register are maintained set when using them analog functions on the pin to operate correctly.
as analog inputs. I/O pins configured as analog input
always read ‘0’. The state of the ANSELC bits has no effect on digital out-
put functions. A pin with TRIS clear and ANSELC set will
12.5.3 OPEN-DRAIN CONTROL still operate as a digital output, but the Input mode will be
analog. This can cause unexpected behavior when exe-
The ODCONC register (Register 12-22) controls the cuting read-modify-write instructions on the affected
open-drain feature of the port. Open-drain operation is port.
independently selected for each pin. When an
ODCONC bit is set, the corresponding port output Note: The ANSELC bits default to the Analog
becomes an open-drain driver capable of sinking mode after Reset. To use any pins as
current only. When an ODCONC bit is cleared, the digital general purpose or peripheral
corresponding port output pin is the standard push-pull inputs, the corresponding ANSEL bits
drive capable of sourcing and sinking current. must be initialized to ‘0’ by user software.
12.5.4 SLEW RATE CONTROL 12.5.7 HIGH DRIVE STRENGTH PINS

The SLRCONC register (Register 12-23) controls the The HIDRVC register (Register 12-25) controls the
slew rate option for each port pin. Slew rate control is high drive options on the RC4 and RC5. When a
independently selectable for each port pin. When an HIDRVC bit is cleared, the pin has normal drive
SLRCONC bit is set, the corresponding port pin drive is strengths. When a HIDRVC bit is set, its respective pin
slew rate limited. When an SLRCONC bit is cleared, can sink or source currents up to 100mA.
The corresponding port pin drive slews at the maximum
rate possible.

PIC16(L)F1615/9
12.5.8 PORTC FUNCTIONS AND OUTPUT
PRIORITIES
the I/O pin is set for Analog mode using the ANSELC
register. Digital output functions continue to may
continue to control the pin when it is in Analog mode.

PIC16(L)F1615/9
12.6 Register Definitions: PORTC
REGISTER 12-17: PORTC: PORTC REGISTER

RC7(1) RC6(1) RC5 RC4 RC3 RC2 RC1 RC0
bit 7 bit 0
Legend:
bit 7-0 RC<7:0>: PORTC I/O Value bits(1, 2)

Note 1: RC<7:6> on PIC16(L)F1619 only.

2: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is
REGISTER 12-18: TRISC: PORTC TRI-STATE REGISTER

TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
bit 7 bit 0
Legend:
bit 7-0 TRISC<7:0>: PORTC Tri-State Control bits(1)

1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output
Note 1: TRISC<7:6> on PIC16(L)F1619 only.

PIC16(L)F1615/9
REGISTER 12-19: LATC: PORTC DATA LATCH REGISTER

LATC7(1) LATC6(1) LATC5 LATC4 LATC3 LATC2 LATC1 LATC0
bit 7 bit 0
Legend:
bit 7-0 LATC<7:0>: RC<7:0> Output Latch Value bits(1)

1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output
Note 1: LATC<7:6> on PIC16(L)F1619 only.

2: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is
REGISTER 12-20: ANSELC: PORTC ANALOG SELECT REGISTER

R/W-1/1 R/W-1/1 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
ANSC7(1) ANSC6(1) — — ANSC3 ANSC2 ANSC1 ANSC0
bit 7 bit 0
Legend:
bit 7-6 ANSC<7:6>: Analog Select between Analog or Digital Function on Pins RC<7:6>, respectively(1)
bit 3-0 ANSC<3:0>: Analog Select between Analog or Digital Function on Pins RC<3:0>, respectively
Note 1: ANSC<7:6> on PIC16(L)F1619 only.

2: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

PIC16(L)F1615/9
REGISTER 12-21: WPUC: WEAK PULL-UP PORTC REGISTER(2),(3)

(1) WPUC6(1)
WPUC7 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0
bit 7 bit 0
Legend:
bit 7-0 WPUC<7:0>: Weak Pull-up Register bits(1)

1 = Pull-up enabled
Note 1: WPUC<7:6> on PIC16(L)F1619 only.

2: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
REGISTER 12-22: ODCONC: PORTC OPEN-DRAIN CONTROL REGISTER

ODC7(1) ODC6(1) ODC5 ODC4 ODC3 ODC2 ODC1 ODC0
bit 7 bit 0
Legend:
bit 7-0 ODC<7:0>: PORTC Open-Drain Enable bits(1)

For RC<7:0> pins, respectively
Note 1: ODC<7:6> on PIC16(L)F1619 only.

PIC16(L)F1615/9
REGISTER 12-23: SLRCONC: PORTC SLEW RATE CONTROL REGISTER

SLRC7(1) SLRC6(1) SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0
bit 7 bit 0
Legend:
bit 7-0 SLRC<7:0>: PORTC Slew Rate Enable bits(1)

Note 1: SLRC<7:6> on PIC16(L)F1619 only.
REGISTER 12-24: INLVLC: PORTC INPUT LEVEL CONTROL REGISTER

(1)
INLVLC7 INLVLC6(1) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0
bit 7 bit 0
Legend:
bit 7-0 INLVLC<7:0>: PORTC Input Level Select bits(1)

Note 1: INLVLC<7:6> on PIC16(L)F1619 only.

PIC16(L)F1615/9
REGISTER 12-25: HIDRVC: PORTC HIGH DRIVE STRENGTH REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0
— — HIDC5 HIDC4 — — — —
bit 7 bit 0
Legend:

bit 5 HIDC5: High Current Drive Enable on Port C5
1 = High Drive enabled
0 = High Drive disabled
bit 4 HIDC4: High Current Drive Enable on Port C4
1 = High Drive enabled
0 = High Drive disabled
TABLE 12-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Register
on Page
ANSELC ANSC7(1) ANSC6(1) — — ANSC3 ANSC2 ANSC1 ANSC0 166

HIDRVC — — HIDC5 HIDC4 — — — — 169
INLVLC INLVLC7(1) INLVLC6(1) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 168
LATC LATC7(1) LATC6(1) LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 166
ODCONC ODC7(1) ODC6(1) ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 167
PORTC RC7(1) RC6(1) RC5 RC4 RC3 RC2 RC1 RC0 165
SLRCONC SLRC7(1) SLRC6(1) SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 168
TRISC TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 165
(1) (1)
WPUC WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 167
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.
Note 1: PIC16(L)F1619 only

PIC16(L)F1615/9
13.0 PERIPHERAL PIN SELECT 13.2 PPS Outputs
(PPS) MODULE Each I/O pin has a PPS register with which the pin out-
The Peripheral Pin Select (PPS) module connects put source is selected. With few exceptions, the port
peripheral inputs and outputs to the device I/O pins. TRIS control associated with that pin retains control
Only digital signals are included in the selections. All over the pin output driver. Peripherals that control the
analog inputs and outputs remain fixed to their pin output driver as part of the peripheral operation will
assigned pins. Input and output selections are indepen- override the TRIS control as needed. These peripher-
dent as shown in the simplified block diagram als include:
Figure 13-1. • EUSART (synchronous operation)
• MSSP (I2C)
13.1 PPS Inputs • CWG (auto-shutdown)
Each peripheral has a PPS register with which the Although every pin has its own PPS peripheral selec-
inputs to the peripheral are selected. Inputs include the tion register, the selections are identical for every pin as
device pins. shown in Register 13-2.
Multiple peripherals can operate from the same source Note: The notation “Rxy” is a place holder for the
simultaneously. Port reads always return the pin level pin identifier. For example, RA0PPS.
regardless of peripheral PPS selection. If a pin also has
associated analog functions, the ANSEL bit for that pin
must be cleared to enable the digital input buffer.
Although every peripheral has its own PPS input selec-
tion register, the selections are identical for every
peripheral as shown in Register 13-1.
Note: The notation “xxx” in the register name is
a place holder for the peripheral identifier.
For example, CLC1PPS.
FIGURE 13-1: SIMPLIFIED PPS BLOCK DIAGRAM

PPS Outputs
RA0PPS
PPS Inputs
abcPPS RA0
RA0
Peripheral abc
RxyPPS
Rxy
Peripheral xyz
RC7 RC7PPS
xyzPPS RC7

PIC16(L)F1615/9
13.3 Bidirectional Pins 13.5 PPS Permanent Lock
PPS selections for peripherals with bidirectional sig- The PPS can be permanently locked by setting the
nals on a single pin must be made so that the PPS input PPS1WAY Configuration bit. When this bit is set, the
and PPS output select the same pin. Peripherals that PPSLOCKED bit can only be cleared and set one time
have bidirectional signals include: after a device Reset. This allows for clearing the
• EUSART (synchronous operation) PPSLOCKED bit so that the input and output selections
can be made during initialization. When the
• MSSP (I2C)
PPSLOCKED bit is set after all selections have been
made, it will remain set and cannot be cleared until after
the next device Reset event.
Note: The I2C default input pins are I2C and
SMBus compatible and are the only pins
on the device with this compatibility. 13.6 Operation During Sleep
PPS input and output selections are unaffected by
13.4 PPS Lock Sleep.
The PPS includes a mode in which all input and output
selections can be locked to prevent inadvertent
13.7 Effects of a Reset
changes. PPS selections are locked by setting the A device Power-On-Reset (POR) clears all PPS input
PPSLOCKED bit of the PPSLOCK register. Setting and and output selections to their default values. All other
clearing this bit requires a special sequence as an extra Resets leave the selections unchanged. Default input
precaution against inadvertent changes. Examples of selections are shown in Table 13-1.
setting and clearing the PPSLOCKED bit are shown in
Example 13-1.
EXAMPLE 13-1: PPS LOCK/UNLOCK

SEQUENCE
; suspend interrupts
bcf INTCON,GIE
; BANKSEL PPSLOCK ; set bank
; required sequence, next 5 instructions
movlw 0x55
movwf PPSLOCK
movlw 0xAA
movwf PPSLOCK
; Set PPSLOCKED bit to disable writes or
; Clear PPSLOCKED bit to enable writes
bsf PPSLOCK,PPSLOCKED
; restore interrupts
bsf INTCON,GIE

PIC16(L)F1615/9
13.8 Register Definitions: PPS Input Selection
REGISTER 13-1: xxxPPS: PERIPHERAL xxx INPUT SELECTION
U-0 U-0 U-0 R/W-q/u R/W-q/u R/W-q/u R/W-q/u R/W-q/u
— — — xxxPPS<4:0>
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on peripheral

bit 4-3 xxxPPS<4:3>: Peripheral xxx Input PORT Selection bits
11 = Reserved. Do not use.
10 = Peripheral input is PORTC
01 = Peripheral input is PORTB (PIC16(L)F1619 only)
00 = Peripheral input is PORTA
bit 2-0 xxxPPS<2:0>: Peripheral xxx Input Bit Selection bits (1)
111 = Peripheral input is from PORTx Bit 7 (Rx7)
Note 1: See Table 13-1 for Reset values.
REGISTER 13-2: RxyPPS: PIN Rxy OUTPUT SOURCE SELECTION REGISTER

U-0 U-0 U-0 R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u
— — — RxyPPS<4:0>
bit 7 bit 0
Legend:

bit 4-0 RxyPPS<4:0>: Pin Rxy Output Source Selection bits
Selection code determines the output signal on the port pin.
See Table 13-2 for the selection codes

PIC16(L)F1615/9
REGISTER 13-3: PPSLOCK: PPS LOCK REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0
— — — — — — — PPSLOCKED
bit 7 bit 0
Legend:

bit 0 PPSLOCKED: PPS Locked bit
1 = PPS is locked. PPS selections can not be changed.
0 = PPS is not locked. PPS selections can be changed.

PIC16(L)F1615/9
TABLE 13-1: PPS INPUT REGISTER RESET VALUES

xxxPPS Default Pin Selection Reset Value (xxxPPS<4:0>)
Peripheral
Register PIC16(L)F1619 PIC16(L)F1615 PIC16(L)F1619 PIC16(L)F1615
Interrupt on change INTPPS RA2 RA2 00010 00010
Timer 0 clock T0CKIPPS RA2 RA2 00010 00010
Timer 1 gate T1GPPS RA4 RA4 00100 00100
Timer 3 clock T3CKIPPS RC5 RC5 10101 10101
Timer 3 gate T3GPPS RC4 RC4 10100 10100
Timer 5 gate T5GPPS RC3 RC3 10011 10011
CCP1 CCP1PPS RC5 RC5 10101 10101
CCP2 CCP2PPS RC3 RC3 10011 10011
CWG1 CWG1INPPS RA2 RA2 00010 00010
SPI and I2C clock SSPCLKPPS RB6 RC0 01110 10000
SPI and I2C data SSPDATPPS RB4 RC1 01100 10001
SPI slave select SSPSSPPS RC6 RC3 10110 10011
EUSART RX RXPPS RB5 RC5 01101 10101
EUSART CK CKPPS RB7 RC4 01111 10100
All CLCs CLCIN0PPS RC3 RC3 10011 10011
All CLCs CLCIN3PPS RA5 RA5 00101 00101
SMT1 Window Input SMTWIN1PPS RA5 RA5 00101 00101
SMT1 Signal Input SMTSIG1PPS RA4 RA4 00100 00100
SMT2 Window Input SMTWIN2PPS RA3 RA3 00101 00101
SMT2 Signal Input SMTSIG2PPS RC1 RC1 10001 10001
Angular Timer 1 Clock Input AT1INPPS RC5 RC5 10101 10101
Angular Timer 1 CC1 Input AT1CC1PPS RC3 RC3 10011 10011
Example: CCP1PPS = 0x13 selects RC3 as the CCP1 input.

PIC16(L)F1615/9
TABLE 13-2: AVAILABLE PORTS FOR OUTPUT BY PERIPHERAL(2)

PIC16(L)F1619 PIC16(L)F1615
RxyPPS<4:0> Output Signal
PORTA PORTB PORTC PORTA PORTC
11xxx Reserved ● ● ● ● ●
10111 Reserved ● ● ● ● ●
10110 Reserved ● ● ● ● ●
10101 Reserved ● ● ● ● ●
10100 Reserved ● ● ● ● ●
10011 DT ● ● ● ● ●
10010 TX/CK ● ● ● ● ●
(1)
10001 SDO/SDA ● ● ● ● ●
10000 SCK/SCL(1) ● ● ● ● ●
01111 PWM4_out ● ● ● ● ●
01110 PWM3_out ● ● ● ● ●
01101 CCP2_out ● ● ● ● ●
01100 CCP1_out ● ● ● ● ●
(1)
01011 CWG1OUTD ● ● ● ● ●
01010 CWG1OUTC(1) ● ● ● ● ●
(1)
01001 CWG1OUTB ● ● ● ● ●
01000 CWG1OUTA(1) ● ● ● ● ●
00111 LC4_out ● ● ● ● ●
00110 LC3_out ● ● ● ● ●
00101 LC2_out ● ● ● ● ●
00100 LC1_out ● ● ● ● ●
00011 ZCD1_out ● ● ● ● ●
00010 sync_C2OUT ● ● ● ● ●
00001 sync_C1OUT ● ● ● ● ●
00000 LATxy ● ● ● ● ●
Note 1: TRIS control is overridden by the peripheral as required.

2: Unsupported peripherals will output a ‘0’.

PIC16(L)F1615/9
TABLE 13-3: SUMMARY OF REGISTERS ASSOCIATED WITH THE PPS MODULE

Register
on page
PPSLOCK — — — — — — — PPSLOCKED 173
INTPPS — — — INTPPS<4:0> 172
T0CKIPPS — — — T0CKIPPS<4:0> 172
T1GPPS — — — T1GPPS<4:0> 172
T3GPPS — — — T3GPPS<4:0> 172
T5GPPS — — — T5GPPS<4:0> 172
CCP1PPS — — — CCP1PPS<4:0> 172
CCP2PPS — — — CCP2PPS<4:0> 172
CWG1INPPS — — — CWG1INPPS<4:0> 172
SSPCLKPPS — — — SSPCLKPPS<4:0> 172
SSPDATPPS — — — SSPDATPPS<4:0> 172
SSPSSPPS — — — SSPSSPPS<4:0> 172
RXPPS — — — RXPPS<4:0> 172
CKPPS — — — CKPPS<4:0> 172
CLCIN0PPS — — — CLCIN0PPS<4:0> 172
AT1INPPS — — — AT1INPPS<4:0> 172
ATCC1PPS — — — ATCC1PPS<4:0> 172
SMT1SIGPPS — — — SMT1SIGPPS<4:0> 172
SMT1WINPPS — — — SMT1WINPPS<4:0> 172
SMT2SIGPPS — — — SMT2SIGPPS<4:0> 172
SMT2WINPPS — — — SMT2WINPPS<4:0> 172
RA0PPS — — — RA0PPS<4:0> 172
RA1PPS — — — RA1PPS<4:0> 172
RA2PPS — — — RA2PPS<4:0> 172
RA4PPS — — — RA4PPS<4:0> 172
RA5PPS — — — RA5PPS<4:0> 172
RB4PPS(1) — — — RB4PPS<4:0> 172
RB5PPS(1) — — — RB5PPS<4:0> 172
RB6PPS(1) — — — RB6PPS<4:0> 172
RB7PPS(1) — — — RB7PPS<4:0> 172
RC0PPS — — — RC0PPS<4:0> 172

PIC16(L)F1615/9
TABLE 13-3: SUMMARY OF REGISTERS ASSOCIATED WITH THE PPS MODULE (CONTINUED)
Register
on page
RC1PPS — — — RC1PPS<4:0> 172
RC2PPS — — — RC2PPS<4:0> 172
RC3PPS — — — RC3PPS<4:0> 172
RC4PPS — — — RC4PPS<4:0> 172
RC5PPS — — — RC5PPS<4:0> 172
(1)
RC6PPS — — — RC6PPS<4:0> 172
RC7PPS(1) — — — RC7PPS<4:0> 172

PIC16(L)F1615/9
14.0 INTERRUPT-ON-CHANGE 14.3 Interrupt Flags
The PORTA, PORTB(1) and PORTC pins can be The IOCAFx, IOCBFx and IOCCFx bits located in the
configured to operate as Interrupt-On-Change (IOC) IOCAF, IOCBF and IOCCF registers, respectively, are
pins. An interrupt can be generated by detecting a signal status flags that correspond to the interrupt-on-change
that has either a rising edge or a falling edge. Any pins of the associated port. If an expected edge is
individual port pin, or combination of port pins, can be detected on an appropriately enabled pin, then the
configured to generate an interrupt. The interrupt-on- status flag for that pin will be set, and an interrupt will be
change module has the following features: generated if the IOCIE bit is set. The IOCIF bit of the
INTCON register reflects the status of all IOCAFx,
• Interrupt-on-Change enable (Master Switch)
IOCBFx and IOCCFx bits.
• Individual pin configuration
• Rising and falling edge detection 14.4 Clearing Interrupt Flags
• Individual pin interrupt flags
The individual status flags, (IOCAFx, IOCBFx and
Figure 14-1 is a block diagram of the IOC module.
IOCCFx bits), can be cleared by resetting them to zero.
If another edge is detected during this clearing
operation, the associated status flag will be set at the
Note 1: PORTB available on PIC16(L)F1619 only.
end of the sequence, regardless of the value actually
being written.
14.1 Enabling the Module
In order to ensure that no detected edge is lost while
To allow individual port pins to generate an interrupt, the clearing flags, only AND operations masking out known
IOCIE bit of the INTCON register must be set. If the changed bits should be performed. The following
IOCIE bit is disabled, the edge detection on the pin will sequence is an example of what should be performed.
still occur, but an interrupt will not be generated.
EXAMPLE 14-1: CLEARING INTERRUPT
14.2 Individual Pin Configuration FLAGS
(PORTA EXAMPLE)
For each port pin, a rising edge detector and a falling
edge detector are present. To enable a pin to detect a MOVLW 0xff
rising edge, the associated bit of the IOCxP register is XORWF IOCAF, W
set. To enable a pin to detect a falling edge, the ANDWF IOCAF, F
associated bit of the IOCxN register is set.
A pin can be configured to detect rising and falling 14.5 Operation in Sleep
edges simultaneously by setting both associated bits of
the IOCxP and IOCxN registers, respectively. The interrupt-on-change interrupt sequence will wake
the device from Sleep mode, if the IOCIE bit is set.
If an edge is detected while in Sleep mode, the IOCxF
register will be updated prior to the first instruction
executed out of Sleep.

PIC16(L)F1615/9
FIGURE 14-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE)
Rev. 10-000 037A
6/2/201 4
IOCANx D Q
R Q4Q1
edge
detect
RAx
to data bus
data bus = S
IOCAFx
IOCAPx D Q
0 or 1
D Q
R
write IOCAFx
IOCIE
Q2
IOC interrupt
to CPU core
from all other
IOCnFx individual
pin detectors
FOSC
Q1 Q1 Q1
Q2 Q2 Q2
Q3 Q3 Q3
Q4 Q4 Q4
Q4Q1 Q4Q1 Q4Q1 Q4Q1

PIC16(L)F1615/9
14.6 Register Definitions: Interrupt-on-Change Control
REGISTER 14-1: IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0
bit 7 bit 0
Legend:

bit 5-0 IOCAP<5:0>: Interrupt-on-Change PORTA Positive Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCAFx bit and IOCIF flag will be set upon
detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
REGISTER 14-2: IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0
bit 7 bit 0
Legend:

bit 5-0 IOCAN<5:0>: Interrupt-on-Change PORTA Negative Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCAFx bit and IOCIF flag will be set upon
detecting an edge.
REGISTER 14-3: IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER

U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
— — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware

bit 5-0 IOCAF<5:0>: Interrupt-on-Change PORTA Flag bits
1 = An enabled change was detected on the associated pin.
Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling edge was
detected on RAx.
0 = No change was detected, or the user cleared the detected change.

PIC16(L)F1615/9
REGISTER 14-4: IOCBP: INTERRUPT-ON-CHANGE PORTB POSITIVE EDGE REGISTER(1)

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0
IOCBP7 IOCBP6 IOCBP5 IOCBP4 — — — —
bit 7 bit 0
Legend:
bit 7-4 IOCBP<7:4>: Interrupt-on-Change PORTB Positive Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCBFx bit and IOCIF flag will be set upon
detecting an edge.
REGISTER 14-5: IOCBN: INTERRUPT-ON-CHANGE PORTB NEGATIVE EDGE REGISTER(1)

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0
IOCBN7 IOCBN6 IOCBN5 IOCBN4 — — — —
bit 7 bit 0
Legend:
bit 7-4 IOCBN<7:4>: Interrupt-on-Change PORTB Negative Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCBFx bit and IOCIF flag will be set upon
detecting an edge.
REGISTER 14-6: IOCBF: INTERRUPT-ON-CHANGE PORTB FLAG REGISTER(1)

R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 U-0 U-0 U-0 U-0
IOCBF7 IOCBF6 IOCBF5 IOCBF4 — — — —
bit 7 bit 0
Legend:
bit 7-4 IOCBF<7:4>: Interrupt-on-Change PORTB Flag bits

Set when IOCBPx = 1 and a rising edge was detected on RBx, or when IOCBNx = 1 and a falling edge was
detected on RBx.

PIC16(L)F1615/9
REGISTER 14-7: IOCCP: INTERRUPT-ON-CHANGE PORTC POSITIVE EDGE REGISTER

IOCCP7(1) IOCCP6(1) IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0
bit 7 bit 0
Legend:
bit 7-0 IOCCP<7:0>: Interrupt-on-Change PORTC Positive Edge Enable bits(1)

1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCCFx bit and IOCIF flag will be set upon
detecting an edge.
Note 1: IOCCP<7:6> available on PIC16(L)F1619 only.
REGISTER 14-8: IOCCN: INTERRUPT-ON-CHANGE PORTC NEGATIVE EDGE REGISTER(1)

(1) (1)
IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0
bit 7 bit 0
Legend:
bit 7-0 IOCCN<7:0>: Interrupt-on-Change PORTC Negative Edge Enable bits(1)

1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCCFx bit and IOCIF flag will be set upon
detecting an edge.
Note 1: IOCCN<7:6> available on PIC16(L)F1619 only.
REGISTER 14-9: IOCCF: INTERRUPT-ON-CHANGE PORTC FLAG REGISTER(1)

R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
IOCCF(1) IOCCF6(1) IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0
bit 7 bit 0
Legend:
bit 7-0 IOCCF<7:0>: Interrupt-on-Change PORTC Flag bits(1)

Set when IOCCPx = 1 and a rising edge was detected on RCx, or when IOCCNx = 1 and a falling edge was
detected on RCx.
Note 1: IOCCF<7:6> available on PIC16(L)F1619 only.

PIC16(L)F1615/9
TABLE 14-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE
Register
on Page
IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 180
IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 180
IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 180
IOCBF(2) IOCBF7 IOCBF6 IOCBF5 IOCBF4 — — — — 181
(2)
IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 — — — — 181
IOCBP(2) IOCBP7 IOCBP6 IOCBP5 IOCBP4 — — — — 181
IOCCF IOCCF7(2) IOCCF6(2) IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 182
IOCCN IOCCN7(2) IOCCN6(2) IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 182
(2) (2)
IOCCP IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 182
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change.

PIC16(L)F1615/9
15.0 FIXED VOLTAGE REFERENCE The ADFVR<1:0> bits of the FVRCON register are
used to enable and configure the gain amplifier settings
(FVR) for the reference supplied to the ADC module. Refer-
The Fixed Voltage Reference (FVR) is a stable voltage ence Section17.0 “Analog-to-Digital Converter
reference, independent of VDD, with a nominal output (ADC) Module” for additional information.
level (VFVR) of 1.024V. The output of the FVR can be The CDAFVR<1:0> bits of the FVRCON register are
configured to supply a reference voltage to the used to enable and configure the gain amplifier settings
following: for the reference supplied to the comparator modules.
• ADC input channel Reference Section19.0 “Comparator Module” for
• Comparator positive input additional information.
• Comparator negative input To minimize current consumption when the FVR is
disabled, the FVR buffers should be turned off by
The FVR can be enabled by setting the FVREN bit of
clearing the Buffer Gain Selection bits.
the FVRCON register.
15.1 Independent Gain Amplifier 15.2 FVR Stabilization Period

When the Fixed Voltage Reference module is enabled, it
The output of the FVR supplied to the peripherals,
requires time for the reference and amplifier circuits to
(listed above), is routed through a programmable gain
stabilize. Once the circuits stabilize and are ready for use,
amplifier. Each amplifier can be programmed for a gain
the FVRRDY bit of the FVRCON register will be set. See
of 1x, 2x or 4x, to produce the three possible voltage
Figure 36-62: FVR Stabilization Period, PIC16LF1614/8
levels.
Only.
FIGURE 15-1: VOLTAGE REFERENCE BLOCK DIAGRAM
Rev. 10-000 053C

12/9/201 3
2
ADFVR<1:0>
1x
FVR_buffer1
2x
4x (To ADC Module)
2
CDAFVR<1:0>
1x FVR_buffer2
2x (To Comparators
4x and DAC)
FVREN
+
_ FVRRDY
Note 1
Note 1: Any peripheral requiring the Fixed Reference (See Table 15-1)

PIC16(L)F1615/9
TABLE 15-1: PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR)

Peripheral Conditions Description
HFINTOSC FOSC<2:0> = 010 and INTOSC is active and device is not in Sleep.
IRCF<3:0> = 000x
BOREN<1:0> = 11 BOR always enabled.
BOR BOREN<1:0> = 10 and BORFS = 1 BOR disabled in Sleep mode, BOR Fast Start enabled.
BOREN<1:0> = 01 and BORFS = 1 BOR under software control, BOR Fast Start enabled.
LDO All PIC16F1615/9 devices, when The device runs off of the Low-Power Regulator when in
VREGPM = 1 and not in Sleep Sleep mode.

PIC16(L)F1615/9
15.3 Register Definitions: FVR Control
REGISTER 15-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER

R/W-0/0 R-q/q R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
FVREN(1) FVRRDY(2) TSEN(3) TSRNG(3) CDAFVR<1:0>(1) ADFVR<1:0>(1)
bit 7 bit 0
Legend:
bit 7 FVREN: Fixed Voltage Reference Enable bit(1)

1 = Fixed Voltage Reference is enabled
0 = Fixed Voltage Reference is disabled
bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(2)
1 = Fixed Voltage Reference output is ready for use
0 = Fixed Voltage Reference output is not ready or not enabled
bit 5 TSEN: Temperature Indicator Enable bit(3)
1 = Temperature Indicator is enabled
0 = Temperature Indicator is disabled
bit 4 TSRNG: Temperature Indicator Range Selection bit(3)
1 = VOUT = VDD - 4VT (High Range)
0 = VOUT = VDD - 2VT (Low Range)
bit 3-2 CDAFVR<1:0>: Comparator FVR Buffer Gain Selection bits(1)
11 = Comparator FVR Buffer Gain is 4x, with output VCDAFVR = 4x VFVR(4)
10 = Comparator FVR Buffer Gain is 2x, with output VCDAFVR = 2x VFVR(4)
01 = Comparator FVR Buffer Gain is 1x, with output VCDAFVR = 1x VFVR
00 = Comparator FVR Buffer is off
bit 1-0 ADFVR<1:0>: ADC FVR Buffer Gain Selection bit(1)
11 = ADC FVR Buffer Gain is 4x, with output VADFVR = 4x VFVR(4)
10 = ADC FVR Buffer Gain is 2x, with output VADFVR = 2x VFVR(4)
01 = ADC FVR Buffer Gain is 1x, with output VADFVR = 1x VFVR
00 = ADC FVR Buffer is off
Note 1: To minimize current consumption when the FVR is disabled, the FVR buffers should be turned off by clear-
ing the Buffer Gain Selection bits.
2: FVRRDY is always ‘1’ for the PIC16LF1615/9 devices.
3: See Section16.0 “Temperature Indicator Module” for additional information.
4: Fixed Voltage Reference output cannot exceed VDD.
TABLE 15-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE FIXED VOLTAGE REFERENCE
Register
on page
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 186
Legend: Shaded cells are unused by the Fixed Voltage Reference module.

PIC16(L)F1615/9
16.0 TEMPERATURE INDICATOR FIGURE 16-1: TEMPERATURE CIRCUIT
MODULE DIAGRAM
This family of devices is equipped with a temperature Rev. 10-000069A

7/31/2013
circuit designed to measure the operating temperature VDD

of the silicon die. The circuit’s range of operating
temperature falls between -40°C and +85°C. The
output is a voltage that is proportional to the device TSEN
temperature. The output of the temperature indicator is
internally connected to the device ADC.
The circuit may be used as a temperature threshold
detector or a more accurate temperature indicator, TSRNG
depending on the level of calibration performed. A one-
point calibration allows the circuit to indicate a
temperature closely surrounding that point. A two-point
calibration allows the circuit to sense the entire range
of temperature more accurately. Reference Application
VOUT
Note AN1333, “Use and Calibration of the Internal To ADC
Temperature Indicator” (DS01333) for more details Temp. Indicator
regarding the calibration process.
16.1 Circuit Operation

Figure 16-1 shows a simplified block diagram of the
temperature circuit. The proportional voltage output is 16.2 Minimum Operating VDD
achieved by measuring the forward voltage drop across When the temperature circuit is operated in low range,
multiple silicon junctions. the device may be operated at any operating voltage
Equation 16-1 describes the output characteristics of that is within specifications.
the temperature indicator. When the temperature circuit is operated in high range,
the device operating voltage, VDD, must be high
EQUATION 16-1: VOUT RANGES enough to ensure that the temperature circuit is
correctly biased.
High Range: VOUT = VDD - 4VT Table 16-1 shows the recommended minimum VDD vs.
range setting.
Low Range: VOUT = VDD - 2VT
TABLE 16-1: RECOMMENDED VDD VS.
RANGE
The temperature sense circuit is integrated with the
Fixed Voltage Reference (FVR) module. See Min. VDD, TSRNG = 1 Min. VDD, TSRNG = 0
Section15.0 “Fixed Voltage Reference (FVR)” for 3.6V 1.8V
more information.
The circuit is enabled by setting the TSEN bit of the 16.3 Temperature Output
FVRCON register. When disabled, the circuit draws no
current. The output of the circuit is measured using the internal
Analog-to-Digital Converter. A channel is reserved for
The circuit operates in either high or low range. The high
the temperature circuit output. Refer to
range, selected by setting the TSRNG bit of the
Section17.0 “Analog-to-Digital Converter (ADC)
FVRCON register, provides a wider output voltage. This
Module” for detailed information.
provides more resolution over the temperature range,
but may be less consistent from part to part. This range
requires a higher bias voltage to operate and thus, a 16.4 ADC Acquisition Time
higher VDD is needed. To ensure accurate temperature measurements, the
The low range is selected by clearing the TSRNG bit of user must wait at least 200 s after the ADC input
the FVRCON register. The low range generates a lower multiplexer is connected to the temperature indicator
voltage drop and thus, a lower bias voltage is needed to output before the conversion is performed. In addition,
operate the circuit. The low range is provided for low the user must wait 200 s between sequential
voltage operation. conversions of the temperature indicator output.

PIC16(L)F1615/9
TABLE 16-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR
Register
on page
Legend: Shaded cells are unused by the temperature indicator module.

PIC16(L)F1615/9
17.0 ANALOG-TO-DIGITAL The ADC voltage reference is software selectable to be
either internally generated or externally supplied.
CONVERTER (ADC) MODULE
The ADC can generate an interrupt upon completion of
The Analog-to-Digital Converter (ADC) allows a conversion. This interrupt can be used to wake-up the
conversion of an analog input signal to a 10-bit binary device from Sleep.
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESH:ADRESL register pair).
Figure 17-1 shows the block diagram of the ADC.
FIGURE 17-1: ADC BLOCK DIAGRAM

ADPREF<1:0> Rev. 10-000033F
11/15/2016
FVR_buffer1 11 Positive
VREF+ pin Reference
10 Select
Reserved 01
00
VDD
VSS ADCS<2:0>
AN0
ANa Vref- Vref+
External .
Channel . FOSC/n Fosc
. Divider FOSC
Inputs ADC
ANz ADC_clk
sampled Clock
VSS input Select FRC
FRC
Temp Indicator
Internal
Channel DACx_output ADC CLOCK SOURCE
Inputs
FVR_buffer1 ADC
Sample Circuit
CHS<4:0>
ADFM
set bit ADIF
10
complete 10-bit Result
Write to bit
GO/DONE
GO/DONE Q1 16
start
Q4
ADRESH ADRESL
Q2 Enable
Trigger Select
TRIGSEL<3:0> ADON
. . . VSS
Trigger Sources
AUTO CONVERSION
TRIGGER

PIC16(L)F1615/9
17.1 ADC Configuration 17.1.3 ADC VOLTAGE REFERENCE
When configuring and using the ADC the following The ADC module uses a positive and a negative
functions must be considered: voltage reference. The positive reference is labeled
ref+ and the negative reference is labeled ref-.
• Port configuration
The positive voltage reference (ref+) is selected by the
• Channel selection
ADPREF bits in the ADCON1 register. The positive
• ADC voltage reference selection voltage reference source can be:
• ADC conversion clock source
• VREF+ pin
• Interrupt control
• VDD
• Result formatting
• FVR_buffer1
17.1.1 PORT CONFIGURATION The negative voltage reference (ref-) source is:
The ADC can be used to convert both analog and • VSS
digital signals. When converting analog signals, the I/O
pin should be configured for analog by setting the 17.1.4 CONVERSION CLOCK
associated TRIS and ANSEL bits. Refer to The source of the conversion clock is software select-
Section12.0 “I/O Ports” for more information. able via the ADCS bits of the ADCON1 register. There
Note: Analog voltages on any pin that is defined are seven possible clock options:
as a digital input may cause the input • FOSC/2
buffer to conduct excess current. • FOSC/4
• FOSC/8
17.1.2 CHANNEL SELECTION
• FOSC/16
There are up to 15 channel selections available: • FOSC/32
• AN<11:0> pins (PIC16(L)F1619 only) • FOSC/64
• AN<7:0> pins (PIC16(L)F1615 only) • FRC (internal RC oscillator)
• Temperature Indicator The time to complete one bit conversion is defined as
• DAC1_output TAD. One full 10-bit conversion requires 11.5 TAD
• FVR_buffer1 periods as shown in Figure 17-2.
The CHS bits of the ADCON0 register determine which For correct conversion, the appropriate TAD specifica-
channel is connected to the sample and hold circuit. tion must be met. Refer to the ADC conversion require-
When changing channels, a delay (TACQ) is required ments in Section35.0 “Electrical Specifications” for
before starting the next conversion. Refer to more information. Table 17-1 gives examples of appro-
Section17.2.6 “ADC Conversion Procedure” for priate ADC clock selections.
more information. Note: Unless using the FRC, any changes in the
Note: It is recommended that when switching system clock frequency will change the
from an ADC channel of a higher voltage ADC clock frequency, which may
to a channel of a lower voltage, the soft- adversely affect the ADC result.
ware selects the VSS channel before
switching to the channel of the lower volt-
age. If the ADC does not have a dedicated
VSS input channel, the VSS selection
(DAC1R<4:0> = b'00000') through the
DAC output channel can be used. If the
DAC is in use, a free input channel can be
connected to VSS, and can be used in
place of the DAC.

PIC16(L)F1615/9
TABLE 17-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
ADC Clock Period (TAD) Device Frequency (FOSC)
ADC
ADCS<2:0
Clock 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz
>
Source
Fosc/2 000 100 ns 125 ns 250 ns 500 ns 2.0 s
Fosc/4 100 200 ns 250 ns 500 ns 1.0 s 4.0 s
Fosc/8 001 400 ns 500 ns 1.0 s 2.0 s 8.0 s
Fosc/16 101 800 ns 1.0 s 2.0 s 4.0 s 16.0 s
Fosc/32 010 1.6 s 2.0 s 4.0 s 8.0 s 32.0 s
Fosc/64 110 3.2 s 4.0 s 8.0 s 16.0 s 64.0 s
FRC x11 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s
Legend: Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 1.7 us.
2: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the
conversion will be performed during Sleep.
3: The TAD period when using the FRC clock source can fall within a specified range, (see TAD parameter).
The TAD period when using the FOSC-based clock source can be configured for a more precise TAD period.
However, the FRC clock source must be used when conversions are to be performed with the device in
Sleep mode.
FIGURE 17-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES

Rev. 10-000035A
7/30/2013
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
THCD
Conversion Starts
TACQ On the following cycle:
Holding capacitor disconnected
from analog input (THCD).
ADRESH:ADRESL is loaded,
GO bit is cleared,
Set GO bit ADIF bit is set,
holding capacitor is reconnected to analog input.
Enable ADC (ADON bit)
and
Select channel (ACS bits)

PIC16(L)F1615/9
17.1.5 INTERRUPTS 17.1.6 RESULT FORMATTING
The ADC module allows for the ability to generate an The 10-bit ADC conversion result can be supplied in
interrupt upon completion of an Analog-to-Digital two formats, left justified or right justified. The ADFM bit
conversion. The ADC Interrupt Flag is the ADIF bit in of the ADCON1 register controls the output format.
the PIR1 register. The ADC Interrupt Enable is the Figure 17-3 shows the two output formats.
ADIE bit in the PIE1 register. The ADIF bit must be
cleared in software.
Note 1: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
2: The ADC operates during Sleep only
when the FRC oscillator is selected.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP instruc-
tion is always executed. If the user is attempting to
wake-up from Sleep and resume in-line code execu-
tion, the GIE and PEIE bits of the INTCON register
must be disabled. If the GIE and PEIE bits of the
INTCON register are enabled, execution will switch to
the Interrupt Service Routine.
FIGURE 17-3: 10-BIT ADC CONVERSION RESULT FORMAT
Rev. 10-000 054A

12/21/201 6
ADRESH ADRESL
(ADFM = 0) MSb LSb

bit 7 bit 0 bit 7 bit 0
10-bit ADC Result Unimplemented: Read as ‘0’
(ADFM = 1) MSb LSb

bit 7 bit 0 bit 7 bit 0
Unimplemented: Read as ‘0’ 10-bit ADC Result

PIC16(L)F1615/9
17.2 ADC Operation 17.2.4 ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This
17.2.1 STARTING A CONVERSION requires the ADC clock source to be set to the FRC
To enable the ADC module, the ADON bit of the option. Performing the ADC conversion during Sleep
ADCON0 register must be set to a ‘1’. Setting the GO/ can reduce system noise. If the ADC interrupt is
DONE bit of the ADCON0 register to a ‘1’ will start the enabled, the device will wake-up from Sleep when the
Analog-to-Digital conversion. conversion completes. If the ADC interrupt is disabled,
the ADC module is turned off after the conversion com-
Note: The GO/DONE bit should not be set in the
pletes, although the ADON bit remains set.
same instruction that turns on the ADC.
Refer to Section17.2.6 “ADC Conver- When the ADC clock source is something other than
sion Procedure”. FRC, a SLEEP instruction causes the present conver-
sion to be aborted and the ADC module is turned off,
17.2.2 COMPLETION OF A CONVERSION although the ADON bit remains set.
When the conversion is complete, the ADC module will: 17.2.5 AUTO-CONVERSION TRIGGER
• Clear the GO/DONE bit The auto-conversion trigger allows periodic ADC mea-
• Set the ADIF Interrupt Flag bit surements without software intervention. When a rising
• Update the ADRESH and ADRESL registers with edge of the selected source occurs, the GO/DONE bit
new conversion result is set by hardware.
The auto-conversion trigger source is selected with the
17.2.3 TERMINATING A CONVERSION TRIGSEL<4:0> bits of the ADCON2 register.
If a conversion must be terminated before completion, Using the auto-conversion trigger does not assure
the GO/DONE bit can be cleared in software. The proper ADC timing. It is the user’s responsibility to
ADRESH and ADRESL registers will be updated with ensure that the ADC timing requirements are met.
the partially complete Analog-to-Digital conversion
sample. Incomplete bits will match the last bit See Table 17-2 for auto-conversion sources.
converted.
Note: A device Reset forces all registers to their TABLE 17-2: AUTO-CONVERSION
Reset state. Thus, the ADC module is SOURCES
turned off and any pending conversion is Source Peripheral Signal Name
terminated.
Timer0 T0_overflow
Timer1 T1_overflow
Timer2 TMR2_postscaled
Comparator C1 C1_OUT_sync
SMT1 SMT1_CPW
SMT1 SMT1_CPR
SMT1 SMT1_PR
SMT2 SMT2_CPW
SMT2 SMT2_CPR
SMT2 SMT2_PR
CCP1 CCP1_out
CCP2 CCP2_out

PIC16(L)F1615/9
17.2.6 ADC CONVERSION PROCEDURE EXAMPLE 17-1: ADC CONVERSION
This is an example procedure for using the ADC to ;This code block configures the ADC
perform an Analog-to-Digital conversion: ;for polling, Vdd and Vss references, FRC
;oscillator and AN0 input.
1. Configure Port:
;
• Disable pin output driver (Refer to the TRIS ;Conversion start & polling for completion
register) ; are included.
• Configure pin as analog (Refer to the ANSEL ;
register) BANKSEL ADCON1 ;
MOVLW B’11110000’ ;Right justify, FRC
• Disable weak pull-ups either globally (Refer ;oscillator
to the OPTION_REG register) or individually MOVWF ADCON1 ;Vdd and Vss Vref+
(Refer to the appropriate WPUx register) BANKSEL TRISA ;
2. Configure the ADC module: BSF TRISA,0 ;Set RA0 to input
BANKSEL WPUA ;
• Select ADC conversion clock
BCF WPUA,0 ;Disable weak
• Configure voltage reference ;pull-up on RA0
• Select ADC input channel BANKSEL ANSEL ;
• Turn on ADC module BSF ANSEL,0 ;Set RA0 to analog
BANKSEL ADCON0 ;
3. Configure ADC interrupt (optional): MOVLW B’00000001’ ;Select channel AN0
• Clear ADC interrupt flag MOVWF ADCON0 ;Turn ADC On
• Enable ADC interrupt CALL SampleTime ;Acquisiton delay
BSF ADCON0,ADGO ;Start conversion
• Enable peripheral interrupt
BTFSC ADCON0,ADGO ;Is conversion done?
• Enable global interrupt(1) GOTO $-1 ;No, test again
4. Wait the required acquisition time(2). BANKSEL ADRESH ;
5. Start conversion by setting the GO/DONE bit. MOVF ADRESH,W ;Read upper 2 bits
MOVWF RESULTHI ;store in GPR space
6. Wait for ADC conversion to complete by one of BANKSEL ADRESL ;
the following: MOVF ADRESL,W ;Read lower 8 bits
• Polling the GO/DONE bit MOVWF RESULTLO ;Store in GPR space
• Waiting for the ADC interrupt (interrupts
enabled)
7. Read ADC Result.
8. Clear the ADC interrupt flag (required if interrupt
is enabled).
Note 1: The global interrupt can be disabled if the

user is attempting to wake-up from Sleep
and resume in-line code execution.
2: Refer to Section17.4 “ADC Acquisition
Requirements”.

PIC16(L)F1615/9
17.3 Register Definitions: ADC Control
REGISTER 17-1: ADCON0: ADC CONTROL REGISTER 0

U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— CHS<4:0> GO/DONE ADON
bit 7 bit 0
Legend:

bit 6-2 CHS<4:0>: Analog Channel Select bits
11111 = FVR (Fixed Voltage Reference) Buffer 1 Output(3)
11110 = DAC (Digital-to-Analog Converter)(2)
11101 = Temperature Indicator(1)
11100 = Reserved. No channel connected.
•
•
•
01011 = AN11(4)
01010 = AN10(4)
01001 = AN9(4)
01000 = AN8(4)
00111 = AN7
00110 = AN6
00101 = AN5
00100 = AN4
00011 = AN3
00010 = AN2
00001 = AN1
00000 = AN0
bit 1 GO/DONE: ADC Conversion Status bit
1 = ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle.
This bit is automatically cleared by hardware when the ADC conversion has completed.
0 = ADC conversion completed/not in progress
bit 0 ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current
Note 1: See Section16.0 “Temperature Indicator Module”.
2: See Section18.0 “8-bit Digital-to-Analog Converter (DAC1) Module” for more information.
3: See Section15.0 “Fixed Voltage Reference (FVR)” for more information.
4: AN<11:8> available on PIC16(L)F1619 only.

PIC16(L)F1615/9
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0
ADFM ADCS<2:0> — — ADPREF<1:0>
bit 7 bit 0
Legend:
bit 7 ADFM: ADC Result Format Select bit

1 = Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is
loaded.
0 = Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is
loaded.
bit 6-4 ADCS<2:0>: ADC Conversion Clock Select bits
111 = FRC (clock supplied from an internal RC oscillator)
110 = FOSC/64
101 = FOSC/16
100 = FOSC/4
011 = FRC (clock supplied from an internal RC oscillator)
010 = FOSC/32
001 = FOSC/8
000 = FOSC/2
bit 1-0 ADPREF<1:0>: ADC Positive Voltage Reference Configuration bits
11 = VRPOS is connected to internal Fixed Voltage Reference (FVR)
10 = VRPOS is connected to external VREF+ pin(1)
01 = Reserved
00 = VRPOS is connected to VDD
Note 1: When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltage
specification exists. See SectionTABLE 35-13: “Analog-to-Digital Converter (ADC)
Characteristics(1,2,3)” for details.

PIC16(L)F1615/9

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0
TRIGSEL<4:0>(1) — — —
bit 7 bit 0
Legend:
bit 7-3 TRIGSEL<4:0>: Auto-Conversion Trigger Selection bits(1)

11111 = Reserved
•
•
•
10101 = Reserved
10100 = AT1_cmp3
10011 = AT1_cmp2
10010 = AT1_cmp1
10001 = CLC4OUT
10000 = CLC3OUT
01111 = CLC2OUT
01110 = CLC1OUT
01101 = TMR5_overflow
01011 = SMT2_match
01010 =SMT1_match
00111 = C2_OUT_sync
00110 = C1_OUT_sync
00100 = T1_overflow(2)
00011 = T0_overflow(2)
00010 = CCP2_out
00001 = CCP1_out
00000 = No auto-conversion trigger selected
Note 1: This is a rising edge sensitive input for all sources.

2: Signal also sets its corresponding interrupt flag.

PIC16(L)F1615/9
REGISTER 17-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0

ADRES<9:2>
bit 7 bit 0
Legend:
bit 7-0 ADRES<9:2>: ADC Result Register bits

Upper eight bits of 10-bit conversion result
REGISTER 17-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0

ADRES<1:0> — — — — — —
bit 7 bit 0
Legend:

Lower two bits of 10-bit conversion result
bit 5-0 Reserved: Do not use.

PIC16(L)F1615/9
REGISTER 17-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1

— — — — — — ADRES<9:8>
bit 7 bit 0
Legend:
bit 7-2 Reserved: Do not use.

Upper two bits of 10-bit conversion result
REGISTER 17-7: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1

ADRES<7:0>
bit 7 bit 0
Legend:

Lower eight bits of 10-bit conversion result

PIC16(L)F1615/9
17.4 ADC Acquisition Requirements source impedance is decreased, the acquisition time
may be decreased. After the analog input channel is
For the ADC to meet its specified accuracy, the charge selected (or changed), an ADC acquisition must be
holding capacitor (CHOLD) must be allowed to fully done before the conversion can be started. To calculate
charge to the input channel voltage level. The Analog the minimum acquisition time, Equation 17-1 may be
Input model is shown in Figure 17-4. The source used. This equation assumes that 1/2 LSb error is used
impedance (RS) and the internal sampling switch (RSS) (1,024 steps for the ADC). The 1/2 LSb error is the
impedance directly affect the time required to charge maximum error allowed for the ADC to meet its
the capacitor CHOLD. The sampling switch (RSS) specified resolution.
impedance varies over the device voltage (VDD), refer
to Figure 17-4. The maximum recommended
impedance for analog sources is 10 k. As the
EQUATION 17-1: ACQUISITION TIME EXAMPLE
Assumptions: Temperature = 50°C and external impedance of 10k  5.0V V DD
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2µs + T C +   Temperature - 25°C   0.05µs/°C  
The value for TC can be approximated with the following equations:
V AP P LI ED  1 – -------------------------- = V CHOLD
1
;[1] VCHOLD charged to within 1/2 lsb
n+1 
2 –1
–TC
 ----------
RC
V AP P LI ED  1 – e  = V CHOLD ;[2] VCHOLD charge response to VAPPLIED
 
– Tc
 ---------
V AP P LI ED  1 – e  = V A PP LIE D  1 – -------------------------- ;combining [1] and [2]
RC 1
   n+1 
2 –1
Note: Where n = number of bits of the ADC.
Solving for TC:
T C = – C HOLD  R IC + R SS + R S  ln(1/2047)
= – 12.5pF  1k  + 7k  + 10k   ln(0.0004885)
= 1.12 µs
Therefore:
T A CQ = 2µs + 1.12 µs +   50°C- 25°C   0.05 µs/°C  
= 4.37µs
Note 1: The reference voltage (VRPOS) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.

PIC16(L)F1615/9
FIGURE 17-4: ANALOG INPUT MODEL
Rev. 10-000070A
8/23/2016
VDD
Sampling
Analog switch
VT § 0.6V SS
RS Input pin RIC 1K RSS
ILEAKAGE(1) CHOLD = 10 pF
VA CPIN VT § 0.6V
5pF
Ref-
6V
Legend: CHOLD = Sample/Hold Capacitance 5V
CPIN = Input Capacitance VDD 4V RSS
3V
ILEAKAGE = Leakage Current at the pin due to varies injunctions 2V
RIC = Interconnect Resistance
RSS = Resistance of Sampling switch
SS = Sampling Switch 5 6 7 8 9 10 11
VT = Threshold Voltage Sampling Switch
RS = Source Resistance (k )
Note 1: Refer to Section35.0 “Electrical Specifications”.
FIGURE 17-5: ADC TRANSFER FUNCTION
Full-Scale Range
3FFh
3FEh
3FDh
3FCh
ADC Output Code
3FBh
03h
02h
01h
00h
Analog Input Voltage
0.5 LSB 1.5 LSB
Ref- Zero-Scale
Transition Full-Scale
Transition Ref+

PIC16(L)F1615/9
TABLE 17-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC
Register
on Page
ADCON0 — CHS<4:0> GO/DONE ADON 195

ADCON1 ADFM ADCS<2:0> — — ADPREF<1:0> 196
ADCON2 TRIGSEL<4:0> — — — 197
ADRESH ADC Result Register High 198, 199
ADRESL ADC Result Register Low 198, 199
—(1)
TRISA — — TRISA5 TRISA4 TRISA2 TRISA1 TRISA0 151
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are not
used for ADC module.

PIC16(L)F1615/9
18.0 8-BIT DIGITAL-TO-ANALOG 18.1 Output Voltage Selection
CONVERTER (DAC1) MODULE The DAC has 256 voltage level ranges. The 256 levels
The Digital-to-Analog Converter supplies a variable are set with the DAC1R<7:0> bits of the DAC1CON1
voltage reference, ratiometric with the input source, register.
with 256 selectable output levels. The DAC output voltage is determined by Equation 18-1:
The input of the DAC can be connected to:
• External VREF pins
• VDD supply voltage
• FVR (Fixed Voltage Reference)
The output of the DAC can be configured to supply a
reference voltage to the following:
• Comparator positive input
• ADC input channel
• DACXOUT1 pin
The Digital-to-Analog Converter (DAC) is enabled by
setting the DAC1EN bit of the DAC1CON0 register.
EQUATION 18-1: DAC OUTPUT VOLTAGE

IF DAC1EN = 1
DAC1R  7:0 
VOUT =   VSOURCE+ – VSOURCE-   --------------------------------
- + VSOURCE-
 8 
2
VSOURCE+ = VDD, VREF, or FVR BUFFER 2
VSOURCE- = VSS
18.2 Ratiometric Output Level

The DAC output value is derived using a resistor ladder
with each end of the ladder tied to a positive and
negative voltage reference input source. If the voltage
of either input source fluctuates, a similar fluctuation will
result in the DAC output value.
The value of the individual resistors within the ladder
can be found in Section35.0 “Electrical
Specifications”.
18.3 DAC Voltage Reference Output

The DAC voltage can be output to the DACxOUT1 pin
by setting the DAC1OE1 bit of the DAC1CON0 register.
Selecting the DAC reference voltage for output on the
DACXOUT1 pin automatically overrides the digital
output buffer and digital input threshold detector
functions of that pin. Reading the DACXOUT1 pin when
it has been configured for DAC reference voltage
output will always return a ‘0’.
Due to the limited current drive capability, a buffer must
be used on the DAC voltage reference output for
external connections to either DACXOUT1 pin.
Figure 18-2 shows an example buffering technique.

PIC16(L)F1615/9
FIGURE 18-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM
Rev. 10-000 026C
12/11/201 3
VDD 00
VREF+ 01 VSOURCE+
FVR_buffer2 10 DACR<7:0>
8
Reserved 11 R
DACPSS R
DACEN R
32-to-1 MUX
32 DACx_output
To Peripherals
Steps
R DACxOUT1 (1)
DACOE1
R
VSOURCE-
VSS
Note 1: The unbuffered DACx_output is provided on the DACxOUT pin(s).
FIGURE 18-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC® MCU
DAC
R
Module
+
Voltage DACXOUT1 Buffered DAC Output
–
Reference
Output
Impedance

PIC16(L)F1615/9
18.4 Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the DAC1CON0 register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.

A device Reset affects the following:
• DAC is disabled.
• DAC output voltage is removed from the
DACXOUT1 pin.
• The DAC1R<7:0> range select bits are cleared.

PIC16(L)F1615/9
18.6 Register Definitions: DAC Control
REGISTER 18-1: DAC1CON0: DAC1 CONTROL REGISTER 0

R/W-0/0 U-0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 U-0
DAC1EN — DAC1OE1 — DAC1PSS<1:0> — —
bit 7 bit 0
Legend:
bit 7 DAC1EN: DAC1 Enable bit

1 = DAC is enabled
0 = DAC is disabled
bit 5 DAC1OE1: DAC1 Voltage Output 1 Enable bit
1 = DAC voltage level is also an output on the DACxOUT1 pin
0 = DAC voltage level is disconnected from the DACxOUT1 pin
bit 3-2 DAC1PSS<1:0>: DAC1 Positive Source Select bits
11 = Reserved, do not use
10 = FVR Buffer2 output
01 = VREF+ pin
00 = VDD
REGISTER 18-2: DAC1CON1: DAC1 CONTROL REGISTER 1

DAC1R<7:0>
bit 7 bit 0
Legend:
bit 7-0 DAC1R<7:0>: DAC1 Voltage Output Select bits
TABLE 18-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC1 MODULE

Register
on page
DAC1CON0 DAC1EN — DAC1OE1 — DAC1PSS<1:0> — — 206
DAC1CON1 DAC1R<7:0> 206
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used with the DAC module.

PIC16(L)F1615/9
19.0 COMPARATOR MODULE FIGURE 19-1: SINGLE COMPARATOR
Comparators are used to interface analog circuits to a
digital circuit by comparing two analog voltages and VIN+ +
providing a digital indication of their relative magnitudes. Output
Comparators are very useful mixed signal building VIN- –
blocks because they provide analog functionality
independent of program execution. The analog
comparator module includes the following features:
• Independent comparator control VIN-
• Programmable input selection VIN+
• Comparator output is available internally/externally
• Programmable output polarity
• Interrupt-on-change
• Wake-up from Sleep Output
• Programmable Speed/Power optimization
• PWM shutdown
Note: The black areas of the output of the
• Programmable and Fixed Voltage Reference
comparator represents the uncertainty
19.1 Comparator Overview due to input offsets and response time.
A single comparator is shown in Figure 19-1 along with

the relationship between the analog input levels and
the digital output. When the analog voltage at VIN+ is
less than the analog voltage at VIN-, the output of the
comparator is a digital low level. When the analog
voltage at VIN+ is greater than the analog voltage at
VIN-, the output of the comparator is a digital high level.
The comparators available for this device are located in
Table 19-1.
TABLE 19-1: COMPARATOR AVAILABILITY

PER DEVICE
Device C1 C2
PIC16(L)F1619 ● ●
PIC16(L)F1615 ● ●

PIC16(L)F1615/9
FIGURE 19-2: COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM
Rev. 10-000027J
10/15/2015
3
CxNCH<2:0> CxON(1)
Interrupt CxINTP
Rising
Edge set bit
CxIN0- 000 CxIF
Interrupt CxINTN
CxIN1- 001
Falling
CxIN2- 010 CxON(1) Edge
CxIN3- 011 CxVN

- D Q
CxOUT
Reserved 100
Cx MCxOUT
Reserved 101 CxVP
FVR_buffer2 110
+ Q1
111 CxSP CxHYS CxPOL
CxOUT_sync to
peripherals
CxSYNC
CxIN+ 00
TRIS bit
DAC_output 01 0
FVR_buffer2 10 PPS CxOUT

D Q 1
11
(From Timer1 Module) T1CLK RxyPPS

CxPCH<1:0> CxON(1)
2
Note 1: When CxON = 0, all multiplexer inputs are disconnected and the Comparator will produce a ‘0’ at the output.

PIC16(L)F1615/9
19.2 Comparator Control 19.2.3 COMPARATOR OUTPUT POLARITY
Each comparator has two control registers: CMxCON0 Inverting the output of the comparator is functionally
and CMxCON1. equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
The CMxCON0 registers (see Register 19-1) contain setting the CxPOL bit of the CMxCON0 register.
Control and Status bits for the following: Clearing the CxPOL bit results in a non-inverted output.
• Enable Table 19-2 shows the output state versus input
• Output selection conditions, including polarity control.
• Output polarity TABLE 19-2: COMPARATOR OUTPUT
• Speed/Power selection STATE VS. INPUT
• Hysteresis enable CONDITIONS
• Output synchronization Input Condition CxPOL CxOUT
The CMxCON1 registers (see Register 19-2) contain
CxVN > CxVP 0 0
Control bits for the following:
CxVN < CxVP 0 1
• Interrupt enable
CxVN > CxVP 1 1
• Interrupt edge polarity
CxVN < CxVP 1 0
• Positive input channel selection
• Negative input channel selection 19.2.4 COMPARATOR SPEED/POWER
19.2.1 COMPARATOR ENABLE SELECTION
The trade-off between speed or power can be
Setting the CxON bit of the CMxCON0 register enables
optimized during program execution with the CxSP
the comparator for operation. Clearing the CxON bit
control bit. The default state for this bit is ‘1’ which
disables the comparator resulting in minimum current
selects the Normal Speed mode. Device power
consumption.
consumption can be optimized at the cost of slower
19.2.2 COMPARATOR OUTPUT comparator propagation delay by clearing the CxSP bit
to ‘0’.
SELECTION
The output of the comparator can be monitored by
reading either the CxOUT bit of the CMxCON0 register
or the MCxOUT bit of the CMOUT register. In order to
make the output available for an external connection,
the following conditions must be true:
• CxOE bit of the CMxCON0 register must be set
• Corresponding TRIS bit must be cleared
• CxON bit of the CMxCON0 register must be set
Note 1: The CxOE bit of the CMxCON0 register

overrides the PORT data latch. Setting
the CxON bit of the CMxCON0 register
has no impact on the port override.
2: The internal output of the comparator is
latched with each instruction cycle.
Unless otherwise specified, external
outputs are not latched.

PIC16(L)F1615/9
19.3 Comparator Hysteresis The associated interrupt flag bit, CxIF bit of the PIR2
register, must be cleared in software. If another edge is
A selectable amount of separation voltage can be detected while this flag is being cleared, the flag will still
added to the input pins of each comparator to provide a be set at the end of the sequence.
hysteresis function to the overall operation. Hysteresis
is enabled by setting the CxHYS bit of the CMxCON0 Note: Although a comparator is disabled, an
register. interrupt can be generated by changing
the output polarity with the CxPOL bit of
See Section35.0 “Electrical Specifications” for
the CMxCON0 register, or by switching
more information.
the comparator on or off with the CxON bit
of the CMxCON0 register.
19.4 Timer1 Gate Operation
The output resulting from a comparator operation can 19.6 Comparator Positive Input
be used as a source for gate control of Timer1. See Selection
Section22.5 “Timer1 Gate” for more information. This
feature is useful for timing the duration or interval of an Configuring the CxPCH<1:0> bits of the CMxCON1
analog event. register directs an internal voltage reference or an
analog pin to the non-inverting input of the comparator:
It is recommended that the comparator output be
synchronized to Timer1. This ensures that Timer1 does • CxIN+ analog pin
not increment while a change in the comparator is • DAC output
occurring. • FVR (Fixed Voltage Reference)
• VSS (Ground)
19.4.1 COMPARATOR OUTPUT
SYNCHRONIZATION See Section15.0 “Fixed Voltage Reference (FVR)”
for more information on the Fixed Voltage Reference
The output from a comparator can be synchronized module.
with Timer1 by setting the CxSYNC bit of the
CMxCON0 register. See Section18.0 “8-bit Digital-to-Analog Converter
(DAC1) Module” for more information on the DAC
Once enabled, the comparator output is latched on the input signal.
falling edge of the Timer1 source clock. If a prescaler is
used with Timer1, the comparator output is latched after Any time the comparator is disabled (CxON = 0), all
the prescaling function. To prevent a race condition, the comparator inputs are disabled.
comparator output is latched on the falling edge of the
Timer1 clock source and Timer1 increments on the 19.7 Comparator Negative Input
rising edge of its clock source. See the Comparator Selection
Block Diagram (Figure 19-2) and the Timer1 Block
Diagram (Figure 22-1) for more information. The CxNCH<2:0> bits of the CMxCON1 register direct
an analog input pin or analog ground to the inverting
input of the comparator:
19.5 Comparator Interrupt
• CxIN0- pin
An interrupt can be generated upon a change in the
• CxIN1- pin
output value of the comparator for each comparator, a
rising edge detector and a falling edge detector are • CxIN2- pin
present. • CxIN3- pin
When either edge detector is triggered and its associ- • Analog Ground
ated enable bit is set (CxINTP and/or CxINTN bits of • FVR_buffer2
the CMxCON1 register), the Corresponding Interrupt Some inverting input selections share a pin with the
Flag bit (CxIF bit of the PIR2 register) will be set. operational amplifier output function. Enabling both
To enable the interrupt, the following bits must be set: functions at the same time will direct the operational
amplifier output to the comparator inverting input.
• CxON, CxPOL and CxSP bits of the CMxCON0
register
• CxIE bit of the PIE2 register
Note: To use CxINy+ and CxINy- pins as analog
• CxINTP bit of the CMxCON1 register (for a rising
input, the appropriate bits must be set in
edge detection)
the ANSEL register and the correspond-
• CxINTN bit of the CMxCON1 register (for a falling ing TRIS bits must also be set to disable
edge detection) the output drivers.
• PEIE and GIE bits of the INTCON register

PIC16(L)F1615/9
19.8 Comparator Response Time A maximum source impedance of 10 k is recommended
for the analog sources. Also, any external component
The comparator output is indeterminate for a period of connected to an analog input pin, such as a capacitor or
time after the change of an input source or the selection a Zener diode, should have very little leakage current to
of a new reference voltage. This period is referred to as minimize inaccuracies introduced.
the response time. The response time of the comparator
differs from the settling time of the voltage reference. Note 1: When reading a PORT register, all pins
Therefore, both of these times must be considered when configured as analog inputs will read as a
determining the total response time to a comparator ‘0’. Pins configured as digital inputs will
input change. See the Comparator and Voltage convert as an analog input, according to
Reference Specifications in Section35.0 “Electrical the input specification.
Specifications” for more details. 2: Analog levels on any pin defined as a
digital input, may cause the input buffer to
19.9 Analog Input Connection consume more current than is specified.
Considerations
A simplified circuit for an analog input is shown in
Figure 19-3. Since the analog input pins share their
connection with a digital input, they have reverse
biased ESD protection diodes to VDD and VSS. The
analog input, therefore, must be between VSS and VDD.
If the input voltage deviates from this range by more
than 0.6V in either direction, one of the diodes is
forward biased and a latch-up may occur.
FIGURE 19-3: ANALOG INPUT MODEL
Rev. 10-000071A
8/2/2013
VDD
Analog
VT § 0.6V
RS < 10K Input pin RIC
To Comparator
ILEAKAGE(1)
VA CPIN VT § 0.6V
5pF
VSS
Legend: CPIN = Input Capacitance

ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS = Source Impedance
VA = Analog Voltage
VT = Threshold Voltage
Note 1: See Section35.0 “Electrical Specifications”.

PIC16(L)F1615/9
19.10 Register Definitions: Comparator Control
REGISTER 19-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0

R/W-0/0 R-0/0 U-0 R/W-0/0 U-0 R/W-1/1 R/W-0/0 R/W-0/0
CxON CxOUT — CxPOL — CxSP CxHYS CxSYNC
bit 7 bit 0
Legend:
bit 7 CxON: Comparator Enable bit

1 = Comparator is enabled
0 = Comparator is disabled and consumes no active power
bit 6 CxOUT: Comparator Output bit
If CxPOL = 1 (inverted polarity):
1 = CxVP < CxVN
0 = CxVP > CxVN
If CxPOL = 0 (non-inverted polarity):
1 = CxVP > CxVN
0 = CxVP < CxVN
bit 4 CxPOL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 2 CxSP: Comparator Speed/Power Select bit
1 = Comparator operates in normal power, higher speed mode
0 = Comparator operates in Low-power, Low-speed mode
bit 1 CxHYS: Comparator Hysteresis Enable bit
1 = Comparator hysteresis enabled
0 = Comparator hysteresis disabled
bit 0 CxSYNC: Comparator Output Synchronous Mode bit
1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source.
Output updated on the falling edge of Timer1 clock source.
0 = Comparator output to Timer1 and I/O pin is asynchronous

PIC16(L)F1615/9
REGISTER 19-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1

CxINTP CxINTN CxPCH<1:0> — CxNCH<2:0>
bit 7 bit 0
Legend:
bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits

1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit
0 = No interrupt flag will be set on a positive going edge of the CxOUT bit
bit 6 CxINTN: Comparator Interrupt on Negative Going Edge Enable bits
1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit
0 = No interrupt flag will be set on a negative going edge of the CxOUT bit
bit 5-4 CxPCH<1:0>: Comparator Positive Input Channel Select bits
11 = CxVP connects to AGND
10 = CxVP connects to FVR Buffer 2
01 = CxVP connects to VDAC
00 = CxVP connects to CxIN+ pin
bit 2-0 CxNCH<2:0>: Comparator Negative Input Channel Select bits
111 = CxVN connects to AGND
110 = CxVN connects to FVR Buffer 2
101 = Reserved
100 = Reserved
011 = CxVN connects to CxIN3- pin
REGISTER 19-3: CMOUT: COMPARATOR OUTPUT REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R-0/0 R-0/0
— — — — — — MC2OUT MC1OUT
bit 7 bit 0
Legend:

bit 1 MC2OUT: Mirror Copy of C2OUT bit
bit 0 MC1OUT: Mirror Copy of C1OUT bit

PIC16(L)F1615/9
TABLE 19-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Register
on Page

CM1CON0 C1ON C1OUT — C1POL — C1SP C1HYS C1SYNC 212
CM1CON1 C1INTP C1INTN C1PCH<1:0> — C1NCH<2:0> 213
CM2CON0 C2ON C2OUT — C2POL — C2SP C2HYS C2SYNC 212
CM2CON1 C2INTP C2INTN C2PCH<1:0> — C2NCH<2:0> 213
CMOUT — — — — — — MC2OUT MC1OUT 213
DAC1CON0 DAC1EN — DAC1OE1 — DAC1PSS<1:0> — — 206
DAC1CON1 DAC1R<7:0> 206
TRISC(2) TRISC7(2) TRISC6(2) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 165
Legend: — = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module.
2: PIC16F1619 only.

PIC16(L)F1615/9
20.0 ZERO-CROSS DETECTION 20.1 External Resistor Selection
(ZCD) MODULE The ZCD module requires a current limiting resistor in
The ZCD module detects when an A/C signal crosses series with the external voltage source. The impedance
through the ground potential. The actual zero crossing and rating of this resistor depends on the external
threshold is the zero crossing reference voltage, source peak voltage. Select a resistor value that will drop
VCPINV, which is typically 0.75V above ground. all of the peak voltage when the current through the
resistor is nominally 300 A. Refer to Equation 20-1 and
The connection to the signal to be detected is through Figure 20-1. Make sure that the ZCD I/O pin internal
a series current limiting resistor. The module applies a weak pull-up is disabled so it does not interfere with the
current source or sink to the ZCD pin to maintain a current source and sink.
constant voltage on the pin, thereby preventing the pin
voltage from forward biasing the ESD protection
EQUATION 20-1: EXTERNAL RESISTOR
diodes. When the applied voltage is greater than the
reference voltage, the module sinks current. When the
applied voltage is less than the reference voltage, the
module sources current. The current source and sink
action keeps the pin voltage constant over the full V PEAK
R SERIES = ----------------
-
range of the applied voltage. The ZCD module is –4
shown in the simplified block diagram Figure 20-2.
3 10
The ZCD module is useful when monitoring an A/C
waveform for, but not limited to, the following purposes:
• A/C period measurement
• Accurate long term time measurement
FIGURE 20-1: EXTERNAL VOLTAGE
• Dimmer phase delayed drive
• Low EMI cycle switching VMAXPEAK
VPEAK VMINPEAK
VCPINV

PIC16(L)F1615/9
FIGURE 20-2: SIMPLIFIED ZCD BLOCK DIAGRAM
VPULLUP Rev. 10-000194B

5/14/2014
optional
VDD RPULLUP
- ZCDxIN RSERIES
External
Zcpinv + RPULLDOWN voltage
source
optional
ZCDx_output
D Q OUT bit
POL
Q1
Interrupt
det
INTP Set
ZCDIF
INTN flag
Interrupt
det

PIC16(L)F1615/9
20.2 ZCD Logic Output 20.5 Correcting for VCPINV offset
The ZCD module includes a Status bit, which can be The actual voltage at which the ZCD switches is the
read to determine whether the current source or sink is reference voltage at the non-inverting input of the ZCD
active. The ZCDxOUT bit of the ZCDxCON register is op amp. For external voltage source waveforms other
set when the current sink is active, and cleared when than square waves, this voltage offset from zero
the current source is active. The ZCDxOUT bit is causes the zero-cross event to occur either too early or
affected by the polarity bit. too late.
20.3 ZCD Logic Polarity 20.5.1 CORRECTION BY AC COUPLING

When the external voltage source is sinusoidal, the
The ZCDxPOL bit of the ZCDxCON register inverts the
effects of the ZCPINV offset can be eliminated by
ZCDxOUT bit relative to the current source and sink
isolating the external voltage source from the ZCD pin
output. When the ZCDxPOL bit is set, a ZCDxOUT high
with a capacitor, in addition to the voltage reducing
indicates that the current source is active, and a low
resistor. The capacitor will cause a phase shift resulting
output indicates that the current sink is active.
in the ZCD output switch in advance of the actual zero-
The ZCDxPOL bit affects the ZCD interrupts. See crossing event. The phase shift will be the same for
Section20.4 “ZCD Interrupts”. both rising and falling zero crossings, which can be
compensated for by either delaying the CPU response
20.4 ZCD Interrupts to the ZCD switch by a timer or other means, or
selecting a capacitor value large enough that the phase
An interrupt will be generated upon a change in the shift is negligible.
ZCD logic output when the appropriate interrupt
enables are set. A rising edge detector and a falling To determine the series resistor and capacitor values
edge detector are present in the ZCD for this purpose. for this configuration, start by computing the
impedance, Z, to obtain a peak current of 300 uA. Next,
The ZCDIF bit of the PIR3 register will be set when arbitrarily select a suitably large non-polar capacitor
either edge detector is triggered and its associated and compute its reactance, Xc, at the external voltage
enable bit is set. The ZCDxINTP enables rising edge source frequency. Finally, compute the series resistor,
interrupts and the ZCDxINTN bit enables falling edge capacitor peak voltage, and phase shift by the formulas
interrupts. Both are located in the ZCDxCON register. shown in Equation 20-2.
To fully enable the interrupt, the following bits must be set: When this technique is used and the input signal is not
• ZCDIE bit of the PIE3 register present, the ZCD will tend to oscillate. To avoid this
• ZCDxINTP bit of the ZCDxCON register oscillation, connect the ZCD pin to VDD or GND with a
(for a rising edge detection) high-impedance resistor such as 200K.
• ZCDxINTN bit of the ZCDxCON register
(for a falling edge detection)
Changing the ZCDxPOL bit will cause an interrupt,
regardless of the level of the ZCDxEN bit.
The ZCDIF bit of the PIR3 register must be cleared in
software as part of the interrupt service. If another edge
is detected while this flag is being cleared, the flag will
still be set at the end of the sequence.

PIC16(L)F1615/9
EQUATION 20-2: R-C CALCULATIONS 20.5.2 CORRECTION BY OFFSET
VPEAK = External voltage source peak voltage
CURRENT
f = External voltage source frequency When the waveform is varying relative to VSS, then the
C = Series capacitor zero cross is detected too early as the waveform falls
R = Series resistor and too late as the waveform rises. When the
VC = Peak capacitor voltage
waveform is varying relative to VDD, then the zero cross
is detected too late as the waveform rises and too early
Φ = Capacitor induced zero crossing phase advance in
radians
as the waveform falls. The actual offset time can be
determined for sinusoidal waveforms with the
TΦ = Time ZC event occurs before actual zero crossing
corresponding equations shown in Equation 20-3.
V PEAK
Z = -------------------
-
3  10
–4 EQUATION 20-3: ZCD EVENT OFFSET
1 When External Voltage Source is relative to Vss:
X C = -------------
2fC
asin  ------------------
Vcpinv
2 2
R = Z – XC V PEAK
T OFFSET = ----------------------------------
–4 2  Freq
V C = X C  3  10 
When External Voltage Source is relative to VDD:
 = Tan  -------
–1 X C
 R
asin  --------------------------------

V DD – Vcpinv
T = ---------
2f  V PEAK 
T OFFSET = -------------------------------------------------
2  Freq
EXAMPLE 20-1: R-C CALCULATIONS
This offset time can be compensated for by adding a
VRMS = 120
pull-up or pull-down biasing resistor to the ZCD pin. A
VPEAK = VRMS *= 169.7
pull-up resistor is used when the external voltage
f = 60 Hz
source is varying relative to VSS. A pull-down resistor is
C = 0.1 µF used when the voltage is varying relative to VDD. The
V PEAK 169.7 resistor adds a bias to the ZCD pin so that the target
Z = -------------------
–4
- = 565.7k 
- = -------------------
–4 external voltage source must go to zero to pull the pin
3  10 3  10 voltage to the VCPINV switching voltage. The pull-up or
pull-down value can be determined with the equations
1 1
- = 26.53k 
X C = ------------- = -------------------------------------------------
–7
shown in Equation 20-4 or Equation 20-5.
2fC  2  60  1  10 
EQUATION 20-4: ZCD PULL-UP/DOWN
2 2
R =  Z  X C  = 565.1k   computed  When External Signal is relative to Vss:
R SERIE S  V PULLUP – V cpinv 

R = 560k  used  R PULLUP = ------------------------------------------------------------------------
V cpinv
2 2
ZR = R + X C = 560.6k   u sin g actual resistor  When External Signal is relative to VDD:
V PEAK –6 R SERIES  V cpinv 

I PEAK = ------------------ = 302.7  10 R PULLDOWN = --------------------------------------------
ZR  V DD – V cpinv 
V C = X C  Ipeak = 8.0V
 = Tan  ------- = 0.047 radians

–1 X C
 R

T = --------- = 125.6s
2f

PIC16(L)F1615/9
20.6 Handling VPEAK variations
If the peak amplitude of the external voltage is
expected to vary, the series resistor must be selected
to keep the ZCD current source and sink below the
design maximum range of ± 600 A and above a
reasonable minimum range. A general rule of thumb is
that the maximum peak voltage can be no more than
six times the minimum peak voltage. To ensure that the
maximum current does not exceed ± 600 A and the
minimum is at least ± 100 A, compute the series
resistance as shown in Equation 20-5. The
compensating pull-up for this series resistance can be
determined with Equation 20-4 because the pull-up
value is independent from the peak voltage.
EQUATION 20-5: SERIES R FOR V RANGE
V MAXPEAK + V MINPEAK
R SERIES = ---------------------------------------------------------
–4
7 10

The ZCD current sources and interrupts are unaffected
by Sleep.

The ZCD circuit can be configured to default to the active
or inactive state on Power-On-Reset (POR). When the
ZCD Configuration bit is cleared, the ZCD circuit will be
active at POR. When the ZCD Configuration bit is set,
the ZCDxEN bit of the ZCDxCON register must be set to
enable the ZCD module.

PIC16(L)F1615/9
20.9 Register Definitions: ZCD Control
REGISTER 20-1: ZCDxCON: ZERO-CROSS DETECTION CONTROL REGISTER

R/W-q/q U-0 R-x/x R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0
ZCDxEN — ZCDxOUT ZCDxPOL — — ZCDxINTP ZCDxINTN
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on configuration bits
bit 7 ZCDxEN: Zero-Cross Detection Enable bit

1 = Zero-cross detect is enabled. ZCD pin is forced to output to source and sink current.
0 = Zero-cross detect is disabled. ZCD pin operates according to PPS and TRIS controls.
bit 5 ZCDxOUT: Zero-Cross Detection Logic Level bit
ZCDxPOL bit = 0:
1 = ZCD pin is sinking current
0 = ZCD pin is sourcing current
ZCDxPOL bit = 1:
1 = ZCD pin is sourcing current
0 = ZCD pin is sinking current
bit 4 ZCDxPOL: Zero-Cross Detection Logic Output Polarity bit
1 = ZCD logic output is inverted
0 = ZCD logic output is not inverted
bit 1 ZCDxINTP: Zero-Cross Positive Edge Interrupt Enable bit
1 = ZCDIF bit is set on low-to-high ZCDx_output transition
0 = ZCDIF bit is unaffected by low-to-high ZCDx_output transition
bit 0 ZCDxINTN: Zero-Cross Negative Edge Interrupt Enable bit
1 = ZCDIF bit is set on high-to-low ZCDx_output transition
0 = ZCDIF bit is unaffected by high-to-low ZCDx_output transition
TABLE 20-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE ZCD MODULE

Register
on page
ZCD1CON ZCD1EN — ZCD1OUT ZCD1POL — — ZCD1INTP ZCD1INTN 220
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the ZCD module.
TABLE 20-2: SUMMARY OF CONFIGURATION WORD WITH THE ZCD MODULE

Register
on Page
CONFIG2 13:8 — — LVP DEBUG LPBOR BORV STVREN PLLEN 69

7:0 ZCD — — — — PPS1WAY WRT<1:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the ZCD module.

PIC16(L)F1615/9
21.0 TIMER0 MODULE 21.1.2 8-BIT COUNTER MODE
The Timer0 module is an 8-bit timer/counter with the In 8-Bit Counter mode, the Timer0 module will increment
following features: on every rising or falling edge of the T0CKI pin.
• 8-bit timer/counter register (TMR0) 8-Bit Counter mode using the T0CKI pin is selected by
setting the TMR0CS bit in the OPTION_REG register to
• 3-bit prescaler (independent of Watchdog Timer)
‘1’.
• Programmable internal or external clock source
The rising or falling transition of the incrementing edge
• Programmable external clock edge selection
for either input source is determined by the TMR0SE bit
• Interrupt on overflow in the OPTION_REG register.
• TMR0 can be used to gate Timer1
Figure 21-1 is a block diagram of the Timer0 module.
21.1 Timer0 Operation

The Timer0 module can be used as either an 8-bit timer
or an 8-bit counter.
21.1.1 8-BIT TIMER MODE

The Timer0 module will increment every instruction
cycle, if used without a prescaler. 8-bit Timer mode is
selected by clearing the TMR0CS bit of the
OPTION_REG register.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
Note: The value written to the TMR0 register
can be adjusted, in order to account for
the two instruction cycle delay when
TMR0 is written.
FIGURE 21-1: TIMER0 BLOCK DIAGRAM
Rev. 10-000017A
TMR0CS 8/5/2013
Fosc/4 PSA
T0CKI(1) 0 T0_overflow
1 T0CKI
TMR0
1 Prescaler 0 FOSC/2 Sync Circuit Q1
write R
to
TMR0
TMR0SE set bit
PS<2:0>
TMR0IF
Note 1: The T0CKI prescale output frequency should not exceed FOSC/8.

PIC16(L)F1615/9
21.1.3 SOFTWARE PROGRAMMABLE
PRESCALER
A software programmable prescaler is available for
exclusive use with Timer0. The prescaler is enabled by
clearing the PSA bit of the OPTION_REG register.
Note: The Watchdog Timer (WDT) uses its own
independent prescaler.
There are eight prescaler options for the Timer0
module ranging from 1:2 to 1:256. The prescale values
are selectable via the PS<2:0> bits of the
OPTION_REG register. In order to have a 1:1 prescaler
value for the Timer0 module, the prescaler must be
disabled by setting the PSA bit of the OPTION_REG
register.
The prescaler is not readable or writable. All instructions
writing to the TMR0 register will clear the prescaler.
21.1.4 TIMER0 INTERRUPT

Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The TMR0IF
interrupt flag bit of the INTCON register is set every
time the TMR0 register overflows, regardless of
whether or not the Timer0 interrupt is enabled. The
TMR0IF bit can only be cleared in software. The Timer0
interrupt enable is the TMR0IE bit of the INTCON
register.
Note: The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
21.1.5 8-BIT COUNTER MODE

SYNCHRONIZATION
When in 8-Bit Counter mode, the incrementing edge on
the T0CKI pin must be synchronized to the instruction
clock. Synchronization can be accomplished by
sampling the prescaler output on the Q2 and Q4 cycles
of the instruction clock. The high and low periods of the
external clocking source must meet the timing
requirements as shown in Section35.0 “Electrical
Specifications”.
21.1.6 OPERATION DURING SLEEP

Timer0 cannot operate while the processor is in Sleep
mode. The contents of the TMR0 register will remain
unchanged while the processor is in Sleep mode.

PIC16(L)F1615/9
21.2 Register Definitions: Option Register
REGISTER 21-1: OPTION_REG: OPTION REGISTER

WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0>
bit 7 bit 0
Legend:
bit 7 WPUEN: Weak Pull-Up Enable bit

1 = All weak pull-ups are disabled (except MCLR, if it is enabled)
0 = Weak pull-ups are enabled by individual WPUx latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5 TMR0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4 TMR0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is not assigned to the Timer0 module
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Bit Value Timer0 Rate
000 1:2
001 1:4
010 1:8
011 1 : 16
100 1 : 32
101 1 : 64
110 1 : 128
111 1 : 256
TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Register
on Page
ADCON2 TRIGSEL<4:0> — — — 197
TMR0 Holding Register for the 8-bit Timer0 Count 221*
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module.

PIC16(L)F1615/9
22.0 TIMER1/3/5 MODULE WITH • Selectable Gate Source Polarity
GATE CONTROL • Gate Toggle mode
• Gate Single-Pulse mode
The Timer1/3/5 modules are a 16-bit timers/counters
• Gate Value Status
with the following features:
• Gate Event Interrupt
• 16-bit timer/counter register pair (TMR1H:TMR1L)
Figure 22-1 is a block diagram of the Timer1 module.
• Programmable internal or external clock source
• 2-bit prescaler
• Optionally synchronized comparator out Note: Three identical Timer1 modules are
implemented on this device. The timers
• Multiple Timer1 gate (count enable) sources
are named Timer1, Timer3, and Timer5.
• Interrupt on overflow All references to Timer1 apply as well to
• Wake-up on overflow (external clock, Timer3 and Timer5, as well as references
Asynchronous mode only) to their associated registers.
• ADC Auto-Conversion Trigger(s)
T1GSS<1:0> Rev. 10-000018H

7/28/2015
T1GPPS
T1GSPM
PPS 00
T0_overflow 01
1
C1OUT_sync 10 0 Single Pulse D Q T1GVAL
0
C2OUT_sync 11 1 Acq. Control
Q1
D Q
T1GPOL T1GGO/DONE
CK Q
TMR1ON Interrupt
set bit
R
T1GTM det TMR1GIF
TMR1GE
set flag bit
TMR1IF
TMR1ON
EN
(2)
TMR1
T1_overflow Synchronized Clock Input
TMR1H TMR1L Q D 0
1
T1CLK
T1SYNC
TMR1CS<1:0>
LFINTOSC 11
(1)
T1CKI PPS 10 Prescaler
Fosc Synchronize(3)
01 1,2,4,8
Internal Clock det
00
2
T1CKIPPS Fosc/4 Fosc/2
Internal Clock T1CKPS<1:0> Internal Sleep
Clock Input
Note 1: ST Buffer is high speed type when using T1CKI.

2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.

PIC16(L)F1615/9
22.1 Timer1 Operation 22.2 Clock Source Selection
The Timer1 module is a 16-bit incrementing counter The TMR1CS<1:0> bits of the T1CON register are used
which is accessed through the TMR1H:TMR1L register to select the clock source for Timer1. Table 22-2
pair. Writes to TMR1H or TMR1L directly update the displays the clock source selections.
counter.
22.2.1 INTERNAL CLOCK SOURCE
When used with an internal clock source, the module is
a timer and increments on every instruction cycle. When the internal clock source is selected, the
When used with an external clock source, the module TMR1H:TMR1L register pair will increment on multiples
can be used as either a timer or counter and incre- of FOSC as determined by the Timer1 prescaler.
ments on every selected edge of the external source. When the FOSC internal clock source is selected, the
Timer1 is enabled by configuring the TMR1ON and Timer1 register value will increment by four counts every
TMR1GE bits in the T1CON and T1GCON registers, instruction clock cycle. Due to this condition, a 2 LSB
respectively. Table 22-1 displays the Timer1 enable error in resolution will occur when reading the Timer1
selections. value. To utilize the full resolution of Timer1, an
asynchronous input signal must be used to gate the
Timer1 clock input.
TABLE 22-1: TIMER1 ENABLE
The following asynchronous sources may be used:
SELECTIONS
• Asynchronous event on the T1G pin to Timer1
Timer1
TMR1ON TMR1GE gate
Operation
• C1 or C2 comparator input to Timer1 gate
0 0 Off
0 1 Off 22.2.2 EXTERNAL CLOCK SOURCE
1 0 Always On When the external clock source is selected, the Timer1
1 1 Count Enabled module may work as a timer or a counter.
When enabled to count, Timer1 is incremented on the
rising edge of the external clock input T1CKI. The
external clock source can be synchronized to the
microcontroller system clock or it can run
asynchronously.
Note: In Counter mode, a falling edge must be

registered by the counter prior to the first
incrementing rising edge after any one or
more of the following conditions:
•Timer1 enabled after POR
•Write to TMR1H or TMR1L
•Timer1 is disabled
•Timer1 is disabled (TMR1ON = 0)
when T1CKI is high then Timer1 is
enabled (TMR1ON=1) when T1CKI is
low.
TABLE 22-2: CLOCK SOURCE SELECTIONS

TMR1CS<1:0> Clock Source
11 LFINTOSC
10 External Clocking on T1CKI Pin
01 System Clock (FOSC)
00 Instruction Clock (FOSC/4)

PIC16(L)F1615/9
22.3 Timer1 Prescaler For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
Timer1 has four prescaler options allowing 1, 2, 4 or 8 contention may occur by writing to the timer registers,
divisions of the clock input. The T1CKPS bits of the while the register is incrementing. This may produce an
T1CON register control the prescale counter. The unpredictable value in the TMR1H:TMR1L register pair.
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write to
22.5 Timer1 Gate
TMR1H or TMR1L.
Timer1 can be configured to count freely or the count
22.4 Timer1 Operation in can be enabled and disabled using Timer1 gate
Asynchronous Counter Mode circuitry. This is also referred to as Timer1 Gate Enable.
Timer1 gate can also be driven by multiple selectable
If control bit T1SYNC of the T1CON register is set, the
sources.
external clock input is not synchronized. The timer
increments asynchronously to the internal phase 22.5.1 TIMER1 GATE ENABLE
clocks. If the external clock source is selected then the
timer will continue to run during Sleep and can The Timer1 Gate Enable mode is enabled by setting
generate an interrupt on overflow, which will wake-up the TMR1GE bit of the T1GCON register. The polarity
the processor. However, special precautions in of the Timer1 Gate Enable mode is configured using
software are needed to read/write the timer (see the T1GPOL bit of the T1GCON register.
Section22.4.1 “Reading and Writing Timer1 in When Timer1 Gate Enable mode is enabled, Timer1
Asynchronous Counter Mode”). will increment on the rising edge of the Timer1 clock
source. When Timer1 Gate Enable mode is disabled,
Note: When switching from synchronous to
no incrementing will occur and Timer1 will hold the
asynchronous operation, it is possible to
current count. See Figure 22-3 for timing details.
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce an additional TABLE 22-3: TIMER1 GATE ENABLE
increment. SELECTIONS
22.4.1 READING AND WRITING TIMER1 IN T1CLK T1GPOL T1G Timer1 Operation
ASYNCHRONOUS COUNTER  0 0 Counts
MODE  0 1 Holds Count
Reading TMR1H or TMR1L while the timer is running  1 0 Holds Count
from an external asynchronous clock will ensure a valid  1 1 Counts
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two 22.5.2 TIMER1 GATE SOURCE
8-bit values itself, poses certain problems, since the
SELECTION
timer may overflow between the reads.
Timer1 gate source selections are shown in Table 22-4.
Source selection is controlled by the T1GSS<1:0> bits
of the T1GCON register. The polarity for each available
source is also selectable. Polarity selection is controlled
by the T1GPOL bit of the T1GCON register.
TABLE 22-4: TIMER1 GATE SOURCES

T1GSS Timer1 Gate Source
00 Timer1 Gate pin (T1G)
01 Overflow of Timer0 (T0_overflow)
(TMR0 increments from FFh to 00h)
10 Comparator 1 Output (C1_OUT_sync)(1)
11 Comparator 2 Output (C2_OUT_sync)(1)
Note 1: Optionally synchronized comparator output.
22.5.2.1 T1G Pin Gate Operation gate circuitry.

The T1G pin is one source for Timer1 gate control. It
can be used to supply an external source to the Timer1

PIC16(L)F1615/9
22.5.2.2 Timer0 Overflow Gate Operation 22.5.5 TIMER1 GATE VALUE STATUS
When Timer0 increments from FFh to 00h, a low-to- When Timer1 Gate Value Status is utilized, it is possible
high pulse will automatically be generated and inter- to read the most current level of the gate control value.
nally supplied to the Timer1 gate circuitry. The value is stored in the T1GVAL bit in the T1GCON
register. The T1GVAL bit is valid even when the Timer1
22.5.3 TIMER1 GATE TOGGLE MODE gate is not enabled (TMR1GE bit is cleared).
When Timer1 Gate Toggle mode is enabled, it is possi-
ble to measure the full-cycle length of a Timer1 gate 22.5.6 TIMER1 GATE EVENT INTERRUPT
signal, as opposed to the duration of a single level When Timer1 Gate Event Interrupt is enabled, it is pos-
pulse. sible to generate an interrupt upon the completion of a
The Timer1 gate source is routed through a flip-flop that gate event. When the falling edge of T1GVAL occurs,
changes state on every incrementing edge of the sig- the TMR1GIF flag bit in the PIR1 register will be set. If
nal. See Figure 22-4 for timing details. the TMR1GIE bit in the PIE1 register is set, then an
interrupt will be recognized.
Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit of the T1GCON register. When the T1GTM The TMR1GIF flag bit operates even when the Timer1
bit is cleared, the flip-flop is cleared and held clear. This gate is not enabled (TMR1GE bit is cleared).
is necessary in order to control which edge is
measured.
Note: Enabling Toggle mode at the same time
as changing the gate polarity may result in
indeterminate operation.
22.5.4 TIMER1 GATE SINGLE-PULSE

MODE
When Timer1 Gate Single-Pulse mode is enabled, it is
possible to capture a single pulse gate event. Timer1
Gate Single-Pulse mode is first enabled by setting the
T1GSPM bit in the T1GCON register. Next, the T1GGO/
DONE bit in the T1GCON register must be set. The
Timer1 will be fully enabled on the next incrementing
edge. On the next trailing edge of the pulse, the T1GGO/
DONE bit will automatically be cleared. No other gate
events will be allowed to increment Timer1 until the
T1GGO/DONE bit is once again set in software. See
Figure 22-5 for timing details.
If the Single Pulse Gate mode is disabled by clearing the
T1GSPM bit in the T1GCON register, the T1GGO/DONE
bit should also be cleared.
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the cycle times on the Timer1 gate
source to be measured. See Figure 22-6 for timing
details.

PIC16(L)F1615/9
22.6 Timer1 Interrupt Timer1 oscillator will continue to operate in Sleep
regardless of the T1SYNC bit setting.
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit of the PIR1 register is
set. To enable the interrupt on rollover, the following
bits must be set:
• TMR1ON bit of the T1CON register
• TMR1IE bit of the PIE1 register
• PEIE bit of the INTCON register
• GIE bit of the INTCON register
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
Note: The TMR1H:TMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
22.7 Timer1 Operation During Sleep

Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:
• TMR1ON bit of the T1CON register must be set
• TMR1IE bit of the PIE1 register must be set
• PEIE bit of the INTCON register must be set
• T1SYNC bit of the T1CON register must be set
• TMR1CS bits of the T1CON register must be
configured
The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine.
FIGURE 22-2: TIMER1 INCREMENTING EDGE
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter increments.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.

PIC16(L)F1615/9
FIGURE 22-3: TIMER1 GATE ENABLE MODE
TMR1GE
T1GPOL
T1G_in
T1CKI
T1GVAL
Timer1 N N+1 N+2 N+3 N+4
FIGURE 22-4: TIMER1 GATE TOGGLE MODE
TMR1GE
T1GPOL
T1GTM
T1G_in
T1CKI
T1GVAL
Timer1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8

PIC16(L)F1615/9
FIGURE 22-5: TIMER1 GATE SINGLE-PULSE MODE
TMR1GE
T1GPOL
T1GSPM
Cleared by hardware on
T1GGO/ Set by software falling edge of T1GVAL
DONE
Counting enabled on
rising edge of T1G
T1G_in
T1CKI
T1GVAL
Timer1 N N+1 N+2
Cleared by
TMR1GIF Cleared by software Set by hardware on software
falling edge of T1GVAL

PIC16(L)F1615/9
FIGURE 22-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
TMR1GE
T1GPOL
T1GSPM
T1GTM
Cleared by hardware on
T1GGO/ Set by software falling edge of T1GVAL
DONE Counting enabled on
rising edge of T1G
T1G_in
T1CKI
T1GVAL
Timer1 N N+1 N+2 N+3 N+4
Set by hardware on Cleared by

TMR1GIF Cleared by software falling edge of T1GVAL software

PIC16(L)F1615/9
22.8 Register Definitions: Timer1 Control
REGISTER 22-1: T1CON: TIMER1 CONTROL REGISTER

R/W-0/u R/W-0/u R/W-0/u R/W-0/u U-0 R/W-0/u U-0 R/W-0/u
TMR1CS<1:0> T1CKPS<1:0> — T1SYNC — TMR1ON
bit 7 bit 0
Legend:
bit 7-6 TMR1CS<1:0>: Timer1 Clock Source Select bits

11 =LFINTOSC
10 =T1CKI
01 =FOSC
00 =FOSC/4
bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 =1:8 Prescale value
bit 2 T1SYNC: Timer1 Synchronization Control bit
1 = Do not synchronize asynchronous clock input
0 = Synchronize asynchronous clock input with system clock (FOSC)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1 and clears Timer1 gate flip-flop

PIC16(L)F1615/9
REGISTER 22-2: T1GCON: TIMER1 GATE CONTROL REGISTER

R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x R/W-0/u R/W-0/u
TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0>
DONE
bit 7 bit 0
Legend:
bit 7 TMR1GE: Timer1 Gate Enable bit

If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1 = Timer1 counting is controlled by the Timer1 gate function
0 = Timer1 counts regardless of Timer1 gate function
bit 6 T1GPOL: Timer1 Gate Polarity bit
1 = Timer1 gate is active-high (Timer1 counts when gate is high)
0 = Timer1 gate is active-low (Timer1 counts when gate is low)
bit 5 T1GTM: Timer1 Gate Toggle Mode bit
1 = Timer1 Gate Toggle mode is enabled
0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared
Timer1 gate flip-flop toggles on every rising edge.
bit 4 T1GSPM: Timer1 Gate Single-Pulse Mode bit
1 = Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate
0 = Timer1 gate Single-Pulse mode is disabled
bit 3 T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit
1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge
0 = Timer1 gate single-pulse acquisition has completed or has not been started
bit 2 T1GVAL: Timer1 Gate Value Status bit
Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L.
Unaffected by Timer1 Gate Enable (TMR1GE).
bit 0 T1GSS<1:0>: Timer1 Gate Source Select bits
11 =Comparator 2 optionally synchronized output (C2_OUT_sync)
10 =Comparator 1 optionally synchronized output (C1_OUT_sync)
01 =Timer0 overflow output (T0_overflow)
00 =Timer1 gate pin (T1G)

PIC16(L)F1615/9
Register
on Page
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Count 228*
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Count 228*
T1CON TMR1CS<1:0> T1CKPS<1:0> — T1SYNC — TMR1ON 232
T1GGO/
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GVAL T1GSS<1:0> 233
DONE
T3GGO/
DONE
T5GGO/
DONE
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module.

PIC16(L)F1615/9
23.0 TIMER2/4/6 MODULE • Three modes of operation:
- Free Running Period
The Timer2/4/6 modules are 8-bit timers that can
- One-shot
operate as free-running period counters or in
conjunction with external signals that control start, run, - Monostable
freeze, and reset operation in One-Shot and See Figure 23-1 for a block diagram of Timer2. See
Monostable modes of operation. Sophisticated Figure 23-2 for the clock source block diagram.
waveform control such as pulse density modulation are
possible by combining the operation of these timers Note: Three identical Timer2 modules are
with other internal peripherals such as the comparators implemented on this device. The timers are
and CCP modules. Features of the timer include: named Timer2, Timer4, and Timer6. All
references to Timer2 apply as well to
• 8-bit timer register Timer4 and Timer6. All references to T2PR
• 8-bit period register apply as well to T4PR and T6PR.
• Selectable external hardware timer Resets
• Programmable prescaler (1:1 to 1:128)
• Programmable postscaler (1:1 to 1:16)
• Selectable synchronous/asynchronous operation
• Alternate clock sources
• Interrupt-on-period
RSEL Rev. 10-000 168B

5/29/201 4
TxINPPS
TxIN PPS
MODE<4:0> MODE<3>
Edg e Detecto r reset

External Reset TMRx_ers Level Dete ctor CCP_pset
Sources Mode Control
(Table 23-4) (2 clock Sync)
enable MODE<4:3>=01
Clear ON
MODE<4:1>=1011 D Q
CKPOL
TMRx_clk Pre scaler 0
R
TMRx
Set flag bi t
3 Sync 1 TMRxIF
CKPS<2:0> Fosc/4 PSYNC TMRx_postscaled

Comparator Postscaler
4
ON Sync
(2 Clocks)
1
PRx OUTPS<3:0>
0
CKSYNC
Note 1: Signal to the CCP to trigger the PWM pulse

2: See Section 22.5 for description of CCP interaction in the different TMR modes

PIC16(L)F1615/9
FIGURE 23-2: TIMER2 CLOCK SOURCE
BLOCK DIAGRAM Note: TMR2 is not cleared when T2CON is
written.
TxCLKCON Rev. 10-000 169B
5/29/201 4
TXINPPS 23.1.1 FREE RUNNING PERIOD MODE

TXIN PPS The value of TMR2 is compared to that of the Period
register, T2PR, on each clock cycle. When the two
values match, the comparator resets the value of TMR2
to 00h on the next cycle and increments the output
Timer Clock Sources TMR2_clk postscaler counter. When the postscaler count equals
(See Table 23-3) the value in the OUTPS<4:0> bits of the TMRxCON1
register then a one clock period wide pulse occurs on the
TMR2_postscaled output, and the postscaler count is
cleared.
23.1.2 ONE-SHOT MODE

The One-Shot mode is identical to the Free Running
Period mode except that the ON bit is cleared and the
23.1 Timer2 Operation timer is stopped when TMR2 matches T2PR and will
not restart until the T2ON bit is cycled off and on.
Timer2 operates in three major modes: Postscaler OUTPS<4:0> values other than 0 are
• Free Running Period meaningless in this mode because the timer is stopped
at the first period event and the postscaler is reset
• One-shot
when the timer is restarted.
• Monostable
Within each mode there are several options for starting, 23.1.3 MONOSTABLE MODE
stopping, and reset. Table 23-1 lists the options. Monostable modes are similar to One-Shot modes
In all modes, the TMR2 count register is incremented except that the ON bit is not cleared and the timer can
on the rising edge of the clock signal from the program- be restarted by an external Reset event.
mable prescaler. When TMR2 equals T2PR, a high
level is output to the postscaler counter. TMR2 is 23.2 PRx Period Register
cleared on the next clock input.
The PRx period register is double buffered. Software
An external signal from hardware can also be config- reads and writes the PRx register. However, the timer
ured to gate the timer operation or force a TMR2 count uses a buffered PRx register for operation. Software
Reset. In Gate modes the counter stops when the gate does not have direct access to the buffered PRx
is disabled and resumes when the gate is enabled. In register. The contents of the PRx register is transferred
Reset modes the TMR2 count is reset on either the to the buffer by any of the following events:
level or edge from the external source.
• A write to the TMRx register
The TMR2 register is directly readable and writable.
• A write to the TMRxCON register
The TMR2 register is cleared on any device Reset. The
T2PR register is double-buffered and initializes to 0xFF • When TMRx = PRx buffer and the prescaler rolls
on any device Reset. The SFR is directly readable and over
writable, but the actual period buffer is only updated • An external Reset event
with the SFR value when the following events occur:
• a write to the TMR2 register
• a write to the T2CON register
• a write to the T2HLT register
• TMR2 = T2PR and the prescaler is full
• External Reset Source event that resets the timer
Both the prescaler and postscaler counters are cleared
on the following events:
• a write to the TMR2 register
• a write to the T2CON register
• any device Reset
• External Reset Source event that resets the timer.

PIC16(L)F1615/9
23.3 Timer2 Output
The Timer2 module’s primary output is TMR2_posts-
caled, which pulses for a single TMR2_clk period when
the postscaler counter matches the value in the
OUTPS bits of the TMR2xCON register. The T2PR
postscaler is incremented each time the TMR2 value
matches the T2PR value. This signal can be selected
as an input to several other input modules:
• The ADC module, as an Auto-conversion Trigger
• CWG, as an auto-shutdown source
In addition, the Timer2 is also used by the CCP module
for pulse generation in PWM mode. Both the actual
TMR2 value as well as other internal signals are sent to
the CCP module to properly clock both the period and
pulse width of the PWM signal. See Section
26.4 “CCP/PWM Clock Selection” for more details on
setting up Timer2 for use with the CCP, as well as the
timing diagrams in Section 23.6 “Operation Exam-
ples” for examples of how the varying Timer2 modes
affect CCP PWM output.
23.4 External Reset Sources

In addition to the clock source, the Timer2 also takes in
an external Reset source. This external Reset source
is selected for Timer2, Timer4, and Timer6 with the
T2RST, T4RST, and T6RST registers, respectively.
This source can control starting and stopping of the
timer, as well as resetting the timer, depending on
which mode the timer is in. The mode of the timer is
controlled by the MODE<4:0> bits of the TMRxHLT
register. Edge-Triggered modes require six Timer clock
periods between external triggers. Level-Triggered
modes require the triggering level to be at least three
Timer clock periods long. External triggers are ignored
while in Debug Freeze mode.

PIC16(L)F1615/9
TABLE 23-1: TIMER2 OPERATING MODES

MODE<4:0> Output Timer Control
Mode Operation
<4:3> <2:0> Operation Start Reset Stop
000 Software gate (Figure 23-4) ON = 1 — ON = 0
Hardware gate, active-high ON = 1 and — ON = 0 or
001 Period
(Figure 23-5) TMRx_ers = 1 TMRx_ers = 0
Pulse
ON = 1 and — ON = 0 or
010 Hardware gate, active-low
TMRx_ers = 0 TMRx_ers = 1
Free 011 Rising or falling edge Reset TMRx_ers ↕
Running 00
Period 100 Period Rising edge Reset (Figure 23-6) TMRx_ers ↑ ON = 0
101 Pulse Falling edge Reset TMRx_ers ↓
with ON = 1 ON = 0 or
110 Hardware Low level Reset TMRx_ers = 0
TMRx_ers = 0
Reset
High level Reset (Figure 23-7) ON = 0 or
111 TMRx_ers = 1
TMRx_ers = 1
000 One-shot Software start (Figure 23-8) ON = 1 —
ON = 1 and
001 Rising edge start (Figure 23-9) —
Edge TMRx_ers ↑
triggered ON = 1 and
010 Falling edge start —
start TMRx_ers ↓
(Note 1) ON = 1 and ON = 0
011 Any edge start — or
TMRx_ers ↕
Next clock
One-shot 01 Rising edge start and ON = 1 and
100 TMRx_ers ↑ after
Edge Rising edge Reset (Figure 23-10) TMRx_ers ↑ TMRx = PRx
triggered Falling edge start and ON = 1 and (Note 2)
101 start TMRx_ers ↓
Falling edge Reset TMRx_ers ↓
and
hardware Rising edge start and ON = 1 and
110 TMRx_ers = 0
Reset Low level Reset (Figure 23-11) TMRx_ers ↑
(Note 1) Falling edge start and ON = 1 and
111 TMRx_ers = 1
High level Reset TMRx_ers ↓
000 Reserved
Rising edge start ON = 1 and ON = 0
001 —
Edge (Figure 23-12) TMRx_ers ↑ or
Mono-stable triggered ON = 1 and Next clock
010 Falling edge start —
start TMRx_ers ↓ after
(Note 1) ON = 1 and TMRx = PRx
011 Any edge start — (Note 3)
TMRx_ers ↕
Reserved 10 100 Reserved
Reserved 101 Reserved
Level High level start and ON = 1 and
110 TMRx_ers = 0
triggered Low level Reset (Figure 23-13) TMRx_ers = 1
ON = 0 or
start
One-shot Held in Reset
and Low level start & ON = 1 and
111 TMRx_ers = 1 (Note 2)
hardware High level Reset TMRx_ers = 0
Reset
Reserved 11 xxx Reserved
Note 1: If ON = 0 then an edge is required to restart the timer after ON = 1.
2: When TMRx = PRx then the next clock clears ON and stops TMRx at 00h.
3: When TMRx = PRx then the next clock stops TMRx at 00h but does not clear ON.

PIC16(L)F1615/9
23.5 Timer2 Interrupt
Timer2 can also generate a device interrupt. The
interrupt is generated when the postscaler counter
matches one of 16 postscale options (from 1:1 through
1:16), which are selected with the postscaler control
bits, OUTPS<3:0> of the T2CON register. The interrupt
is enabled by setting the TMR2IE interrupt enable bit of
the PIE1 register. Interrupt timing is illustrated in
Figure 23-3.
FIGURE 23-3: TIMER2 PRESCALER, POSTSCALER, AND INTERRUPT TIMING DIAGRAM

Rev. 10-000205A
4/7/2016
CKPS 0b010
PRx 1
OUTPS 0b0001
TMRx_clk
TMRx 0 1 0 1 0 1 0
TMRx_postscaled
(1) (2) (1)

TMRxIF
Note 1: Setting the interrupt flag is synchronized with the instruction clock.
Synchronization may take as many as 2 instruction cycles
2: Cleared by software.

PIC16(L)F1615/9
23.6 Operation Examples 23.6.1 SOFTWARE GATE MODE
Unless otherwise specified, the following notes apply to This mode corresponds to legacy Timer2 operation.
the following timing diagrams: The timer increments with each clock input when
ON = 1 and does not increment when ON = 0. When
- Both the prescaler and postscaler are set to the TMRx count equals the PRx period count the timer
1:1 (both the CKPS and OUTPS bits in the resets on the next clock and continues counting from 0.
TxCON register are cleared). Operation with the ON bit software controlled is illus-
- The diagrams illustrate any clock except trated in Figure 23-4. With PRx = 5, the counter
Fosc/4 and show clock-sync delays of at advances until TMRx = 5, and goes to zero with the
least two full cycles for both ON and next clock.
Timer2_ers. When using Fosc/4, the clock-
sync delay is at least one instruction period
for Timer2_ers; ON applies in the next
instruction period.
- The PWM Duty Cycle and PWM output are
illustrated assuming that the timer is used for
the PWM function of the CCP module as
described in Section 26.4 “CCP/PWM Clock
Selection”. The signals are not a part of the
Timer2 module.
FIGURE 23-4: SOFTWARE GATE MODE TIMING DIAGRAM (MODE = 00000)

Rev. 10-000195B
5/30/2014
MODE 0b00000
TMRx_clk
Instruction(1) BSF BCF BSF
ON
PRx 5
TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.

PIC16(L)F1615/9
23.6.2 HARDWARE GATE MODE When MODE<4:0> = 00001 then the timer is stopped
when the external signal is high. When
The Hardware Gate modes operate the same as the
MODE<4:0> = 00010 then the timer is stopped when
Software Gate mode except the TMRx_ers external
the external signal is low.
signal can also gate the timer. When used with the CCP
the gating extends the PWM period. If the timer is Figure 23-5 illustrates the Hardware Gating mode for
stopped when the PWM output is high then the duty MODE<4:0> = 00001 in which a high input level starts
cycle is also extended. the counter.
FIGURE 23-5: HARDWARE GATE MODE TIMING DIAGRAM (MODE = 00001)

Rev. 10-000 196B
5/30/201 4
MODE 0b00001
TMRx_clk
TMRx_ers
PRx 5
TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0 1
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output

PIC16(L)F1615/9
23.6.3 EDGE-TRIGGERED HARDWARE When the timer is used in conjunction with the CCP in
LIMIT MODE PWM mode then an early Reset shortens the period
and restarts the PWM pulse after a two-clock delay.
In Hardware Limit mode the timer can be reset by the
Refer to Figure 23-6.
TMRx_ers external signal before the timer reaches the
period count. Three types of Resets are possible:
• Reset on rising or falling edge
(MODE<4:0>= 00011)
• Reset on rising edge (MODE<4:0> = 00100)
• Reset on falling edge (MODE<4:0> = 00101)
FIGURE 23-6: EDGE-TRIGGERED HARDWARE LIMIT MODE TIMING DIAGRAM

(MODE = 00100)
Rev. 10-000 197B
5/30/201 4
MODE 0b00100
TMRx_clk
PRx 5
ON
TMRx_ers
TMRx 0 1 2 0 1 2 3 4 5 0 1 2 3 4 5 0 1
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output

PIC16(L)F1615/9
23.6.4 LEVEL-TRIGGERED HARDWARE When the CCP uses the timer as the PWM time base
LIMIT MODE then the PWM output will be set high when the timer
starts counting and then set low only when the timer
In the Level-Triggered Hardware Limit Timer modes the
count matches the CCPRx value. The timer is reset
counter is reset by high or low levels of the external
when either the timer count matches the PRx value or
signal TMRx_ers, as shown in Figure 23-7. Selecting
two clock periods after the external Reset signal goes
MODE<4:0> = 00110 will cause the timer to reset on a
true and stays true.
low level external signal. Selecting
MODE<4:0> = 00111 will cause the timer to reset on a The timer starts counting, and the PWM output is set
high level external signal. In the example, the counter high, on either the clock following the PRx match or two
is reset while TMRx_ers = 1. ON is controlled by BSF clocks after the external Reset signal relinquishes the
and BCF instructions. When ON = 0 the external signal Reset. The PWM output will remain high until the timer
is ignored. counts up to match the CCPRx pulse width value. If the
external Reset signal goes true while the PWM output
is high then the PWM output will remain high until the
Reset signal is released allowing the timer to count up
to match the CCPRx value.
FIGURE 23-7: LEVEL-TRIGGERED HARDWARE LIMIT MODE TIMING DIAGRAM

(MODE = 00111)
Rev. 10-000198B
5/30/2014
MODE 0b00111
TMRx_clk
PRx 5
ON
TMRx_ers
TMRx 0 1 2 0 1 2 3 4 5 0 0 1 2 3 4 5 0
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output

PIC16(L)F1615/9
23.6.5 SOFTWARE START ONE-SHOT When One-Shot mode is used in conjunction with the
MODE CCP PWM operation the PWM pulse drive starts con-
current with setting the ON bit. Clearing the ON bit
In One-Shot mode the timer resets and the ON bit is
while the PWM drive is active will extend the PWM
cleared when the timer value matches the PRx period
drive. The PWM drive will terminate when the timer
value. The ON bit must be set by software to start
value matches the CCPRx pulse width value. The
another timer cycle. Setting MODE<4:0> = 01000
PWM drive will remain off until software sets the ON bit
selects One-Shot mode which is illustrated in
to start another cycle. If software clears the ON bit after
Figure 23-8. In the example, ON is controlled by BSF
the CCPRx match but before the PRx match then the
and BCF instructions. In the first case, a BSF instruc-
PWM drive will be extended by the length of time the
tion sets ON and the counter runs to completion and
ON bit remains cleared. Another timing cycle can only
clears ON. In the second case, a BSF instruction starts
be initiated by setting the ON bit after it has been
the cycle, BCF/BSF instructions turn the counter off
cleared by a PRx period count match.
and on during the cycle, and then it runs to completion.
FIGURE 23-8: SOFTWARE START ONE-SHOT MODE TIMING DIAGRAM (MODE = 01000)
Rev. 10-000199B
4/7/2016
MODE 0b01000
TMRx_clk
PRx 5
Instruction(1) BSF BSF BCF BSF
ON
TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions
executed by the CPU to set or clear the ON bit of TxCON. CPU
execution is asynchronous to the timer clock input.

PIC16(L)F1615/9
23.6.6 EDGE-TRIGGERED ONE-SHOT If the timer is halted by clearing the ON bit then another
MODE TMRx_ers edge is required after the ON bit is set to
resume counting. Figure 23-9 illustrates operation in
The Edge-Triggered One-Shot modes start the timer the rising edge One-Shot mode.
on an edge from the external signal input, after the ON
When Edge-Triggered One-Shot mode is used in con-
bit is set, and clear the ON bit when the timer matches
junction with the CCP then the edge-trigger will activate
the PRx period value. The following edges will start the the PWM drive and the PWM drive will deactivate when
timer: the timer matches the CCPRx pulse width value and
• Rising edge (MODE<4:0> = 01001) stay deactivated when the timer halts at the PRx period
• Falling edge (MODE<4:0> = 01010) count match.
• Rising or Falling edge (MODE<4:0> = 01011)
FIGURE 23-9: EDGE-TRIGGERED ONE-SHOT MODE TIMING DIAGRAM (MODE = 01001)

Rev. 10-000200B
5/19/2016
MODE 0b01001
TMRx_clk
PRx 5
Instruction(1) BSF BSF BCF
ON
TMRx_ers
TMRx 0 1 2 3 4 5 0 1 2
CCP_pset
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output

PIC16(L)F1615/9
23.6.7 EDGE-TRIGGERED HARDWARE
LIMIT ONE-SHOT MODE
In Edge-Triggered Hardware Limit One-Shot modes
the timer starts on the first external signal edge after
the ON bit is set and resets on all subsequent edges.
Only the first edge after the ON bit is set is needed to
start the timer. The counter will resume counting
automatically two clocks after all subsequent external
Reset edges. Edge triggers are as follows:
• Rising edge start and Reset
(MODE<4:0> = 01100)
• Falling edge start and Reset
(MODE<4:0> = 01101)
The timer resets and clears the ON bit when the timer
value matches the PRx period value. External signal
edges will have no effect until after software sets the
ON bit. Figure 23-10 illustrates the rising edge hard-
ware limit one-shot operation.
When this mode is used in conjunction with the CCP
then the first starting edge trigger, and all subsequent
Reset edges, will activate the PWM drive. The PWM
drive will deactivate when the timer matches the
CCPRx pulse-width value and stay deactivated until
the timer halts at the PRx period match unless an exter-
nal signal edge resets the timer before the match
occurs.

FIGURE 23-10: EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 01100)
Rev. 10-000201B
4/7/2016
MODE 0b01100
TMRx_clk
PRx 5
Instruction(1) BSF BSF
ON
TMRx_ers
TMRx 0 1 2 3 4 5 0 1 2 0 1 2 3 4 5 0
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output
PIC16(L)F1615/9
DS40001770D-page 247
PIC16(L)F1615/9
23.6.8 LEVEL RESET, EDGE-TRIGGERED
HARDWARE LIMIT ONE-SHOT
MODES
In Level -Triggered One-Shot mode the timer count is
reset on the external signal level and starts counting
on the rising/falling edge of the transition from Reset
level to the active level while the ON bit is set. Reset
levels are selected as follows:
• Low Reset level (MODE<4:0> = 01110)
• High Reset level (MODE<4:0> = 01111)
When the timer count matches the PRx period count,
the timer is reset and the ON bit is cleared. When the
ON bit is cleared by either a PRx match or by software
control a new external signal edge is required after the
ON bit is set to start the counter.
When Level-Triggered Reset One-Shot mode is used
in conjunction with the CCP PWM operation the PWM
drive goes active with the external signal edge that
starts the timer. The PWM drive goes inactive when the
timer count equals the CCPRx pulse width count. The
PWM drive does not go active when the timer count
clears at the PRx period count match.

FIGURE 23-11: LOW LEVEL RESET, EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 01110)
Rev. 10-000202B
4/7/2016
MODE 0b01110
TMRx_clk
PRx 5
Instruction(1) BSF BSF
ON
TMRx_ers
TMRx 0 1 2 3 4 5 0 1 0 1 2 3 4 5 0
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output
PIC16(L)F1615/9
DS40001770D-page 249
PIC16(L)F1615/9
23.6.9 EDGE-TRIGGERED MONOSTABLE
MODES
The Edge-Triggered Monostable modes start the timer
on an edge from the external Reset signal input, after
the ON bit is set, and stop incrementing the timer when
the timer matches the PRx period value. The following
edges will start the timer:
• Rising edge (MODE<4:0> = 10001)
• Falling edge (MODE<4:0> = 10010)
• Rising or Falling edge (MODE<4:0> = 10011)
When an Edge-Triggered Monostable mode is used in
conjunction with the CCP PWM operation the PWM
drive goes active with the external Reset signal edge
that starts the timer, but will not go active when the
timer matches the PRx value. While the timer is incre-
menting, additional edges on the external Reset signal
will not affect the CCP PWM.

FIGURE 23-12: RISING EDGE-TRIGGERED MONOSTABLE MODE TIMING DIAGRAM (MODE = 10001)
Rev. 10-000203A
4/7/2016
MODE 0b10001
TMRx_clk
PRx 5
Instruction(1) BSF BCF BSF BCF BSF
ON
TMRx_ers
TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output
PIC16(L)F1615/9
DS40001770D-page 251
PIC16(L)F1615/9
23.6.10 LEVEL-TRIGGERED HARDWARE
LIMIT ONE-SHOT MODES
The Level-Triggered Hardware Limit One-Shot modes
hold the timer in Reset on an external Reset level and
start counting when both the ON bit is set and the exter-
nal signal is not at the Reset level. If one of either the
external signal is not in Reset or the ON bit is set then
the other signal being set/made active will start the
timer. Reset levels are selected as follows:
• Low Reset level (MODE<4:0> = 10110)
• High Reset level (MODE<4:0> = 10111)
When the timer count matches the PRx period count,
the timer is reset and the ON bit is cleared. When the
ON bit is cleared by either a PRx match or by software
control the timer will stay in Reset until both the ON bit
is set and the external signal is not at the Reset level.
When Level-Triggered Hardware Limit One-Shot
modes are used in conjunction with the CCP PWM
operation the PWM drive goes active with either the
external signal edge or the setting of the ON bit, which-
ever of the two starts the timer.

FIGURE 23-13: LEVEL-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 10110)
Rev. 10-000204A
4/7/2016
MODE 0b10110
TMR2_clk
PRx 5
Instruction(1) BSF BSF BCF BSF
ON
TMR2_ers
TMRx 0 1 2 3 4 5 0 1 2 3 0 1 2 3 4 5 0
TMR2_postscaled
PWM Duty
‘D3
Cycle
PWM Output
PIC16(L)F1615/9
DS40001770D-page 253
PIC16(L)F1615/9
23.7 Timer2 Operation During Sleep
When PSYNC = 1, Timer2 cannot be operated while
the processor is in Sleep mode. The contents of the
TMR2 and T2PR registers will remain unchanged while
processor is in Sleep mode.
When PSYNC = 0, Timer2 will operate in Sleep as long
as the clock source selected is also still running.
Selecting the LFINTOSC, MFINTOSC, or HFINTOSC
oscillator as the timer clock source will keep the
selected oscillator running during Sleep.

PIC16(L)F1615/9
23.8 Register Definitions: Timer2/4/6 Control
Long bit name prefixes for the Timer2/4/6 peripherals
are shown in Table 23-2. Refer to Section
1.1.2.2 “Long Bit Names” for more information
TABLE 23-2:
Peripheral Bit Name Prefix
Timer2 T2
Timer4 T4
Timer6 T6
REGISTER 23-1: TxCLKCON: TIMERx CLOCK SELECTION REGISTER

U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — CS<3:0>
bit 7 bit 0
Legend:

bit 3-0 CS<3:0>: Timerx Clock Selection bits
See Table 23-3.
TABLE 23-3: TIMERX CLOCK SOURCES

CS<3:0> Timer2 Timer4 Timer6
1101-1111 Reserved Reserved Reserved
1011 AT1_perclk AT1_perclk AT1_perclk
1010 LC4_out LC4_out LC4_out
0110 Pin selected by T2INPPS Pin selected by T2INPPS Pin selected by T2INPPS
0101 MFINTOSC 31.25 kHz MFINTOSC 31.25 kHz MFINTOSC 31.25 kHz
0100 ZCD1_output ZCD1_output ZCD1_output
0011 LFINTOSC LFINTOSC LFINTOSC
0010 HFINTOSC 16 MHz HFINTOSC 16 MHz HFINTOSC 16 MHz
0001 Fosc Fosc Fosc
0000 Fosc/4 Fosc/4 Fosc/4

PIC16(L)F1615/9
REGISTER 23-2: TxCON: TIMERx CONTROL REGISTER

R/W/HC-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
ON(1) CKPS<2:0> OUTPS<3:0>
bit 7 bit 0
Legend:
bit 7 ON: Timerx On bit

1 = Timerx is on
0 = Timerx is off: all counters and state machines are reset
bit 6-4 CKPS<2:0>: Timer2-type Clock Prescale Select bits
111 = 1:128 Prescaler
011 = 1:8 Prescaler
010 = 1:4 Prescaler
001 = 1:2 Prescaler
000 = 1:1 Prescaler
bit 3-0 OUTPS<3:0>: Timerx Output Postscaler Select bits
1111 = 1:16 Postscaler
Note 1: In certain modes, the ON bit will be auto-cleared by hardware. See Section 23.6 “Operation Examples”.

PIC16(L)F1615/9
REGISTER 23-3: TxHLT: TIMERx HARDWARE LIMIT CONTROL REGISTER

PSYNC(1, 2) CKPOL(3) CKSYNC(4, 5) MODE<4:0>(6, 7)
bit 7 bit 0
Legend:
bit 7 PSYNC: Timerx Prescaler Synchronization Enable bit(1, 2)

1 = TMRx Prescaler Output is synchronized to Fosc/4
0 = TMRx Prescaler Output is not synchronized to Fosc/4
bit 6 CKPOL: Timerx Clock Polarity Selection bit(3)
1 = Falling edge of input clock clocks timer/prescaler
0 = Rising edge of input clock clocks timer/prescaler
bit 5 CKSYNC: Timerx Clock Synchronization Enable bit(4, 5)
1 = ON register bit is synchronized to TMR2_clk input
0 = ON register bit is not synchronized to TMR2_clk input
bit 4-0 MODE<4:0>: Timerx Control Mode Selection bits(6, 7)
See Table 23-1.
Note 1: Setting this bit ensures that reading TMRx will return a valid value.
2: When this bit is ‘1’, Timer2 cannot operate in Sleep mode.
3: CKPOL should not be changed while ON = 1.
4: Setting this bit ensures glitch-free operation when the ON is enabled or disabled.
5: When this bit is set then the timer operation will be delayed by two TMRx input clocks after the ON bit is set.
6: Unless otherwise indicated, all modes start upon ON = 1 and stop upon ON = 0 (stops occur without affecting the value
of TMRx).
7: When TMRx = PRx, the next clock clears TMRx, regardless of the operating mode.

PIC16(L)F1615/9
REGISTER 23-4: TXRST: TIMERX EXTERNAL RESET SIGNAL SELECTION REGISTER

U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — RSEL<3:0>
bit 7 bit 0
Legend:

bit 3-0 RSEL<4:0>: TimerX External Reset Signal Source Selection bits
See Table 23-4.
TABLE 23-4: EXTERNAL RESET SOURCES

RSEL<4:0> Timer2 Timer4 Timer6
1111 Reserved Reserved Reserved
1110 PWM4_out PWM4_out PWM4_out
1101 PWM3_out PWM3_out PWM3_out
1000 ZCD1_out ZCD1_out ZCD1_out
0111 TMR6_postscaled TMR6_postscaled Reserved
0110 TMR4_postscaled Reserved TMR4_postscaled
0101 Reserved TMR2_postscaled TMR2_postscaled
0100 CCP2_out CCP2_out CCP2_out
0011 CCP1_out CCP1_out CCP1_out
0010 C2OUT_sync C2OUT_sync C2OUT_sync
0001 C1OUT_sync C1OUT_sync C1OUT_sync
0000 Pin selected by T2INPPS Pin selected by T2INPPS Pin selected by T2INPPS

PIC16(L)F1615/9
Register
on Page
CCP1CON EN — OUT FMT MODE<3:0> 354
PIE1 TMR1GIE ADIE — — — CCP1IE TMR2IE TMR1IE 98
PR2 Timer2 Module Period Register 244*
TMR2 Holding Register for the 8-bit TMR2 Register 236*
T2CON ON CKPS<2:0> OUTPS<3:0> 256
T2CLKCON — — — — CS<3:0> 255
T2RST — — — — RSEL<3:0> 258
T2HLT PSYNC CKPOL CKSYNC MODE<4:0> 257
T4CLKCON — — — — CS<3:0> 255
T4RST — — — — RSEL<3:0> 258
T6CLKCON — — — — — T6CS<2:0> 255
T6RST — — — — RSEL<3:0> 258
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module.

PIC16(L)F1615/9
24.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
24.1 MSSP Module Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
The SPI interface supports the following modes and
features:
• Master mode
• Slave mode
• Clock Parity
• Slave Select Synchronization (Slave mode only)
• Daisy-chain connection of slave devices
Figure 24-1 is a block diagram of the SPI interface
module.
FIGURE 24-1: MSSP BLOCK DIAGRAM (SPI MODE)
Data Bus
Read Write
SSPxBUF Reg
SSPDATPPS
SDI
PPS SSPSR Reg
SDO bit 0 Shift
Clock
PPS
RxyPPS
SS SS Control 2 (CKP, CKE)

PPS Enable Clock Select
Edge
SSPSSPPS Select
SSPCLKPPS(2) SSPM<3:0>
SCK PPS
4
( T2_match
2
)
Edge Prescaler TOSC
PPS Select 4, 16, 64
TRIS bit RxyPPS(1) Baud Rate

Generator
(SSPxADD)
Note 1: Output selection for master mode.
2: Input selection for slave mode.

PIC16(L)F1615/9
The I2C interface supports the following modes and
features:
• Master mode
• Slave mode
• Byte NACKing (Slave mode)
• Limited multi-master support
• 7-bit and 10-bit addressing
• Start and Stop interrupts
• Interrupt masking
• Clock stretching
• Bus collision detection
• General call address matching
• Address masking
• Address Hold and Data Hold modes
• Selectable SDA hold times
Figure 24-2 is a block diagram of the I2C interface mod-
ule in Master mode. Figure 24-3 is a diagram of the I2C
interface module in Slave mode.
FIGURE 24-2: MSSP BLOCK DIAGRAM (I2C MASTER MODE)
Internal
data bus [SSPM<3:0>]
SSPDATPPS(1) Read Write
SDA
SDA in
PPS SSPxBUF Baud Rate
Generator
(SSPxADD)
Shift
RxyPPS(1) Clock
Clock arbitrate/BCOL detect

SSPSR
Clock Cntl
PPS
(Hold off clock source)

MSb LSb
Receive Enable (RCEN)
Start bit, Stop bit,

Acknowledge
SSPCLKPPS(2) Generate (SSPxCON2)
SCL
PPS
PPS
Start bit detect,

RxyPPS(2) Stop bit detect
Write collision detect Set/Reset: S, P, SSPxSTAT, WCOL, SSPOV
SCL in
Clock arbitration Reset SEN, PEN (SSPxCON2)
State counter for Set SSP1IF, BCL1IF
Bus Collision end of XMIT/RCV
Address Match detect
Note 1: SDA pin selections must be the same for input and output.
2: SCL pin selections must be the same for input and output.

PIC16(L)F1615/9
FIGURE 24-3: MSSP BLOCK DIAGRAM (I2C SLAVE MODE)
Internal
Data Bus
Read Write
SSPCLKPPS(2) SSPxBUF Reg

SCL
PPS
Shift
Clock
Clock
PPS Stretching SSPSR Reg
MSb LSb
RxyPPS(2)
SSPxMSK Reg
SSPDATPPS(1)
SDA Match Detect Addr Match
PPS
SSPxADD Reg
PPS
Start and Set, Reset
RxyPPS(1) Stop bit Detect S, P bits
(SSPxSTAT Reg)
Note 1: SDA pin selections must be the same for input and output.
2: SCL pin selections must be the same for input and output.

PIC16(L)F1615/9
24.2 SPI Mode Overview its SDO pin) and the slave device is reading this bit and
saving it as the LSb of its shift register, that the slave
The Serial Peripheral Interface (SPI) bus is a device is also sending out the MSb from its shift register
synchronous serial data communication bus that (on its SDO pin) and the master device is reading this
operates in Full-Duplex mode. Devices communicate bit and saving it as the LSb of its shift register.
in a master/slave environment where the master device
initiates the communication. A slave device is After eight bits have been shifted out, the master and
controlled through a Chip Select known as Slave slave have exchanged register values.
Select. If there is more data to exchange, the shift registers are
The SPI bus specifies four signal connections: loaded with new data and the process repeats itself.
• Serial Clock (SCK) Whether the data is meaningful or not (dummy data),
depends on the application software. This leads to
• Serial Data Out (SDO)
three scenarios for data transmission:
• Serial Data In (SDI)
• Master sends useful data and slave sends dummy
• Slave Select (SS)
data.
Figure 24-1 shows the block diagram of the MSSP • Master sends useful data and slave sends useful
module when operating in SPI mode. data.
The SPI bus operates with a single master device and • Master sends dummy data and slave sends useful
one or more slave devices. When multiple slave data.
devices are used, an independent Slave Select
Transmissions may involve any number of clock
connection is required from the master device to each
cycles. When there is no more data to be transmitted,
slave device.
the master stops sending the clock signal and it
Figure 24-4 shows a typical connection between a deselects the slave.
master device and multiple slave devices.
Every slave device connected to the bus that has not
The master selects only one slave at a time. Most slave been selected through its slave select line must disre-
devices have tri-state outputs so their output signal gard the clock and transmission signals and must not
appears disconnected from the bus when they are not transmit out any data of its own.
selected.
Transmissions involve two shift registers, eight bits in
size, one in the master and one in the slave. With either
the master or the slave device, data is always shifted
out one bit at a time, with the Most Significant bit (MSb)
shifted out first. At the same time, a new Least
Significant bit (LSb) is shifted into the same register.
Figure 24-5 shows a typical connection between two
processors configured as master and slave devices.
Data is shifted out of both shift registers on the
programmed clock edge and latched on the opposite
edge of the clock.
The master device transmits information out on its SDO
output pin which is connected to, and received by, the
slave’s SDI input pin. The slave device transmits infor-
mation out on its SDO output pin, which is connected
to, and received by, the master’s SDI input pin.
To begin communication, the master device first sends
out the clock signal. Both the master and the slave
devices should be configured for the same clock polar-
ity.
The master device starts a transmission by sending out
the MSb from its shift register. The slave device reads
this bit from that same line and saves it into the LSb
position of its shift register.
During each SPI clock cycle, a full-duplex data

transmission occurs. This means that while the master
device is sending out the MSb from its shift register (on

PIC16(L)F1615/9
FIGURE 24-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION
SCK SCK
SPI Master
SDO SDI SPI Slave
SDI SDO #1
General I/O SS
General I/O
General I/O SCK
SDI SPI Slave
SDO #2
SS
SCK
SDI SPI Slave
SDO #3
SS
24.2.1 SPI MODE REGISTERS 24.2.2 SPI MODE OPERATION

The MSSP module has five registers for SPI mode When initializing the SPI, several options need to be
operation. These are: specified. This is done by programming the appropriate
• MSSP STATUS register (SSPxSTAT) control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
These control bits allow the following to be specified:
• MSSP Control register 1 (SSPxCON1)
• MSSP Control register 3 (SSPxCON3) • Master mode (SCK is the clock output)
• MSSP Data Buffer register (SSPxBUF) • Slave mode (SCK is the clock input)
• MSSP Address register (SSPxADD) • Clock Polarity (Idle state of SCK)
• MSSP Shift register (SSPSR) • Data Input Sample Phase (middle or end of data
(Not directly accessible) output time)
• Clock Edge (output data on rising/falling edge of
SSPxCON1 and SSPxSTAT are the control and
SCK)
STATUS registers in SPI mode operation. The
SSPxCON1 register is readable and writable. The • Clock Rate (Master mode only)
lower six bits of the SSPxSTAT are read-only. The • Slave Select mode (Slave mode only)
upper two bits of the SSPxSTAT are read/write. To enable the serial port, SSP Enable bit, SSPEN of the
In one SPI master mode, SSPxADD can be loaded SSPxCON1 register, must be set. To reset or reconfig-
with a value used in the Baud Rate Generator. More ure SPI mode, clear the SSPEN bit, re-initialize the
information on the Baud Rate Generator is available in SSPxCONx registers and then set the SSPEN bit. This
Section 24.7 “Baud Rate Generator”. configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port
SSPSR is the shift register used for shifting data in and
function, some must have their data direction bits (in
out. SSPxBUF provides indirect access to the SSPSR
the TRIS register) appropriately programmed as
register. SSPxBUF is the buffer register to which data
follows:
bytes are written, and from which data bytes are read.
• SDI must have corresponding TRIS bit set
In receive operations, SSPSR and SSPxBUF together
create a buffered receiver. When SSPSR receives a • SDO must have corresponding TRIS bit cleared
complete byte, it is transferred to SSPxBUF and the • SCK (Master mode) must have corresponding
SSPxIF interrupt is set. TRIS bit cleared
During transmission, the SSPxBUF is not buffered. A • SCK (Slave mode) must have corresponding
write to SSPxBUF will write to both SSPxBUF and TRIS bit set
SSPSR. • SS must have corresponding TRIS bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.

PIC16(L)F1615/9
The MSSP consists of a transmit/receive shift register When the application software is expecting to receive
(SSPSR) and a buffer register (SSPxBUF). The valid data, the SSPxBUF should be read before the
SSPSR shifts the data in and out of the device, MSb next byte of data to transfer is written to the SSPxBUF.
first. The SSPxBUF holds the data that was written to The Buffer Full bit, BF of the SSPxSTAT register,
the SSPSR until the received data is ready. Once the indicates when SSPxBUF has been loaded with the
eight bits of data have been received, that byte is received data (transmission is complete). When the
moved to the SSPxBUF register. Then, the Buffer Full SSPxBUF is read, the BF bit is cleared. This data may
Detect bit, BF of the SSPxSTAT register, and the inter- be irrelevant if the SPI is only a transmitter. Generally,
rupt flag bit, SSPxIF, are set. This double-buffering of the MSSP interrupt is used to determine when the
the received data (SSPxBUF) allows the next byte to transmission/reception has completed. If the interrupt
start reception before reading the data that was just method is not going to be used, then software polling
received. Any write to the SSPxBUF register during can be done to ensure that a write collision does not
transmission/reception of data will be ignored and the occur.
write collision detect bit WCOL of the SSPxCON1 reg- The SSPSR is not directly readable or writable and can
ister, will be set. User software must clear the WCOL bit only be accessed by addressing the SSPxBUF register.
to allow the following write(s) to the SSPxBUF register Additionally, the SSPxSTAT register indicates the
to complete successfully. various Status conditions.
FIGURE 24-5: SPI MASTER/SLAVE CONNECTION
SPI Master SSPM<3:0> = 00xx SPI Slave SSPM<3:0> = 010x

= 1010
SDO SDI
Serial Input Buffer Serial Input Buffer

(BUF) (SSPxBUF)
Shift Register SDI SDO Shift Register

(SSPSR) (SSPSR)
MSb LSb MSb LSb
Serial Clock
SCK SCK
Slave Select
General I/O SS
Processor 1 (optional) Processor 2

PIC16(L)F1615/9
24.2.3 SPI MASTER MODE The clock polarity is selected by appropriately
programming the CKP bit of the SSPxCON1 register
The master can initiate the data transfer at any time
and the CKE bit of the SSPxSTAT register. This then,
because it controls the SCK line. The master
would give waveforms for SPI communication as
determines when the slave (Processor 2, Figure 24-5)
shown in Figure 24-6, Figure 24-8, Figure 24-9 and
is to broadcast data by the software protocol.
Figure 24-10, where the MSB is transmitted first. In
In Master mode, the data is transmitted/received as Master mode, the SPI clock rate (bit rate) is user
soon as the SSPxBUF register is written to. If the SPI programmable to be one of the following:
is only going to receive, the SDO output could be
• FOSC/4 (or TCY)
disabled (programmed as an input). The SSPSR
register will continue to shift in the signal present on the • FOSC/16 (or 4 * TCY)
SDI pin at the programmed clock rate. As each byte is • FOSC/64 (or 16 * TCY)
received, it will be loaded into the SSPxBUF register as • Timer2 output/2
if a normal received byte (interrupts and Status bits • FOSC/(4 * (SSPxADD + 1))
appropriately set).
Figure 24-6 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPxBUF is loaded with the received
data is shown.
Note: In Master mode the clock signal output to
the SCK pin is also the clock signal input
to the peripheral. The pin selected for out-
put with the RxyPPS register must also be
selected as the peripheral input with the
SSPCLKPPS register.

PIC16(L)F1615/9
FIGURE 24-6: SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPxBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
SCK Modes
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

(CKE = 0)

(CKE = 1)
SDI
(SMP = 0) bit 7 bit 0
Input
Sample
(SMP = 0)
SDI
(SMP = 1) bit 0
bit 7
Input
Sample
(SMP = 1)
SSPxIF
SSPSR to
SSPxBUF
24.2.4 SPI SLAVE MODE 24.2.4.1 Daisy-Chain Configuration

In Slave mode, the data is transmitted and received as The SPI bus can sometimes be connected in a daisy-
external clock pulses appear on SCK. When the last chain configuration. The first slave output is connected
bit is latched, the SSPxIF interrupt flag bit is set. to the second slave input, the second slave output is
Before enabling the module in SPI Slave mode, the clock connected to the third slave input, and so on. The final
line must match the proper Idle state. The clock line can slave output is connected to the master input. Each
be observed by reading the SCK pin. The Idle state is slave sends out, during a second group of clock
determined by the CKP bit of the SSPxCON1 register. pulses, an exact copy of what was received during the
first group of clock pulses. The whole chain acts as
While in Slave mode, the external clock is supplied by one large communication shift register. The daisy-
the external clock source on the SCK pin. This external chain feature only requires a single Slave Select line
clock must meet the minimum high and low times as from the master device.
specified in the electrical specifications.
Figure 24-7 shows the block diagram of a typical
While in Sleep mode, the slave can transmit/receive daisy-chain connection when operating in SPI mode.
data. The shift register is clocked from the SCK pin
input and when a byte is received, the device will In a daisy-chain configuration, only the most recent
generate an interrupt. If enabled, the device will wake- byte on the bus is required by the slave. Setting the
up from Sleep. BOEN bit of the SSPxCON3 register will enable writes
to the SSPxBUF register, even if the previous byte has
not been read. This allows the software to ignore data
that may not apply to it.

PIC16(L)F1615/9
24.2.5 SLAVE SELECT When the SS pin is low, transmission and reception are
SYNCHRONIZATION enabled and the SDO pin is driven.
The Slave Select can also be used to synchronize When the SS pin goes high, the SDO pin is no longer
communication. The Slave Select line is held high until driven, even if in the middle of a transmitted byte and
the master device is ready to communicate. When the becomes a floating output. External pull-up/pull-down
Slave Select line is pulled low, the slave knows that a resistors may be desirable depending on the applica-
new transmission is starting. tion.
If the slave fails to receive the communication properly, Note 1: When the SPI is in Slave mode with SS pin
it will be reset at the end of the transmission, when the control enabled (SSPxCON1<3:0> =
Slave Select line returns to a high state. The slave is 0100), the SPI module will reset if the SS
then ready to receive a new transmission when the pin is set to VDD.
Slave Select line is pulled low again. If the Slave Select 2: When the SPI is used in Slave mode with
line is not used, there is a risk that the slave will CKE set; the user must enable SS pin
eventually become out of sync with the master. If the control.
slave misses a bit, it will always be one bit off in future
transmissions. Use of the Slave Select line allows the 3: While operated in SPI Slave mode the
slave and master to align themselves at the beginning SMP bit of the SSPxSTAT register must
of each transmission. remain clear.
The SS pin allows a Synchronous Slave mode. The When the SPI module resets, the bit counter is forced
SPI must be in Slave mode with SS pin control enabled to ‘0’. This can be done by either forcing the SS pin to
(SSPxCON1<3:0> = 0100). a high level or clearing the SSPEN bit.
FIGURE 24-7: SPI DAISY-CHAIN CONNECTION
SCK SCK
SPI Master
SDO SDI SPI Slave
SDI SDO #1
General I/O SS
SCK
SDI SPI Slave
SDO #2
SS
SCK
SDI SPI Slave
SDO #3
SS

PIC16(L)F1615/9
FIGURE 24-8: SLAVE SELECT SYNCHRONOUS WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPxBUF
Shift register SSPSR
and bit count are reset
SSPxBUF to
SSPSR
SDO bit 7 bit 6 bit 7 bit 6 bit 0
SDI bit 0
bit 7 bit 7
Input
Sample
SSPxIF
Interrupt
Flag
SSPSR to
SSPxBUF

PIC16(L)F1615/9
FIGURE 24-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPxBUF
Valid
SDI
bit 7 bit 0
Input
Sample
SSPxIF
Interrupt
Flag
SSPSR to
SSPxBUF
Write Collision
detection active
FIGURE 24-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPxBUF
Valid
SDI
bit 7 bit 0
Input
Sample
SSPxIF
Interrupt
Flag
SSPSR to
SSPxBUF
Write Collision
detection active

PIC16(L)F1615/9
24.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmission/
In SPI Master mode, module clocks may be operating
reception will remain in that state until the device
at a different speed than when in Full-Power mode; in
wakes. After the device returns to Run mode, the
the case of the Sleep mode, all clocks are halted.
module will resume transmitting and receiving data.
Special care must be taken by the user when the MSSP
In SPI Slave mode, the SPI Transmit/Receive Shift
clock is much faster than the system clock.
register operates asynchronously to the device. This
In Slave mode, when MSSP interrupts are enabled, allows the device to be placed in Sleep mode and data
after the master completes sending data, an MSSP to be shifted into the SPI Transmit/Receive Shift
interrupt will wake the controller from Sleep. register. When all eight bits have been received, the
If an exit from Sleep mode is not desired, MSSP MSSP interrupt flag bit will be set and if enabled, will
interrupts should be disabled. wake the device.
TABLE 24-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION

Register
on Page

RxyPPS — — — RxyPPS<4:0> 172
SSPCLKPPS — — — SSPCLKPPS<4:0> 174, 172
SSPDATPPS — — — SSPDATPPS<4:0> 174, 172
SSPSSPPS — — — SSPSSPPS<4:0> 174, 172
SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register 264*
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 309
SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 308
SSP1STAT SMP CKE D/A P S R/W UA BF 308
TRISB(2) TRISB7 TRISB6 TRISB5 TRISB4 — — — — 158
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.

PIC16(L)F1615/9
24.3 I2C MODE OVERVIEW FIGURE 24-11: I2C MASTER/
SLAVE CONNECTION
The Inter-Integrated Circuit (I2C) bus is a multi-master
serial data communication bus. Devices communicate
in a master/slave environment where the master VDD
devices initiate the communication. A slave device is
controlled through addressing. SCL SCL
The I2C bus specifies two signal connections:
VDD
• Serial Clock (SCL) Master Slave
• Serial Data (SDA)
SDA SDA
Figure 24-11 shows the block diagram of the MSSP
module when operating in I2C mode.
Both the SCL and SDA connections are bidirectional
open-drain lines, each requiring pull-up resistors for the The Acknowledge bit (ACK) is an active-low signal,
supply voltage. Pulling the line to ground is considered which holds the SDA line low to indicate to the transmit-
a logical zero and letting the line float is considered a ter that the slave device has received the transmitted
logical one. data and is ready to receive more.
Figure 24-11 shows a typical connection between two The transition of a data bit is always performed while
processors configured as master and slave devices. the SCL line is held low. Transitions that occur while the
The I2C bus can operate with one or more master SCL line is held high are used to indicate Start and Stop
devices and one or more slave devices. bits.
There are four potential modes of operation for a given If the master intends to write to the slave, then it repeat-
device: edly sends out a byte of data, with the slave responding
after each byte with an ACK bit. In this example, the
• Master Transmit mode
master device is in Master Transmit mode and the
(master is transmitting data to a slave)
slave is in Slave Receive mode.
• Master Receive mode
(master is receiving data from a slave) If the master intends to read from the slave, then it
repeatedly receives a byte of data from the slave, and
• Slave Transmit mode
responds after each byte with an ACK bit. In this exam-
(slave is transmitting data to a master)
ple, the master device is in Master Receive mode and
• Slave Receive mode the slave is Slave Transmit mode.
(slave is receiving data from the master)
On the last byte of data communicated, the master
To begin communication, a master device starts out in device may end the transmission by sending a Stop bit.
Master Transmit mode. The master device sends out a If the master device is in Receive mode, it sends the
Start bit followed by the address byte of the slave it Stop bit in place of the last ACK bit. A Stop bit is
intends to communicate with. This is followed by a indicated by a low-to-high transition of the SDA line
single Read/Write bit, which determines whether the while the SCL line is held high.
master intends to transmit to or receive data from the
slave device. In some cases, the master may want to maintain
control of the bus and re-initiate another transmission.
If the requested slave exists on the bus, it will respond If so, the master device may send another Start bit in
with an Acknowledge bit, otherwise known as an ACK. place of the Stop bit or last ACK bit when it is in receive
The master then continues in either Transmit mode or mode.
Receive mode and the slave continues in the comple-
ment, either in Receive mode or Transmit mode, The I2C bus specifies three message protocols;
respectively. • Single message where a master writes data to a
A Start bit is indicated by a high-to-low transition of the slave.
SDA line while the SCL line is held high. Address and • Single message where a master reads data from
data bytes are sent out, Most Significant bit (MSb) first. a slave.
The Read/Write bit is sent out as a logical one when the • Combined message where a master initiates a
master intends to read data from the slave, and is sent minimum of two writes, or two reads, or a
out as a logical zero when it intends to write data to the combination of writes and reads, to one or more
slave. slaves.

PIC16(L)F1615/9
When one device is transmitting a logical one, or letting 24.3.2 ARBITRATION
the line float, and a second device is transmitting a log-
Each master device must monitor the bus for Start and
ical zero, or holding the line low, the first device can
Stop bits. If the device detects that the bus is busy, it
detect that the line is not a logical one. This detection,
cannot begin a new message until the bus returns to an
when used on the SCL line, is called clock stretching.
Idle state.
Clock stretching gives slave devices a mechanism to
control the flow of data. When this detection is used on However, two master devices may try to initiate a trans-
the SDA line, it is called arbitration. Arbitration ensures mission on or about the same time. When this occurs,
that there is only one master device communicating at the process of arbitration begins. Each transmitter
any single time. checks the level of the SDA data line and compares it
to the level that it expects to find. The first transmitter to
24.3.1 CLOCK STRETCHING observe that the two levels do not match, loses arbitra-
tion, and must stop transmitting on the SDA line.
When a slave device has not completed processing
data, it can delay the transfer of more data through the For example, if one transmitter holds the SDA line to a
process of clock stretching. An addressed slave device logical one (lets it float) and a second transmitter holds
may hold the SCL clock line low after receiving or send- it to a logical zero (pulls it low), the result is that the
ing a bit, indicating that it is not yet ready to continue. SDA line will be low. The first transmitter then observes
The master that is communicating with the slave will that the level of the line is different than expected and
attempt to raise the SCL line in order to transfer the concludes that another transmitter is communicating.
next bit, but will detect that the clock line has not yet The first transmitter to notice this difference is the one
been released. Because the SCL connection is open- that loses arbitration and must stop driving the SDA
drain, the slave has the ability to hold that line low until line. If this transmitter is also a master device, it also
it is ready to continue communicating. must stop driving the SCL line. It then can monitor the
Clock stretching allows receivers that cannot keep up lines for a Stop condition before trying to reissue its
with a transmitter to control the flow of incoming data. transmission. In the meantime, the other device that
has not noticed any difference between the expected
and actual levels on the SDA line continues with its
original transmission. It can do so without any compli-
cations, because so far, the transmission appears
exactly as expected with no other transmitter disturbing
the message.
Slave Transmit mode can also be arbitrated, when a
master addresses multiple slaves, but this is less
common.
If two master devices are sending a message to two
different slave devices at the address stage, the master
sending the lower slave address always wins arbitra-
tion. When two master devices send messages to the
same slave address, and addresses can sometimes
refer to multiple slaves, the arbitration process must
continue into the data stage.
Arbitration usually occurs very rarely, but it is a
necessary process for proper multi-master support.

PIC16(L)F1615/9
24.4 I2C MODE OPERATION TABLE 24-2: I2C BUS TERMS
TERM Description
All MSSP I2C communication is byte oriented and
shifted out MSb first. Six SFR registers and two Transmitter The device which shifts data out
interrupt flags interface the module with the PIC® onto the bus.
microcontroller and user software. Two pins, SDA and Receiver The device which shifts data in
SCL, are exercised by the module to communicate from the bus.
with other external I2C devices. Master The device that initiates a transfer,
generates clock signals and termi-
24.4.1 BYTE FORMAT nates a transfer.
All communication in I2C is done in 9-bit segments. A Slave The device addressed by the
byte is sent from a master to a slave or vice-versa, fol- master.
lowed by an Acknowledge bit sent back. After the Multi-master A bus with more than one device
eighth falling edge of the SCL line, the device output- that can initiate data transfers.
ting data on the SDA changes that pin to an input and
Arbitration Procedure to ensure that only one
reads in an acknowledge value on the next clock
master at a time controls the bus.
pulse.
Winning arbitration ensures that
The clock signal, SCL, is provided by the master. Data the message is not corrupted.
is valid to change while the SCL signal is low, and Synchronization Procedure to synchronize the
sampled on the rising edge of the clock. Changes on clocks of two or more devices on
the SDA line while the SCL line is high define special the bus.
conditions on the bus, explained below.
Idle No master is controlling the bus,
24.4.2 DEFINITION OF I2C TERMINOLOGY and both SDA and SCL lines are
high.
There is language and terminology in the description
Active Any time one or more master
of I2C communication that have definitions specific to
devices are controlling the bus.
I2C. That word usage is defined below and may be
used in the rest of this document without explanation. Addressed Slave device that has received a
This table was adapted from the Philips I2C Slave matching address and is actively
specification. being clocked by a master.
Matching Address byte that is clocked into a
24.4.3 SDA AND SCL PINS Address slave that matches the value
stored in SSPxADD.
Selection of any I2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain. These Write Request Slave receives a matching
pins should be set by the user to inputs by setting the address with R/W bit clear, and is
appropriate TRIS bits. ready to clock in data.
Read Request Master sends an address byte with
Note 1: Data is tied to output zero when an I2C the R/W bit set, indicating that it
mode is enabled. wishes to clock data out of the
2: Any device pin can be selected for SDA Slave. This data is the next and all
and SCL functions with the PPS peripheral. following bytes until a Restart or
These functions are bidirectional. The SDA Stop.
input is selected with the SSPDATPPS Clock Stretching When a device on the bus holds
registers. The SCL input is selected with SCL low to stall communication.
the SSPCLKPPS registers. Outputs are Bus Collision Any time the SDA line is sampled
selected with the RxyPPS registers. It is the low by the module while it is out-
user’s responsibility to make the selections putting and expected high state.
so that both the input and the output for
each function is on the same pin.
24.4.4 SDA HOLD TIME

The hold time of the SDA pin is selected by the SDAHT
bit of the SSPxCON3 register. Hold time is the time
SDA is held valid after the falling edge of SCL. Setting
the SDAHT bit selects a longer 300 ns minimum hold
time and may help on buses with large capacitance.

PIC16(L)F1615/9
24.4.5 START CONDITION 24.4.7 RESTART CONDITION
The I2C specification defines a Start condition as a A Restart is valid any time that a Stop would be valid.
transition of SDA from a high to a low state while SCL A master can issue a Restart if it wishes to hold the
line is high. A Start condition is always generated by bus after terminating the current transfer. A Restart
the master and signifies the transition of the bus from has the same effect on the slave that a Start would,
an Idle to an Active state. Figure 24-12 shows wave resetting all slave logic and preparing it to clock in an
forms for Start and Stop conditions. address. The master may want to address the same or
A bus collision can occur on a Start condition if the another slave. Figure 24-13 shows the wave form for a
module samples the SDA line low before asserting it Restart condition.
low. This does not conform to the I2C Specification that In 10-bit Addressing Slave mode a Restart is required
states no bus collision can occur on a Start. for the master to clock data out of the addressed slave.
Once a slave has been fully addressed, matching both
24.4.6 STOP CONDITION high and low address bytes, the master can issue a
A Stop condition is a transition of the SDA line from Restart and the high address byte with the R/W bit set.
low-to-high state while the SCL line is high. The slave logic will then hold the clock and prepare to
clock out data.
Note: At least one SCL low time must appear
After a full match with R/W clear in 10-bit mode, a prior
before a Stop is valid, therefore, if the SDA
match flag is set and maintained until a Stop condition, a
line goes low then high again while the SCL
high address with R/W clear, or high address match fails.
line stays high, only the Start condition is
detected.
24.4.8 START/STOP CONDITION
INTERRUPT MASKING
The SCIE and PCIE bits of the SSPxCON3 register
can enable the generation of an interrupt in Slave
modes that do not typically support this function. Slave
modes where interrupt on Start and Stop detect are
already enabled, these bits will have no effect.
FIGURE 24-12: I2C START AND STOP CONDITIONS
SDA
SCL
S P
Change of Change of
Data Allowed Data Allowed
Start Stop
Condition Condition
FIGURE 24-13: I2C RESTART CONDITION
Sr
Change of Change of
Data Allowed Data Allowed
Restart
Condition

PIC16(L)F1615/9
24.4.9 ACKNOWLEDGE SEQUENCE 24.5 I2C SLAVE MODE OPERATION
The 9th SCL pulse for any transferred byte in I2C is
The MSSP Slave mode operates in one of four modes
dedicated as an Acknowledge. It allows receiving
selected by the SSPM bits of SSPxCON1 register. The
devices to respond back to the transmitter by pulling
modes can be divided into 7-bit and 10-bit Addressing
the SDA line low. The transmitter must release control
mode. 10-bit Addressing modes operate the same as
of the line during this time to shift in the response. The
7-bit with some additional overhead for handling the
Acknowledge (ACK) is an active-low signal, pulling the
larger addresses.
SDA line low indicates to the transmitter that the
device has received the transmitted data and is ready Modes with Start and Stop bit interrupts operate the
to receive more. same as the other modes with SSPxIF additionally
getting set upon detection of a Start, Restart, or Stop
The result of an ACK is placed in the ACKSTAT bit of
condition.
the SSPxCON2 register.
Slave software, when the AHEN and DHEN bits are 24.5.1 SLAVE MODE ADDRESSES
set, allow the user to set the ACK value sent back to The SSPxADD register (Register 24-6) contains the
the transmitter. The ACKDT bit of the SSPxCON2 reg- Slave mode address. The first byte received after a
ister is set/cleared to determine the response. Start or Restart condition is compared against the
Slave hardware will generate an ACK response if the value stored in this register. If the byte matches, the
AHEN and DHEN bits of the SSPxCON3 register are value is loaded into the SSPxBUF register and an
clear. interrupt is generated. If the value does not match, the
There are certain conditions where an ACK will not be module goes idle and no indication is given to the
sent by the slave. If the BF bit of the SSPxSTAT regis- software that anything happened.
ter or the SSPOV bit of the SSPxCON1 register are The SSP Mask register (Register 24-5) affects the
set when a byte is received. address matching process. See Section 24.5.8 “SSP
When the module is addressed, after the eighth falling Mask Register” for more information.
edge of SCL on the bus, the ACKTIM bit of the
24.5.1.1 I2C Slave 7-bit Addressing Mode
SSPxCON3 register is set. The ACKTIM bit indicates
the acknowledge time of the active bus. The ACKTIM In 7-bit Addressing mode, the LSb of the received data
Status bit is only active when the AHEN bit or DHEN byte is ignored when determining if there is an address
bit is enabled. match.
24.5.1.2 I2C Slave 10-bit Addressing Mode

In 10-bit Addressing mode, the first received byte is
compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9
and A8 are the two MSb’s of the 10-bit address and
stored in bits 2 and 1 of the SSPxADD register.
After the acknowledge of the high byte the UA bit is set
and SCL is held low until the user updates SSPxADD
with the low address. The low address byte is clocked
in and all eight bits are compared to the low address
value in SSPxADD. Even if there is not an address
match; SSPxIF and UA are set, and SCL is held low
until SSPxADD is updated to receive a high byte
again. When SSPxADD is updated the UA bit is
cleared. This ensures the module is ready to receive
the high address byte on the next communication.
A high and low address match as a write request is
required at the start of all 10-bit addressing communi-
cation. A transmission can be initiated by issuing a
Restart once the slave is addressed, and clocking in
the high address with the R/W bit set. The slave
hardware will then acknowledge the read request and
prepare to clock out data. This is only valid for a slave
after it has received a complete high and low address
byte match.

PIC16(L)F1615/9
24.5.2 SLAVE RECEPTION 24.5.2.2 7-bit Reception with AHEN and
When the R/W bit of a matching received address byte DHEN
is clear, the R/W bit of the SSPxSTAT register is Slave device reception with AHEN and DHEN set
cleared. The received address is loaded into the operate the same as without these options with extra
SSPxBUF register and acknowledged. interrupts and clock stretching added after the eighth
When the overflow condition exists for a received falling edge of SCL. These additional interrupts allow
address, then not Acknowledge is given. An overflow the slave software to decide whether it wants to ACK
condition is defined as either bit BF of the SSPxSTAT the receive address or data byte, rather than the hard-
register is set, or bit SSPOV of the SSPxCON1 register ware. This functionality adds support for PMBus™ that
is set. The BOEN bit of the SSPxCON3 register modi- was not present on previous versions of this module.
fies this operation. For more information see This list describes the steps that need to be taken by
Register 24-4. slave software to use these options for I2C communi-
An MSSP interrupt is generated for each transferred cation. Figure 24-16 displays a module using both
data byte. Flag bit, SSPxIF, must be cleared by soft- address and data holding. Figure 24-17 includes the
ware. operation with the SEN bit of the SSPxCON2 register
set.
When the SEN bit of the SSPxCON2 register is set,
SCL will be held low (clock stretch) following each 1. S bit of SSPxSTAT is set; SSPxIF is set if inter-
received byte. The clock must be released by setting rupt on Start detect is enabled.
the CKP bit of the SSPxCON1 register, except 2. Matching address with R/W bit clear is clocked
sometimes in 10-bit mode. See Section 24.5.6.2 “10- in. SSPxIF is set and CKP cleared after the
bit Addressing Mode” for more detail. eighth falling edge of SCL.
3. Slave clears the SSPxIF.
24.5.2.1 7-bit Addressing Reception 4. Slave can look at the ACKTIM bit of the
This section describes a standard sequence of SSPxCON3 register to determine if the SSPxIF
events for the MSSP module configured as an I2C was after or before the ACK.
slave in 7-bit Addressing mode. Figure 24-14 and 5. Slave reads the address value from SSPxBUF,
Figure 24-15 is used as a visual reference for this clearing the BF flag.
description. 6. Slave sets ACK value clocked out to the master
This is a step by step process of what typically must by setting ACKDT.
be done to accomplish I2C communication. 7. Slave releases the clock by setting CKP.
1. Start bit detected. 8. SSPxIF is set after an ACK, not after a NACK.
2. S bit of SSPxSTAT is set; SSPxIF is set if inter- 9. If SEN = 1 the slave hardware will stretch the
rupt on Start detect is enabled. clock after the ACK.
3. Matching address with R/W bit clear is received. 10. Slave clears SSPxIF.
4. The slave pulls SDA low sending an ACK to the Note: SSPxIF is still set after the 9th falling edge
master, and sets SSPxIF bit. of SCL even if there is no clock stretching
5. Software clears the SSPxIF bit. and BF has been cleared. Only if NACK is
6. Software reads received address from sent to master is SSPxIF not set
SSPxBUF clearing the BF flag. 11. SSPxIF set and CKP cleared after eighth falling
7. If SEN = 1; Slave software sets CKP bit to edge of SCL for a received data byte.
release the SCL line.
12. Slave looks at ACKTIM bit of SSPxCON3 to
8. The master clocks out a data byte. determine the source of the interrupt.
9. Slave drives SDA low sending an ACK to the 13. Slave reads the received data from SSPxBUF
master, and sets SSPxIF bit. clearing BF.
10. Software clears SSPxIF. 14. Steps 7-14 are the same for each received data
11. Software reads the received byte from byte.
SSPxBUF clearing BF. 15. Communication is ended by either the slave
12. Steps 8-12 are repeated for all received bytes sending an ACK = 1, or the master sending a
from the master. Stop condition. If a Stop is sent and Interrupt on
13. Master sends Stop condition, setting P bit of Stop Detect is disabled, the slave will only know
SSPxSTAT, and the bus goes idle. by polling the P bit of the SSTSTAT register.

FIGURE 24-14:
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)
Bus Master sends
Stop condition
From Slave to Master
Receiving Address Receiving Data Receiving Data ACK = 1

SDA
A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPxIF
SSPxIF set on 9th
Cleared by software Cleared by software falling edge of
SCL
BF
First byte
SSPxBUF is read of data is
available
in SSPxBUF
PIC16(L)F1615/9
SSPOV
SSPOV set because

SSPxBUF is still full.
ACK is not sent.
DS40001770D-page 278
FIGURE 24-15:
Bus Master sends
Stop condition

Receive Address Receive Data Receive Data ACK
SDA A7 A6 A5 A4 A3 A2 A1 R/W=0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL S 1 2 3 4 5 6 7 8 9 SEN 1 2 3 4 5 6 7 8 9 SEN 1 2 3 4 5 6 7 8 9 P
Clock is held low until CKP is set to ‘1’
SSPxIF
SSPxIF set on 9th

Cleared by software Cleared by software falling edge of SCL
BF
First byte
of data is
SSPxBUF is read available
in SSPxBUF
SSPOV
PIC16(L)F1615/9
SSPOV set because
SSPxBUF is still full.
ACK is not sent.
CKP
SCL is not held

CKP is written to ‘1’ in software, CKP is written to ‘1’ in software,
low because
DS40001770D-page 279
releasing SCL releasing SCL

ACK= 1
FIGURE 24-16:
Master Releases SDA Master sends
to slave for ACK sequence Stop condition
SDA Receiving Address Receiving Data ACK Received Data ACK=1

A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SCL
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
SSPxIF
If AHEN = 1: SSPxIF is set on
SSPxIF is set 9th falling edge of Cleared by software No interrupt
SCL, after ACK after not ACK
BF from Slave
Address is
read from Data is read from SSPxBUF
ACKDT SSBUF
Slave software
clears ACKDT to Slave software
ACK the received sets ACKDT to
CKP byte not ACK
When AHEN=1:
When DHEN=1: CKP set by software,
CKP is cleared by hardware
CKP is cleared by SCL is released
and SCL is stretched hardware on 8th falling
edge of SCL
ACKTIM
PIC16(L)F1615/9
ACKTIM set by hardware ACKTIM cleared by ACKTIM set by hardware
on 8th falling edge of SCL hardware in 9th on 8th falling edge of SCL
rising edge of SCL
S
DS40001770D-page 280
P
FIGURE 24-17:
Master sends
Stop condition
Master releases
R/W = 0 SDA to slave for ACK sequence
Receiving Address Receive Data Receive Data ACK
SDA

SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
S
SSPxIF
Cleared by software No interrupt after
if not ACK
from Slave
BF
Received
address is loaded into Received data is SSPxBUF can be
SSPxBUF available on SSPxBUF read any time before
next byte is loaded
ACKDT
Slave software clears

Slave sends
ACKDT to ACK not ACK
the received byte
CKP
When AHEN = 1; When DHEN = 1; CKP is not cleared
on the 8th falling edge on the 8th falling edge Set by software, if not ACK
of SCL of an address of SCL of a received release SCL
byte, CKP is cleared data byte, CKP is cleared
PIC16(L)F1615/9
ACKTIM
ACKTIM is set by hardware ACKTIM is cleared by hardware

on 8th falling edge of SCL on 9th rising edge of SCL
S
DS40001770D-page 281
P
PIC16(L)F1615/9
24.5.3 SLAVE TRANSMISSION 24.5.3.2 7-bit Transmission
When the R/W bit of the incoming address byte is set A master device can transmit a read request to a slave,
and an address match occurs, the R/W bit of the and then clock data out of the slave. The list below out-
SSPxSTAT register is set. The received address is lines what software for a slave will need to do to
loaded into the SSPxBUF register, and an ACK pulse is accomplish a standard transmission. Figure 24-18 can
sent by the slave on the ninth bit. be used as a reference to this list.
Following the ACK, slave hardware clears the CKP bit 1. Master sends a Start condition on SDA and
and the SCL pin is held low (see Section SCL.
24.5.6 “Clock Stretching” for more detail). By 2. S bit of SSPxSTAT is set; SSPxIF is set if inter-
stretching the clock, the master will be unable to assert rupt on Start detect is enabled.
another clock pulse until the slave is done preparing 3. Matching address with R/W bit set is received by
the transmit data. the Slave setting SSPxIF bit.
The transmit data must be loaded into the SSPxBUF 4. Slave hardware generates an ACK and sets
register which also loads the SSPSR register. Then the SSPxIF.
SCL pin should be released by setting the CKP bit of 5. SSPxIF bit is cleared by user.
the SSPxCON1 register. The eight data bits are shifted
6. Software reads the received address from
out on the falling edge of the SCL input. This ensures
SSPxBUF, clearing BF.
that the SDA signal is valid during the SCL high time.
7. R/W is set so CKP was automatically cleared
The ACK pulse from the master-receiver is latched on after the ACK.
the rising edge of the ninth SCL input pulse. This ACK
8. The slave software loads the transmit data into
value is copied to the ACKSTAT bit of the SSPxCON2
SSPxBUF.
register. If ACKSTAT is set (not ACK), then the data
transfer is complete. In this case, when the not ACK is 9. CKP bit is set releasing SCL, allowing the
latched by the slave, the slave goes idle and waits for master to clock the data out of the slave.
another occurrence of the Start bit. If the SDA line was 10. SSPxIF is set after the ACK response from the
low (ACK), the next transmit data must be loaded into master is loaded into the ACKSTAT register.
the SSPxBUF register. Again, the SCL pin must be 11. SSPxIF bit is cleared.
released by setting bit CKP. 12. The slave software checks the ACKSTAT bit to
An MSSP interrupt is generated for each data transfer see if the master wants to clock out more data.
byte. The SSPxIF bit must be cleared by software and Note 1: If the master ACKs the clock will be
the SSPxSTAT register is used to determine the status stretched.
of the byte. The SSPxIF bit is set on the falling edge of
the ninth clock pulse. 2: ACKSTAT is the only bit updated on the
rising edge of SCL (9th) rather than the
24.5.3.1 Slave Mode Bus Collision falling.
A slave receives a Read request and begins shifting 13. Steps 9-13 are repeated for each transmitted
data out on the SDA line. If a bus collision is detected byte.
and the SBCDE bit of the SSPxCON3 register is set, 14. If the master sends a not ACK; the clock is not
the BCL1IF bit of the PIR2 register is set. Once a bus held, but SSPxIF is still set.
collision is detected, the slave goes idle and waits to be 15. The master sends a Restart condition or a Stop.
addressed again. User software can use the BCL1IF bit
16. The slave is no longer addressed.
to handle a slave bus collision.

FIGURE 24-18:
Master sends
Stop condition
Receiving Address ACK

R/W = 1 Automatic Transmitting Data Automatic Transmitting Data
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)

SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPxIF
Cleared by software
BF
BF is automatically
Received address Data to transmit is cleared after 8th falling
is read from SSPxBUF loaded into SSPxBUF edge of SCL
CKP
When R/W is set CKP is not
SCL is always held for not
held low after 9th SCL Set by software ACK
falling edge
ACKSTAT
Masters not ACK

is copied to
ACKSTAT
R/W
PIC16(L)F1615/9
R/W is copied from the
matching address byte
D/A
Indicates an address
has been received
DS40001770D-page 283
P
PIC16(L)F1615/9
24.5.3.3 7-bit Transmission with Address
Hold Enabled
Setting the AHEN bit of the SSPxCON3 register
enables additional clock stretching and interrupt
generation after the eighth falling edge of a received
matching address. Once a matching address has
been clocked in, CKP is cleared and the SSPxIF
interrupt is set.
Figure 24-19 displays a standard waveform of a 7-bit
address slave transmission with AHEN enabled.
1. Bus starts Idle.
2. Master sends Start condition; the S bit of
SSPxSTAT is set; SSPxIF is set if interrupt on
Start detect is enabled.
3. Master sends matching address with R/W bit
set. After the eighth falling edge of the SCL line
the CKP bit is cleared and SSPxIF interrupt is
generated.
4. Slave software clears SSPxIF.
5. Slave software reads ACKTIM bit of SSPxCON3
register, and R/W and D/A of the SSPxSTAT
register to determine the source of the interrupt.
6. Slave reads the address value from the
SSPxBUF register clearing the BF bit.
7. Slave software decides from this information if it
wishes to ACK or not ACK and sets the ACKDT
bit of the SSPxCON2 register accordingly.
8. Slave sets the CKP bit releasing SCL.
9. Master clocks in the ACK value from the slave.
10. Slave hardware automatically clears the CKP bit
and sets SSPxIF after the ACK if the R/W bit is
set.
11. Slave software clears SSPxIF.
12. Slave loads value to transmit to the master into
SSPxBUF setting the BF bit.
Note: SSPxBUF cannot be loaded until after the
ACK.
13. Slave sets the CKP bit releasing the clock.
14. Master clocks out the data from the slave and
sends an ACK value on the 9th SCL pulse.
15. Slave hardware copies the ACK value into the
ACKSTAT bit of the SSPxCON2 register.
16. Steps 10-15 are repeated for each byte transmit-
ted to the master from the slave.
17. If the master sends a not ACK the slave
releases the bus allowing the master to send a
Stop and end the communication.
Note: Master must send a not ACK on the last
byte to ensure that the slave releases the
SCL line to receive a Stop.

FIGURE 24-19:
Master sends
Master releases SDA Stop condition
to slave for ACK sequence
Receiving Address R/W = 1 Automatic Transmitting Data Automatic Transmitting Data ACK
SDA
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)

SCL
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
P
SSPxIF
Cleared by software
BF BF is automatically
Received address Data to transmit is cleared after 8th falling
is read from SSPxBUF loaded into SSPxBUF edge of SCL
ACKDT
Slave clears
ACKDT to ACK
address
ACKSTAT
Master’s ACK
response is copied
to SSPxSTAT
CKP
When AHEN = 1; CKP not cleared
CKP is cleared by hardware When R/W = 1;
PIC16(L)F1615/9
Set by software, after not ACK
after receiving matching CKP is always releases SCL
address. cleared after ACK
ACKTIM
ACKTIM is set on 8th falling ACKTIM is cleared
edge of SCL on 9th rising edge of SCL
DS40001770D-page 285
R/W
D/A
PIC16(L)F1615/9
24.5.4 SLAVE MODE 10-BIT ADDRESS 24.5.5 10-BIT ADDRESSING WITH
RECEPTION ADDRESS OR DATA HOLD
This section describes a standard sequence of events Reception using 10-bit addressing with AHEN or
for the MSSP module configured as an I2C slave in DHEN set is the same as with 7-bit modes. The only
10-bit Addressing mode. difference is the need to update the SSPxADD register
Figure 24-20 is used as a visual reference for this using the UA bit. All functionality, specifically when the
description. CKP bit is cleared and SCL line is held low are the
same. Figure 24-21 can be used as a reference of a
This is a step by step process of what must be done by slave in 10-bit addressing with AHEN set.
slave software to accomplish I2C communication.
Figure 24-22 shows a standard waveform for a slave
1. Bus starts Idle. transmitter in 10-bit Addressing mode.
2. Master sends Start condition; S bit of SSPxSTAT
is set; SSPxIF is set if interrupt on Start detect is
enabled.
3. Master sends matching high address with R/W
bit clear; UA bit of the SSPxSTAT register is set.
4. Slave sends ACK and SSPxIF is set.
5. Software clears the SSPxIF bit.
6. Software reads received address from
SSPxBUF clearing the BF flag.
7. Slave loads low address into SSPxADD,
releasing SCL.
8. Master sends matching low address byte to the
slave; UA bit is set.
Note: Updates to the SSPxADD register are not
allowed until after the ACK sequence.
9. Slave sends ACK and SSPxIF is set.

Note: If the low address does not match, SSPxIF
and UA are still set so that the slave soft-
ware can set SSPxADD back to the high
address. BF is not set because there is no
match. CKP is unaffected.
10. Slave clears SSPxIF.
11. Slave reads the received matching address
from SSPxBUF clearing BF.
12. Slave loads high address into SSPxADD.
13. Master clocks a data byte to the slave and
clocks out the slaves ACK on the 9th SCL pulse;
SSPxIF is set.
14. If SEN bit of SSPxCON2 is set, CKP is cleared
by hardware and the clock is stretched.
15. Slave clears SSPxIF.
16. Slave reads the received byte from SSPxBUF
clearing BF.
17. If SEN is set the slave sets CKP to release the
SCL.
18. Steps 13-17 repeat for each received byte.
19. Master sends Stop to end the transmission.

FIGURE 24-20:
Master sends
Stop condition

Receive First Address Byte Receive Second Address Byte Receive Data Receive Data
SDA
1 1 1 1
0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
S
SCL is held low
while CKP = 0
SSPxIF
Set by hardware Cleared by software
on 9th falling edge
BF
If address matches Receive address is Data is read
SSPxADD it is loaded into read from SSPxBUF from SSPxBUF
SSPxBUF
UA
PIC16(L)F1615/9
When UA = 1; Software updates SSPxADD
SCL is held low and releases SCL
CKP
DS40001770D-page 287
When SEN = 1; Set by software,

CKP is cleared after releasing SCL
9th falling edge of received byte
FIGURE 24-21:
Receive First Address Byte R/W = 0 Receive Second Address Byte Receive Data Receive Data
SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5

SCL S 1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 1 2
SSPxIF
Set by hardware Cleared by software Cleared by software
on 9th falling edge
BF
SSPxBUF can be Received data

read anytime before is read from
the next received byte SSPxBUF
ACKDT
Slave software clears
ACKDT to ACK
the received byte
UA
PIC16(L)F1615/9
Update to SSPxADD is Update of SSPxADD,
not allowed until 9th
falling edge of SCL clears UA and releases
SCL
CKP If when AHEN = 1;

on the 8th falling edge Set CKP with software
DS40001770D-page 288
of SCL of an address releases SCL

byte, CKP is cleared
ACKTIM
ACKTIM is set by hardware
on 8th falling edge of SCL
FIGURE 24-22:
Master sends
Master sends Stop condition
I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)

Restart event Master sends
not ACK
Receiving Address R/W = 0 Receiving Second Address Byte Receive First Address Byte Transmitting Data Byte ACK = 1
SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
S
Sr
SSPxIF
Set by hardware Cleared by software Set by hardware
BF
SSPxBUF loaded Received address is Data to transmit is

with received address read from SSPxBUF loaded into SSPxBUF
UA
High address is loaded
UA indicates SSPxADD After SSPxADD is back into SSPxADD
must be updated updated, UA is cleared
CKP and SCL is released
PIC16(L)F1615/9
When R/W = 1; Set by software
ACKSTAT CKP is cleared on releases SCL
9th falling edge of SCL
Masters not ACK

is copied
R/W
DS40001770D-page 289
R/W is copied from the

matching address byte
D/A
Indicates an address
has been received
PIC16(L)F1615/9
24.5.6 CLOCK STRETCHING 24.5.6.2 10-bit Addressing Mode
Clock stretching occurs when a device on the bus In 10-bit Addressing mode, when the UA bit is set the
holds the SCL line low, effectively pausing communi- clock is always stretched. This is the only time the SCL
cation. The slave may stretch the clock to allow more is stretched without CKP being cleared. SCL is
time to handle data or prepare a response for the released immediately after a write to SSPxADD.
master device. A master device is not concerned with
Note: Previous versions of the module did not
stretching as anytime it is active on the bus and not
stretch the clock if the second address byte
transferring data it is stretching. Any stretching done
did not match.
by a slave is invisible to the master software and
handled by the hardware that generates SCL.
24.5.6.3 Byte NACKing
The CKP bit of the SSPxCON1 register is used to
control stretching in software. Any time the CKP bit is When the AHEN bit of SSPxCON3 is set; CKP is
cleared, the module will wait for the SCL line to go low cleared by hardware after the eighth falling edge of
and then hold it. Setting CKP will release SCL and SCL for a received matching address byte. When the
allow more communication. DHEN bit of SSPxCON3 is set; CKP is cleared after
the eighth falling edge of SCL for received data.
24.5.6.1 Normal Clock Stretching Stretching after the eighth falling edge of SCL allows
Following an ACK if the R/W bit of SSPxSTAT is set, a the slave to look at the received address or data and
read request, the slave hardware will clear CKP. This decide if it wants to ACK the received data.
allows the slave time to update SSPxBUF with data to
transfer to the master. If the SEN bit of SSPxCON2 is 24.5.6.4 Clock Synchronization and
set, the slave hardware will always stretch the clock the CKP Bit
after the ACK sequence. Once the slave is ready; CKP Any time the CKP bit is cleared, the module will wait
is set by software and communication resumes. for the SCL line to go low and then hold it. However,
clearing the CKP bit will not assert the SCL output low
Note 1:The BF bit has no effect on if the clock will
until the SCL output is already sampled low. There-
be stretched or not. This is different than
fore, the CKP bit will not assert the SCL line until an
previous versions of the module that
external I2C master device has already asserted the
would not stretch the clock, clear CKP, if
SCL line. The SCL output will remain low until the CKP
SSPxBUF was read before the 9th falling
bit is set and all other devices on the I2C bus have
edge of SCL.
released SCL. This ensures that a write to the CKP bit
2: Previous versions of the module did not will not violate the minimum high time requirement for
stretch the clock for a transmission if SCL (see Figure 24-23).
SSPxBUF was loaded before the 9th
falling edge of SCL. It is now always
cleared for read requests.
FIGURE 24-23: CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA DX DX ‚ – 1
SCL
Master device
CKP asserts clock
Master device
releases clock
WR
SSPxCON1

PIC16(L)F1615/9
24.5.7 GENERAL CALL ADDRESS R/W bit clear, an interrupt is generated and slave soft-
SUPPORT ware can read SSPxBUF and respond. Figure 24-24
shows a general call reception sequence.
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually deter- In 10-bit Address mode, the UA bit will not be set on
mines which device will be the slave addressed by the the reception of the general call address. The slave
master device. The exception is the general call will prepare to receive the second byte as data, just as
address which can address all devices. When this it would in 7-bit mode.
address is used, all devices should, in theory, respond If the AHEN bit of the SSPxCON3 register is set, just
with an acknowledge. as with any other address reception, the slave hard-
The general call address is a reserved address in the ware will stretch the clock after the eighth falling edge
I2C protocol, defined as address 0x00. When the of SCL. The slave must then set its ACKDT value and
GCEN bit of the SSPxCON2 register is set, the slave release the clock with communication progressing as it
module will automatically ACK the reception of this would normally.
address regardless of the value stored in SSPxADD.
After the slave clocks in an address of all zeros with the
FIGURE 24-24: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE

Address is compared to General Call Address
after ACK, set interrupt
R/W = 0 Receiving Data ACK

SDA General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
SSPxIF
BF (SSPxSTAT<0>)
Cleared by software
SSPxBUF is read
GCEN (SSPxCON2<7>)
’1’
24.5.8 SSP MASK REGISTER

An SSP Mask (SSPxMSK) register (Register 24-5) is
available in I2C Slave mode as a mask for the value
held in the SSPSR register during an address
comparison operation. A zero (‘0’) bit in the SSPxMSK
register has the effect of making the corresponding bit
of the received address a “don’t care”.
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSP operation until written with a mask value.
The SSP Mask register is active during:
• 7-bit Address mode: address compare of A<7:1>.
• 10-bit Address mode: address compare of A<7:0>
only. The SSP mask has no effect during the
reception of the first (high) byte of the address.

PIC16(L)F1615/9
24.6 I2C Master Mode 24.6.1 I2C MASTER MODE OPERATION
Master mode is enabled by setting and clearing the The master device generates all of the serial clock
appropriate SSPM bits in the SSPxCON1 register and pulses and the Start and Stop conditions. A transfer is
by setting the SSPEN bit. In Master mode, the SDA and ended with a Stop condition or with a Repeated Start
SCK pins must be configured as inputs. The MSSP condition. Since the Repeated Start condition is also
peripheral hardware will override the output driver TRIS the beginning of the next serial transfer, the I2C bus will
controls when necessary to drive the pins low. not be released.
Master mode of operation is supported by interrupt In Master Transmitter mode, serial data is output
generation on the detection of the Start and Stop through SDA, while SCL outputs the serial clock. The
conditions. The Stop (P) and Start (S) bits are cleared first byte transmitted contains the slave address of the
from a Reset or when the MSSP module is disabled. receiving device (7 bits) and the Read/Write (R/W) bit.
Control of the I 2C bus may be taken when the P bit is In this case, the R/W bit will be logic ‘0’. Serial data is
set, or the bus is Idle. transmitted eight bits at a time. After each byte is
transmitted, an Acknowledge bit is received. Start and
In Firmware Controlled Master mode, user code Stop conditions are output to indicate the beginning
conducts all I 2C bus operations based on Start and and the end of a serial transfer.
Stop bit condition detection. Start and Stop condition
detection is the only active circuitry in this mode. All In Master Receive mode, the first byte transmitted
other communication is done by the user software contains the slave address of the transmitting device
directly manipulating the SDA and SCL lines. (7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
The following events will cause the SSP Interrupt Flag address followed by a ‘1’ to indicate the receive bit.
bit, SSPxIF, to be set (SSP interrupt, if enabled): Serial data is received via SDA, while SCL outputs the
• Start condition detected serial clock. Serial data is received eight bits at a time.
After each byte is received, an Acknowledge bit is
• Stop condition detected
transmitted. Start and Stop conditions indicate the
• Data transfer byte transmitted/received beginning and end of transmission.
• Acknowledge transmitted/received
A Baud Rate Generator is used to set the clock
• Repeated Start generated frequency output on SCL. See Section 24.7 “Baud
Note 1:The MSSP module, when configured in I2C Rate Generator” for more detail.
Master mode, does not allow queuing of
events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPxBUF register
to initiate transmission before the Start
condition is complete. In this case, the
SSPxBUF will not be written to and the
WCOL bit will be set, indicating that a
write to the SSPxBUF did not occur
2: Master mode suspends Start/Stop
detection when sending the Start/Stop
condition by means of the SEN/PEN
control bits. The SSPxIF bit is set at the
end of the Start/Stop generation when
hardware clears the control bit.

PIC16(L)F1615/9
24.6.2 CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
releases the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the Baud Rate
Generator (BRG) is suspended from counting until the
SCL pin is actually sampled high. When the SCL pin is
sampled high, the Baud Rate Generator is reloaded
with the contents of SSPxADD<7:0> and begins count-
ing. This ensures that the SCL high time will always be
at least one BRG rollover count in the event that the
clock is held low by an external device (Figure 24-25).
FIGURE 24-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA DX DX ‚ – 1
SCL deasserted but slave holds SCL allowed to transition high

SCL low (clock arbitration)
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
03h 02h 01h 00h (hold off) 03h 02h
Value
SCL is sampled high, reload takes

place and BRG starts its count
BRG
Reload
24.6.3 WCOL STATUS FLAG

If the user writes the SSPxBUF when a Start, Restart,
Stop, Receive or Transmit sequence is in progress, the
WCOL bit is set and the contents of the buffer are
unchanged (the write does not occur). Any time the
WCOL bit is set it indicates that an action on SSPxBUF
was attempted while the module was not idle.
Note: Because queuing of events is not allowed,
writing to the lower five bits of SSPxCON2
is disabled until the Start condition is
complete.

PIC16(L)F1615/9
24.6.4 I2C MASTER MODE START by hardware; the Baud Rate Generator is suspended,
CONDITION TIMING leaving the SDA line held low and the Start condition is
complete.
To initiate a Start condition (Figure 24-26), the user
sets the Start Enable bit, SEN bit of the SSPxCON2 Note 1: If at the beginning of the Start condition,
register. If the SDA and SCL pins are sampled high, the SDA and SCL pins are already
the Baud Rate Generator is reloaded with the contents sampled low, or if during the Start condi-
of SSPxADD<7:0> and starts its count. If SCL and tion, the SCL line is sampled low before
SDA are both sampled high when the Baud Rate Gen- the SDA line is driven low, a bus collision
erator times out (TBRG), the SDA pin is driven low. The occurs, the Bus Collision Interrupt Flag,
action of the SDA being driven low while SCL is high is BCL1IF, is set, the Start condition is
the Start condition and causes the S bit of the aborted and the I2C module is reset into
SSPxSTAT1 register to be set. Following this, the its Idle state.
Baud Rate Generator is reloaded with the contents of 2: The Philips I2C specification states that a
SSPxADD<7:0> and resumes its count. When the bus collision cannot occur on a Start.
Baud Rate Generator times out (TBRG), the SEN bit of
the SSPxCON2 register will be automatically cleared
FIGURE 24-26: FIRST START BIT TIMING
Write to SEN bit occurs here Set S bit (SSPxSTAT<3>)
At completion of Start bit,

SDA = 1,
SCL = 1 hardware clears SEN bit
and sets SSPxIF bit
TBRG TBRG Write to SSPxBUF occurs here
SDA 1st bit 2nd bit
TBRG
SCL
S
TBRG

PIC16(L)F1615/9
24.6.5 I2C MASTER MODE REPEATED cally cleared and the Baud Rate Generator will not be
START CONDITION TIMING reloaded, leaving the SDA pin held low. As soon as a
Start condition is detected on the SDA and SCL pins,
A Repeated Start condition (Figure 24-27) occurs when
the S bit of the SSPxSTAT register will be set. The
the RSEN bit of the SSPxCON2 register is pro-
SSPxIF bit will not be set until the Baud Rate Generator
grammed high and the master state machine is no lon-
has timed out.
ger active. When the RSEN bit is set, the SCL pin is
asserted low. When the SCL pin is sampled low, the Note 1: If RSEN is programmed while any other
Baud Rate Generator is loaded and begins counting. event is in progress, it will not take effect.
The SDA pin is released (brought high) for one Baud 2: A bus collision during the Repeated Start
Rate Generator count (TBRG). When the Baud Rate condition occurs if:
Generator times out, if SDA is sampled high, the SCL
pin will be deasserted (brought high). When SCL is •SDA is sampled low when SCL goes
sampled high, the Baud Rate Generator is reloaded from low-to-high.
and begins counting. SDA and SCL must be sampled •SCL goes low before SDA is
high for one TBRG. This action is then followed by asserted low. This may indicate
assertion of the SDA pin (SDA = 0) for one TBRG while that another master is attempting
SCL is high. SCL is asserted low. Following this, the to transmit a data ‘1’.
RSEN bit of the SSPxCON2 register will be automati-
FIGURE 24-27: REPEATED START CONDITION WAVEFORM
S bit set by hardware

Write to SSPxCON2
occurs here At completion of Start bit,
SDA = 1, SDA = 1,
hardware clears RSEN bit
SCL (no change) SCL = 1 and sets SSPxIF
TBRG TBRG TBRG
SDA 1st bit
Write to SSPxBUF occurs here

TBRG
SCL
Sr TBRG
Repeated Start

PIC16(L)F1615/9
24.6.6 I2C MASTER MODE 24.6.6.3 ACKSTAT Status Flag
TRANSMISSION In Transmit mode, the ACKSTAT bit of the SSPxCON2
Transmission of a data byte, a 7-bit address or the register is cleared when the slave has sent an Acknowl-
other half of a 10-bit address is accomplished by simply edge (ACK = 0) and is set when the slave does not
writing a value to the SSPxBUF register. This action will Acknowledge (ACK = 1). A slave sends an Acknowl-
set the Buffer Full flag bit, BF, and allow the Baud Rate edge when it has recognized its address (including a
Generator to begin counting and start the next trans- general call), or when the slave has properly received
mission. Each bit of address/data will be shifted out its data.
onto the SDA pin after the falling edge of SCL is
asserted. SCL is held low for one Baud Rate Generator 24.6.6.4 Typical Transmit Sequence:
rollover count (TBRG). Data should be valid before SCL 1. The user generates a Start condition by setting
is released high. When the SCL pin is released high, it the SEN bit of the SSPxCON2 register.
is held that way for TBRG. The data on the SDA pin 2. SSPxIF is set by hardware on completion of the
must remain stable for that duration and some hold Start.
time after the next falling edge of SCL. After the eighth
3. SSPxIF is cleared by software.
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA. 4. The MSSP module will wait the required start
This allows the slave device being addressed to time before any other operation takes place.
respond with an ACK bit during the ninth bit time if an 5. The user loads the SSPxBUF with the slave
address match occurred, or if data was received prop- address to transmit.
erly. The status of ACK is written into the ACKSTAT bit 6. Address is shifted out the SDA pin until all eight
on the rising edge of the ninth clock. If the master bits are transmitted. Transmission begins as
receives an Acknowledge, the Acknowledge Status bit, soon as SSPxBUF is written to.
ACKSTAT, is cleared. If not, the bit is set. After the ninth 7. The MSSP module shifts in the ACK bit from the
clock, the SSPxIF bit is set and the master clock (Baud slave device and writes its value into the
Rate Generator) is suspended until the next data byte ACKSTAT bit of the SSPxCON2 register.
is loaded into the SSPxBUF, leaving SCL low and SDA
8. The MSSP module generates an interrupt at the
unchanged (Figure 24-28).
end of the ninth clock cycle by setting the
After the write to the SSPxBUF, each bit of the address SSPxIF bit.
will be shifted out on the falling edge of SCL until all 9. The user loads the SSPxBUF with eight bits of
seven address bits and the R/W bit are completed. On data.
the falling edge of the eighth clock, the master will
10. Data is shifted out the SDA pin until all eight bits
release the SDA pin, allowing the slave to respond with
are transmitted.
an Acknowledge. On the falling edge of the ninth clock,
the master will sample the SDA pin to see if the address 11. The MSSP module shifts in the ACK bit from the
was recognized by a slave. The status of the ACK bit is slave device and writes its value into the
loaded into the ACKSTAT Status bit of the SSPxCON2 ACKSTAT bit of the SSPxCON2 register.
register. Following the falling edge of the ninth clock 12. Steps 8-11 are repeated for all transmitted data
transmission of the address, the SSPxIF is set, the BF bytes.
flag is cleared and the Baud Rate Generator is turned 13. The user generates a Stop or Restart condition
off until another write to the SSPxBUF takes place, by setting the PEN or RSEN bits of the
holding SCL low and allowing SDA to float. SSPxCON2 register. Interrupt is generated once
the Stop/Restart condition is complete.
24.6.6.1 BF Status Flag
In Transmit mode, the BF bit of the SSPxSTAT register
is set when the CPU writes to SSPxBUF and is cleared
when all eight bits are shifted out.
24.6.6.2 WCOL Status Flag

If the user writes the SSPxBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write does not occur).
WCOL must be cleared by software before the next
transmission.

FIGURE 24-28:
Write SSPxCON2<0> SEN = 1 ACKSTAT in

Start condition begins SSPxCON2 = 1
From slave, clear ACKSTAT bit SSPxCON2<6>
SEN = 0
R/W = 0 Transmitting Data or Second Half
Transmit Address to Slave of 10-bit Address ACK

SDA A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0
SSPxBUF written with 7-bit address and R/W

start transmit
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SCL held low
while CPU
responds to SSPxIF
SSPxIF
Cleared by software service routine
Cleared by software from SSP interrupt
Cleared by software
BF (SSPxSTAT<0>)
SSPxBUF written SSPxBUF is written by software

SEN
After Start condition, SEN cleared by hardware
PEN
R/W
I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
PIC16(L)F1615/9
DS40001770D-page 297
PIC16(L)F1615/9
24.6.7 I2C MASTER MODE RECEPTION 24.6.7.4 Typical Receive Sequence:
Master mode reception (Figure 24-29) is enabled by 1. The user generates a Start condition by setting
programming the Receive Enable bit, RCEN bit of the the SEN bit of the SSPxCON2 register.
SSPxCON2 register. 2. SSPxIF is set by hardware on completion of the
Note: The MSSP module must be in an Idle Start.
state before the RCEN bit is set or the 3. SSPxIF is cleared by software.
RCEN bit will be disregarded. 4. User writes SSPxBUF with the slave address to
transmit and the R/W bit set.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes (high-to-low/ 5. Address is shifted out the SDA pin until all eight
low-to-high) and data is shifted into the SSPSR. After bits are transmitted. Transmission begins as
the falling edge of the eighth clock, the receive enable soon as SSPxBUF is written to.
flag is automatically cleared, the contents of the 6. The MSSP module shifts in the ACK bit from the
SSPSR are loaded into the SSPxBUF, the BF flag bit is slave device and writes its value into the
set, the SSPxIF flag bit is set and the Baud Rate Gen- ACKSTAT bit of the SSPxCON2 register.
erator is suspended from counting, holding SCL low. 7. The MSSP module generates an interrupt at the
The MSSP is now in Idle state awaiting the next com- end of the ninth clock cycle by setting the
mand. When the buffer is read by the CPU, the BF flag SSPxIF bit.
bit is automatically cleared. The user can then send an 8. User sets the RCEN bit of the SSPxCON2 regis-
Acknowledge bit at the end of reception by setting the ter and the master clocks in a byte from the slave.
Acknowledge Sequence Enable, ACKEN bit of the 9. After the eighth falling edge of SCL, SSPxIF and
SSPxCON2 register. BF are set.
24.6.7.1 BF Status Flag 10. Master clears SSPxIF and reads the received
byte from SSPxBUF, clears BF.
In receive operation, the BF bit is set when an address
11. Master sets ACK value sent to slave in ACKDT
or data byte is loaded into SSPxBUF from SSPSR. It is
bit of the SSPxCON2 register and initiates the
cleared when the SSPxBUF register is read.
ACK by setting the ACKEN bit.
24.6.7.2 SSPOV Status Flag 12. Master’s ACK is clocked out to the slave and
SSPxIF is set.
In receive operation, the SSPOV bit is set when eight
bits are received into the SSPSR and the BF flag bit is 13. User clears SSPxIF.
already set from a previous reception. 14. Steps 8-13 are repeated for each received byte
from the slave.
24.6.7.3 WCOL Status Flag 15. Master sends a not ACK or Stop to end
If the user writes the SSPxBUF when a receive is communication.
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write does not occur).

FIGURE 24-29:
Write to SSPxCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPxCON2<5>) = 0
Write to SSPxCON2<0>(SEN = 1),
begin Start condition ACK from Master Set ACKEN, start Acknowledge sequence
Master configured as a receiver SDA = ACKDT = 0 SDA = ACKDT = 1
SEN = 0 by programming SSPxCON2<3> (RCEN = 1)
PEN bit = 1
I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)

Write to SSPxBUF occurs here, RCEN cleared RCEN = 1, start RCEN cleared
ACK from Slave next receive automatically written here
start XMIT automatically
Transmit Address to Slave Receiving Data from Slave Receiving Data from Slave
SDA A7 A6 A5 A4 A3 A2 A1 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Bus master
ACK is not sent terminates
transfer
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL S P
Data shifted in on falling edge of CLK Set SSPxIF at end
of receive Set SSPxIF interrupt
Set SSPxIF interrupt at end of Acknow-
Set SSPxIF interrupt ledge sequence
at end of receive at end of Acknowledge
SSPxIF sequence
Set P bit
Cleared by software Cleared by software Cleared by software Cleared by software (SSPxSTAT<4>)
SDA = 0, SCL = 1 Cleared in
while CPU software and SSPxIF
responds to SSPxIF
BF
(SSPxSTAT<0>) Last bit is shifted into SSPSR and
contents are unloaded into SSPxBUF
SSPOV
PIC16(L)F1615/9
SSPOV is set because
SSPxBUF is still full
ACKEN
DS40001770D-page 299
RCEN
Master configured as a receiver RCEN cleared ACK from Master RCEN cleared
by programming SSPxCON2<3> (RCEN = 1) automatically SDA = ACKDT = 0 automatically
PIC16(L)F1615/9
24.6.8 ACKNOWLEDGE SEQUENCE 24.6.9 STOP CONDITION TIMING
TIMING A Stop bit is asserted on the SDA pin at the end of a
An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable
Acknowledge Sequence Enable bit, ACKEN bit of the bit, PEN bit of the SSPxCON2 register. At the end of a
SSPxCON2 register. When this bit is set, the SCL pin is receive/transmit, the SCL line is held low after the
pulled low and the contents of the Acknowledge data bit falling edge of the ninth clock. When the PEN bit is set,
are presented on the SDA pin. If the user wishes to the master will assert the SDA line low. When the SDA
generate an Acknowledge, then the ACKDT bit should line is sampled low, the Baud Rate Generator is
be cleared. If not, the user should set the ACKDT bit reloaded and counts down to ‘0’. When the Baud Rate
before starting an Acknowledge sequence. The Baud Generator times out, the SCL pin will be brought high
Rate Generator then counts for one rollover period and one TBRG (Baud Rate Generator rollover count)
(TBRG) and the SCL pin is deasserted (pulled high). later, the SDA pin will be deasserted. When the SDA
When the SCL pin is sampled high (clock arbitration), pin is sampled high while SCL is high, the P bit of the
the Baud Rate Generator counts for TBRG. The SCL pin SSPxSTAT register is set. A TBRG later, the PEN bit is
is then pulled low. Following this, the ACKEN bit is auto- cleared and the SSPxIF bit is set (Figure 24-31).
matically cleared, the Baud Rate Generator is turned off
and the MSSP module then goes into Idle mode 24.6.9.1 WCOL Status Flag
(Figure 24-30). If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
24.6.8.1 WCOL Status Flag contents of the buffer are unchanged (the write does
If the user writes the SSPxBUF when an Acknowledge not occur).
sequence is in progress, then WCOL bit is set and the
contents of the buffer are unchanged (the write does
not occur).
FIGURE 24-30: ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here, ACKEN automatically cleared
write to SSPxCON2
ACKEN = 1, ACKDT = 0
TBRG TBRG
SDA D0 ACK
SCL 8 9
SSPxIF
Cleared in
SSPxIF set at software
the end of receive Cleared in
software SSPxIF set at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
FIGURE 24-31: STOP CONDITION RECEIVE OR TRANSMIT MODE

Write to SSPxCON2, SCL = 1 for TBRG, followed by SDA = 1 for TBRG
set PEN after SDA sampled high. P bit (SSPxSTAT<4>) is set.
Falling edge of PEN bit (SSPxCON2<2>) is cleared by

9th clock hardware and the SSPxIF bit is set
TBRG
SCL
SDA ACK
P
TBRG TBRG TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition
Note: TBRG = one Baud Rate Generator period.

PIC16(L)F1615/9
24.6.10 SLEEP OPERATION 24.6.13 MULTI -MASTER COMMUNICATION,
While in Sleep mode, the I2C slavemodule can receive BUS COLLISION AND BUS
addresses or data and when an address match or ARBITRATION
complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus arbitra-
from Sleep (if the MSSP interrupt is enabled). tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
24.6.11 EFFECTS OF A RESET outputs a ‘1’ on SDA, by letting SDA float high and
A Reset disables the MSSP module and terminates the another master asserts a ‘0’. When the SCL pin floats
current transfer. high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’,
24.6.12 MULTI-MASTER MODE then a bus collision has taken place. The master will set
In Multi-Master mode, the interrupt generation on the the Bus Collision Interrupt Flag, BCL1IF and reset the
detection of the Start and Stop conditions allows the I2C port to its Idle state (Figure 24-32).
determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision
Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is
MSSP module is disabled. Control of the I 2C bus may cleared, the SDA and SCL lines are deasserted and the
be taken when the P bit of the SSPxSTAT register is SSPxBUF can be written to. When the user services
set, or the bus is Idle, with both the S and P bits clear. the bus collision Interrupt Service Routine and if the I2C
When the bus is busy, enabling the SSP interrupt will bus is free, the user can resume communication by
generate the interrupt when the Stop condition occurs. asserting a Start condition.
In multi-master operation, the SDA line must be If a Start, Repeated Start, Stop or Acknowledge condi-
monitored for arbitration to see if the signal level is the tion was in progress when the bus collision occurred, the
expected output level. This check is performed by condition is aborted, the SDA and SCL lines are deas-
hardware with the result placed in the BCL1IF bit. serted and the respective control bits in the SSPxCON2
The states where arbitration can be lost are: register are cleared. When the user services the bus
collision Interrupt Service Routine and if the I2C bus is
• Address Transfer free, the user can resume communication by asserting a
• Data Transfer Start condition.
• A Start Condition The master will continue to monitor the SDA and SCL
• A Repeated Start Condition pins. If a Stop condition occurs, the SSPxIF bit will be set.
• An Acknowledge Condition A write to the SSPxBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the deter-
mination of when the bus is free. Control of the I2C bus
can be taken when the P bit is set in the SSPxSTAT
register, or the bus is Idle and the S and P bits are
cleared.
FIGURE 24-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

Sample SDA. While SCL is high,
Data changes SDA line pulled low data does not match what is driven
while SCL = 0 by another source by the master.
Bus collision has occurred.
SDA released
by master
SDA
SCL Set bus collision

interrupt (BCL1IF)
BCL1IF

PIC16(L)F1615/9
24.6.13.1 Bus Collision During a Start If the SDA pin is sampled low during this count, the
Condition BRG is reset and the SDA line is asserted early
(Figure 24-35). If, however, a ‘1’ is sampled on the SDA
During a Start condition, a bus collision occurs if:
pin, the SDA pin is asserted low at the end of the BRG
a) SDA or SCL are sampled low at the beginning of count. The Baud Rate Generator is then reloaded and
the Start condition (Figure 24-33). counts down to zero; if the SCL pin is sampled as ‘0’
b) SCL is sampled low before SDA is asserted low during this time, a bus collision does not occur. At the
(Figure 24-34). end of the BRG count, the SCL pin is asserted low.
During a Start condition, both the SDA and the SCL Note: The reason that bus collision is not a
pins are monitored. factor during a Start condition is that no
If the SDA pin is already low, or the SCL pin is already two bus masters can assert a Start condi-
low, then all of the following occur: tion at the exact same time. Therefore,
one master will always assert SDA before
• the Start condition is aborted,
the other. This condition does not cause a
• the BCL1IF flag is set and bus collision because the two masters
• the MSSP module is reset to its Idle state must be allowed to arbitrate the first
(Figure 24-33). address following the Start condition. If the
The Start condition begins with the SDA and SCL pins address is the same, arbitration must be
deasserted. When the SDA pin is sampled high, the allowed to continue into the data portion,
Baud Rate Generator is loaded and counts down. If the Repeated Start or Stop conditions.
SCL pin is sampled low while SDA is high, a bus
collision occurs because it is assumed that another
master is attempting to drive a data ‘1’ during the Start
condition.
FIGURE 24-33: BUS COLLISION DURING START CONDITION (SDA ONLY)

SDA goes low before the SEN bit is set.
Set BCL1IF,
S bit and SSPxIF set because
SDA = 0, SCL = 1.
SDA
SCL
Set SEN, enable Start SEN cleared automatically because of bus collision.
condition if SDA = 1, SCL = 1 SSP module reset into Idle state.
SEN
SDA sampled low before
Start condition. Set BCL1IF.
S bit and SSPxIF set because
BCL1IF SDA = 0, SCL = 1.
SSPxIF and BCL1IF are
cleared by software
SSPxIF
SSPxIF and BCL1IF are

cleared by software

PIC16(L)F1615/9
FIGURE 24-34: BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG TBRG
SDA
SCL Set SEN, enable Start

sequence if SDA = 1, SCL = 1
SCL = 0 before SDA = 0,
bus collision occurs. Set BCL1IF.
SEN
SCL = 0 before BRG time-out,
bus collision occurs. Set BCL1IF.
BCL1IF
Interrupt cleared
by software
S ’0’ ’0’
SSPxIF ’0’ ’0’
FIGURE 24-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S Set SSPxIF
Less than TBRG
TBRG
SDA SDA pulled low by other master.

Reset BRG and assert SDA.
SCL S
SCL pulled low after BRG
time-out
SEN
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
BCL1IF ’0’
SSPxIF
SDA = 0, SCL = 1, Interrupts cleared
set SSPxIF by software

PIC16(L)F1615/9
24.6.13.2 Bus Collision During a Repeated If SDA is low, a bus collision has occurred (i.e., another
Start Condition master is attempting to transmit a data ‘0’, Figure 24-36).
If SDA is sampled high, the BRG is reloaded and begins
During a Repeated Start condition, a bus collision
counting. If SDA goes from high-to-low before the BRG
occurs if:
times out, no bus collision occurs because no two
a) A low level is sampled on SDA when SCL goes masters can assert SDA at exactly the same time.
from low level to high level (Case 1).
If SCL goes from high-to-low before the BRG times out
b) SCL goes low before SDA is asserted low, and SDA has not already been asserted, a bus collision
indicating that another master is attempting to occurs. In this case, another master is attempting to
transmit a data ‘1’ (Case 2). transmit a data ‘1’ during the Repeated Start condition,
When the user releases SDA and the pin is allowed to see Figure 24-37.
float high, the BRG is loaded with SSPxADD and If, at the end of the BRG time-out, both SCL and SDA
counts down to zero. The SCL pin is then deasserted are still high, the SDA pin is driven low and the BRG is
and when sampled high, the SDA pin is sampled. reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
FIGURE 24-36: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.

If SDA = 0, set BCL1IF and release SDA and SCL.
RSEN
BCL IF
Cleared by software
S ’0’
SSPxIF ’0’
FIGURE 24-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG TBRG
SDA
SCL
SCL goes low before SDA,

BCL1IF set BCL1IF. Release SDA and SCL.
Interrupt cleared
by software
RSEN
S ’0’
SSPxIF

PIC16(L)F1615/9
24.6.13.3 Bus Collision During a Stop The Stop condition begins with SDA asserted low.
Condition When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
Bus collision occurs during a Stop condition if:
the Baud Rate Generator is loaded with SSPxADD and
a) After the SDA pin has been deasserted and counts down to zero. After the BRG times out, SDA is
allowed to float high, SDA is sampled low after sampled. If SDA is sampled low, a bus collision has
the BRG has timed out (Case 1). occurred. This is due to another master attempting to
b) After the SCL pin is deasserted, SCL is sampled drive a data ‘0’ (Figure 24-38). If the SCL pin is sampled
low before SDA goes high (Case 2). low before SDA is allowed to float high, a bus collision
occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 24-39).
FIGURE 24-38: BUS COLLISION DURING A STOP CONDITION (CASE 1)
TBRG TBRG TBRG SDA sampled

low after TBRG,
set BCL1IF
SDA
SDA asserted low

SCL
PEN
BCL1IF
P ’0’
SSPxIF ’0’
FIGURE 24-39: BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG TBRG TBRG
SDA
Assert SDA SCL goes low before SDA goes high,

set BCL1IF
SCL
PEN
BCL1IF
P ’0’
SSPxIF ’0’

PIC16(L)F1615/9
TABLE 24-3: SUMMARY OF REGISTERS ASSOCIATED WITH I2C OPERATION
Reset
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on
Page:

ANSELB(1) — — ANSB5 ANSB4 — — — — 159
SSPCLKPPS — — — SSPCLKPPS<4:0> 174, 172
SSPDATPPS — — — SSPDATPPS<4:0> 174, 172
SSPSSPPS — — — SSPSSPPS<4:0> 174, 172
SSP1ADD ADD<7:0> 312
SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register 264*
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 309
SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 310
SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 311
SSP1MSK MSK<7:0> 312
SSP1STAT SMP CKE D/A P S R/W UA BF 308
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module in I2C mode.

PIC16(L)F1615/9
24.7 BAUD RATE GENERATOR module clock line. The logic dictating when the reload
signal is asserted depends on the mode the MSSP is
The MSSP module has a Baud Rate Generator avail- being operated in.
able for clock generation in both I2C and SPI Master
Table 24-4 demonstrates clock rates based on
modes. The Baud Rate Generator (BRG) reload value
instruction cycles and the BRG value loaded into
is placed in the SSPxADD register (Register 24-6).
SSPxADD.
When a write occurs to SSPxBUF, the Baud Rate
Generator will automatically begin counting down.
EQUATION 24-1:
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will FOSC
remain in its last state. FCLOCK = -------------------------------------------------
 SSPxADD + 1   4 
An internal signal “Reload” in Figure 24-40 triggers the
value from SSPxADD to be loaded into the BRG
counter. This occurs twice for each oscillation of the
FIGURE 24-40: BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM<3:0> SSPxADD<7:0>
SSPM<3:0> Reload Reload

SCL Control
SSPCLK BRG Down Counter FOSC/2
Note: Values of 0x00, 0x01 and 0x02 are not valid

for SSPxADD when used as a Baud Rate
Generator for I2C. This is an implementation
limitation.
TABLE 24-4: MSSP CLOCK RATE W/BRG

FCLOCK
FOSC FCY BRG Value
(2 Rollovers of BRG)
32 MHz 8 MHz 13h 400 kHz
32 MHz 8 MHz 4Fh 100 kHz
16 MHz 4 MHz 0Ch 308 kHz
Note: Refer to the I/O port electrical specifications in Figure 35-7 and Table 35-10 to ensure the system is
designed to support the I/O timing requirements.

PIC16(L)F1615/9
24.8 Register Definitions: MSSP Control
REGISTER 24-1: SSP1STAT: SSP STATUS REGISTER
R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0
SMP CKE D/A P S R/W UA BF
bit 7 bit 0
Legend:
bit 7 SMP: SPI Data Input Sample bit

SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
In I2 C Master or Slave mode:
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High-Speed mode (400 kHz)
bit 6 CKE: SPI Clock Edge Select bit (SPI mode only)
In SPI Master or Slave mode:
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
In I2 C™ mode only:
1 = Enable input logic so that thresholds are compliant with SMBus specification
0 = Disable SMBus specific inputs
bit 5 D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: Stop bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0 = Stop bit was not detected last
bit 3 S: Start bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0 = Start bit was not detected last
bit 2 R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the
next Start bit, Stop bit, or not ACK bit.
In I2 C Slave mode:
1 = Read
0 = Write
In I2 C Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode.
bit 1 UA: Update Address bit (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSP1ADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
Receive (SPI and I2 C modes):
1 = Receive complete, SSP1BUF is full
0 = Receive not complete, SSP1BUF is empty
Transmit (I2 C mode only):
1 = Data transmit in progress (does not include the ACK and Stop bits), SSP1BUF is full
0 = Data transmit complete (does not include the ACK and Stop bits), SSP1BUF is empty

PIC16(L)F1615/9
REGISTER 24-2: SSP1CON1: SSP CONTROL REGISTER 1

R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
WCOL SSPOV(1) SSPEN CKP SSPM<3:0>
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared
bit 7 WCOL: Write Collision Detect bit

Master mode:
1 = A write to the SSP1BUF register was attempted while the I2C conditions were not valid for a transmission to be started
0 = No collision
Slave mode:
1 = The SSP1BUF register is written while it is still transmitting the previous word (must be cleared in software)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit(1)
In SPI mode:
1 = A new byte is received while the SSP1BUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost.
Overflow can only occur in Slave mode. In Slave mode, the user must read the SSP1BUF, even if only transmitting data, to avoid
setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the
SSP1BUF register (must be cleared in software).
0 = No overflow
2 C mode:
In I
1 = A byte is received while the SSP1BUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode
(must be cleared in software).
0 = No overflow
bit 5 SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output
In SPI mode:
1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2)
0 = Disables serial port and configures these pins as I/O port pins
In I2C mode:
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3)
0 = Disables serial port and configures these pins as I/O port pins
bit 4 CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I2C Slave mode:
SCL release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I2C Master mode:
Unused in this mode
bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1101 = Reserved
1100 = Reserved
1011 = I2C firmware controlled Master mode (slave idle)
1010 = SPI Master mode, clock = FOSC/(4 * (SSP1ADD+1))(5)
1001 = Reserved
1000 = I2C Master mode, clock = FOSC / (4 * (SSP1ADD+1))(4)
0111 = I2C Slave mode, 10-bit address
0110 = I2C Slave mode, 7-bit address
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0011 = SPI Master mode, clock = T2_match/2
0010 = SPI Master mode, clock = FOSC/64
Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSP1BUF register.
2: When enabled, these pins must be properly configured as input or output. Use SSPSSPPS, SSPCLKPPS, SSPDATPPS, and RxyPPS
to select the pins.
3: When enabled, the SDA and SCL pins must be configured as inputs. Use SSPCLKPPS, SSPDATPPS, and RxyPPS to select the pins.
4: SSP1ADD values of 0, 1 or 2 are not supported for I2C mode.
5: SSP1ADD value of ‘0’ is not supported. Use SSPM = 0000 instead.

PIC16(L)F1615/9
REGISTER 24-3: SSP1CON2: SSP CONTROL REGISTER 2(1)

R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set
bit 7 GCEN: General Call Enable bit (in I2C Slave mode only)
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only)
1 = Acknowledge was not received
0 = Acknowledge was received
bit 5 ACKDT: Acknowledge Data bit (in I2C mode only)
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1 = Not Acknowledge
0 = Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
bit 3 RCEN: Receive Enable bit (in I2C Master mode only)
1 = Enables Receive mode for I2C
0 = Receive idle
bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only)
SCKMSSP Release Control:
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1 RSEN: Repeated Start Condition Enable bit (in I2C Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0 SEN: Start Condition Enable/Stretch Enable bit
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSP1BUF may not be written (or writes to the SSP1BUF are disabled).

PIC16(L)F1615/9
REGISTER 24-4: SSP1CON3: SSP CONTROL REGISTER 3

R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
ACKTIM(3) PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN
bit 7 bit 0
Legend:
bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3)

1 = Indicates the I2C bus is in an Acknowledge sequence, set on eighth falling edge of SCL clock
0 = Not an Acknowledge sequence, cleared on 9th rising edge of SCL clock
bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C Slave mode only)
1 = Enable interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled(2)
bit 5 SCIE: Start Condition Interrupt Enable bit (I2C Slave mode only)
1 = Enable interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled(2)
bit 4 BOEN: Buffer Overwrite Enable bit
In SPI Slave mode:(1)
1 = SSP1BUF updates every time that a new data byte is shifted in ignoring the BF bit
0 = If new byte is received with BF bit of the SSP1STAT register already set, SSPOV bit of the
SSP1CON1 register is set, and the buffer is not updated
In I2C Master mode and SPI Master mode:
In I2C Slave mode:
1 = SSP1BUF is updated and ACK is generated for a received address/data byte, ignoring the
state of the SSPOV bit only if the BF bit = 0.
0 = SSP1BUF is only updated when SSPOV is clear
bit 3 SDAHT: SDA Hold Time Selection bit (I2C mode only)
1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL
0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL
bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If, on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the
BCL1IF bit of the PIR2 register is set, and bus goes idle
1 = Enable slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only)
1 = Following the eighth falling edge of SCL for a matching received address byte; CKP bit of the
SSP1CON1 register will be cleared and the SCL will be held low.
0 = Address holding is disabled
bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only)
1 = Following the eighth falling edge of SCL for a received data byte; slave hardware clears the CKP
bit of the SSP1CON1 register and SCL is held low.
0 = Data holding is disabled
Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to
SSP1BUF.
2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.

PIC16(L)F1615/9
REGISTER 24-5: SSP1MSK: SSP MASK REGISTER

MSK<7:0>
bit 7 bit 0
Legend:
bit 7-1 MSK<7:1>: Mask bits

1 = The received address bit n is compared to SSP1ADD<n> to detect I2C address match
0 = The received address bit n is not used to detect I2C address match
bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address
I2C Slave mode, 10-bit address (SSPM<3:0> = 0111 or 1111):
1 = The received address bit 0 is compared to SSP1ADD<0> to detect I2C address match
0 = The received address bit 0 is not used to detect I2C address match
I2C Slave mode, 7-bit address, the bit is ignored
REGISTER 24-6: SSP1ADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE)
ADD<7:0>
bit 7 bit 0
Legend:
Master mode:
bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits

SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC
10-Bit Slave mode – Most Significant Address Byte:
bit 7-3 Not used: Unused for Most Significant Address Byte. Bit state of this register is a “don’t care”. Bit
pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits
are compared by hardware and are not affected by the value in this register.
bit 2-1 ADD<2:1>: Two Most Significant bits of 10-bit address
bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.
10-Bit Slave mode – Least Significant Address Byte:
bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address

7-Bit Slave mode:
bit 7-1 ADD<7:1>: 7-bit address

bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.

PIC16(L)F1615/9
25.0 ENHANCED UNIVERSAL • Two-character input buffer
SYNCHRONOUS • One-character output buffer
ASYNCHRONOUS RECEIVER • Programmable 8-bit or 9-bit character length
• Address detection in 9-bit mode
TRANSMITTER (EUSART)
• Input buffer overrun error detection
The Enhanced Universal Synchronous Asynchronous • Received character framing error detection
Receiver Transmitter (EUSART) module is a serial I/O
• Half-duplex synchronous master
communications peripheral. It contains all the clock
generators, shift registers and data buffers necessary • Half-duplex synchronous slave
to perform an input or output serial data transfer • Programmable clock polarity in synchronous
independent of device program execution. The modes
EUSART, also known as a Serial Communications • Sleep operation
Interface (SCI), can be configured as a full-duplex The EUSART module implements the following
asynchronous system or half-duplex synchronous additional features, making it ideally suited for use in
system. Full-Duplex mode is useful for Local Interconnect Network (LIN) bus systems:
communications with peripheral systems, such as CRT
terminals and personal computers. Half-Duplex • Automatic detection and calibration of the baud rate
Synchronous mode is intended for communications • Wake-up on Break reception
with peripheral devices, such as A/D or D/A integrated • 13-bit Break character transmit
circuits, serial EEPROMs or other microcontrollers.
Block diagrams of the EUSART transmitter and
These devices typically do not have internal clocks for
receiver are shown in Figure 25-1 and Figure 25-2.
baud rate generation and require the external clock
signal provided by a master synchronous device. The EUSART transmit output (TX_out) is available to
the TX/CK pin and internally to the following peripherals:
The EUSART module includes the following capabilities:
• Configurable Logic Cell (CLC)
• Full-duplex asynchronous transmit and receive
FIGURE 25-1: EUSART TRANSMIT BLOCK DIAGRAM

Data Bus
TXIE
SYNC
Interrupt
CSRC
TXxREG Register TXIF
8 RxyPPS(1)
CK pin TXEN
MSb LSb RX/DT pin
PPS 1 (8) 0 Pin Buffer
• • • and Control PPS
0 Transmit Shift Register (TSR)
CKPPS SYNC
TRMT TX_out
Baud Rate Generator FOSC
÷n
TX9
BRG16 n
+1 Multiplier x4 x16 x64
TX9D TX/CK pin
SYNC 1 X 0 0 0 0
SPxBRGH SPxBRGL PPS
BRGH X 1 1 0 0
1
BRG16 X 1 0 1 0
RxyPPS
SYNC
Note 1: In Synchronous mode the DT output and RX input PPS CSRC
selections should enable the same pin.

PIC16(L)F1615/9
FIGURE 25-2: EUSART RECEIVE BLOCK DIAGRAM
SPEN CREN OERR RCIDL
RXPPS(1)
RX/DT pin MSb RSR Register LSb
Pin Buffer Data
PPS and Control Recovery
Stop (8) 7 ••• 1 0 Start
Baud Rate Generator FOSC RX9

÷n
BRG16
+1 n
Multiplier x4 x16 x64
SYNC 1 X 0 0 0
SPxBRGH SPxBRGL BRGH FIFO
X 1 1 0 0 FERR RX9D RCxREG Register
BRG16 X 1 0 1 0
8
Data Bus
Note 1: In Synchronous mode the DT output and RX input PPS RCIF Interrupt
selections should enable the same pin. RCIE
The operation of the EUSART module is controlled

through three registers:
• Transmit Status and Control (TXxSTA)
• Receive Status and Control (RCxSTA)
• Baud Rate Control (BAUDxCON)
These registers are detailed in Register 25-1,
Register 25-2 and Register 25-3, respectively.
The RX and CK input pins are selected with the RXPPS
and CKPPS registers, respectively. TX, CK, and DT
output pins are selected with each pin’s RxyPPS register.
Since the RX input is coupled with the DT output in
Synchronous mode, it is the user’s responsibility to select
the same pin for both of these functions when operating
in Synchronous mode. The EUSART control logic will
control the data direction drivers automatically.

PIC16(L)F1615/9
25.1 EUSART Asynchronous Mode 25.1.1.2 Transmitting Data
The EUSART transmits and receives data using the A transmission is initiated by writing a character to the
standard non-return-to-zero (NRZ) format. NRZ is TXxREG register. If this is the first character, or the
implemented with two levels: a VOH Mark state which previous character has been completely flushed from
represents a ‘1’ data bit, and a VOL Space state which the TSR, the data in the TXxREG is immediately
represents a ‘0’ data bit. NRZ refers to the fact that transferred to the TSR register. If the TSR still contains
consecutively transmitted data bits of the same value all or part of a previous character, the new character
stay at the output level of that bit without returning to a data is held in the TXxREG until the Stop bit of the
neutral level between each bit transmission. An NRZ previous character has been transmitted. The pending
transmission port idles in the Mark state. Each character character in the TXxREG is then transferred to the TSR
transmission consists of one Start bit followed by eight in one TCY immediately following the Stop bit
or nine data bits and is always terminated by one or transmission. The transmission of the Start bit, data bits
more Stop bits. The Start bit is always a space and the and Stop bit sequence commences immediately
Stop bits are always marks. The most common data following the transfer of the data to the TSR from the
format is eight bits. Each transmitted bit persists for a TXxREG.
period of 1/(Baud Rate). An on-chip dedicated 8-bit/16-
bit Baud Rate Generator is used to derive standard 25.1.1.3 Transmit Data Polarity
baud rate frequencies from the system oscillator. See The polarity of the transmit data can be controlled with
Table 25-5 for examples of baud rate configurations. the SCKP bit of the BAUDxCON register. The default
The EUSART transmits and receives the LSb first. The state of this bit is ‘0’ which selects high true transmit idle
EUSART’s transmitter and receiver are functionally and data bits. Setting the SCKP bit to ‘1’ will invert the
independent, but share the same data format and baud transmit data resulting in low true idle and data bits. The
rate. Parity is not supported by the hardware, but can SCKP bit controls transmit data polarity in
be implemented in software and stored as the ninth Asynchronous mode only. In Synchronous mode, the
data bit. SCKP bit has a different function. See Section
25.5.1.2 “Clock Polarity”.
25.1.1 EUSART ASYNCHRONOUS
TRANSMITTER 25.1.1.4 Transmit Interrupt Flag
The TXIF interrupt flag bit of the PIR1 register is set
The EUSART transmitter block diagram is shown in
whenever the EUSART transmitter is enabled and no
Figure 25-1. The heart of the transmitter is the serial
character is being held for transmission in the TXxREG.
Transmit Shift Register (TSR), which is not directly
In other words, the TXIF bit is only clear when the TSR
accessible by software. The TSR obtains its data from
is busy with a character and a new character has been
the transmit buffer, which is the TXxREG register.
queued for transmission in the TXxREG. The TXIF flag
25.1.1.1 Enabling the Transmitter bit is not cleared immediately upon writing TXxREG.
TXIF becomes valid in the second instruction cycle
The EUSART transmitter is enabled for asynchronous following the write execution. Polling TXIF immediately
operations by configuring the following three control following the TXxREG write will return invalid results.
bits: The TXIF bit is read-only, it cannot be set or cleared by
• TXEN = 1 software.
• SYNC = 0 The TXIF interrupt can be enabled by setting the TXIE
• SPEN = 1 interrupt enable bit of the PIE1 register. However, the
TXIF flag bit will be set whenever the TXxREG is
All other EUSART control bits are assumed to be in
empty, regardless of the state of TXIE enable bit.
their default state.
To use interrupts when transmitting data, set the TXIE
Setting the TXEN bit of the TXxSTA register enables the
bit only when there is more data to send. Clear the
transmitter circuitry of the EUSART. Clearing the SYNC
TXIE interrupt enable bit upon writing the last character
bit of the TXxSTA register configures the EUSART for
of the transmission to the TXxREG.
asynchronous operation. Setting the SPEN bit of the
RCxSTA register enables the EUSART and
automatically configures the TX/CK I/O pin as an output.
If the TX/CK pin is shared with an analog peripheral, the
analog I/O function must be disabled by clearing the
corresponding ANSEL bit.
Note: The TXIF Transmitter Interrupt flag is set
when the TXEN enable bit is set.

PIC16(L)F1615/9
25.1.1.5 TSR Status 25.1.1.7 Asynchronous Transmission Set-up:
The TRMT bit of the TXxSTA register indicates the 1. Initialize the SPxBRGH, SPxBRGL register pair
status of the TSR register. This is a read-only bit. The and the BRGH and BRG16 bits to achieve the
TRMT bit is set when the TSR register is empty and is desired baud rate (see Section 25.4 “EUSART
cleared when a character is transferred to the TSR Baud Rate Generator (BRG)”).
register from the TXxREG. The TRMT bit remains clear 2. Enable the asynchronous serial port by clearing
until all bits have been shifted out of the TSR register. the SYNC bit and setting the SPEN bit.
No interrupt logic is tied to this bit, so the user has to 3. If 9-bit transmission is desired, set the TX9
poll this bit to determine the TSR status. control bit. A set ninth data bit will indicate that
Note: The TSR register is not mapped in data the eight Least Significant data bits are an
memory, so it is not available to the user. address when the receiver is set for address
detection.
25.1.1.6 Transmitting 9-Bit Characters 4. Set SCKP bit if inverted transmit is desired.
The EUSART supports 9-bit character transmissions. 5. Enable the transmission by setting the TXEN
When the TX9 bit of the TXxSTA register is set, the control bit. This will cause the TXIF interrupt bit
EUSART will shift nine bits out for each character trans- to be set.
mitted. The TX9D bit of the TXxSTA register is the 6. If interrupts are desired, set the TXIE interrupt
ninth, and Most Significant data bit. When transmitting enable bit of the PIE1 register. An interrupt will
9-bit data, the TX9D data bit must be written before occur immediately provided that the GIE and
writing the eight Least Significant bits into the TXxREG. PEIE bits of the INTCON register are also set.
All nine bits of data will be transferred to the TSR shift 7. If 9-bit transmission is selected, the ninth bit
register immediately after the TXxREG is written. should be loaded into the TX9D data bit.
A special 9-bit Address mode is available for use with 8. Load 8-bit data into the TXxREG register. This
multiple receivers. See Section 25.1.2.7 “Address will start the transmission.
Detection” for more information on the Address mode.
FIGURE 25-3: ASYNCHRONOUS TRANSMISSION
Write to TXxREG
Word 1
BRG Output
(Shift Clock)
TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit
Word 1
TXIF bit
(Transmit Buffer 1 TCY
Reg. Empty Flag)
TRMT bit Word 1

Transmit Shift Reg.
(Transmit Shift
Reg. Empty Flag)
FIGURE 25-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXxREG
Word 1 Word 2
BRG Output
(Shift Clock)
TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0
TXIF bit 1 TCY Word 1 Word 2
(Transmit Buffer
Reg. Empty Flag) 1 TCY
TRMT bit Word 1 Word 2

(Transmit Shift Transmit Shift Reg. Transmit Shift Reg.
Reg. Empty Flag)
Note: This timing diagram shows two consecutive transmissions.

PIC16(L)F1615/9
TABLE 25-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Register on
Page

ANSELB(1) — — ANSB5 ANSB4 — — — — 159
BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 325
RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 324
SP1BRGL BRG<7:0> 326*
SP1BRGH BRG<15:8> 326*
(1)
TX1REG EUSART Transmit Data Register 315*
TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 323
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous transmission.

PIC16(L)F1615/9
25.1.2 EUSART ASYNCHRONOUS 25.1.2.2 Receiving Data
RECEIVER The receiver data recovery circuit initiates character
The Asynchronous mode is typically used in RS-232 reception on the falling edge of the first bit. The first bit,
systems. The receiver block diagram is shown in also known as the Start bit, is always a zero. The data
Figure 25-2. The data is received on the RX/DT pin and recovery circuit counts one-half bit time to the center of
drives the data recovery block. The data recovery block the Start bit and verifies that the bit is still a zero. If it is
is actually a high-speed shifter operating at 16 times not a zero then the data recovery circuit aborts
the baud rate, whereas the serial Receive Shift character reception, without generating an error, and
Register (RSR) operates at the bit rate. When all eight resumes looking for the falling edge of the Start bit. If
or nine bits of the character have been shifted in, they the Start bit zero verification succeeds then the data
are immediately transferred to a two character First-In- recovery circuit counts a full bit time to the center of the
First-Out (FIFO) memory. The FIFO buffering allows next bit. The bit is then sampled by a majority detect
reception of two complete characters and the start of a circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.
third character before software must start servicing the This repeats until all data bits have been sampled and
EUSART receiver. The FIFO and RSR registers are not shifted into the RSR. One final bit time is measured and
directly accessible by software. Access to the received the level sampled. This is the Stop bit, which is always
data is via the RCxREG register. a ‘1’. If the data recovery circuit samples a ‘0’ in the
Stop bit position then a framing error is set for this
25.1.2.1 Enabling the Receiver character, otherwise the framing error is cleared for this
The EUSART receiver is enabled for asynchronous character. See Section 25.1.2.4 “Receive Framing
operation by configuring the following three control bits: Error” for more information on framing errors.
• CREN = 1 Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
• SYNC = 0
to the EUSART receive FIFO and the RCIF interrupt
• SPEN = 1 flag bit of the PIR1 register is set. The top character in
All other EUSART control bits are assumed to be in the FIFO is transferred out of the FIFO by reading the
their default state. RCxREG register.
Setting the CREN bit of the RCxSTA register enables Note: If the receive FIFO is overrun, no additional
the receiver circuitry of the EUSART. Clearing the SYNC characters will be received until the overrun
bit of the TXxSTA register configures the EUSART for condition is cleared. See Section
asynchronous operation. Setting the SPEN bit of the 25.1.2.5 “Receive Overrun Error” for
RCxSTA register enables the EUSART. The more information on overrun errors.
programmer must set the corresponding TRIS bit to
configure the RX/DT I/O pin as an input. 25.1.2.3 Receive Interrupts
Note: If the RX/DT function is on an analog pin, The RCIF interrupt flag bit of the PIR1 register is set
the corresponding ANSEL bit must be whenever the EUSART receiver is enabled and there is
cleared for the receiver to function. an unread character in the receive FIFO. The RCIF
interrupt flag bit is read-only, it cannot be set or cleared
by software.
RCIF interrupts are enabled by setting all of the
following bits:
• RCIE, Interrupt Enable bit of the PIE1 register
• PEIE, Peripheral Interrupt Enable bit of the
INTCON register
• GIE, Global Interrupt Enable bit of the INTCON
register
The RCIF interrupt flag bit will be set when there is an
unread character in the FIFO, regardless of the state of
interrupt enable bits.

PIC16(L)F1615/9
25.1.2.4 Receive Framing Error 25.1.2.7 Address Detection
Each character in the receive FIFO buffer has a A special Address Detection mode is available for use
corresponding framing error Status bit. A framing error when multiple receivers share the same transmission
indicates that a Stop bit was not seen at the expected line, such as in RS-485 systems. Address detection is
time. The framing error status is accessed via the enabled by setting the ADDEN bit of the RCxSTA
FERR bit of the RCxSTA register. The FERR bit register.
represents the status of the top unread character in the Address detection requires 9-bit character reception.
receive FIFO. Therefore, the FERR bit must be read When address detection is enabled, only characters
before reading the RCxREG. with the ninth data bit set will be transferred to the
The FERR bit is read-only and only applies to the top receive FIFO buffer, thereby setting the RCIF interrupt
unread character in the receive FIFO. A framing error bit. All other characters will be ignored.
(FERR = 1) does not preclude reception of additional Upon receiving an address character, user software
characters. It is not necessary to clear the FERR bit. determines if the address matches its own. Upon
Reading the next character from the FIFO buffer will address match, user software must disable address
advance the FIFO to the next character and the next detection by clearing the ADDEN bit before the next
corresponding framing error. Stop bit occurs. When user software detects the end of
The FERR bit can be forced clear by clearing the SPEN the message, determined by the message protocol
bit of the RCxSTA register which resets the EUSART. used, software places the receiver back into the
Clearing the CREN bit of the RCxSTA register does not Address Detection mode by setting the ADDEN bit.
affect the FERR bit. A framing error by itself does not
generate an interrupt.
Note: If all receive characters in the receive
FIFO have framing errors, repeated reads
of the RCxREG will not clear the FERR bit.
25.1.2.5 Receive Overrun Error

The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before the FIFO is accessed. When
this happens the OERR bit of the RCxSTA register is
set. The characters already in the FIFO buffer can be
read but no additional characters will be received until
the error is cleared. The error must be cleared by either
clearing the CREN bit of the RCxSTA register or by
resetting the EUSART by clearing the SPEN bit of the
RCxSTA register.
25.1.2.6 Receiving 9-Bit Characters

The EUSART supports 9-bit character reception. When
the RX9 bit of the RCxSTA register is set, the EUSART
will shift nine bits into the RSR for each character
received. The RX9D bit of the RCxSTA register is the
ninth and Most Significant data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the eight Least Significant bits
from the RCxREG.

PIC16(L)F1615/9
25.1.2.8 Asynchronous Reception Set-up 25.1.2.9 9-bit Address Detection Mode Set-up
1. Initialize the SPxBRGH, SPxBRGL register pair This mode would typically be used in RS-485 systems.
and the BRGH and BRG16 bits to achieve the To set up an Asynchronous Reception with Address
desired baud rate (see Section 25.4 “EUSART Detect Enable:
Baud Rate Generator (BRG)”). 1. Initialize the SPxBRGH, SPxBRGL register pair
2. Clear the ANSEL bit for the RX pin (if applicable). and the BRGH and BRG16 bits to achieve the
3. Enable the serial port by setting the SPEN bit. desired baud rate (see Section 25.4 “EUSART
The SYNC bit must be clear for asynchronous Baud Rate Generator (BRG)”).
operation. 2. Clear the ANSEL bit for the RX pin (if applicable).
4. If interrupts are desired, set the RCIE bit of the 3. Enable the serial port by setting the SPEN bit.
PIE1 register and the GIE and PEIE bits of the The SYNC bit must be clear for asynchronous
INTCON register. operation.
5. If 9-bit reception is desired, set the RX9 bit. 4. If interrupts are desired, set the RCIE bit of the
6. Enable reception by setting the CREN bit. PIE1 register and the GIE and PEIE bits of the
7. The RCIF interrupt flag bit will be set when a INTCON register.
character is transferred from the RSR to the 5. Enable 9-bit reception by setting the RX9 bit.
receive buffer. An interrupt will be generated if 6. Enable address detection by setting the ADDEN
the RCIE interrupt enable bit was also set. bit.
8. Read the RCxSTA register to get the error flags 7. Enable reception by setting the CREN bit.
and, if 9-bit data reception is enabled, the ninth 8. The RCIF interrupt flag bit will be set when a
data bit. character with the ninth bit set is transferred
9. Get the received eight Least Significant data bits from the RSR to the receive buffer. An interrupt
from the receive buffer by reading the RCxREG will be generated if the RCIE interrupt enable bit
register. was also set.
10. If an overrun occurred, clear the OERR flag by 9. Read the RCxSTA register to get the error flags.
clearing the CREN receiver enable bit. The ninth data bit will always be set.
10. Get the received eight Least Significant data bits
from the receive buffer by reading the RCxREG
register. Software determines if this is the
device’s address.
11. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
12. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
FIGURE 25-5: ASYNCHRONOUS RECEPTION

Start Start Start
RX/DT pin bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop
bit bit bit
Rcv Shift
Reg
Rcv Buffer Reg.
Word 1 Word 2
RCxREG RCxREG
RCIDL
Read Rcv
Buffer Reg.
RCxREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCxREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.

PIC16(L)F1615/9
TABLE 25-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Register
on Page

ANSELB(1) — — ANSB5 ANSB4 — — — — 159
RC1REG EUSART Receive Data Register 318*
SP1BRGL BRG<7:0> 326
SP1BRGH BRG<15:8> 326
(2)
TRISA — — TRISA5 TRISA4 — TRISA2 TRISA1 TRISA0 151
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous reception.

PIC16(L)F1615/9
25.2 Clock Accuracy with
Asynchronous Operation
The factory calibrates the internal oscillator block
output (INTOSC). However, the INTOSC frequency
may drift as VDD or temperature changes, and this
directly affects the asynchronous baud rate. Two
methods may be used to adjust the baud rate clock, but
both require a reference clock source of some kind.
The first (preferred) method uses the OSCTUNE
register to adjust the INTOSC output. Adjusting the
value in the OSCTUNE register allows for fine resolution
changes to the system clock source. See Section
5.2.2.3 “Internal Oscillator Frequency Adjustment”
for more information.
The other method adjusts the value in the Baud Rate
Generator. This can be done automatically with the
Auto-Baud Detect feature (see Section 25.4.1 “Auto-
Baud Detect”). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.

PIC16(L)F1615/9
25.3 Register Definitions: EUSART Control
REGISTER 25-1: TX1STA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-1/1 R/W-0/0
CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D
bit 7 bit 0
Legend:
bit 7 CSRC: Clock Source Select bit

Asynchronous mode:
Don’t care
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4 SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Don’t care
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.

PIC16(L)F1615/9
REGISTER 25-2: RC1STA: RECEIVE STATUS AND CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
Legend:
bit 7 SPEN: Serial Port Enable bit

1 = Serial port enabled
0 = Serial port disabled (held in Reset)
bit 6 RX9: 9-Bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave
Don’t care
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Don’t care
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCxREG register and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: Ninth bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.

PIC16(L)F1615/9
REGISTER 25-3: BAUD1CON: BAUD RATE CONTROL REGISTER

R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN
bit 7 bit 0
Legend:
bit 7 ABDOVF: Auto-Baud Detect Overflow bit

Asynchronous mode:
1 = Auto-baud timer overflowed
0 = Auto-baud timer did not overflow
Synchronous mode:
Don’t care
bit 6 RCIDL: Receive Idle Flag bit
Asynchronous mode:
1 = Receiver is Idle
0 = Start bit has been received and the receiver is receiving
Synchronous mode:
Don’t care
bit 4 SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
1 = Transmit inverted data to the TX/CK pin
0 = Transmit non-inverted data to the TX/CK pin
Synchronous mode:
1 = Data is clocked on rising edge of the clock
0 = Data is clocked on falling edge of the clock
bit 3 BRG16: 16-bit Baud Rate Generator bit
1 = 16-bit Baud Rate Generator is used
0 = 8-bit Baud Rate Generator is used
bit 1 WUE: Wake-up Enable bit
Asynchronous mode:
1 = Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE
will automatically clear after RCIF is set.
0 = Receiver is operating normally
Synchronous mode:
Don’t care
bit 0 ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete)
0 = Auto-Baud Detect mode is disabled
Synchronous mode:
Don’t care

PIC16(L)F1615/9
25.4 EUSART Baud Rate Generator EXAMPLE 25-1: CALCULATING BAUD
(BRG) RATE ERROR
The Baud Rate Generator (BRG) is an 8-bit or 16-bit For a device with FOSC of 16 MHz, desired baud rate
timer that is dedicated to the support of both the of 9600, Asynchronous mode, 8-bit BRG:
asynchronous and synchronous EUSART operation. F OS C
Desired Baud Rate = ------------------------------------------------------------------------
By default, the BRG operates in 8-bit mode. Setting the 64  [SPBRGH:SPBRGL] + 1 
BRG16 bit of the BAUDxCON register selects 16-bit Solving for SPxBRGH:SPxBRGL:
mode.
FOSC
The SPxBRGH, SPxBRGL register pair determines the ---------------------------------------------
Desired Baud Rate
period of the free running baud rate timer. In X = --------------------------------------------- – 1
64
Asynchronous mode the multiplier of the baud rate
16000000
period is determined by both the BRGH bit of the ------------------------
9600
TXxSTA register and the BRG16 bit of the BAUDxCON = ------------------------ – 1
64
register. In Synchronous mode, the BRGH bit is ignored.
=  25.042  = 25
Table 25-3 contains the formulas for determining the
baud rate. Example 25-1 provides a sample calculation 16000000
Calculated Baud Rate = ---------------------------
for determining the baud rate and baud rate error. 64  25 + 1 
Typical baud rates and error values for various = 9615

Asynchronous modes have been computed for your
convenience and are shown in Table 25-5. It may be Calc. Baud Rate – Desired Baud Rate
Error = --------------------------------------------------------------------------------------------
advantageous to use the high baud rate (BRGH = 1), Desired Baud Rate
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate  9615 – 9600 
error. The 16-bit BRG mode is used to achieve slow = ---------------------------------- = 0.16%
9600
baud rates for fast oscillator frequencies.
Writing a new value to the SPxBRGH, SPxBRGL regis-
ter pair causes the BRG timer to be reset (or cleared).
This ensures that the BRG does not wait for a timer
overflow before outputting the new baud rate.
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
make sure that the receive operation is idle before
changing the system clock.

PIC16(L)F1615/9
TABLE 25-3: BAUD RATE FORMULAS
Configuration Bits
BRG/EUSART Mode Baud Rate Formula
SYNC BRG16 BRGH
0 0 0 8-bit/Asynchronous FOSC/[64 (n+1)]

0 0 1 8-bit/Asynchronous
FOSC/[16 (n+1)]
1 0 x 8-bit/Synchronous FOSC/[4 (n+1)]
1 1 x 16-bit/Synchronous
Legend: x = Don’t care, n = value of SPxBRGH, SPxBRGL register pair.
TABLE 25-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Register
on Page
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the Baud Rate Generator.

PIC16(L)F1615/9
TABLE 25-5: BAUD RATES FOR ASYNCHRONOUS MODES

SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz
BAUD
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — — — —
1200 1221 1.73 255 1200 0.00 239 1202 0.16 207 1200 0.00 143
2400 2404 0.16 129 2400 0.00 119 2404 0.16 103 2400 0.00 71
9600 9470 -1.36 32 9600 0.00 29 9615 0.16 25 9600 0.00 17
10417 10417 0.00 29 10286 -1.26 27 10417 0.00 23 10165 -2.42 16
19.2k 19.53k 1.73 15 19.20k 0.00 14 19.23k 0.16 12 19.20k 0.00 8
57.6k — — — 57.60k 0.00 7 — — — 57.60k 0.00 2
115.2k — — — — — — — — — — — —
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
300 — — — 300 0.16 207 300 0.00 191 300 0.16 51
1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12
2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — —
9600 9615 0.16 12 — — — 9600 0.00 5 — — —
10417 10417 0.00 11 10417 0.00 5 — — — — — —
19.2k — — — — — — 19.20k 0.00 2 — — —
57.6k — — — — — — 57.60k 0.00 0 — — —
115.2k — — — — — — — — — — — —
SYNC = 0, BRGH = 1, BRG16 = 0
300 — — — — — — — — — — — —
1200 — — — — — — — — — — — —
2400 — — — — — — — — — — — —
9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71
10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65
19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35
57.6k 56.82k -1.36 21 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11
115.2k 113.64k -1.36 10 115.2k 0.00 9 111.1k -3.55 8 115.2k 0.00 5

PIC16(L)F1615/9
TABLE 25-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 0
300 — — — — — — — — — 300 0.16 207
1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —
SYNC = 0, BRGH = 0, BRG16 = 1
300 300.0 -0.01 4166 300.0 0.00 3839 300.03 0.01 3332 300.0 0.00 2303
1200 1200 -0.03 1041 1200 0.00 959 1200.5 0.04 832 1200 0.00 575
2400 2399 -0.03 520 2400 0.00 479 2398 -0.08 416 2400 0.00 287
9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71
10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65
19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35
57.6k 56.818 -1.36 21 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11
115.2k 113.636 -1.36 10 115.2k 0.00 9 111.11k -3.55 8 115.2k 0.00 5
SYNC = 0, BRGH = 0, BRG16 = 1
300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207
1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —

PIC16(L)F1615/9
TABLE 25-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
300 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 13332 300.0 0.00 9215
1200 1200 -0.01 4166 1200 0.00 3839 1200.1 0.01 3332 1200 0.00 2303
2400 2400 0.02 2082 2400 0.00 1919 2399.5 -0.02 1666 2400 0.00 1151
9600 9597 -0.03 520 9600 0.00 479 9592 -0.08 416 9600 0.00 287
10417 10417 0.00 479 10425 0.08 441 10417 0.00 383 10433 0.16 264
19.2k 19.23k 0.16 259 19.20k 0.00 239 19.23k 0.16 207 19.20k 0.00 143
57.6k 57.47k -0.22 86 57.60k 0.00 79 57.97k 0.64 68 57.60k 0.00 47
115.2k 116.3k 0.94 42 115.2k 0.00 39 114.29k -0.79 34 115.2k 0.00 23
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832
1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207
2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103
9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25
10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23
19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12
57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — —
115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —

PIC16(L)F1615/9
25.4.1 AUTO-BAUD DETECT The BRG auto-baud clock is determined by the BRG16
and BRGH bits as shown in Table 25-6. During ABD,
The EUSART module supports automatic detection
both the SPxBRGH and SPxBRGL registers are used
and calibration of the baud rate.
as a 16-bit counter, independent of the BRG16 bit set-
In the Auto-Baud Detect (ABD) mode, the clock to the ting. While calibrating the baud rate period, the
BRG is reversed. Rather than the BRG clocking the SPxBRGH and SPxBRGL registers are clocked at 1/
incoming RX signal, the RX signal is timing the BRG. 8th the BRG base clock rate. The resulting byte
The Baud Rate Generator is used to time the period of measurement is the average bit time when clocked at
a received 55h (ASCII “U”) which is the Sync character full speed.
for the LIN bus. The unique feature of this character is
Note 1: If the WUE bit is set with the ABDEN bit,
that it has five rising edges including the Stop bit edge.
auto-baud detection will occur on the byte
Setting the ABDEN bit of the BAUDxCON register following the Break character (see
starts the auto-baud calibration sequence. While the Section 25.4.3 “Auto-Wake-up on
ABD sequence takes place, the EUSART state Break”).
machine is held in Idle. On the first rising edge of the
2: It is up to the user to determine that the
receive line, after the Start bit, the SPxBRG begins
incoming character baud rate is within the
counting up using the BRG counter clock as shown in
range of the selected BRG clock source.
Figure 25-6. The fifth rising edge will occur on the RX
Some combinations of oscillator frequency
pin at the end of the eighth bit period. At that time, an
and EUSART baud rates are not possible.
accumulated value totaling the proper BRG period is
left in the SPxBRGH, SPxBRGL register pair, the 3: During the auto-baud process, the auto-
ABDEN bit is automatically cleared and the RCIF baud counter starts counting at one. Upon
interrupt flag is set. The value in the RCxREG needs to completion of the auto-baud sequence, to
be read to clear the RCIF interrupt. RCxREG content achieve maximum accuracy, subtract 1
should be discarded. When calibrating for modes that from the SPxBRGH:SPxBRGL register
do not use the SPxBRGH register the user can verify pair.
that the SPxBRGL register did not overflow by
checking for 00h in the SPxBRGH register.
TABLE 25-6: BRG COUNTER CLOCK RATES

BRG Base BRG ABD
BRG16 BRGH
Clock Clock
0 0 FOSC/64 FOSC/512
1 1 FOSC/4 FOSC/32
Note: During the ABD sequence, SPxBRGL and
SPxBRGH registers are both used as a 16-
bit counter, independent of the BRG16
setting.

PIC16(L)F1615/9
FIGURE 25-6: AUTOMATIC BAUD RATE CALIBRATION
BRG Value XXXXh 0000h 001Ch

Edge #1 Edge #2 Edge #3 Edge #4 Edge #5
RX pin Start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Stop bit
BRG Clock
Set by User Auto Cleared

ABDEN bit
RCIDL
RCIF bit
(Interrupt)
Read
RCxREG
SPxBRGL XXh 1Ch
SPxBRGH XXh 00h
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.

PIC16(L)F1615/9
25.4.2 AUTO-BAUD OVERFLOW 25.4.3.1 Special Considerations
During the course of automatic baud detection, the Break Character
ABDOVF bit of the BAUDxCON register will be set if To avoid character errors or character fragments during
the baud rate counter overflows before the fifth rising a wake-up event, the wake-up character must be all
edge is detected on the RX pin. The ABDOVF bit indi- zeros.
cates that the counter has exceeded the maximum
count that can fit in the 16 bits of the When the wake-up is enabled the function works
SPxBRGH:SPxBRGL register pair. The overflow condi- independent of the low time on the data stream. If the
tion will set the RCIF flag. The counter continues to WUE bit is set and a valid non-zero character is
count until the fifth rising edge is detected on the RX received, the low time from the Start bit to the first rising
pin. The RCIDL bit will remain false (‘0’) until the fifth edge will be interpreted as the wake-up event. The
rising edge at which time the RCIDL bit will be set. If the remaining bits in the character will be received as a
RCREG is read after the overflow occurs but before the fragmented character and subsequent characters can
fifth rising edge then the fifth rising edge will set the result in framing or overrun errors.
RCIF again. Therefore, the initial character in the transmission must
Terminating the auto-baud process early to clear an be all ‘0’s. This must be ten or more bit times, 13-bit
overflow condition will prevent proper detection of the times recommended for LIN bus, or any number of bit
sync character fifth rising edge. If any falling edges of times for standard RS-232 devices.
the sync character have not yet occurred when the Oscillator Start-up Time
ABDEN bit is cleared then those will be falsely detected
Oscillator start-up time must be considered, especially
as Start bits. The following steps are recommended to
in applications using oscillators with longer start-up
clear the overflow condition:
intervals (i.e., HS/PLL mode). The Sync Break (or
1. Read RCREG to clear RCIF. wake-up signal) character must be of sufficient length,
2. If RCIDL is zero then wait for RCIF and repeat and be followed by a sufficient interval, to allow enough
step 1. time for the selected oscillator to start and provide
3. Clear the ABDOVF bit. proper initialization of the EUSART.
WUE Bit
25.4.3 AUTO-WAKE-UP ON BREAK
The wake-up event causes a receive interrupt by
During Sleep mode, all clocks to the EUSART are setting the RCIF bit. The WUE bit is cleared in
suspended. Because of this, the Baud Rate Generator hardware by a rising edge on RX/DT. The interrupt
is inactive and a proper character reception cannot be condition is then cleared in software by reading the
performed. The Auto-Wake-up feature allows the RCxREG register and discarding its contents.
controller to wake-up due to activity on the RX/DT line.
To ensure that no actual data is lost, check the RCIDL
This feature is available only in Asynchronous mode.
bit to verify that a receive operation is not in process
The Auto-Wake-up feature is enabled by setting the before setting the WUE bit. If a receive operation is not
WUE bit of the BAUDxCON register. Once set, the occurring, the WUE bit may then be set just prior to
normal receive sequence on RX/DT is disabled, and the entering the Sleep mode.
EUSART remains in an Idle state, monitoring for a wake-
up event independent of the CPU mode. A wake-up
event consists of a high-to-low transition on the RX/DT
line. (This coincides with the start of a Sync Break or a
wake-up signal character for the LIN protocol.)
The EUSART module generates an RCIF interrupt
coincident with the wake-up event. The interrupt is
generated synchronously to the Q clocks in normal CPU
operating modes (Figure 25-7), and asynchronously if
the device is in Sleep mode (Figure 25-8). The interrupt
condition is cleared by reading the RCxREG register.
The WUE bit is automatically cleared by the low-to-high
transition on the RX line at the end of the Break. This
signals to the user that the Break event is over. At this
point, the EUSART module is in Idle mode waiting to
receive the next character.

PIC16(L)F1615/9
FIGURE 25-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Bit set by user Auto Cleared
WUE bit
RX/DT Line
RCIF
Cleared due to User Read of RCxREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
FIGURE 25-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4

OSC1
Bit Set by User Auto Cleared
WUE bit
RX/DT Line Note 1
RCIF
Cleared due to User Read of RCxREG
Sleep Command Executed Sleep Ends
Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.

PIC16(L)F1615/9
25.4.4 BREAK CHARACTER SEQUENCE 25.4.5 RECEIVING A BREAK CHARACTER
The EUSART module has the capability of sending the The Enhanced EUSART module can receive a Break
special Break character sequences that are required by character in two ways.
the LIN bus standard. A Break character consists of a The first method to detect a Break character uses the
Start bit, followed by 12 ‘0’ bits and a Stop bit. FERR bit of the RCxSTA register and the received data
To send a Break character, set the SENDB and TXEN as indicated by RCxREG. The Baud Rate Generator is
bits of the TXxSTA register. The Break character trans- assumed to have been initialized to the expected baud
mission is then initiated by a write to the TXxREG. The rate.
value of data written to TXxREG will be ignored and all A Break character has been received when;
‘0’s will be transmitted.
• RCIF bit is set
The SENDB bit is automatically reset by hardware after
• FERR bit is set
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte • RCxREG = 00h
following the Break character (typically, the Sync The second method uses the Auto-Wake-up feature
character in the LIN specification). described in Section 25.4.3 “Auto-Wake-up on
The TRMT bit of the TXxSTA register indicates when the Break”. By enabling this feature, the EUSART will
transmit operation is active or idle, just as it does during sample the next two transitions on RX/DT, cause an
normal transmission. See Figure 25-9 for the timing of RCIF interrupt, and receive the next data byte followed
the Break character sequence. by another interrupt.
Note that following a Break character, the user will
25.4.4.1 Break and Sync Transmit Sequence typically want to enable the Auto-Baud Detect feature.
The following sequence will start a message frame For both methods, the user can set the ABDEN bit of
header made up of a Break, followed by an auto-baud the BAUDxCON register before placing the EUSART in
Sync byte. This sequence is typical of a LIN bus Sleep mode.
master.
1. Configure the EUSART for the desired mode.
2. Set the TXEN and SENDB bits to enable the
Break sequence.
3. Load the TXxREG with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TXxREG to load the Sync charac-
ter into the transmit FIFO buffer.
5. After the Break has been sent, the SENDB bit is
reset by hardware and the Sync character is
then transmitted.
When the TXxREG becomes empty, as indicated by
the TXIF, the next data byte can be written to TXxREG.
FIGURE 25-9: SEND BREAK CHARACTER SEQUENCE
Write to TXxREG
Dummy Write
BRG Output
(Shift Clock)
TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit

Break
TXIF bit
(Transmit
Interrupt Flag)
TRMT bit
(Transmit Shift
Empty Flag)
SENDB Sampled Here Auto Cleared
SENDB
(send Break
control bit)

PIC16(L)F1615/9
25.5 EUSART Synchronous Mode Clearing the SCKP bit sets the Idle state as low. When
the SCKP bit is cleared, the data changes on the rising
Synchronous serial communications are typically used edge of each clock.
in systems with a single master and one or more
slaves. The master device contains the necessary 25.5.1.3 Synchronous Master Transmission
circuitry for baud rate generation and supplies the clock
Data is transferred out of the device on the RX/DT pin.
for all devices in the system. Slave devices can take
The RX/DT and TX/CK pin output drivers are automat-
advantage of the master clock by eliminating the
ically enabled when the EUSART is configured for
internal clock generation circuitry.
synchronous master transmit operation.
There are two signal lines in Synchronous mode: a
A transmission is initiated by writing a character to the
bidirectional data line and a clock line. Slaves use the
TXxREG register. If the TSR still contains all or part of
external clock supplied by the master to shift the serial
a previous character, the new character data is held in
data into and out of their respective receive and trans-
the TXxREG until the last bit of the previous character
mit shift registers. Since the data line is bidirectional,
has been transmitted. If this is the first character, or the
synchronous operation is half-duplex only. Half-duplex
previous character has been completely flushed from
refers to the fact that master and slave devices can
the TSR, the data in the TXxREG is immediately trans-
receive and transmit data but not both simultaneously.
ferred to the TSR. The transmission of the character
The EUSART can operate as either a master or slave
commences immediately following the transfer of the
device.
data to the TSR from the TXxREG.
Start and Stop bits are not used in synchronous
Each data bit changes on the leading edge of the
transmissions.
master clock and remains valid until the subsequent
leading clock edge.
25.5.1 SYNCHRONOUS MASTER MODE
The following bits are used to configure the EUSART Note: The TSR register is not mapped in data
for synchronous master operation: memory, so it is not available to the user.
• SYNC = 1 25.5.1.4 Synchronous Master Transmission

• CSRC = 1 Set-up:
• SREN = 0 (for transmit); SREN = 1 (for receive)
1. Initialize the SPxBRGH, SPxBRGL register pair
• CREN = 0 (for transmit); CREN = 1 (for receive) and the BRGH and BRG16 bits to achieve the
• SPEN = 1 desired baud rate (see Section 25.4 “EUSART
Setting the SYNC bit of the TXxSTA register configures Baud Rate Generator (BRG)”).
the device for synchronous operation. Setting the CSRC 2. Enable the synchronous master serial port by
bit of the TXxSTA register configures the device as a setting bits SYNC, SPEN and CSRC.
master. Clearing the SREN and CREN bits of the 3. Disable Receive mode by clearing bits SREN
RCxSTA register ensures that the device is in the and CREN.
Transmit mode, otherwise the device will be configured 4. Enable Transmit mode by setting the TXEN bit.
to receive. Setting the SPEN bit of the RCxSTA register
5. If 9-bit transmission is desired, set the TX9 bit.
enables the EUSART.
6. If interrupts are desired, set the TXIE bit of the
25.5.1.1 Master Clock PIE1 register and the GIE and PEIE bits of the
INTCON register.
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device config- 7. If 9-bit transmission is selected, the ninth bit
ured as a master transmits the clock on the TX/CK line. should be loaded in the TX9D bit.
The TX/CK pin output driver is automatically enabled 8. Start transmission by loading data to the
when the EUSART is configured for synchronous TXxREG register.
transmit or receive operation. Serial data bits change
on the leading edge to ensure they are valid at the
trailing edge of each clock. One clock cycle is gener-
ated for each data bit. Only as many clock cycles are
generated as there are data bits.
25.5.1.2 Clock Polarity

A clock polarity option is provided for Microwire
compatibility. Clock polarity is selected with the SCKP
bit of the BAUDxCON register. Setting the SCKP bit
sets the clock Idle state as high. When the SCKP bit is
set, the data changes on the falling edge of each clock.

PIC16(L)F1615/9
FIGURE 25-10: SYNCHRONOUS TRANSMISSION
RX/DT
pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7
Word 1 Word 2
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
TXxREG Reg Write Word 1 Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
‘1’ ‘1’
TXEN bit
Note: Sync Master mode, SPxBRGL = 0, continuous transmission of two 8-bit words.
FIGURE 25-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7
TX/CK pin
Write to
TXxREG reg
TXIF bit
TRMT bit
TXEN bit

PIC16(L)F1615/9
TABLE 25-7: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
TRANSMISSION
Register
on Page

ANSELB(1) — — ANSB5 ANSB4 — — — — 159
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master transmission.

PIC16(L)F1615/9
25.5.1.5 Synchronous Master Reception 25.5.1.7 Receive Overrun Error
Data is received at the RX/DT pin. The RX/DT pin The receive FIFO buffer can hold two characters. An
output driver is automatically disabled when the overrun error will be generated if a third character, in its
EUSART is configured for synchronous master receive entirety, is received before RCxREG is read to access
operation. the FIFO. When this happens the OERR bit of the
In Synchronous mode, reception is enabled by setting RCxSTA register is set. Previous data in the FIFO will
either the Single Receive Enable bit (SREN of the not be overwritten. The two characters in the FIFO
RCxSTA register) or the Continuous Receive Enable buffer can be read, however, no additional characters
bit (CREN of the RCxSTA register). will be received until the error is cleared. The OERR bit
can only be cleared by clearing the overrun condition.
When SREN is set and CREN is clear, only as many If the overrun error occurred when the SREN bit is set
clock cycles are generated as there are data bits in a and CREN is clear then the error is cleared by reading
single character. The SREN bit is automatically cleared RCxREG. If the overrun occurred when the CREN bit is
at the completion of one character. When CREN is set, set then the error condition is cleared by either clearing
clocks are continuously generated until CREN is the CREN bit of the RCxSTA register or by clearing the
cleared. If CREN is cleared in the middle of a character SPEN bit which resets the EUSART.
the CK clock stops immediately and the partial charac-
ter is discarded. If SREN and CREN are both set, then 25.5.1.8 Receiving 9-bit Characters
SREN is cleared at the completion of the first character
The EUSART supports 9-bit character reception. When
and CREN takes precedence.
the RX9 bit of the RCxSTA register is set the EUSART
To initiate reception, set either SREN or CREN. Data is will shift nine bits into the RSR for each character
sampled at the RX/DT pin on the trailing edge of the received. The RX9D bit of the RCxSTA register is the
TX/CK clock pin and is shifted into the Receive Shift ninth, and Most Significant, data bit of the top unread
Register (RSR). When a complete character is character in the receive FIFO. When reading 9-bit data
received into the RSR, the RCIF bit is set and the char- from the receive FIFO buffer, the RX9D data bit must
acter is automatically transferred to the two character be read before reading the eight Least Significant bits
receive FIFO. The Least Significant eight bits of the top from the RCxREG.
character in the receive FIFO are available in RCxREG.
The RCIF bit remains set as long as there are unread 25.5.1.9 Synchronous Master Reception Set-
characters in the receive FIFO. up:
Note: If the RX/DT function is on an analog pin, 1. Initialize the SPxBRGH, SPxBRGL register pair
the corresponding ANSEL bit must be for the appropriate baud rate. Set or clear the
cleared for the receiver to function. BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
25.5.1.6 Slave Clock 2. Clear the ANSEL bit for the RX pin (if applicable).
Synchronous data transfers use a separate clock line, 3. Enable the synchronous master serial port by
which is synchronous with the data. A device configured setting bits SYNC, SPEN and CSRC.
as a slave receives the clock on the TX/CK line. The TX/ 4. Ensure bits CREN and SREN are clear.
CK pin output driver is automatically disabled when the 5. If interrupts are desired, set the RCIE bit of the
device is configured for synchronous slave transmit or PIE1 register and the GIE and PEIE bits of the
receive operation. Serial data bits change on the leading INTCON register.
edge to ensure they are valid at the trailing edge of each
6. If 9-bit reception is desired, set bit RX9.
clock. One data bit is transferred for each clock cycle.
Only as many clock cycles should be received as there 7. Start reception by setting the SREN bit or for
are data bits. continuous reception, set the CREN bit.
8. Interrupt flag bit RCIF will be set when reception
Note: If the device is configured as a slave and of a character is complete. An interrupt will be
the TX/CK function is on an analog pin, the generated if the enable bit RCIE was set.
corresponding ANSEL bit must be cleared.
9. Read the RCxSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
10. Read the 8-bit received data by reading the
RCxREG register.
11. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCxSTA
register or by clearing the SPEN bit which resets
the EUSART.

PIC16(L)F1615/9
FIGURE 25-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RX/DT
pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit ‘0’ ‘0’
RCIF bit
(Interrupt)
Read
RCxREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 25-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER

RECEPTION
Register
on Page

ANSELB(1) — — ANSB5 ANSB4 — — — — 159
CKPPS — — — CKPPS<4:0> 174, 172
RXPPS — — — RXPPS<4:0> 174, 172
SP1BRGL BRG<7:0> 326*
SP1BRGH BRG<15:8> 326*
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master reception.

PIC16(L)F1615/9
25.5.2 SYNCHRONOUS SLAVE MODE 25.5.2.2 Synchronous Slave Transmission
The following bits are used to configure the EUSART Set-up:
for synchronous slave operation: 1. Set the SYNC and SPEN bits and clear the
• SYNC = 1 CSRC bit.
• CSRC = 0 2. Clear the ANSEL bit for the CK pin (if applicable).
• SREN = 0 (for transmit); SREN = 1 (for receive) 3. Clear the CREN and SREN bits.
• CREN = 0 (for transmit); CREN = 1 (for receive) 4. If interrupts are desired, set the TXIE bit of the
PIE1 register and the GIE and PEIE bits of the
• SPEN = 1
INTCON register.
Setting the SYNC bit of the TXxSTA register configures 5. If 9-bit transmission is desired, set the TX9 bit.
the device for synchronous operation. Clearing the
6. Enable transmission by setting the TXEN bit.
CSRC bit of the TXxSTA register configures the device as
a slave. Clearing the SREN and CREN bits of the 7. If 9-bit transmission is selected, insert the Most
RCxSTA register ensures that the device is in the Significant bit into the TX9D bit.
Transmit mode, otherwise the device will be configured to 8. Start transmission by writing the Least
receive. Setting the SPEN bit of the RCxSTA register Significant eight bits to the TXxREG register.
enables the EUSART.
25.5.2.1 EUSART Synchronous Slave

Transmit
The operation of the Synchronous Master and Slave
modes are identical (see Section
25.5.1.3 “Synchronous Master Transmission”), except
in the case of the Sleep mode.
If two words are written to the TXxREG and then the
SLEEP instruction is executed, the following will occur:
1. The first character will immediately transfer to
the TSR register and transmit.
2. The second word will remain in the TXxREG
register.
3. The TXIF bit will not be set.
4. After the first character has been shifted out of
TSR, the TXxREG register will transfer the
second character to the TSR and the TXIF bit will
now be set.
5. If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.

PIC16(L)F1615/9
TABLE 25-9: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE
TRANSMISSION
Register
on Page

ANSELB(1) — — ANSB5 ANSB4 — — — — 159
CKPPS — — — CKPPS<4:0> 174, 172
RXPPS — — — RXPPS<4:0> 174, 172
(1)
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave transmission.

PIC16(L)F1615/9
25.5.2.3 EUSART Synchronous Slave 25.5.2.4 Synchronous Slave Reception Set-
Reception up:
The operation of the Synchronous Master and Slave 1. Set the SYNC and SPEN bits and clear the
modes is identical (Section 25.5.1.5 “Synchronous CSRC bit.
Master Reception”), with the following exceptions: 2. Clear the ANSEL bit for both the CK and DT pins
• Sleep (if applicable).
• CREN bit is always set, therefore the receiver is 3. If interrupts are desired, set the RCIE bit of the
never idle PIE1 register and the GIE and PEIE bits of the
• SREN bit, which is a “don’t care” in Slave mode INTCON register.
4. If 9-bit reception is desired, set the RX9 bit.
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the 5. Set the CREN bit to enable reception.
word is received, the RSR register will transfer the data 6. The RCIF bit will be set when reception is
to the RCxREG register. If the RCIE enable bit is set, complete. An interrupt will be generated if the
the interrupt generated will wake the device from Sleep RCIE bit was set.
and execute the next instruction. If the GIE bit is also 7. If 9-bit mode is enabled, retrieve the Most
set, the program will branch to the interrupt vector. Significant bit from the RX9D bit of the RCxSTA
register.
8. Retrieve the eight Least Significant bits from the
receive FIFO by reading the RCxREG register.
9. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCxSTA
register or by clearing the SPEN bit which resets
the EUSART.
TABLE 25-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE

RECEPTION
Register
on Page

ANSELB(1) — — ANSB5 ANSB4 — — — — 159
CKPPS — — — CKPPS<4:0> 174, 172
RXPPS — — — RXPPS<4:0> 174, 172
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave reception.

PIC16(L)F1615/9
25.6 EUSART Operation During Sleep 25.6.2 SYNCHRONOUS TRANSMIT
DURING SLEEP
The EUSART will remain active during Sleep only in the
Synchronous Slave mode. All other modes require the To transmit during Sleep, all the following conditions
system clock and therefore cannot generate the neces- must be met before entering Sleep mode:
sary signals to run the Transmit or Receive Shift • The RCxSTA and TXxSTA Control registers must
registers during Sleep. be configured for synchronous slave transmission
Synchronous Slave mode uses an externally generated (see Section 25.5.2.2 “Synchronous Slave
clock to run the Transmit and Receive Shift registers. Transmission Set-up:”).
• The TXIF interrupt flag must be cleared by writing
25.6.1 SYNCHRONOUS RECEIVE DURING the output data to the TXxREG, thereby filling the
SLEEP TSR and transmit buffer.
To receive during Sleep, all the following conditions • If interrupts are desired, set the TXIE bit of the
must be met before entering Sleep mode: PIE1 register and the PEIE bit of the INTCON
register.
• RCxSTA and TXxSTA Control registers must be
configured for Synchronous Slave Reception (see • Interrupt enable bits TXIE of the PIE1 register and
Section 25.5.2.4 “Synchronous Slave PEIE of the INTCON register must set.
Reception Set-up:”). Upon entering Sleep mode, the device will be ready to
• If interrupts are desired, set the RCIE bit of the accept clocks on TX/CK pin and transmit data on the
PIE1 register and the GIE and PEIE bits of the RX/DT pin. When the data word in the TSR has been
INTCON register. completely clocked out by the external device, the
• The RCIF interrupt flag must be cleared by read- pending byte in the TXxREG will transfer to the TSR
ing RCxREG to unload any pending characters in and the TXIF flag will be set. Thereby, waking the pro-
the receive buffer. cessor from Sleep. At this point, the TXxREG is avail-
able to accept another character for transmission,
Upon entering Sleep mode, the device will be ready to which will clear the TXIF flag.
accept data and clocks on the RX/DT and TX/CK pins,
respectively. When the data word has been completely Upon waking from Sleep, the instruction following the
clocked in by the external device, the RCIF interrupt SLEEP instruction will be executed. If the Global
flag bit of the PIR1 register will be set. Thereby, waking Interrupt Enable (GIE) bit is also set then the Interrupt
the processor from Sleep. Service Routine at address 0004h will be called.
Upon waking from Sleep, the instruction following the

SLEEP instruction will be executed. If the Global
Interrupt Enable (GIE) bit of the INTCON register is
also set, then the Interrupt Service Routine at address
004h will be called.

PIC16(L)F1615/9
26.0 CAPTURE/COMPARE/PWM 26.1 Capture Mode
MODULES The Capture mode function described in this section is
The Capture/Compare/PWM module is a peripheral available and identical for all CCP modules.
which allows the user to time and control different Capture mode makes use of the 16-bit Timer1
events, and to generate Pulse-Width Modulation resource. When an event occurs on the CCPx input,
(PWM) signals. In Capture mode, the peripheral allows the 16-bit CCPRxH:CCPRxL register pair captures and
the timing of the duration of an event. The Compare stores the 16-bit value of the TMR1H:TMR1L register
mode allows the user to trigger an external event when pair, respectively. An event is defined as one of the
a predetermined amount of time has expired. The following and is configured by the MODE<3:0> bits of
PWM mode can generate Pulse-Width Modulated the CCPxCON register:
signals of varying frequency and duty cycle. • Every edge (rising or falling)
This family of devices contains two standard Capture/ • Every falling edge
Compare/PWM modules (CCP1 and CCP2). • Every rising edge
• Every 4th rising edge
• Every 16th rising edge
Note 1: In devices with more than one CCP
module, it is very important to pay close The CCPx capture input signal is configured by the
attention to the register names used. A CTS bits of the CCPxCAP register with the following
number placed after the module acronym options:
is used to distinguish between separate • CCPx pin
modules. For example, the CCP1CON • Comparator 1 output (C1_OUT_sync)
and CCP2CON control the same
• Comparator 2 output (C2_OUT_sync)
operational aspects of two completely
different CCP modules. • Interrupt-on-change interrupt trigger
(IOC_interrupt)
2: Throughout this section, generic
references to a CCP module in any of its When a capture is made, the Interrupt Request Flag bit
operating modes may be interpreted as CCPxIF of the PIRx register is set. The interrupt flag
being equally applicable to CCPx module. must be cleared in software. If another capture occurs
Register names, module signals, I/O pins, before the value in the CCPRxH, CCPRxL register pair
and bit names may use the generic is read, the old captured value is overwritten by the new
designator ‘x’ to indicate the use of a captured value.
numeral to distinguish a particular module, Figure 26-1 shows a simplified diagram of the capture
when required. operation.
26.1.1 CCP PIN CONFIGURATION

In Capture mode, select the interrupt source using the
CTS bits of the CCPxCAP register. If the CCPx pin is
chosen, it should be configured as an input by setting
the associated TRIS control bit.

PIC16(L)F1615/9
FIGURE 26-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
Rev. 10-000158D
7/17/2014
RxyPPS
CCPx
CTS<2:0>
TRIS Control
Reserved 111
Reserved 110 CCPRxH CCPRxL
LC2_output 101 16
set CCPxIF
LC1_output 100 Prescaler and
IOC_interrupt 011 1,4,16 Edge Detect
16
C2OUT_sync 010
C1OUT_sync 001 MODE <3:0> TMR1H TMR1L
CCPx 000
26.1.2 TIMER1 MODE RESOURCE 26.1.5 CAPTURE DURING SLEEP

Timer1 must be running in Timer mode or Synchronized Capture mode depends upon the Timer1 module for
Counter mode for the CCP module to use the capture proper operation. There are two options for driving the
feature. In Asynchronous Counter mode, the capture Timer1 module in Capture mode. It can be driven by the
operation may not work. instruction clock (FOSC/4), or by an external clock source.
See Section22.0 “Timer1/3/5 Module with Gate When Timer1 is clocked by FOSC/4, Timer1 will not
Control” for more information on configuring Timer1. increment during Sleep. When the device wakes from
Sleep, Timer1 will continue from its previous state.
26.1.3 SOFTWARE INTERRUPT MODE
Capture mode will operate during Sleep when Timer1
When the Capture mode is changed, a false capture is clocked by an external clock source.
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit of the PIEx register clear to 26.1.6 CAPTURE OUTPUT
avoid false interrupts. Additionally, the user should Whenever a capture occurs, the output of the CCP will
clear the CCPxIF interrupt flag bit of the PIRx register go high for a period equal to one system clock period
following any change in Operating mode. (1/FOSC). This output is available as an input signal to
Note: Clocking Timer1 from the system clock the CWG, as an auto-conversion trigger for the ADC, as
(FOSC) should not be used in Capture an External Reset Signal for the TMR2 modules, as a
mode. In order for Capture mode to window input to the SMT, and as an input to the CLC
recognize the trigger event on the CCPx module. In addition, the CCPx pin output can be
pin, Timer1 must be clocked from the mapped to output pins through the use of PPS (see
instruction clock (FOSC/4) or from an 13.2 “PPS Outputs”).
external clock source.
26.1.4 CCP PRESCALER

There are four prescaler settings specified by the
MODE<3:0> bits of the CCPxCON register. Whenever
the CCP module is turned off, or the CCP module is not
in Capture mode, the prescaler counter is cleared. Any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another does not
clear the prescaler and may generate a false interrupt. To
avoid this unexpected operation, turn the module off by
clearing the EN bit of the CCPxCON register before
changing the prescaler.

PIC16(L)F1615/9
26.2 Compare Mode The action on the pin is based on the value of the
MODE<3:0> control bits of the CCPxCON register. At
The Compare mode function described in this section the same time, the interrupt flag CCPxIF bit is set.
is available and identical for all CCP modules.
All Compare modes can generate an interrupt.
Compare mode makes use of the 16-bit Timer1
resource. The 16-bit value of the CCPRxH:CCPRxL Figure 26-2 shows a simplified diagram of the compare
register pair is constantly compared against the 16-bit operation.
value of the TMR1H:TMR1L register pair. When a
26.2.1 CCPx PIN CONFIGURATION
match occurs, one of the following events can occur:
The user must configure the CCPx pin as an output by
• Toggle the CCPx output
clearing the associated TRIS bit.
• Set the CCPx output
• Clear the CCPx output
• Pulse the CCPx output
• Generate a Software Interrupt
• Optionally Reset TMR1
FIGURE 26-2: COMPARE MODE OPERATION BLOCK DIAGRAM
Rev. 10-000 159B
9/5/201 4
To Peripherals
CCPRxH CCPRxL
set CCPxIF
Output S Q PPS CCP x
Comparator
Logic
R TRIS Control
4 RxyPPS
TMR1H TMR1L MODE<3:0>

PIC16(L)F1615/9
26.2.2 TIMER1 MODE RESOURCE
In Compare mode, Timer1 must be running in either
Timer mode or Synchronized Counter mode. The
compare operation may not work in Asynchronous
Counter mode.
See Section22.0 “Timer1/3/5 Module with Gate
Control” for more information on configuring Timer1.
Note: Clocking Timer1 from the system clock
(FOSC) should not be used in Compare
mode. In order for Compare mode to
recognize the trigger event on the CCPx
pin, TImer1 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.
26.2.3 SOFTWARE INTERRUPT MODE

When Generate Software Interrupt mode is chosen
(MODE<3:0> = 1010), the CCPx module does not
assert control of the CCPx pin (see the CCPxCON
register).
26.2.4 COMPARE DURING SLEEP

The Compare mode is dependent upon the system
clock (FOSC) for proper operation. Since FOSC is shut
down during Sleep mode, the Compare mode will not
function properly during Sleep.
26.2.5 CAPTURE OUTPUT

When in Compare mode, the CCP will provide an
output upon the 16-bit value of the CCPRxH:CCPRxL
register pair matching the TMR1H:TMR1L register pair.
The compare output depends on which Compare mode
the CCP is configured as. If the MODE bits of
CCPxCON register are equal to ‘1011’ or ‘1010’, the
CCP module will output high, while TMR1 is equal to
CCPRxH:CCPRxL register pair. This means that the
pulse width is determined by the TMR1 prescaler. If the
MODE bits of CCPxCON are equal to ‘0001’ or ‘0010’,
the output will toggle upon a match, going from ‘0’ to ‘1’
or vice-versa. If the MODE bits of CCPxCON are equal
to ‘1001’, the output is cleared on a match, and if the
MODE bits are equal to ‘1000’, the output is set on a
match. This output is available as an input signal to the
CWG, as an auto-conversion trigger for the ADC, as an
external Reset signal for the TMR2 modules, as a
window input to the SMT, and as an input to the CLC
module. In addition, the CCPx pin output can be
mapped to output pins through the use of PPS (see
Section13.2 “PPS Outputs”).

PIC16(L)F1615/9
26.3 PWM Overview The term duty cycle describes the proportion of the on
time to the off time and is expressed in percentages,
Pulse-Width Modulation (PWM) is a scheme that where 0% is fully off and 100% is fully on. A lower duty
provides power to a load by switching quickly between cycle corresponds to less power applied and a higher
fully on and fully off states. The PWM signal resembles duty cycle corresponds to more power applied.
a square wave where the high portion of the signal is
considered the on state and the low portion of the signal
is considered the off state. The high portion, also known
as the pulse width, can vary in time and is defined in
steps. A larger number of steps applied, which
lengthens the pulse width, also supplies more power to
the load. Lowering the number of steps applied, which
shortens the pulse width, supplies less power. The
PWM period is defined as the duration of one complete
cycle or the total amount of on and off time combined.
PWM resolution defines the maximum number of steps
that can be present in a single PWM period. A higher
resolution allows for more precise control of the pulse
width time and in turn the power that is applied to the
load.
FIGURE 26-3: SIMPLIFIED PWM BLOCK DIAGRAM
Rev. 10-000 157C
Duty cycle registers 9/5/201 4
CCPRxH CCPRxL
CCPx_out
To Peripherals
set CCPIF
10-bit Latch(2)
(Not accessible by user)
Comparator R Q PPS CCPx
S RxyPPS
TMR2 Module TRIS Control
R
TMR2 (1)
ERS logic
Comparator CCPx_pset
PR2
Notes: 1. 8-bit timer is concatenated with two bits generated by Fosc or two bits of the internal prescaler to
create 10-bit time-base.
2. The alignment of the 10 bits from the CCPR register is determined by the FMT bit.

PIC16(L)F1615/9
26.3.1 STANDARD PWM OPERATION 26.3.2 SETUP FOR PWM OPERATION
The standard PWM function described in this section is The following steps should be taken when configuring
available and identical for all CCP modules. the CCP module for standard PWM operation:
The standard PWM mode generates a Pulse-Width 1. Disable the CCPx pin output driver by setting the
Modulation (PWM) signal on the CCPx pin with up to 10 associated TRIS bit.
bits of resolution. The period, duty cycle, and resolution 2. Determine which timer will be used to clock the
are controlled by the following registers: CCP; Timer2/4/6.
• PR2/4/6 registers 3. Load the associated PR2/4/6 register with the
• T2CON/T4CON/T6CON registers PWM period value.
• CCPRxH:CCPRxL register pair 4. Configure the CCP module for the PWM mode
by loading the CCPxCON register with the
Figure shows a simplified block diagram of PWM
appropriate values.
operation.
5. Load the CCPRxH:CCPRxL register pair with
Note 1: The corresponding TRIS bit must be the PWM duty cycle value.
cleared to enable the PWM output on the 6. Configure and start Timer2/4/6:
CCPx pin.
• Clear the TMR2IF/TMR4IF/TMR6IF
2: Clearing the CCPxCON register will interrupt flag bit of the PIRx register. See
relinquish control of the CCPx pin. Note below.
• Configure the CKPS bits of the TxCON
register with the Timer prescale value.
• Enable the Timer by setting the ON bit of
the TxCON register.
7. Enable PWM output pin:
• Wait until the Timer overflows and the
TMR2IF/TMR4IF/TMR6IF bit of the PIRx
register is set. See Note below.
• Enable the CCPx pin output driver by
clearing the associated TRIS bit.
Note: In order to send a complete duty cycle and
period on the first PWM output, the above
steps must be included in the setup
sequence. If it is not critical to start with a
complete PWM signal on the first output,
then step 6 may be ignored.

PIC16(L)F1615/9
26.4 CCP/PWM Clock Selection Significant two bits of the duty cycle should be written to
bits <7:6> of the CCPRxL register and the Most
The PIC16(L)F1615/9 allows each individual CCP and Significant eight bits to the CCPRxH register. This is
PWM module to select the timer source that controls illustrated in Figure 26-4. These bits can be written at any
the module. Each module has an independent time. The duty cycle value is not latched into the internal
selection. latch until after the period completes (i.e., a match
As there are up to three 8-bit timers with auto-reload between PR2/4/6 and TMR2/4/6 registers occurs).
(Timer2/4/6), PWM mode on the CCP and PWM mod- Equation 26-2 is used to calculate the PWM pulse width.
ules can use any of these timers. Equation 26-3 is used to calculate the PWM duty cycle
The CCPTMRS register is used to select which timer is ratio.
used.
EQUATION 26-2: PULSE WIDTH
26.4.1 USING THE TMR2/4/6 WITH THE
CCP MODULE Pulse Width = CCPRxH:CCPRxL  T OSC
This device has a new version of the TMR2 module that  (TMR2 Prescale Value)
has many new modes, which allow for greater custom-
ization and control of the PWM signals than older parts.
Refer to Section23.6 “Operation Examples” for
examples of PWM signal generation using the different EQUATION 26-3: DUTY CYCLE RATIO
modes of Timer2. The CCP operation requires that the
timer used as the PWM time base has the FOSC/4 clock  CCPRxH:CCPRxL 
Duty Cycle Ratio = --------------------------------------------------
source selected. 4  PRx + 1 
26.4.2 PWM PERIOD

The PWM duty cycle registers are double buffered for
The PWM period is specified by the PR2/4/6 register of glitchless PWM operation.
Timer2/4/6. The PWM period can be calculated using
The 8-bit timer TMR2/4/6 register is concatenated with
the formula of Equation 26-1.
either the 2-bit internal system clock (FOSC), or two bits
of the prescaler, to create the 10-bit time base. The
EQUATION 26-1: PWM PERIOD system clock is used if the Timer2/4/6 prescaler is set to
1:1.
PWM Period =   PR2  + 1   4  T OSC 
When the 10-bit time base matches the internal buffer
(TMR2 Prescale Value)
register, then the CCPx pin is cleared (see Figure ).
Note 1: TOSC = 1/FOSC
FIGURE 26-4: CCPx DUTY-CYCLE
When TMR2/4/6 is equal to its respective PR2/4/6 ALIGNMENT
register, the following three events occur on the next
increment cycle: Rev. 10-000 160A
12/9/201 3
• TMR2/4/6 is cleared CCPRxH CCPRxL

FMT = 0
• The CCPx pin is set. (Exception: If the PWM duty 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
cycle = 0%, the pin will not be set.)
• The PWM duty cycle is latched from the CCPRxH CCPRxL
CCPRxH:CCPRxL pair into the internal 10-bit FMT = 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
latch.
Note: The Timer postscaler (see Figure ) is not 10-bit Duty Cycle
used in the determination of the PWM 9 8 7 6 5 4 3 2 1 0
frequency.
26.4.3 PWM DUTY CYCLE

The PWM duty cycle is specified by writing a 10-bit value 26.4.4 PWM RESOLUTION
to two registers: the CCPRxH:CCPRxL register pair. The resolution determines the number of available duty
Where the particular bits go is determined by the FMT bit cycles for a given period. For example, a 10-bit resolution
of the CCPxCON register. If FMT = 0, the two Most will result in 1024 discrete duty cycles, whereas an 8-bit
Significant bits of the duty cycle value should be written resolution will result in 256 discrete duty cycles.
to bits <1:0> of CCPRxH register and the remaining eight
bits to the CCPRxL register. If FMT = 1, the Least

PIC16(L)F1615/9
The maximum PWM resolution is ten bits when PR2/4/6
is 255. The resolution is a function of the PR2/4/6
register value as shown by Equation 26-4.
EQUATION 26-4: PWM RESOLUTION
log  4  PR2 + 1  
Resolution = ------------------------------------------ bits
log  2 
Note: If the pulse width value is greater than the

period, the assigned PWM pin(s) will
remain unchanged.

PIC16(L)F1615/9
TABLE 26-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescale 16 4 1 1 1 1
PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 6

PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09
26.4.5 CHANGES IN SYSTEM CLOCK

FREQUENCY
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section5.0 “Oscillator Module” for additional details.
26.4.6 EFFECTS OF RESET

Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
26.4.7 PWM OUTPUT

The output of the CCP in PWM mode is the PWM signal
generated by the module and described above. This
output is available as an input signal to the CWG, as an
auto-conversion trigger for the ADC, as an external
Reset signal for the TMR2 modules, as a window input
to the SMT, and as an input to the CLC module. In addi-
tion, the CCPx pin output can be mapped to output pins
through the use of PPS (see Section13.2 “PPS Out-
puts”).

PIC16(L)F1615/9
26.5 Register Definitions: CCP Control
REGISTER 26-1: CCPxCON: CCPx CONTROL REGISTER

R/W-0/0 U-0 R-x R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
EN — OUT FMT MODE<3:0>
bit 7 bit 0
Legend:
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset
bit 7 EN: CCPx Module Enable bit

1 = CCPx is enabled
0 = CCPx is disabled
bit 5 OUT: CCPx Output Data bit (read-only)
bit 4 FMT: CCPW (Pulse-Width) Alignment bit
If MODE = PWM Mode:
1 = Left-aligned format, CCPRxH <7> is the MSb of the PWM duty cycle
0 = Right-aligned format, CCPRxL<0> is the LSb of the PWM duty cycle
bit 3-0 MODE<3:0>: CCPx Mode Selection bit
11xx = PWM mode
1011 = Compare mode: Pulse output, clear TMR1

1010 = Compare mode: Pulse output (0 - 1 - 0)
1001 = Compare mode: clear output on compare match
1000 = Compare mode: set output on compare match
0111 = Capture mode: every 16th rising edge

0110 = Capture mode: every 4th rising edge
0101 = Capture mode: every rising edge
0100 = Capture mode: every falling edge
0011 = Capture mode: every rising or falling edge

0010 = Compare mode: toggle output on match
0001 = Compare mode: Toggle output and clear TMR1 on match
0000 = Capture/Compare/PWM off (resets CCPx module) (reserved for backwards compatibility)

PIC16(L)F1615/9
REGISTER 26-2: CCPTMRS: PWM TIMER SELECTION CONTROL REGISTER 0

P4TSEL<1:0> P3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0>
bit 7 bit 0
Legend:
bit 7-6 P4TSEL<1:0>: PWM4 Timer Selection bits

11 = Reserved
10 = PWM4 is based off Timer6 in PWM mode
bit 5-4 P3TSEL<1:0>: PWM3 Timer Selection bits
11 = Reserved
bit 3-2 C2TSEL<1:0>: CCP2 (PWM2) Timer Selection bits
11 = Reserved
10 = CCP2 is based off Timer6 in PWM mode
bit 1-0 C1TSEL<1:0>: CCP1 (PWM1) Timer Selection bits
11 = Reserved

PIC16(L)F1615/9
REGISTER 26-3: CCPRxL: CCPx LOW BYTE REGISTER

CCPR<7:0>
bit 7 bit 0
Legend:
bit 7-0 MODE = Capture Mode

CCPRxL<7:0>: LSB of captured TMR1 value
MODE = Compare Mode
CCPRxL<7:0>: LSB compared to TMR1 value
MODE = PWM Mode && FMT = 0
CCPRxL<7:0>: CCPW<7:0> — Pulse width Least Significant eight bits
MODE = PWM Mode && FMT = 1
CCPRxL<7:6>: CCPW<1:0> — Pulse width Least Significant two bits
CCPRxL<5:0>: Not used

PIC16(L)F1615/9
REGISTER 26-4: CCPRxH: CCPx HIGH BYTE REGISTER

CCPR<15:8>
bit 7 bit 0
Legend:
bit 7-0 MODE = Capture Mode:

CCPRxH<7:0>: MSB of captured TMR1 value
MODE = Compare Mode:
CCPRxH<7:0>: MSB compared to TMR1 value
MODE = PWM Mode && FMT = 0:
CCPRxH<7:2>: Not used
CCPRxH<1:0>: CCPW<9:8> — Pulse width Most Significant two bits
MODE = PWM Mode && FMT = 1:
CCPRxH<7:0>: CCPW<9:2> — Pulse width Most Significant eight bits
REGISTER 26-5: CCPxCAP: CCPx CAPTURE INPUT SELECTION REGISTER

U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — — CTS<2:0>
bit 7 bit 0
Legend:

bit 2-0 CTS<2:0>: Capture Trigger Input Selection bits
111 = LC4_out
110 = LC3_out
101 = LC2_out
100 = LC1_out
011 = IOC_interrupt
010 = C2_OUT_sync
001 = C1_OUT_sync
000 = CCPx pin

PIC16(L)F1615/9
TABLE 26-3: SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM
Register on
Page
CCPxCAP — — — — — — CTS<1:0> 357

CCPRxL Capture/Compare/PWM Register x (LSB) 356
CCPRxH Capture/Compare/PWM Register x (MSB) 357
CCPTMRS P4TSEL<1:0> P3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> 355
PR2 Timer2 Period Register 244*
TMR2 Timer2 Module Register 236*
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM.

PIC16(L)F1615/9
27.0 PULSE-WIDTH MODULATION Figure 27-1 shows a simplified block diagram of PWM
operation.
(PWM) MODULE
For a step-by-step procedure on how to set up this
The PWM module generates a Pulse-Width Modulated module for PWM operation, refer to Section
signal determined by the duty cycle, period, and reso- 27.1.9 “Setup for PWM Operation using PWMx
lution that are configured by the following registers: Pins”.
• PR2
• T2CON
• PWMxDCH
• PWMxDCL
• PWMxCON
FIGURE 27-1: SIMPLIFIED PWM BLOCK DIAGRAM
Rev. 10-000022B
9/24/2014
Duty cycle registers PWMxDCL<7:6>

PWMxDCH
PWMx_out
To Peripherals
10-bit Latch
(Not visible to user)
Comparator R Q
0
PPS PWMx
1
S Q
TMR2 Module
R PWMxPOL RxyPPS TRIS Control
TMR2 (1)
Comparator
T2_match
PR2
Note 1: 8-bit timer is concatenated with two bits generated by Fosc or two bits of the internal prescaler to
create 10-bit time-base.

PIC16(L)F1615/9
27.1 PWMx Pin Configuration When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
All PWM outputs are multiplexed with the PORT data
latch. The user must configure the pins as outputs by • TMR2 is cleared
clearing the associated TRIS bits. • The PWM output is active. (Exception: When the
PWM duty cycle = 0%, the PWM output will
27.1.1 FUNDAMENTAL OPERATION remain inactive.)
The PWM module produces a 10-bit resolution output. • The PWMxDCH and PWMxDCL register values
Timer2 and PR2 set the period of the PWM. The are latched into the buffers.
PWMxDCL and PWMxDCH registers configure the Note: The Timer2 postscaler has no effect on
duty cycle. The period is common to all PWM modules, the PWM operation.
whereas the duty cycle is independently controlled.
Note: The Timer2 postscaler is not used in the 27.1.4 PWM DUTY CYCLE
determination of the PWM frequency. The The PWM duty cycle is specified by writing a 10-bit
postscaler could be used to have a servo value to the PWMxDCH and PWMxDCL register pair.
update rate at a different frequency than The PWMxDCH register contains the eight MSbs and
the PWM output. the PWMxDCL<7:6>, the two LSbs. The PWMxDCH
All PWM outputs associated with Timer2 are set when and PWMxDCL registers can be written to at any time.
TMR2 is cleared. Each PWMx is cleared when TMR2 Equation 27-2 is used to calculate the PWM pulse width.
is equal to the value specified in the corresponding Equation 27-3 is used to calculate the PWM duty cycle
PWMxDCH (8 MSb) and PWMxDCL<7:6> (2 LSb) reg- ratio.
isters. When the value is greater than or equal to PR2,
the PWM output is never cleared (100% duty cycle).
EQUATION 27-2: PULSE WIDTH
Note: The PWMxDCH and PWMxDCL registers
are double buffered. The buffers are Pulse Width =  PWMxDCH:PWMxDCL<7:6>  
updated when Timer2 matches PR2. Care
should be taken to update both registers T OS C  (TMR2 Prescale Value)
before the timer match occurs.
Note: TOSC = 1/FOSC
27.1.2 PWM OUTPUT POLARITY
The output polarity is inverted by setting the PWMxPOL EQUATION 27-3: DUTY CYCLE RATIO
bit of the PWMxCON register.
 PWMxDCH:PWMxDCL<7:6> 
27.1.3 PWM PERIOD Duty Cycle Ratio = -----------------------------------------------------------------------------------
4  PR2 + 1 
The PWM period is specified by the PR2 register of
Timer2. The PWM period can be calculated using the
The 8-bit timer TMR2 register is concatenated with the
formula of Equation 27-1.
two Least Significant bits of 1/FOSC, adjusted by the
Timer2 prescaler to create the 10-bit time base. The
EQUATION 27-1: PWM PERIOD system clock is used if the Timer2 prescaler is set to 1:1.
PWM Period =   PR2  + 1   4  T OSC  Figure 27-2 shows a waveform of the PWM signal when
the duty cycle is set for the smallest possible pulse.
(TMR2 Prescale Value)
Note: TOSC = 1/FOSC FIGURE 27-2: PWM OUTPUT
Q1 Q2 Q3 Q4 Rev. 10-000023A
7/30/2013
FOSC
PWM Pulse Width
TMR2 = 0
TMR2 = PWMxDC
TMR2 = PR2

PIC16(L)F1615/9
27.1.5 PWM RESOLUTION
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit resolu-
tion will result in 1024 discrete duty cycles, whereas an
8-bit resolution will result in 256 discrete duty cycles.
The maximum PWM resolution is ten bits when PR2 is
255. The resolution is a function of the PR2 register
value as shown by Equation 27-4.
EQUATION 27-4: PWM RESOLUTION
log  4  PR2 + 1  
Resolution = ------------------------------------------ bits
log  2 
Note: If the pulse width value is greater than the

period the assigned PWM pin(s) will
remain unchanged.

PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 6.6

PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09
27.1.6 OPERATION IN SLEEP MODE

In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the
PWMx pin is driving a value, it will continue to drive that
value. When the device wakes up, TMR2 will continue
from its previous state.
27.1.7 CHANGES IN SYSTEM CLOCK

FREQUENCY
The PWM frequency is derived from the system clock
frequency (FOSC). Any changes in the system clock
frequency will result in changes to the PWM frequency.
Refer to Section 5.0 “Oscillator Module” for
additional details.
27.1.8 EFFECTS OF RESET

Any Reset will force all ports to Input mode and the
PWM registers to their Reset states.

PIC16(L)F1615/9
27.1.9 SETUP FOR PWM OPERATION
USING PWMx PINS
The following steps should be taken when configuring
the module for PWM operation using the PWMx pins:
1. Disable the PWMx pin output driver(s) by setting
the associated TRIS bit(s).
2. Clear the PWMxCON register.
3. Load the PR2 register with the PWM period
value.
4. Clear the PWMxDCH register and bits <7:6> of
the PWMxDCL register.
5. Configure and start Timer2:
• Clear the TMR2IF interrupt flag bit of the
PIR1 register. See note below.
• Configure the CKPS bits of the T2CON
register with the Timer2 prescale value.
• Enable Timer2 by setting the ON bit of the
T2CON register.
6. Enable PWM output pin and wait until Timer2
overflows, TMR2IF bit of the PIR1 register is set.
See note below.
7. Enable the PWMx pin output driver(s) by clear-
ing the associated TRIS bit(s) and setting the
PWMxOE bit of the PWMxCON register.
8. Configure the PWM module by loading the
PWMxCON register with the appropriate values.
Note 1: In order to send a complete duty cycle
and period on the first PWM output, the
above steps must be followed in the order
given. If it is not critical to start with a
complete PWM signal, then move Step 8
to replace Step 4.
2: For operation with other peripherals only,
disable PWMx pin outputs.

PIC16(L)F1615/9
27.2 Register Definitions: PWM Control
REGISTER 27-1: PWMxCON: PWM CONTROL REGISTER

R/W-0/0 U-0 R-0/0 R/W-0/0 U-0 U-0 U-0 U-0
PWMxEN — PWMxOUT PWMxPOL — — — —
bit 7 bit 0
Legend:
bit 7 PWMxEN: PWM Module Enable bit

1 = PWM module is enabled
0 = PWM module is disabled
bit 5 PWMxOUT: PWM Module Output Value bit
bit 4 PWMxPOL: PWMx Output Polarity Select bit
1 = PWM output is active-low
0 = PWM output is active-high
REGISTER 27-2: PWMxDCH: PWM DUTY CYCLE HIGH BITS
PWMxDCH<7:0>
bit 7 bit 0
Legend:
bit 7-0 PWMxDCH<7:0>: PWM Duty Cycle Most Significant bits

These bits are the MSbs of the PWM duty cycle. The two LSbs are found in the PWMxDCL register.
REGISTER 27-3: PWMxDCL: PWM DUTY CYCLE LOW BITS

R/W-x/u R/W-x/u U-0 U-0 U-0 U-0 U-0 U-0
PWMxDCL<7:6> — — — — — —
bit 7 bit 0
Legend:
bit 7-6 PWMxDCL<7:6>: PWM Duty Cycle Least Significant bits

These bits are the LSbs of the PWM duty cycle. The MSbs are found in the PWMxDCH register.

PIC16(L)F1615/9
TABLE 27-3: SUMMARY OF REGISTERS ASSOCIATED WITH PWM

Register
on Page
PR2 Timer2 module Period Register 361*
PWM3CON EN — OUT POL — — — — 363
PWM3DCH DC<9:2> 363
PWM3DCL DC<1:0> — — — — — — 363
PWM4CON EN — OUT POL — — — — 363
PWM4DCH DC<9:2> 363
PWM4DCL DC<1:0> — — — — — — 363
TMR2 Timer2 module Register 236*
—(1)
TRISA — — TRISA5 TRISA4 TRISA2 TRISA1 TRISA0 151
Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the PWM.

PIC16(L)F1615/9
28.0 COMPLEMENTARY WAVEFORM 28.1 Fundamental Operation
GENERATOR (CWG) MODULE The CWG module can operate in six different modes,
The Complementary Waveform Generator (CWG) as specified by MODE of the CWGxCON0 register:
produces half-bridge, full-bridge, and steering of PWM • Half-Bridge mode (Figure 28-9)
waveforms. It is backwards compatible with previous • Push-Pull mode (Figure 28-2)
ECCP functions. - Full-Bridge mode, Forward (Figure 28-3)
The CWG has the following features: - Full-Bridge mode, Reverse (Figure 28-3)
• Six operating modes: • Steering mode (Figure 28-10)
- Synchronous Steering mode • Synchronous Steering mode (Figure 28-11)
- Asynchronous Steering mode It may be necessary to guard against the possibility of
- Full-Bridge mode, Forward circuit faults or a feedback event arriving too late or not
- Full-Bridge mode, Reverse at all. In this case, the active drive must be terminated
- Half-Bridge mode before the Fault condition causes damage. Thus, all
output modes support auto-shutdown, which is covered
- Push-Pull mode
in 28.10 “Auto-Shutdown”.
• Output polarity control
• Output steering 28.1.1 HALF-BRIDGE MODE
- Synchronized to rising event In Half-Bridge mode, two output signals are generated
- Immediate effect as true and inverted versions of the input as illustrated
• Independent 6-bit rising and falling event dead- in Figure 28-9. A non-overlap (dead-band) time is
band timers inserted between the two outputs to prevent shoot
- Clocked dead band through current in various power supply applications.
Dead-band control is described in Section
- Independent rising and falling dead-band
28.5 “Dead-Band Control”.
enables
• Auto-shutdown control with: The unused outputs CWGxC and CWGxD drive similar
signals, with polarity independently controlled by the
- Selectable shutdown sources
POLC and POLD bits of the CWGxCON1 register,
- Auto-restart enable respectively.
- Auto-shutdown pin override control

FIGURE 28-1: SIMPLIFIED CWG BLOCK DIAGRAM (HALF-BRIDGE MODE)
Rev. 10-000166B
8/29/2014
CWG_data
Rising Deadband Block

See clock CWG_dataA
CWGxISM signal_out
Register signal_in CWG_dataC
D Q
CWGxISM<3:0>
E Q
R
Falling Deadband Block
clock CWG_dataB
signal_out
signal_in CWG_dataD
EN
SHUTDOWN
HFINTOSC 1
FOSC 0
PIC16(L)F1615/9
CWGxCLK<0>
DS40001770D-page 366
PIC16(L)F1615/9
28.1.2 PUSH-PULL MODE
In Push-Pull mode, two output signals are generated,
alternating copies of the input as illustrated in
Figure 28-2. This alternation creates the push-pull
effect required for driving some transformer-based
power supply designs.
The push-pull sequencer is reset whenever EN = 0 or
if an auto-shutdown event occurs. The sequencer is
clocked by the first input pulse, and the first output
appears on CWGxA.
The unused outputs CWGxC and CWGxD drive copies
of CWGxA and CWGxB, respectively, but with polarity
controlled by the POLC and POLD bits of the
CWGxCON1 register, respectively.
28.1.3 FULL-BRIDGE MODES

In Forward and Reverse Full-Bridge modes, three out-
puts drive static values while the fourth is modulated by
the input data signal. In Forward Full-Bridge mode,
CWGxA is driven to its active state, CWGxB and
CWGxC are driven to their inactive state, and CWGxD
is modulated by the input signal. In Reverse Full-Bridge
mode, CWGxC is driven to its active state, CWGxA and
CWGxD are driven to their inactive states, and CWGxB
is modulated by the input signal. In Full-Bridge mode,
the dead-band period is used when there is a switch
from forward to reverse or vice-versa. This dead-band
control is described in Section 28.5 “Dead-Band Con-
trol”, with additional details in Section 28.6 “Rising
Edge and Reverse Dead Band” and Section
28.7 “Falling Edge and Forward Dead Band”.
The mode selection may be toggled between forward
and reverse by toggling the MODE<0> bit of the
CWGxCON0 while keeping MODE<2:1> static, without
disabling the CWG module.

FIGURE 28-2: SIMPLIFIED CWG BLOCK DIAGRAM (PUSH-PULL MODE)
Rev. 10-000167B
8/29/2014
CWG_data
See
CWGxISM
Register D Q
CWG_dataA
Q CWG_dataC
R
CWG_dataB
D Q
CWG_dataD
CWGxISM<3:0>
E Q
R
EN
SHUTDOWN
PIC16(L)F1615/9
DS40001770D-page 368
FIGURE 28-3: SIMPLIFIED CWG BLOCK DIAGRAM (FORWARD AND REVERSE FULL-BRIDGE MODES)
Rev. 10-000165B
8/29/2014
MODE0 Reverse Deadband Block

clock
signal_out
See signal_in
CWGxISM
Register
CWG_dataA
D Q CWG_dataB
D Q
Q CWG_dataC
CWGxISM<3:0>
E
R
Q CWG_dataD
clock
signal_out
signal_in
Forward Deadband Block
EN CWG_data
SHUTDOWN
HFINTOSC 1
FOSC 0
PIC16(L)F1615/9
CWGxCLK<0>
DS40001770D-page 369
PIC16(L)F1615/9
28.1.4 STEERING MODES
In Steering modes, the data input can be steered to any
or all of the four CWG output pins. In Synchronous
Steering mode, changes to steering selection registers
take effect on the next rising input.
In Non-Synchronous mode, steering takes effect on the
next instruction cycle. Additional details are provided in
Section 28.9 “CWG Steering Mode”.

FIGURE 28-4: SIMPLIFIED CWG BLOCK DIAGRAM (OUTPUT STEERING MODES)
Rev. 10-000164B
8/26/2015
See
CWGxISM CWG_dataA
Register
CWG_dataB
CWG_data
CWG_dataC
CWG_dataD
D Q
CWGxISM <3:0>
E Q
R
EN
SHUTDOWN
PIC16(L)F1615/9
DS40001770D-page 371
PIC16(L)F1615/9
28.2 Clock Source
The CWG module allows the following clock sources to
be selected:
• Fosc (system clock)
• HFINTOSC (16 MHz only)
The clock sources are selected using the CS bit of the
CWGxCLKCON register.
28.3 Selectable Input Sources

The CWG generates the output waveforms from the
input sources in Table 28-1.
TABLE 28-1: SELECTABLE INPUT

SOURCES
Source Peripheral Signal Name
CWG pin PPS selection
CCP1 CCP1_out
CCP2 CCP2_out
CLC1 LC1_out
CLC2 LC2_out
CLC3 LC3_out
CLC4 LC4_out
PWM3 PWM3_out
PWM4 PWM4_out
The input sources are selected using the CWGxISM
register.
28.4 Output Control

28.4.1 OUTPUT ENABLES
Each CWG output pin has individual output enable con-
trol. Output enables are selected with the Gx1OEx
<3:0> bits. When an output enable control is cleared,
the module asserts no control over the pin. When an
output enable is set, the override value or active PWM
waveform is applied to the pin per the port priority
selection. The output pin enables are dependent on the
module enable bit, EN of the CWGxCON0 register.
When EN is cleared, CWG output enables and CWG
drive levels have no effect.
28.4.2 POLARITY CONTROL

The polarity of each CWG output can be selected inde-
pendently. When the output polarity bit is set, the corre-
sponding output is active-high. Clearing the output
polarity bit configures the corresponding output as
active-low. However, polarity does not affect the over-
ride levels. Output polarity is selected with the POLx
bits of the CWGxCON1. Auto-shutdown and steering
options are unaffected by polarity.

PIC16(L)F1615/9
FIGURE 28-5: CWG OUTPUT BLOCK DIAGRAM
Rev. 10-000171B
9/24/2014
LSAC<1:0>
‘1’ 11 RxyPPS
TRIS Control
‘0’ 10
1
CWG_dataA High Z 01 PPS CWGxA
1 0
POLA 00
OVRA 0
STRA(1)
LSBD<1:0>
‘1’ 11 RxyPPS
TRIS Control
‘0’ 10
1
CWG_dataB High Z 01 PPS CWGxB
1 0
POLB 00
OVRB 0
STRB(1)
LSAC<1:0>
‘1’ 11 RxyPPS
TRIS Control
‘0’ 10
1
CWG_dataC High Z 01 PPS CWGxC
1 0
POLC 00
OVRC 0
STRC(1)
LSBD<1:0>
‘1’ 11 RxyPPS
TRIS Control
‘0’ 10
1
CWG_dataD High Z 01 PPS CWGxD
1 0
POLD 00
OVRD 0
STRD(1)
CWG_shutdown
Note 1: STRx is held to 1 in all modes other than Output Steering Mode.

PIC16(L)F1615/9
28.5 Dead-Band Control 28.7 Falling Edge and Forward Dead
The dead-band control provides non-overlapping PWM
Band
signals to prevent shoot-through current in PWM CWGxDBF controls the dead-band time at the leading
switches. Dead-band operation is employed for Half-
edge of CWGxB (Half-Bridge mode) or the leading
Bridge and Full-Bridge modes. The CWG contains two
edge of CWGxD (Full-Bridge mode). The CWGxDBF
6-bit dead-band counters. One is used for the rising
edge of the input source control in Half-Bridge mode or value is double-buffered. When EN = 0, the
for reverse dead-band Full-Bridge mode. The other is CWGxDBF register is loaded immediately when
used for the falling edge of the input source control in CWGxDBF is written. When EN = 1 then software
Half-Bridge mode or for forward dead band in Full- must set the LD bit of the CWGxCON0 register, and
Bridge mode. the buffer will be loaded at the next falling edge of the
Dead band is timed by counting CWG clock periods CWG input signal. If the input source signal is not
from zero up to the value in the rising or falling dead- present for enough time for the count to be completed,
band counter registers. See CWGxDBR and no output will be seen on the respective output.
CWGxDBF registers, respectively.
Refer to Figure 28.6 and Figure 28-7 for examples.
28.5.1 DEAD-BAND FUNCTIONALITY IN
HALF-BRIDGE MODE
In Half-Bridge mode, the dead-band counters dictate
the delay between the falling edge of the normal output
and the rising edge of the inverted output. This can be
seen in Figure 28-9.
28.5.2 DEAD-BAND FUNCTIONALITY IN

FULL-BRIDGE MODE
In Full-Bridge mode, the dead-band counters are used
when undergoing a direction change. The MODE<0>
bit of the CWGxCON0 register can be set or cleared
while the CWG is running, allowing for changes from
Forward to Reverse mode. The CWGxA and CWGxC
signals will change immediately upon the first rising
input edge following a direction change, but the modu-
lated signals (CWGxB or CWGxD, depending on the
direction of the change) will experience a delay dictated
by the dead-band counters. This is demonstrated in
Figure 28-3.
28.6 Rising Edge and Reverse Dead

Band
CWGxDBR controls the rising edge dead-band time at
the leading edge of CWGxA (Half-Bridge mode) or the
leading edge of CWGxB (Full-Bridge mode). The
CWGxDBR value is double-buffered. When EN = 0,
the CWGxDBR register is loaded immediately when
CWGxDBR is written. When EN = 1, then software
must set the LD bit of the CWGxCON0 register, and the
buffer will be loaded at the next falling edge of the CWG
input signal. If the input source signal is not present for
enough time for the count to be completed, no output
will be seen on the respective output.

FIGURE 28-6: DEAD-BAND OPERATION CWGXDBR = 0X01, CWGXDBF = 0X02
cwg_clock
Input Source
CWGxA
CWGxB
FIGURE 28-7: DEAD-BAND OPERATION, CWGXDBR = 0X03, CWGXDBF = 0X04, SOURCE SHORTER THAN DEAD BAND
cwg_clock
Input Source
PIC16(L)F1615/9
CWGxA
CWGxB
source shorter than dead band

DS40001770D-page 375
PIC16(L)F1615/9
28.8 Dead-Band Uncertainty EQUATION 28-1: DEAD-BAND
UNCERTAINTY
When the rising and falling edges of the input source
are asynchronous to the CWG clock, it creates uncer-
tainty in the dead-band time delay. The maximum 1
TDEADBAND_UNCERTAINTY = -----------------------------
uncertainty is equal to one CWG clock period. Refer to Fcwg_clock
Equation 28-1 for more details.
Example:
FCWG_CLOCK = 16 MHz
Therefore:
1
TDEADBAND_UNCERTAINTY = -----------------------------
Fcwg_clock
1
= ------------------
16MHz
= 62.5ns
FIGURE 28-8: EXAMPLE OF PWM DIRECTION CHANGE
MODE0
CWGxA
CWGxB
CWGxC
CWGxD
No delay CWGxDBR No delay CWGxDBF

CWGx_data
Note 1:WGPOL{ABCD} = 0
2: The direction bit MODE<0> (Register 28-1) can be written any time during the PWM cycle, and takes effect at the
next rising CWGx_data.
3: When changing directions, CWGxA and CWGxC switch at rising CWGx_data; modulated CWGxB and CWGxD are
held inactive for the dead band duration shown; dead band affects only the first pulse after the direction change.
FIGURE 28-9: CWG HALF-BRIDGE MODE OPERATION
CWGx_clock
CWGxA
CWGxC
Rising Event Dead Band Rising Event D
Falling Event Dead Band Falling Event Dead Band
CWGxB
CWGxD
CWGx_data
Note: CWGx_rising_src = CCP1_out, CWGx_falling_src = ~CCP1_out

PIC16(L)F1615/9
28.9 CWG Steering Mode 28.9.1 STEERING SYNCHRONIZATION
In Steering mode (MODE = 00x), the CWG allows any Changing the MODE bits allows for two modes of steer-
combination of the CWGxx pins to be the modulated ing, synchronous and asynchronous.
signal. The same signal can be simultaneously avail- When MODE = 000, the steering event is asynchro-
able on multiple pins, or a fixed-value output can be nous and will happen at the end of the instruction that
presented. writes to STRx (that is, immediately). In this case, the
When the respective STRx bit of CWGxOCON0 is ‘0’, output signal at the output pin may be an incomplete
the corresponding pin is held at the level defined. When waveform. This can be useful for immediately removing
the respective STRx bit of CWGxOCON0 is ‘1’, the pin a signal from the pin.
is driven by the input data signal. The user can assign When MODE = 001, the steering update is synchro-
the input data signal to one, two, three, or all four output nous and occurs at the beginning of the next rising
pins. edge of the input data signal. In this case, steering the
The POLx bits of the CWGxCON1 register control the output on/off will always produce a complete waveform.
signal polarity only when STRx = 1. Figure 28-10 and Figure 28-11 illustrate the timing of
The CWG auto-shutdown operation also applies in asynchronous and synchronous steering, respectively.
Steering modes as described in Section 28.10 “Auto-
Shutdown”. An auto-shutdown event will only affect
pins that have STRx = 1.
FIGURE 28-10: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION

(MODE<2:0> = 000)
Rising Event
CWGx_data
(Rising and Falling Source)
STR<D:A>
CWGx<D:A> OVR<D:A> OVR<D:A> Data
follows CWGx_data
FIGURE 28-11: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION

(MODE<2:0> = 001)
CWGx_data
(Rising and Falling Source)
STR<D:A>
CWGx<D:A> OVR<D:A> Data OVR<D:A> Data
follows CWGx_data

PIC16(L)F1615/9
28.10 Auto-Shutdown 28.11 Operation During Sleep
Auto-shutdown is a method to immediately override the The CWG module operates independently from the
CWG output levels with specific overrides that allow for system clock and will continue to run during Sleep,
safe shutdown of the circuit. The shutdown state can be provided that the clock and input sources selected
either cleared automatically or held until cleared by remain active.
software. The auto-shutdown circuit is illustrated in The HFINTOSC remains active during Sleep when all
Figure 28-12. the following conditions are met:
28.10.1 SHUTDOWN • CWG module is enabled
The shutdown state can be entered by either of the • Input source is active
following two methods: • HFINTOSC is selected as the clock source,
regardless of the system clock source selected.
• Software generated
• External Input In other words, if the HFINTOSC is simultaneously
selected as the system clock and the CWG clock
28.10.1.1 Software Generated Shutdown source, when the CWG is enabled and the input source
is active, then the CPU will go idle during Sleep, but the
Setting the SHUTDOWN bit of the CWGxAS0 register HFINTOSC will remain active and the CWG will con-
will force the CWG into the shutdown state. tinue to operate. This will have a direct effect on the
When the auto-restart is disabled, the shutdown state Sleep mode current.
will persist as long as the SHUTDOWN bit is set.
When auto-restart is enabled, the SHUTDOWN bit will
clear automatically and resume operation on the next
rising edge event.
28.10.2 EXTERNAL INPUT SOURCE

External shutdown inputs provide the fastest way to
safely suspend CWG operation in the event of a Fault
condition. When any of the selected shutdown inputs
goes active, the CWG outputs will immediately go to the
selected override levels without software delay. Several
input sources can be selected to cause a shutdown con-
dition. All input sources are active-low. The sources are:
• Comparator C1_OUT_sync
• Comparator C2_OUT_sync
• Timer2 – TMR2_postscaled
• CWGxIN input pin
Shutdown inputs are selected using the CWGxAS1
register (Register 28-6).
Note: Shutdown inputs are level sensitive, not
edge sensitive. The shutdown state can-
not be cleared, except by disabling auto-
shutdown, as long as the shutdown input
level persists.

FIGURE 28-12: CWG SHUTDOWN BLOCK DIAGRAM
Write ‘1’ to Rev. 10-000172B

1/21/2015
SHUTDOWN bit
PPS
INAS
CWGINPPS
C1OUT_sync
C1AS
C2OUT_sync
C2AS
TMR2_postscaled SHUTDOWN S
S Q
TMR2AS
D Q CWG_shutdown
TMR4_postscaled
REN FREEZE
R
TMR4AS Write ‘0’ to
SHUTDOWN bit
TMR6_postscaled CWG_data CK
TMR6AS
PIC16(L)F1615/9
DS40001770D-page 379
PIC16(L)F1615/9
28.12 Configuring the CWG 28.12.2 AUTO-SHUTDOWN RESTART
The following steps illustrate how to properly configure After an auto-shutdown event has occurred, there are
the CWG. two ways to resume operation:
1. Ensure that the TRIS control bits corresponding • Software controlled

to the desired CWG pins for your application are • Auto-restart
set so that the pins are configured as inputs. The restart method is selected with the REN bit of the
2. Clear the EN bit, if not already cleared. CWGxAS0 register. Waveforms of software controlled
3. Set desired mode of operation with the MODE and automatic restarts are shown in Figure 28-13 and
bits. Figure 28-14.
4. Set desired dead-band times, if applicable to
mode, with the CWGxDBR and CWGxDBF reg- 28.12.2.1 Software Controlled Restart
isters. When the REN bit of the CWGxAS0 register is cleared,
5. Setup the following controls in the CWGxAS0 the CWG must be restarted after an auto-shutdown
and CWGxAS1 registers. event by software. Clearing the shutdown state
requires all selected shutdown inputs to be low, other-
a. Select the desired shutdown source.
wise the SHUTDOWN bit will remain set. The overrides
b. Select both output overrides to the desired lev- will remain in effect until the first rising edge event after
els (this is necessary even if not using auto- the SHUTDOWN bit is cleared. The CWG will then
shutdown because start-up will be from a shut- resume operation.
down state).
c. Set which pins will be affected by auto-shut- 28.12.2.2 Auto-Restart
down with the CWGxAS1 register. When the REN bit of the CWGxAS0 register is set, the
d. Set the SHUTDOWN bit and clear the REN bit. CWG will restart from the auto-shutdown state auto-
matically. The SHUTDOWN bit will clear automatically
6. Select the desired input source using the when all shutdown sources go low. The overrides will
CWGxISM register. remain in effect until the first rising edge event after the
7. Configure the following controls. SHUTDOWN bit is cleared. The CWG will then resume
a. Select desired clock source using the operation.
CWGxCLKCON register.
b. Select the desired output polarities using the
CWGxCON1 register.
c. Set the output enables for the desired outputs.
8. Set the EN bit.
9. Clear TRIS control bits corresponding to the
desired output pins to configure these pins as
outputs.
10. If auto-restart is to be used, set the REN bit and
the SHUTDOWN bit will be cleared automati-
cally. Otherwise, clear the SHUTDOWN bit to
start the CWG.
28.12.1 PIN OVERRIDE LEVELS

The levels driven to the output pins, while the shutdown
input is true, are controlled by the LSBD and LSAC bits
of the CWGxAS0 register. LSBD<1:0> controls the
CWGxB and D override levels and LSAC<1:0> controls
the CWGxA and C override levels. The control bit logic
level corresponds to the output logic drive level while in
the shutdown state. The polarity control does not affect
the override level.

FIGURE 28-13: SHUTDOWN FUNCTIONALITY, AUTO-RESTART DISABLED (REN = 0, LSAC = 01, LSBD = 01)
Shutdown Event Ceases REN Cleared by Software
CWG Input
Source
Shutdown Source
SHUTDOWN
CWGxA Tri-State (No Pulse)

CWGxC
CWGxB Tri-State (No Pulse)

CWGxD
No Shutdown
Shutdown Output Resumes
PIC16(L)F1615/9
DS40001770D-page 381
PIC16(L)F1615/9
FIGURE 28-14: SHUTDOWN FUNCTIONALITY, AUTO-RESTART ENABLED (REN = 1, LSAC = 01,
LSBD = 01)
Shutdown Event Ceases REN auto-cleared by hardware
Tri-State (No Pulse)
Tri-State (No Pulse)

No Shutdown
Shutdown Output Resumes

PIC16(L)F1615/9
28.13 Register Definitions: CWG Control
REGISTER 28-1: CWGxCON0: CWGx CONTROL REGISTER 0

R/W-0/0 R/W/HC-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
EN LD(1) — — — MODE<2:0>
bit 7 bit 0
Legend:
bit 7 EN: CWGx Enable bit

1 = Module is enabled
0 = Module is disabled
bit 6 LD: CWGx Load Buffer bits(1)
1 = Buffers to be loaded on the next rising/falling event
0 = Buffers not loaded
bit 2-0 MODE<2:0>: CWGx Mode bits
111 = Reserved
110 = Reserved
101 = CWG outputs operate in Push-Pull mode
100 = CWG outputs operate in Half-Bridge mode
011 = CWG outputs operate in Reverse Full-Bridge mode
010 = CWG outputs operate in Forward Full-Bridge mode
001 = CWG outputs operate in Synchronous Steering mode
000 = CWG outputs operate in Steering mode
Note 1: This bit can only be set after EN = 1 and cannot be set in the same instruction that EN is set.

PIC16(L)F1615/9
REGISTER 28-2: CWGxCON1: CWGx CONTROL REGISTER 1

U-0 U-0 R-x U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — IN — POLD POLC POLB POLA
bit 7 bit 0
Legend:

bit 5 IN: CWG Input Value
bit 3 POLD: CWGxD Output Polarity bit
1 = Signal output is inverted polarity
0 = Signal output is normal polarity
bit 2 POLC: CWGxC Output Polarity bit
bit 1 POLB: CWGxB Output Polarity bit
bit 0 POLA: CWGxA Output Polarity bit

PIC16(L)F1615/9
REGISTER 28-3: CWGxDBR: CWGx RISING DEAD-BAND COUNTER REGISTER

— — DBR<5:0>
bit 7 bit 0
Legend:

bit 5-0 DBR<5:0>: Rising Event Dead-Band Value for Counter bits
REGISTER 28-4: CWGxDBF: CWGx FALLING DEAD-BAND COUNTER REGISTER

— — DBF<5:0>
bit 7 bit 0
Legend:

bit 5-0 DBF<5:0>: Falling Event Dead-Band Value for Counter bits

PIC16(L)F1615/9
REGISTER 28-5: CWGxAS0: CWGx AUTO-SHUTDOWN CONTROL REGISTER 0

R/W/HS-0/0 R/W-0/0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 U-0 U-0
SHUTDOWN(1, 2) REN LSBD<1:0> LSAC<1:0> — —
bit 7 bit 0
Legend:
bit 7 SHUTDOWN: Auto-Shutdown Event Status bit(1, 2)

1 = An Auto-Shutdown state is in effect
0 = No Auto-shutdown event has occurred
bit 6 REN: Auto-Restart Enable bit
1 = Auto-restart enabled
0 = Auto-restart disabled
bit 5-4 LSBD<1:0>: CWGxB and CWGxD Auto-Shutdown State Control bits
11 = A logic ‘1’ is placed on CWGxB/D when an auto-shutdown event is present
10 = A logic ‘0’ is placed on CWGxB/D when an auto-shutdown event is present
01 = Pin is tri-stated on CWGxB/D when an auto-shutdown event is present
00 = The inactive state of the pin, including polarity, is placed on CWGxB/D after the required
dead-band interval
bit 3-2 LSAC<1:0>: CWGxA and CWGxC Auto-Shutdown State Control bits
11 = A logic ‘1’ is placed on CWGxA/C when an auto-shutdown event is present
10 = A logic ‘0’ is placed on CWGxA/C when an auto-shutdown event is present
01 = Pin is tri-stated on CWGxA/C when an auto-shutdown event is present
00 = The inactive state of the pin, including polarity, is placed on CWGxA/C after the required
dead-band interval
Note 1: This bit may be written while EN = 0 (CWGxCON0 register) to place the outputs into the shutdown config-
uration.
2: The outputs will remain in auto-shutdown state until the next rising edge of the input signal after this bit is
cleared.

PIC16(L)F1615/9
REGISTER 28-6: CWGxAS1: CWGx AUTO-SHUTDOWN CONTROL REGISTER 1

U-1 R/W-0/0 R/W-0/0 R/W-0/0 U-1 R/W-0/0 R/W-0/0 R/W-0/0
— TMR6AS TMR4AS TMR2AS — C2AS(1) C1AS INAS
bit 7 bit 0
Legend:

bit 6 TMR6AS: TMR6 Postscale Output bit
1 = TMR6 postscale shut-down is enabled
0 = TMR6 postscale shut-down is disabled
bit 2 C2AS: Comparator C2 Output bit
1 = C2 output shut-down is enabled
0 = C2 output shut-down is disabled
bit 1 C1AS: Comparator C1 Output bit
1 = C1 output shut-down is enabled
0 = C1 output shut-down is disabled
bit 0 INAS: CWGx Input Pin bit
1 = CWGxIN input pin shut-down is enabled
0 = CWGxIN input pin shut-down is disabled

PIC16(L)F1615/9
REGISTER 28-7: CWGxOCON0: CWGx STEERING CONTROL REGISTER 0(1)

OVRD OVRC OVRB OVRA STRD(2) STRC(2) STRB(2) STRA(2)
bit 7 bit 0
Legend:
bit 7 OVRD: Steering Data D bit

bit 6 OVRC: Steering Data C bit
bit 5 OVRB: Steering Data B bit
bit 4 OVRA: Steering Data A bit
bit 3 STRD: Steering Enable D bit(2)
1 = CWGxD output has the CWGx_data waveform with polarity control from POLD bit
0 = CWGxD output is assigned the value of OVRD bit
bit 2 STRC: Steering Enable C bit(2)
1 = CWGxC output has the CWGx_data waveform with polarity control from POLC bit
0 = CWGxC output is assigned the value of OVRC bit
bit 1 STRB: Steering Enable B bit(2)
1 = CWGxB output has the CWGx_data waveform with polarity control from POLB bit
0 = CWGxB output is assigned the value of OVRB bit
bit 0 STRA: Steering Enable A bit(2)
1 = CWGxA output has the CWGx_data waveform with polarity control from POLA bit
0 = CWGxA output is assigned the value of OVRA bit
Note 1: The bits in this register apply only when MODE<2:0> = 00x.
2: This bit is effectively double-buffered when MODE<2:0> = 001.

PIC16(L)F1615/9
REGISTER 28-8: CWGxCLKCON: CWGx CLOCK SELECTION CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0
— — — — — — — CS
bit 7 bit 0
Legend:

bit 0 CS: CWGx Clock Selection bit
1 = HFINTOSC 16 MHz is selected
0 = FOSC is selected
REGISTER 28-9: CWGxISM: CWGx INPUT SELECTION REGISTER

U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — IS<3:0>
bit 7 bit 0
Legend:

bit 3-0 IS<3:0>: CWGx Input Selection bits
•
•
•
1010 = PWM4_out
1001 = PWM3_out
1000 = LC4_out
0111 = LC3_out
0110 = LC2_out
0101 = LC1_out
0100 = CCP2_out
0011 = CCP1_out
0010 = C2_OUT_sync
0001 = C1_OUT_sync
0000 = CWGxIN pin

PIC16(L)F1615/9
TABLE 28-2: SUMMARY OF REGISTERS ASSOCIATED WITH CWG
Register
on Page
CWG1AS0 SHUTDOWN REN LSBD<1:0> LSAC<1:0> — — 386

CWG1AS1 — TMR6AS TMR4AS TMR2AS — C2AS C1AS INAS 387
CWG1CLKCON — — — — — — — CS 389
CWG1CON0 EN LD — — — MODE<2:0> 388
CWG1CON1 — — IN — POLD POLC POLB POLA 384
CWG1DBF — — DBF<5:0> 385
CWG1DBR — — DBR<5:0> 385
CWG1ISM — — — — IS<3:0> 389
CWG1OCON0 OVRD OVRC OVRB OVRA STRD STRC STRB STRA 388
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by CWG.

PIC16(L)F1615/9
29.0 SIGNAL MEASUREMENT TIMER
(SMT)
The SMT is a 24-bit counter with advanced clock and
gating logic, which can be configured for measuring a
variety of digital signal parameters such as pulse width,
frequency and duty cycle, and the time difference
between edges on two signals.
Features of the SMT include:
• 24-bit timer/counter
- Four 8-bit registers (SMTxTMRL/H/U)
- Readable and writable
- Optional 16-bit operating mode
• Two 24-bit measurement capture registers
• One 24-bit period match register
• Multi-mode operation, including relative timing
measurement
• Interrupt on period match
• Multiple clock, gate and signal sources
• Interrupt on acquisition complete
• Ability to read current input values
Note: These devices implement two SMT mod-

ules. All references to SMTx apply to
SMT1 and SMT2.

PIC16(L)F1615/9
FIGURE 29-1: SMT BLOCK DIAGRAM
Rev. 10-000161B
7/3/2014
Period Latch
Set SMTxPRAIF
SMT_window SMT
Clock SMTxPR
Sync
Circuit
Control Set SMTxIF
Logic Comparator
SMT_signal SMT
Clock
Sync
Circuit
24-bit
Reset SMTxCPR
Buffer
Enable SMTxTMR 24-bit

SMTxCPW
Reserved 111 Buffer
AT1_perclk 110 Window Latch

Set SMTxPWAIF
MFINTOSC 101
MFINTOSC/16 100
Prescaler
LFINTOSC 011
HFINTOSC 010
FOSC/4 001
FOSC 000
SMTxCLK<2:0>
FIGURE 29-2: SMT SIGNAL AND WINDOW BLOCK DIAGRAM

Rev. 10-000173B
7/21/2014
See See
SMTxSIG SMT_signal SMTxWIN SMT_window
Register Register
SMTxSIG<3:0> SMTxWIN<3:0>

PIC16(L)F1615/9
29.1 SMT Operation 29.2.3 PERIOD LATCH REGISTERS
The core of the module is the 24-bit counter, SMTxTMR The SMTxCPR registers are the 24-bit SMT period
combined with a complex data acquisition front-end. latch. They are used to latch in other values of the
Depending on the mode of operation selected, the SMT SMTxTMR when triggered by various other signals,
can perform a variety of measurements summarized in which are determined by the mode the SMT is currently
Table 29-1. in.
The SMTxCPR registers can also be updated with the
29.1.1 CLOCK SOURCES current value of the SMTxTMR value by setting the
Clock sources available to the SMT include: CPRUP bit in the SMTxSTAT register.
• FOSC
29.3 Halt Operation
• FOSC/4
• HFINTOSC 16 MHz The counter can be prevented from rolling-over using
• LFINTOSC the STP bit in the SMTxCON0 register. When halting is
enabled, the period match interrupt persists until the
• MFINTOSC 31.25 kHz
SMTxTMR is reset (either by a manual reset,
The SMT clock source is selected by configuring the Section29.2.1 “Time Base”) or by clearing the
CSEL<2:0> bits in the SMTxCLK register. The clock SMTxGO bit of the SMTxCON1 register and writing the
source can also be prescaled using the PS<1:0> bits of SMTxTMR values in software.
the SMTxCON0 register. The prescaled clock source is
used to clock both the counter and any synchronization 29.4 Polarity Control
logic used by the module.
The three input signals for the SMT have polarity
29.1.2 PERIOD MATCH INTERRUPT control to determine whether or not they are active
Similar to other timers, the SMT triggers an interrupt high/positive edge or active low/negative edge signals.
when SMTxTMR rolls over to ‘0’. This happens when The following bits apply to Polarity Control:
SMTxTMR = SMTxPR, regardless of mode. Hence, in
• WSEL bit (Window Polarity)
any mode that relies on an external signal or a window
to reset the timer, proper operation requires that • SSEL bit (Signal Polarity)
SMTxPR be set to a period larger than that of the • CSEL bit (Clock Polarity)
expected signal or window. These bits are located in the SMTxCON0 register.
29.2 Basic Timer Function Registers 29.5 Status Information

The SMTxTMR time base and the The SMT provides input status information for the user
SMTxCPW/SMTxPR/SMTxCPR buffer registers serve without requiring the need to deal with the polarity of
several functions and can be manually updated using the incoming signals.
software.
29.5.1 WINDOW STATUS
29.2.1 TIME BASE
Window status is determined by the WS bit of the
The SMTxTMR is the 24-bit counter that is the center of SMTxSTAT register. This bit is only used in Windowed
the SMT. It is used as the basic counter/timer for Measure, Gated Counter and Gated Window Measure
measurement in each of the modes of the SMT. It can be modes, and is only valid when TS = 1, and will be
reset to a value of 24'h00_0000 by setting the RST bit of delayed in time by synchronizer delays in non-Counter
the SMTxSTAT register. It can be written to and read modes.
from software, but it is not guarded for atomic access,
therefore reads and writes to the SMTxTMR should only 29.5.2 SIGNAL STATUS
be made when the GO = 0, or the software should have
Signal status is determined by the AS bit of the
other measures to ensure integrity of SMTxTMR
SMTxSTAT register. This bit is used in all modes except
reads/writes.
Window Measure, Time of Flight and Capture modes,
and is only valid when TS = 1, and will be delayed in
29.2.2 PULSE WIDTH LATCH REGISTERS
time by synchronizer delays in non-Counter modes.
The SMTxCPW registers are the 24-bit SMT pulse
width latch. They are used to latch in the value of the 29.5.3 GO STATUS
SMTxTMR when triggered by various signals, which
Timer run status is determined by the TS bit of the
are determined by the mode the SMT is currently in.
SMTxSTAT register, and will be delayed in time by
The SMTxCPW registers can also be updated with the
synchronizer delays in non-Counter modes.
current value of the SMTxTMR value by setting the
CPWUP bit of the SMTxSTAT register.

PIC16(L)F1615/9
29.6 Modes of Operation 29.6.1 TIMER MODE
The modes of operation are summarized in Table 29-1. Timer mode is the simplest mode of operation where
The following sections provide detailed descriptions, the SMTxTMR is used as a 16/24-bit timer. No data
examples of how the modes can be used. Note that all acquisition takes place in this mode. The timer
waveforms assume WPOL/SPOL/CPOL = 0. When increments as long as the SMTxGO bit has been set by
WPOL/SPOL/CPOL = 1, all SMTSIGx, SMTWINx and software. No SMT window or SMT signal events affect
SMT clock signals will have a polarity opposite to that the SMTxGO bit. Everything is synchronized to the
indicated. For all modes, the REPEAT bit controls SMT clock source. When the timer experiences a
whether the acquisition is repeated or single. When period match (SMTxTMR = SMTxPR), SMTxTMR is
REPEAT = 0 (Single Acquisition mode), the timer will reset and the period match interrupt trips. See
stop incrementing and the SMTxGO bit will be reset Figure 29-3.
upon the completion of an acquisition. Otherwise, the
timer will continue and allow for continued acquisitions
to overwrite the previous ones until the timer is stopped
in software.
TABLE 29-1: MODES OF OPERATION

Synchronous
MODE Mode of Operation Reference
Operation
0000 Timer Yes Section29.6.1 “Timer Mode”
0001 Gated Timer Yes Section29.6.2 “Gated Timer Mode”
0010 Period and Duty Cycle Acquisition Yes Section29.6.3 “Period and Duty-Cycle Mode”
0011 High and Low Time Measurement Yes Section29.6.4 “High and Low Measure Mode”
0100 Windowed Measurement Yes Section29.6.5 “Windowed Measure Mode”
0101 Gated Windowed Measurement Yes Section29.6.6 “Gated Window Measure Mode”
0110 Time of Flight Yes Section29.6.7 “Time of Flight Measure Mode”
0111 Capture Yes Section29.6.8 “Capture Mode”
1000 Counter No Section29.6.9 “Counter Mode”
1001 Gated Counter No Section29.6.10 “Gated Counter Mode”
1010 Windowed Counter No Section29.6.11 “Windowed Counter Mode”
1011 - 1111 Reserved — —

FIGURE 29-3: TIMER MODE TIMING DIAGRAM
Rev. 10-000 174A

12/19/201 3
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxPR 11
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9
SMTxIF
PIC16(L)F1615/9
DS40001770D-page 395
PIC16(L)F1615/9
29.6.2 GATED TIMER MODE
Gated Timer mode uses the SMTSIGx input to control
whether or not the SMTxTMR will increment. Upon a
falling edge of the external signal, the SMTxCPW
register will update to the current value of the
SMTxTMR. Example waveforms for both repeated and
single acquisitions are provided in Figure 29-4 and
Figure 29-5.

FIGURE 29-4: GATED TIMER MODE REPEAT ACQUISITION TIMING DIAGRAM
Rev. 10-000 176A

12/19/201 3
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxPR 0xFFFFFF
SMTxTMR 0 1 2 3 4 5 6 7
SMTxCPW 5 7
SMTxPWAIF
PIC16(L)F1615/9
DS40001770D-page 397
FIGURE 29-5: GATED TIMER MODE SINGLE ACQUISITION TIMING DIAGRAM
Rev. 10-000 175A

12/19/201 3
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxPR 0xFFFFFF
SMTxTMR 0 1 2 3 4 5
SMTxCPW 5
SMTxPWAIF
PIC16(L)F1615/9
DS40001770D-page 398
PIC16(L)F1615/9
29.6.3 PERIOD AND DUTY-CYCLE MODE
In Duty-Cycle mode, either the duty cycle or period
(depending on polarity) of the SMTx_signal can be
acquired relative to the SMT clock. The CPW register is
updated on a falling edge of the signal, and the CPR
register is updated on a rising edge of the signal, along
with the SMTxTMR resetting to 0x0001. In addition, the
SMTxGO bit is reset on a rising edge when the SMT is
in Single Acquisition mode. See Figure 29-6 and
Figure 29-7.

FIGURE 29-6: PERIOD AND DUTY-CYCLE REPEAT ACQUISITION MODE TIMING DIAGRAM
Rev. 10-000 177A

12/19/201 3
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 1 2 3 4 5
SMTxCPW 5 2
SMTxCPR 11
SMTxPWAIF
SMTxPRAIF
PIC16(L)F1615/9
DS40001770D-page 400
FIGURE 29-7: PERIOD AND DUTY-CYCLE SINGLE ACQUISITION TIMING DIAGRAM
Rev. 10-000 178A

12/19/201 3
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11
SMTxCPW 5
SMTxCPR 11
SMTxPWAIF
SMTxPRAIF
PIC16(L)F1615/9
DS40001770D-page 401
PIC16(L)F1615/9
29.6.4 HIGH AND LOW MEASURE MODE
This mode measures the high and low pulse time of the
SMTSIGx relative to the SMT clock. It begins
incrementing the SMTxTMR on a rising edge on the
SMTSIGx input, then updates the SMTxCPW register
with the value and resets the SMTxTMR on a falling
edge, starting to increment again. Upon observing
another rising edge, it updates the SMTxCPR register
with its current value and once again resets the
SMTxTMR value and begins incrementing again. See
Figure 29-8 and Figure 29-9.

FIGURE 29-8: HIGH AND LOW MEASURE MODE REPEAT ACQUISITION TIMING DIAGRAM
Rev. 10-000 180A

12/19/201 3
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 1 2 3 4 5 6 1 2 1 2 3
SMTxCPW 5 2
SMTxCPR 6
SMTxPWAIF
SMTxPRAIF
PIC16(L)F1615/9
DS40001770D-page 403
FIGURE 29-9: HIGH AND LOW MEASURE MODE SINGLE ACQUISITION TIMING DIAGRAM
Rev. 10-000 179A

12/19/201 3
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 1 2 3 4 5 6
SMTxCPW 5
SMTxCPR 6
SMTxPWAIF
SMTxPRAIF
PIC16(L)F1615/9
DS40001770D-page 404
PIC16(L)F1615/9
29.6.5 WINDOWED MEASURE MODE
This mode measures the window duration of the
SMTWINx input of the SMT. It begins incrementing the
timer on a rising edge of the SMTWINx input and
updates the SMTxCPR register with the value of the
timer and resets the timer on a second rising edge. See

FIGURE 29-10: WINDOWED MEASURE MODE REPEAT ACQUISITION TIMING DIAGRAM
Rev. 10-000 182A

12/19/201 3
SMTxWIN
SMTxWIN_sync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 1 2 3 4
SMTxCPR 12 8
SMTxPRAIF
PIC16(L)F1615/9
DS40001770D-page 406
FIGURE 29-11: WINDOWED MEASURE MODE SINGLE ACQUISITION TIMING DIAGRAM
Rev. 10-000 181A

12/19/201 3
SMTxWIN
SMTxWIN_sync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12
SMTxCPR 12
SMTxPRAIF
PIC16(L)F1615/9
DS40001770D-page 407
PIC16(L)F1615/9
29.6.6 GATED WINDOW MEASURE MODE
This mode measures the duty cycle of the SMTx_signal
input over a known input window. It does so by
incrementing the timer on each pulse of the clock signal
while the SMTx_signal input is high, updating the
SMTxCPR register and resetting the timer on every
rising edge of the SMTWINx input after the first. See

FIGURE 29-12: GATED WINDOWED MEASURE MODE REPEAT ACQUISITION TIMING DIAGRAM
Rev. 10-000 184A

12/19/201 3
SMTxWIN
SMTxWIN_sync
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 6 0 1 2 3 0
SMTxCPR 6 3
SMTxPRAIF
PIC16(L)F1615/9
DS40001770D-page 409
FIGURE 29-13: GATED WINDOWED MEASURE MODE SINGLE ACQUISITION TIMING DIAGRAMS
Rev. 10-000 183A

12/19/201 3
SMTxWIN
SMTxWIN_sync
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 6
SMTxCPR 6
SMTxPRAIF
PIC16(L)F1615/9
DS40001770D-page 410
PIC16(L)F1615/9
29.6.7 TIME OF FLIGHT MEASURE MODE
This mode measures the time interval between a rising
edge on the SMTWINx input and a rising edge on the
SMTx_signal input, beginning to increment the timer
upon observing a rising edge on the SMTWINx input,
while updating the SMTxCPR register and resetting the
timer upon observing a rising edge on the SMTx_signal
input. In the event of two SMTWINx rising edges
without an SMTx_signal rising edge, it will update the
SMTxCPW register with the current value of the timer
and reset the timer value. See Figure 29-14 and
Figure 29-15.

FIGURE 29-14: TIME OF FLIGHT MODE REPEAT ACQUISITION TIMING DIAGRAM
Rev. 10-000186A
4/22/2016
SMTxWIN
SMTxWIN_sync
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2
SMTxCPW 13
SMTxCPR 4
SMTxPWAIF
PIC16(L)F1615/9
SMTxPRAIF
DS40001770D-page 412
FIGURE 29-15: TIME OF FLIGHT MODE SINGLE ACQUISITION TIMING DIAGRAM
Rev. 10-000185A
4/26/2016
SMTxWIN
SMTxWIN_sync
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5
SMTxCPW
SMTxCPR 4
SMTxPWAIF
PIC16(L)F1615/9
SMTxPRAIF
DS40001770D-page 413
PIC16(L)F1615/9
29.6.8 CAPTURE MODE
This mode captures the Timer value based on a rising
or falling edge on the SMTWINx input and triggers an
interrupt. This mimics the capture feature of a CCP
module. The timer begins incrementing upon the
SMTxGO bit being set, and updates the value of the
SMTxCPR register on each rising edge of SMTWINx,
and updates the value of the CPW register on each
falling edge of the SMTWINx. The timer is not reset by
any hardware conditions in this mode and must be
reset by software, if desired. See Figure 29-16 and
Figure 29-17.

FIGURE 29-16: CAPTURE MODE REPEAT ACQUISITION TIMING DIAGRAM
Rev. 10-000 188A

12/19/201 3
SMTxWIN
SMTxWIN_sync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SMTxCPW 3 19 32
SMTxCPR 2 18 31
SMTxPWAIF
SMTxPRAIF
PIC16(L)F1615/9
DS40001770D-page 415
FIGURE 29-17: CAPTURE MODE SINGLE ACQUISITION TIMING DIAGRAM
Rev. 10-000 187A

12/19/201 3
SMTxWIN
SMTxWIN_sync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3
SMTxCPW 3
SMTxCPR 2
SMTxPWAIF
SMTxPRAIF
PIC16(L)F1615/9
DS40001770D-page 416
PIC16(L)F1615/9
29.6.9 COUNTER MODE
This mode increments the timer on each pulse of the
SMTx_signal input. This mode is asynchronous to the
SMT clock and uses the SMTx_signal as a time source.
The SMTxCPW register will be updated with the
current SMTxTMR value on the falling edge of the
SMTxWIN input. See Figure 29-18.

FIGURE 29-18: COUNTER MODE TIMING DIAGRAM
Rev. 10-000189A
4/12/2016
SMTxWIN
SMTx_signal
SMTxEN
SMTxGO
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
SMTxCPW 12 25
PIC16(L)F1615/9
DS40001770D-page 418
PIC16(L)F1615/9
29.6.10 GATED COUNTER MODE
This mode counts pulses on the SMTx_signal input,
gated by the SMTxWIN input. It begins incrementing
the timer upon seeing a rising edge of the SMTxWIN
input and updates the SMTxCPW register upon a fall-
ing edge on the SMTxWIN input. See Figure 29-19
and Figure 29-20.

FIGURE 29-19: GATED COUNTER MODE REPEAT ACQUISITION TIMING DIAGRAM
Rev. 10-000190A
12/18/2013
SMTxWIN
SMTx_signal
SMTxEN
SMTxGO
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 13
SMTxCPW 8 13
SMTxPWAIF
FIGURE 29-20: GATED COUNTER MODE SINGLE ACQUISITION TIMING DIAGRAM

Rev. 10-000191A
12/18/2013
SMTxWIN
SMTx_signal
PIC16(L)F1615/9
SMTxEN
SMTxGO
SMTxTMR 0 1 2 3 4 5 6 7 8
DS40001770D-page 420
SMTxCPW 8
SMTxPWAIF
PIC16(L)F1615/9
29.6.11 WINDOWED COUNTER MODE
This mode counts pulses on the SMTx_signal input,
within a window dictated by the SMTxWIN input. It
begins counting upon seeing a rising edge of the
SMTxWIN input, updates the SMTxCPW register on a
falling edge of the SMTxWIN input, and updates the
SMTxCPR register on each rising edge of the
SMTxWIN input beyond the first. See Figure 29-21 and
Figure 29-22.

FIGURE 29-21: WINDOWED COUNTER MODE REPEAT ACQUISITION TIMING DIAGRAM
SMTxWIN
SMTx_signal
SMTxEN
SMTxGO
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5
SMTxCPW 9 5
SMTxCPR 16
SMTxPWAIF
SMTxPRAIF
FIGURE 29-22: WINDOWED COUNTER MODE SINGLE ACQUISITION TIMING DIAGRAM
SMTxWIN
SMTx_signal
SMTxEN
PIC16(L)F1615/9
SMTxGO
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SMTxCPW 9
DS40001770D-page 422
SMTxCPR 16
SMTxPWAIF
SMTxPRAIF
PIC16(L)F1615/9
29.7 Interrupts
The SMT can trigger an interrupt under three different
conditions:
• PW Acquisition Complete
• PR Acquisition Complete
• Counter Period Match
The interrupts are controlled by the PIR and PIE
registers of the device.
29.7.1 PW AND PR ACQUISITION

INTERRUPTS
The SMT can trigger interrupts whenever it updates the
SMTxCPW and SMTxCPR registers, the circum-
stances for which are dependent on the SMT mode,
and are discussed in each mode’s specific section. The
SMTxCPW interrupt is controlled by SMTxPWAIF and
SMTxPWAIE bits in registers PIR4 and PIE4, respec-
tively. The SMTxCPR interrupt is controlled by the
SMTxPRAIF and SMTxPRAIE bits, also located in
registers PIR4 and PIE4, respectively.
In synchronous SMT modes, the interrupt trigger is
synchronized to the SMTxCLK. In Asynchronous
modes, the interrupt trigger is asynchronous. In either
mode, once triggered, the interrupt will be synchro-
nized to the CPU clock.
29.7.2 COUNTER PERIOD MATCH

INTERRUPT
As described in Section 29.1.2 “Period Match
interrupt”, the SMT will also interrupt upon SMTxTMR,
matching SMTxPR with its period match limit functionality
described in Section29.3 “Halt Operation”. The period
match interrupt is controlled by SMTxIF and SMTxIE,
located in registers PIR4 and PIE4, respectively.

PIC16(L)F1615/9
29.8 Register Definitions: SMT Control
Long bit name prefixes for the Signal Measurement
Timer peripherals are shown in Table 29-2. Refer to
Section 1.1 “Register and Bit Naming Conven-
tions” for more information.
TABLE 29-2:
SMT1 SMT1
SMT2 SMT2
REGISTER 29-1: SMTxCON0: SMT CONTROL REGISTER 0

R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
(1)
EN — STP WPOL SPOL CPOL SMTxPS<1:0>
bit 7 bit 0
Legend:
bit 7 EN: SMT Enable bit(1)

1 = SMT is enabled
0 = SMT is disabled; internal states are reset, clock requests are disabled
bit 5 STP: SMT Counter Halt Enable bit
When SMTxTMR = SMTxPR:
1 = Counter remains SMTxPR; period match interrupt occurs when clocked
0 = Counter resets to 24'h000000; period match interrupt occurs when clocked
bit 4 WPOL: SMTxWIN Input Polarity Control bit
1 = SMTxWIN signal is active-low/falling edge enabled
0 = SMTxWIN signal is active-high/rising edge enabled
bit 3 SPOL: SMTxSIG Input Polarity Control bit
1 = SMTx_signal is active-low/falling edge enabled
0 = SMTx_signal is active-high/rising edge enabled
bit 2 CPOL: SMT Clock Input Polarity Control bit
1 = SMTxTMR increments on the falling edge of the selected clock signal
0 = SMTxTMR increments on the rising edge of the selected clock signal
bit 1-0 SMTxPS<1:0>: SMT Prescale Select bits
11 = Prescaler = 1:8
Note 1: Setting EN to ‘0‘ does not affect the register contents.

PIC16(L)F1615/9
REGISTER 29-2: SMTxCON1: SMT CONTROL REGISTER 1

R/W/HC-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
SMTxGO REPEAT — — MODE<3:0>
bit 7 bit 0
Legend:
bit 7 SMTxGO: SMT GO Data Acquisition bit

1 = Incrementing, acquiring data is enabled
0 = Incrementing, acquiring data is disabled
bit 6 REPEAT: SMT Repeat Acquisition Enable bit
1 = Repeat Data Acquisition mode is enabled
0 = Single Acquisition mode is enabled
bit 3-0 MODE<3:0> SMT Operation Mode Select bits
1111 = Reserved
•
•
•
1011 = Reserved
1010 = Windowed counter
1001 = Gated counter
1000 = Counter
0111 = Capture
0110 = Time of flight
0101 = Gated windowed measure
0100 = Windowed measure
0011 = High and low time measurement
0010 = Period and Duty-Cycle Acquisition
0001 = Gated Timer
0000 = Timer

PIC16(L)F1615/9
REGISTER 29-3: SMTxSTAT: SMT STATUS REGISTER

R/W/HC-0/0 R/W/HC-0/0 R/W/HC-0/0 U-0 U-0 R-0/0 R-0/0 R-0/0
CPRUP CPWUP RST — — TS WS AS
bit 7 bit 0
Legend:
bit 7 CPRUP: SMT Manual Period Buffer Update bit

1 = Request update to SMTxCPRx registers
0 = SMTxCPRx registers update is complete
bit 6 CPWUP: SMT Manual Pulse Width Buffer Update bit
1 = Request update to SMTxCPW registers
0 = SMTxCPW registers update is complete
bit 5 RST: SMT Manual Timer Reset bit
1 = Request Reset to SMTxTMR registers
0 = SMTxTMR registers update is complete
bit 2 TS: SMT GO Value Status bit
1 = SMT timer is incrementing
0 = SMT timer is not incrementing
bit 1 WS: SMTxWIN Value Status bit
1 = SMT window is open
0 = SMT window is closed
bit 0 AS: SMT_signal Value Status bit
1 = SMT acquisition is in progress
0 = SMT acquisition is not in progress

PIC16(L)F1615/9
REGISTER 29-4: SMTxCLK: SMT CLOCK SELECTION REGISTER

U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — — CSEL<2:0>
bit 7 bit 0
Legend:

bit 2-0 CSEL<2:0>: SMT Clock Selection bits
111 = Reserved
110 = AT1_perclk
101 = MFINTOSC
100 = MFINTOSC/16
011 = LFINTOSC
010 = HFINTOSC 16 MHz
001 = FOSC/4
000 = FOSC

PIC16(L)F1615/9
REGISTER 29-5: SMT1WIN: SMT1 WINDOW INPUT SELECT REGISTER

U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — WSEL<4:0>
bit 7 bit 0
Legend:

bit 4-0 WSEL<4:0>: SMT1 Window Selection bits
11111 = Reserved
•
•
•
11000 = Reserved
10111 = MFINTOSC/16
10110 = AT1_perclk
10101 = LFINTOSC
10100 = PWM4_out
10011 = PWM3_out
10010 = SMT2_match
10001 = Reserved
01100 = LC4_out
01011 = LC3_out
01010 = LC2_out
01001 = LC1_out
00101 = ZCD1_out
00100 = CCP2_out
00011 = CCP1_out
00010 = C2OUT_sync
00001 = C1OUT_sync
00000 = SMTWINx pin

PIC16(L)F1615/9
REGISTER 29-6: SMT2WIN: SMT2 WINDOW INPUT SELECT REGISTER

U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — WSEL<4:0>
bit 7 bit 0
Legend:

bit 4-0 WSEL<4:0>: SMT2 Window Selection bits
11111 = Reserved
•
•
•
11000 = Reserved
10111 = MFINTOSC/16
10110 = AT1_perclk
10101 = LFINTOSC
10100 = PWM4_out
10011 = PWM3_out
10010 = Reserved
10001 = SMT1_match
01100 = LC4_out
01011 = LC3_out
01010 = LC2_out
01001 = LC1_out
00101 = ZCD1_out
00100 = CCP2_out
00011 = CCP1_out
00010 = C2OUT_sync
00001 = C1OUT_sync
00000 = SMTWINx pin

PIC16(L)F1615/9
REGISTER 29-7: SMT1SIG: SMT1 SIGNAL INPUT SELECT REGISTER

U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — SSEL<4:0>
bit 7 bit 0
Legend:

bit 4-0 SSEL<4:0>: SMT1 Signal Selection bits
11111 = Reserved
•
•
•
10101 = Reserved
10100 = PWM4_out
10011 = PWM3_out
10010 = CCP2_out
10001 = CCP1_out
01111 = SMT2_match
01110 = Reserved
01010 = LC4_out
01001 = LC3_out
01000 = LC2_out
00111 = LC1_out
00011 = ZCD1_out
00010 = C2OUT_sync
00001 = C1OUT_sync
00000 = SMTxSIG pin

PIC16(L)F1615/9
REGISTER 29-8: SMT2SIG: SMT2 SIGNAL INPUT SELECT REGISTER

U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — SSEL<4:0>
bit 7 bit 0
Legend:

bit 4-0 SSEL<4:0>: SMT2 Signal Selection bits
11111 = Reserved
•
•
•
10101 = Reserved
10100 = PWM4_out
10011 = PWM3_out
10010 = CCP2_out
10001 = CCP1_out
01111 = Reserved
01110 = SMT1_match
01010 = LC4_out
01001 = LC3_out
01000 = LC2_out
00111 = LC1_out
00011 = ZCD1_out
00010 = C2OUT_sync
00001 = C1OUT_sync
00000 = SMTxSIG pin

PIC16(L)F1615/9
REGISTER 29-9: SMTxTMRL: SMT TIMER REGISTER – LOW BYTE

SMTxTMR<7:0>
bit 7 bit 0
Legend:
bit 7-0 SMTxTMR<7:0>: Significant bits of the SMT Counter – Low Byte
REGISTER 29-10: SMTxTMRH: SMT TIMER REGISTER – HIGH BYTE

SMTxTMR<15:8>
bit 7 bit 0
Legend:
bit 7-0 SMTxTMR<15:8>: Significant bits of the SMT Counter – High Byte
REGISTER 29-11: SMTxTMRU: SMT TIMER REGISTER – UPPER BYTE

SMTxTMR<23:16>
bit 7 bit 0
Legend:
bit 7-0 SMTxTMR<23:16>: Significant bits of the SMT Counter – Upper Byte

PIC16(L)F1615/9
REGISTER 29-12: SMTxCPRL: SMT CAPTURED PERIOD REGISTER – LOW BYTE

R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x
SMTxCPR<7:0>
bit 7 bit 0
Legend:
bit 7-0 SMTxCPR<7:0>: Significant bits of the SMT Period Latch – Low Byte
REGISTER 29-13: SMTxCPRH: SMT CAPTURED PERIOD REGISTER – HIGH BYTE

SMTxCPR<15:8>
bit 7 bit 0
Legend:
bit 7-0 SMTxCPR<15:8>: Significant bits of the SMT Period Latch – High Byte
REGISTER 29-14: SMTxCPRU: SMT CAPTURED PERIOD REGISTER – UPPER BYTE

SMTxCPR<23:16>
bit 7 bit 0
Legend:
bit 7-0 SMTxCPR<23:16>: Significant bits of the SMT Period Latch – Upper Byte

PIC16(L)F1615/9
REGISTER 29-15: SMTxCPWL: SMT CAPTURED PULSE WIDTH REGISTER – LOW BYTE
SMTxCPW<7:0>
bit 7 bit 0
Legend:
bit 7-0 SMTxCPW<7:0>: Significant bits of the SMT PW Latch – Low Byte
REGISTER 29-16: SMTxCPWH: SMT CAPTURED PULSE WIDTH REGISTER – HIGH BYTE
SMTxCPW<15:8>
bit 7 bit 0
Legend:
bit 7-0 SMTxCPW<15:8>: Significant bits of the SMT PW Latch – High Byte
REGISTER 29-17: SMTxCPWU: SMT CAPTURED PULSE WIDTH REGISTER – UPPER BYTE
SMTxCPW<23:16>
bit 7 bit 0
Legend:
bit 7-0 SMTxCPW<23:16>: Significant bits of the SMT PW Latch – Upper Byte

PIC16(L)F1615/9
REGISTER 29-18: SMTxPRL: SMT PERIOD REGISTER – LOW BYTE

R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1
SMTxPR<7:0>
bit 7 bit 0
Legend:
bit 7-0 SMTxPR<7:0>: Significant bits of the SMT Timer Value for Period Match – Low Byte
REGISTER 29-19: SMTxPRH: SMT PERIOD REGISTER – HIGH BYTE

SMTxPR<15:8>
bit 7 bit 0
Legend:
bit 7-0 SMTxPR<15:8>: Significant bits of the SMT Timer Value for Period Match – High Byte
REGISTER 29-20: SMTxPRU: SMT PERIOD REGISTER – UPPER BYTE

SMTxPR<23:16>
bit 7 bit 0
Legend:
bit 7-0 SMTxPR<23:16>: Significant bits of the SMT Timer Value for Period Match – Upper Byte

PIC16(L)F1615/9
TABLE 29-3: SUMMARY OF REGISTERS ASSOCIATED WITH SMTx
Register on
Page
PIE4 SCANIE CRCIE SMT2PWAIE SMT2PRAIE SMT2IE SMT1PWAIE SMT1PRAIE SMT1IE 101
SMT1CON0 EN — STP WPOL SPOL CPOL SMT1PS<1:0> 424
SMT1CON1 SMT1GO REPEAT — — MODE<3:0> 425
SMT1CPRH SMT1CPR<15:8> 433
SMT1CPRL SMT1CPR<7:0> 433
SMT1CPRU SMT1CPR<23:16> 433
SMT1CPWH SMT1CPW<15:8> 434
SMT1CPWL SMT1CPW<7:0> 434
SMT1CPWU SMT1CPW<23:16> 434
SMT1PRH SMT1PR<15:8> 435
SMT1PRL SMT1PR<7:0> 435
SMT1PRU SMT1PR<23:16> 435
SMT1SIG — — — SSEL<4:0> 430
SMT1STAT CPRUP CPWUP RST — — TS WS AS 426
SMT1TMRH SMT1TMR<15:8> 432
SMT1TMRL SMT1TMR<7:0> 432
SMT1TMRU SMT1TMR<23:16> 432
SMT1WIN — — — WSEL<4:0> 428
SMT2CLK — — — — — CSEL<2:0> 427
SMT2CON0 EN — STP WPOL SPOL CPOL SMT2PS<1:0> 424
SMT2CON1 SMT2GO REPEAT — — MODE<3:0> 425
SMT2CPRH SMT2CPR<15:8> 433
SMT2CPRL SMT2CPR<7:0> 433
SMT2CPRU SMT2CPR<23:16> 433
SMT2CPWH SMT2CPW<15:8> 434
SMT2CPWL SMT2CPW<7:0> 434
SMT2CPWU SMT2CPW<23:16> 434
SMT2PRH SMT2PR<15:8> 435
SMT2PRL SMT2PR<7:0> 435
SMT2PRU SMT2PR<23:16> 435
SMT2SIG — — — — — SSEL<2:0> 430
SMT2STAT CPRUP CPWUP RST — — TS WS AS 426
SMT2TMRH SMT2TMR<15:8> 432
SMT2TMRL SMT2TMR<7:0> 432
SMT2TMRU SMT2TMR<23:16> 432
SMT2WIN — — — WSEL<4:0> 427
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are not used for SMTx module.

PIC16(L)F1615/9
30.0 CONFIGURABLE LOGIC CELL Refer to Figure 30-1 for a simplified diagram showing
signal flow through the CLCx.
(CLC)
Possible configurations include:
The Configurable Logic Cell (CLCx) provides program-
mable logic that operates outside the speed limitations • Combinatorial Logic
of software execution. The logic cell takes up to 16 - AND
input signals, and through the use of configurable - NAND
gates, reduces the 16 inputs to four logic lines that drive - AND-OR
one of eight selectable single-output logic functions. - AND-OR-INVERT
Input sources are a combination of the following: - OR-XOR
• I/O pins - OR-XNOR
• Internal clocks • Latches
• Peripherals - S-R
• Register bits - Clocked D with Set and Reset
The output can be directed internally to peripherals and - Transparent D with Set and Reset
to an output pin. - Clocked J-K with Reset
FIGURE 30-1: CONFIGURABLE LOGIC CELL BLOCK DIAGRAM
Rev. 10-000025E
7/7/2014
LCxOUT
D Q
MLCxOUT
Q1
LCx_in[0]
LCx_in[1] LCx_out
to Peripherals
LCx_in[2]
Input Data Selection Gates(1)
. g1
EN
CLCxPPS
. g2
g3
Logic
Function
(2)
q
PPS CLCx
. g4
POL TRIS
LCx_in[38] MODE<2:0> Interrupt

LCx_in[39] det
LCx_in[40]
INTP
set bit
INTN CLCxIF
Interrupt
det

2: See Figure 30-3.

PIC16(L)F1615/9
30.1 CLCx Setup
TABLE 30-1: CLCx DATA INPUT
Programming the CLCx module is performed by config-
uring the four stages in the logic signal flow. The four SELECTION
stages are: Data Input CLCxSELy CLC Input Signal
• Data selection LCx_in[0] 000000 CLCIN0
• Data gating LCx_in[1] 000001 CLCIN1
• Logic function selection
LCx_in[2] 000010 CLCIN2
• Output polarity
LCx_in[3] 000011 CLCIN3
Each stage is setup at run time by writing to the corre-
LCx_in[4] 000100 LC1_out
sponding CLCx Special Function Registers. This has
the added advantage of permitting logic reconfiguration LCx_in[5] 000101 LC2_out
on-the-fly during program execution. LCx_in[6] 000110 LC3_out
30.1.1 DATA SELECTION LCx_in[7] 000111 LC4_out

LCx_in[8] 001000 C1OUT_sync
There are 41 signals available as inputs to the configu-
rable logic. Four 41 input multiplexers are used to LCx_in[9] 001001 C2OUT_sync
select the inputs to pass on to the next stage. This LCx_in[10] 001010 CWGOUTA
allows for any of the possible input signals to be used
LCx_in[11] 001011 CWGOUTB
as any of the four inputs to the CLC module.
LCx_in[12] 001100 CCP1_out
Data selection is through four multiplexers as indicated
on the left side of Figure 30-2. Data inputs in the figure LCx_in[13] 001101 CCP2_out
are identified by a generic numbered input name. LCx_in[14] 001110 PWM3_out
Table 30-1 correlates the generic input name to the LCx_in[15] 001111 PWM4_out
actual signal for each CLC module. The column labeled LCx_in[16] 010000 AT1_cmp1
CLCxSELy refers to the value of any of the four registers
associated with the four multiplexers, CLCxSEL0 LCx_in[17] 010001 AT1_cmp2
through CLCxSEL3. LCx_in[18] 010010 AT1_cmp3
Data inputs for each multiplexer are selected with their LCx_in[19] 010011 SMT1_match
respective CLCxSELy registers. LCx_in[20] 010100 SMT2_match
Note: Data selections are undefined at power-up. LCx_in[21] 010101 ZCD1_output
LCx_in[22] 010110 TMR0_overflow
LCx_in[24] 011000 TMR2_postscaled
LCx_in[29] 011101 IOC_interrupt
LCx_in[30] 011110 ADC_rc
LCx_in[31] 011111 LFINTOSC
LCx_in[32] 100000 HFINTOSC
LCx_in[33] 100001 FOSC
LCx_in[34] 100010 AT1_missedpulse
LCx_in[35] 100011 AT1_perclk
LCx_in[36] 100100 AT1_phsclk
LCx_in[37] 100101 TX
LCx_in[38] 100110 RX
LCx_in[39] 100111 SCK
LCx_in[40] 101000 SDO

PIC16(L)F1615/9
30.2 Data Gating Data gating is indicated in the right side of Figure 30-2.
Only one gate is shown in detail. The remaining three
Outputs from the input multiplexers are directed to the gates are configured identically with the exception that
desired logic function input through the data gating the data enables correspond to the enables for that
stage. Each data gate can direct any combination of the gate.
four selected inputs.
Note: Data gating is undefined at power-up. 30.2.1 LOGIC FUNCTION
There are eight available logic functions including:
The gate stage is more than just signal direction. The
gate can be configured to direct each input signal as • AND-OR
inverted or non-inverted data. Directed signals are • OR-XOR
ANDed together in each gate. The output of each gate • AND
can be inverted before going on to the logic function • S-R Latch
stage.
• D Flip-Flop with Set and Reset
The gating is in essence a 1-to-4 input AND/NAND/OR/ • D Flip-Flop with Reset
NOR gate. When every input is inverted and the output
• J-K Flip-Flop with Reset
is inverted, the gate is an OR of all enabled data inputs.
When the inputs and output are not inverted, the gate • Transparent Latch with Set and Reset
is an AND or all enabled inputs. Logic functions are shown in Figure 30-3. Each logic
function has four inputs and one output. The four inputs
Table 30-2 summarizes the basic logic that can be
are the four data gate outputs of the previous stage.
obtained in gate 1 by using the gate logic select bits.
The output is fed to the inversion stage and from there
The table shows the logic of four input variables, but to other peripherals, an output pin, and back to the
each gate can be configured to use less than four. If CLCx itself.
no inputs are selected, the output will be zero or one,
depending on the gate output polarity bit. 30.2.2 OUTPUT POLARITY
The last stage in the configurable logic cell is the output
TABLE 30-2: DATA GATING LOGIC
polarity. Setting the LCxPOL bit of the CLCxCON reg-
CLCxGLS0 LCxG1POL Gate Logic ister inverts the output signal from the logic stage.
Changing the polarity while the interrupts are enabled
0x55 1 AND will cause an interrupt for the resulting output transition.
0x55 0 NAND
0xAA 1 NOR
0xAA 0 OR
0x00 0 Logic 0
0x00 1 Logic 1
It is possible (but not recommended) to select both the

true and negated values of an input. When this is done,
the gate output is zero, regardless of the other inputs,
but may emit logic glitches (transient-induced pulses).
If the output of the channel must be zero or one, the
recommended method is to set all gate bits to zero and
use the gate polarity bit to set the desired level.
Data gating is configured with the logic gate select
registers as follows:
• Gate 1: CLCxGLS0 (Register 30-6)
Register number suffixes are different than the gate
numbers because other variations of this module have
multiple gate selections in the same register.

PIC16(L)F1615/9
30.2.3 CLCx SETUP STEPS 30.3 CLCx Interrupts
The following steps should be followed when setting up An interrupt will be generated upon a change in the
the CLCx: output value of the CLCx when the appropriate interrupt
• Disable CLCx by clearing the LCxEN bit. enables are set. A rising edge detector and a falling
• Select desired inputs using CLCxSEL0, edge detector are present in each CLC for this purpose.
CLCxSEL1, CLCxSEL2 and CLCxSEL3 registers The CLCxIF bit of the associated PIR registers will be
(See Table 30-1). set when either edge detector is triggered and its asso-
• Clear any associated ANSEL bits. ciated enable bit is set. The LCxINTP enables rising
• Set all TRIS bits associated with inputs. edge interrupts and the LCxINTN bit enables falling
• Clear all TRIS bits associated with outputs. edge interrupts. Both are located in the CLCxCON
register.
• Enable the chosen inputs through the four gates
using CLCxGLS0, CLCxGLS1, CLCxGLS2, and To fully enable the interrupt, set the following bits:
CLCxGLS3 registers. • LCxON bit of the CLCxCON register
• Select the gate output polarities with the • CLCxIE bit of the associated PIE registers
LCxPOLy bits of the CLCxPOL register.
• LCxINTP bit of the CLCxCON register (for a rising
• Select the desired logic function with the edge detection)
LCxMODE<2:0> bits of the CLCxCON register.
• LCxINTN bit of the CLCxCON register (for a
• Select the desired polarity of the logic output with falling edge detection)
the LCxPOL bit of the CLCxPOL register. (This
step may be combined with the previous gate
output polarity step). The CLCxIF bit of the associated PIR registers, must
• If driving a device, set the desired pin PPS control be cleared in software as part of the interrupt service. If
register and also clear the TRIS bit corresponding another edge is detected while this flag is being
to that output. cleared, the flag will still be set at the end of the
sequence.
• If interrupts are desired, configure the following
bits:
30.4 Output Mirror Copies
- Set the LCxINTP bit in the CLCxCON register
for rising event. Mirror copies of all LCxCON output bits are contained
- Set the LCxINTN bit in the CLCxCON in the CLCxDATA register. Reading this register reads
register or falling event. the outputs of all CLCs simultaneously. This prevents
- Set the CLCxIE bit of the associated PIE any reading skew introduced by testing or reading the
registers. CLCxOUT bits in the individual CLCxCON registers.
- Set the GIE and PEIE bits of the INTCON
register. 30.5 Effects of a Reset
• Enable the CLCx by setting the LCxEN bit of the The CLCxCON register is cleared to zero as the result
CLCxCON register. of a Reset. All other selection and gating values remain
unchanged.

The CLC module operates independently from the
system clock and will continue to run during Sleep,
provided that the input sources selected remain active.
The HFINTOSC remains active during Sleep when the
CLC module is enabled and the HFINTOSC is
selected as an input source, regardless of the system
clock source selected.
In other words, if the HFINTOSC is simultaneously
selected as the system clock and as a CLC input
source, when the CLC is enabled, the CPU will go idle
during Sleep, but the CLC will continue to operate and
the HFINTOSC will remain active.
This will have a direct effect on the Sleep mode current.

PIC16(L)F1615/9
FIGURE 30-2: INPUT DATA SELECTION AND GATING
Data Selection
LCx_in[0] 00000
Data GATE 1
lcxd1T LCxD1G1T
lcxd1N LCxD1G1N
LCx_in[31] 11111
LCxD2G1T
LCxD1S<4:0>
LCxD2G1N lcxg1
LCx_in[0] 00000
LCxD3G1T
LCxG1POL
lcxd2T
LCxD3G1N
lcxd2N
LCxD4G1T
LCx_in[31] 11111
LCxD2S<4:0> LCxD4G1N
LCx_in[0] 00000
Data GATE 2
lcxg2
lcxd3T
(Same as Data GATE 1)
lcxd3N
Data GATE 3
LCx_in[31] 11111
lcxg3
LCxD3S<4:0>
(Same as Data GATE 1)
LCx_in[0] 00000 Data GATE 4

lcxg4
lcxd4T (Same as Data GATE 1)
lcxd4N
LCx_in[31] 11111
LCxD4S<4:0>
Note: All controls are undefined at power-up.

PIC16(L)F1615/9
FIGURE 30-3: PROGRAMMABLE LOGIC FUNCTIONS
Rev. 10-000122A
5/18/2016
AND-OR OR-XOR
lcxg1 lcxg1
lcxg2 lcxg2
lcxq lcxq
lcxg3 lcxg3
lcxg4 lcxg4
LCxMODE<2:0> = 000 LCxMODE<2:0> = 001

4-input AND S-R Latch
lcxg1 lcxg1
S Q lcxq
lcxg2
lcxg2
lcxq
lcxg3
lcxg3
R
lcxg4 lcxg4
LCxMODE<2:0> = 010 LCxMODE<2:0> = 011

1-Input D Flip-Flop with S and R 2-Input D Flip-Flop with R
lcxg4
S
lcxg4
lcxg2 D Q lcxq D Q lcxq
lcxg2
lcxg1 R
lcxg1 R
lcxg3 lcxg3
LCxMODE<2:0> = 100 LCxMODE<2:0> = 101

J-K Flip-Flop with R 1-Input Transparent Latch with S and R
lcxg4
lcxg2 J Q lcxq S
lcxg2 D Q lcxq
lcxg1
lcxg4 K
R
lcxg3 LE
R
lcxg3
lcxg1
LCxMODE<2:0> = 110 LCxMODE<2:0> = 111

PIC16(L)F1615/9
30.7 Register Definitions: CLC Control
REGISTER 30-1: CLCxCON: CONFIGURABLE LOGIC CELL CONTROL REGISTER

R/W-0/0 U-0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
LCxEN — LCxOUT LCxINTP LCxINTN LCxMODE<2:0>
bit 7 bit 0
Legend:
bit 7 LCxEN: Configurable Logic Cell Enable bit

1 = Configurable logic cell is enabled and mixing input signals
0 = Configurable logic cell is disabled and has logic zero output
bit 5 LCxOUT: Configurable Logic Cell Data Output bit
Read-only: logic cell output data, after LCxPOL; sampled from lcx_out wire.
bit 4 LCxINTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit
1 = CLCxIF will be set when a rising edge occurs on lcx_out
0 = CLCxIF will not be set
bit 3 LCxINTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit
1 = CLCxIF will be set when a falling edge occurs on lcx_out
0 = CLCxIF will not be set
bit 2-0 LCxMODE<2:0>: Configurable Logic Cell Functional Mode bits
111 = Cell is 1-input transparent latch with S and R
110 = Cell is J-K flip-flop with R
101 = Cell is 2-input D flip-flop with R
100 = Cell is 1-input D flip-flop with S and R
011 = Cell is S-R latch
010 = Cell is 4-input AND
001 = Cell is OR-XOR
000 = Cell is AND-OR

PIC16(L)F1615/9
REGISTER 30-2: CLCxPOL: SIGNAL POLARITY CONTROL REGISTER

R/W-0/0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u
LCxPOL — — — LCxG4POL LCxG3POL LCxG2POL LCxG1POL
bit 7 bit 0
Legend:
bit 7 LCxPOL: LCOUT Polarity Control bit

1 = The output of the logic cell is inverted
0 = The output of the logic cell is not inverted
bit 3 LCxG4POL: Gate 4 Output Polarity Control bit
1 = The output of gate 4 is inverted when applied to the logic cell
0 = The output of gate 4 is not inverted

PIC16(L)F1615/9
REGISTER 30-3: CLCxSEL0: MULTIPLEXER DATA 0 SELECT REGISTERS

— — LCxD1S<5:0>
bit 7 bit 0
Legend:

bit 5-0 LCxD1S<5:0>: Input Data 1 Selection Control bits
See Table 30-1 for signal names associated with inputs.

— — LCxD2S<5:0>
bit 7 bit 0
Legend:


— — LCxD3S<5:0>
bit 7 bit 0
Legend:


PIC16(L)F1615/9

— — LCxD4S<5:0>
bit 7 bit 0
Legend:


PIC16(L)F1615/9
REGISTER 30-7: CLCxGLS0: GATE 1 LOGIC SELECT REGISTER

LCxG1D4T LCxG1D4N LCxG1D3T LCxG1D3N LCxG1D2T LCxG1D2N LCxG1D1T LCxG1D1N
bit 7 bit 0
Legend:
bit 7 LCxG1D4T: Gate 1 Data 4 True (non-inverted) bit

1 = lcxd4T is gated into lcxg1
0 = lcxd4T is not gated into lcxg1
bit 6 LCxG1D4N: Gate 1 Data 4 Negated (inverted) bit
1 = lcxd4N is gated into lcxg1
0 = lcxd4N is not gated into lcxg1

PIC16(L)F1615/9

bit 7 bit 0
Legend:


PIC16(L)F1615/9

bit 7 bit 0
Legend:


PIC16(L)F1615/9

bit 7 bit 0
Legend:


PIC16(L)F1615/9
REGISTER 30-11: CLCDATA: CLC DATA OUTPUT

U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0
— — — — MLC4OUT MLC3OUT MLC2OUT MLC1OUT
bit 7 bit 0
Legend:

bit 3 MLC4OUT: Mirror copy of LC4OUT bit
TABLE 30-3: SUMMARY OF REGISTERS ASSOCIATED WITH CLCx

Register
Name Bit7 Bit6 Bit5 Bit4 BIt3 Bit2 Bit1 Bit0
on Page

ANSELB — — ANSB5 ANSB4 — — — — 159
CLC1CON LC1EN — LC1OUT LC1INTP LC1INTN LC1MODE<2:0> 443
CLCDATA — — — — MLC4OUT MLC3OUT MLC2OUT MLC1OUT 450
CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N 446
CLC1POL LC1POL — — — LC1G4POL LC1G3POL LC1G2POL LC1G1POL 444
CLC1SEL0 — — LC1D1S<5:0> 445
CLC1SEL1 — — LC1D2S<5:0> 445
CLC1SEL2 — — LC1D3S<5:0> 453
CLC1SEL3 — — LC1D4S<5:0> 454
CLC2SEL0 — — LC2D1S<5:0> 445
CLC2SEL1 — — LC2D2S<5:0> 445
CLC2SEL2 — — LC2D3S<5:0> 453
CLC2SEL3 — — LC2D4S<5:0> 454
Legend: — = unimplemented read as ‘0’,. Shaded cells are not used for CLC module.

PIC16(L)F1615/9
TABLE 30-3: SUMMARY OF REGISTERS ASSOCIATED WITH CLCx (continued)
Register
Name Bit7 Bit6 Bit5 Bit4 BIt3 Bit2 Bit1 Bit0
on Page
CLC3SEL0 — — LC3D1S<5:0> 453
CLC3SEL1 — — LC3D2S<5:0> 453
CLC3SEL2 — — LC3D3S<5:0> 453
CLC3SEL3 — — LC3D4S<5:0> 454
CLC4SEL0 — — LC4D1S<5:0> 453
CLC4SEL1 — — LC4D2S<5:0> 453
CLC4SEL2 — — LC4D3S<5:0> 453
CLC4SEL3 — — LC4D4S<5:0> 454
Legend: — = unimplemented read as ‘0’,. Shaded cells are not used for CLC module.

PIC16(L)F1615/9
31.0 ANGULAR TIMER (AT) MODULE 31.1 Principle of Operation
The Angular Timer (AT) module subdivides periodic Consider the statements in Equation 31-1:
signals into smaller equally spaced intervals, the num-
ber of which remain constant as the periodic signal fre- EQUATION 31-1:
quency changes. A counter tracks the intervals starting
If: And: Then:
at zero at each period event. The counter can be com-
pared to user defined values to cause events, or the F F
P = --- A = --- A = R
counter value can be captured by events external to the R P
module. This allows for a variety of applications, such
as measuring of A/C mains, stall detection for motors,
In these three equations:
commutation for brushless motors, and TDC detection
for internal combustion engines. A second counter • P represents the period count ATxPER
tracks the period time. This can be used to measure the • A represents the angle or phase count ATxPHS
error of the period based on a pre-programmed set • R represents the desired resolution ATxRES
point, as well as detect missing pulses in the signal. • F represents some arbitrary scaler value
The angular timer includes the following features: Notice that the phase count equals the desired resolu-
• Two operating modes tion regardless of what F is. If we let F equal the ratio of
- Single-pulse per period a system clock to the input signal frequency then that
- Multiple-pulses per period means the phase count is a constant equaling the
• Two missing pulse modes desired resolution regardless of the input frequency.
- Adaptive This has many extraordinary uses including:
- Fixed • Use phase compare feature to create an event at
• Multiple selectable clock sources a fixed phase angle in the period
• Phase clock output with polarity control • Use capture feature to capture the phase angle at
which an event occurs
• Period clock output with polarity control
• Use error feature to monitor deviations from a
• Missing pulse output with polarity control user specified period time
• Interrupts for phase and period clock generation,
The details of these features, and more, are described
as well as for missing pulse detect
in the following sections of this chapter.
• Period set point and error register
• Compare-pulse outputs 31.2 Angular Timer Operating Modes
- Independent interrupts
The AT module operates in two basic modes:
• Capture inputs
- Input polarity control • Single-Pulse mode
• Multi-Pulse mode
- Independent interrupts
Both modes function on the same principle: Dividing a
periodic input signal into intervals, and allowing events
to trigger off of these smaller intervals. The primary
difference between these two modes is how the period
is determined. The Single-Pulse mode determines the
period as the time between every pulse in the input
pulse stream. The Multi-Pulse mode determines the
period as the time between missing pulses in the input
pulse stream.
The primary parameter for both modes is the ATxRES
register pair. This value is used to determine the
granularity of the phase counter and the frequency of
the phase clock output of the module.

PIC16(L)F1615/9
31.2.1 SINGLE-PULSE MODE Notice that the division is ATxPER + 1. Ideally, this would
be just ATxPER but the divider includes zero in the
The operation of Single-Pulse mode is illustrated in
count. In most applications, ATxPER is a large number
Figure 31-1. The calculations on the input signal are done
so the error introduced by adding one is negligible.
in a few distinct steps. First, there is a divider that divides
the module clock by the ATxRES register pair and uses ATxPHS counting from 0 to ATxRES is useful when the
the resulting signal to increment a period counter. This input signal represents a rotation (for example, a motor
operation is expressed by Equation 31-2. This equation or A/C mains). In this case, the input signal is under-
differs slightly from that of Equation 31-1 because the stood to provide a period pulse every 360 degrees.
counters include the count of zero. To compensate for Since the phase clock equally divides the signal period
this, the number written to the resolution register, into a number of intervals determined by the ATxRES
ATxRES, must be one less than the desired resolution. register pair, each pulse on the phase clock output
marks a fixed phase angle in that rotation, as
EQUATION 31-2: expressed by Equation 31-4.
F  ATxclk  EQUATION 31-4:

---------------------------
F  ATxsig 
ATxPER = ------------------------------------
 ATxRES + 1  360degrees
AngleReso l ution = ----------------------------------
ATxRES + 1
Variables in Equation 31-2 are as follows:
• ATxPER is the value of the period counter latched ATxRES can then be used with the instantaneous value
by the input signal. of the ATxPHS register pair to get the instantaneous
• ATxRES is the user-specified resolution. The angle of the rotation using Equation 31-5.
phase counter will count up to this value.
• F(ATxclk) is the ATx clock frequency. EQUATION 31-5:
• F(ATxsig) is the input signal frequency.
The second step in the angular timer’s operation is the ATxPHS
creation of the phase clock, which is also illustrated in
Angle = 360degrees  -------------------------------
ATxRES + 1
Figure 31-1. The input clock is divided by the ATxPER
value, latched-in during the previous step, and the
resulting signal is used to increment the phase counter.
31.2.2 MULTI-PULSE MODE
This signal also is used as the phase clock output, and for
setting the PHSIF interrupt flag bit of the ATxIR0 register. The operation of Multi-Pulse mode is illustrated in
The result is that the phase counter counts from zero to Figure 31-3. The calculations on the input signal are
a final value expressed in Equation 31-3, outputting a similar to those in Single-Pulse mode, with the primary
pulse each time the counter increments. The value of the difference relating to when the ATxPHS register pair is
phase counter can be accessed by software by reading reset.
the ATxPHS register pair. However, because of the The period counter is latched into the ATxPER register
synchronization required, in order for reads of this pair and reset on every input pulse except the pulse
register pair to be accurate, the instruction clock (FOSC/4) immediately following a missing pulse. The first active
needs to be at least 3x the ATx_phsclk output frequency. pulse following a missing pulse triggers all of the following:
• Period clock output
EQUATION 31-3:
• PERIF interrupt
• Phase counter reset
F  ATxclk 
--------------------------- The result is a period clock output that has a period
 F  ATxsig 
ATxPHS  final  = ------------------------------------- length equal to the time between missing pulses (e.g.,
 ATxPER + 1  a missing tooth in a gear). This leads to a significantly
different relation between ATxRES and the maximum
The variables in Equation 31-3 are as follows: phase count, ATxPHS, as shown in Equation 31-6.
• ATxPHS(final) is the maximum value that the

EQUATION 31-6:
phase counter will reach before being reset by the
input signal. As noted in Equation 31-1, this will
equal ATxRES.
ATxPHS  final  = ATxRES  ------------------
MissP
• ATxPER is the maximum value of the period  PulseP
counter.
• F(ATxclk) is the ATx clock frequency.
• F(ATxsig) is the input signal frequency.

PIC16(L)F1615/9
The variables in Equation 31-6 are as follows:
• MissP is the period between missing pulses
• PulseP is the period between input pulses
• ATxPHS(final) is the maximum value of the phase
counter
This results in a phase clock output that pulses
ATxRES+1 times every input pulse, and a phase
counter that increments from 0 to ATxPHS(final) over
the entire time between the missing pulses.
Similar to Single-Pulse mode, this allows for triggered
events to occur at fixed phase angles in the signal’s
period where the period is defined as the time between
missing pulses. An example of multi-pulse operation is
illustrated in the timing diagram of Figure 31-5, which
also demonstrates what happens as a result of
variations in the input signal period.

FIGURE 31-1: ANGULAR TIMER SIMPLIFIED BLOCK DIAGRAM, SINGLE-PULSE MODE
Rev. 10-000245A
ATxRES 1/21/2015
15
Set PERIF
SSEL Divide by Period
ATxRES+1 Counter
R R
ATx_perclk
PRP
LC4_out 111
PREC 15
LC3_out 110 ATxMISS
LC2_out 101
+ Divide by 2
LC1_out 100 Sync ATxsig LD ATxPER Difference
ZCD1_out 011 (2 Clocks)
-
15
C2OUT_sync 010 1 0 APMOD
C1OUT_sync 001
PPS 000 MPP ATx_missedpulse
Comparator
ATxINPPS
PHP
PS 1 Clock
CS Delay
ATx_phsclk
HFINTOSC (16 MHz) 1 Divide by Phase
Prescaler ATxclk
PIC16(L)F1615/9
FOSC 0 ATxPER+1 Counter
R R Set PHSIF
ATxclkcc
10
To Capture/
DS40001770D-page 454
Compare
Instruction
LD ATxPHS
Clock
FIGURE 31-2: ANGULAR TIMER SIMPLIFIED BLOCK DIAGRAM, MULTI-PULSE MODE
DS40001770D-page 455
PIC16(L)F1615/9
Rev. 10-000246A
ATxRES 1/21/2015
15
SSEL Divide by Period Set PERIF

ATxRES+1 Counter
R R
PREC ATx_perclk
LC4_out 111 PRP
15
LC3_out 110 ATx_missedpulse ATxMISS
ATxperiod
LC2_out 101
+ Divide by 2
LC1_out 100 Missing ATxsig
ATx_in
Pulse Period LD ATxPER Difference
ZCD1_out 011 Trigger -
15
C2OUT_sync 010 1 0 APMOD
C1OUT_sync 001
PPS 000 MPP ATx_missedpulse
Comparator
ATxINPPS
PHP
PS 1 Clock
CS Delay
ATx_phsclk
HFINTOSC (16 MHz) 1 ATxclk Divide by Phase
Prescaler
FOSC 0 ATxPER+1 Counter
R R Set PHSIF
ATxclkcc
10
To Capture/
Compare
Instruction
LD ATxPHS
Clock
FIGURE 31-3: ANGULAR TIMER SIMPLIFIED MULTI-PULSE PERIOD TRIGGER BLOCK DIAGRAM
Rev. 10-000247A
7/25/2014
1 D Q D Q
ATxsig
Atx_in
R
Atxclk
ATxperiod
1 D Q D Q
Atx_missedpulse
R
PIC16(L)F1615/9
DS40001770D-page 456
PIC16(L)F1615/9
31.2.3 MISSING PULSE DETECTION
In both Single-Pulse and Multi-Pulse modes, the AT
module monitors for missing pulses in the following
manner. The latched value of the ATxPER register pair
is continuously subtracted from the value of the period
counter as it counts up. The result of this subtraction is
compared to a third value and a missing pulse event is
generated when the comparison is equal.
The third value is either the ATxMISS register pair or the
ATxPER register pair divided by two. The APMOD bit of
ATxCON0 register (Register 31-1) selects which of
these two values is used.
In Single-Pulse mode, a missing pulse event generates
the missing pulse output of the module as well as
triggering the MISSIF interrupt.
In Multi-Pulse mode, a missing pulse event generates
the output and interrupt, and is also used to determine
the period signal timing.
31.2.4 MISSING PULSE MODES

Missing pulse detection has two modes of operation
selected with the APMOD bit of the ATxCON0 register:
• Adaptive
• Fixed
31.2.4.1 Adaptive Missing Pulse Mode

When APMOD = 1, the missing pulse detection is in the
Adaptive mode. In Adaptive mode, the difference
between the period counter and the latched ATxPER
value is compared to the latched ATxPER value divided
by two. A missing pulse event will occur when an input
signal pulse is not detected within 1.5 times the
previous time between pulses. If the signal input period
changes, the missing pulse comparison adapts to the
change to maintain the relative time to the missing pulse
event at 1.5 times the previous pulse interval.
31.2.4.2 Fixed Missing Pulse Mode

When APMOD = 0, the missing pulse detection is in the
Fixed mode. In Fixed mode, the difference between the
period counter and the latched ATxPER value is
compared to the value in the ATxMISS register pair.
This gives the user absolute control over when the
missing pulse will be detected, with the trade-off of not
being adaptive to changes in the period.

FIGURE 31-4: TIMING DIAGRAM FOR SINGLE PULSE MODE
Rev. 10-000243A
7/25/2014
Input Signal
(case #1: narrow)
Input Signal
(case #2: wide)
ATxPER
ATx_perclk
ATx_phsclk
ATxPHS
FIGURE 31-5: TIMING DIAGRAM FOR MULTI-PULSE MODE

Rev. 10-000244A
7/25/2014
Input Signal
ATxPER
PIC16(L)F1615/9
ATx_missedpulse
ATx_perclk
ATx_phsclk
DS40001770D-page 458
ATxPHS
PIC16(L)F1615/9
31.2.5 VALID BIT The actual error can be determined with Equation 31-7.
Several values used by the AT module must be
calculated from external signals. As such, these values EQUATION 31-7:
may be inaccurate for a period of time after the angular
timer starts up. Because of this, the module will not F  ATxclk 
output signals or trigger interrupts for a period of time period = ---------------------------------------------------------------------
F  ATxsig    ATxRES + 1 
after the module is enabled, or under certain other
conditions that might jeopardize accurate output
values. This output inhibition is indicated by the period – int  period + 1 
read-only VALID bit of the ATxCON1 being clear. error% = 100   --------------------------------------------------------------
 period 
The following cases will clear the VALID bit in hardware:
• Any write to ATxRES register pair
• Phase counter overflow (ATxPHS register pair) 31.3 Input and Clock Selection
clocked beyond 0x3FF) The input clock for the AT module can come from either
• In-Circuit Debugger halt the FOSC system clock or the 16 MHz HFINTOSC, and
• EN = 0 is chosen by the CS0 bit of the ATxCLK register. In
• ATxPER register pair = 0 addition, the clock is run through a prescaler that can
• Device Reset be /1, /2, /4, or /8, which is configured by the PS<1:0>
bits of the ATxCON0 register. This prescaled clock is
As long as the VALID bit is cleared, the following then used for all clock operations of the Angular Timer,
occurs: and as such, should be used for all of the equations
• Period clock is not output and associated demonstrated above determining the Angular Timer’s
interrupts do not trigger. behavior.
• Missed pulse is not output and associated The input signal for the AT module can come from a
interrupts do not trigger. variety of sources. The source is selected by the SSEL
• Phase clock is not output and associated bits of the ATxSIG register (Register 31-4).
interrupts do not trigger.
• Phase counter does not increment. 31.4 Module Outputs
• Capture logic does not function and associated
interrupts do not trigger. 31.4.1 ANGLE/PHASE CLOCK OUTPUT
• Compare logic does not function and associated The angle/phase clock signal (ATx_phsclk) can be
interrupts do not trigger. used by the CLC as an input signal to combinational
• Every ATxsig edge latches the period counter into logic. The polarity of this signal is configured by the
the ATxPER register pair, regardless of mode. PHP bit of the ATxCON1 register.
In single-pulse modes, the VALID bit becomes set upon 31.4.2 PERIOD CLOCK OUTPUT
the 3rd active input edge of the signal that latches the
ATxPER register pair. In multi-pulse modes, a missing The period clock signal (ATx_perclk) can be used as an
pulse trigger is also required, ensuring that at least one input clock for the Timer2/4/6 and Signal Measurement
full revolution of the input has occurred. module, as well as an input signal to the CLC for
combinational logic. The polarity of this signal is
An example of the VALID bit in Single-Pulse mode is configured by the PRP bit of the ATxCON1 register
shown in Figure 31-6. (Register 31-2).
31.2.6 DETERMINING ACCURACY 31.4.3 MISSED PULSE OUTPUT
The ATxRES register pair determines the resolution of The missed pulse signal (ATx_missedpulse) can be
the period measurement and, by extension, the used by the CLC as an input signal to combinational
maximum value that the phase counter reaches at the logic. The polarity of this signal is configured by the
end of each input signal period. The interim value, MPP bit of the ATxCON1 register.
ATxPER, used to derive the phase counter is, by nature
of the circuitry, an integer. The ratio of the integer value
obtained by the circuit and the calculated floating point
value is the inherent error of the measurement. When
ATxRES is small then integer rounding results in large
errors. Factors that contribute to large errors include:
• Large values for ATxRES
• Relatively low ATxclk frequency
• Relatively high ATxsig input frequency

FIGURE 31-6: EXAMPLE OPERATION (ATxRES = 4)
Rev. 10-000242A
5/29/2014
ATxRES 4
Input Signal
ATxPER 5 20
Atx_phsclk
ATxPHS 0 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3
VALID
PIC16(L)F1615/9
DS40001770D-page 460
PIC16(L)F1615/9
31.5 Period Set Point and Error The capture event also generates a pulse that can be
Measurement used for the following:
• Trigger an ADC reading
The ATxSTPT register pair controls the period set point
• CLC logic input
of the AT module. The signal period captured in the
• Set the CCyIF bit
ATxPER register pair at every signal input pulse. The
unsigned 15-bit ATxSTPT value is subtracted from the See Section 31.7 “Interrupts” for more details on the
unsigned 15-bit ATxPER value and the signed 16-bit interrupts triggered by the AT module.
result is placed in the ATxERR register pair. The capture input signal source is selected by the
The ATxSTPT value is double buffered requiring an capture/compare’s respective ATxCSELy register
ATxSTPTL value write for the ATxSTPTH value to take (Register 31-22), and its polarity is selected by the
effect. This is done so that all 16 bits update at the ATxCAPyP bit of the ATxCCONy register
same time, thereby avoiding a miscalculation of the (Register 31-21). Note that when in Capture mode, the
error. ATxCCy register pair is read-only.
31.6.2 COMPARE MODE

FIGURE 31-7: ANGULAR TIMER SET
POINT CALCULATION Compare mode is selected when the CCyMODE bit (of
BLOCK DIAGRAM the ATxCCONy register) = 0. Refer to Figure 31-9.
In Compare mode, the module compares the current
Rev. 10-000216A
7/25/2014
value in the ATxCCy register pair to the phase counter
value. When the two values are equal then a compare
event is generated and output to the following:
ATxSTPT
• Trigger an ADC reading
• CLC logic input
• Set the CCyIF bit
-
ATxPER Difference
See Section 31.7 “Interrupts” for more details on the
+ interrupts triggered by the AT module.
ATxERR
31.6 Capture and Compare Functions

The angular timer contains multiple built-in
capture/compare modules. These are controlled by
their respective ATxCCONy registers where “x” refers to
the AT instance and “y’ refers to the Capture/Compare
instance within that AT module.
This particular device contains three capture/compare
modules within the AT module. The CCyMODE bit of the
ATxCCONy register controls whether each particular
module is in Capture or Compare mode. The polarity of
each module’s respective output signal is controlled by
the CCyPOL bit of the ATxCCONy register
(Register 31-21). Both the Capture and Compare modes
use an edge detect that runs off of the ATxclk signal.
31.6.1 CAPTURE MODE

Capture mode is selected when the CCyMODE bit (of
the ATxCCONy register) = 1. Refer to Figure 31-8.
In Capture mode, the value of the phase counter is
written to the respective ATxCCy registers on the rising
edge of the capture input signal.

PIC16(L)F1615/9
FIGURE 31-8: ANGULAR TIMER CAPTURE/COMPARE UNIT BLOCK DIAGRAM:
CAPTURE MODE
Rev. 10-000218A
7/25/2014
ATxPHS
FOSC Clock
Set CCyIF(1)
Sync(2)
ATxCCy(1)
CCPyPOL
ATx_cmpy(1)
PPS
ATCCyPPS(1)
Notes 1: This diagram applies to all capture/compare units in the Angular Timer
module. Replace “y” with the appropriate number for all registers/
signals
2: The CCyIF interrupt trigger is synchronized with FOSC unless the
device is in Sleep, in which case this synchronizer is bypassed
FIGURE 31-9: ANGULAR TIMER CAPTURE/COMPARE UNIT BLOCK DIAGRAM:

COMPARE MODE
Rev. 10-000217A
7/25/2014
ATxCCy(1) FOSC Clock

Set CCyIF(1)
Sync(2)
CCPyPOL
Compare ATx_cmpy(1)
ATx_clkcc
ATxPHS
Notes 1: This diagram applies to all capture/compare units in the Angular Timer
module. Replace “y” with the appropriate number for all registers/
signals
2: The CCyIF interrupt trigger is synchronized with FOSC unless the
device is in Sleep, in which case this synchronizer is bypassed

PIC16(L)F1615/9
31.7 Interrupts 31.7.4 ANGULAR TIMER
CAPTURE/COMPARE INTERRUPTS
The angular timer and its capture/compare features
can generate multiple interrupt conditions. To accom- Capture and compare interrupts are triggered by the
modate all of these interrupt sources, the module is capture/compare functions of the module. If configured
provided with its own interrupt logic structure, similar to for Capture mode, the interrupt will trigger after the
that of the micro controller. Angular timer interrupts are capture signal has successfully latched the value of the
enabled by the ATxIE0 register (Register 31-13) and phase counter into the capture registers. If configured
their respective flags are located in the ATxIR0 register for Compare mode, the interrupt will trigger when a
(Register 31-14). The capture/compare interrupts are match is detected between the value placed in the
enabled by the ATxIE1 register (Register 31-15) with compare register and the value of the phase counter.
flags in the ATxIR1 register (Register 31-16). All These interrupts are controlled by the CC1IE, CC2IE,
sources are funneled into a single Angular Timer Inter- and CC3IE bits of the ATxIE1 register, respectively, and
rupt Flag bit, ATxIF of the PIR5 register (Register 7-11). are similarly indicated by the CC1IF, CC2IF, and CC3IF
This means that upon a triggered interrupt, the ATxIR0 bits of the ATxIR1 register.
and ATxIR1 register bits will indicate the source of the
triggered interrupt. It also means that in order for spe-
cific interrupts to generate a microcontroller interrupt,
both the ATxIE bit of the PIE register and the desired
enable bit in either ATxIE0 or ATxIE1 must be set.
Note: Due to the nature of the angular timer
interrupts, the ATxIF flag bit of the PIR5
register is read-only.
31.7.1 ANGULAR TIMER PERIOD

INTERRUPT
This interrupt is triggered when the AT module detects
a period event. In Single-Pulse mode, a period event
occurs on every input signal edge. In Multi-Pulse mode,
a period event occurs on the input signal edge following
a missed pulse. The period interrupt generation
matches with the pulses on the period clock output of
the timer. It is enabled by the ATPERIE bit of the
ATxIE0 register and the status is indicated by the
PERIF bit of the ATxIR0 register.
31.7.2 ANGULAR TIMER PHASE CLOCK

INTERRUPT
This interrupt is triggered on each pulse of the phase
clock output of the timer. It is enabled by the ATPHIE bit
of the ATxIE0 register and the status is indicated by the
PHSIF bit of the ATxIR0 register.
31.7.3 ANGULAR TIMER MISSING PULSE

INTERRUPT
This interrupt is triggered upon the output of a missing
pulse detection signal. Refer to Section 31.2.3 “Missing
Pulse Detection” for more information. This interrupt is
enabled by the ATMISSIE bit of the ATxIE0 register and
its status is indicated by the ATMISSIF bit of the ATxIR0
register.

PIC16(L)F1615/9
31.8 Angular Timer Control Registers
Long bit name prefixes for the angular timer peripherals
are shown in Table 31-1. Refer to Section 1.1 “Regis-
ter and Bit Naming Conventions” for more informa-
tion.
TABLE 31-1:
AT1 AT1
REGISTER 31-1: ATxCON0: ANGULAR TIMER CONTROL 0 REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0
EN PREC PS<1:0> POL — APMOD MODE
bit 7 bit 0
Legend:
bit 7 EN: Angular Timer Enable bit

1 = Angular timer is enabled; internal clocks are active
0 = Angular timer is disabled
bit 6 PREC: Period Precision Control bit
1 = Period prescaler is reset at the start of every period
0 = Period prescaler is not reset at the start of every period; fraction period affects next period mea-
surement
bit 5-4 PS<1:0>: Clock Prescaler Control bits
11 = Resolution and phase counter prescale logic is clocked by ATxCLK/8
00 = Resolution and phase counter prescale logic is clocked by ATxCLK
bit 3 POL: ATxsig Active Edge (Polarity) Select bit
1 = Falling edge of ATxsig is the active edge
0 = Rising edge of ATxsig is the active edge
bit 1 APMOD: Adaptive Missing Pulse Mode Select bit
1 = Adaptive Missing Pulse mode. Missing pulse is detected when no pulse is detected within
1.5 times ATxPER
0 = Fixed Missing Pulse mode. ATxMISS register pair determines missing pulse event.
bit 0 MODE: Angular Timer Mode Select bit
1 = Angular timer is in Multi-Pulse mode (period of input signal defined by missing pulses)
0 = Angular timer is in Single-Pulse mode (period of input signal defined by input pulses)

PIC16(L)F1615/9
REGISTER 31-2: ATxCON1: ANGULAR TIMER CONTROL 1 REGISTER

U-0 R/W-0/0 U-0 R/W-0/0 U-0 R/W-0/0 R-0/0 R-0/0
— PHP — PRP — MPP ACCS VALID
bit 7 bit 0
Legend:

bit 6 PHP: Phase Clock Output Polarity bit
1 = Phase clock output is active-low
0 = Phase clock output is active-high
bit 4 PRP: Period Clock Output Polarity bit
1 = Period clock output is active-low
0 = Period clock output is active-high
bit 2 MPP: Missing Pulse Output Polarity bit
1 = Missing pulse output is active-low
0 = Missing pulse output is active-high
bit 1 ACCS: Acceleration Sign bit
1 = The value currently in ATxPER is less than the previous value
0 = The value currently in ATxPER is greater than or equal to the previous value
bit 0 VALID: Valid Measurement bit
1 = Sufficient input cycles have occurred to make ATxPER and ATxPHS valid.
0 = The values in ATxPER and ATxPHS are not valid; not enough input cycles have occurred

PIC16(L)F1615/9
REGISTER 31-3: ATxCLK: ANGULAR TIMER CLOCK SELECTION REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-x/x
— — — — — — — CS0
bit 7 bit 0
Legend:

bit 0 CS0: Angular Timer Clock Selection bit
1 = HFINTOSC 16 MHz
0 = FOSC
REGISTER 31-4: ATxSIG: ANGULAR TIMER INPUT SIGNAL SELECTION REGISTER

U-0 U-0 U-0 U-0 U-0 R/W-x/x R/W-x/x R/W-x/x
— — — — — SSEL<2:0>
bit 7 bit 0
Legend:

bit 2-0 SSEL<2:0>: Angular Input Signal Selection bit
111 = LC4_out
110 = LC3_out
101 = LC2_out
100 = LC1_out
011 = ZCD1_out
010 = cmp2_sync
001 = cmp1_sync
000 = ATxINPPS

PIC16(L)F1615/9
REGISTER 31-5: ATxRESH: ANGULAR TIMER RESOLUTION HIGH REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R/W-x/u R/W-x/u
— — — — — — RES<9:8>
bit 7 bit 0
Legend:

bit 1-0 RES<9:8>: ATxRES Most Significant bits, the Phase Counter Resolution
Note 1: Writing to this register resets VALID bit of the ATxCON1 (Register 31-2); output signals are inhibited for at
least two input cycles.
2: This register is not guarded for atomic access, and should only be accessed while the timer is not running.
REGISTER 31-6: ATxRESL: ANGULAR TIMER RESOLUTION LOW REGISTER

RES<7:0>
bit 7 bit 0
Legend:
bit 7-0 RES<7:0>: ATxRES Least Significant bits, the Phase Counter Resolution
Note 1: Writing to this register resets VALID bit of the ATxCON1 (Register 31-2); output signals are inhibited for at
least two input cycles.
2: This register is not guarded for atomic access, and should only be accessed while the timer is not running.

PIC16(L)F1615/9
REGISTER 31-7: ATxMISSH: ANGULAR TIMER MISSING PULSE DELAY HIGH REGISTER
MISS<15:8>(1)
bit 7 bit 0
Legend:
bit 7-0 MISS<15:8>(1): Most Significant bits (2’s complement) of ATxMISS. ATxMISS defines the period
counter value at which the missing pulse output becomes valid, based on the difference between the
current counter value and the latched-in value of ATxPER.
Note 1: ATxMISSH is held until ATxMISSL is written. Proper writes of ATxMISS should write to ATxMISSH first,
then ATxMISSL to ensure the value is properly written.
REGISTER 31-8: ATxMISSL: ANGULAR TIMER MISSING PULSE DELAY LOW REGISTER
MISS<7:0>
bit 7 bit 0
Legend:
bit 7-0 MISS<7:0>: Least Significant bits (2’s complement) of ATxMISS. ATxMISS defines the period counter
value at which the missing pulse output becomes valid, based on the difference between the current
counter value and the latched-in value of ATxPER.

PIC16(L)F1615/9
REGISTER 31-9: ATxPERH: ANGULAR TIMER MEASURED PERIOD HIGH REGISTER

POV PER<14:8>
bit 7 bit 0
Legend:
bit 7 POV: Period Counter Overflow bit

1 = Counter rolled over one or more times during measurement
0 = Value shown by ATxPER is valid
bit 6-0 PER<14:8>: Most Significant bits of ATxPER. ATxPER is the measured period value from the period
counter.
REGISTER 31-10: ATxPERL: ANGULAR TIMER MEASURED PERIOD LOW REGISTER

PER<7:0>
bit 7 bit 0
Legend:
bit 7-0 PER<7:0>: Least Significant bits of ATxPER. ATxPER is the measured period value from the period
counter.

PIC16(L)F1615/9
REGISTER 31-11: ATxPHSH: ANGULAR TIMER PHASE COUNTER HIGH REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R-x/x R-x/x
— — — — — — PHS<9:8>
bit 7 bit 0
Legend:

bit 1-0 PHS<9:8>: Most Significant bits of ATxPHS. ATxPHS is the instantaneous value of the phase counter.
REGISTER 31-12: ATxPHSL: ANGULAR TIMER PHASE COUNTER LOW REGISTER

PHS<7:0>
bit 7 bit 0
Legend:
bit 7-0 PHS<7:0>: Least Significant bits of ATxPHS. ATxPHS is the instantaneous value of the phase
counter.

PIC16(L)F1615/9
REGISTER 31-13: ATxIE0: ANGULAR TIMER ENABLE 0 REGISTER

U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — — PHSIE MISSIE PERIE
bit 7 bit 0
Legend:

bit 2 PHSIE: Phase Interrupt Enable bit
1 = The phase interrupt is enabled
0 = The phase interrupt is disabled
bit 1 MISSIE: Missed Pulse Interrupt Enable bit
1 = The missed pulse interrupt is enabled
0 = The missed pulse interrupt is disabled
bit 0 PERIE: Period Interrupt Enable bit
1 = The period interrupt is enabled
0 = The period interrupt is disabled
REGISTER 31-14: ATxIR0: ANGULAR TIMER INTERRUPT FLAG 0 REGISTER

U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — — PHSIF MISSIF PERIF
bit 7 bit 0
Legend:

bit 2 PHSIF: Phase Interrupt Flag bit
1 = The phase interrupt has occurred
0 = The phase interrupt has not occurred, or has been cleared
bit 1 MISSIF: Missed Pulse Interrupt Flag bit
1 = The missed pulse interrupt has occurred
0 = The missed pulse interrupt has not occurred, or has been cleared
bit 0 PERIF: Period Interrupt Flag bit
1 = The period interrupt has occurred
0 = The period interrupt has not occurred, or has been cleared

PIC16(L)F1615/9
REGISTER 31-15: ATxIE1: ANGULAR TIMER ENABLE 1 REGISTER

U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — — CC3IE CC2IE CC1IE
bit 7 bit 0
Legend:

bit 2 CC3IE: Capture/Compare Interrupt 3 Enable bit
If CC3MODE = 1 (Capture)
1 = Capture interrupt 3 is enabled
0 = Capture interrupt 3 is disabled
If CC3MODE = 0 (Compare)
1 = Compare interrupt 3 is enabled
0 = Compare interrupt 3 is disabled

PIC16(L)F1615/9
REGISTER 31-16: ATxIR1: ANGULAR TIMER INTERRUPT FLAG 1 REGISTER

U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — — CC3IF CC2IF CC1IF
bit 7 bit 0
Legend:

bit 2 CC3IF: Capture/Compare Interrupt 3 Flag bit
1 = Capture interrupt 3 has occurred; captured phase value is in ATxCC3
0 = Capture interrupt 3 has not occurred, or has been cleared
1 = Compare interrupt 3 has occurred
0 = Compare interrupt 3 has not occurred, or has been cleared

PIC16(L)F1615/9
REGISTER 31-17: ATxSTPTH: ANGULAR TIMER SET POINT HIGH REGISTER (1)
U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— STPT<14:8>
bit 7 bit 0
Legend:

bit 6-0 STPT<14:8>: Set Point Most Significant bits. ATxSTPT determines the threshold setting that the
period is compared against for error calculation.
Note 1: Writes to ATxSTPTH are double buffered. The value written to this register is held until a write to
ATxSTPTL occurs, at which point the value will be latched into the register
REGISTER 31-18: ATxSTPTL: ANGULAR TIMER SET POINT LOW REGISTER

STPT<7:0>
bit 7 bit 0
Legend:
bit 7-0 STPT<7:0>: Set Point Least Significant bits. ATxSTPT determines the threshold setting that the
period is compared against for error calculation.

PIC16(L)F1615/9
REGISTER 31-19: ATxERRH: ANGULAR TIMER SET POINT ERROR VALUE HIGH REGISTER
ERR<15:8>
bit 7 bit 0
Legend:
bit 7-0 ERR<15:8>: Most Significant bits of ATxERR. ATxERR is the error of the measured period value
compared to the threshold setting, defined as ATxPER-ATxSTPTP.
REGISTER 31-20: ATxERRL: ANGULAR TIMER SET POINT ERROR VALUE LOW REGISTER
ERR<7:0>
bit 7 bit 0
Legend:
bit 7-0 ERR<7:0>: Least Significant bits of ATxERR. ATxERR is the error of the measured period value
compared to the threshold setting, defined as ATxPER-ATxSTPTP.

PIC16(L)F1615/9
REGISTER 31-21: ATxCCONy: ANGULAR TIMER CAPTURE/COMPARE CONTROL 1 REGISTER

R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0
CCyEN — — CCPyPOL CAPyP — — CCyMODE
bit 7 bit 0
Legend:
bit 7 CCyEN: Capture/Compare Enable bit

1 = Capture/Compare logic is enabled
0 = Capture/Compare logic is disabled
bit 4 CCyPOL: Capture/Compare Output Polarity bit
In Capture mode (CCyMODE = 1):
1 = ATxCCOUT1 is active low when ATxCCy is updated
0 = ATxCCOUT1 is active high when ATxCCy is updated
In Compare mode (CCyMODE = 0):
1 = ATxCCOUT1 is active low when ATxPHS = ATxCCy
0 = ATxCCOUT1 is active high when ATxPHS = ATxCCy
bit 3 CAPyP: Capture Input Polarity bit
In Capture mode (CCyMODE = 1):
1 = At falling edge of the capture input (Selected by ATxCSELy) the value of the phase counter is
captured in ATxCC1
0 = At rising edge of the capture input (Selected by ATxCSELy) the value of the phase counter is
captured in ATxCC1
bit 0 CCyMODE: Capture/Compare Mode Select bit
1 = Capture/compare logic is in Capture mode
0 = Capture/compare logic is in Compare mode

PIC16(L)F1615/9
REGISTER 31-22: ATxCSELy: ANGULAR TIMER CAPTURE INPUT SELECT y REGISTER

U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — — CPyS<2:0>
bit 7 bit 0
Legend:

bit 2-0 CPyS<2:0>: Capture Input Source Select bits
111 = CWG_interrupt
110 = LC4_out
101 = LC3_out
100 = LC2_out
111 = LC1_out
010 = cmp2_sync
001 = cmp1_sync
000 = ATxCCy pin

PIC16(L)F1615/9
REGISTER 31-23: ATxCCyH: ANGULAR TIMER CAPTURE/COMPARE y HIGH REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R/q-0/0 R/q-0/0
— — — — — — CCy<9:8>
bit 7 bit 0
Legend:

bit 1-0 CCy<9:8>: ATxCCy Most Significant bits
In Capture mode (CCyMODE = 1) (Read-only):
ATxCCy is the captured value of ATxPHS when the capture input is signaled.
ATxCCy is the value that is compared to the current value of ATxPHS to trigger an interrupt/output
pulse.
Note 1: Writes to ATxCCyH are double buffered. The value written to this register is held until a write to ATxCCyL
occurs, at which point the value will be latched into the register
REGISTER 31-24: ATxCCyL: ANGULAR TIMER CAPTURE/COMPARE y LOW REGISTER

R/q-0/0 R/q-0/0 R/q-0/0 R/q-0/0 R/q-0/0 R/q-0/0 R/q-0/0 R/q-0/0
CCy<7:0>
bit 7 bit 0
Legend:
bit 7-0 CCy<7:0>: ATxCCy Least Significant bits

In Capture mode (CCyMODE = 1) (Read-only):
ATxCCy is the captured value of ATxPHS when the capture input is signaled.
ATxCCy is the value that is compared to the current value of ATxPHS to trigger an interrupt/output
pulse.

PIC16(L)F1615/9
TABLE 31-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE ANGULAR TIMER MODULE
Register
on page
AT1CC1H — — — — — — CC1<9:8> 478
AT1CC1L CC1<7:0> 478
AT1CCON1 CC1EN — — CC1POL CAP1P — — CC1MODE 476
AT1CLK — — — — — — — CS0 466
AT1CON0 EN PREC PS<1:0> POL — APMOD MODE 464
AT1CON1 — PHP — PRP — MPP ACCS VALID 465
AT1CSEL1 — — — — — CP1S<2:0> 477
AT1CSEL2 — — — — — CP2S<2:0> 477
AT1CSEL3 — — — — — CP3S<2:0> 477
AT1ERRH ERR<15:8> 475
AT1ERRL ERR<7:0> 475
AT1IE0 — — — — — PHSIE MISSIE PERIE 471
AT1IR0 — — — — — PHSIF MISSIF PERIF 471
AT1IE1 — — — — — CC3IE CC2IE CC1IE 472
AT1IR1 — — — — — CC3IF CC2IF CC1IF 473
AT1MISSH MISS<15:8> 468
AT1MISSL MISS<7:0> 468
AT1PERH POV PER<14:8> 469
AT1PERL PER<7:0> 469
AT1PHSH — — — — — — PHS<9:8> 470
AT1PHSL PHS<7:0> 470
AT1RESH — — — — — — RES<9:8> 467
AT1RESL RES<7:0> 467
AT1SIG — — — — — SSEL<2:0> 466
AT1STPTH — STPT<14:8> 474
AT1STPTL STPT<7:0> 474
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the AT module.

PIC16(L)F1615/9
32.0 MATH ACCELERATOR WITH 32.1 PID Module Setup Summary
PROPORTIONAL-INTEGRAL- The PID module can be configured either as a PID con-
DERIVATIVE (PID) MODULE troller or as a multiply and accumulate module. Multiply
and accumulate can be performed in four modes:
The math accelerator module is a mathematics module
that can perform a variety of operations, most promi- • Unsigned multiply and add, without accumulation
nently acting as a PID (Proportional-Integral-Deriva- • Unsigned multiply and accumulate
tive) controller. A PID controller is an algorithm that • Signed multiply and add, without accumulation
uses the present error (proportional), the sum of the • Signed multiply and accumulate
present and all previous errors (integral), and the dif-
ference between the present and previous change All of the modes are selected by the MODE<2:0> bits
(derivative) to correct errors and provide stability in a of the PIDxCON register.
system. It provides feedback to a system through a
32.1.1 PID MODE SETUP AND
series of iterations, using the present error as well as
previous errors to calculate a new input to the control- OPERATION
ler. The data flow for both PID modes is illustrated in When the MODE<2:0> bits of the PIDxCON register
Figure 32-1. are equal to ‘101’, the module is in PID controller
The module accomplishes the task of calculating the mode. The operation of the module in PID controller
PID algorithm by utilizing user-provided coefficients mode is generally performed as a loop. The input from
along with a multiplier and accumulator. As such, this an external system is fed into the controller, and the
multiplier and accumulator can also be configured to controller’s output is fed back into the external system.
quickly and efficiently perform signed and unsigned This will produce a new response from the system that
multiply-and-add calculations both with and without is then looped back into the PID controller. The data
accumulation. The data flow for these modes is flow for the PID operation is illustrated in Figure 32-1.
illustrated in Figure 32-2.
Features of this module include:
• Signed multiplier
• 35-bit signed accumulator
• PID controller support with user inputs for K1, K2,
K3, system error and desired set point
• Completion and Error interrupts
• Multiple user modes allowing for PID with or with-
out accumulation as well as several multiplication
operations

FIGURE 32-1: PID MODULE BASIC DATA FLOW BLOCK DIAGRAM, PID MODES
DS40001770D-page 481
PIC16(L)F1615/9
Rev. 10-000227A
PIDxSET PIDxK1 3/3/2016
+
Difference Z0 Multiplier
-
PIDxIIN
PIDxK2
+ +
PIDxZ1 Multiplier + Adder + Accumulator PIDxOUT
+
PIDxK3
PIDxZ2 Multiplier
Note 1: After the results of PIDxZ2 are multiplied by PIDxK3 and the result is added to the
accumulator, the current value from PIDxZ1 is loaded into PIDxZ2. The same is true
for PIDxZ1 and the current SET-IN value.
PIC16(L)F1615/9
Within the controller, the input is subtracted from a pre- To operate the module in PID controller mode, perform
programmed set point to get an error value. This error the following steps:
value, along with the previous two error values (if any), 1. Set the MODE<2:0> bits of the PIDxCON regis-
are multiplied by user-input coefficients and the results ter to ‘101’, then set the EN bit of the PIDxCON
of these multiplications are added together to make up register.
the output. If the MODE<2:0> bits of the PIDxCON reg-
2. Write the previously calculated K1, K2, and K3
ister = 101, the PID output is equal to the current output
values to the PIDxK1, PIDxK2, and PIDxK3
added to any previous outputs.
registers, respectively.
The three user-input coefficients (K1, K2, and K3) are 3. Write the desired set point that the input will be
derived from the three classic PID coefficients Kp, Ki, compared against to the PIDxSET registers.
and Kd, and must be calculated prior to using the PID
4. Write the high byte of the value from the external
module.
system to PIDxINH. Then write the low byte of
1. K1 is the coefficient that is multiplied with the the value from the external system to PIDxINL.
current error (SET-IN). It is defined by the following This will begin the calculation and set the BUSY
equation: bit of the PIDxCON register.
5. Either poll the BUSY bit of the PIDxCON register
EQUATION 32-1: to check for it clearing or wait for the PIDxDIF
interrupt to trigger, indicating that the operation
has completed.
Kd 6. Read the PIDxOUT registers for the output
K1 = Kp + Ki  T + ------- value. If the PID was in Accumulation mode,
T
PIDxOUT will contain the accumulation of the
output added to the previous outputs, otherwise,
Note: T is the sampling period. it will contain only the latest output.
7. For proper PID operation, this output needs to
be applied to the external system before the
2. K2 is the coefficient that is multiplied with the next input to the PID is applied. This is to ensure
previous iteration’s error (Z1). Where T is the that the system can adjust based on the PID
sampling period, it is defined by the following controller’s feedback before the next calculation
equation: is made.
Note: The BUSY bit of the PIDxCON register
EQUATION 32-2: goes high as soon as PIDxINL is written
and remains high until all computation is
complete. Until the BUSY bit goes low, the
PIDxOUT values are not valid, and none
K2 = –  Kp + ----------
2Kd of the registers associated with the PID
 T  module should be written to, as any such
writes will corrupt the calculation.
Note: T is the sampling period. 32.1.2 CONTEXT SAVING

It is possible to save the current state of the PID
controller in software and restore it at a later time. In
3. K3 is the coefficient that is multiplied with the
order to perform this, a calculation must not currently
error that occurred two iterations previous to the
be active (BUSY = 0). Saving the PIDxOUT, PIDxZ1,
current one (Z2). It is defined by the following
and PIDxZ2 values elsewhere in memory will save the
equation:
current state of the PID controller, although it may be
desirable to also save PIDxK1, PIDxK2, PIDxK3, and/
EQUATION 32-3: or PIDxSET, depending on the application. At the
desired later time, these values can be written back into
their respective registers, writing PIDxINL last, and the
Kd PID will continue from its previous state.
K3 = -------
T
Note: T is the sampling period.

PIC16(L)F1615/9
32.2 Add and Multiply Mode Setup and
Operation
The PID module can also be used to perform 16-bit
Add and Multiply computations. When the MODE<2:0>
bits of the PIDxCON register are equal to ‘000’, ‘001’,
‘010’, or ‘011’, the module is in Add and Multiply mode.
The data flow for the multiply and add operation is
illustrated in Figure 32-2.
FIGURE 32-2: PID MODULE BASIC DATA FLOW BLOCK DIAGRAM, ADD AND MULTIPLY
MODES
Rev. 10-000228A
4/7/2015
0
PIDxACC
PIDxIN PIDxK1
MODE<0> 0 1
+ +
Adder Multiplier + Adder PIDxOUT
+
PIDxSET
All Add and Multiply modes perform operations of the In order to perform an Add and Multiply operation,
following form. perform the following steps:
1. Set the MODE<2:0> bits of the PIDxCON
EQUATION 32-4: register to one of the four Add/Multiply modes,
depending on which form of the calculation is
desired, then set the EN bit of the PIDxCON
OUTPUT =  A + B   C register.
2. Write the value of C to the PIDxK1H/L register
pair and the value of B to the PIDxSETH/L reg-
Note: A = PIDxIN, B = PICxSET, and C = PIDxK1. ister pair, as well as the high byte of A to the
PIDxINH register.
3. Finally, write the low byte of A to the PIDxINL
The four different Add and Multiply modes are: register. This will begin the mathematical
• MODE<2:0> = 000: Inputs are unsigned, and the operation and set the BUSY bit of the PIDxCON
output does not accumulate register.
• MODE<2:0> = 001: Inputs are unsigned, and the 4. Either poll the BUSY bit of the PIDxCON register
output accumulates with previous outputs to check for it clearing or wait for the PIDxDIF
• MODE<2:0> = 010: Inputs are signed, and the interrupt to trigger, indicating that the operation
output does not accumulate has completed.
• MODE<2:0> = 011: Inputs are signed, and the 5. Read the PIDxOUT registers for the result of the
output accumulates with previous outputs calculation. In accumulation modes, the
PIDxOUT register will hold any previous values
added to the current calculation’s value. In non-
accumulation modes, the PIDxOUT register will
just hold the current calculation’s value.
These modes can also be used to perform 16-bit
addition (by setting the C term in the above equation to
1) or 16-bit multiplication (by setting A or B to 0).

PIC16(L)F1615/9
32.3 Interrupts
The PID module has two interrupts, indicated by the
interrupt flags PIDxDIF and PIDxEIF in the PIR5
register, and controlled by the interrupt control bits
PIDxDIE and PIDxEIE, respectively, in the PIE5 register.
The PIDxDIF interrupt triggers at the successful
completion of a calculation, when the BUSY bit of the
PIDxCON register goes low.
The PIDxEIF interrupt triggers when there is an error in
the PID or multiply and add calculation, specifically an
overflow error on the output value.
32.4 Handling Error Overflow

If a calculation causes an overflow of the value in the
OUT registers, the value in said registers will roll over
and the PIDxEIF interrupt will trigger. In the case of a
PID calculation, this indicates that the error has
outpaced the PID’s capability to correct for the error of
the system. In this case, it is recommended to ‘saturate’
the OUT registers in software whenever the PIDxEIF
interrupt is set as part of the Interrupt Service Routine
(IRS), as shown in Example 32-1.
EXAMPLE 32-1: HANDLING PID

OVERFLOWS
//Interrupt service routine
void interrupt ISR(void)
IF (PIR5BITS.PID1EIF==1&&PIE5BITS.PID1EIE==1)
{
//saturate the PID1OUT registers
PID1OUTHH=0xFF;
PID1OUTHL=0xFF;
PID1OUTLH=0xFF;
PID1OUTLL=0xFF;
PID1OUTHH=0xFF;
//clear the interrupt flag
PIR5bits.PID1EIF=0;
}

PIC16(L)F1615/9
32.5 PID Control Registers
Long bit name prefixes for the 16-bit PID peripherals
are shown in Table 32-1. Refer to Section 1.1 “Regis-
ter and Bit Naming Conventions” for more informa-
tion
TABLE 32-1:
PID1 PID1
REGISTER 32-1: PIDxCON: PID CONFIGURATION REGISTER

R/W-0/0 R/HS/HC-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
EN BUSY — — — MODE<2:0>
bit 7 bit 0
Legend:
u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets
bit 7 EN: PID Module Enable bit

1 = PID module is enabled
0 = PID module is disabled
bit 6 BUSY: PID module is currently calculating
bit 2-0 MODE<2:0>: PID Mode Control bits
11x = Reserved. Do not use.
101 = PID output is the calculated output (current error plus accumulated previous errors) in 2’s
complement notation
100 = Reserved. Do not use.
011 = (IN<15:0>+SET<15:0>)*K1<15:0> 2’s complement signed inputs, with accumulation
010 = (IN<15:0>+SET<15:0>)*K1<15:0> 2’s complement signed inputs, without accumulation
001 = (IN<15:0>+SET<15:0>)*K1<15:0> unsigned inputs, with accumulation
000 = (IN<15:0>+SET<15:0>)*K1<15:0> unsigned inputs, without accumulation

PIC16(L)F1615/9
REGISTER 32-2: PIDxINH: PID INPUT HIGH REGISTER

IN<15:8>
bit 7 bit 0
Legend:
bit 7-0 IN<15:8>: IN upper eight bits. IN is the 16-bit input from the control system to the PID module
REGISTER 32-3: PIDxINL: PID INPUT LOW REGISTER

IN<7:0>
bit 7 bit 0
Legend:
bit 7-0 IN<7:0>: IN lower eight bits. IN is the 16-bit input from the control system to the PID module
REGISTER 32-4: PIDxSETH: PID SET POINT HIGH REGISTER

SET<15:8>
bit 7 bit 0
Legend:
bit 7-0 SET<15:8>: SET upper eight bits. SET is the 16-bit user-controlled variable that the input from the control system is
compared against to determine the error in the system
REGISTER 32-5: PIDxSETL: PID SET POINT LOW REGISTER

SET<7:0>
bit 7 bit 0
Legend:
bit 7-0 SET<7:0>: SET lower eight bits. SET is the 16-bit user-controlled variable that the input from the control system is
compared against to determine the error in the system

PIC16(L)F1615/9
REGISTER 32-6: PIDxK1H: PID K1 HIGH REGISTER

K1<15:8>
bit 7 bit 0
Legend:
bit 7-0 K1<15:8>: K1 upper eight bits. K1 is the 16-bit user-controlled coefficient calculated from Kp + Ki + Kd
REGISTER 32-7: PIDxK1L: PID K1 LOW REGISTER

K1<7:0>
bit 7 bit 0
Legend:
bit 7-0 K1<7:0>: K1 lower eight bits. K1 is the 16-bit user-controlled coefficient calculated from Kp + Ki + Kd

K2<15:8>
bit 7 bit 0
Legend:
bit 7-0 K2<15:8>: K2 upper eight bits. K2 is the 16-bit user-controlled coefficient calculated from -(Kp + 2Kd)

K2<7:0>
bit 7 bit 0
Legend:
bit 7-0 K2<7:0>: K2 lower eight bits. K2 is the 16-bit user-controlled coefficient calculated from -(Kp + 2Kd)

PIC16(L)F1615/9

K3<15:8>
bit 7 bit 0
Legend:
bit 7-0 K3<15:8>: K3 upper eight bits. K3 is the 16-bit user-controlled coefficient calculated from Kd

K3<7:0>
bit 7 bit 0
Legend:
bit 7-0 K3<7:0>: K3 lower eight bits. K3 is the 16-bit user-controlled coefficient calculated from Kd

PIC16(L)F1615/9
REGISTER 32-12: PIDxOUTU: PID OUTPUT UPPER REGISTER

U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — OUT<35:32>
bit 7 bit 0
Legend:

bit 3-0 OUT<35:32>: Bits <35:32> of OUT. OUT is the output value of the PID after completing the designated
calculation on the specified inputs.
REGISTER 32-13: PIDxOUTHH: PID OUTPUT HIGH HIGH REGISTER

OUT<31:24>
bit 7 bit 0
Legend:

PIC16(L)F1615/9
REGISTER 32-14: PIDxOUTHL: PID OUTPUT HIGH LOW REGISTER

OUT<23:16>
bit 7 bit 0
Legend:
REGISTER 32-15: PIDxOUTLH: PID OUTPUT LOW HIGH REGISTER

OUT<15:8>
bit 7 bit 0
Legend:
REGISTER 32-16: PIDxOUTLL: PID OUTPUT LOW LOW REGISTER

OUT<7:0>
bit 7 bit 0
Legend:

PIC16(L)F1615/9
REGISTER 32-17: PIDxZ1U: PID Z1 UPPER REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0
— — — — — — — Z116
bit 7 bit 0
Legend:

bit 0 Z116: Bit 16 of Z1. In PID mode, Z1 is the value of the error (IN minus SET) from the previous iteration
of the PID control loop.
REGISTER 32-18: PIDxZ1H: PID Z1 HIGH REGISTER

Z1<15:8>
bit 7 bit 0
Legend:
bit 7-0 Z1<15:8>: Bits <15:8> of Z1. In PID mode, Z1 is the value of the error (IN minus SET) from the previ-
ous iteration of the PID control loop.
REGISTER 32-19: PIDxZ1L: PID Z1 LOW REGISTER

Z1<7:0>
bit 7 bit 0
Legend:
bit 7-0 Z1<7:0>: Bits <7:0> of Z1. In PID mode, Z1 is the value of the error (IN minus SET) from the previous
iteration of the PID control loop.

PIC16(L)F1615/9
REGISTER 32-20: PIDxZ2U: PID Z2 UPPER REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0
— — — — — — — Z216
bit 7 bit 0
Legend:

bit 0 Z216: Bit 16 of Z2. In PID mode, Z2 is the value of the error (IN minus SET) from the previous iteration
of the PID control loop.
REGISTER 32-21: PIDxZ2H: PID Z2 HIGH REGISTER

Z2<15:8>
bit 7 bit 0
Legend:
bit 7-0 Z2<15:8>: Bits <15:8> of Z2. In PID mode, Z2 is the value of the error (IN minus SET) from the
previous iteration of the PID control loop.
REGISTER 32-22: PIDxZ2L: PID Z2 LOW REGISTER

Z2<7:0>
bit 7 bit 0
Legend:
bit 7-0 Z2<7:0>: Bits <7:0> of Z2. In PID mode, Z2 is the value of the error (IN minus SET) from the previous
iteration of the PID control loop.

PIC16(L)F1615/9
REGISTER 32-23: PIDxACCU: PID ACCUMULATOR UPPER REGISTER

U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — — ACC<34:32>
bit 7 bit 0
Legend:

bit 2-0 ACC<34:32>: Bits <34:32> of ACC. ACC is the accumulator register in which all of the multiplier
results for the PID are accumulated before being written to the output.
REGISTER 32-24: PIDxACCHH: PID ACCUMULATOR HIGH HIGH REGISTER

ACC<31:24>
bit 7 bit 0
Legend:
REGISTER 32-25: PIDxACCHL: PID ACCUMULATOR HIGH LOW REGISTER

ACC<23:16>
bit 7 bit 0
Legend:

PIC16(L)F1615/9
REGISTER 32-26: PIDxACCLH: PID ACCUMULATOR LOW HIGH REGISTER

ACC<15:8>
bit 7 bit 0
Legend:
bit 7-0 ACC<15:8>: Bits <15:8> of ACC. ACC is the accumulator register in which all of the multiplier results
for the PID are accumulated before being written to the output.
REGISTER 32-27: PIDxACCLL: PID ACCUMULATOR LOW LOW REGISTER

ACC<7:0>
bit 7 bit 0
Legend:
bit 7-0 ACC<7:0>: Bits <7:0> of ACC. ACC is the accumulator register in which all of the multiplier results for
the PID are accumulated before being written to the output.

PIC16(L)F1615/9
TABLE 32-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE PID MODULE
Register
on page
PID1ACCU — — — — — ACC<34:32> 493
PID1ACCHH ACC<31:24> 493
PID1ACCHL ACC<23:16> 493
PID1ACCLH ACC<15:8> 494
PID1ACCLL ACC<7:0> 494
PID1CON EN BUSY — — — MODE<2:0> 485
PID1INH IN<15:8> 486
PID1INL IN<7:0> 486
PID1K1H K1<15:8> 487
PID1K1L K1<7:0> 487
PID1K2H K2<15:8> 487
PID1K2L K2<7:0> 487
PID1K3H K3<15:8> 488
PID1K3L K3<7:0> 488
PID1OUTU — — — — OUT<35:32> 489
PID1OUTHH OUT<31:24> 489
PID1OUTHL OUT<23:16> 490
PID1OUTLH OUT<15:8> 490
PID1OUTLL OUT<7:0> 490
PID1SETH SET<15:8> 486
PID1SETL SET<7:0> 486
PID1Z1U — — — — — — — Z116 491
PID1Z1H Z1<15:8> 491
PID1Z1L Z1<7:0> 491
PID1Z2U — — — — — — — Z216 492
PID1Z2H Z2<15:8> 492
PID1Z2L Z2<7:0> 492
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the PID module.

PIC16(L)F1615/9
33.0 IN-CIRCUIT SERIAL 33.3 Common Programming Interfaces
PROGRAMMING™ (ICSP™) Connection to a target device is typically done
ICSP™ programming allows customers to manufacture through an ICSP™ header. A commonly found
circuit boards with unprogrammed devices. Programming connector on development tools is the RJ-11 in the
can be done after the assembly process allowing the 6P6C (6-pin, 6-connector) configuration. See
device to be programmed with the most recent firmware Figure 33-1.
or a custom firmware. Five pins are needed for ICSP™
programming: FIGURE 33-1: ICD RJ-11 STYLE
• ICSPCLK CONNECTOR INTERFACE
• ICSPDAT
• MCLR/VPP
• VDD
• VSS
ICSPDAT
In Program/Verify mode the program memory, user IDs 2 4 6 NC
VDD
and the Configuration Words are programmed through ICSPCLK
serial communications. The ICSPDAT pin is a bidirec- 1 3 5
Target
tional I/O used for transferring the serial data and the VPP/MCLR PC Board
VSS
ICSPCLK pin is the clock input. For more information on Bottom Side
ICSP™ refer to the “PIC12(L)F1612/PIC16(L)F161X
Memory Programming Specification” (DS40001720).
Pin Description*
33.1 High-Voltage Programming Entry 1 = VPP/MCLR
Mode 2 = VDD Target
3 = VSS (ground)
The device is placed into High-Voltage Programming
Entry mode by holding the ICSPCLK and ICSPDAT 4 = ICSPDAT
pins low then raising the voltage on MCLR/VPP to VIHH. 5 = ICSPCLK

6 = No Connect
33.2 Low-Voltage Programming Entry

Mode Another connector often found in use with the PICkit™
programmers is a standard 6-pin header with 0.1 inch
The Low-Voltage Programming Entry mode allows the
spacing. Refer to Figure 33-2.
PIC® Flash MCUs to be programmed using VDD only,
without high voltage. When the LVP bit of Configuration
Words is set to ‘1’, the ICSP Low-Voltage Programming
Entry mode is enabled. To disable the Low-Voltage
ICSP mode, the LVP bit must be programmed to ‘0’.
Entry into the Low-Voltage Programming Entry mode
requires the following steps:
1. MCLR is brought to VIL.
2. A 32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be
maintained.
If low-voltage programming is enabled (LVP = 1), the
MCLR Reset function is automatically enabled and
cannot be disabled. See Section6.5 “MCLR” for more
information.
The LVP bit can only be reprogrammed to ‘0’ by using
the High-Voltage Programming mode.

PIC16(L)F1615/9
FIGURE 33-2: PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE
Rev. 10-000128A
7/30/2013
Pin 1 Indicator
Pin Description*
1 = VPP/MCLR
1
2
2 = VDD Target
3
4 3 = VSS (ground)
5
6 4 = ICSPDAT
5 = ICSPCLK
6 = No connect
* The 6-pin header (0.100" spacing) accepts 0.025" square pins
For additional interface recommendations, refer to your It is recommended that isolation devices be used to
specific device programmer manual prior to PCB separate the programming pins from other circuitry.
design. The type of isolation is highly dependent on the specific
application and may include devices such as resistors,
diodes, or even jumpers. See Figure 33-3 for more
information.
FIGURE 33-3: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING
Rev. 10-000129A
7/30/2013
External Device to be
Programming VDD Programmed
Signals
VDD VDD
VPP MCLR/VPP
VSS VSS
Data ICSPDAT
Clock ICSPCLK
* * *
To Normal Connections
* Isolation devices (as required).

PIC16(L)F1615/9
34.0 INSTRUCTION SET SUMMARY • One additional instruction cycle will be used when
any instruction references an indirect file register
Each instruction is a 14-bit word containing the opera- and the file select register is pointing to program
tion code (opcode) and all required operands. The memory.
opcodes are broken into three broad categories.
One instruction cycle consists of 4 oscillator cycles; for
• Byte Oriented an oscillator frequency of 4 MHz, this gives a nominal
• Bit Oriented instruction execution rate of 1 MHz.
• Literal and Control All instruction examples use the format ‘0xhh’ to
The literal and control category contains the most represent a hexadecimal number, where ‘h’ signifies a
varied instruction word format. hexadecimal digit.
Table 34-3 lists the instructions recognized by the
MPASMTM assembler. 34.1 Read-Modify-Write Operations
All instructions are executed within a single instruction Any instruction that specifies a file register as part of
cycle, with the following exceptions, which may take the instruction performs a Read-Modify-Write (R-M-W)
two or three cycles: operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
• Subroutine takes two cycles (CALL, CALLW)
tion, or the destination designator ‘d’. A read operation
• Returns from interrupts or subroutines take two
is performed on a register even if the instruction writes
cycles (RETURN, RETLW, RETFIE)
to that register.
• Program branching takes two cycles (GOTO, BRA,
BRW, BTFSS, BTFSC, DECFSZ, INCSFZ)
TABLE 34-1: OPCODE FIELD DESCRIPTIONS

Field Description
f Register file address (0x00 to 0x7F)
W Working register (accumulator)
b Bit address within an 8-bit file register
k Literal field, constant data or label
x Don’t care location (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
n FSR or INDF number. (0-1)
mm Pre-post increment-decrement mode
selection
TABLE 34-2: ABBREVIATION DESCRIPTIONS

Field Description
PC Program Counter
TO Time-Out bit
C Carry bit
DC Digit Carry bit
Z Zero bit
PD Power-Down bit

PIC16(L)F1615/9
FIGURE 34-1: GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13 8 7 6 0
OPCODE d f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations

13 10 9 7 6 0
OPCODE b (BIT #) f (FILE #)
b = 3-bit bit address

f = 7-bit file register address
Literal and control operations

General
13 8 7 0
OPCODE k (literal)
k = 8-bit immediate value
CALL and GOTO instructions only

13 11 10 0
OPCODE k (literal)
MOVLP instruction only

13 7 6 0
OPCODE k (literal)
MOVLB instruction only

13 5 4 0
OPCODE k (literal)
BRA instruction only

13 9 8 0
OPCODE k (literal)
FSR Offset instructions

13 7 6 5 0
OPCODE n k (literal)
n = appropriate FSR
FSR Increment instructions

13 3 2 1 0
OPCODE n m (mode)
n = appropriate FSR
m = 2-bit mode value
OPCODE only
13 0
OPCODE

PIC16(L)F1615/9
TABLE 34-3: ENHANCED MID-RANGE INSTRUCTION SET
Mnemonic, 14-Bit Opcode Status
Description Cycles Notes
Operands MSb LSb Affected
BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF f, d Add W and f 1 00 0111 dfff ffff C, DC, Z 2
ADDWFC f, d Add with Carry W and f 1 11 1101 dfff ffff C, DC, Z 2
ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 2
ASRF f, d Arithmetic Right Shift 1 11 0111 dfff ffff C, Z 2
LSLF f, d Logical Left Shift 1 11 0101 dfff ffff C, Z 2
LSRF f, d Logical Right Shift 1 11 0110 dfff ffff C, Z 2
CLRF f Clear f 1 00 0001 lfff ffff Z 2
CLRW – Clear W 1 00 0001 0000 00xx Z
COMF f, d Complement f 1 00 1001 dfff ffff Z 2
DECF f, d Decrement f 1 00 0011 dfff ffff Z 2
INCF f, d Increment f 1 00 1010 dfff ffff Z 2
IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 2
MOVF f, d Move f 1 00 1000 dfff ffff Z 2
MOVWF f Move W to f 1 00 0000 1fff ffff 2
RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 2
RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 2
SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C, DC, Z 2
SUBWFB f, d Subtract with Borrow W from f 1 11 1011 dfff ffff C, DC, Z 2
SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 2
XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 2
BYTE ORIENTED SKIP OPERATIONS
DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1, 2

INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF f, b Bit Clear f 1 01 00bb bfff ffff 2

BSF f, b Bit Set f 1 01 01bb bfff ffff 2
BIT-ORIENTED SKIP OPERATIONS

BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 1, 2
BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 1, 2
LITERAL OPERATIONS
ADDLW k Add literal and W 1 11 1110 kkkk kkkk C, DC, Z
ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z
IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z
MOVLB k Move literal to BSR 1 00 0000 001k kkkk
MOVLP k Move literal to PCLATH 1 11 0001 1kkk kkkk
MOVLW k Move literal to W 1 11 0000 kkkk kkkk
SUBLW k Subtract W from literal 1 11 1100 kkkk kkkk C, DC, Z
XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one
additional instruction cycle.

PIC16(L)F1615/9
TABLE 34-3: ENHANCED MID-RANGE INSTRUCTION SET (CONTINUED)
Mnemonic, 14-Bit Opcode Status
Description Cycles Notes
Operands MSb LSb Affected
CONTROL OPERATIONS
BRA k Relative Branch 2 11 001k kkkk kkkk
BRW – Relative Branch with W 2 00 0000 0000 1011
CALL k Call Subroutine 2 10 0kkk kkkk kkkk
CALLW – Call Subroutine with W 2 00 0000 0000 1010
GOTO k Go to address 2 10 1kkk kkkk kkkk
RETFIE k Return from interrupt 2 00 0000 0000 1001
RETLW k Return with literal in W 2 11 0100 kkkk kkkk
RETURN – Return from Subroutine 2 00 0000 0000 1000
INHERENT OPERATIONS
CLRWDT – Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD
NOP – No Operation 1 00 0000 0000 0000
OPTION – Load OPTION_REG register with W 1 00 0000 0110 0010
RESET – Software device Reset 1 00 0000 0000 0001
SLEEP – Go into Standby mode 1 00 0000 0110 0011 TO, PD
TRIS f Load TRIS register with W 1 00 0000 0110 0fff
C-COMPILER OPTIMIZED
ADDFSR n, k Add Literal k to FSRn 1 11 0001 0nkk kkkk
MOVIW n mm Move Indirect FSRn to W with pre/post inc/dec 1 00 0000 0001 0nmm Z 2, 3
modifier, mm kkkk
k[n] Move INDFn to W, Indexed Indirect. 1 11 1111 0nkk 1nmm Z 2
MOVWI n mm Move W to Indirect FSRn with pre/post inc/dec 1 00 0000 0001 kkkk 2, 3
modifier, mm
k[n] Move W to INDFn, Indexed Indirect. 1 11 1111 1nkk 2
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
3: See Table in the MOVIW and MOVWI instruction descriptions.

PIC16(L)F1615/9
34.2 Instruction Descriptions
ADDFSR Add Literal to FSRn ANDLW AND literal with W

Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW k
Operands: -32  k  31 Operands: 0  k  255
n  [ 0, 1]
Operation: (W) .AND. (k)  (W)
Operation: FSR(n) + k  FSR(n)
Status Affected: Z
Status Affected: None
Description: The contents of W register are
Description: The signed 6-bit literal ‘k’ is added to AND’ed with the 8-bit literal ‘k’. The
the contents of the FSRnH:FSRnL result is placed in the W register.
register pair.
FSRn is limited to the range 0000h -

FFFFh. Moving beyond these bounds
will cause the FSR to wrap-around.
ADDLW Add literal and W ANDWF AND W with f

Syntax: [ label ] ADDLW k Syntax: [ label ] ANDWF f,d
Operands: 0  k  255 Operands: 0  f  127
d 0,1
Operation: (W) + k  (W)
Operation: (W) .AND. (f)  (destination)
Status Affected: C, DC, Z
Status Affected: Z
Description: The contents of the W register are
added to the 8-bit literal ‘k’ and the Description: AND the W register with register ‘f’. If
result is placed in the W register. ‘d’ is ‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
ADDWF Add W and f ASRF Arithmetic Right Shift

Syntax: [ label ] ADDWF f,d Syntax: [ label ] ASRF f {,d}
Operands: 0  f  127 Operands: 0  f  127
d 0,1 d [0,1]
Operation: (W) + (f)  (destination) Operation: (f<7>) dest<7>
(f<7:1>)  dest<6:0>,
(f<0>)  C,
Description: Add the contents of the W register
Status Affected: C, Z
with register ‘f’. If ‘d’ is ‘0’, the result is
stored in the W register. If ‘d’ is ‘1’, the Description: The contents of register ‘f’ are shifted
result is stored back in register ‘f’. one bit to the right through the Carry
flag. The MSb remains unchanged. If
‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in
register ‘f’.
ADDWFC ADD W and CARRY bit to f register f C
Syntax: [ label ] ADDWFC f {,d}
Operands: 0  f  127
d [0,1]
Operation: (W) + (f) + (C)  dest
Description: Add W, the Carry flag and data mem-
ory location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.

PIC16(L)F1615/9
BCF Bit Clear f BTFSC Bit Test f, Skip if Clear
Syntax: [ label ] BCF f,b Syntax: [ label ] BTFSC f,b
Operands: 0  f  127 Operands: 0  f  127

0b7 0b7
Operation: 0  (f<b>) Operation: skip if (f<b>) = 0
Status Affected: None Status Affected: None
Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the next
instruction is discarded, and a NOP is
executed instead, making this a 2-
cycle instruction.
BRA Relative Branch BTFSS Bit Test f, Skip if Set

Syntax: [ label ] BRA label Syntax: [ label ] BTFSS f,b
[ label ] BRA $+k Operands: 0  f  127
Operands: -256  label - PC + 1  255 0b<7
-256  k  255 Operation: skip if (f<b>) = 1
Operation: (PC) + 1 + k  PC Status Affected: None
Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next
Description: Add the signed 9-bit literal ‘k’ to the instruction is executed.
PC. Since the PC will have incre- If bit ‘b’ is ‘1’, then the next
mented to fetch the next instruction, instruction is discarded and a NOP is
the new address will be PC + 1 + k. executed instead, making this a
This instruction is a 2-cycle instruc- 2-cycle instruction.
tion. This branch has a limited range.
CALL Call Subroutine

BRW Relative Branch with W
Syntax: [ label ] CALL k
Syntax: [ label ] BRW
Operands: 0  k  2047
Operands: None
Operation: (PC)+ 1 TOS,
Operation: (PC) + (W)  PC
k  PC<10:0>,
Status Affected: None (PCLATH<6:3>)  PC<14:11>
Description: Add the contents of W (unsigned) to Status Affected: None
the PC. Since the PC will have incre-
Description: Call Subroutine. First, return address
mented to fetch the next instruction,
(PC + 1) is pushed onto the stack.
the new address will be PC + 1 + (W).
The 11-bit immediate address is
This instruction is a 2-cycle instruc-
loaded into PC bits <10:0>. The upper
tion.
bits of the PC are loaded from
PCLATH. CALL is a 2-cycle instruc-
tion.
BSF Bit Set f

Syntax: [ label ] BSF f,b
0b7
Operation: 1  (f<b>)
Description: Bit ‘b’ in register ‘f’ is set.

PIC16(L)F1615/9
COMF Complement f
CALLW Subroutine Call With W
Syntax: [ label ] COMF f,d
Syntax: [ label ] CALLW Operands: 0  f  127
Operands: None d  [0,1]
Operation: (PC) +1  TOS, Operation: (f)  (destination)
(W)  PC<7:0>, Status Affected: Z
(PCLATH<6:0>) PC<14:8>
Description: The contents of register ‘f’ are com-
plemented. If ‘d’ is ‘0’, the result is
Status Affected: None stored in W. If ‘d’ is ‘1’, the result is
Description: Subroutine call with W. First, the stored back in register ‘f’.
return address (PC + 1) is pushed
onto the return stack. Then, the con-
tents of W is loaded into PC<7:0>,
and the contents of PCLATH into
PC<14:8>. CALLW is a 2-cycle
instruction.
DECF Decrement f
CLRF Clear f
Syntax: [ label ] DECF f,d
Syntax: [ label ] CLRF f
Operands: 0  f  127 d  [0,1]
Operation: 00h  (f) Operation: (f) - 1  (destination)
1Z
Status Affected: Z
Status Affected: Z
Description: Decrement register ‘f’. If ‘d’ is ‘0’, the
Description: The contents of register ‘f’ are cleared result is stored in the W register. If ‘d’
and the Z bit is set. is ‘1’, the result is stored back in regis-
ter ‘f’.
CLRW Clear W
DECFSZ Decrement f, Skip if 0
Syntax: [ label ] CLRW
Operands: None Syntax: [ label ] DECFSZ f,d
Operation: 00h  (W) Operands: 0  f  127

1Z d  [0,1]
Status Affected: Z Operation: (f) - 1  (destination);

skip if result = 0
Description: W register is cleared. Zero bit (Z) is
set. Status Affected: None
Description: The contents of register ‘f’ are decre-
mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
CLRWDT Clear Watchdog Timer is placed back in register ‘f’.
If the result is ‘1’, the next instruction is
Syntax: [ label ] CLRWDT
executed. If the result is ‘0’, then a
Operands: None NOP is executed instead, making it a
Operation: 00h  WDT 2-cycle instruction.
0  WDT prescaler,
1  TO
1  PD
Status Affected: TO, PD
Description: CLRWDT instruction resets the Watch-
dog Timer. It also resets the prescaler
of the WDT.
Status bits TO and PD are set.

PIC16(L)F1615/9
GOTO Unconditional Branch IORWF Inclusive OR W with f

Syntax: [ label ] GOTO k Syntax: [ label ] IORWF f,d
Operands: 0  k  2047 Operands: 0  f  127
d  [0,1]
Operation: k  PC<10:0>
PCLATH<6:3>  PC<14:11> Operation: (W) .OR. (f)  (destination)
Status Affected: None Status Affected: Z
Description: GOTO is an unconditional branch. The Description: Inclusive OR the W register with regis-
11-bit immediate value is loaded into ter ‘f’. If ‘d’ is ‘0’, the result is placed in
PC bits <10:0>. The upper bits of PC the W register. If ‘d’ is ‘1’, the result is
are loaded from PCLATH<4:3>. GOTO placed back in register ‘f’.
is a 2-cycle instruction.
LSLF Logical Left Shift

INCF Increment f
Syntax: [ label ] LSLF f {,d}
Syntax: [ label ] INCF f,d
Operands: 0  f  127 d [0,1]
d  [0,1]
Operation: (f<7>)  C
Operation: (f) + 1  (destination) (f<6:0>)  dest<7:1>
0  dest<0>
Status Affected: Z
Description: The contents of register ‘f’ are incre- Status Affected: C, Z
mented. If ‘d’ is ‘0’, the result is placed Description: The contents of register ‘f’ are shifted
in the W register. If ‘d’ is ‘1’, the result one bit to the left through the Carry flag.
is placed back in register ‘f’. A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’,
the result is placed in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
INCFSZ Increment f, Skip if 0 C register f 0
Syntax: [ label ] INCFSZ f,d
d  [0,1]
LSRF Logical Right Shift
Operation: (f) + 1  (destination),
skip if result = 0 Syntax: [ label ] LSRF f {,d}
Status Affected: None Operands: 0  f  127

d [0,1]
Description: The contents of register ‘f’ are incre-
mented. If ‘d’ is ‘0’, the result is placed Operation: 0  dest<7>
in the W register. If ‘d’ is ‘1’, the result (f<7:1>)  dest<6:0>,
is placed back in register ‘f’. (f<0>)  C,
If the result is ‘1’, the next instruction is Status Affected: C, Z
executed. If the result is ‘0’, a NOP is
Description: The contents of register ‘f’ are shifted
executed instead, making it a 2-cycle
one bit to the right through the Carry
instruction.
flag. A ‘0’ is shifted into the MSb. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is stored back in register ‘f’.
IORLW Inclusive OR literal with W
0 register f C
Syntax: [ label ] IORLW k
Operation: (W) .OR. k  (W)
Status Affected: Z
OR’ed with the 8-bit literal ‘k’. The
result is placed in the W register.

PIC16(L)F1615/9
MOVF Move f MOVIW Move INDFn to W

Syntax: [ label ] MOVF f,d Syntax: [ label ] MOVIW ++FSRn
[ label ] MOVIW --FSRn
[ label ] MOVIW FSRn++
d  [0,1]
[ label ] MOVIW FSRn--
Operation: (f)  (dest) [ label ] MOVIW k[FSRn]
Status Affected: Z Operands: n  [0,1]
Description: The contents of register f is moved to mm  [00,01, 10, 11]
a destination dependent upon the -32  k  31
status of d. If d = 0, destination is W Operation: INDFn  W
register. If d = 1, the destination is file Effective address is determined by
register f itself. d = 1 is useful to test a • FSR + 1 (preincrement)
file register since status flag Z is • FSR - 1 (predecrement)
affected. • FSR + k (relative offset)
Words: 1 After the Move, the FSR value will be
either:
Cycles: 1
• FSR + 1 (all increments)
Example: MOVF FSR, 0 • FSR - 1 (all decrements)
After Instruction • Unchanged
W = value in FSR register Status Affected: Z
Z = 1
Mode Syntax mm
Preincrement ++FSRn 00
Predecrement --FSRn 01
Postincrement FSRn++ 10
Postdecrement FSRn-- 11
Description: This instruction is used to move data

between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Note: The INDFn registers are not

physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.

FFFFh. Incrementing/decrementing it
beyond these bounds will cause it to
wrap-around.
MOVLB Move literal to BSR

Syntax: [ label ] MOVLB k
Operation: k  BSR
Description: The 5-bit literal ‘k’ is loaded into the
Bank Select Register (BSR).

PIC16(L)F1615/9
MOVLP Move literal to PCLATH MOVWI Move W to INDFn

Syntax: [ label ] MOVLP k Syntax: [ label ] MOVWI ++FSRn
[ label ] MOVWI --FSRn
[ label ] MOVWI FSRn++
Operation: k  PCLATH [ label ] MOVWI FSRn--
Status Affected: None [ label ] MOVWI k[FSRn]
Description: The 7-bit literal ‘k’ is loaded into the Operands: n  [0,1]
PCLATH register. mm  [00,01, 10, 11]
-32  k  31
Operation: W  INDFn
MOVLW Move literal to W Effective address is determined by
• FSR + 1 (preincrement)
Syntax: [ label ] MOVLW k
• FSR - 1 (predecrement)
Operands: 0  k  255 • FSR + k (relative offset)
Operation: k  (W) After the Move, the FSR value will be
either:
Status Affected: None • FSR + 1 (all increments)
Description: The 8-bit literal ‘k’ is loaded into W reg- • FSR - 1 (all decrements)
ister. The “don’t cares” will assemble as Unchanged
‘0’s. Status Affected: None
Words: 1
Cycles: 1 Mode Syntax mm
Example: MOVLW 0x5A Preincrement ++FSRn 00
After Instruction Predecrement --FSRn 01
W = 0x5A
Postincrement FSRn++ 10
Postdecrement FSRn-- 11
MOVWF Move W to f
Syntax: [ label ] MOVWF f
Description: This instruction is used to move data
Operands: 0  f  127 between W and one of the indirect
Operation: (W)  (f) registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Description: Move data from W register to register
‘f’. Note: The INDFn registers are not
physical registers. Any instruction that
Words: 1
accesses an INDFn register actually
Cycles: 1 accesses the register at the address
Example: MOVWF OPTION_REG specified by the FSRn.
Before Instruction
OPTION_REG = 0xFF
FFFFh. Incrementing/decrementing it
W = 0x4F
beyond these bounds will cause it to
After Instruction
wrap-around.
OPTION_REG = 0x4F
W = 0x4F
The increment/decrement operation on
FSRn WILL NOT affect any Status bits.

PIC16(L)F1615/9
NOP No Operation RETFIE Return from Interrupt

Syntax: [ label ] NOP Syntax: [ label ] RETFIE
Operands: None Operands: None
Operation: No operation Operation: TOS  PC,
Status Affected: None 1  GIE
Description: No operation. Status Affected: None
Words: 1 Description: Return from Interrupt. Stack is POPed

and Top-of-Stack (TOS) is loaded in
Cycles: 1 the PC. Interrupts are enabled by
Example: NOP setting Global Interrupt Enable bit,
GIE (INTCON<7>). This is a 2-cycle
instruction.
Words: 1
Load OPTION_REG Register Cycles: 2

OPTION
with W Example: RETFIE
Syntax: [ label ] OPTION After Interrupt

PC = TOS
Operands: None
GIE = 1
Operation: (W)  OPTION_REG
Description: Move data from W register to RETLW Return with literal in W
OPTION_REG register.
Syntax: [ label ] RETLW k
Operation: k  (W);
RESET Software Reset TOS  PC
Syntax: [ label ] RESET
Description: The W register is loaded with the 8-bit
Operands: None
literal ‘k’. The program counter is
Operation: Execute a device Reset. Resets the loaded from the top of the stack (the
RI flag of the PCON register. return address). This is a 2-cycle
Status Affected: None instruction.
Description: This instruction provides a way to Words: 1

execute a hardware Reset by soft- Cycles: 2
ware.
Example: CALL TABLE;W contains table
;offset value
• ;W now has table value
TABLE •
•
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
•
•
•
RETLW kn ; End of table
Before Instruction
W = 0x07
After Instruction
W = value of k8

PIC16(L)F1615/9
RETURN Return from Subroutine RRF Rotate Right f through Carry

Syntax: [ label ] RETURN Syntax: [ label ] RRF f,d
Operands: None Operands: 0  f  127
d  [0,1]
Operation: TOS  PC
Operation: See description below
Description: Return from subroutine. The stack is Status Affected: C
POPed and the top of the stack (TOS) Description: The contents of register ‘f’ are rotated
is loaded into the program counter. one bit to the right through the Carry
This is a 2-cycle instruction. flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
C Register f
SLEEP Enter Sleep mode

RLF Rotate Left f through Carry Syntax: [ label ] SLEEP
Syntax: [ label ] RLF f,d Operands: None
Operands: 0  f  127 Operation: 00h  WDT,
d  [0,1] 0  WDT prescaler,
Operation: See description below 1  TO,
0  PD
Status Affected: C
Status Affected: TO, PD
Description: The contents of register ‘f’ are rotated
one bit to the left through the Carry Description: The power-down Status bit, PD is
flag. If ‘d’ is ‘0’, the result is placed in cleared. Time-out Status bit, TO is
the W register. If ‘d’ is ‘1’, the result is set. Watchdog Timer and its pres-
stored back in register ‘f’. caler are cleared.
C Register f The processor is put into Sleep mode
with the oscillator stopped.
Words: 1
Cycles: 1
Example: RLF REG1,0
Before Instruction
REG1 = 1110 0110
C = 0
After Instruction
REG1 = 1110 0110
W = 1100 1100
C = 1

PIC16(L)F1615/9
SUBLW Subtract W from literal

SWAPF Swap Nibbles in f
Syntax: [ label ] SUBLW k
Operands: 0 k 255 Syntax: [ label ] SWAPF f,d
Operation: k - (W) W) Operands: 0  f  127

d  [0,1]
Operation: (f<3:0>)  (destination<7:4>),
Description: The W register is subtracted (2’s com- (f<7:4>)  (destination<3:0>)
plement method) from the 8-bit literal
‘k’. The result is placed in the W regis- Status Affected: None
ter. Description: The upper and lower nibbles of regis-
ter ‘f’ are exchanged. If ‘d’ is ‘0’, the
C=0 Wk result is placed in the W register. If ‘d’
C=1 Wk is ‘1’, the result is placed in register ‘f’.
DC = 0 W<3:0>  k<3:0>
DC = 1 W<3:0>  k<3:0>
TRIS Load TRIS Register with W
Syntax: [ label ] TRIS f
Operands: 5f7
SUBWF Subtract W from f
Operation: (W)  TRIS register ‘f’
Syntax: [ label ] SUBWF f,d
Operands: 0 f 127
d  [0,1] Description: Move data from W register to TRIS
register.
Operation: (f) - (W) destination) When ‘f’ = 5, TRISA is loaded.
Status Affected: C, DC, Z When ‘f’ = 6, TRISB is loaded.
When ‘f’ = 7, TRISC is loaded.
Description: Subtract (2’s complement method) W
register from register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f.
C=0 Wf
C=1 Wf
DC = 0 W<3:0>  f<3:0>
DC = 1 W<3:0>  f<3:0>
SUBWFB Subtract W from f with Borrow

Syntax: SUBWFB f {,d}
d  [0,1]
Operation: (f) – (W) – (B) dest
Description: Subtract W and the BORROW flag
(CARRY) from register ‘f’ (2’s comple-
ment method). If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.

PIC16(L)F1615/9
XORLW Exclusive OR literal with W

Syntax: [ label ] XORLW k
Operands: 0 k 255
Operation: (W) .XOR. k W)
Status Affected: Z
XOR’ed with the 8-bit literal ‘k’. The
result is placed in the W register.
XORWF Exclusive OR W with f

Syntax: [ label ] XORWF f,d
d  [0,1]
Operation: (W) .XOR. (f) destination)
Status Affected: Z
Description: Exclusive OR the contents of the W
register with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If ‘d’
is ‘1’, the result is stored back in regis-
ter ‘f’.

PIC16(L)F1615/9
35.0 ELECTRICAL SPECIFICATIONS
35.1 Absolute Maximum Ratings(†)
Ambient temperature under bias...................................................................................................... -40°C to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Voltage on pins with respect to VSS
on VDD pin
PIC16F1615/9 ........................................................................................................... -0.3V to +6.5V
PIC16LF1615/9 ......................................................................................................... -0.3V to +4.0V
on MCLR pin ........................................................................................................................... -0.3V to +9.0V
on all other pins ............................................................................................................ -0.3V to (VDD + 0.3V)
Maximum current
on VSS pin(1)
-40°C  TA  +85°C .............................................................................................................. 250 mA
+85°C  TA  +125°C ............................................................................................................. 85 mA
on VDD pin(1)
-40°C  TA  +85°C .............................................................................................................. 250 mA
+85°C  TA  +125°C ............................................................................................................. 85 mA
Sunk by any standard I/O pin ............................................................................................................... 50 mA
Sourced by any standard I/O pin .......................................................................................................... 50 mA
Sunk by any High Current I/O pin ....................................................................................................... 100 mA
Sourced by any High Current I/O pin ................................................................................................. 100 mA
Clamp current, IK (VPIN < 0 or VPIN > VDD) ................................................................................................... 20 mA
Total power dissipation(2) ............................................................................................................................... 800 mW
Note 1: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be
limited by the device package power dissipation characterizations, see Table 35-6: “Thermal Characteris-
tics” to calculate device specifications.
2: Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOl x IOL).
.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.

PIC16(L)F1615/9
35.2 Standard Operating Conditions
The standard operating conditions for any device are defined as:
Operating Voltage: VDDMIN VDD VDDMAX
Operating Temperature: TA_MIN TA TA_MAX
VDD — Operating Supply Voltage(1)
PIC16LF1615/9
VDDMIN (Fosc  16 MHz) ......................................................................................................... +1.8V
VDDMIN (Fosc  32 MHz) ......................................................................................................... +2.5V
VDDMAX .................................................................................................................................... +3.6V
PIC16F1615/9
VDDMIN (Fosc  16 MHz) ......................................................................................................... +2.3V
VDDMIN (Fosc  32 MHz) ......................................................................................................... +2.5V
VDDMAX .................................................................................................................................... +5.5V
TA — Operating Ambient Temperature Range
Industrial Temperature
TA_MIN ...................................................................................................................................... -40°C
TA_MAX .................................................................................................................................... +85°C
Extended Temperature
TA_MIN ...................................................................................................................................... -40°C
TA_MAX .................................................................................................................................. +125°C
Note 1: See Parameter D001, DS Characteristics: Supply Voltage.

PIC16(L)F1615/9
FIGURE 35-1: VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C,
PIC16F1615/9 ONLY
Rev. 10-000130B
9/19/2013
5.5
VDD (V)
2.5
2.3
0 16 32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 35-7 for each Oscillator mode’s supported frequencies.
FIGURE 35-2: VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C,

PIC16LF1615/9 ONLY
Rev. 10-000131B
9/19/2013
3.6
VDD (V)
2.5
1.8
0 16 32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 35-7 for each Oscillator mode’s supported frequencies.

PIC16(L)F1615/9
35.3 DC Characteristics
TABLE 35-1: SUPPLY VOLTAGE
PIC16LF1615/9 Standard Operating Conditions (unless otherwise stated)
PIC16F1615/9
Param. Sym. Characteristic Min. Typ† Max. Units Conditions
No.
D001 VDD Supply Voltage
VDDMIN VDDMAX
1.8 — 3.6 V FOSC  16 MHz
2.5 — 3.6 V FOSC  32 MHz
D001 2.3 — 5.5 V FOSC  16 MHz
2.5 — 5.5 V FOSC  32 MHz
D002* VDR RAM Data Retention Voltage(1)
1.5 — — V Device in Sleep mode
D002* 1.7 — — V Device in Sleep mode
D002A* VPOR Power-on Reset Release Voltage(2)
— 1.6 — V
D002A* — 1.6 — V
(2)
D002B* VPORR* Power-on Reset Rearm Voltage
— 0.8 — V
D002B* — 1.5 — V
D003 VFVR Fixed Voltage Reference Voltage
— 1.024 — V -40°C  TA  +85°C
D003 — 1.024 — V -40°C  TA  +85°C
D003A VADFVR FVR Gain Voltage Accuracy for ADC
1x VFVR, VDD 2.5V
-4 — +4 % 2x VFVR, VDD 2.5V
D003A 1x VFVR, VDD 2.5V
-5 — +5 % 2x VFVR, VDD 2.5V
D003B VCDAFVR FVR Gain Voltage Accuracy for Comparator/DAC
-4 — +4 % 2x VFVR, VDD 2.5V
D003B 1x VFVR, VDD 2.5V
-7 — +7 % 2x VFVR, VDD 2.5V
D004* SVDD VDD Rise Rate(2)
0.05 — — V/ms Ensures that the Power-on Reset
signal is released properly.
D004* 0.05 — — V/ms Ensures that the Power-on Reset
signal is released properly.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2: See Figure 35-3, POR and POR REARM with Slow Rising VDD.

PIC16(L)F1615/9
FIGURE 35-3: POR AND POR REARM WITH SLOW RISING VDD
VDD
VPOR
VPORR
SVDD
VSS
NPOR(1)
POR REARM
VSS
TVLOW(2) TPOR(3)
Note 1: When NPOR is low, the device is held in Reset.

2: TPOR 1 s typical.
3: TVLOW 2.7 s typical.
TABLE 35-2: SUPPLY CURRENT (IDD)(1,2)

PIC16F1615/9
Param. Device Conditions

Min. Typ† Max. Units
No. Characteristics VDD Note
D013 — 30 90 A 1.8 FOSC = 1 MHz,
— 55 110 A 3.0 External Clock (ECM),
Medium-Power mode
D013 — 65 120 A 2.3 FOSC = 1 MHz,
Medium-Power mode
— 115 200 A 5.0
D014 — 115 260 A 1.8 FOSC = 4 MHz,
Medium-Power mode
D014 — 180 310 A 2.3 FOSC = 4 MHz,
Medium-Power mode
— 295 520 A 5.0
*
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave,
from rail-to-rail; all I/O pins tri-stated, pulled to VSS; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption.

PIC16(L)F1615/9
TABLE 35-2: SUPPLY CURRENT (IDD)(1,2) (CONTINUED)
PIC16F1615/9

D015 — 9.6 36 A 1.8 FOSC = 31 kHz,
— 16.2 60 A 3.0 LFINTOSC,
-40°C  TA  +85°C
D015 — 39 84 A 2.3 FOSC = 31 kHz,
— 45 90 A 3.0 LFINTOSC,
-40°C  TA  +85°C
— 51 108 A 5.0
D016 — 215 360 A 1.8 FOSC = 500 kHz,
— 275 480 A 3.0 HFINTOSC
D016 — 270 450 A 2.3 FOSC = 500 kHz,
— 300 500 A 3.0 HFINTOSC
— 350 620 A 5.0
D017* — 410 800 A 1.8 FOSC = 8 MHz,
— 630 1200 A 3.0 HFINTOSC
D017* — 530 950 A 2.3 FOSC = 8 MHz,
— 660 1300 A 3.0 HFINTOSC
— 730 1400 A 5.0
D018 — 600 1200 A 1.8 FOSC = 16 MHz,
— 970 1850 A 3.0 HFINTOSC
D018 — 780 1500 A 2.3 FOSC = 16 MHz,
— 1000 1900 A 3.0 HFINTOSC
— 1090 2100 A 5.0
*
†

PIC16(L)F1615/9
TABLE 35-2: SUPPLY CURRENT (IDD)(1,2) (CONTINUED)
PIC16F1615/9

D019 — 1.6 5.0 mA 3.0 FOSC = 32 MHz, HFINTOSC
— 1.9 6.0 mA 3.6
D019 — 1.6 5.0 mA 3.0 FOSC = 32 MHz, HFINTOSC
— 1.9 6.0 mA 5.0
D020A — 1.6 5.0 mA 3.0 FOSC = 32 MHz,
— 1.9 6.0 mA 3.6 External Clock (ECH),
High-Power mode
D020A — 1.6 5.0 mA 3.0 FOSC = 32 MHz,
— 1.9 6.0 mA 5.0 External Clock (ECH),
High-Power mode
D020B — 6 16 A 1.8 FOSC = 32 kHz,
— 8 22 A 3.0 External Clock (ECL),
Low-Power mode
D020B — 13 43 A 2.3 FOSC = 32 kHz,
Low-Power mode
— 16 57 A 5.0
D020C — 19 40 A 1.8 FOSC = 500 kHz,
Low-Power mode
D020C — 31 60 A 2.3 FOSC = 500 kHz,
Low-Power mode
— 44 100 A 5.0
*
†

PIC16(L)F1615/9
TABLE 35-3: POWER-DOWN CURRENTS (IPD)(1,2)

Operating Conditions: (unless otherwise stated)
PIC16LF1615/9
Low-Power Sleep Mode
PIC16F1615/9 Low-Power Sleep Mode, VREGPM = 1
Param. Max. Max. Conditions

Device Characteristics Min. Typ† Units
No. +85°C +125°C VDD Note
D022 Base IPD — 0.020 1.0 8.0 A 1.8 WDT, BOR, FVR disabled, all
— 0.025 2.0 9.0 A 3.0 Peripherals inactive
D022 Base IPD — 0.25 3.0 10 A 2.3 WDT, BOR, FVR disabled, all
— 0.30 4.0 12 A 3.0 Peripherals inactive,
Low-Power Sleep mode
— 0.40 6.0 15 A 5.0
D022A Base IPD — 9.8 16 18 A 2.3 WDT, BOR, FVR disabled, all
— 10.3 18 20 A 3.0 Peripherals inactive,
Normal-Power Sleep mode,
— 11.5 21 26 A 5.0
VREGPM = 0
D023 — 0.26 2.0 9.0 A 1.8 WDT Current
— 0.44 3.0 10 A 3.0
D023 — 0.43 6.0 15 A 2.3 WDT Current
— 0.53 7.0 20 A 3.0
— 0.64 8.0 22 A 5.0
D023A — 15 28 30 A 1.8 FVR Current
— 18 30 33 A 3.0
D023A — 18 33 35 A 2.3 FVR Current
— 19 35 37 A 3.0
— 20 37 39 A 5.0
D024 — 6.0 17 20 A 3.0 BOR Current
D024 — 7.0 17 30 A 3.0 BOR Current
— 8.0 20 40 A 5.0
D24A — 0.1 4.0 10 A 3.0 LPBOR Current
D24A — 0.35 5.0 14 A 3.0 LPBOR Current
— 0.45 8.0 17 A 5.0
D026 — 0.11 1.5 9.0 A 1.8 ADC Current (Note 3),
— 0.12 2.7 10 A 3.0 No conversion in progress
D026 — 0.30 4.0 11 A 2.3 ADC Current (Note 3),

— 0.35 5.0 13 A 3.0 No conversion in progress
— 0.45 8.0 16 A 5.0

D026A* — 250 — — A 1.8 ADC Current (Note 3),
— 250 — — A 3.0 Conversion in progress
D026A* — 280 — — A 2.3 ADC Current (Note 3),

— 280 — — A 3.0 Conversion in progress
— 280 — — A 5.0
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Legend: TBD = To Be Determined
Note 1: The peripheral  current can be determined by subtracting the base IPD current from this limit. Max. values should be
used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS.
3: ADC clock source is FRC.

PIC16(L)F1615/9
TABLE 35-3: POWER-DOWN CURRENTS (IPD)(1,2) (CONTINUED)
Operating Conditions: (unless otherwise stated)
PIC16LF1615/9
Low-Power Sleep Mode
PIC16F1615/9 Low-Power Sleep Mode, VREGPM = 1
Param. Max. Max. Conditions

Device Characteristics Min. Typ† Units
No. +85°C +125°C VDD Note
D027 — 7 22 25 A 1.8 Comparator,
— 8 23 27 A 3.0 CxSP = 0
D027 — 17 35 37 A 2.3 Comparator,

— 18 37 38 A 3.0 CxSP = 0
— 19 38 40 A 5.0
not tested.
Legend: TBD = To Be Determined
Note 1: The peripheral  current can be determined by subtracting the base IPD current from this limit. Max. values should be
used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS.
3: ADC clock source is FRC.

PIC16(L)F1615/9
TABLE 35-4: I/O PORTS

Standard Operating Conditions (unless otherwise stated)
Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
VIL Input Low Voltage
I/O PORT:
D030 with TTL buffer — — 0.8 V 4.5V  VDD  5.5V
D030A — — 0.15 VDD V 1.8V  VDD  4.5V
D031 with Schmitt Trigger buffer — — 0.2 VDD V 2.0V  VDD  5.5V
D032 MCLR — — 0.2 VDD V
VIH Input High Voltage
I/O PORT:
D040 with TTL buffer 2.0 — — V 4.5V  VDD 5.5V
D040A 0.25 VDD + — — V 1.8V  VDD  4.5V
0.8
D041 with Schmitt Trigger buffer 0.8 VDD — — V 2.0V  VDD  5.5V
D042 MCLR 0.8 VDD — — V
IIL Input Leakage Current(1)
D060 I/O Ports — ±5 ± 125 nA VSS  VPIN  VDD,
Pin at high-impedance, 85°C
— ±5 ± 1000 nA VSS  VPIN  VDD,
D061 MCLR(3) — ± 50 ± 200 nA VSS  VPIN  VDD,
IPUR Weak Pull-up Current
D070* 25 100 200 A VDD = 3.3V, VPIN = VSS
25 140 300 A VDD = 5.0V, VPIN = VSS
VOL Output Low Voltage(3)
D080 I/O Ports IOL = 8.0 mA, VDD = 5.0V
— — 0.6 V IOL = 6.0 mA, VDD = 3.3V
IOL = 1.8 mA, VDD = 1.8V
D080A High Drive I/O(1) — 2.5V — V IOL = 100 mA, VDD = 5.0V
VOH Output High Voltage(3)
D090 I/O Ports IOH = 3.5 mA, VDD = 5.0V
VDD - 0.7 — — V IOH = 3.0 mA, VDD = 3.3V
IOH = 1.0 mA, VDD = 1.8V
D090A High Drive I/O(1) — 2.5V — V IOL = 100 mA, VDD = 5.0V
D101A* CIO All I/O pins — — 50 pF
*
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Negative current is defined as current sourced by the pin.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Excluding OSC2 in CLKOUT mode.

PIC16(L)F1615/9
TABLE 35-5: MEMORY PROGRAMMING SPECIFICATIONS

Param.
No.
Program Memory
Programming Specifications
D110 VIHH Voltage on MCLR/VPP pin 8.0 — 9.0 V (Note 2)
D111 IDDP Supply Current during — — 10 mA
Programming
D112 VBE VDD for Bulk Erase 2.7 — VDDMAX V
D113 VPEW VDD for Write or Row Erase VDDMIN — VDDMAX V
D114 IPPPGM Current on MCLR/VPP during — 1.0 — mA
Erase/Write
D115 IDDPGM Current on VDD during Erase/ — 5.0 — mA
Write
Program Flash Memory
D121 EP Cell Endurance 10K — — E/W -40C  TA  +85C
(Note 1)
D122 VPRW VDD for Read/Write VDDMIN — VDDMAX V
D123 TIW Self-timed Write Cycle Time — 2 2.5 ms
D124 TRETD Characteristic Retention — 40 — Year Provided no other
specifications are violated
D125 EHEFC High-Endurance Flash Cell 100K — — E/W 0C  TA  +60°C, lower
byte last 128 addresses
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
Note 1: Self-write and Block Erase.
2: Required only if single-supply programming is disabled.

PIC16(L)F1615/9
TABLE 35-6: THERMAL CHARACTERISTICS
Param.
Sym. Characteristic Typ. Units Conditions
No.
TH01 JA Thermal Resistance Junction to Ambient 62.2 C/W 20-pin DIP package
77.7 C/W 20-pin SOIC package
87.3 C/W 20-pin SSOP package
43 C/W 20-pin QFN 4X4mm package
TH02 JC Thermal Resistance Junction to Case 27.5 C/W 20-pin DIP package
23.1 C/W 20-pin SOIC package
31.1 C/W 20-pin SSOP package
5.3 C/W 20-pin QFN 4X4mm package
TH03 TJMAX Maximum Junction Temperature 150 C
TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O
TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1)
TH06 PI/O I/O Power Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH))
TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2)
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature; TJ = Junction Temperature

PIC16(L)F1615/9
35.4 AC Characteristics
Timing Parameter Symbology has been created with one of the following formats:
1. TppS2ppS
2. TppS
T
F Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc CLKIN
ck CLKOUT rd RD
cs CS rw RD or WR
di SDIx sc SCKx
do SDO ss SS
dt Data in t0 T0CKI
io I/O PORT t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (High-impedance) V Valid
L Low Z High-impedance
FIGURE 35-4: LOAD CONDITIONS
Rev. 10-000133A
8/1/2013
Load Condition
Pin
CL
VSS
Legend: CL=50 pF for all pins

PIC16(L)F1615/9
FIGURE 35-5: CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
CLKIN
OS02 OS12 OS11
OS03
CLKOUT
(CLKOUT mode)
Note 1: See Table 35-10.
TABLE 35-7: CLOCK OSCILLATOR TIMING REQUIREMENTS

Param.
No.
OS01 FOSC External CLKIN Frequency(1) DC — 0.5 MHz External Clock (ECL)
DC — 4 MHz External Clock (ECM)
DC — 32 MHz External Clock (ECH)
OS02 TOSC External CLKIN Period(1) 31.25 —  ns External Clock (EC)
OS03 TCY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC
†Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at “min” values with an external clock applied to CLKIN pin. When an external
clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

PIC16(L)F1615/9
TABLE 35-8: OSCILLATOR PARAMETERS
Param. Freq.
No. Tolerance
OS08 HFOSC Internal Calibrated HFINTOSC — — 16.0 — MHz (Note 2)
Frequency(1)
OS09 LFOSC Internal LFINTOSC Frequency — — 31 — kHz (Note 3)
OS10 TWARM HFINTOSC — — 5 15 s
Wake-up from Sleep Start-up Time
LFINTOSC — — 0.5 — ms
Wake-up from Sleep Start-up Time
not tested.
Note 1:To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
2: See Figure 35-6: “HFINTOSC Frequency Accuracy over Device VDD and Temperature”,
3: See Figure 36-43: “LFINTOSC Frequency over VDD and Temperature, PIC16LF1615/9 Only”, and
Figure 36-44: “LFINTOSC Frequency over VDD and Temperature, PIC16F1615/9 Only”.
FIGURE 35-6: HFINTOSC FREQUENCY ACCURACY OVER VDD AND TEMPERATURE
Rev. 10-000 135B

12/4/201 3
125
±5%
85
±3%
Temperature (°C)
60
25
±2%
±5%
-40
1.8 2.3 5.5
VDD (V)

PIC16(L)F1615/9
TABLE 35-9: PLL CLOCK TIMING SPECIFICATIONS
Param
No.
F10 FOSC Oscillator Frequency Range 4 — 8 MHz
F11 FSYS On-Chip VCO System Frequency 16 — 32 MHz
F12 TRC PLL Start-up Time (Lock Time) — — 2 ms
F13* CLK CLKOUT Stability (Jitter) -0.25% — +0.25% %
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance

PIC16(L)F1615/9
FIGURE 35-7: CLKOUT AND I/O TIMING
Cycle Write Fetch Read Execute
Q4 Q1 Q2 Q3
F
OSC
OS11 OS12
OS20
CLKOUT
OS21
OS19 OS18
OS16
OS13 OS17
I/O pin
(Input)
OS15 OS14
I/O pin
Old Value New Value
(Output)
OS18, OS19
TABLE 35-10: CLKOUT AND I/O TIMING PARAMETERS

Param.
No.
OS11 TosH2ckL FOSC to CLKOUT(1) — — 70 ns 3.3V  VDD 5.0V

OS12 TosH2ckH FOSC to CLKOUT(1) — — 72 ns 3.3V  VDD 5.0V
OS13 TckL2ioV CLKOUT to Port out valid(1) — — 20 ns
OS14 TioV2ckH Port input valid before CLKOUT(1) TOSC + 200 ns — — ns
OS15 TosH2ioV Fosc (Q1 cycle) to Port out valid — 50 70* ns 3.3V  VDD 5.0V
OS16 TosH2ioI Fosc (Q2 cycle) to Port input invalid 50 — — ns 3.3V  VDD 5.0V
(I/O in setup time)
OS17 TioV2osH Port input valid to Fosc(Q2 cycle) 20 — — ns
(I/O in setup time)
OS18* TioR Port output rise time — 40 72 ns VDD = 1.8V
— 15 32 3.3V  VDD 5.0V
OS19* TioF Port output fall time — 28 55 ns VDD = 1.8V
— 15 30 3.3V  VDD 5.0V
OS20* Tinp INT pin input high or low time 25 — — ns
OS21* Tioc Interrupt-on-change new input level time 25 — — ns
† Data in “Typ” column is at 3.0V, 25C unless otherwise stated.
Note 1: Measurements are taken in EXTRC mode where CLKOUT output is 4 x TOSC.

PIC16(L)F1615/9
FIGURE 35-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
Vdd
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Start-up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
31
34
34
I/O pins
Note 1:Asserted low.

PIC16(L)F1615/9
TABLE 35-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Param.
No.
30 TMCL MCLR Pulse Width (low) 2 — — s

31 TWDTLP Low-Power Watchdog Timer 10 16 27 ms VDD = 3.3V-5V,
Time-out Period 1:512 Prescaler used
32 TOST Oscillator Start-up Timer Period(1) — 1024 — TOSC
33* TPWRT Power-up Timer Period 40 65 140 ms PWRTE = 0
34* TIOZ I/O high-impedance from MCLR Low — — 2.0 s
or Watchdog Timer Reset
35 VBOR Brown-out Reset Voltage(2) 2.55 2.70 2.85 V BORV = 0
2.35 2.45 2.58 V BORV = 1 (PIC16F1615/9)

1.80 1.90 2.05 V BORV = 1 (PIC16LF1615/9)
36* VHYST Brown-out Reset Hysteresis 0 25 60 mV -40°C  TA  +85°C
37* TBORDC Brown-out Reset DC Response Time 1 16 35 s VDD  VBOR
38 VLPBOR Low-Power Brown-Out Reset Voltage 1.8 2.1 2.5 V LPBOR = 1
*
†
Note 1: By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency.
2: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
FIGURE 35-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS
V
DD
VBOR and VHYST

VBOR
(Device in Brown-out Reset) (Device not in Brown-out Reset)
37
Reset
33
(due to BOR)

PIC16(L)F1615/9
FIGURE 35-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40 41
42
T1CKI
45 46
47 49
TMR0 or
TMR1
TABLE 35-12: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param.
No.
40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 10 — — ns
41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 10 — — ns
42* TT0P T0CKI Period Greater of: — — ns N = prescale value
20 or TCY + 40
N
45* TT1H T1CKI High Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Time Synchronous, with Prescaler 15 — — ns
Asynchronous 30 — — ns
46* TT1L T1CKI Low Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Time Synchronous, with Prescaler 15 — — ns
47* TT1P T1CKI Input Synchronous Greater of: — — ns N = prescale value
Period 30 or TCY + 40
N
49* TCKEZTMR1 Delay from External Clock Edge to Timer 2 TOSC — 7 TOSC — Timers in Sync
Increment mode
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.

PIC16(L)F1615/9
TABLE 35-13: ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS(1,2,3)
Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25°C
Param.
No.
AD01 NR Resolution — — 10 bit
AD02 EIL Integral Error — ±1 ±1.7 LSb VREF = 3.0V
AD03 EDL Differential Error — ±1 ±1 LSb No missing codes
VREF = 3.0V
AD04 EOFF Offset Error — ±1 ±2.5 LSb VREF = 3.0V
AD05 EGN Gain Error — ±1 ±2.0 LSb VREF = 3.0V
AD06 VREF Reference Voltage 1.8 — VDD V VREF = (VRPOS - VRNEG) (Note 4)
AD07 VAIN Full-Scale Range VSS — VREF V
AD08 ZAIN Recommended Impedance of — — 10 k Can go higher if external 0.01F capacitor is
Analog Voltage Source present on input pin.
tested.
Note 1:Total Absolute Error includes integral, differential, offset and gain errors.
2: The ADC conversion result never decreases with an increase in the input voltage and has no missing codes.
3: See Section 36.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.
4: ADC VREF is selected by ADPREF<0> bit.

PIC16(L)F1615/9
FIGURE 35-11: ADC CONVERSION TIMING (ADC CLOCK FOSC-BASED)
BSF ADCON0, GO
1 Tcy
AD133
AD131
Q4
AD130
ADC_clk
ADC Data 9 8 7 6 3 2 1 0
ADRES OLD_DATA NEW_DATA
ADIF 1 Tcy
GO DONE
Sampling Stopped
AD132
Sample
FIGURE 35-12: ADC CONVERSION TIMING (ADC CLOCK FROM FRC)

BSF ADCON0, GO
AD133 1 Tcy
AD131
Q4
AD130
ADC_clk
ADC Data 9 8 7 6 3 2 1 0
ADRES OLD_DATA NEW_DATA
ADIF 1 Tcy
GO
DONE
Sampling Stopped
AD132
Sample
Note 1: If the ADC clock source is selected as FRC, a time of TCY is added before the ADC clock starts. This allows the
SLEEP instruction to be executed.

PIC16(L)F1615/9
TABLE 35-14: ADC CONVERSION REQUIREMENTS
Param.
No.
AD130* TAD ADC Clock Period (TADC) 1.0 — 6.0 s FOSC-based
ADC Internal FRC Oscillator Period (TFRC) 1.0 2.0 6.0 s ADCS<2:0> = x11 (ADC FRC mode)
AD131 TCNV Conversion Time — 11 — TAD Set GO/DONE bit to conversion
(not including Acquisition Time)(1) complete
AD132* TACQ Acquisition Time — 5.0 — s
AD133* THCD Holding Capacitor Disconnect Time — 1/2 TAD — FOSC-based
— 1/2 TAD + 1TCY — ADCS<2:0> = x11 (ADC FRC mode)
tested.
Note 1: The ADRES register may be read on the following TCY cycle.
TABLE 35-15: COMPARATOR SPECIFICATIONS(1)

VDD = 3.0V, TA = 25°C
Param.
Sym. Characteristics Min. Typ. Max. Units Comments
No.
CM01 Vioff Input Offset Voltage — ±7.5 ±60 mV CxSP = 1,
Vicm = VDD/2
CM02 Vicm Input Common Mode Voltage 0 — VDD V
CM03 CMRR Common Mode Rejection Ratio — 50 — dB
CM04A Response Time Rising Edge — 400 800 ns CxSP = 1
CM04B Response Time Falling Edge — 200 400 ns CxSP = 1
Tresp(2)
CM04C Response Time Rising Edge — 1200 — ns CxSP = 0
CM04D Response Time Falling Edge — 550 — ns CxSP = 0
CM05* Tmc2ov Comparator Mode Change to — — 10 s
Output Valid
CM06 CHYSTER Comparator Hysteresis — 25 — mV CxHYS = 1,
CxSP = 1
Note 1: See Section 36.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.
2: Response time measured with one comparator input at VDD/2, while the other input transitions from Vss to
VDD.

PIC16(L)F1615/9
TABLE 35-16: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS(1)

VDD = 3.0V, TA = 25°C
Param.
No.
DAC01* CLSB Step Size — VDD/256 — V

DAC02* CACC Absolute Accuracy — —  1.5 LSb
DAC03* CR Unit Resistor Value (R) — — — 
DAC04* CST Settling Time(2) — — 10 s
Note 1: See Section 36.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.
2: Settling time measured while DACR<4:0> transitions from ‘0000’ to ‘1111’.
TABLE 35-17: ZERO CROSS PIN SPECIFICATIONS

VDD = 3.0V, TA = 25°C
Param.
No.
ZC01 ZCPINV Voltage on Zero Cross Pin — 0.75 — V
ZC02 ZCSRC Source current — -300 -600 A
ZC03 ZCSNK Sink current — 300 600 A
ZC04 ZCISW Response Time Rising Edge — 1 — s
Response Time Falling Edge — 1 — s
ZC05 ZCOUT Response Time Rising Edge — 1 — s
Response Time Falling Edge — 1 — s

PIC16(L)F1615/9
36.0 DC AND AC
CHARACTERISTICS GRAPHS
AND CHARTS
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
Unless otherwise noted, all graphs apply to both the L and LF devices.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at 25C. “Maximum”, “Max.”, “Minimum” or “Min.”
represents (mean + 3) or (mean - 3) respectively, where  is a standard deviation, over each
temperature range.
 2014-2017 Microchip Technology Inc.  DS40001770D-page 536

PIC16(L)F1615/9
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C.
18 300 Max.
16 Max. 280 Max: 85°C + 3ı

Max: 85°C + 3ı
Typical: 25°C
Typical: 25°C
260
14 Typical
240
12
220
IDD (µA)
IDD (µA)
10
200
8
Typical 180
6
160
4 140
2 120
0 100
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V) VDD (V)
FIGURE 36-1: IDD, EC Oscillator LP Mode, FIGURE 36-4: IDD, EC Oscillator LP Mode,
Fosc = 32 kHz, PIC16LF1615/9 Only. Fosc = 500 kHz, PIC16F1615/9 Only.
2.5
35
Max. Typical: 25°C 32 MHz

30
2.0
25
16 MHz
1.5
IDD (mA)
IDD (µA)
Typical
20
8 MHz
15 1.0
4 MHz
10
0.5
Max: 85°C + 3ı
5 Typical: 25°C 1 MHz
0.0
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
VDD (V)
FIGURE 36-2: IDD, EC Oscillator LP Mode, FIGURE 36-5: IDD Typical, EC Oscillator
Fosc = 32 kHz, PIC16F1615/9 Only. MP Mode, PIC16LF1615/9 Only.
6.0
220
Max: 85°C + 3ı
200 Max: 85°C + 3ı 5.0
Typical: 25°C
32 MHz
180 4.0
IDD (mA)
Max.
IDD (µA)
160 3.0
16 MHz
140 2.0
8 MHz
Typical 4 MHz
120
1.0
1 MHz
100
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V) VDD (V)
FIGURE 36-3: IDD, EC Oscillator LP Mode, FIGURE 36-6: IDD Maximum, EC Oscillator
Fosc = 500 kHz, PIC16LF1615/9 Only. MP Mode, PIC16LF1615/9 Only.

PIC16(L)F1615/9
2.5
25 Max.
32 MHz
Typical: 25°C Max: 85°C + 3ı

2.0 Typical: 25°C Typical
20
IDD (µA)
1.5 16 MHz 15
IDD (mA)
1.0 8 MHz 10
4 MHz
5
0.5
1 MHz
0
0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V) VDD (V)
FIGURE 36-7: IDD Typical, EC Oscillator FIGURE 36-10: IDD Maximum, EC Oscillator
MP Mode, PIC16F1615/9 Only. HP Mode, PIC16LF1615/9 Only.
5.0
32 MHz 70
4.5 Max: 85°C + 3ı
60 Max: 85°C + 3ı
4.0 Typical: 25°C
3.5 50
Max.
3.0
IDD (mA)
40 Typical
IDD (µA)
2.5
16 MHz 30
2.0
1.5 8 MHz 20
4 MHz
1.0
10
1 MHz
0.5
0
0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V) VDD (V)
FIGURE 36-8: IDD Maximum, EC Oscillator FIGURE 36-11: IDD Typical, EC Oscillator
MP Mode, PIC16F1615/9 Only. HP Mode, PIC16F1615/9 Only.
12 Max. 80
Max.
70 Max: 85°C + 3ı
10 Max: 85°C + 3ı Typical: 25°C
Typical: 25°C
60
8
50
IDD (µA)
Typical
IDD (µA)
6 Typical
40
30
4
20
2
10
0 0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V) VDD (V)
FIGURE 36-9: IDD Typical, EC Oscillator FIGURE 36-12: IDD Maximum, EC Oscillator
HP Mode, PIC16LF1615/9 Only. HP Mode, PIC16F1615/9 Only.

PIC16(L)F1615/9
350 600
Max: 85°C + 3ı
300 Typical: 25°C 500
4 MHz
4 MHz
250
400
IDD (µA)
200
IDD (µA)
300
150 1 MHz
200
100 1 MHz
100
50
0 0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V) VDD (V)
FIGURE 36-13: IDD, LFINTOSC Mode, FIGURE 36-16: IDD, MFINTOSC Mode,
Fosc = 31 kHz, PIC16LF1615/9 Only. Fosc = 500 kHz, PIC16F1615/9 Only.
500
2.5
450
Max: 85°C + 3ı 4 MHz
Typical: 25°C 32 MHz
400
2.0
350
300
IDD (µA)
1.5
IDD (mA)
250
200 16 MHz
1.0
150 1 MHz
100 8 MHz
0.5
50
0 0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V) VDD (V)
FIGURE 36-14: IDD, LFINTOSC Mode, FIGURE 36-17: IDD Typical, HFINTOSC
Fosc = 31 kHz, PIC16F1615/9 Only. Mode, PIC16LF1615/9 Only.
400 4.0
350 3.5 Max: 85°C + 3ı 32 MHz

Typical: 25°C
4 MHz
300 3.0
250 2.5
IDD (µA)
IDD (mA)
200 2.0
1 MHz 16 MHz
150 1.5
100 1.0
8 MHz
50 0.5
0 0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V) VDD (V)
FIGURE 36-15: IDD, MFINTOSC Mode, FIGURE 36-18: IDD Maximum, HFINTOSC
Fosc = 500 kHz, PIC16LF1615/9 Only. Mode, PIC16LF1615/9 Only.

PIC16(L)F1615/9
2.5 2.0
32 MHz
1.8 Max: 85°C + 3ı
Typical: 25°C
20 MHz
2.0 1.6
1.4 16 MHz
1.5 1.2
IDD (mA)
IDD (mA)
16 MHz
1.0
1.0 0.8 8 MHz
8 MHz
0.6
0.5 0.4
4 MHz
0.2
0.0 0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V) VDD (V)
FIGURE 36-19: IDD Typical, HFINTOSC FIGURE 36-22: IDD Maximum, HS Oscillator,
Mode, PIC16F1615/9 Only. PIC16LF1615/9 Only.
, ,
2
4.0 20 MHz
1.8
32 MHz
Max: 85°C + 3ı
3.5 16 MHz
1.6
3.0 1.4
1.2
2.5
IDD (mA)
IDD (mA)
1 8 MHz
16 MHz
2.0
0.8
1.5
8 MHz 0.6
1.0 0.4
4 MHz
0.5 0.2
0
0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
VDD (V)
FIGURE 36-20: IDD Maximum, HFINTOSC FIGURE 36-23: IDD Typical, HS Oscillator,
Mode, PIC16F1615/9 Only. 25°C, PIC16F1615/9 Only.
2 2.1
Max: 85°C + 3ı 20 MHz
1.8
1.8
20 MHz
1.6 16 MHz
1.4 1.5
1.2 16 MHz
1.2
IDD (mA)
IDD (mA)
1 8 MHz
0.9
0.8 8 MHz
0.6 4 MHz
0.6
0.4
0.3
0.2 4 MHz
0 0.0
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V) VDD (V)
FIGURE 36-21: IDD Typical, HS Oscillator, FIGURE 36-24: IDD Maximum, HS Oscillator,
25°C, PIC16LF1615/9 Only. PIC16F1615/9 Only.

PIC16(L)F1615/9
4.5
1.2
4.0 Max.
Max
1
3.5
3.0 0.8
Typical
IPD (µA)
2.5
IDD (mA)
Max: 85°C + 3ı
0.6 Typical: 25°C
2.0
1.5 0.4
Typical
1.0
Typical: 25°C 0.2
0.5 Max: 85°C + 3ı
0.0 0
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V) VDD (V)
FIGURE 36-25: IDD, HS Oscillator, 32 MHz FIGURE 36-28: IPD Base, LP Sleep Mode
(8 MHz + 4x PLL), PIC16LF1615/9 Only. (VREGPM = 1), PIC16F1615/9 Only.
4.5 35
Max: 85°C + 3ı
4.0 Max Typical: 25°C
30
3.5
Max.
3.0 25
Typical
IPD (nA)
2.5
IDD (mA)
20
2.0
Typical
1.5 15
1.0
10
Typical: 25°C
0.5 Max: 85°C + 3ı
0.0 5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V) VDD (V)
FIGURE 36-26: IDD, HS Oscillator, 32 MHz FIGURE 36-29: IPD, Fixed Voltage Reference
(8 MHz + 4x PLL), PIC16F1615/9 Only. (FVR), PIC16LF1615/9 Only.
450 35
400 Max.
Max. 30
350
25
300
Typical
IPD (nA)
IPD (nA)
250 20
200 Max: 85°C + 3ı

Typical: 25°C 15
150
10
100
Typical Max: 85°C + 3ı
50 5 Typical: 25°C
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
VDD (V)
FIGURE 36-27: IPD Base, LP Sleep Mode,

PIC16LF1615/9 Only. FIGURE 36-30: IPD, Fixed Voltage Reference
(FVR), PIC16F1615/9 Only.

PIC16(L)F1615/9
11 1.8
Max: 85°C + 3ı Max: 85°C + 3ı

Max. 1.6 Typical: 25°C
Typical: 25°C
10 Max.
1.4
9
1.2
IPD (nA)
Typical
IPD (µA)
8 1.0
0.8
7
0.6
6 Typical
0.4
5 0.2
4 0.0
2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
VDD (V) VDD (V)
FIGURE 36-31: IPD, Brown-Out Reset FIGURE 36-34: IPD, LP Brown-Out Reset
(BOR), BORV = 1, PIC16LF1615/9 Only. (LPBOR = 0), PIC16F1615/9 Only.
7
13
Max: 85°C + 3ı Max: 85°C + 3ı
12 Typical: 25°C 6 Typical: 25°C
Max. Max.
11
5
10
IPD (µA)
4
9
IPD (nA)
Typical
8 3
Typical
7
2
6
1
5
4 0
2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
VDD (V)
FIGURE 36-32: IPD, Brown-Out Reset FIGURE 36-35: IPD, Timer1 Oscillator,
(BOR), BORV = 1, PIC16F1615/9 Only. FOSC = 32 kHz, PIC16LF1615/9 Only.
1.8 12
Max: 85°C + 3ı
1.6 Max.
Typical: 25°C
10
1.4
Max.
1.2 8
Max: 85°C + 3ı
IPD (µA)
1 Typical: 25°C
IPD (nA)
6
0.8 Typical
0.6 4
Typical
0.4
2
0.2
0 0
2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V) VDD (V)
FIGURE 36-33: IPD, LP Brown-Out Reset FIGURE 36-36: IPD, Timer1 Oscillator,
(LPBOR = 0), PIC16LF1615/9 Only. FOSC = 32 kHz, PIC16F1615/9 Only.

PIC16(L)F1615/9
800
500
Max: -40°C + 3ı
Typical: 25°C Max.
450 Max: 85°C + 3ı
Typical: 25°C 700
Max.
400
350 600
300 Typical
IPD(µA)
IPD (nA)
500
250
200
400
150
100 300
Typical
50
200
0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
VDD (V)
FIGURE 36-37: IPD, ADC Non-Converting, FIGURE 36-40: IPD, Comparator, NP Mode
PIC16LF1615/9 Only. (CxSP = 1), PIC16F1615/9 Only.
6
Graph represents 3ı Limits
1.4
Max: 85°C + 3ı 5
1.2 Typical: 25°C
Max.
4
1
VOH (V)
-40°C
IPD(µA)
0.8 3
0.6 125°C
2 Typical
0.4
Typical
1
0.2
0 0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -30 -25 -20 -15 -10 -5 0
IOH (mA)
VDD (V)
FIGURE 36-38: IPD, ADC Non-Converting, FIGURE 36-41: VOH vs. IOH Over
PIC16F1615/9 Only. Temperature, VDD = 5.0V, PIC16F1615/9 Only.
800 5
Max: -40°C + 3ı Graph represents 3ı Limits

Typical: 25°C Max.
700
4
600
3
Typical
IPD(µA)
VOL (V)
500 -40°C
2 Typical
400
125°C
1
300
200 0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 0 10 20 30 40 50 60 70 80
IOL (mA)
VDD (V)
FIGURE 36-42: VOL vs. IOL Over

FIGURE 36-39: IPD, Comparator, NP Mode Temperature, VDD = 5.0V, PIC16F1615/9 Only.
(CxSP = 1), PIC16LF1615/9 Only.

PIC16(L)F1615/9
6 3.0
Max: 85°C + 3ı Graph represents 3ı Limits

Typical: 25°C
5 2.5
Min: -40°C - 3ı
4 2.0
VOL (V)
-40°C
VOH (V)
3 1.5 Typical
Min. (-40°C)
125°C
2 Typical (25°C) Max. (85°C) 1.0
1 0.5
0 0.0
-200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0 5 10 15 20 25 30
IOH (mA) IOL (mA)
FIGURE 36-43: VOH vs. IOH Over FIGURE 36-46: VOL vs. IOL Over
Temperature for High Drive Pins, VDD = 5.0V, Temperature, VDD = 3.0V.
PIC16F1615/9 Only.
2.0
1.8
5
1.6
Max: 85°C + 3ı 1.4

Typical: 25°C
4
Min: -40°C - 3ı 1.2
VOH (V)
1.0 125°C
Max. (125°C) Typical (25°C)
3
0.8
VOL (V)
Typical
0.6 -40°C
2 Min. (-40°C) 0.4
0.2
1
0.0
-4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0
0 IOH (mA)
0 20 40 60 80 100 120 140 160 180 200
IOL (mA) FIGURE 36-47: VOH vs. IOH Over
Temperature, VDD = 1.8V, PIC16LF1615/9 Only.
FIGURE 36-44: VOL vs. IOL Over
Temperature for High Drive Pins, VDD = 5.0V,
1.8
PIC16F1615/9 Only. Graph represents 3ı Limits
1.6
1.4
3.5
1.2
3.0
Vol (V)
1.0
125°C Typical
2.5 0.8
-40°C
0.6
2.0
VOH (V)
0.4
1.5
125°C
0.2
Typical
1.0 0.0
0 1 2 3 4 5 6 7 8 9 10
-40°C
0.5 IOL (mA)
0.0 FIGURE 36-48: VOL vs. IOL Over

-14 -12 -10 -8 -6 -4 -2 0
Temperature, VDD = 1.8V, PIC16LF1615/9 Only.
IOH (mA)
FIGURE 36-45: VOH vs. IOH Over

Temperature, VDD = 3.0V.

PIC16(L)F1615/9
40,000 24
38,000
Max. 22
Max.
36,000
20
34,000
Typical
Time (ms)
Frequency (Hz)
32,000 18
Typical
30,000
Min. 16
28,000
Min.
26,000 14
24,000 Max: Typical + 3ı (-40°C to +125°C)

Max: Typical + 3ı (-40°C to +125°C) 12 Typical; statistical mean @ 25°C
Typical; statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C)
22,000 Min: Typical - 3ı (-40°C to +125°C)
20,000 10
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
VDD (V)
FIGURE 36-49: LFINTOSC Frequency, FIGURE 36-52: WDT Time-Out Period,

PIC16LF1615/9 Only. PIC16LF1615/9 Only.
40,000 2.00
38,000
Max.
Max.
36,000
1.95
34,000
Typical
Typical
Voltage (V)
Frequency (Hz)
32,000
30,000 1.90
Min.
28,000 Min.
26,000
1.85
24,000 Max: Typical + 3ı
Max: Typical + 3ı (-40°C to +125°C) Typical: statistical mean
22,000 Typical; statistical mean @ 25°C Min: Typical - 3ı
Min: Typical - 3ı (-40°C to +125°C)
20,000 1.80
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
( C)
VDD (V)
FIGURE 36-50: LFINTOSC Frequency, FIGURE 36-53: Brown-Out Reset Voltage,

PIC16F1615/9 Only. Low Trip Point (BORV = 1), PIC16LF1615/9
Only.
24
70
22
Max: Typical + 3ı
Max.
60 Typical: statistical mean
Min: Typical - 3ı
20
50 Max.
Time (ms)
18
Typical
Voltage (mV)
40
16
Min. 30
14 Typical
Max: Typical + 3ı (-40°C to +125°C) 20

12 Typical; statistical mean @ 25°C
Min: Typical - 3ı (-40°C to +125°C) Min.
10
10
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0
-60 -40 -20 0 20 40 60 80 100 120 140
VDD (V)
FIGURE 36-51: WDT Time-Out Period, Temperature (°C)
PIC16F1615/9 Only. FIGURE 36-54: Brown-Out Reset Hysteresis,

Low Trip Point (BORV = 1), PIC16LF1615/9 Only.

PIC16(L)F1615/9
2.60 80
Max: Typical + 3ı
70 Typical: statistical mean
2.55 Min: Typical - 3ı
Max. Max.
Typical 60
2.50
50
Voltage (V)
Voltage (mV)
Min. Typical
2.45 40
30
2.40
Max: Typical + 3ı
20
Typical: statistical mean
2.35 Min: Typical - 3ı Min.
10
2.30 0
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C)

( C)
FIGURE 36-55: Brown-Out Reset Voltage, FIGURE 36-58: Brown-Out Reset Hysteresis,
Low Trip Point (BORV = 1), PIC16F1615/9 Only. High Trip Point (BORV = 0).
70.0 2.7
Max: Typical + 3ı Max: Typical + 3ı
Typical: statistical mean 2.6 Typical: statistical mean
60.0 Min: Typical - 3ı Min: Typical - 3ı Max.
Max. 2.5
50.0 2.4
Voltage (V)
Voltage (mV)
2.3
40.0
Typical 2.2
30.0 Typical
2.1
20.0 2.0
Min. 1.9
Min.
10.0
1.8
0.0 1.7
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C)
FIGURE 36-56: Brown-Out Reset Hysteresis, FIGURE 36-59: LPBOR Reset Voltage.
Low Trip Point (BORV = 1), PIC16F1615/9 Only.
50
2.85 45 Max: Typical + 3ı

Typical: statistical mean Max.
Max: Typical + 3ı 40
2.80 Min: Typical - 3ı 35
Max.
Voltage (mV)
30
25
Voltage (V)
2.75
Typical
20
Typical
2.70 Min. 15
10
2.65 5
0
-60 -40 -20 0 20 40 60 80 100 120 140
2.60
-60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C)
Temperature (°C) FIGURE 36-60: LPBOR Reset Hysteresis.

FIGURE 36-57: Brown-Out Reset Voltage,
High Trip Point (BORV = 0).

PIC16(L)F1615/9
1.58
1.58
100
Max: Typical + 3ı (-40°C to +125°C)
Max: Typical + 3ı
Typical; statistical mean @ 25°C 1.56 Typical: 25°C
90 Min: Typical - 3ı (-40°C to +125°C)
Max.
Max.
1.54
1.54
(V) (V)
80
Typical
Voltage
1.52
Time (ms)
1.52
Typical
Voltage
70 1.5
1.50
Min. Min.
60 1.48
1.48
1.46
Max: Typical + 3ı 0
50 1.46 -40 Typical:-20
statistical mean
20 40 60 80 100 120
Min: Typical - 3ı Temperature (°C)
40 1.44
2 2.5 3 3.5 4 4.5 5 5.5 6 -50 -25 0 25 50 75 100 125 150
Temperature (°C)
VDD (V)
FIGURE 36-61: PWRT Period, FIGURE 36-64: POR Rearm Voltage,

PIC16F1615/9 Only. NP Mode (VREGPM1 = 0), PIC16F1615/9 Only.
100 1.4
Typical; statistical mean @ 25°C 1.3
90 Max.
Max. 1.2
80
1.1
Voltage (V)
Time (ms)
Typical
Typical 1.0
70
0.9
60 Min.
Min.
0.8
50 Max: Typical + 3ı
0.7 Typical: statistical mean
Min: Typical - 3ı
40 0.6
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 -50 -25 0 25 50 75 100 125 150
Temperature (°C)
VDD (V)
FIGURE 36-62: PWRT Period, FIGURE 36-65: POR Rearm Voltage,

PIC16LF1615/9 Only. NP Mode, PIC16LF1615/9 Only.
12
1.70
Typical; statistical mean @ 25°C
1.68 Min: Typical - 3ı (-40°C to +125°C)
10
Max.
1.66
1.64 8
Typical
Time (µs)
Voltage (V)
1.62 Max.
6
1.60
Min. Typical
1.58
4
1.56
1.54 2
Max: Typical + 3ı
0
1.50 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
-50 -25 0 25 50 75 100 125 150
VDD (V)
Temperature (°C)
FIGURE 36-63: POR Release Voltage. FIGURE 36-66: Wake From Sleep,
VREGPM = 0.

PIC16(L)F1615/9
1.0
50
45
40
Max. 0.5
35
DNL (LSb)
Time (µs)
30
Typical
0.0
25
20
15
-0.5
10 Max: Typical + 3ı (-40°C to +125°C)
Typical; statistical mean @ 25°C
0 -1.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 128 256 384 512 640 768 896 1024
Output Code
VDD (V)
FIGURE 36-67: Wake From Sleep, FIGURE 36-70: ADC 10-bit Mode,
VREGPM = 1. Single-Ended DNL, VDD = 3.0V, TAD = 4 S, 25°C.
1.0
40
Max: Typical + 3ı
Typical: statistical mean @ 25°C
35
0.5
Max.
30
INL (LSb)
Time (µs)
Typical 0.0
25
20
-0.5
Note:
15 The FVR Stabiliztion Period applies when coming out of RESET
or exiting sleep mode.
-1.0
10
0 128 256 384 512 640 768 896 1024
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (mV) Output Code
FIGURE 36-68: FVR Stabilization Period, FIGURE 36-71: ADC 10-bit Mode,
PIC16LF1615/9 Only. Single-Ended INL, VDD = 3.0V, TAD = 1 S, 25°C.
2.0
1.0
1.0
1.5
1.0
0.5 0.5
0.5
(LSb)(LSb)
0.0
DNL (LSb)
INL DNL
-0.5
0.0 0.0
-1.0
-1.5
-0.5 -0.5
-2.0
0 512 1024 1536 2048 2560 3072 3584 4096
Output Code
-1.0 -1.0
0 128 256 384 512 640 768 896 1024 0 128 256 384 512 640 768 896 1024
Output Code Output Code
FIGURE 36-69: ADC 10-bit Mode, FIGURE 36-72: ADC 10-bit Mode,
Single-Ended DNL, VDD = 3.0V, TAD = 1 S, 25°C. Single-Ended INL, VDD = 3.0V, TAD = 4 S, 25°C

PIC16(L)F1615/9
2
2.5
2 1.5
Max -40C
1 Max 125C
1.5
Min 125C
Max 25C
1 0.5
Min -40C
0.5 0
DNL (LSB)
Min 25C
INL (LSB)
Min -40C
0 -0.5
Min 25C
Min 25C
-0.5 -1
Min 125C Min 125C
-1 -1.5
Min -40C
-1.5 -2
-2 -2.5
DC 10-BIT
-2.5 MODE, SINGLE-ENDED INL, Vdd = 3.0V, VREF = 3.0V, -3
5.00E-07 1.00E-06 2.00E-06 4.00E-06 8.00E-06 1.8 2.3 3
TADs VREF
FIGURE 36-73: ADC 10-bit Mode, FIGURE 36-76: ADC 10-bit Mode,
Single-Ended DNL, VDD = 3.0V, VREF = 3.0V. Single-Ended INL, VDD = 3.0V, TAD = 1 S.
2 800
ADC VREF+ SET TO VDD
ADC VREF- SET TO GND
1.5 700
Max.
Max -40C
1 600
Max 125C Typical
0.5 Max 25C 500
ADC Output Codes

Min.
INL (LSB)
0 400
Min 25C
Min -40C 300
-0.5
Min 125C 200

-1
Max: Typical + 3ı
100 Typical; statistical mean
-1.5 Min: Typical - 3ı
0
-2 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
5.00E-07 1.00E-06 2.00E-06 4.00E-06 8.00E-06
TADs VDD (V)
FIGURE 36-74: ADC 10-bit Mode, FIGURE 36-77: Temp. Indicator Initial Offset,
Single-Ended INL, VDD = 3.0V, VREF = 3.0V. High Range, Temp. = 20°C, PIC16F1615/9 Only.
2 900
ADC VREF+ SET TO VDD
ADC VREF- SET TO GND Max.
Max 125C
1.5
800 Typical
1 Max -40C Min.
Max 25C
700
0.5
ADC Output Codes
DNL (LSB)
600
0
Min -40C
-0.5 500
Min 25C
-1 Max: Typical + 3ı
Min 125C 400 Typical; statistical mean
Min: Typical - 3ı
-1.5
300
-2 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
1.8 2.3 3
VDD (V)
VREF
FIGURE 36-75: ADC 10-bit Mode, FIGURE 36-78: Temp. Indicator Initial Offset,
Single-Ended DNL, VDD = 3.0V, TAD = 1 S. Low Range, Temp. = 20°C, PIC16F1615/9 Only.

PIC16(L)F1615/9
800 150
ADC VREF+ SET TO VDD ADC VREF+ SET TO VDD Max.
ADC VREF- SET TO GND 125 ADC VREF- SET TO GND
700 Max. Typical
100
Typical
600 Min.
Min. 75
ADC Output Codes

ADC Output Codes
500 50
25
400
0
300
-25
Max: Typical + 3ı
200 Max: Typical + 3ı
-50 Typical; statistical mean
Typical; statistical mean
Min: Typical - 3ı
Min: Typical - 3ı
100 -75
1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 3.9 -50 -25 0 25 50 75 100 125 150
VDD (V) Temperature (°C)

( C)
FIGURE 36-79: Temp. Indicator Initial Offset, FIGURE 36-82: Temp. Indicator Slope
Low Range, Temp. = 20°C, PIC16LF1615/9 Only. Normalized to 20°C, Low Range, VDD = 3.0V,
PIC16F1615/9 Only.
150
ADC VREF+ SET TO VDD Max.
ADC VREF- SET TO GND 250
125 Typical
100 200 Typical
Min.
75 150
Min.
ADC Output Codes
50 100
ADC Output Codes
25 50
0 0
-25
-50
Max: Typical + 3ı
-50 Max: Typical + 3ı
Min: Typical - 3ı -100
-75 Min: Typical - 3ı
-50 -25 0 25 50 75 100 125 150 -150
Temperature (°C)
( C) -50 -25 0 25 50 75 100 125 150
FIGURE 36-80: Temp. Indicator Slope Temperature (°C)

( C)
Normalized to 20°C, High Range, VDD = 5.5V, FIGURE 36-83: Temp. Indicator Slope
PIC16F1615/9 Only. Normalized to 20°C, Low Range, VDD = 1.8V,
PIC16LF1615/9 Only.
250
ADC VREF+ SET TO VDD 150
Max.
200 ADC VREF+ SET TO VDD Max.
Typical
Typical
150 Min. 100
Min.
100
ADC Output Codes
ADC Output Codes
50
50
0
0
-50
Max: Typical + 3ı
-100 -50
Max: Typical + 3ı
Min: Typical - 3ı
-150 Min: Typical - 3ı
-50 -25 0 25 50 75 100 125 150 -100
-50 -25 0 25 50 75 100 125 150
Temperature (°C)
( C)
Temperature (°C)
( C)
FIGURE 36-81: Temp. Indicator Slope
FIGURE 36-84: Temp. Indicator Slope
Normalized to 20°C, High Range, VDD = 3.0V,
Normalized to 20°C, Low Range, VDD = 3.0V,
PIC16F1615/9 Only.
PIC16LF1615/9 Only.

PIC16(L)F1615/9
250 30
ADC VREF- SET TO GND 25
200
Typical Max.
20
150
Min.
15
Offset Voltage (mV)

100 10
ADC Output Codes
50 5
0
0 Min.
-5
-50
-10
Max: Typical + 3ı
-100 Typical; statistical mean -15
Min: Typical - 3ı
-20
-150
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
-50 -25 0 25 50 75 100 125 150
Common Mode Voltage (V)

Temperature (°C)
FIGURE 36-85: Temp. Indicator Slope FIGURE 36-88: Comparator Offset, NP Mode
Normalized to 20°C, High Range, VDD = 3.6V, (CxSP = 1), VDD = 3.0V, Typical Measured Values
PIC16LF1615/9 Only. From -40°C to 125°C.
45 50
43
-40°C 45
41 -40°C
39
Hysteresis (mV)
40
Hysteresis (mV)
25°C
25°C
37 85°C 85°C
35 35 125°C
125°C
33
30
31
29 25
27
25 20
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Common Mode Voltage (V) Common Mode Voltage (V)
FIGURE 36-86: Comparator Hysteresis, FIGURE 36-89: Comparator Hysteresis,

NP Mode (CxSP = 1), VDD = 3.0V, Typical NP Mode (CxSP = 1), VDD = 5.5V, Typical
Measured Values. Measured Values, PIC16F1615/9 Only.
30
30
25
25
20 Max.
20
Max. 15
Hysteresis (mV)
15
Offset Voltage (mV)
10
10
5
5
0
Min.
0
Min. -5
-5
-10
-10
-15
-15
-20
-20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
FIGURE 36-90: Comparator Offset, NP Mode
FIGURE 36-87: Comparator Offset, NP Mode
(CxSP = 1), VDD = 5.0V, Typical Measured Values
(CxSP = 1), VDD = 3.0V, Typical Measured Values
at 25°C, PIC16F1615/9 Only.
at 25°C.

PIC16(L)F1615/9
1,400
40
1,200 Typical; statistical mean @ 25°C
30
Max.
1,000
Offset Voltage (mV)
20
Time (ns)
800
10
600
0 400
Min. Max.
-10 200 Typical

Min.
-20 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.5 2.0 2.5 3.0 3.5 4.0
VDD (V)
FIGURE 36-91: Comparator Offset, NP Mode FIGURE 36-94: Comparator Output Filter
(CxSP = 1), VDD = 5.5V, Typical Measured Values Delay Time Over Temp., NP Mode (CxSP = 1),
From -40°C to 125°C, PIC16F1615/9 Only. Typical Measured Values, PIC16LF1615/9 Only.
TYPICAL MEASURED VALUES
140 800
Max: Typical + 3ı (-40°C to +125°C) Max: Typical + 3ı (-40°C to +125°C)

Typical; statistical mean @ 25°C 700 Typical; statistical mean @ 25°C
600
100
500
Time (ns)
Time (ns)
80
400
60
Max.
300
40 Typical
200 Max.
Min.
Typical
20
100
Min.
0 0
1.5 2.0 2.5 3.0 3.5 4.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
9''
VDD (V)
FIGURE 36-92: Comparator Response Time FIGURE 36-95: Comparator Output Filter
Over Voltage, NP Mode (CxSP = 1), Typical Delay Time Over Temp., NP Mode (CxSP = 1),
Measured Values, PIC16LF1615/9 Only. Typical Measured Values, PIC16F1615/9 Only.
0.025
90
Max: Typical + 3ı (-40°C to +125°C) 0.02

80 Typical; statistical mean @ 25°C
0.015
70
60 0.01
Time (ns)
DNL (LSb)
50 0.005
-40°C
Max. 25°C
40 0
Typical 85°C
30 -0.005 125°C
Min.
20 -0.01
10 -0.015
0
-0.02
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
VDD (V) Output Code
FIGURE 36-93: Comparator Response Time FIGURE 36-96: Typical DAC DNL Error,
Over Voltage, NP Mode (CxSP = 1), Typical VDD = 3.0V, VREF = External 3V.
Measured Values, PIC16F1615/9 Only.

PIC16(L)F1615/9
0.00
24
-0.05
22
Max.
-0.10
20
-0.15
DNL (LSb)
18
Typical
INL (LSb)
-0.20
-40°C 16
25°C
-0.25
85°C 14
Min. Max: Typical + 3ı (-40°C to +125°C)
-0.30 125°C Typical; statistical mean @ 25°C
-0.35
10
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8
-0.40
VREF (V)
-0.45
0 14 28 42 56 70 84 98 112126140154168182196210224238252
Output Code
FIGURE 36-97: Typical DAC INL Error, FIGURE 36-100: DAC INL Error, VDD = 3.0V.
VDD = 3.0V, VREF = External 3V.
0.45
0.4
0.4
0.020
0.35 Vref = Int. Vdd
DNL (LSb)
0.015 0.3
0.3 Vref = Ext. 1.8V
0.25 Vref = Ext. 2.0V Vref = Int. Vdd
DNL (LSb)
0.010 Vref = Ext. 1.8V
Absolute
Vref = Ext. 2.0V
0.15
0.2
Absolute
Vref = Ext. 3.0V
DNL (LSb)
0.005
-40°C 0.1
25°C 0.05
0.000
85°C
0.10
125°C -50 0 50 100 150
-0.005 0
-0.010
0.0
-60 -40 -20 0 20 40 60 80 100 120 140
-0.015 Temperature (°C)
0 14 28 42 56 70 84 98 112126140154168182196210224238252
Output Code FIGURE 36-101: Absolute Value of DAC DNL
FIGURE 36-98: Typical DAC INL Error, Error, VDD = 3.0V, VREF = VDD.
VDD = 5.0V, VREF = External 5V, PIC16F1615/9
Only. 0.90
-2.1
-2.3
INL (LSb)
0.00
-2.5 Vref = Ext. 1.8V
-0.05 0.86 Vref = Ext. 2.0V -40

INL (LSb)
-2.7
Absolute
Vref = Ext. 3.0V 25

-0.10 -2.9
85
0.84
Absolute
-3.1 125
-0.15
-3.3
INL (LSb)
-0.20 0.82
-40°C
25°C -3.5
-0.25 0.0 1.0 2.0 3.0 4.0 5.0
85°C 0.80 0
-0.30 125°C
-0.35 0.78
-60.0 -40.0 -20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
-0.40 Temperature (°C)
-0.45 FIGURE 36-102: Absolute Value of DAC INL

0 14 28 42 56 70 84 98 112126140154168182196210224238252
Output Code Error, VDD = 3.0V, VREF = VDD.
FIGURE 36-99: Typical DAC INL Error,
VDD = 5.0V, VREF = External 5V, PIC16F1615/9
Only.

PIC16(L)F1615/9
0.30
0.3 25 Max.
0.25 Max: 85°C + 3ı

Vref = Int. Vdd Typical: 25°C Typical
0.26 20
DNL (LSb)
Vref = Ext. 2.0V -40

DNL (LSb)
0.15
IDD (µA)
0.22 25 15
Absolute
Vref = Ext. 3.0V
Vref = Ext. 5.0V 85

0.1
Absolute
125
10
0.18
0.05
0
5
0.14 0.0 1.0 2.0 3.0 4.0 5.0 6.0
0
0
0.10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
-60.0 -40.0 -20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
Temperature (°C) VDD (V)
FIGURE 36-103: Absolute Value of DAC DNL FIGURE 36-106: ZCD Response Time over
Error, VDD = 5.0V, VREF = VDD, PIC16F1615/9 Voltage Typical Measured Values.
Only.
8.00
5.5V
ZCD Source/Sink Current (mA)

0.9
-2.1 6.00
3.0V
-2.3
4.00
INL (LSb)
-2.5 Vref = Ext. 1.8V 2.3V

Vref = Ext. 2.0V
0.86
-2.7 -40
INL (LSb)
Vref = Ext. 3.0V 2.00

Absolute
25 1.8V
-2.9 Vref = Ext. 5.0V
85
0.84 0.00
Absolute
-3.1 125
0.00 0.50 1.00 1.50 2.00
-3.3
0.82 -2.00
-3.5
0.0 1.0 2.0 3.0 4.0 5.0 6.0
0.8 0 -4.00
ZCD Pin Voltage (V)
0.78
-60.0 -40.0 -20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
Temperature (°C) FIGURE 36-107: ZCD Pin Current over ZCD
FIGURE 36-104: Absolute Value of DAC INL Pin Voltage, Typical Measured Values from
Error, VDD = 5.0V, VREF = VDD, PIC16F1615/9 -40°C to 125°C.
Only.
1.00
0.90
0.85
0.80
0.80 0.70
Time (us)
0.60
ZCD Pin Voltage (V)
-40°C
0.75 0.50
0.40
25°C
0.70 1.8V
0.30
2.3V
0.20 3.0V
85°C
0.65 5.5V
0.10
125°
30.00 80.00 130.00 180.00 230.00 280.00 330.00 380.00 430.00
0.60 ZCD Source/Sink Current (uA)

2.3 2.8 3.3 3.8 4.3 4.8 5.3
VDD (V) FIGURE 36-108: ZCD Pin Response Timer
over Current, Typical Measured Values from
FIGURE 36-105: ZCD Pin Voltage, Typical -40°C to 125°C.
Measured Values.

PIC16(L)F1615/9
37.0 DEVELOPMENT SUPPORT 37.1 MPLAB X Integrated Development
Environment Software
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user
of software and hardware development tools: interface for Microchip and third-party software, and
• Integrated Development Environment hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
- MPLAB® X IDE Software
MPLAB X IDE is an entirely new IDE with a host of free
• Compilers/Assemblers/Linkers software components and plug-ins for high-
- MPLAB XC Compiler performance application development and debugging.
- MPASMTM Assembler Moving between tools and upgrading from software
- MPLINKTM Object Linker/ simulators to hardware debugging and programming
MPLIBTM Object Librarian tools is simple with the seamless user interface.
- MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs,
Various Device Families a configurable watch window and a feature-rich editor
• Simulators that includes code completion and context menus,
- MPLAB X SIM Software Simulator MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
• Emulators
multiple projects with simultaneous debugging, MPLAB
- MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced
• In-Circuit Debuggers/Programmers users.
- MPLAB ICD 3 Feature-Rich Editor:
- PICkit™ 3
• Color syntax highlighting
• Device Programmers
• Smart code completion makes suggestions and
- MPLAB PM3 Device Programmer provides hints as you type
• Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined
Evaluation Kits and Starter Kits rules
• Third-party development tools • Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
• Multiple projects
• Multiple tools
• Multiple configurations
• Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker

PIC16(L)F1615/9
37.2 MPLAB XC Compilers 37.4 MPLINK Object Linker/
The MPLAB XC Compilers are complete ANSI C
MPLIB Object Librarian
compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable
and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link
integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using
ease of use. MPLAB XC Compilers run on Windows, directives from a linker script.
Linux or MAC OS X.
The MPLIB Object Librarian manages the creation and
For easy source level debugging, the compilers provide modification of library files of precompiled code. When
debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only
IDE. the modules that contain that routine will be linked in
The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be
devices and commands, with no time or memory used efficiently in many different applications.
restrictions, and offer sufficient code optimization for The object linker/library features include:
most applications.
• Efficient linking of single libraries instead of many
MPLAB XC Compilers include an assembler, linker and smaller files
utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping
files that can then be archived or linked with other relo- related modules together
catable object files and archives to create an execut-
• Flexible creation of libraries with easy module
able file. MPLAB XC Compiler uses the assembler to
listing, replacement, deletion and extraction
produce its object file. Notable features of the assem-
bler include:
37.5 MPLAB Assembler, Linker and
• Support for the entire device instruction set
Librarian for Various Device
• Support for fixed-point and floating-point data
Families
• Command-line interface
• Rich directive set MPLAB Assembler produces relocatable machine
• Flexible macro language code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
• MPLAB X IDE compatibility
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
37.3 MPASM Assembler then be archived or linked with other relocatable object
The MPASM Assembler is a full-featured, universal files and archives to create an executable file. Notable
macro assembler for PIC10/12/16/18 MCUs. features of the assembler include:
The MPASM Assembler generates relocatable object • Support for the entire device instruction set
files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data
files, MAP files to detail memory usage and symbol • Command-line interface
reference, absolute LST files that contain source lines • Rich directive set
and generated machine code, and COFF files for • Flexible macro language
debugging.
• MPLAB X IDE compatibility
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process

PIC16(L)F1615/9
37.6 MPLAB X SIM Software Simulator 37.8 MPLAB ICD 3 In-Circuit Debugger
The MPLAB X SIM Software Simulator allows code
System
development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is
ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware
level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and
examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash
a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful,
logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB
buffer and logic analyzer display extend the power of IDE.
the simulator to record and track program execution,
The MPLAB ICD 3 In-Circuit Debugger probe is
actions on I/O, most peripherals and internal registers.
connected to the design engineer’s PC using a high-
The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target
symbolic debugging using the MPLAB XC Compilers, with a connector compatible with the MPLAB ICD 2 or
and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers.
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software 37.9 PICkit 3 In-Circuit Debugger/
development tool.
Programmer
37.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program-
Emulator System ming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is
Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full-
Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the tar-
programs all 8, 16 and 32-bit MCU, and DSC devices get via a Microchip debug (RJ-11) connector (compati-
with the easy-to-use, powerful graphical user interface of ble with MPLAB ICD 3 and MPLAB REAL ICE). The
the MPLAB X IDE. connector uses two device I/O pins and the Reset line
The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial
PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™).
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11) 37.10 MPLAB PM3 Device Programmer
or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection The MPLAB PM3 Device Programmer is a universal,
(CAT5). CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
The emulator is field upgradeable through future firm- maximum reliability. It features a large LCD display
ware downloads in MPLAB X IDE. MPLAB REAL ICE (128 x 64) for menus and error messages, and a mod-
offers significant advantages over competitive emulators ular, detachable socket assembly to support various
including full-speed emulation, run-time variable package types. The ICSP cable assembly is included
watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB
probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program
three meters) interconnection cables. PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.

PIC16(L)F1615/9
37.11 Demonstration/Development 37.12 Third-Party Development Tools
Boards, Evaluation Kits, and Microchip also offers a great collection of tools from
Starter Kits third-party vendors. These tools are carefully selected
A wide variety of demonstration, development and to offer good value and unique functionality.
evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers
DSCs allows quick application development on fully from companies, such as SoftLog and CCS
functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel
areas for adding custom circuitry and provide applica- and Trace Systems
tion firmware and source code for examination and • Protocol Analyzers from companies, such as
modification. Saleae and Total Phase
The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as
temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex
interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies,
EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstra-
tion software for analog filter design, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.

PIC16(L)F1615/9
38.0 PACKAGING INFORMATION
38.1 Package Marking Information
14-Lead PDIP Example
XXXXXXXXXXXXXX PIC16F1614
XXXXXXXXXXXXXX \P e3
YYWWNNN 1410017
14-Lead SOIC (.150”) Example
XXXXXXXXXXX PIC16F1614
XXXXXXXXXXX \SL e3
YYWWNNN 1410017
14-Lead TSSOP Example
XXXXXXXX F1614ST
YYWW 1410
NNN 017
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC® designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

PIC16(L)F1615/9
38.1 Package Marking Information (Continued)
20-Lead PDIP (300 mil) Example
XXXXXXXXXXXXXXXXX PIC16F1618
XXXXXXXXXXXXXXXXX \P e3
YYWWNNN 1420123
20-Lead SOIC (7.50 mm) Example
PIC16F1618
/SO e3
1420123
20-Lead SSOP (5.30 mm) Example
PIC16F1618
/SS e3
1420123

PIC16(L)F1615/9
38.1 Package Marking Information (Continued)
16-Lead QFN (4x4x0.5 mm) Example
PIC16
F1618
PIN 1 PIN 1
/ML e3
420123
20-Lead QFN/UQFN (4x4x0.5 mm) Example
PIC16
F1618
PIN 1 PIN 1
/ML e3
420123

PIC16(L)F1615/9
38.2 Package Details
The following sections give the technical details of the packages.
.

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E1
1 2 3
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L c
A1
b1
b e eB
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("$# ,, ( $((
#

, .34

PIC16(L)F1615/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

PIC16(L)F1615/9

PIC16(L)F1615/9
6( )#(
$(
7%, #*##(

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7
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((588,,,)

)8
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PIC16(L)F1615/9

PIC16(L)F1615/9

PIC16(L)F1615/9

PIC16(L)F1615/9
!

6( )#(
$(
7%, #*##(

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1 2 3
A A2
L
c
A1
b1
b e eB
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4.
(( ! ? ?
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4#(( ! 3 ? ?
$%( $%@ %( 0 / / /3
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="<( B / D
(( ! < 3 / 3
<%
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B 3
9<%@ %( + 3 D
<,<%@ %( + B
=",
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! " #$ %&'($)"*+$()$#(+
(%, ( ( (
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)# (
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PIC16(L)F1615/9

PIC16(L)F1615/9

PIC16(L)F1615/9

PIC16(L)F1615/9
!
"#$% " & "" '( ""&

6( )#(
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7%, #*##(

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N
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NOTE 1
1 2
e
b
c
A A2
φ
A1
L1 L
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(%'' 3 ? ?
="@ %( 0 B B
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="<( D 3
6(<( < 33 3 3
6( ( < 306
<%
7##
? 3
6( ^ ^ B^
<%@ %( + ? /B

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(%, ( ( (
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, .4

PIC16(L)F1615/9

PIC16(L)F1615/9
16-Lead Plastic Quad Flat, No Lead Package (ML) - 4x4x0.9mm Body [QFN]
D A B
N
NOTE 1
2
E
(DATUM B)
(DATUM A)
2X
0.15 C
2X
0.15 C TOP VIEW
0.10 C
C A1
A
SEATING
PLANE 16X
(A3) 0.08 C
SIDE VIEW
0.10 C A B
D2
0.10 C A B
E2
2
e
2
1
NOTE 1
K
N
0.40 16X b
e 0.10 C A B
BOTTOM VIEW
Microchip Technology Drawing C04-127D Sheet 1 of 2

PIC16(L)F1615/9
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 16
Pitch e 0.65 BSC
Overall Height A 0.80 0.90 1.00
Standoff A1 0.00 0.02 0.05
Contact Thickness A3 0.20 REF
Overall Width E 4.00 BSC
Exposed Pad Width E2 2.50 2.65 2.80
Overall Length D 4.00 BSC
Exposed Pad Length D2 2.50 2.65 2.80
Contact Width b 0.25 0.30 0.35
Contact Length L 0.30 0.40 0.50
Contact-to-Exposed Pad K 0.20 - -
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-127D Sheet 2 of 2

PIC16(L)F1615/9

PIC16(L)F1615/9
!
) * +
%, - ..(/ )*
6( )#(
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7

D D2
EXPOSED
PAD
e
E2
E
2 2 b
1 1
K
N N
NOTE 1 L
TOP VIEW BOTTOM VIEW
A3 A1
9 (# <<00
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34.
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(%'' 3
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PIC16(L)F1615/9
6( )#(
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7

PIC16(L)F1615/9
20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN]
D A B
N
NOTE 1
1
2
E
(DATUM B)
(DATUM A)
2X
0.20 C
2X
0.20 C TOP VIEW
C 0.10 C A1
SEATING A
PLANE 20X
(A3) 0.08 C
SIDE VIEW
0.10 C A B
D2
L
0.10 C A B
E2
2
K
1
NOTE 1 N
20X b
e 0.10 C A B
BOTTOM VIEW
Microchip Technology Drawing C04-255A Sheet 1 of 2

PIC16(L)F1615/9
Units MILLIMETERS
Number of Terminals N 20
Pitch e 0.50 BSC
Overall Height A 0.45 0.50 0.55
Standoff A1 0.00 0.02 0.05
Terminal Thickness A3 0.127 REF
Overall Width E 4.00 BSC
Exposed Pad Width E2 2.60 2.70 2.80
Overall Length D 4.00 BSC
Exposed Pad Length D2 2.60 2.70 2.80
Terminal Width b 0.20 0.25 0.30
Terminal Length L 0.30 0.40 0.50
Terminal-to-Exposed-Pad K 0.20 - -
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-255A Sheet 2 of 2

PIC16(L)F1615/9
C1
X2
20
1
2
C2 Y2
G1
Y1
X1
E SILK SCREEN
RECOMMENDED LAND PATTERN
Units MILLIMETERS
Contact Pitch E 0.50 BSC
Optional Center Pad Width X2 2.80
Optional Center Pad Length Y2 2.80
Contact Pad Spacing C1 4.00
Contact Pad Spacing C2 4.00
Contact Pad Width (X20) X1 0.30
Contact Pad Length (X20) Y1 0.80
Contact Pad to Center Pad (X20) G1 0.20
Notes:
Microchip Technology Drawing C04-2255A

PIC16(L)F1615/9
APPENDIX A: DATA SHEET
REVISION HISTORY
Revision A (10/2014)
Original release.
Revision B (4/2015)
Added High-Current pins.
Updated PIC12/16(L)F161X Family Types table and
Packages Table
Added Figures 36-7 and 36-8 for VOH vs. IOH for high
drive pins.
Deleted Figures 36-27 and 36-28.
Updated Example 3-2.
Updated Figures 5-1, 23-1, 23-2, 28-12, 31-1, 31-2,
31-4, 1, and 35-6.
Updated Registers 23-4, 27-2, 31-4 and 31-7.
Updated Sections 26.3, 25.4.2, 27.1, 30.0, 35.0, and
35.1.
Updated Table 1-2, 1-3, 3-5, 3-16, 13-2, 23-3, 23-4,
23-7, 28-1, 35-4, 35-8, and 35-17.
Updated Section 23 - added missing modes/mode
summary table, reworded text to be more clear/descrip-
tive.
Minor typos corrected.
Revision C (5/2016)
Added High endurance column to Table 1:
PIC12/16(L)F161x Family Types.
Minor typos corrected.
Updated the High-Endurance Flash data memory infor-
mation on the cover page. Updated Register 21-1.
Updated Section 19.6, 19.7. Updated Registers 19-2,
29-1, and 31-22. Updated Table 3: Pin Allocations
Table and Table 5-1. Updated Figure 19-2.
Updated Package Drawings C04-127.
Revision D (11/2017)
Added Equation 21-2: R-C Calculations and Example
21-1. Added Sections 5.3.2 Clock Switching Before
Sleep; 20.5.1: Correction by AC Coupling, and 23.2:
PRx Period Register.
Updated Example 17-1; Figure 16-1; Register 12-8,
12-16, 24-4; Sections 11.3, 11.5, 17.1.2, 17.2.6, 23.1
and 24.6; Tables 1, 1-3, 5.1, 24-4, 35-8 and 35-11.
Removed Figures 36-29, 36-30, IPD Watchdog Timer.

PIC16(L)F1615/9
THE MICROCHIP WEBSITE CUSTOMER SUPPORT
Microchip provides online support via our website at Users of Microchip products can receive assistance
www.microchip.com. This website is used as a means through several channels:
to make files and information easily available to • Distributor or Representative
customers. Accessible by using your favorite Internet
• Local Sales Office
browser, the website contains the following information:
• Field Application Engineer (FAE)
• Product Support – Data sheets and errata, appli-
• Technical Support
cation notes and sample programs, design
resources, user’s guides and hardware support Customers should contact their distributor, representa-
documents, latest software releases and archived tive or Field Application Engineer (FAE) for support.
software Local sales offices are also available to help custom-
• General Technical Support – Frequently Asked ers. A listing of sales offices and locations is included in
Questions (FAQ), technical support requests, the back of this document.
online discussion groups, Microchip consultant Technical support is available through the website
program member listing at: http://www.microchip.com/support
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of Micro-
chip sales offices, distributors and factory repre-
sentatives
CUSTOMER CHANGE NOTIFICATION

SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a spec-
ified product family or development tool of interest.
To register, access the Microchip website at
www.microchip.com. Under “Support”, click on “Cus-
tomer Change Notification” and follow the registration
instructions.

PIC16(L)F1615/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. [X](1) - X /XX XXX
Examples:
Device Tape and Reel Temperature Package Pattern a) PIC16LF1615T - I/SL
Option Range Tape and Reel,
Industrial temperature,
SOIC package
b) PIC16F1619 - I/P
Device: PIC16LF1615, PIC16F1615, Industrial temperature
PIC16LF1619, PIC16F1619 PDIP package
c) PIC16F1619 - E/ML 298
Extended temperature,
Tape and Reel Blank = Standard packaging (tube or tray) QFN package
Option: T = Tape and Reel(1) QTP pattern #298
Temperature I = -40C to +85C (Industrial)

Range: E = -40C to +125C (Extended)
Package:(2) ML = QFN (16-Lead and 20-Lead)

P = Plastic DIP Note 1: Tape and Reel identifier only appears in the
SL = SOIC (14-Lead) catalog part number description. This
ST = TSSOP identifier is used for ordering purposes and is
GZ = UQFN (20-Lead) not printed on the device package. Check
with your Microchip Sales Office for package
availability with the Tape and Reel option.
Pattern: QTP, SQTP, Code or Special Requirements 2: For other small form-factor package
(blank otherwise) availability and marking information, please
visit www.microchip.com/packaging or
contact your local sales office.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate, AVR,
and may be superseded by updates. It is your responsibility to AVR logo, AVR Freaks, BeaconThings, BitCloud, chipKIT, chipKIT
ensure that your application meets with your specifications. logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR,
MICROCHIP MAKES NO REPRESENTATIONS OR Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK
WARRANTIES OF ANY KIND WHETHER EXPRESS OR MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST
IMPLIED, WRITTEN OR ORAL, STATUTORY OR logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32
OTHERWISE, RELATED TO THE INFORMATION, logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are
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the buyer’s risk, and the buyer agrees to defend, indemnify and mTouch, Precision Edge, and Quiet-Wire are registered
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conveyed, implicitly or otherwise, under any Microchip Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
intellectual property rights unless otherwise stated. CryptoAuthentication, CryptoCompanion, CryptoController,
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and India. The Company’s quality system processes and procedures
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PIC16(L)F1615/9

14/20-Pin, 8-Bit Flash Microcontroller

Core Features Digital Peripherals

 2014-2017 Microchip Technology Inc. DS40001770D-page 1

 2014-2017 Microchip Technology Inc. DS40001770D-page 2

TABLE 1: PIC12/16(L)F161X FAMILY TYPES

Math Accelerator with PID

High-Current I/O 100mA

Program Memory Flash

High Endurance Flash

PIC12(L)F1612 (A) 2048 3.5 256 256 6 4 1 0 Y 1 1 4 1 2/0 1 0 Y 0 0 N 0 0

Note: Pin details are subject to change.

14-pin PDIP, SOIOC, TSSOP

20-pin PDIP, SOIC, SSOP

 2014-2017 Microchip Technology Inc. DS40001770D-page 4

20-pin QFN, UQFN

 2014-2017 Microchip Technology Inc. DS40001770D-page 5

TABLE 3: 14/16-PIN ALLOCATION TABLE (PIC16(L)F1615)

High Current I/O

RA0 13 12 AN0 DAC1OUT1 C1IN+ — — — — — — — — — — — IOC Y ICSPDAT

— — — — C1OUT — CCP1 CWG1A ZCD1OUT CLC1OUT DT(3) — — SDO PWM3OUT — — — —

— — — — C2OUT — CCP2 CWG1B — CLC2OUT CK — — SCK(3) PWM4OUT — — — —

TABLE 4: 20-Pin PDIP, SOIC, SSOP 20-PIN ALLOCATION TABLE (PIC16(L)F1619)

High Current I/O

RA0 19 16 AN0 DAC1OUT C1IN+ — — — — — — — — — — — IOC Y ICSPDAT

RC7 9 6 AN9 — — — — — — — — — — — — — IOC Y —

20-Pin PDIP, SOIC, SSOP

High Current I/O

— — — — C1OUT — CCP1 CWG1A ZCD1OUT CLC1OUT DT(3) — — SDO PWM3OUT — — — —

Device Overview ................................................................................................................................................................................. 11

 2014-2017 Microchip Technology Inc. DS40001770D-page 9

TO OUR VALUED CUSTOMERS

Most Current Data Sheet

Customer Notification System

 2014-2017 Microchip Technology Inc. DS40001770D-page 10

Analog-to-Digital Converter (ADC) ● ●

 2014-2017 Microchip Technology Inc. DS40001770D-page 11

 2014-2017 Microchip Technology Inc. DS40001770D-page 12

Note 1: See applicable chapters for more information on peripherals.

TABLE 1-2: PIC16(L)F1615 PINOUT DESCRIPTION

RA0/AN0/C1IN+/DAC1OUT1/ RA0 TTL/ST CMOS/OD General purpose I/O.

 2014-2017 Microchip Technology Inc. DS40001770D-page 14

 2014-2017 Microchip Technology Inc. DS40001770D-page 15

 2014-2017 Microchip Technology Inc. DS40001770D-page 16

TABLE 1-3: PIC16(L)F1619 PINOUT DESCRIPTION

RA0/AN0/C1IN+/DAC1OUT/ RA0 TTL/ST CMOS/OD General purpose I/O.

 2014-2017 Microchip Technology Inc. DS40001770D-page 17

RB6/SCK(1, 3) RB6 TTL/ST CMOS/OD General purpose I/O.

 2014-2017 Microchip Technology Inc. DS40001770D-page 18

 2014-2017 Microchip Technology Inc. DS40001770D-page 19

FIGURE 2-1: CORE BLOCK DIAGRAM

 2014-2017 Microchip Technology Inc. DS40001770D-page 19

2.2 16-Level Stack with Overflow and

2.3 File Select Registers

2.4 Instruction Set

 2014-2017 Microchip Technology Inc. DS40001770D-page 20

3.1 Program Memory Organization

 2014-2017 Microchip Technology Inc. DS40001770D-page 21

Rollover to Page 3 7FFFh

 2014-2017 Microchip Technology Inc. DS40001770D-page 22