PIC16(L)F1508/9

20-Pin Flash, 8-Bit Microcontrollers with XLP Technology

High-Performance RISC CPU: Extreme Low-Power Management

• C Compiler Optimized Architecture with XLP (PIC16LF1508/9):
• Only 49 Instructions • Standby Current:
• Up to 8 Kwords Linear Program Memory - 20 nA @ 1.8V, typical
Addressing • Watchdog Timer Current:
• Up to 512 bytes Linear Data Memory Addressing - 260 nA @ 1.8V, typical
• Operating Speed: • Operating Current:
- DC – 20 MHz clock input - 30 A/MHz @ 1.8V, typical
- DC – 200 ns instruction cycle • Secondary Oscillator Current:
• Interrupt Capability with Automatic Context - 700 nA @ 32 kHz, 1.8V, typical
Saving
• 16-Level Deep Hardware Stack with Optional Peripheral Features:
Overflow/Underflow Reset
• Direct, Indirect and Relative Addressing modes: • Analog-to-Digital Converter (ADC):
- Two full 16-bit File Select Registers (FSRs) - 10-bit resolution
- FSRs can read program and data memory - 12 external channels
- Three internal channels:
Flexible Oscillator Structure: - Fixed Voltage Reference
• 16 MHz Internal Oscillator Block: - Digital-to-Analog Converter (DAC)
- Factory calibrated to ±1%, typical - Temperature Indicator channel
- Software selectable frequency range from - Auto acquisition capability
16 MHz to 31 kHz - Conversion available during Sleep
• 31 kHz Low-Power Internal Oscillator • 5-Bit Digital-to-Analog Converter (DAC):
• Three External Clock modes up to 20 MHz - Output available externally
Special Microcontroller Features: - Positive reference selection
• Operating Voltage Range: - Internal connections to comparators and
- 1.8V to 3.6V (PIC16LF1508/9) ADC
- 2.3V to 5.5V (PIC16F1508/9) • Two Comparators:
• Self-Programmable under Software Control - Rail-to-rail inputs
• Power-On Reset (POR) - Power mode control
• Power-up Timer (PWRT) - Software controllable hysteresis
• Programmable Low-Power Brown-Out Reset • Voltage Reference module:
(LPBOR) - 1.024V Fixed Voltage Reference (FVR) with
• Extended Watchdog Timer (WDT): 1x, 2x and 4x Gain output levels
- Programmable period from 1 ms to 256s • 18 I/O Pins (1 Input-only Pin):
• Programmable Code Protection - High current sink/source 25 mA/25 mA
• In-Circuit Serial Programming™ (ICSP™) via Two - Individually programmable weak pull-ups
Pins - Individually programmable
• Enhanced Low-Voltage Programming (LVP) Interrupt-On-Change (IOC) pins
• In-Circuit Debug (ICD) via Two Pins • Timer0: 8-Bit Timer/Counter with 8-Bit
• Power-Saving Sleep mode: Programmable Prescaler
- Low-Power Sleep mode • Enhanced Timer1:
- Low-Power BOR (LPBOR) - 16-bit timer/counter with prescaler
• Integrated Temperature Indicator - External Gate Input mode
• 128 Bytes High-Endurance Flash • Timer2: 8-Bit Timer/Counter with 8-Bit Period
- 100,000 write Flash endurance (minimum) Register, Prescaler and Postscaler
• Four 10-bit PWM modules

 2011-2013 Microchip Technology Inc. DS40001609C-page 1

PIC16(L)F1508/9
Peripheral Features (Continued): • Numerically Controlled Oscillator (NCO):
- 20-bit accumulator
• Master Synchronous Serial Port (MSSP) with SPI - 16-bit increment
and I2C™ with: - True linear frequency control
- 7-bit address masking - High-speed clock input
- SMBus/PMBus™ compatibility - Selectable Output modes
• Enhanced Universal Synchronous Asynchronous - Fixed Duty Cycle (FDC) mode
Receiver Transmitter (EUSART) - Pulse Frequency (PF) mode
- RS-232, RS-485 and LIN compatible • Complementary Waveform Generator (CWG):
- Auto-Baud Detect - Eight selectable signal sources
- Auto-wake-up on Start - Selectable falling and rising edge dead-band
• Four Configurable Logic Cell (CLC) modules: control
- 16 selectable input source signals - Polarity control
- Four inputs per module - Four auto-shutdown sources
- Software control of combinational/sequential - Multiple input sources: PWM, CLC, NCO
logic/state/clock functions
- AND/OR/XOR/D Flop/D Latch/SR/JK
- Inputs from external and internal sources
- Output available to pins and peripherals
- Operation while in Sleep

PIC12(L)F1501/PIC16(L)F150X FAMILY TYPES

Program Memory

MSSP (I2C™/SPI)
Data Sheet Index

10-bit ADC (ch)

Flash (words)

Comparators
Data SRAM

(8/16-bit)

EUSART

Debug(1)
(bytes)

Timers
I/O’s(2)

PWM

CWG

NCO
DAC

CLC

XLP
Device

PIC12(L)F1501 (1) 1024 64 6 4 1 1 2/1 4 — — 1 2 1 H —

PIC16(L)F1503 (2) 2048 128 12 8 2 1 2/1 4 — 1 1 2 1 H —
PIC16(L)F1507 (3) 2048 128 18 12 — — 2/1 4 — — 1 2 1 H —
PIC16(L)F1508 (4) 4096 256 18 12 2 1 2/1 4 1 1 1 4 1 I/H Y
PIC16(L)F1509 (4) 8192 512 18 12 2 1 2/1 4 1 1 1 4 1 I/H Y
Note 1: Debugging Methods: (I) - Integrated on Chip; (H) - using Debug Header; (E) - using Emulation Header.
2: One pin is input-only.
Data Sheet Index: (Unshaded devices are described in this document.)
1: DS00041615 PIC12(L)F1501 Data Sheet, 8-Pin Flash, 8-bit Microcontrollers.
2: DS00041607 PIC16(L)F1503 Data Sheet, 14-Pin Flash, 8-bit Microcontrollers.
3: DS00041586 PIC16(L)F1507 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers.
4: DS00041609 PIC16(L)F1508/9 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers.

Note: For other small form-factor package availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.

DS40001609C-page 2  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
PIN DIAGRAMS

Pin Diagram – 20-Pin PDIP, SOIC, SSOP

VDD 1 20 VSS
RA5 2 19 RA0/ICSPDAT
RA4 3 18 RA1/ICSPCLK
MCLR/VPP/RA3 4 17 RA2

PIC16(L)F1509
PIC16(L)F1508
RC5 5 16 RC0
RC4 6 15 RC1
RC3 7 14 RC2
RC6 8 13 RB4
RC7 9 12 RB5
RB7 10 11 RB6

Note: See Table 1 for location of all peripheral functions.

Pin Diagram – 20-Pin QFN

RA0/ICSPDAT
RA4
RA5
VDD
VSS

20 19 18 17 16

MCLR/VPP/RA3 1 15 RA1/ICSPCLK
RC5 2 14 RA2
PIC16(L)F1509
RC4 3 13 RC0
PIC16(L)F1508
RC3 4 12 RC1

RC6 5 11 RC2

6 7 8 9 10
RC7
RB7
RB6
RB5
RB4

Note 1: See Table 1 for location of all peripheral functions.

2: It is recommended that the exposed bottom pad be connected to VSS.

 2011-2013 Microchip Technology Inc. DS40001609C-page 3

PIC16(L)F1508/9
PIN ALLOCATION TABLE

TABLE 1:
20-Pin PDIP/SOIC/SSOP 20-PIN ALLOCATION TABLE (PIC16(L)F1508/9)

Comparator
20-Pin QFN

Reference

EUSART

Interrupt

Pull-up
Timers

MSSP

Basic
PWM
CWG

NCO
ADC

CLC
I/O

RA0 19 16 AN0 DAC1OUT1 C1IN+ — — — — — — IOC Y ICSPDAT

—
ICDDAT
RA1 18 15 AN1 VREF+ C1IN0- — — — — — CLC4IN1 — IOC Y ICSPCLK
C2IN0- ICDCLK
RA2 17 14 AN2 DAC1OUT2 C1OUT T0CKI — — CWG1FLT — CLC1 PWM3 INT/ Y —
IOC
RA3 4 1 — — — T1G(1) — SS(1) — — CLC1IN0 — IOC Y MCLR
VPP
RA4 3 20 AN3 — — SOSCO — — — — — — IOC Y CLKOUT
T1G OSC2
RA5 2 19 — — — SOSCI — — — NCO1CLK — — IOC Y CLKIN
T1CKI OSC1
RB4 13 10 AN10 — — — — SDA/SDI — — CLC3IN0 — IOC Y —
RB5 12 9 AN11 — — — RX/DT — — — CLC4IN0 — IOC Y —
RB6 11 8 — — — — — SCL/SCK — — — — IOC Y —
RB7 10 7 — — — — TX/CK — — — CLC3 — IOC Y —
RC0 16 13 AN4 — C2IN+ — — — — — CLC2 — — — —
RC1 15 12 AN5 — C1IN1- — — — — NCO1 — PWM4 — — —
C2IN1-
RC2 14 11 AN6 — C1IN2- — — — — — — — — — —
C2IN2-
RC3 7 4 AN7 — C1IN3- — — — — — CLC2IN0 PWM2 — — —
C2IN3-
RC4 6 3 — — C2OUT — — — CWG1B — CLC4 — — — —
CLC2IN1
RC5 5 2 — — — — — — CWG1A — CLC1(1) PWM1 — — —
(1)
RC6 8 5 AN8 — — — — SS — NCO1 CLC3IN1 — — — —
RC7 9 6 AN9 — — — — SDO — — CLC1IN1 — — — —
VDD 1 18 — — — — — — — — — — — — VDD
VSS 20 17 — — — — — — — — — — — — VSS
Note 1: Alternate pin function selected with the APFCON (Register 11-1) register.

DS40001609C-page 4  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
TABLE OF CONTENTS
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 13
3.0 Memory Organization ................................................................................................................................................................. 15
4.0 Device Configuration .................................................................................................................................................................. 41
5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 47
6.0 Resets ........................................................................................................................................................................................ 63
7.0 Interrupts .................................................................................................................................................................................... 71
8.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 85
9.0 Watchdog Timer (WDT) ............................................................................................................................................................. 89
10.0 Flash Program Memory Control ................................................................................................................................................. 93
11.0 I/O Ports ................................................................................................................................................................................... 109
12.0 Interrupt-On-Change ................................................................................................................................................................ 123
13.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 129
14.0 Temperature Indicator Module ................................................................................................................................................. 133
15.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 135
16.0 5-Bit Digital-to-Analog Converter (DAC) Module...................................................................................................................... 149
17.0 Comparator Module.................................................................................................................................................................. 153
18.0 Timer0 Module ......................................................................................................................................................................... 161
19.0 Timer1 Module with Gate Control............................................................................................................................................. 165
20.0 Timer2 Module ......................................................................................................................................................................... 177
21.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 181
22.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 237
23.0 Pulse Width Modulation (PWM) Module................................................................................................................................... 265
24.0 Configurable Logic Cell (CLC).................................................................................................................................................. 271
25.0 Numerically Controlled Oscillator (NCO) Module ..................................................................................................................... 287
26.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 295
27.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 307
28.0 Instruction Set Summary .......................................................................................................................................................... 309
29.0 Electrical Specifications............................................................................................................................................................ 323
30.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 355
31.0 Development Support............................................................................................................................................................... 397
32.0 Packaging Information.............................................................................................................................................................. 401
Appendix A: Data Sheet Revision History.......................................................................................................................................... 411
The Microchip Web Site..................................................................................................................................................................... 413
Customer Change Notification Service .............................................................................................................................................. 413
Customer Support .............................................................................................................................................................................. 414
Reader Response .............................................................................................................................................................................. 414
Product Identification System ............................................................................................................................................................ 415

 2011-2013 Microchip Technology Inc. DS40001609C-page 5

PIC16(L)F1508/9

TO OUR VALUED CUSTOMERS

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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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DS40001609C-page 6  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
1.0 DEVICE OVERVIEW
The PIC16(L)F1508/9 are described within this data
sheet. The block diagram of these devices are shown in
Figure 1-1, the available peripherals are shown in
Table 1-1, and the pin out descriptions are shown in
Tables 1-2 .

TABLE 1-1: DEVICE PERIPHERAL SUMMARY

PIC12(L)F1501

PIC16(L)F1503

PIC16(L)F1507

PIC16(L)F1508

PIC16(L)F1509
Peripheral

Analog-to-Digital Converter (ADC) ● ● ● ● ●

Complementary Wave Generator ● ● ● ● ●
(CWG)
Digital-to-Analog Converter (DAC) ● ● ● ●
Enhanced Universal ● ●
Synchronous/Asynchronous
Receiver/Transmitter (EUSART)
Fixed Voltage Reference (FVR) ● ● ● ● ●
Numerically Controlled Oscillator (NCO) ● ● ● ● ●
Temperature Indicator ● ● ● ● ●
Comparators
C1 ● ● ● ●
C2 ● ● ●
Configurable Logic Cell (CLC)
CLC1 ● ● ● ● ●
CLC2 ● ● ● ● ●
CLC3 ● ●
CLC4 ● ●
Master Synchronous Serial Ports
MSSP1 ● ● ●
PWM Modules
PWM1 ● ● ● ● ●
PWM2 ● ● ● ● ●
PWM3 ● ● ● ● ●
PWM4 ● ● ● ● ●
Timers
Timer0 ● ● ● ● ●
Timer1 ● ● ● ● ●
Timer2 ● ● ● ● ●

 2011-2013 Microchip Technology Inc. DS40001609C-page 7

PIC16(L)F1508/9
FIGURE 1-1: PIC16(L)F1508/9 BLOCK DIAGRAM

Rev. 10-000039A
8/1/2013

Program
Flash Memory
RAM

PORTA

OSC2/CLKOUT
Timing
Generation
CPU PORTB

OSC1/CLKIN INTRC
Oscillator
(Note 3)
PORTC

MCLR

Temp ADC
MSSP1 TMR2 TMR1 TMR0 C2 C1 DAC FVR
Indicator 10-bit

CWG1 NCO1 CLC4 CLC3 CLC2 CLC1 PWM4 PWM3 PWM2 PWM1 EUSART

Note 1: See applicable chapters for more information on peripherals.

2: See Table 1-1 for peripherals available on specific devices.
3: See Figure 2-1.

DS40001609C-page 8  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9

TABLE 1-2: PIC16(L)F1508/9 PINOUT DESCRIPTION

Input Output
Name Function Description
Type Type

RA0/AN0/C1IN+/DAC1OUT1/ RA0 TTL CMOS General purpose I/O.

ICSPDAT/ICDDAT AN0 AN — ADC Channel input.
C1IN+ AN — Comparator positive input.
DAC1OUT1 — AN Digital-to-Analog Converter output.
ICSPDAT ST CMOS ICSP™ Data I/O.
ICDDAT ST CMOS In-Circuit Debug data.
RA1/AN1/CLC4IN1/VREF+/ RA1 TTL CMOS General purpose I/O.
C1IN0-/C2IN0-/ICSPCLK/ AN1 AN — ADC Channel input.
ICDCLK
CLC4IN1 ST — Configurable Logic Cell source input.
VREF+ AN — ADC Positive Voltage Reference input.
C1IN0- AN — Comparator negative input.
C2IN0- AN — Comparator negative input.
ICSPCLK ST — ICSP Programming Clock.
ICDCLK ST — In-Circuit Debug Clock.
RA2/AN2/C1OUT/DAC1OUT2/ RA2 ST CMOS General purpose I/O.
T0CKI/INT/PWM3/CLC1/ AN2 AN — ADC Channel input.
CWG1FLT
C1OUT — CMOS Comparator output.
DAC1OUT2 — AN Digital-to-Analog Converter output.
T0CKI ST — Timer0 clock input.
INT ST — External interrupt.
PWM3 — CMOS PWM output.
CLC1 — CMOS Configurable Logic Cell source output.
CWG1FLT ST — Complementary Waveform Generator Fault input.
RA3/CLC1IN0/VPP/T1G(1)/SS(1)/ RA3 TTL — General purpose input with IOC and WPU.
MCLR CLC1IN0 ST — Configurable Logic Cell source input.
VPP HV — Programming voltage.
T1G ST — Timer1 Gate input.
SS ST — Slave Select input.
MCLR ST — Master Clear with internal pull-up.
RA4/AN3/SOSCO/ RA4 TTL CMOS General purpose I/O.
CLKOUT/T1G AN3 AN — ADC Channel input.
SOSCO XTAL XTAL Secondary Oscillator Connection.
CLKOUT — CMOS FOSC/4 output.
T1G ST — Timer1 Gate input.
RA5/CLKIN/T1CKI/NCO1CLK/ RA5 TTL CMOS General purpose I/O.
SOSCI CLKIN CMOS — External clock input (EC mode).
T1CKI ST — Timer1 clock input.
NCO1CLK ST — Numerically Controlled Oscillator Clock source input.
SOSCI XTAL XTAL Secondary Oscillator Connection.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: Alternate pin function selected with the APFCON (Register 11-1) register.

 2011-2013 Microchip Technology Inc. DS40001609C-page 9

PIC16(L)F1508/9
TABLE 1-2: PIC16(L)F1508/9 PINOUT DESCRIPTION (CONTINUED)
Input Output
Name Function Description
Type Type
RB4/AN10/CLC3IN0/SDA/SDI RB4 TTL CMOS General purpose I/O.
AN10 AN — ADC Channel input.
CLC3IN0 ST — Configurable Logic Cell source input.
SDA I2C OD I2C data input/output.
SDI CMOS — SPI data input.
RB5/AN11/CLC4IN0/RX/DT RB5 TTL CMOS General purpose I/O.
AN11 AN — ADC Channel input.
CLC4IN0 ST — Configurable Logic Cell source input.
RX ST — USART asynchronous input.
DT ST CMOS USART synchronous data.
RB6/SCL/SCK RB6 TTL CMOS General purpose I/O.
SCL I2C OD I2C™ clock.
SCK ST CMOS SPI clock.
RB7/CLC3/TX/CK RB7 TTL CMOS General purpose I/O.
CLC3 — CMOS Configurable Logic Cell source output.
TX — CMOS USART asynchronous transmit.
CK ST CMOS USART synchronous clock.
RC0/AN4/CLC2/C2IN+ RC0 TTL CMOS General purpose I/O.
AN4 AN — ADC Channel input.
CLC2 — CMOS Configurable Logic Cell source output.
C2IN+ AN — Comparator positive input.
RC1/AN5/C1IN1-/C2IN1-/PWM4/ RC1 TTL CMOS General purpose I/O.
NCO1 AN5 AN — ADC Channel input.
C1IN1- AN — Comparator negative input.
C2IN1- AN — Comparator negative input.
PWM4 — CMOS PWM output.
NCO1 — CMOS Numerically Controlled Oscillator is source output.
RC2/AN6/C1IN2-/C2IN2- RC2 TTL CMOS General purpose I/O.
AN6 AN — ADC Channel input.
C1IN2- AN — Comparator negative input.
C2IN2- AN — Comparator negative input.
RC3/AN7/C1IN3-/C2IN3-/PWM2/ RC3 TTL CMOS General purpose I/O.
CLC2IN0 AN7 AN — ADC Channel input.
C1IN3- AN — Comparator negative input.
C2IN3- AN — Comparator negative input.
PWM2 — CMOS PWM output.
CLC2IN0 ST — Configurable Logic Cell source input.
RC4/C2OUT/CLC2IN1/CLC4/ RC4 TTL CMOS General purpose I/O.
CWG1B C2OUT — CMOS Comparator output.
CLC2IN1 ST — Configurable Logic Cell source input.
CLC4 — CMOS Configurable Logic Cell source output.
CWG1B — CMOS CWG complementary output.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: Alternate pin function selected with the APFCON (Register 11-1) register.

DS40001609C-page 10  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
TABLE 1-2: PIC16(L)F1508/9 PINOUT DESCRIPTION (CONTINUED)
Input Output
Name Function Description
Type Type
RC5/PWM1/CLC1(1)/ RC5 TTL CMOS General purpose I/O.
CWG1A PWM1 — CMOS PWM output.
CLC1 — CMOS Configurable Logic Cell source output.
CWG1A — CMOS CWG primary output.
RC6/AN8/NCO1(1)/CLC3IN1/ RC6 TTL CMOS General purpose I/O.
SS AN8 AN — ADC Channel input.
NCO1 — CMOS Numerically Controlled Oscillator source output.
CLC3IN1 ST — Configurable Logic Cell source input.
SS ST — Slave Select input.
RC7/AN9/CLC1IN1/SDO RC7 TTL CMOS General purpose I/O.
AN9 AN — ADC Channel input.
CLC1IN1 ST — Configurable Logic Cell source input.
SDO — CMOS SPI data output.
VDD VDD Power — Positive supply.
VSS VSS Power — Ground reference.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: Alternate pin function selected with the APFCON (Register 11-1) register.

 2011-2013 Microchip Technology Inc. DS40001609C-page 11

PIC16(L)F1508/9
NOTES:

DS40001609C-page 12  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
2.0 ENHANCED MID-RANGE CPU
This family of devices contain an enhanced mid-range
8-bit CPU core. The CPU has 49 instructions. Interrupt
capability includes automatic context saving. The
hardware stack is 16 levels deep and has Overflow and
Underflow Reset capability. Direct, Indirect, and
Relative addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
program and data memory.
• Automatic Interrupt Context Saving
• 16-level Stack with Overflow and Underflow
• File Select Registers
• Instruction Set

FIGURE 2-1: CORE BLOCK DIAGRAM

Rev. 10-000055A
7/30/2013

15 Configuration
15 Data Bus 8
Program Counter

Flash
MUX

Program
Memory
16-Level Stack
RAM
(15-bit)

14
Program 12
Program Memory RAM Addr
Bus
Read (PMR)
Addr MUX
Instruction Reg
Indirect
Direct Addr 7 Addr
12
5 12

BSR Reg
15
FSR0 Reg

15 FSR1 Reg

STATUS Reg
8

3 MUX
Power-up
Instruction
Timer
Decode and
Power-on
Control
Reset ALU
8
Watchdog
CLKIN Timer
Timing
Generation Brown-out
CLKOUT Reset W Reg

Internal
Oscillator VDD VSS
Block

 2011-2013 Microchip Technology Inc. DS40001609C-page 13

PIC16(L)F1508/9

2.1 Automatic Interrupt Context

Saving
During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 7.5 “Automatic Context Saving”,
for more information.

2.2 16-Level Stack with Overflow and

Underflow
These devices have a hardware stack memory 15 bits
wide and 16 words deep. A Stack Overflow or Under-
flow will set the appropriate bit (STKOVF or STKUNF)
in the PCON register, and if enabled, will cause a soft-
ware Reset. See section Section 3.4 “Stack” for more
details.

2.3 File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers and program memory,
which allows one Data Pointer for all memory. When an
FSR points to program memory, there is one additional
instruction cycle in instructions using INDF to allow the
data to be fetched. General purpose memory can now
also be addressed linearly, providing the ability to
access contiguous data larger than 80 bytes. There are
also new instructions to support the FSRs. See
Section 3.5 “Indirect Addressing” for more details.

2.4 Instruction Set

There are 49 instructions for the enhanced mid-range
CPU to support the features of the CPU. See
Section 28.0 “Instruction Set Summary” for more
details.

DS40001609C-page 14  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
3.0 MEMORY ORGANIZATION The following features are associated with access and
control of program memory and data memory:
These devices contain the following types of memory:
• PCL and PCLATH
• Program Memory • Stack
- Configuration Words • Indirect Addressing
- Device ID
- User ID 3.1 Program Memory Organization
- Flash Program Memory
The enhanced mid-range core has a 15-bit program
• Data Memory
counter capable of addressing a 32K x 14 program
- Core Registers memory space. Table 3-1 shows the memory sizes
- Special Function Registers implemented. Accessing a location above these
- General Purpose RAM boundaries will cause a wrap-around within the
- Common RAM implemented memory space. The Reset vector is at
0000h and the interrupt vector is at 0004h (See
Figure 3-1).

TABLE 3-1: DEVICE SIZES AND ADDRESSES

Program Memory Last Program Memory High-Endurance Flash
Device
Space (Words) Address Memory Address Range (1)
PIC16LF1508
4,096 0FFFh 0F80h-0FFFh
PIC16F1508
PIC16LF1509
8,192 1FFFh 1F80h-1FFFh
PIC16F1509
Note 1: High-endurance Flash applies to low byte of each address in the range.

 2011-2013 Microchip Technology Inc. DS40001609C-page 15

PIC16(L)F1508/9
FIGURE 3-1: PROGRAM MEMORY MAP FIGURE 3-2: PROGRAM MEMORY MAP
AND STACK FOR AND STACK FOR
PIC16(L)F1508 PIC16(L)F1509

Rev. 10-000040A Rev. 10-000040B

7/30/2013 7/30/2013

PC<14:0> PC<14:0>
CALL, CALLW CALL, CALLW
15 RETURN, RETLW
15
RETURN, RETLW
Interrupt, RETFIE Interrupt, RETFIE

Stack Level 0 Stack Level 0

Stack Level 1 Stack Level 1

Stack Level 15 Stack Level 15

Reset Vector 0000h Reset Vector 0000h

Interrupt Vector 0004h Interrupt Vector 0004h

0005h 0005h
Page 0 Page 0
On-chip 07FFh 07FFh
Program 0800h
0800h
Memory Page 1 Page 1
On-chip
0FFFh 0FFFh
Program
Rollover to Page 0 1000h Memory 1000h
Page 2
17FFh
1800h
Page 3
1FFFh
Rollover to Page 0 2000h

Rollover to Page 1 7FFFh

Rollover to Page 3 7FFFh

DS40001609C-page 16  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
3.1.1 READING PROGRAM MEMORY AS 3.1.1.2 Indirect Read with FSR
DATA The program memory can be accessed as data by set-
There are two methods of accessing constants in pro- ting bit 7 of the FSRxH register and reading the match-
gram memory. The first method is to use tables of ing INDFx register. The MOVIW instruction will place the
RETLW instructions. The second method is to set an lower eight bits of the addressed word in the W register.
FSR to point to the program memory. Writes to the program memory cannot be performed via
the INDF registers. Instructions that access the pro-
3.1.1.1 RETLW Instruction gram memory via the FSR require one extra instruction
The RETLW instruction can be used to provide access cycle to complete. Example 3-2 demonstrates access-
to tables of constants. The recommended way to create ing the program memory via an FSR.
such a table is shown in Example 3-1. The HIGH operator will set bit<7> if a label points to a
location in program memory.
EXAMPLE 3-1: RETLW INSTRUCTION
constants EXAMPLE 3-2: ACCESSING PROGRAM
BRW ;Add Index in W to MEMORY VIA FSR
;program counter to constants
;select data RETLW DATA0 ;Index0 data
RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data
RETLW DATA1 ;Index1 data RETLW DATA2
RETLW DATA2 RETLW DATA3
RETLW DATA3 my_function
;… LOTS OF CODE…
MOVLW LOW constants
my_function MOVWF FSR1L
;… LOTS OF CODE… MOVLW HIGH constants
MOVLW DATA_INDEX MOVWF FSR1H
call constants MOVIW 0[FSR1]
;… THE CONSTANT IS IN W ;THE PROGRAM MEMORY IS IN W

The BRW instruction makes this type of table very sim-

ple to implement. If your code must remain portable
with previous generations of microcontrollers, then the
BRW instruction is not available so the older table read
method must be used.

 2011-2013 Microchip Technology Inc. DS40001609C-page 17

PIC16(L)F1508/9
3.2 Data Memory Organization 3.2.1 CORE REGISTERS
The data memory is partitioned in 32 memory banks The core registers contain the registers that directly
with 128 bytes in a bank. Each bank consists of affect the basic operation. The core registers occupy
(Figure 3-3): the first 12 addresses of every data memory bank
(addresses x00h/x08h through x0Bh/x8Bh). These
• 12 core registers registers are listed below in Table 3-2. For detailed
• 20 Special Function Registers (SFR) information, see Table 3-8.
• Up to 80 bytes of General Purpose RAM (GPR)
• 16 bytes of common RAM TABLE 3-2: CORE REGISTERS
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be Addresses BANKx
accessed either directly (via instructions that use the x00h or x80h INDF0
file registers) or indirectly via the two File Select x01h or x81h INDF1
Registers (FSR). See Section 3.5 “Indirect x02h or x82h PCL
Addressing” for more information. x03h or x83h STATUS
Data memory uses a 12-bit address. The upper five bits x04h or x84h FSR0L
of the address define the Bank address and the lower x05h or x85h FSR0H
seven bits select the registers/RAM in that bank. x06h or x86h FSR1L
x07h or x87h FSR1H
x08h or x88h BSR
x09h or x89h WREG
x0Ah or x8Ah PCLATH
x0Bh or x8Bh INTCON

DS40001609C-page 18  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
3.2.1.1 STATUS Register For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
The STATUS register, shown in Register 3-1, contains:
as ‘000u u1uu’ (where u = unchanged).
• the arithmetic status of the ALU
It is recommended, therefore, that only BCF, BSF,
• the Reset status SWAPF and MOVWF instructions are used to alter the
The STATUS register can be the destination for any STATUS register, because these instructions do not
instruction, like any other register. If the STATUS affect any Status bits. For other instructions not
register is the destination for an instruction that affects affecting any Status bits (Refer to Section 28.0
the Z, DC or C bits, then the write to these three bits is “Instruction Set Summary”).
disabled. These bits are set or cleared according to the
Note 1: The C and DC bits operate as Borrow
device logic. Furthermore, the TO and PD bits are not
and Digit Borrow out bits, respectively, in
writable. Therefore, the result of an instruction with the
subtraction.
STATUS register as destination may be different than
intended.
REGISTER 3-1: STATUS: STATUS REGISTER
U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u
— — — TO PD Z DC(1) C(1)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-5 Unimplemented: Read as ‘0’

bit 4 TO: Time-Out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-Down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.

 2011-2013 Microchip Technology Inc. DS40001609C-page 19

PIC16(L)F1508/9
3.2.2 SPECIAL FUNCTION REGISTER FIGURE 3-3: BANKED MEMORY
The Special Function Registers are registers used by PARTITIONING
the application to control the desired operation of Rev. 10-000041A

peripheral functions in the device. The Special Function 7/30/2013

Registers occupy the 20 bytes after the core registers of

every data memory bank (addresses x0Ch/x8Ch 7-bit Bank Offset Memory Region
through x1Fh/x9Fh). The registers associated with the
operation of the peripherals are described in the appro- 00h
priate peripheral chapter of this data sheet. Core Registers
(12 bytes)
3.2.3 GENERAL PURPOSE RAM 0Bh
0Ch
There are up to 80 bytes of GPR in each data memory Special Function Registers
bank. The Special Function Registers occupy the 20 (20 bytes maximum)
bytes after the core registers of every data memory 1Fh
bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). 20h

3.2.3.1 Linear Access to GPR

The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3.5.2
“Linear Data Memory” for more information.
General Purpose RAM
3.2.4 COMMON RAM (80 bytes maximum)

There are 16 bytes of common RAM accessible from all

banks.

3.2.5 DEVICE MEMORY MAPS

The memory maps for PIC16(L)F1508/9 are as shown
in Table 3-5 through Table 3-7. 6Fh
70h
Common RAM
(16 bytes)
7Fh

DS40001609C-page 20  2011-2013 Microchip Technology Inc.

 TABLE 3-3: PIC16(L)F1509 MEMORY MAP, BANK 1-7
 2011-2013 Microchip Technology Inc.

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h 080h 100h 180h 200h 280h 300h 380h
Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers
(Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2)
00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch — 30Ch — 38Ch —
00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh — 30Dh — 38Dh —
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh — 28Eh — 30Eh — 38Eh —
00Fh — 08Fh — 10Fh — 18Fh — 20Fh — 28Fh — 30Fh — 38Fh —
010h — 090h — 110h — 190h — 210h — 290h — 310h — 390h —
011h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h SSP1BUF 291h — 311h — 391h IOCAP
012h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h SSP1ADD 292h — 312h — 392h IOCAN
013h PIR3 093h PIE3 113h CM2CON0 193h PMDATL 213h SSP1MSK 293h — 313h — 393h IOCAF
014h — 094h — 114h CM2CON1 194h PMDATH 214h SSP1STAT 294h — 314h — 394h IOCBP
015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h SSP1CON1 295h — 315h — 395h IOCBN
016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSP1CON2 296h — 316h — 396h IOCBF
017h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON 217h SSP1CON3 297h — 317h — 397h —
018h T1CON 098h — 118h DAC1CON0 198h — 218h — 298h — 318h — 398h —
019h T1GCON 099h OSCCON 119h DAC1CON1 199h RCREG 219h — 299h — 319h — 399h —
01Ah TMR2 09Ah OSCSTAT 11Ah — 19Ah TXREG 21Ah — 29Ah — 31Ah — 39Ah —
01Bh PR2 09Bh ADRESL 11Bh — 19Bh SPBRG 21Bh — 29Bh — 31Bh — 39Bh —
01Ch T2CON 09Ch ADRESH 11Ch — 19Ch SPBRGH 21Ch — 29Ch — 31Ch — 39Ch —
01Dh — 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh — 29Dh — 31Dh — 39Dh —
01Eh — 09Eh ADCON1 11Eh — 19Eh TXSTA 21Eh — 29Eh — 31Eh — 39Eh —
01Fh — 09Fh ADCON2 11Fh — 19Fh BAUDCON 21Fh — 29Fh — 31Fh — 39Fh —
020h 0A0h 120h 1A0h 220h 2A0h 320h 3A0h

General General General

Purpose Purpose Purpose Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented
Register Register Register Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’

PIC16(L)F1508/9
80 Bytes 80 Bytes 80 Bytes

06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh

070h 0F0h 170h 1F0h 270h 2F0h 370h 3F0h
Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM
Common RAM (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses
70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh)
07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

Legend: = Unimplemented data memory locations, read as ‘0’.

DS40001609C-page 21
 TABLE 3-4: PIC16(L)F1508 MEMORY MAP, BANK 1-7
DS40001609C-page 22

PIC16(L)F1508/9
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
000h 080h 100h 180h 200h 280h 300h 380h
Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers
(Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2)
00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch — 30Ch — 38Ch —
00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh — 30Dh — 38Dh —
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh — 28Eh — 30Eh — 38Eh —
00Fh — 08Fh — 10Fh — 18Fh — 20Fh — 28Fh — 30Fh — 38Fh —
010h — 090h — 110h — 190h — 210h — 290h — 310h — 390h —
011h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h SSP1BUF 291h — 311h — 391h IOCAP
012h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h SSP1ADD 292h — 312h — 392h IOCAN
013h PIR3 093h PIE3 113h CM2CON0 193h PMDATL 213h SSP1MSK 293h — 313h — 393h IOCAF
014h — 094h — 114h CM2CON1 194h PMDATH 214h SSP1STAT 294h — 314h — 394h IOCBP
015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h SSP1CON1 295h — 315h — 395h IOCBN
016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSP1CON2 296h — 316h — 396h IOCBF
017h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON 217h SSP1CON3 297h — 317h — 397h —
018h T1CON 098h — 118h DAC1CON0 198h — 218h — 298h — 318h — 398h —
019h T1GCON 099h OSCCON 119h DAC1CON1 199h RCREG 219h — 299h — 319h — 399h —
01Ah TMR2 09Ah OSCSTAT 11Ah — 19Ah TXREG 21Ah — 29Ah — 31Ah — 39Ah —
01Bh PR2 09Bh ADRESL 11Bh — 19Bh SPBRG 21Bh — 29Bh — 31Bh — 39Bh —
01Ch T2CON 09Ch ADRESH 11Ch — 19Ch SPBRGH 21Ch — 29Ch — 31Ch — 39Ch —
01Dh — 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh — 29Dh — 31Dh — 39Dh —
01Eh — 09Eh ADCON1 11Eh — 19Eh TXSTA 21Eh — 29Eh — 31Eh — 39Eh —
01Fh — 09Fh ADCON2 11Fh — 19Fh BAUDCON 21Fh — 29Fh — 31Fh — 39Fh —
0A0h 320h General Purpose
Register
020h 120h 1A0h 220h 2A0h 16Bytes 3A0h
General General General General General General
Purpose Purpose Purpose Purpose Purpose Purpose Unimplemented
Register Register Register Register Register Register Read as ‘0’
80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes Unimplemented
Read as ‘0’

06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh

 2011-2013 Microchip Technology Inc.

070h 0F0h 170h 1F0h 270h 2F0h 370h 3F0h

Accesses Accesses Accesses Accesses Accesses Accesses Accesses
Common RAM
70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh
07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

Legend: = Unimplemented data memory locations, read as ‘0’.

 TABLE 3-5: PIC16(L)F1508/9 MEMORY MAP, BANK 8-23
 2011-2013 Microchip Technology Inc.

BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15

400h 480h 500h 580h 600h 680h 700h 780h
Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers
(Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2)
40Bh 48Bh 50Bh 58Bh 60Bh 68Bh 70Bh 78Bh
40Ch — 48Ch — 50Ch — 58Ch — 60Ch — 68Ch — 70Ch — 78Ch —
40Dh — 48Dh — 50Dh — 58Dh — 60Dh — 68Dh — 70Dh — 78Dh —
40Eh — 48Eh — 50Eh — 58Eh — 60Eh — 68Eh — 70Eh — 78Eh —
40Fh — 48Fh — 50Fh — 58Fh — 60Fh — 68Fh — 70Fh — 78Fh —
410h — 490h — 510h — 590h — 610h — 690h — 710h — 790h —
411h — 491h — 511h — 591h — 611h PWM1DCL 691h CWG1DBR 711h — 791h —
412h — 492h — 512h — 592h — 612h PWM1DCH 692h CWG1DBF 712h — 792h —
413h — 493h — 513h — 593h — 613h PWM1CON 693h CWG1CON0 713h — 793h —
414h — 494h — 514h — 594h — 614h PWM2DCL 694h CWG1CON1 714h — 794h —
415h — 495h — 515h — 595h — 615h PWM2DCH 695h CWG1CON2 715h — 795h —
416h — 496h — 516h — 596h — 616h PWM2CON 696h — 716h — 796h —
417h — 497h — 517h — 597h — 617h PWM3DCL 697h — 717h — 797h —
418h — 498h NCO1ACCL 518h — 598h — 618h PWM3DCH 698h — 718h — 798h —
419h — 499h NCO1ACCH 519h — 599h — 619h PWM3CON 699h — 719h — 799h —
41Ah — 49Ah NCO1ACCU 51Ah — 59Ah — 61Ah PWM4DCL 69Ah — 71Ah — 79Ah —
41Bh — 49Bh NCO1INCL 51Bh — 59Bh — 61Bh PWM4DCH 69Bh — 71Bh — 79Bh —
41Ch — 49Ch NCO1INCH 51Ch — 59Ch — 61Ch PWM4CON 69Ch — 71Ch — 79Ch —
41Dh — 49Dh — 51Dh — 59Dh — 61Dh — 69Dh — 71Dh — 79Dh —
41Eh — 49Eh NCO1CON 51Eh — 59Eh — 61Eh — 69Eh — 71Eh — 79Eh —
41Fh — 49Fh NCO1CLK 51Fh — 59Fh — 61Fh — 69Fh — 71Fh — 79Fh —
420h 4A0h 520h 5A0h 620h 6A0h 720h 7A0h

Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented

Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’

46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh

470h 4F0h 570h 5F0h 670h 6F0h 770h 7F0h
Accesses Accesses Accesses Accesses Accesses Accesses Accesses Accesses

PIC16(L)F1508/9
70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh
47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh

BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23

800h 880h 900h 980h A00h A80h B00h B80h
Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers
(Table 3-2 ) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2)
80Bh 88Bh 90Bh 98Bh A0Bh A8Bh B0Bh B8Bh
80Ch 88Ch 90Ch 98Ch A0Ch A8Ch B0Ch B8Ch
DS40001609C-page 23

Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented

Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’
86Fh 8EFh 96Fh 9EFh A6Fh AEFh B6Fh BEFh
870h 8F0h 970h 9F0h A70h AF0h B70h BF0h
Accesses Accesses Accesses Accesses Accesses Accesses Accesses Accesses
70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh
87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh
Legend: = Unimplemented data memory locations, read as ‘0’.
 TABLE 3-6: PIC16(L)F1508/9 MEMORY MAP, BANK 24-31
DS40001609C-page 24

PIC16(L)F1508/9
BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31
C00h C80h D00h D80h E00h E80h F00h F80h
Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers
(Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2)
C0Bh C8Bh D0Bh D8Bh E0Bh E8Bh F0Bh F8Bh
C0Ch — C8Ch — D0Ch — D8Ch — E0Ch — E8Ch — F0Ch F8Ch
C0Dh — C8Dh — D0Dh — D8Dh — E0Dh — E8Dh — F0Dh F8Dh
C0Eh — C8Eh — D0Eh — D8Eh — E0Eh — E8Eh — F0Eh F8Eh
C0Fh — C8Fh — D0Fh — D8Fh — E0Fh — E8Fh — F0Fh F8Fh
C10h — C90h — D10h — D90h — E10h — E90h — F10h F90h
C11h — C91h — D11h — D91h — E11h — E91h — F11h F91h
C12h — C92h — D12h — D92h — E12h — E92h — F12h F92h
C13h — C93h — D13h — D93h — E13h — E93h — F13h F93h
C14h — C94h — D14h — D94h — E14h — E94h — F14h F94h
C15h — C95h — D15h — D95h — E15h — E95h — F15h F95h
C16h — C96h — D16h — D96h — E16h — E96h — F16h F96h
C17h — C97h — D17h — D97h — E17h — E97h — F17h F97h
See Table 3-7 for See Table 3-7 for
C18h — C98h — D18h — D98h — E18h — E98h — F18h register mapping F98h register mapping
C19h — C99h — D19h — D99h — E19h — E99h — F19h details F99h details
C1Ah — C9Ah — D1Ah — D9Ah — E1Ah — E9Ah — F1Ah F9Ah
C1Bh — C9Bh — D1Bh — D9Bh — E1Bh — E9Bh — F1Bh F9Bh
C1Ch — C9Ch — D1Ch — D9Ch — E1Ch — E9Ch — F1Ch F9Ch
C1Dh — C9Dh — D1Dh — D9Dh — E1Dh — E9Dh — F1Dh F9Dh
C1Eh — C9Eh — D1Eh — D9Eh — E1Eh — E9Eh — F1Eh F9Eh
C1Fh — C9Fh — D1Fh — D9Fh — E1Fh — E9Fh — F1Fh F9Fh
C20h CA0h D20h DA0h E20h EA0h F20h FA0h

Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented

Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’

C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFh

C70h CF0h D70h DF0h E70h EF0h F70h FF0h
 2011-2013 Microchip Technology Inc.

Accesses Accesses Accesses Accesses Accesses Accesses Accesses Accesses

70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh
CFFh CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh

Legend: = Unimplemented data memory locations, read as ‘0’.

 PIC16(L)F1508/9
TABLE 3-7: PIC16(L)F1508/9 MEMORY MAP, BANK 30-31
Bank 30
Bank 31
F0Ch —
F8Ch
F0Dh —
F0Eh — Unimplemented
F0Fh CLCDATA Read as ‘0’
F10h CLC1CON
F11h CLC1POL FE3h
F12h CLC1SEL0 FE4h STATUS_SHAD
F13h CLC1SEL1 FE5h WREG_SHAD
F14h CLC1GLS0 FE6h BSR_SHAD
F15h CLC1GLS1 FE7h PCLATH_SHAD
F16h CLC1GLS2 FE8h FSR0L_SHAD
F17h CLC1GLS3 FE9h FSR0H_SHAD
F18h CLC2CON FEAh FSR1L_SHAD
F19h CLC2POL FEBh FSR1H_SHAD
F1Ah CLC2SEL0 FECh —
F1Bh CLC2SEL1 FEDh STKPTR
F1Ch CLC2GLS0 FEEh TOSL
F1Dh CLC2GLS1 FEFh TOSH
F1Eh CLC2GLS2
F1Fh CLC2GLS3
F20h CLC3CON
F21h CLC3POL
F22h CLC3SEL0
F23h CLC3SEL1
F24h CLC3GLS0
F25h CLC3GLS1
F26h CLC3GLS2
F27h CLC3GLS3
F28h CLC4CON
F29h CLC4POL
F2Ah CLC4SEL0
F2Bh CLC4SEL1
F2Ch CLC4GLS0
F2Dh CLC4GLS1
F2Eh CLC4GLS2
F2Fh CLC4GLS3
F30h
Unimplemented
Read as ‘0’
F6Fh

Legend: = Unimplemented data memory locations, read as ‘0’.

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PIC16(L)F1508/9
3.2.6 CORE FUNCTION REGISTERS
SUMMARY
The Core Function registers listed in Table 3-8 can be
addressed from any Bank.

TABLE 3-8: CORE FUNCTION REGISTERS SUMMARY

Value on Value on all
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets

Bank 0-31
x00h or Addressing this location uses contents of FSR0H/FSR0L to address data memory
INDF0 xxxx xxxx uuuu uuuu
x80h (not a physical register)
x01h or Addressing this location uses contents of FSR1H/FSR1L to address data memory
INDF1 xxxx xxxx uuuu uuuu
x81h (not a physical register)
x02h or
PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
x82h
x03h or
STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
x83h
x04h or
FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
x84h
x05h or
FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
x85h
x06h or
FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
x86h
x07h or
FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
x87h
x08h or
BSR — — — BSR<4:0> ---0 0000 ---0 0000
x88h
x09h or
WREG Working Register 0000 0000 uuuu uuuu
x89h
x0Ah or
PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
x8Ah
x0Bh or
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
x8Bh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.

DS40001609C-page 26  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY

Value on all
Value on
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other
POR, BOR
Resets

Bank 0
00Ch PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --xx xxxx
00Dh PORTB RB7 RB6 RB5 RB4 — — — — xxxx ---- xxxx ----
00Eh PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx xxxx xxxx
00Fh — Unimplemented — —
010h — Unimplemented — —
011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF — TMR2IF TMR1IF 0000 0-00 0000 0-00
012h PIR2 OSFIF C2IF C1IF — BCL1IF NCO1IF — — 000- -0-- 000- -0--
013h PIR3 — — — — CLC4IF CLC3IF CLC2IF CLC1IF ---- 0000 ---- 0000
014h — Unimplemented — —
015h TMR0 Holding Register for the 8-bit Timer0 Count xxxx xxxx uuuu uuuu
016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Count xxxx xxxx uuuu uuuu
017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Count xxxx xxxx uuuu uuuu
018h T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 0000 00-0 uuuu uu-u
019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> 0000 0x00 uuuu uxuu
DONE
01Ah TMR2 Timer2 Module Register 0000 0000 0000 0000
01Bh PR2 Timer2 Period Register 1111 1111 1111 1111
01Ch T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000
01Dh — Unimplemented — —
01Eh — Unimplemented — —
01Fh — Unimplemented — —
Bank 1
08Ch TRISA — — TRISA5 TRISA4 —(2) TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
08Dh TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 1111 ----
08Eh TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
08Fh — Unimplemented — —
090h — Unimplemented — —
091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE — TMR2IE TMR1IE 0000 0-00 0000 0-00
092h PIE2 OSFIE C2IE C1IE — BCL1IE NCO1IE — — 000- 00-- 000- 00--
093h PIE3 — — — — CLC4IE CLC3IE CLC2IE CLC1IE ---- 0000 ---- 0000
094h — Unimplemented — —
095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 1111 1111 1111 1111
096h PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 00-1 11qq qq-q qquu
097h WDTCON — — WDTPS<4:0> SWDTEN --01 0110 --01 0110
098h — Unimplemented — —
099h OSCCON — IRCF<3:0> — SCS<1:0> -011 1-00 -011 1-00
09Ah OSCSTAT SOSCR — OSTS HFIOFR — — LFIOFR HFIOFS 0-q0 --00 q-qq --qq
09Bh ADRESL ADC Result Register Low xxxx xxxx uuuu uuuu
09Ch ADRESH ADC Result Register High xxxx xxxx uuuu uuuu
09Dh ADCON0 — CHS<4:0> GO/DONE ADON -000 0000 -000 0000
09Eh ADCON1 ADFM ADCS<2:0> — — ADPREF<1:0> 0000 --00 0000 --00
09Fh ADCON2 TRIGSEL<3:0> — — — — 0000 ---- 0000 ----
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’.
Note 1: PIC16F1508/9 only.
2: Unimplemented, read as ‘1’.

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PIC16(L)F1508/9
TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
Value on
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other
POR, BOR
Resets

Bank 2
10Ch LATA — — LATA5 LATA4 — LATA2 LATA1 LATA0 --xx -xxx --uu -uuu
10Dh LATB LATB7 LATB6 LATB5 LATB4 — — — — xxxx ---- uuuu ----
10Eh LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx uuuu uuuu
10Fh — Unimplemented — —
110h — Unimplemented — —
111h CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 0000 -100 0000 -100
112h CM1CON1 C1INTP C1INTN C1PCH<1:0> — C1NCH<2:0> 0000 -000 0000 -000
113h CM2CON0 C2ON C2OUT C2OE C2POL — C2SP C2HYS C2SYNC 0000 -100 0000 -100
114h CM2CON1 C2INTP C2INTN C2PCH<1:0> — C2NCH<2:0> 0000 -000 0000 -000
115h CMOUT — — — — — — MC2OUT MC1OUT ---- --00 ---- --00
116h BORCON SBOREN BORFS — — — — — BORRDY 10-- ---q uu-- ---u
117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 0q00 0000 0q00 0000
118h DAC1CON0 DACEN — DACOE1 DACOE2 — DACPSS — — 0-00 -0-- 0-00 -0--
119h DAC1CON1 — — — DACR<4:0> ---0 0000 ---0 0000
11Ah
to — Unimplemented — —
11Ch
11Dh APFCON — — — SSSEL T1GSEL — CLC1SEL NCO1SEL ---0 0-00 ---0 0-00
11Eh — Unimplemented — —
11Fh — Unimplemented — —
Bank 3
18Ch ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 ---1 -111 ---1 -111
18Dh ANSELB — — ANSB5 ANSB4 — — — — --11 ---- --11 ----
18Eh ANSELC ANSC7 ANSC6 — — ANSC3 ANSC2 ANSC1 ANSC0 11-- 1111 11-- 1111
18Fh — Unimplemented — —
190h — Unimplemented — —
191h PMADRL Flash Program Memory Address Register Low Byte 0000 0000 0000 0000
192h PMADRH —(2) Flash Program Memory Address Register High Byte 1000 0000 1000 0000
193h PMDATL Flash Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu
194h PMDATH — — Flash Program Memory Read Data Register High Byte --xx xxxx --uu uuuu
195h PMCON1 —(2) CFGS LWLO FREE WRERR WREN WR RD 1000 x000 1000 q000
196h PMCON2 Flash Program Memory Control Register 2 0000 0000 0000 0000
197h VREGCON(1) — — — — — — VREGPM Reserved ---- --01 ---- --01
198h — Unimplemented — —
199h RCREG USART Receive Data Register 0000 0000 0000 0000
19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000
19Bh SPBRGL Baud Rate Generator Data Register Low 0000 0000 0000 0000
19Ch SPBRGH Baud Rate Generator Data Register High 0000 0000 0000 0000
19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
19Fh BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’.
Note 1: PIC16F1508/9 only.
2: Unimplemented, read as ‘1’.

DS40001609C-page 28  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
Value on
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other
POR, BOR
Resets

Bank 4
20Ch WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 --11 1111
20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 — — — — 1111 ---- 1111 ----
20Eh
to — Unimplemented — —
210h
211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
212h SSP1ADD ADD<7:0> 0000 0000 0000 0000
213h SSP1MSK MSK<7:0> 1111 1111 1111 1111
214h SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
215h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000
216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000
218h
to — Unimplemented — —
21Fh
Bank 5
28Ch
to — Unimplemented — —
29Fh
Bank 6
30Ch
to — Unimplemented — —
31Fh
Bank 7
38Ch
to — Unimplemented — —
390h
391h IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 --00 0000 --00 0000
392h IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 --00 0000 --00 0000
393h IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 --00 0000 --00 0000
394h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 — — — — 0000 ---- 0000 ----
395h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 — — — — 0000 ---- 0000 ----
396h IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 — — — — 0000 ---- 0000 ----
397h
to — Unimplemented — —
39Fh
Bank 8
40Ch
to — Unimplemented — —
41Fh
Bank 9
48Ch
to — Unimplemented — —
497h
498h NCO1ACCL NCO1ACC<7:0> 0000 0000 0000 0000
499h NCO1ACCH NCO1ACC<15:8> 0000 0000 0000 0000
49Ah NCO1ACCU NCO1ACC<19:16> 0000 0000 0000 0000
49Bh NCO1INCL NCO1INC<7:0> 0000 0000 0000 0000
49Ch NCO1INCH NCO1INC<15:8> 0000 0000 0000 0000
49Dh — Unimplemented — —
49Eh NCO1CON N1EN N1OE N1OUT N1POL — — — N1PFM 0000 ---0 0000 ---0
49Fh NCO1CLK N1PWS<2:0> — — — N1CKS<1:0> 0000 --00 0000 --00
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’.
Note 1: PIC16F1508/9 only.
2: Unimplemented, read as ‘1’.

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PIC16(L)F1508/9
TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
Value on
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other
POR, BOR
Resets

Bank 10
50Ch
to — Unimplemented — —
51Fh
Bank 11
58Ch
to — Unimplemented — —
59Fh
Bank 12
60Ch
to — Unimplemented — —
610h
611h PWM1DCL PWM1DCL<7:6> — — — — — — 00-- ---- 00-- ----
612h PWM1DCH PWM1DCH<7:0> xxxx xxxx uuuu uuuu
613h PWM1CON0 PWM1EN PWM1OE PWM1OUT PWM1POL — — — — 0000 ---- 0000 ----
614h PWM2DCL PWM2DCL<7:6> — — — — — — 00-- ---- 00-- ----
615h PWM2DCH PWM2DCH<7:0> xxxx xxxx uuuu uuuu
616h PWM2CON0 PWM2EN PWM2OE PWM2OUT PWM2POL — — — — 0000 ---- 0000 ----
617h PWM3DCL PWM3DCL<7:6> — — — — — — 00-- ---- 00-- ----
618h PWM3DCH PWM3DCH<7:0> xxxx xxxx uuuu uuuu
619h PWM3CON0 PWM3EN PWM3OE PWM3OUT PWM3POL — — — — 0000 ---- 0000 ----
61Ah PWM4DCL PWM4DCL<7:6> — — — — — — 00-- ---- 00-- ----
61Bh PWM4DCH PWM4DCH<7:0> xxxx xxxx uuuu uuuu
61Ch PWM4CON0 PWM4EN PWM4OE PWM4OUT PWM4POL — — — — 0000 ---- 0000 ----
61Dh
to — Unimplemented — —
61Fh
Bank 13
68Ch
to — Unimplemented — —
690h
691h CWG1DBR — — CWG1DBR<5:0> --00 0000 --00 0000
692h CWG1DBF — — CWG1DBF<5:0> --xx xxxx --xx xxxx
693h CWG1CON0 G1EN G1OEB G1OEA G1POLB G1POLA — — G1CS0 0000 0--0 0000 0--0
694h CWG1CON1 G1ASDLB<1:0> G1ASDLA<1:0> — G1IS<2:0> 0000 -000 0000 -000
695h CWG1CON2 G1ASE G1ARSEN — — G1ASDC2 G1ASDC1 G1ASDSFLT G1ASDSCLC2 00-- --00 00-- --00
696h
to — Unimplemented — —
69Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’.
Note 1: PIC16F1508/9 only.
2: Unimplemented, read as ‘1’.

DS40001609C-page 30  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
Value on
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other
POR, BOR
Resets

Banks 14-29
x0Ch/ — Unimplemented — —
x8Ch
—
x1Fh/
x9Fh
Bank 30
F0Ch
to — Unimplemented — —
F0Eh
F0Fh CLCDATA — — — — MLC4OUT MLC3OUT MLC2OUT MLC1OUT ---- 0000 ---- 0000
F10h CLC1CON LC1EN LC1OE LC1OUT LC1INTP LC1INTN LC1MODE<2:0> 0000 0000 0000 0000
F11h CLC1POL LC1POL — — — LC1G4POL LC1G3POL LC1G2POL LC1G1POL 0--- xxxx 0--- uuuu
F12h CLC1SEL0 — LC1D2S<2:0> — LC1D1S<2:0> -xxx -xxx -uuu -uuu
F13h CLC1SEL1 — LC1D4S<2:0> — LC1D3S<2:0> -xxx -xxx -uuu -uuu
F14h CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N xxxx xxxx uuuu uuuu
F15h CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N xxxx xxxx uuuu uuuu
F16h CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N xxxx xxxx uuuu uuuu
F17h CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N xxxx xxxx uuuu uuuu
F18h CLC2CON LC2EN LC2OE LC2OUT LC2INTP LC2INTN LC2MODE<2:0> 0000 0000 0000 0000
F19h CLC2POL LC2POL — — — LC2G4POL LC2G3POL LC2G2POL LC2G1POL 0--- xxxx 0--- uuuu
F1Ah CLC2SEL0 — LC2D2S<2:0> — LC2D1S<2:0> -xxx -xxx -uuu -uuu
F1Bh CLC2SEL1 — LC2D4S<2:0> — LC2D3S<2:0> -xxx -xxx -uuu -uuu
F1Ch CLC2GLS0 LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N xxxx xxxx uuuu uuuu
F1Dh CLC2GLS1 LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N xxxx xxxx uuuu uuuu
F1Eh CLC2GLS2 LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N xxxx xxxx uuuu uuuu
F1Fh CLC2GLS3 LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N xxxx xxxx uuuu uuuu
F20h CLC3CON LC3EN LC3OE LC3OUT LC3INTP LC3INTN LC3MODE<2:0> 0000 0000 0000 0000
F21h CLC3POL LC3POL — — — LC3G4POL LC3G3POL LC3G2POL LC3G1POL 0--- xxxx 0--- uuuu
F22h CLC3SEL0 — LC3D2S<2:0> — LC3D1S<2:0> -xxx -xxx -uuu -uuu
F23h CLC3SEL1 — LC3D4S<2:0> — LC3D3S<2:0> -xxx -xxx -uuu -uuu
F24h CLC3GLS0 LC3G1D4T LC3G1D4N LC3G1D3T LC3G1D3N LC3G1D2T LC3G1D2N LC3G1D1T LC3G1D1N xxxx xxxx uuuu uuuu
F25h CLC3GLS1 LC3G2D4T LC3G2D4N LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N LC3G2D1T LC3G2D1N xxxx xxxx uuuu uuuu
F26h CLC3GLS2 LC3G3D4T LC3G3D4N LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N LC3G3D1T LC3G3D1N xxxx xxxx uuuu uuuu
F27h CLC3GLS3 LC3G4D4T LC3G4D4N LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N LC3G4D1T LC3G4D1N xxxx xxxx uuuu uuuu
F28h CLC4CON LC4EN LC4OE LC4OUT LC4INTP LC4INTN LC4MODE<2:0> 0000 0000 0000 0000
F29h CLC4POL LC4POL — — — LC4G4POL LC4G3POL LC4G2POL LC4G1POL 0--- xxxx 0--- uuuu
F2Ah CLC4SEL0 — LC4D2S<2:0> — LC4D1S<2:0> -xxx -xxx -uuu -uuu
F2Bh CLC4SEL1 — LC4D4S<2:0> — LC4D3S<2:0> -xxx -xxx -uuu -uuu
F2Ch CLC4GLS0 LC4G1D4T LC4G1D4N LC4G1D3T LC4G1D3N LC4G1D2T LC4G1D2N LC4G1D1T LC4G1D1N xxxx xxxx uuuu uuuu
F2Dh CLC4GLS1 LC4G2D4T LC4G2D4N LC4G2D3T LC4G2D3N LC4G2D2T LC4G2D2N LC4G2D1T LC4G2D1N xxxx xxxx uuuu uuuu
F2Eh CLC4GLS2 LC4G3D4T LC4G3D4N LC4G3D3T LC4G3D3N LC4G3D2T LC4G3D2N LC4G3D1T LC4G3D1N xxxx xxxx uuuu uuuu
F2Fh CLC4GLS3 LC4G4D4T LC4G4D4N LC4G4D3T LC4G4D3N LC4G4D2T LC4G4D2N LC4G4D1T LC4G4D1N xxxx xxxx uuuu uuuu
F30h
to — Unimplemented — —
F6Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’.
Note 1: PIC16F1508/9 only.
2: Unimplemented, read as ‘1’.

 2011-2013 Microchip Technology Inc. DS40001609C-page 31

PIC16(L)F1508/9
TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
Value on
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other
POR, BOR
Resets

Bank 31
F8Ch — Unimplemented — —
—
FE3h
FE4h STATUS_ — — — — — Z_SHAD DC_SHAD C_SHAD ---- -xxx ---- -uuu
SHAD
FE5h WREG_ Working Register Shadow xxxx xxxx uuuu uuuu
SHAD
FE6h BSR_ — — — Bank Select Register Shadow ---x xxxx ---u uuuu
SHAD
FE7h PCLATH_ — Program Counter Latch High Register Shadow -xxx xxxx uuuu uuuu
SHAD
FE8h FSR0L_ Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu
SHAD
FE9h FSR0H_ Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu
SHAD
FEAh FSR1L_ Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu
SHAD
FEBh FSR1H_ Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu
SHAD
FECh — Unimplemented — —
FEDh STKPTR — — — Current Stack Pointer ---1 1111 ---1 1111
FEEh TOSL Top-of-Stack Low byte xxxx xxxx uuuu uuuu
FEFh TOSH — Top-of-Stack High byte -xxx xxxx -uuu uuuu
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’.
Note 1: PIC16F1508/9 only.
2: Unimplemented, read as ‘1’.

DS40001609C-page 32  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
3.3 PCL and PCLATH 3.3.2 COMPUTED GOTO
The Program Counter (PC) is 15 bits wide. The low byte A computed GOTO is accomplished by adding an offset to
comes from the PCL register, which is a readable and the program counter (ADDWF PCL). When performing a
writable register. The high byte (PC<14:8>) is not directly table read using a computed GOTO method, care should
readable or writable and comes from PCLATH. On any be exercised if the table location crosses a PCL memory
Reset, the PC is cleared. Figure 3-4 shows the five boundary (each 256-byte block). Refer to Application
situations for the loading of the PC. Note AN556, “Implementing a Table Read” (DS00556).

3.3.3 COMPUTED FUNCTION CALLS

FIGURE 3-4: LOADING OF PC IN
DIFFERENT SITUATIONS A computed function CALL allows programs to maintain
tables of functions and provide another way to execute
state machines or look-up tables. When performing a
Rev. 10-000042A
7/30/2013

table read using a computed function CALL, care

14 PCH PCL 0 Instruction should be exercised if the table location crosses a PCL
PC with PCL as
memory boundary (each 256-byte block).
Destination
7 8
6 0 If using the CALL instruction, the PCH<2:0> and PCL
PCLATH ALU result
registers are loaded with the operand of the CALL
instruction. PCH<6:3> is loaded with PCLATH<6:3>.
14 PCH PCL 0 GOTO, The CALLW instruction enables computed calls by com-
PC
CALL bining PCLATH and W to form the destination address.
4 11 A computed CALLW is accomplished by loading the W
6 0
PCLATH OPCODE <10:0> register with the desired address and executing CALLW.
The PCL register is loaded with the value of W and
PCH is loaded with PCLATH.
14 PCH PCL 0
PC CALLW
3.3.4 BRANCHING
6
7
0 8 The branching instructions add an offset to the PC.
PCLATH W This allows relocatable code and code that crosses
page boundaries. There are two forms of branching,
14 PCL 0
BRW and BRA. The PC will have incremented to fetch
PCH
PC BRW the next instruction in both cases. When using either
branching instruction, a PCL memory boundary may be
15
crossed.
PC + W
If using BRW, load the W register with the desired
14 PCH PCL 0
PC BRA unsigned address and execute BRW. The entire PC will
be loaded with the address PC + 1 + W.
15
If using BRA, the entire PC will be loaded with PC + 1 +,
PC + OPCODE <8:0>
the signed value of the operand of the BRA instruction.

3.3.1 MODIFYING PCL

Executing any instruction with the PCL register as the
destination simultaneously causes the Program
Counter PC<14:8> bits (PCH) to be replaced by the
contents of the PCLATH register. This allows the entire
contents of the program counter to be changed by
writing the desired upper seven bits to the PCLATH
register. When the lower eight bits are written to the
PCL register, all 15 bits of the program counter will
change to the values contained in the PCLATH register
and those being written to the PCL register.

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PIC16(L)F1508/9
3.4 Stack 3.4.1 ACCESSING THE STACK
All devices have a 16-level x 15-bit wide hardware The stack is available through the TOSH, TOSL and
stack (refer to Figures 3-5 through 3-8). The stack STKPTR registers. STKPTR is the current value of the
space is not part of either program or data space. The Stack Pointer. TOSH:TOSL register pair points to the
PC is PUSHed onto the stack when CALL or CALLW TOP of the stack. Both registers are read/writable. TOS
instructions are executed or an interrupt causes a is split into TOSH and TOSL due to the 15-bit size of the
branch. The stack is POPed in the event of a RETURN, PC. To access the stack, adjust the value of STKPTR,
RETLW or a RETFIE instruction execution. PCLATH is which will position TOSH:TOSL, then read/write to
not affected by a PUSH or POP operation. TOSH:TOSL. STKPTR is 5 bits to allow detection of
overflow and underflow.
The stack operates as a circular buffer if the STVREN
bit is programmed to ‘0‘ (Configuration Words). This Note: Care should be taken when modifying the
means that after the stack has been PUSHed sixteen STKPTR while interrupts are enabled.
times, the seventeenth PUSH overwrites the value that
During normal program operation, CALL, CALLW and
was stored from the first PUSH. The eighteenth PUSH
Interrupts will increment STKPTR while RETLW,
overwrites the second PUSH (and so on). The
RETURN, and RETFIE will decrement STKPTR. At any
STKOVF and STKUNF flag bits will be set on an Over-
time STKPTR can be inspected to see how much stack
flow/Underflow, regardless of whether the Reset is
is left. The STKPTR always points at the currently used
enabled.
place on the stack. Therefore, a CALL or CALLW will
Note 1: There are no instructions/mnemonics increment the STKPTR and then write the PC, and a
called PUSH or POP. These are actions return will unload the PC and then decrement the
that occur from the execution of the STKPTR.
CALL, CALLW, RETURN, RETLW and Reference Figure 3-5 through Figure 3-8 for examples
RETFIE instructions or the vectoring to of accessing the stack.
an interrupt address.

FIGURE 3-5: ACCESSING THE STACK EXAMPLE 1

Rev. 10-000043A
7/30/2013

Stack Reset Disabled

TOSH:TOSL 0x0F STKPTR = 0x1F
(STVREN = 0)
0x0E
0x0D
0x0C
0x0B
Initial Stack Configuration:
0x0A
0x09 After Reset, the stack is empty. The
empty stack is initialized so the Stack
0x08 Pointer is pointing at 0x1F. If the Stack
0x07 Overflow/Underflow Reset is enabled, the
TOSH/TOSL register will return ‘0’. If the
0x06 Stack Overflow/Underflow Reset is
0x05 disabled, the TOSH/TOSL register will
return the contents of stack address
0x04 0x0F.
0x03
0x02
0x01
0x00
Stack Reset Enabled
TOSH:TOSL 0x1F 0x0000 STKPTR = 0x1F
(STVREN = 1)

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 PIC16(L)F1508/9
FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2

Rev. 10-000043B
7/30/2013

0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09 This figure shows the stack configuration
after the first CALL or a single interrupt.
0x08 If a RETURN instruction is executed, the
0x07 return address will be placed in the
Program Counter and the Stack Pointer
0x06 decremented to the empty state (0x1F).
0x05
0x04
0x03
0x02
0x01
TOSH:TOSL 0x00 Return Address STKPTR = 0x00

FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3

Rev. 10-000043C
7/30/2013

0x0F
0x0E
0x0D
0x0C
After seven CALLs or six CALLs and an
0x0B interrupt, the stack looks like the figure on
the left. A series of RETURN instructions will
0x0A
repeatedly place the return addresses into
0x09 the Program Counter and pop the stack.
0x08
0x07
TOSH:TOSL 0x06 Return Address STKPTR = 0x06

0x05 Return Address

0x04 Return Address
0x03 Return Address
0x02 Return Address
0x01 Return Address
0x00 Return Address

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PIC16(L)F1508/9
FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4

Rev. 10-000043D
7/30/2013

0x0F Return Address

0x0E Return Address
0x0D Return Address
0x0C Return Address
0x0B Return Address
0x0A Return Address When the stack is full, the next CALL or
0x09 Return Address an interrupt will set the Stack Pointer to
0x10. This is identical to address 0x00 so
0x08 Return Address the stack will wrap and overwrite the
0x07 Return Address return address at 0x00. If the Stack
Overflow/Underflow Reset is enabled, a
0x06 Return Address Reset will occur and location 0x00 will
0x05 Return Address not be overwritten.

0x04 Return Address

0x03 Return Address
0x02 Return Address
0x01 Return Address
TOSH:TOSL 0x00 Return Address STKPTR = 0x10

3.4.2 OVERFLOW/UNDERFLOW RESET

If the STVREN bit in Configuration Words is
programmed to ‘1’, the device will be reset if the stack
is PUSHed beyond the sixteenth level or POPed
beyond the first level, setting the appropriate bits
(STKOVF or STKUNF, respectively) in the PCON
register.

3.5 Indirect Addressing

The INDFn registers are not physical registers. Any
instruction that accesses an INDFn register actually
accesses the register at the address specified by the
File Select Registers (FSR). If the FSRn address
specifies one of the two INDFn registers, the read will
return ‘0’ and the write will not occur (though Status bits
may be affected). The FSRn register value is created
by the pair FSRnH and FSRnL.
The FSR registers form a 16-bit address that allows an
addressing space with 65536 locations. These locations
are divided into three memory regions:
• Traditional Data Memory
• Linear Data Memory
• Program Flash Memory

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 PIC16(L)F1508/9
FIGURE 3-9: INDIRECT ADDRESSING

Rev. 10-000044A
7/30/2013

0x0000 0x0000

Traditional
Data Memory

0x0FFF 0x0FFF
0x1000
Reserved
0x1FFF
0x2000

Linear
Data Memory

0x29AF
0x29B0
Reserved
0x7FFF
FSR
0x8000 0x0000
Address
Range

Program
Flash Memory

0xFFFF 0x7FFF

Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits.

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PIC16(L)F1508/9
3.5.1 TRADITIONAL DATA MEMORY
The traditional data memory is a region from FSR
address 0x000 to FSR address 0xFFF. The addresses
correspond to the absolute addresses of all SFR, GPR
and common registers.

FIGURE 3-10: TRADITIONAL DATA MEMORY MAP

Rev. 10-000056A
7/31/2013

Direct Addressing Indirect Addressing

From Opcode
4 BSR 0 6 0 7 FSRxH 0 7 FSRxL 0
0 0 0 0

Bank Select Location Select Bank Select Location Select

00000 00001 00010 11111

0x00

0x7F
Bank 0 Bank 1 Bank 2 Bank 31

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 PIC16(L)F1508/9
3.5.2 LINEAR DATA MEMORY 3.5.3 PROGRAM FLASH MEMORY
The linear data memory is the region from FSR To make constant data access easier, the entire
address 0x2000 to FSR address 0x29AF. This region is program Flash memory is mapped to the upper half of
a virtual region that points back to the 80-byte blocks of the FSR address space. When the MSb of FSRnH is
GPR memory in all the banks. set, the lower 15 bits are the address in program
Unimplemented memory reads as 0x00. Use of the memory which will be accessed through INDF. Only the
linear data memory region allows buffers to be larger lower eight bits of each memory location is accessible
than 80 bytes because incrementing the FSR beyond via INDF. Writing to the program Flash memory cannot
one bank will go directly to the GPR memory of the next be accomplished via the FSR/INDF interface. All
bank. instructions that access program Flash memory via the
FSR/INDF interface will require one additional
The 16 bytes of common memory are not included in instruction cycle to complete.
the linear data memory region.
FIGURE 3-12: PROGRAM FLASH
FIGURE 3-11: LINEAR DATA MEMORY MEMORY MAP
MAP
Rev. 10-000057A Rev. 10-000058A
7/31/2013 7/31/2013

7 FSRnH 0 7 FSRnL 0
7 FSRnH 0 7 FSRnL 0 1
0 0 1
Location Select
Location Select 0x8000
0x2000 0x0000
0x020
Bank 0
0x06F
0x0A0
Bank 1
Program
0x0EF
Flash
0x120 Memory
Bank 2 (low 8 bits)
0x16F

0xF20
Bank 30 0x7FFF
0xF6F 0xFFFF
0x29AF

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PIC16(L)F1508/9
NOTES:

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 PIC16(L)F1508/9
4.0 DEVICE CONFIGURATION
Device configuration consists of Configuration Words,
Code Protection and Device ID.

4.1 Configuration Words

There are several Configuration Word bits that allow
different oscillator and memory protection options.
These are implemented as Configuration Word 1 at
8007h and Configuration Word 2 at 8008h.
Note: The DEBUG bit in Configuration Words is
managed automatically by device
development tools including debuggers
and programmers. For normal device
operation, this bit should be maintained as
a ‘1’.

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PIC16(L)F1508/9
4.2 Register Definitions: Configuration Words

REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1
(1) (1) (2)
FCMEN IESO CLKOUTEN BOREN<1:0> —
bit 13 bit 8

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

(3)
CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>
bit 7 bit 0

Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase

bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit

1 = Fail-Safe Clock Monitor is enabled(1)
0 = Fail-Safe Clock Monitor is disabled
bit 12 IESO: Internal External Switchover bit(1)
1 = Internal/External Switchover (Two-Speed Start-up) mode is enabled
0 = Internal/External Switchover mode is disabled
bit 11 CLKOUTEN: Clock Out Enable bit
1 = CLKOUT function is disabled. I/O function on the CLKOUT pin
0 = CLKOUT function is enabled on the CLKOUT pin
bit 10-9 BOREN<1:0>: Brown-Out Reset Enable bits(2)
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit of the BORCON register
00 = BOR disabled
bit 8 Unimplemented: Read as ‘1’
bit 7 CP: Code Protection bit(3)
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
bit 6 MCLRE: MCLR/VPP Pin Function Select bit
If LVP bit = 1:
This bit is ignored.
If LVP bit = 0:
1 = MCLR/VPP pin function is MCLR; Weak pull-up enabled.
0 = MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of
WPUA3 bit.
bit 5 PWRTE: Power-Up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 4-3 WDTE<1:0>: Watchdog Timer Enable bits
11 = WDT enabled
10 = WDT enabled while running and disabled in Sleep
01 = WDT controlled by the SWDTEN bit in the WDTCON register
00 = WDT disabled

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 PIC16(L)F1508/9
REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1 (CONTINUED)
bit 2-0 FOSC<2:0>: Oscillator Selection bits
111 = ECH:External clock, High-Power mode: on CLKIN pin
110 = ECM: External clock, Medium-Power mode: on CLKIN pin
101 = ECL: External clock, Low-Power mode: on CLKIN pin
100 = INTOSC oscillator: I/O function on CLKIN pin
011 = EXTRC oscillator: External RC circuit connected to CLKIN pin
010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins
001 = XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins
000 = LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins

Note 1: When FSCM is enabled, Two-Speed Start-up will be automatically enabled, regardless of the IESO bit value.
2: Enabling Brown-out Reset does not automatically enable Power-up Timer.
3: Once enabled, code-protect can only be disabled by bulk erasing the device.

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PIC16(L)F1508/9

REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1
(1) (3) (2)
LVP DEBUG LPBOR BORV STVREN —
bit 13 bit 8

U-1 U-1 U-1 U-1 U-1 U-1 R/P-1 R/P-1

— — — — — — WRT<1:0>
bit 7 bit 0

Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase

bit 13 LVP: Low-Voltage Programming Enable bit(1)

1 = Low-voltage programming enabled
0 = High-voltage on MCLR must be used for programming
bit 12 DEBUG: In-Circuit Debugger Mode bit(3)
1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins
0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger
bit 11 LPBOR: Low-Power BOR Enable bit
1 = Low-Power Brown-out Reset is disabled
0 = Low-Power Brown-out Reset is enabled
bit 10 BORV: Brown-Out Reset Voltage Selection bit(2)
1 = Brown-out Reset voltage (VBOR), low trip point selected
0 = Brown-out Reset voltage (VBOR), high trip point selected
bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit
1 = Stack Overflow or Underflow will cause a Reset
0 = Stack Overflow or Underflow will not cause a Reset
bit 8-2 Unimplemented: Read as ‘1’
bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits
4 kW Flash memory (PIC16(L)F1508 only)
11 = Write protection off
10 = 000h to 1FFh write protected, 200h to FFFh may be modified
01 = 000h to 7FFh write protected, 800h to FFFh may be modified
00 = 000h to FFFh write protected, no addresses may be modified
8 kW Flash memory (PIC16(L)F1509 only)
11 = Write protection off
10 = 000h to 01FFh write protected, 0200h to 1FFFh may be modified
01 = 000h to 0FFFh write protected, 1000h to 1FFFh may be modified
00 = 000h to 1FFFh write protected, no addresses may be modified

Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
2: See VBOR parameter for specific trip point voltages.
3: The DEBUG bit in Configuration Words is managed automatically by device development tools including
debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.

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 PIC16(L)F1508/9
4.3 Code Protection
Code protection allows the device to be protected from
unauthorized access. Internal access to the program
memory is unaffected by any code protection setting.

4.3.1 PROGRAM MEMORY PROTECTION

The entire program memory space is protected from
external reads and writes by the CP bit in Configuration
Words. When CP = 0, external reads and writes of
program memory are inhibited and a read will return all
‘0’s. The CPU can continue to read program memory,
regardless of the protection bit settings. Writing the
program memory is dependent upon the write
protection setting. See Section 4.4 “Write
Protection” for more information.

4.4 Write Protection

Write protection allows the device to be protected from
unintended self-writes. Applications, such as
bootloader software, can be protected while allowing
other regions of the program memory to be modified.
The WRT<1:0> bits in Configuration Words define the
size of the program memory block that is protected.

4.5 User ID
Four memory locations (8000h-8003h) are designated as
ID locations where the user can store checksum or other
code identification numbers. These locations are
readable and writable during normal execution. See
Section 10.4 “User ID, Device ID and Configuration
Word Access” for more information on accessing these
memory locations. For more information on checksum
calculation, see the “PIC12(L)F1501/PIC16(L)F150X
Memory Programming Specification” (DS41573).

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PIC16(L)F1508/9
4.6 Device ID and Revision ID
The memory location 8006h is where the Device ID and
Revision ID are stored. The upper nine bits hold the
Device ID. The lower five bits hold the Revision ID. See
Section 10.4 “User ID, Device ID and Configuration
Word Access” for more information on accessing
these memory locations.
Development tools, such as device programmers and
debuggers, may be used to read the Device ID and
Revision ID.

4.7 Register Definitions: Device ID

REGISTER 4-3: DEVID: DEVICE ID REGISTER

R R R R R R
DEV<8:3>
bit 13 bit 8

R R R R R R R R
DEV<2:0> REV<4:0>
bit 7 bit 0

Legend:
R = Readable bit
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 13-5 DEV<8:0>: Device ID bits

DEVID<13:0> Values
Device
DEV<8:0> REV<4:0>
PIC16LF1508 10 1101 111 x xxxx
PIC16F1508 10 1101 001 x xxxx
PIC16LF1509 10 1110 000 x xxxx
PIC16F1509 10 1101 010 x xxxx

bit 4-0 REV<4:0>: Revision ID bits

These bits are used to identify the revision (see Table under DEV<8:0> above).

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 PIC16(L)F1508/9
5.0 OSCILLATOR MODULE (WITH The oscillator module can be configured in one of the
following clock modes.
FAIL-SAFE CLOCK MONITOR)
1. ECL – External Clock Low-Power mode
5.1 Overview (0 MHz to 0.5 MHz)
2. ECM – External Clock Medium-Power mode
The oscillator module has a wide variety of clock (0.5 MHz to 4 MHz)
sources and selection features that allow it to be used 3. ECH – External Clock High-Power mode
in a wide range of applications while maximizing perfor- (4 MHz to 20 MHz)
mance and minimizing power consumption. Figure 5-1
4. LP – 32 kHz Low-Power Crystal mode.
illustrates a block diagram of the oscillator module.
5. XT – Medium Gain Crystal or Ceramic Resonator
Clock sources can be supplied from external oscillators, Oscillator mode (up to 4 MHz)
quartz crystal resonators, ceramic resonators and
6. HS – High Gain Crystal or Ceramic Resonator
Resistor-Capacitor (RC) circuits. In addition, the system
mode (4 MHz to 20 MHz)
clock source can be supplied from one of two internal
oscillators, with a choice of speeds selectable via 7. EXTRC – External Resistor-Capacitor
software. Additional clock features include: 8. INTOSC – Internal oscillator (31 kHz to 16 MHz)
• Selectable system clock source between external Clock Source modes are selected by the FOSC<2:0>
or internal sources via software. bits in the Configuration Words. The FOSC bits
• Two-Speed Start-up mode, which minimizes determine the type of oscillator that will be used when
latency between external oscillator start-up and the device is first powered.
code execution. The ECH, ECM, and ECL clock modes rely on an
• Fail-Safe Clock Monitor (FSCM) designed to external logic level signal as the device clock source.
detect a failure of the external clock source (LP, The LP, XT, and HS clock modes require an external
XT, HS, ECH, ECM, ECL or EXTRC modes) and crystal or resonator to be connected to the device.
switch automatically to the internal oscillator. Each mode is optimized for a different frequency range.
• Oscillator Start-up Timer (OST) ensures stability The EXTRC clock mode requires an external resistor
of crystal oscillator sources and capacitor to set the oscillator frequency.
• Fast start-up oscillator allows internal circuits to The INTOSC internal oscillator block produces a low
power-up and stabilize before switching to the 16 and high-frequency clock source, designated
MHz HFINTOSC LFINTOSC and HFINTOSC. (See Internal Oscillator
Block, Figure 5-1). A wide selection of device clock
frequencies may be derived from these two clock
sources.

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PIC16(L)F1508/9
FIGURE 5-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM

Rev. 10-000030A
7/30/2013
CLKIN/ OSC1/
SOSCI/ T1CKI
Sleep
Primary
Oscillator Primary Clock
(OSC)
(1)
FOSC(1)
CLKOUT/ OSC2/ Secondary Clock
SOSCO/ T1G Secondary to CPU and
Oscillator Peripherals
INTOSC
(SOSC)

IRCF<3:0>
HFINTOSC
16 MHz 4
Start-up 8 MHz
Control Logic 4 MHz Clock
2 MHz Control
16 MHz 1 MHz
Prescaler

Oscillator (1)
HFINTOSC *500 kHz 3 2
Fast Start-up *250 kHz FOSC<2:0> SCS<1:0>
Oscillator *125 kHz
62.5 kHz
*31.25 kHz
*31 kHz
LFINTOSC
31 kHz LFINTOSC(1)
to WDT, PWRT, and
Oscillator other Peripherals

FRC
600 kHz FRC(1) to ADC and
Oscillator other Peripherals

* Available with more than one IRCF selection

Note 1: See Section 5.2.2.4 “Peripheral Clock Sources”.

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 PIC16(L)F1508/9
5.2 Clock Source Types The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
Clock sources can be classified as external, internal or operation after a Power-On Reset (POR) or wake-up
peripheral. from Sleep. Because the PIC® MCU design is fully
External clock sources rely on external circuitry for the static, stopping the external clock input will have the
clock source to function. Examples are: oscillator mod- effect of halting the device while leaving all data intact.
ules (ECH, ECM, ECL modes), quartz crystal resona- Upon restarting the external clock, the device will
tors or ceramic resonators (LP, XT and HS modes) and resume operation as if no time had elapsed.
Resistor-Capacitor (EXTRC) mode circuits.
Internal clock sources are contained within the oscillator FIGURE 5-2: EXTERNAL CLOCK (EC)
module. The internal oscillator block has two internal MODE OPERATION
oscillators that are used to generate the internal system Rev. 10-000045A
7/30/2013

clock sources: the 16 MHz High-Frequency Internal

Oscillator (HFINTOSC) and the 31 kHz Low-Frequency
Internal Oscillator (LFINTOSC).
Clock from
The peripheral clock source is a nominal 600 kHz OSC1/CLKIN
Ext. system
internal RC oscillator, FRC. The FRC is traditionally PIC® MCU
used with the ADC module, but is sometimes available FOSC/4 or I/O(1) OSC2/CLKOUT
to other peripherals. See Section 5.2.2.4 “Peripheral
Clock Sources”.
The system clock can be selected between external or Note 1: Output depends upon the CLKOUTEN bit
internal clock sources via the System Clock Select of the Configuration Words.
(SCS) bits in the OSCCON register. See Section 5.3
“Clock Switching” for additional information.
5.2.1.2 LP, XT, HS Modes
5.2.1 EXTERNAL CLOCK SOURCES The LP, XT and HS modes support the use of quartz
An external clock source can be used as the device crystal resonators or ceramic resonators connected to
system clock by performing one of the following OSC1 and OSC2 (Figure 5-3). The three modes select
actions: a low, medium or high gain setting of the internal
inverter-amplifier to support various resonator types
• Program the FOSC<2:0> bits in the Configuration
and speed.
Words to select an external clock source that will
be used as the default system clock upon a LP Oscillator mode selects the lowest gain setting of the
device Reset. internal inverter-amplifier. LP mode current consumption
• Write the SCS<1:0> bits in the OSCCON register is the least of the three modes. This mode is designed to
to switch the system clock source to: drive only 32.768 kHz tuning-fork type crystals (watch
crystals).
- Secondary oscillator during run-time, or
- An external clock source determined by the XT Oscillator mode selects the intermediate gain
value of the FOSC bits. setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three modes.
See Section 5.3 “Clock Switching” for more informa- This mode is best suited to drive resonators with a
tion. medium drive level specification.
5.2.1.1 EC Mode HS Oscillator mode selects the highest gain setting of the
internal inverter-amplifier. HS mode current consumption
The External Clock (EC) mode allows an externally is the highest of the three modes. This mode is best
generated logic level signal to be the system clock suited for resonators that require a high drive setting.
source. When operating in this mode, an external clock
source is connected to the OSC1 input. Figure 5-3 and Figure 5-4 show typical circuits for
OSC2/CLKOUT is available for general purpose I/O or quartz crystal and ceramic resonators, respectively.
CLKOUT. Figure 5-2 shows the pin connections for EC
mode.
EC mode has three power modes to select from through
the FOSC bits in the Configuration Words:
• ECH – High-power, 4-20 MHz
• ECM – Medium-power, 0.5-4 MHz
• ECL – Low-power, 0-0.5 MHz

 2011-2013 Microchip Technology Inc. DS40001609C-page 49

PIC16(L)F1508/9
FIGURE 5-3: QUARTZ CRYSTAL FIGURE 5-4: CERAMIC RESONATOR
OPERATION (LP, XT OR OPERATION
HS MODE) (XT OR HS MODE)
Rev. 10-000059A Rev. 10-000060A
7/30/2013 7/30/2013

Ceramic PIC® MCU

PIC® MCU Resonator OSC1/CLKIN
OSC1/CLKIN
C1 To Internal
C1 To Internal Logic
Logic
Quartz RP(3) RF(2) Sleep
Crystal RF(2) Sleep

OSC2/CLKOUT
C2 RS(1)
OSC2/CLKOUT
C2 RS(1)

Note 1: A series resistor (Rs) may be required for

Note 1: A series resistor (Rs) may be required for ceramic resonators with low drive level.
quartz crystals with low drive level.
2: The value of RF varies with the Oscillator mode
2: The value of RF varies with the Oscillator mode selected (typically between 2 MΩ and 10 MΩ).
selected (typically between 2 MΩ and 10 MΩ).
3. An additional parallel feedback resistor (RP)
may be required for proper ceramic resonator
operation.
Note 1: Quartz crystal characteristics vary
according to type, package and
manufacturer. The user should consult the 5.2.1.3 Oscillator Start-up Timer (OST)
manufacturer data sheets for specifications If the oscillator module is configured for LP, XT or HS
and recommended application. modes, the Oscillator Start-up Timer (OST) counts
2: Always verify oscillator performance over 1024 oscillations from OSC1. This occurs following a
the VDD and temperature range that is Power-On Reset (POR) and when the Power-up Timer
expected for the application. (PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
3: For oscillator design assistance, reference increment and program execution is suspended,
the following Microchip Applications Notes: unless either FSCM or Two-Speed Start-Up are
• AN826, “Crystal Oscillator Basics and enabled. In this case, code will continue to execute at
Crystal Selection for rfPIC® and PIC® the selected INTOSC frequency while the OST is
Devices” (DS00826) counting. The OST ensures that the oscillator circuit,
• AN849, “Basic PIC® Oscillator Design” using a quartz crystal resonator or ceramic resonator,
(DS00849) has started and is providing a stable system clock to
• AN943, “Practical PIC® Oscillator the oscillator module.
Analysis and Design” (DS00943) In order to minimize latency between external oscillator
• AN949, “Making Your Oscillator Work” start-up and code execution, the Two-Speed Clock
(DS00949) Start-up mode can be selected (see Section 5.4
“Two-Speed Clock Start-up Mode”).

DS40001609C-page 50  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
5.2.1.4 Secondary Oscillator 5.2.1.5 External RC Mode
The secondary oscillator is a separate crystal oscillator The External Resistor-Capacitor (EXTRC) mode
that is associated with the Timer1 peripheral. It is opti- supports the use of an external RC circuit. This allows the
mized for timekeeping operations with a 32.768 kHz designer maximum flexibility in frequency choice while
crystal connected between the SOSCO and SOSCI keeping costs to a minimum when clock accuracy is not
device pins. required.
The secondary oscillator can be used as an alternate The RC circuit connects to OSC1. OSC2/CLKOUT is
system clock source and can be selected during available for general purpose I/O or CLKOUT. The
run-time using clock switching. Refer to Section 5.3 function of the OSC2/CLKOUT pin is determined by the
“Clock Switching” for more information. CLKOUTEN bit in Configuration Words.
Figure 5-6 shows the External RC mode connections.
FIGURE 5-5: QUARTZ CRYSTAL
OPERATION FIGURE 5-6: EXTERNAL RC MODES
(SECONDARY Rev. 10-000062A

OSCILLATOR) 7/31/2013

Rev. 10-000061A
7/30/2013
VDD
PIC® MCU
PIC® MCU REXT

SOSCI OSC1/CLKIN Internal

Clock
C1 CEXT
To Internal
Logic
32.768 kHz
VSS
Quartz
Crystal FOSC/4 OSC2/CLKOUT
or I/O(1)
SOSCO Recommended values:10 kŸ ” REXT ” 100 kŸ, <3V
C2 3 kŸ ” REXT ” 100 kŸ, 3-5V
CEXT > 20 pF, 2-5V

Note 1: Output depends upon the CLKOUTEN bit of the

Configuration Words.
Note 1: Quartz crystal characteristics vary
according to type, package and
manufacturer. The user should consult the The RC oscillator frequency is a function of the supply
manufacturer data sheets for specifications voltage, the resistor (REXT) and capacitor (CEXT) values
and recommended application. and the operating temperature. Other factors affecting
the oscillator frequency are:
2: Always verify oscillator performance over
the VDD and temperature range that is • threshold voltage variation
expected for the application. • component tolerances
• packaging variations in capacitance
3: For oscillator design assistance, reference
the following Microchip Applications Notes: The user also needs to take into account variation due
to tolerance of the external RC components used.
• AN826, “Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
Devices” (DS00826)
• AN849, “Basic PIC® Oscillator Design”
(DS00849)
• AN943, “Practical PIC® Oscillator
Analysis and Design” (DS00943)
• AN949, “Making Your Oscillator Work”
(DS00949)
• TB097, “Interfacing a Micro Crystal
MS1V-T1K 32.768 kHz Tuning Fork
Crystal to a PIC16F690/SS” (DS91097)
• AN1288, “Design Practices for
Low-Power External Oscillators”
(DS01288)

 2011-2013 Microchip Technology Inc. DS40001609C-page 51

PIC16(L)F1508/9
5.2.2 INTERNAL CLOCK SOURCES 5.2.2.2 LFINTOSC
The device may be configured to use the internal oscil- The Low-Frequency Internal Oscillator (LFINTOSC) is
lator block as the system clock by performing one of the a 31 kHz internal clock source.
following actions: The output of the LFINTOSC connects to a multiplexer
• Program the FOSC<2:0> bits in Configuration (see Figure 5-1). Select 31 kHz, via software, using the
Words to select the INTOSC clock source, which IRCF<3:0> bits of the OSCCON register. See
will be used as the default system clock upon a Section 5.2.2.6 “Internal Oscillator Clock Switch
device Reset. Timing” for more information. The LFINTOSC is also
• Write the SCS<1:0> bits in the OSCCON register the frequency for the Power-up Timer (PWRT),
to switch the system clock source to the internal Watchdog Timer (WDT) and Fail-Safe Clock Monitor
oscillator during run-time. See Section 5.3 (FSCM).
“Clock Switching”for more information. The LFINTOSC is enabled by selecting 31 kHz
In INTOSC mode, OSC1/CLKIN is available for general (IRCF<3:0> bits of the OSCCON register = 000) as the
purpose I/O. OSC2/CLKOUT is available for general system clock source (SCS bits of the OSCCON
purpose I/O or CLKOUT. register = 1x), or when any of the following are
enabled:
The function of the OSC2/CLKOUT pin is determined
by the CLKOUTEN bit in Configuration Words. • Configure the IRCF<3:0> bits of the OSCCON
register for the desired LF frequency, and
The internal oscillator block has two independent
oscillators that provides the internal system clock • FOSC<2:0> = 100, or
source. • Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’.
1. The HFINTOSC (High-Frequency Internal
Oscillator) is factory calibrated and operates at Peripherals that use the LFINTOSC are:
16 MHz. • Power-up Timer (PWRT)
2. The LFINTOSC (Low-Frequency Internal • Watchdog Timer (WDT)
Oscillator) operates at 31 kHz. • Fail-Safe Clock Monitor (FSCM)
5.2.2.1 HFINTOSC The Low-Frequency Internal Oscillator Ready bit
(LFIOFR) of the OSCSTAT register indicates when the
The High-Frequency Internal Oscillator (HFINTOSC) is
LFINTOSC is running.
a factory calibrated 16 MHz internal clock source.
The output of the HFINTOSC connects to a postscaler 5.2.2.3 FRC
and multiplexer (see Figure 5-1). The frequency derived The FRC clock is an uncalibrated, nominal 600 kHz
from the HFINTOSC can be selected via software using peripheral clock source.
the IRCF<3:0> bits of the OSCCON register. See
Section 5.2.2.6 “Internal Oscillator Clock Switch The FRC is automatically turned on by the peripherals
Timing” for more information. requesting the FRC clock.

The HFINTOSC is enabled by: The FRC clock continues to run during Sleep.

• Configure the IRCF<3:0> bits of the OSCCON

register for the desired HF frequency, and
• FOSC<2:0> = 100, or
• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’.
A fast start-up oscillator allows internal circuits to
power-up and stabilize before switching to HFINTOSC.
The High-Frequency Internal Oscillator Ready bit
(HFIOFR) of the OSCSTAT register indicates when the
HFINTOSC is running.
The High-Frequency Internal Oscillator Stable bit
(HFIOFS) of the OSCSTAT register indicates when the
HFINTOSC is running within 0.5% of its final value.

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 PIC16(L)F1508/9
5.2.2.4 Peripheral Clock Sources 5.2.2.5 Internal Oscillator Frequency
The clock sources described in this chapter and the Selection
Timer’s are available to different peripherals. Table 5-1 The system clock speed can be selected via software
lists the clocks and timers available for each peripheral. using the Internal Oscillator Frequency Select bits
IRCF<3:0> of the OSCCON register.
TABLE 5-1: PERIPHERAL CLOCK The postscaled output of the 16 MHz HFINTOSC and
SOURCES 31 kHz LFINTOSC connect to a multiplexer (see
Figure 5-1). The Internal Oscillator Frequency Select
HFINTOSC

LFINTOSC
bits IRCF<3:0> of the OSCCON register (Register 5-1)

SOSC
FOSC

TMR0

TMR1

TMR2
FRC

select the frequency output of the internal oscillators.

Note: Following any Reset, the IRCF<3:0> bits
of the OSCCON register are set to ‘0111’
ADC X X and the frequency selection is set to
CLC X X X X X X X X 500 kHz. The user can modify the IRCF
COMP X X bits to select a different frequency.
CWG X X The IRCF<3:0> bits of the OSCCON register allow
EUSART X X duplicate selections for some frequencies. These dupli-
cate choices can offer system design trade-offs. Lower
MSSP X X
power consumption can be obtained when changing
NCO X X oscillator sources for a given frequency. Faster transi-
PWM X X tion times can be obtained between frequency changes
PWRT X that use the same oscillator source.
TMR0 X 5.2.2.6 Internal Oscillator Clock Switch
TMR1 X X X Timing
TMR2 X When switching between the HFINTOSC and the
WDT X LFINTOSC, the new oscillator may already be shut
down to save power (see Figure 5-7). If this is the case,
there is a delay after the IRCF<3:0> bits of the
OSCCON register are modified before the frequency
selection takes place. The OSCSTAT register will
reflect the current active status of the HFINTOSC and
LFINTOSC oscillators. The sequence of a frequency
selection is as follows:
1. IRCF<3:0> bits of the OSCCON register are
modified.
2. If the new clock is shut down, a clock start-up
delay is started.
3. Clock switch circuitry waits for a falling edge of
the current clock.
4. The current clock is held low and the clock
switch circuitry waits for a rising edge in the new
clock.
5. The new clock is now active.
6. The OSCSTAT register is updated as required.
7. Clock switch is complete.
See Figure 5-7 for more details.
If the internal oscillator speed is switched between two
clocks of the same source, there is no start-up delay
before the new frequency is selected. Clock switching
time delays are shown in Table 5-3.
Start-up delay specifications are located in Table 29-8,
“Oscillator Parameters”.

 2011-2013 Microchip Technology Inc. DS40001609C-page 53

PIC16(L)F1508/9
FIGURE 5-7: INTERNAL OSCILLATOR SWITCH TIMING

HFINTOSC LFINTOSC (FSCM and WDT disabled)

HFINTOSC
Oscillator Delay(1) 2-cycle Sync Running

LFINTOSC

IRCF <3:0> 0 0

System Clock

HFINTOSC LFINTOSC (Either FSCM or WDT enabled)

HFINTOSC
2-cycle Sync Running

LFINTOSC

IRCF <3:0> 0 0

System Clock

LFINTOSC HFINTOSC
LFINTOSC turns off unless WDT or FSCM is enabled(2)
LFINTOSC
Oscillator Delay(1) 2-cycle Sync Running

HFINTOSC

IRCF <3:0> =0 0
System Clock

Note 1: See Table 5-3, “Oscillator Switching Delays” for more information.
2: LFINTOSC will continue to run if a peripheral has selected it as the clock source. See
Section 5.2.2.4 “Peripheral Clock Sources”.

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 PIC16(L)F1508/9
5.3 Clock Switching When Fail-Safe Clock Monitor and/or Two-Speed
Start-up are enabled, (FCMEN = 1 and/or IESO = 1),
The system clock source can be switched between the device will operate using the internal oscillator
external and internal clock sources via software using (INTOSC) selected by the IRCF<3:0> bits, whenever
the System Clock Select (SCS) bits of the OSCCON OSTS = 0. When the OST period expires,
register. The following clock sources can be selected (OSTS = 1), the system clock will switch to the external
using the SCS bits: oscillator selected.
• Default system oscillator determined by FOSC When Fail-Safe Clock Monitor and Two-Speed
bits in Configuration Words Start-up are disabled, (FCMEN = 0 and IESO = 0), the
• Secondary oscillator 32 kHz crystal device will be held in Reset while OSTS = 0. When
• Internal Oscillator Block (INTOSC) OST period expires, (OSTS = 1), Reset will be
released and execution will begin 10 FOSC cycles later
5.3.1 SYSTEM CLOCK SELECT (SCS) using the external oscillator selected.
BITS For definition of the OSTS bit with clock sources other
The System Clock Select (SCS) bits of the OSCCON than external oscillator modes (HS, XT or LP), see
register selects the system clock source that is used for Table 5-2.
the CPU and peripherals. The OSTS bit does not reflect the status of the
• When the SCS bits of the OSCCON register = 00, secondary oscillator.
the system clock source is determined by value of
the FOSC<2:0> bits in the Configuration Words.
TABLE 5-2: OSTS BIT DEFINITION
• When the SCS bits of the OSCCON register = 01,
the system clock source is the secondary SCS<1:0> bits
oscillator. FOSC<2:0>
00 01 1x
• When the SCS bits of the OSCCON register = 1x, selection
the system clock source is chosen by the internal OSTS value
oscillator frequency selected by the IRCF<3:0>
INTOSC 0 0 0
bits of the OSCCON register. After a Reset, the
SCS bits of the OSCCON register are always ECH, ECM, ECL,
1 0 0
cleared. EXTRC
Note: Any automatic clock switch, which may HS, XT, LP normal* 0 0
occur from Two-Speed Start-up or * Normal function for oscillator modes (OSTS = 0),
Fail-Safe Clock Monitor, does not update while OST counting (OSTS = 1), after OST count
the SCS bits of the OSCCON register. The has expired.
user can monitor the OSTS bit of the
OSCSTAT register to determine the current 5.3.3 SECONDARY OSCILLATOR
system clock source. See Table 5-2. The secondary oscillator is a separate crystal oscillator
When switching between clock sources, a delay is associated with the Timer1 peripheral. It is optimized
required to allow the new clock to stabilize. These oscil- for timekeeping operations with a 32.768 kHz crystal
lator delays are shown in Table 5-3. connected between the SOSCO and SOSCI device
pins.
5.3.2 OSCILLATOR START-UP TIMER The secondary oscillator is enabled using the
STATUS (OSTS) BIT T1OSCEN control bit in the T1CON register. See
The Oscillator Start-up Timer Status (OSTS) bit in the Section 19.0 “Timer1 Module with Gate Control” for
OSCSTAT register has different definitions that are more information about the Timer1 peripheral.
dependent on the FOSC bit selection in the
Configuration Word. Table 5-2 defines the OSTS bit 5.3.4 SECONDARY OSCILLATOR READY
value for the FOSC selections. (SOSCR) BIT
The normal function of the OSTS bit is when The user must ensure that the secondary oscillator is
FOSC<2:0> selects one of the external oscillator ready to be used before it is selected as a system clock
modes, HS, XT or LP, while the OST is counting pulses source. The Secondary Oscillator Ready (SOSCR) bit
on the OSC1 pin from the external oscillator, of the OSCSTAT register indicates whether the
OSTS = 0. When the OST has counted 1024 pulses, secondary oscillator is ready to be used. After the
the OSTS bit should be set, OSTS = 1, indicating the SOSCR bit is set, the SCS bits can be configured to
oscillator is stable and ready to be used. select the secondary oscillator.

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PIC16(L)F1508/9
5.4 Two-Speed Clock Start-up Mode 5.4.1 TWO-SPEED START-UP MODE
CONFIGURATION
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external oscil- Two-Speed Start-up mode is configured by the following
lator start-up and code execution. In applications that settings:
make heavy use of the Sleep mode, Two-Speed Start-up • IESO (of the Configuration Words) = 1;
will remove the external oscillator start-up time from the Internal/External Switchover bit (Two-Speed
time spent awake and can reduce the overall power con- Start-up mode enabled).
sumption of the device. This mode allows the application • SCS (of the OSCCON register) = 00.
to wake-up from Sleep, perform a few instructions using
• FOSC<2:0> bits in the Configuration Words
the INTOSC internal oscillator block as the clock source
configured for LP, XT or HS mode.
and go back to Sleep without waiting for the external
oscillator to become stable. Two-Speed Start-up mode is entered after:
Two-Speed Start-up provides benefits when the oscilla- • Power-On Reset (POR) and, if enabled, after
tor module is configured for LP, XT, or HS modes. The Power-up Timer (PWRT) has expired, or
Oscillator Start-up Timer (OST) is enabled for these • Wake-up from Sleep.
modes and must count 1024 oscillations before the oscil-
lator can be used as the system clock source.
If the oscillator module is configured for any mode Note: When FSCM is enabled, Two-Speed
other than LP, XT or HS mode, then Two-Speed Start-up will automatically be enabled.
Start-up is disabled. This is because the external clock
oscillator does not require any stabilization time after 5.4.2 TWO-SPEED START-UP
POR or an exit from Sleep. SEQUENCE
If the OST count reaches 1024 before the device enters 1. Wake-up from Power-on Reset or Sleep.
Sleep mode, the OSTS bit of the OSCSTAT register is 2. Instructions begin execution by the internal
set and program execution switches to the external oscil- oscillator at the frequency set in the IRCF<3:0>
lator. However, the system may never operate from the bits of the OSCCON register.
external oscillator if the time spent awake is very short. 3. OST enabled to count 1024 clock cycles.
4. OST timed out, wait for falling edge of the
Note: Executing a SLEEP instruction will abort
internal oscillator.
the oscillator start-up time and will cause
the OSTS bit of the OSCSTAT register to 5. OSTS is set.
remain clear. 6. System clock held low until the next falling edge
of new clock (LP, XT or HS mode).
7. System clock is switched to external clock
source.

5.4.3 CHECKING TWO-SPEED CLOCK

STATUS
Checking the state of the OSTS bit of the OSCSTAT
register will confirm if the CPU is running from the
external clock source, as defined by the FOSC<2:0>
bits in the Configuration Words, or the internal oscilla-
tor. See Table 5-2.

TABLE 5-3: OSCILLATOR SWITCHING DELAYS

Switch From Switch To Oscillator Delay
LFINTOSC 1 cycle of each clock source
HFINTOSC 2 s (approx.)
Any clock source ECH, ECM, ECL, EXTRC 2 cycles
LP, XT, HS 1024 Clock Cycles (OST)
Secondary Oscillator 1024 Secondary Oscillator Cycles

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 PIC16(L)F1508/9
FIGURE 5-8: TWO-SPEED START-UP

INTOSC

TOST

OSC1 0 1 1022 1023

OSC2

Program Counter PC - N PC PC + 1

System Clock

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PIC16(L)F1508/9
5.5 Fail-Safe Clock Monitor 5.5.3 FAIL-SAFE CONDITION CLEARING
The Fail-Safe Clock Monitor (FSCM) allows the device When a Fail-Safe condition exists, the user must take
to continue operating should the external oscillator or the following actions to clear the condition before
external clock fail. If an oscillator mode is selected, the returning to normal operation with the external source.
FSCM can detect oscillator failure any time after the The next sections describe how to clear the Fail-Safe
Oscillator Start-up Timer (OST) has expired. When an condition for specific clock selections (FOSC bits) and
external clock mode is selected, the FSCM can detect clock switching modes (SCS bit settings).
failure as soon as the device is released from Reset.
FSCM is enabled by setting the FCMEN bit in the 5.5.3.1 External Oscillator with
Configuration Words. The FSCM is applicable to external SCS<1:0> = 00
oscillator modes (LP, XT, HS) and external clock modes When a Fail-Safe condition occurs with the FOSC bits
(ECH, ECM, ECL, EXTRC) and the Secondary Oscillator selecting external oscillator (FOSC<2:0> = HS, XT, LP)
(SOSC). and the clock switch has been selected to run from the
FOSC selection (SCS<1:0> = 00), the condition is
FIGURE 5-9: FSCM BLOCK DIAGRAM cleared by performing the following procedure.
Clock Monitor When SCS<1:0> = 00 (Running from FOSC selection)
Latch SCS<1:0> = 1x:
External
S Q
Clock Change the SCS bits in the OSCCON register
to select the internal oscillator block. This resets
the OST timer and allows it to operate again.
LFINTOSC
÷ 64 R Q OSFIF = 0:
Oscillator
Clear the OSFIF bit in the PIR2 register.
31 kHz 488 Hz
(~32 s) (~2 ms) SCS<1:0> = 00:
Change the SCS bits in the OSCCON register
Sample Clock Clock to select the FOSC Configuration Word clock
Failure selection. This will start the OST. The CPU will
Detected continue to operate from the internal oscillator
until the OST count is reached. When OST
expires, the clock module will switch to the
5.5.1 FAIL-SAFE DETECTION
external oscillator and the Fail-Safe condition
The FSCM module detects a failed oscillator by will be cleared.
monitoring falling clock edges and using LFINTOSC as a
If the Fail-Safe condition still exists, the OSFIF bit will
time base. See Figure 5-9. Detection of a failed oscillator
again be set by hardware.
will take 32 to 96 cycles of the LFINTOSC. Figure 5-10
shows a timing diagram of the FSCM module. 5.5.3.2 External Clock with SCS<1:0> = 00
5.5.2 FAIL-SAFE OPERATION When a Fail-Safe condition occurs with the FOSC bits
selecting external clock (FOSC<2:0> = ECH, ECM,
When the external clock fails, the FSCM switches the
ECL, EXTRC) and the clock switch has selected to run
CPU clock to an internal clock source and sets the OSFIF
from the FOSC selection (SCS<1:0> = 00), the condi-
bit of the PIR2 register. The internal clock source is
tion is cleared by performing the following procedure.
determined by the IRCF<3:0> bits in the OSCCON
register. When SCS<1:0> = 00 (Running from FOSC selection)
When the OSFIF bit is set, an interrupt will be generated, SCS<1:0> = 1x:
if the OSFIE bit in the PIE2 register is enabled. The user’s Change the SCS bits in the OSCCON register
firmware in the Interrupt Service Routine (ISR) can then to select the internal oscillator block. This resets
take steps to mitigate the problems that may arise from the OST timer and allows it to operate again.
the failed clock.
OSFIF = 0:
The system clock will continue to be sourced from the
Clear the OSFIF bit in the PIR2 register.
internal clock source until the fail-safe condition has
been cleared, see Section 5.5.3 “Fail-Safe Condition
Clearing”.

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 PIC16(L)F1508/9
SCS<1:0> = 00: SCS<1:0> = 01:
Change the SCS bits in the OSCCON register Change the SCS bits in the OSCCON register
to select the FOSC Configuration Word clock to select the secondary oscillator. The clock
selection. Since the OST is not applicable with module will immediately switch to the
external clocks, the clock module will secondary oscillator and the fail-safe condition
immediately switch to the external clock, and will be cleared.
the fail-safe condition will be cleared. If the Fail-Safe condition still exists, the OSFIF bit will
If the Fail-Safe condition still exists, the OSFIF bit will again be set by hardware.
again be set by hardware.
5.5.4 RESET OR WAKE-UP FROM SLEEP
5.5.3.3 Secondary Oscillator with The FSCM is designed to detect external oscillator or
SCS<1:0> = 01 external clock failures.
When a Fail-Safe condition occurs with the clock switch When FSCM is used with an external oscillator, the
selected to run from the Secondary Oscillator selection Oscillator Start-up Timer (OST) count must expire
(SCS<1:0> = 01), regardless of the FOSC selection, before the FSCM becomes active. The OST is used
the condition is cleared by performing the following pro- after waking up from Sleep and after any type of Reset.
cedure.
When the FSCM is used with external clocks, the OST
SCS<1:0> = 01 (Secondary Oscillator) is not used and the FSCM will be active as soon as the
SCS<1:0> = 1x: Reset or wake-up has completed.
Change the SCS bits in the OSCCON register When the FSCM is enabled, the Two-Speed Start-up is
to select the internal oscillator block. also enabled. Therefore, the device will always be exe-
cuting code while the OST is operating.
OSFIF = 0:
Clear the OSFIF bit in the PIR2 register. Note: Due to the wide range of oscillator start-up
times, the Fail-Safe circuit is not active
Read SOSCR: during oscillator start-up (i.e., after exiting
The OST is not used with the secondary Reset or Sleep).
oscillator, therefore, the user must determine if
the secondary oscillator is ready by monitoring
the SOSCR bit in the OSCSTAT register.
When the SOSCR bit is set, the secondary
oscillator is ready.

FIGURE 5-10: FSCM TIMING DIAGRAM

Sample Clock

System Oscillator
Clock Failure
Output

Clock Monitor Output

(Q)
Failure
Detected
OSFIF

Test Test Test

Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.

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PIC16(L)F1508/9
5.6 Register Definitions: Oscillator Control

REGISTER 5-1: OSCCON: OSCILLATOR CONTROL REGISTER

U-0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 R/W-0/0 R/W-0/0
— IRCF<3:0> — SCS<1:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 Unimplemented: Read as ‘0’

bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits
1111 = 16 MHz
1110 = 8 MHz
1101 = 4 MHz
1100 = 2 MHz
1011 = 1 MHz
1010 = 500 kHz(1)
1001 = 250 kHz(1)
1000 = 125 kHz(1)
0111 = 500 kHz (default upon Reset)
0110 = 250 kHz
0101 = 125 kHz
0100 = 62.5 kHz
001x = 31.25 kHz
000x = 31 kHz LF
bit 2 Unimplemented: Read as ‘0’
bit 1-0 SCS<1:0>: System Clock Select bits
1x = Internal oscillator block
01 = Secondary oscillator
00 = Clock determined by FOSC<2:0> in Configuration Words.

Note 1: Duplicate frequency derived from HFINTOSC.

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REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER

R-1/q U-0 R-q/q R-0/q U-0 U-0 R-0/q R-0/q
SOSCR — OSTS HFIOFR — — LFIOFR HFIOFS
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional

bit 7 SOSCR: Secondary Oscillator Ready bit

If T1OSCEN = 1:
1 = Secondary oscillator is ready
0 = Secondary oscillator is not ready
If T1OSCEN = 0:
1 = Timer1 clock source is always ready
bit 6 Unimplemented: Read as ‘0’
bit 5 OSTS: Oscillator Start-up Timer Status bit
When the FOSC<2:0> bits select HS, XT or LP oscillator:
1 = OST has counted 1024 clocks, device is clocked by the FOSC<2:0> bit selection
0 = OST is counting, device is clocked from the internal oscillator (INTOSC) selected by the IRCF<3:0>
bits.
For all other FOSC<2:0> bit selections:
See Table 5-2, “OSTS Bit Definition”.
bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit
1 = HFINTOSC is ready
0 = HFINTOSC is not ready
bit 3-2 Unimplemented: Read as ‘0’
bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit
1 = LFINTOSC is ready
0 = LFINTOSC is not ready
bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit
1 = HFINTOSC 16 MHz Oscillator is stable and is driving the INTOSC
0 = HFINTOSC 16 MHz is not stable, the Start-up Oscillator is driving INTOSC

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TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
OSCCON — IRCF<3:0> — SCS<1:0> 60
OSCSTAT SOSCR — OSTS HFIOFR — — LFIOFR HFIOFS 61
PIE2 OSFIE C2IE C1IE — BCL1IE NCO1IE — — 78
PIR2 OSFIF C2IF C1IF — BCL1IF NCO1IF — — 81
T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 173
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

TABLE 5-5: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES

Register
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0
on Page

13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> —

CONFIG1 42
7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

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6.0 RESETS
There are multiple ways to reset this device:
• Power-On Reset (POR)
• Brown-Out Reset (BOR)
• Low-Power Brown-Out Reset (LPBOR)
• MCLR Reset
• WDT Reset
• RESET instruction
• Stack Overflow
• Stack Underflow
• Programming mode exit
To allow VDD to stabilize, an optional power-up timer
can be enabled to extend the Reset time after a BOR
or POR event.
A simplified block diagram of the On-chip Reset Circuit
is shown in Figure 6-1.

FIGURE 6-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

Rev. 10-000006A
8/14/2013

ICSP™ Programming Mode Exit

RESET Instruction

Stack Underflow
Stack Overlfow

MCLRE
VPP/MCLR
Sleep

WDT
Time-out Device
Reset

Power-on
Reset
VDD
BOR
Active(1)
Brown-out R
Power-up
Reset
Timer

LFINTOSC
LPBOR PWRTE
Reset

Note 1: See Table 6-1 for BOR active conditions.

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6.1 Power-On Reset (POR) 6.2 Brown-Out Reset (BOR)
The POR circuit holds the device in Reset until VDD has The BOR circuit holds the device in Reset when VDD
reached an acceptable level for minimum operation. reaches a selectable minimum level. Between the
Slow rising VDD, fast operating speeds or analog POR and BOR, complete voltage range coverage for
performance may require greater than minimum VDD. execution protection can be implemented.
The PWRT, BOR or MCLR features can be used to The Brown-out Reset module has four operating
extend the start-up period until all device operation modes controlled by the BOREN<1:0> bits in Configu-
conditions have been met. ration Words. The four operating modes are:
6.1.1 POWER-UP TIMER (PWRT) • BOR is always on
The Power-up Timer provides a nominal 64 ms • BOR is off when in Sleep
time-out on POR or Brown-out Reset. • BOR is controlled by software
The device is held in Reset as long as PWRT is active. • BOR is always off
The PWRT delay allows additional time for the VDD to Refer to Table 6-1 for more information.
rise to an acceptable level. The Power-up Timer is The Brown-out Reset voltage level is selectable by
enabled by clearing the PWRTE bit in Configuration configuring the BORV bit in Configuration Words.
Words.
A VDD noise rejection filter prevents the BOR from trig-
The Power-up Timer starts after the release of the POR gering on small events. If VDD falls below VBOR for a
and BOR. duration greater than parameter TBORDC, the device
For additional information, refer to Application Note will reset. See Figure 6-2 for more information.
AN607, “Power-up Trouble Shooting” (DS00607).

TABLE 6-1: BOR OPERATING MODES

Instruction Execution upon:
BOREN<1:0> SBOREN Device Mode BOR Mode
Release of POR or Wake-up from Sleep

11 X X Active Waits for BOR ready(1)

(BORRDY = 1)
Awake Active Waits for BOR ready
10 X (BORRDY = 1)
Sleep Disabled
1 Active Waits for BOR ready(1)
X
01 (BORRDY = 1)
0 X Disabled Begins immediately
(BORRDY = x)
00 X X Disabled
Note 1: In these specific cases, “release of POR” and “wake-up from Sleep,” there is no delay in start-up. The BOR
ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR
circuit is forced on by the BOREN<1:0> bits.

6.2.1 BOR IS ALWAYS ON BOR protection is not active during Sleep. The device
wake-up will be delayed until the BOR is ready.
When the BOREN bits of Configuration Words are pro-
grammed to ‘11’, the BOR is always on. The device
6.2.3 BOR CONTROLLED BY SOFTWARE
start-up will be delayed until the BOR is ready and VDD
is higher than the BOR threshold. When the BOREN bits of Configuration Words are
programmed to ‘01’, the BOR is controlled by the
BOR protection is active during Sleep. The BOR does
SBOREN bit of the BORCON register. The device
not delay wake-up from Sleep.
start-up is not delayed by the BOR ready condition or
the VDD level.
6.2.2 BOR IS OFF IN SLEEP
BOR protection begins as soon as the BOR circuit is
When the BOREN bits of Configuration Words are pro-
ready. The status of the BOR circuit is reflected in the
grammed to ‘10’, the BOR is on, except in Sleep. The
BORRDY bit of the BORCON register.
device start-up will be delayed until the BOR is ready
and VDD is higher than the BOR threshold. BOR protection is unchanged by Sleep.

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FIGURE 6-2: BROWN-OUT SITUATIONS

VDD
VBOR

Internal
Reset TPWRT(1)

VDD
VBOR

Internal < TPWRT

Reset TPWRT(1)

VDD
VBOR

Internal
Reset TPWRT(1)

Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.

6.3 Register Definitions: BOR Control

REGISTER 6-1: BORCON: BROWN-OUT RESET CONTROL REGISTER
R/W-1/u R/W-0/u U-0 U-0 U-0 U-0 U-0 R-q/u
SBOREN BORFS — — — — — BORRDY
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 SBOREN: Software Brown-Out Reset Enable bit

If BOREN <1:0> in Configuration Words = 01:
1 = BOR Enabled
0 = BOR Disabled
If BOREN <1:0> in Configuration Words  01:
SBOREN is read/write, but has no effect on the BOR
bit 6 BORFS: Brown-Out Reset Fast Start bit(1)
If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control):
1 = Band gap is forced on always (covers sleep/wake-up/operating cases)
0 = Band gap operates normally, and may turn off
If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off)
BORFS is Read/Write, but has no effect.
bit 5-1 Unimplemented: Read as ‘0’
bit 0 BORRDY: Brown-Out Reset Circuit Ready Status bit
1 = The Brown-out Reset circuit is active
0 = The Brown-out Reset circuit is inactive

Note 1: BOREN<1:0> bits are located in Configuration Words.

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6.4 Low-Power Brown-Out Reset 6.6 Watchdog Timer (WDT) Reset
(LPBOR) The Watchdog Timer generates a Reset if the firmware
The Low-Power Brown-Out Reset (LPBOR) operates does not issue a CLRWDT instruction within the time-out
like the BOR to detect low voltage conditions on the period. The TO and PD bits in the STATUS register are
VDD pin. When too low of a voltage is detected, the changed to indicate the WDT Reset. See Section 9.0
device is held in Reset. When this occurs, a register bit “Watchdog Timer (WDT)” for more information.
(BOR) is changed to indicate that a BOR Reset has
occurred. The BOR bit in PCON is used for both BOR 6.7 RESET Instruction
and the LPBOR. Refer to Register 6-2.
A RESET instruction will cause a device Reset. The RI
The LPBOR voltage threshold (VLPBOR) has a wider bit in the PCON register will be set to ‘0’. See Table 6-4
tolerance than the BOR (VBOR), but requires much for default conditions after a RESET instruction has
less current (LPBOR current) to operate. The LPBOR occurred.
is intended for use when the BOR is configured as dis-
abled (BOREN = 00) or disabled in Sleep mode
6.8 Stack Overflow/Underflow Reset
(BOREN = 10).
Refer to Figure 6-1 to see how the LPBOR interacts The device can reset when the Stack Overflows or
with other modules. Underflows. The STKOVF or STKUNF bits of the PCON
register indicate the Reset condition. These Resets are
6.4.1 ENABLING LPBOR enabled by setting the STVREN bit in Configuration
Words. See Section 3.4.2 “Overflow/Underflow
The LPBOR is controlled by the LPBOR bit of
Reset” for more information.
Configuration Words. When the device is erased, the
LPBOR module defaults to disabled.
6.9 Programming Mode Exit
6.5 MCLR Upon exit of Programming mode, the device will
behave as if a POR had just occurred.
The MCLR is an optional external input that can reset
the device. The MCLR function is controlled by the
MCLRE bit of Configuration Words and the LVP bit of 6.10 Power-Up Timer
Configuration Words (Table 6-2). The Power-up Timer optionally delays device execution
after a BOR or POR event. This timer is typically used to
TABLE 6-2: MCLR CONFIGURATION allow VDD to stabilize before allowing the device to start
running.
MCLRE LVP MCLR
The Power-up Timer is controlled by the PWRTE bit of
0 0 Disabled Configuration Words.
1 0 Enabled
x 1 Enabled 6.11 Start-up Sequence
Upon the release of a POR or BOR, the following must
6.5.1 MCLR ENABLED occur before the device will begin executing:
When MCLR is enabled and the pin is held low, the 1. Power-up Timer runs to completion (if enabled).
device is held in Reset. The MCLR pin is connected to
2. MCLR must be released (if enabled).
VDD through an internal weak pull-up.
The total time-out will vary based on oscillator configu-
The device has a noise filter in the MCLR Reset path.
ration and Power-up Timer configuration. See
The filter will detect and ignore small pulses.
Section 5.0 “Oscillator Module (With Fail-Safe
Note: A Reset does not drive the MCLR pin low. Clock Monitor)” for more information.
The Power-up Timer runs independently of MCLR
6.5.2 MCLR DISABLED Reset. If MCLR is kept low long enough, the Power-up
When MCLR is disabled, the pin functions as a general Timer will expire. Upon bringing MCLR high, the device
purpose input and the internal weak pull-up is under will begin execution after 10 FOSC cycles (see
software control. See Section 11.3 “PORTA Regis- Figure 6-3). This is useful for testing purposes or to
ters” for more information. synchronize more than one device operating in parallel.

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FIGURE 6-3: RESET START-UP SEQUENCE
Rev. 10-000032A
7/30/2013

VDD
Internal POR
TPWRT
Power-up Timer
MCLR
Internal RESET
Int. Oscillator
FOSC
Begin Execution
code execution (1) code execution (1)
Internal Oscillator, PWRTEN = 0 Internal Oscillator, PWRTEN = 1

VDD
Internal POR
TPWRT
Power-up Timer
MCLR
Internal RESET
Ext. Clock (EC)
FOSC
Begin Execution
code execution (1) code execution (1)
External Clock (EC modes), PWRTEN = 0 External Clock (EC modes), PWRTEN = 1

VDD
Internal POR
TPWRT
Power-up Timer
MCLR
Internal RESET
TOST TOST
Osc Start-Up Timer
Ext. Oscillator
FOSC
Begin Execution
code code
execution (1) execution (1)

External Oscillators , PWRTEN = 0, IESO = 0 External Oscillators , PWRTEN = 1, IESO = 0

VDD
Internal POR
TPWRT
Power-up Timer
MCLR
Internal RESET
TOST TOST
Osc Start-Up Timer
Ext. Oscillator
Int. Oscillator
FOSC
Begin Execution code execution (1) code execution (1)

External Oscillators , PWRTEN = 0, IESO = 1 External Oscillators , PWRTEN = 1, IESO = 1

Note 1: Code execution begins 10 FOSC cycles after the FOSC clock is released.

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6.12 Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and
PCON registers are updated to indicate the cause of
the Reset. Table 6-3 and Table 6-4 show the Reset
conditions of these registers.

TABLE 6-3: RESET STATUS BITS AND THEIR SIGNIFICANCE

STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition
0 0 1 1 1 0 x 1 1 Power-on Reset
0 0 1 1 1 0 x 0 x Illegal, TO is set on POR
0 0 1 1 1 0 x x 0 Illegal, PD is set on POR
0 0 u 1 1 u 0 1 1 Brown-out Reset
u u 0 u u u u 0 u WDT Reset
u u u u u u u 0 0 WDT Wake-up from Sleep
u u u u u u u 1 0 Interrupt Wake-up from Sleep
u u u 0 u u u u u MCLR Reset during normal operation
u u u 0 u u u 1 0 MCLR Reset during Sleep
u u u u 0 u u u u RESET Instruction Executed
1 u u u u u u u u Stack Overflow Reset (STVREN = 1)
u 1 u u u u u u u Stack Underflow Reset (STVREN = 1)

TABLE 6-4: RESET CONDITION FOR SPECIAL REGISTERS

Program STATUS PCON
Condition
Counter Register Register
Power-on Reset 0000h ---1 1000 00-- 110x
MCLR Reset during normal operation 0000h ---u uuuu uu-- 0uuu
MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu
WDT Reset 0000h ---0 uuuu uu-- uuuu
WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-- uuuu
Brown-out Reset 0000h ---1 1uuu 00-- 11u0
(1)
Interrupt Wake-up from Sleep PC + 1 ---1 0uuu uu-- uuuu
RESET Instruction Executed 0000h ---u uuuu uu-- u0uu
Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-- uuuu
Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-- uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and the Global Interrupt Enable bit (GIE) is set, the return address
is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

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6.13 Power Control (PCON) Register
The Power Control (PCON) register contains flag bits
to differentiate between a:
• Power-On Reset (POR)
• Brown-Out Reset (BOR)
• Reset Instruction Reset (RI)
• MCLR Reset (RMCLR)
• Watchdog Timer Reset (RWDT)
• Stack Underflow Reset (STKUNF)
• Stack Overflow Reset (STKOVF)
The PCON register bits are shown in Register 6-2.

6.14 Register Definitions: Power Control

REGISTER 6-2: PCON: POWER CONTROL REGISTER

R/W/HS-0/q R/W/HS-0/q U-0 R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u
STKOVF STKUNF — RWDT RMCLR RI POR BOR
bit 7 bit 0

Legend:
HC = Bit is cleared by hardware HS = Bit is set by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 STKOVF: Stack Overflow Flag bit

1 = A Stack Overflow occurred
0 = A Stack Overflow has not occurred or cleared by firmware
bit 6 STKUNF: Stack Underflow Flag bit
1 = A Stack Underflow occurred
0 = A Stack Underflow has not occurred or cleared by firmware
bit 5 Unimplemented: Read as ‘0’
bit 4 RWDT: Watchdog Timer Reset Flag bit
1 = A Watchdog Timer Reset has not occurred or set by firmware
0 = A Watchdog Timer Reset has occurred (cleared by hardware)
bit 3 RMCLR: MCLR Reset Flag bit
1 = A MCLR Reset has not occurred or set by firmware
0 = A MCLR Reset has occurred (cleared by hardware)
bit 2 RI: RESET Instruction Flag bit
1 = A RESET instruction has not been executed or set by firmware
0 = A RESET instruction has been executed (cleared by hardware)
bit 1 POR: Power-On Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-Out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset
occurs)

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TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
BORCON SBOREN BORFS — — — — — BORRDY 65
PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 69
STATUS — — — TO PD Z DC C 19
WDTCON — — WDTPS<4:0> SWDTEN 91
Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

TABLE 6-6: SUMMARY OF CONFIGURATION WORD WITH RESETS

Register
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0
on Page
13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> —
CONFIG1 42
7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>
13:8 — — LVP DEBUG LPBOR BORV STVREN —
CONFIG2 44
7:0 — — — — — — WRT<1:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.

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7.0 INTERRUPTS
The interrupt feature allows certain events to preempt
normal program flow. Firmware is used to determine
the source of the interrupt and act accordingly. Some
interrupts can be configured to wake the MCU from
Sleep mode.
This chapter contains the following information for
Interrupts:
• Operation
• Interrupt Latency
• Interrupts During Sleep
• INT Pin
• Automatic Context Saving
Many peripherals produce interrupts. Refer to the
corresponding chapters for details.
A block diagram of the interrupt logic is shown in
Figure 7-1.

FIGURE 7-1: INTERRUPT LOGIC

Rev. 10-000010A
7/30/2013

TMR0IF Wake-up
TMR0IE (If in Sleep mode)

INTF
Peripheral Interrupts INTE
(TMR1IF) PIR1<0>
IOCIF
(TMR1IE) PIE1<0> Interrupt
IOCIE to CPU

PEIE

PIRn<7>
GIE
PIEn<7>

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7.1 Operation 7.2 Interrupt Latency
Interrupts are disabled upon any device Reset. They Interrupt latency is defined as the time from when the
are enabled by setting the following bits: interrupt event occurs to the time code execution at the
• GIE bit of the INTCON register interrupt vector begins. The latency for synchronous
interrupts is three or four instruction cycles. For
• Interrupt Enable bit(s) for the specific interrupt
asynchronous interrupts, the latency is three to five
event(s)
instruction cycles, depending on when the interrupt
• PEIE bit of the INTCON register (if the Interrupt occurs. See Figure 7-2 and Figure 7-3 for more details.
Enable bit of the interrupt event is contained in the
PIE1, PIE2 and PIE3 registers)
The INTCON, PIR1, PIR2 and PIR3 registers record
individual interrupts via interrupt flag bits. Interrupt flag
bits will be set, regardless of the status of the GIE, PEIE
and individual interrupt enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
• Current prefetched instruction is flushed
• GIE bit is cleared
• Current Program Counter (PC) is pushed onto the
stack
• Critical registers are automatically saved to the
shadow registers (See “Section 7.5 “Automatic
Context Saving”.”)
• PC is loaded with the interrupt vector 0004h
The firmware within the Interrupt Service Routine (ISR)
should determine the source of the interrupt by polling
the interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack, restoring the saved
context from the shadow registers and setting the GIE
bit.
For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.
Note 1: Individual interrupt flag bits are set,
regardless of the state of any other
enable bits.
2: All interrupts will be ignored while the GIE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.

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FIGURE 7-2: INTERRUPT LATENCY

Fosc

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CLKR Interrupt Sampled

during Q1

Interrupt

GIE

PC PC-1 PC PC+1 0004h 0005h

Execute 1-Cycle Instruction at PC Inst(PC) NOP NOP Inst(0004h)

Interrupt

GIE

PC+1/FSR New PC/

PC PC-1 PC 0004h 0005h
ADDR PC+1

Execute 2-Cycle Instruction at PC Inst(PC) NOP NOP Inst(0004h)

Interrupt

GIE

PC PC-1 PC FSR ADDR PC+1 PC+2 0004h 0005h

Execute 3-Cycle Instruction at PC INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h)

Interrupt

GIE

PC PC-1 PC FSR ADDR PC+1 PC+2 0004h 0005h

Execute 3-Cycle Instruction at PC INST(PC) NOP NOP NOP NOP Inst(0004h)

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FIGURE 7-3: INT PIN INTERRUPT TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

FOSC

CLKOUT
(3)

INT pin
(1)
(1)
INTF (4) Interrupt Latency (2)

GIE

INSTRUCTION FLOW
PC PC PC + 1 PC + 1 0004h 0005h

Instruction
Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h)

Instruction Forced NOP Forced NOP Inst (0004h)

Inst (PC – 1) Inst (PC)
Executed

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: For minimum width of INT pulse, refer to AC specifications in Section 29.0 “Electrical Specifications”.
4: INTF is enabled to be set any time during the Q4-Q1 cycles.

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 PIC16(L)F1508/9
7.3 Interrupts During Sleep
Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate Interrupt Enable bit(s) set
prior to entering Sleep.
On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEP instruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to Section 8.0 “Power-
Down Mode (Sleep)” for more details.

7.4 INT Pin

The INT pin can be used to generate an asynchronous
edge-triggered interrupt. This interrupt is enabled by
setting the INTE bit of the INTCON register. The
INTEDG bit of the OPTION_REG register determines on
which edge the interrupt will occur. When the INTEDG
bit is set, the rising edge will cause the interrupt. When
the INTEDG bit is clear, the falling edge will cause the
interrupt. The INTF bit of the INTCON register will be set
when a valid edge appears on the INT pin. If the GIE and
INTE bits are also set, the processor will redirect
program execution to the interrupt vector.

7.5 Automatic Context Saving

Upon entering an interrupt, the return PC address is
saved on the stack. Additionally, the following registers
are automatically saved in the shadow registers:
• W register
• STATUS register (except for TO and PD)
• BSR register
• FSR registers
• PCLATH register
Upon exiting the Interrupt Service Routine, these regis-
ters are automatically restored. Any modifications to
these registers during the ISR will be lost. If modifica-
tions to any of these registers are desired, the corre-
sponding shadow register should be modified and the
value will be restored when exiting the ISR. The
shadow registers are available in Bank 31 and are
readable and writable. Depending on the user’s appli-
cation, other registers may also need to be saved.

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PIC16(L)F1508/9
7.6 Register Definitions: Interrupt Control

REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0
GIE(1) PEIE(2) TMR0IE INTE IOCIE TMR0IF INTF IOCIF(3)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 GIE: Global Interrupt Enable bit(1)

1 = Enables all active interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit(2)
1 = Enables all active peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4 INTE: INT External Interrupt Enable bit
1 = Enables the INT external interrupt
0 = Disables the INT external interrupt
bit 3 IOCIE: Interrupt-on-Change Enable bit
1 = Enables the interrupt-on-change
0 = Disables the interrupt-on-change
bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed
0 = TMR0 register did not overflow
bit 1 INTF: INT External Interrupt Flag bit
1 = The INT external interrupt occurred
0 = The INT external interrupt did not occur
bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit(3)
1 = When at least one of the interrupt-on-change pins changed state
0 = None of the interrupt-on-change pins have changed state

Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the Global Interrupt Enable bit, GIE of the INTCON register. User software should ensure the
appropriate interrupt flag bits are clear prior to enabling an interrupt.
2: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
3: The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCxF registers
have been cleared by software.

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REGISTER 7-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0
TMR1GIE ADIE RCIE TXIE SSP1IE — TMR2IE TMR1IE
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit

1 = Enables the Timer1 gate acquisition interrupt
0 = Disables the Timer1 gate acquisition interrupt
bit 6 ADIE: Analog-to-Digital Converter (ADC) Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 5 RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4 TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3 SSP1IE: Synchronous Serial Port (MSSP) Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 2 Unimplemented: Read as ‘0’
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt
bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit
1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

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REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 U-0
OSFIE C2IE C1IE — BCL1IE NCO1IE — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enables the Oscillator Fail interrupt
0 = Disables the Oscillator Fail interrupt
bit 6 C2IE: Comparator C2 Interrupt Enable bit
1 = Enables the Comparator C2 interrupt
0 = Disables the Comparator C2 interrupt
bit 5 C1IE: Comparator C1 Interrupt Enable bit
1 = Enables the Comparator C1 interrupt
0 = Disables the Comparator C1 interrupt
bit 4 Unimplemented: Read as ‘0’
bit 3 BCL1IE: MSSP Bus Collision Interrupt Enable bit
1 = Enables the MSSP Bus Collision Interrupt
0 = Disables the MSSP Bus Collision Interrupt
bit 2 NCO1IE: Numerically Controlled Oscillator Interrupt Enable bit
1 = Enables the NCO interrupt
0 = Disables the NCO interrupt
bit 1-0 Unimplemented: Read as ‘0’

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

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REGISTER 7-4: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3

U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — CLC4IE CLC3IE CLC2IE CLC1IE
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 Unimplemented: Read as ‘0’

bit 3 CLC4IE: Configurable Logic Block 4 Interrupt Enable bit
1 = Enables the CLC 4 interrupt
0 = Disables the CLC 4 interrupt
bit 2 CLC3IE: Configurable Logic Block 3 Interrupt Enable bit
1 = Enables the CLC 3 interrupt
0 = Disables the CLC 3 interrupt
bit 1 CLC2IE: Configurable Logic Block 2 Interrupt Enable bit
1 = Enables the CLC 2 interrupt
0 = Disables the CLC 2 interrupt
bit 0 CLC1IE: Configurable Logic Block 1 Interrupt Enable bit
1 = Enables the CLC 1 interrupt
0 = Disables the CLC 1 interrupt

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

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REGISTER 7-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0
TMR1GIF ADIF RCIF TXIF SSP1IF — TMR2IF TMR1IF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending
bit 6 ADIF: ADC Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 5 RCIF: USART Receive Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 4 TXIF: USART Transmit Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 3 SSP1IF: Synchronous Serial Port (MSSP) Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 2 Unimplemented: Read as ‘0’
bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE of the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.

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REGISTER 7-6: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 U-0
OSFIF C2IF C1IF — BCL1IF NCO1IF — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 OSFIF: Oscillator Fail Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending
bit 6 C2IF: Numerically Controlled Oscillator Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 5 C1IF: Numerically Controlled Oscillator Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 4 Unimplemented: Read as ‘0’
bit 3 BCL1IF: MSSP Bus Collision Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 2 NCO1IF: Numerically Controlled Oscillator Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 1-0 Unimplemented: Read as ‘0’

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE of the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.

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REGISTER 7-7: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3

U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — CLC4IF CLC3IF CLC2IF CLC1IF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 Unimplemented: Read as ‘0’

bit 3 CLC4IF: Configurable Logic Block 4 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 2 CLC3IF: Configurable Logic Block 3 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 1 CLC2IF: Configurable Logic Block 2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 0 CLC1IF: Configurable Logic Block 1 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.

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 PIC16(L)F1508/9
TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 163
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE — TMR2IE TMR1IE 77
PIE2 OSFIE C2IE C1IE — BCL1IE NCO1IE — — 78
PIE3 — — — — CLC4IE CLC3IE CLC2IE CLC1IE 79
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF — TMR2IF TMR1IF 80
PIR2 OSFIF C2IF C1IF — BCL1IF NCO1IF — — 81
PIR3 — — — — CLC4IF CLC3IF CLC2IF CLC1IF 82
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupts.

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8.0 POWER-DOWN MODE (SLEEP) 6. Interrupts by peripherals capable of running
during Sleep (see individual peripheral for more
The Power-down mode is entered by executing a information)
SLEEP instruction.
The first three events will cause a device Reset. The
Upon entering Sleep mode, the following conditions exist: last three events are considered a continuation of pro-
1. WDT will be cleared but keeps running, if gram execution. To determine whether a device Reset
enabled for operation during Sleep. or wake-up event occurred, refer to Section 6.12
2. PD bit of the STATUS register is cleared. “Determining the Cause of a Reset”.
3. TO bit of the STATUS register is set. When the SLEEP instruction is being executed, the next
4. CPU clock is disabled. instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
5. 31 kHz LFINTOSC is unaffected and peripherals
interrupt enable bit must be enabled. Wake-up will
that operate from it may continue operation in
occur regardless of the state of the GIE bit. If the GIE
Sleep.
bit is disabled, the device continues execution at the
6. Timer1 and peripherals that operate from instruction after the SLEEP instruction. If the GIE bit is
Timer1 continue operation in Sleep when the enabled, the device executes the instruction after the
Timer1 clock source selected is: SLEEP instruction, the device will then call the Interrupt
• LFINTOSC Service Routine. In cases where the execution of the
• T1CKI instruction following SLEEP is not desirable, the user
• Timer1 oscillator should have a NOP after the SLEEP instruction.
7. ADC is unaffected, if the dedicated FRC oscillator The WDT is cleared when the device wakes up from
is selected. Sleep, regardless of the source of wake-up.
8. I/O ports maintain the status they had before
SLEEP was executed (driving high, low or high- 8.1.1 WAKE-UP USING INTERRUPTS
impedance). When global interrupts are disabled (GIE cleared) and
9. Resets other than WDT are not affected by any interrupt source has both its interrupt enable bit
Sleep mode. and interrupt flag bit set, one of the following will occur:
Refer to individual chapters for more details on • If the interrupt occurs before the execution of a
peripheral operation during Sleep. SLEEP instruction
To minimize current consumption, the following - SLEEP instruction will execute as a NOP.
conditions should be considered: - WDT and WDT prescaler will not be cleared
• I/O pins should not be floating - TO bit of the STATUS register will not be set
• External circuitry sinking current from I/O pins - PD bit of the STATUS register will not be
cleared.
• Internal circuitry sourcing current from I/O pins
• If the interrupt occurs during or after the execu-
• Current draw from pins with internal weak pull-ups
tion of a SLEEP instruction
• Modules using 31 kHz LFINTOSC
- SLEEP instruction will be completely
• CWG, NCO and CLC modules using HFINTOSC executed
I/O pins that are high-impedance inputs should be - Device will immediately wake-up from Sleep
pulled to VDD or VSS externally to avoid switching - WDT and WDT prescaler will be cleared
currents caused by floating inputs.
- TO bit of the STATUS register will be set
Examples of internal circuitry that might be sourcing - PD bit of the STATUS register will be cleared
current include the FVR module. See Section 13.0
“Fixed Voltage Reference (FVR)” for more Even if the flag bits were checked before executing a
information on this module. SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes.
To determine whether a SLEEP instruction executed,
8.1 Wake-up from Sleep test the PD bit. If the PD bit is set, the SLEEP instruction
The device can wake-up from Sleep through one of the was executed as a NOP.
following events:
1. External Reset input on MCLR pin, if enabled
2. BOR Reset, if enabled
3. POR Reset
4. Watchdog Timer, if enabled
5. Any external interrupt

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PIC16(L)F1508/9
FIGURE 8-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKIN(1)
CLKOUT(2) T1OSC(3)

Interrupt flag Interrupt Latency (4)

GIE bit
(INTCON reg.) Processor in
Sleep

Instruction Flow
PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h
Instruction Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h)
Fetched Inst(PC) = Sleep
Instruction Sleep Inst(PC + 1) Forced NOP Forced NOP
Executed Inst(PC - 1) Inst(0004h)

Note 1: External clock. High, Medium, Low mode assumed.

2: CLKOUT is shown here for timing reference.
3: T1OSC; See Section 29.0 “Electrical Specifications”.
4: GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.

8.2 Low-Power Sleep Mode 8.2.2 PERIPHERAL USAGE IN SLEEP

This device contains an internal Low Dropout (LDO) Some peripherals that can operate in Sleep mode will
voltage regulator, which allows the device I/O pins to not operate properly with the Low-Power Sleep mode
operate at voltages up to 5.5V while the internal device selected. The LDO will remain in the Normal-Power
logic operates at a lower voltage. The LDO and its mode when those peripherals are enabled. The Low-
associated reference circuitry must remain active when Power Sleep mode is intended for use with these
the device is in Sleep mode. peripherals:

Low-Power Sleep mode allows the user to optimize the • Brown-Out Reset (BOR)
operating current in Sleep. Low-Power Sleep mode can • Watchdog Timer (WDT)
be selected by setting the VREGPM bit of the • External interrupt pin/Interrupt-on-change pins
VREGCON register, putting the LDO and reference • Timer1 (with external clock source)
circuitry in a low-power state whenever the device is in
Sleep. The Complementary Waveform Generator (CWG), the
Numerically Controlled Oscillator (NCO) and the Con-
8.2.1 SLEEP CURRENT VS. WAKE-UP figurable Logic Cell (CLC) modules can utilize the
TIME HFINTOSC oscillator as either a clock source or as an
input source. Under certain conditions, when the
In the Default Operating mode, the LDO and reference HFINTOSC is selected for use with the CWG, NCO or
circuitry remain in the normal configuration while in CLC modules, the HFINTOSC will remain active
Sleep. The device is able to exit Sleep mode quickly during Sleep. This will have a direct effect on the
since all circuits remain active. In Low-Power Sleep Sleep mode current.
mode, when waking up from Sleep, an extra delay time
is required for these circuits to return to the normal con- Please refer to sections Section 24.5 “Operation
figuration and stabilize. During Sleep”, Section 25.7 “Operation In Sleep”
and Section 26.10 “Operation During Sleep” for
The Low-Power Sleep mode is beneficial for applica- more information.
tions that stay in Sleep mode for long periods of time.
The Normal mode is beneficial for applications that
need to wake from Sleep quickly and frequently. Note: The PIC16LF1508/9 does not have a con-
figurable Low-Power Sleep mode.
PIC16LF1508/9 is an unregulated device
and is always in the lowest power state
when in Sleep, with no wake-up time pen-
alty. This device has a lower maximum
VDD and I/O voltage than the
PIC16F1508/9. See Section 29.0 “Elec-
trical Specifications” for more informa-
tion.

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 PIC16(L)F1508/9
8.3 Register Definitions: Voltage Regulator Control

REGISTER 8-1: VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1)

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1
— — — — — — VREGPM Reserved
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-2 Unimplemented: Read as ‘0’

bit 1 VREGPM: Voltage Regulator Power Mode Selection bit
1 = Low-Power Sleep mode enabled in Sleep(2)
Draws lowest current in Sleep, slower wake-up
0 = Normal Power mode enabled in Sleep(2)
Draws higher current in Sleep, faster wake-up
bit 0 Reserved: Read as ‘1’. Maintain this bit set.

Note 1: PIC16F1508/9 only.

2: See Section 29.0 “Electrical Specifications”.

TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE

Register on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Page
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76
IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 125
IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 125
IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 125
IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 — — — — 126
IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 — — — — 126
IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 — — — — 126
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE — TMR2IE TMR1IE 77
PIE2 OSFIE C2IE C1IE — BCL1IE NCO1IE — — 78
PIE3 — — — — CLC4IE CLC3IE CLC2IE CLC1IE 79
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF — TMR2IF TMR1IF 80
PIR2 OSFIF C2IF C1IF — BCL1IF NCO1IF — — 81
PIR3 — — — — CLC4IF CLC3IF CLC2IF CLC1IF 82
STATUS — — — TO PD Z DC C 19
WDTCON — — WDTPS<4:0> SWDTEN 91
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-Down mode.

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 PIC16(L)F1508/9
9.0 WATCHDOG TIMER (WDT)
The Watchdog Timer is a system timer that generates
a Reset if the firmware does not issue a CLRWDT
instruction within the time-out period. The Watchdog
Timer is typically used to recover the system from
unexpected events.
The WDT has the following features:
• Independent clock source
• Multiple operating modes
- WDT is always on
- WDT is off when in Sleep
- WDT is controlled by software
- WDT is always off
• Configurable time-out period is from 1 ms to 256
seconds (nominal)
• Multiple Reset conditions
• Operation during Sleep

FIGURE 9-1: WATCHDOG TIMER BLOCK DIAGRAM

Rev. 10-000141A
7/30/2013

WDTE<1:0> = 01
SWDTEN

23-bit Programmable WDT

WDTE<1:0> = 11 LFINTOSC Prescaler WDT Time-out

WDTE<1:0> = 10
Sleep WDTPS<4:0>

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9.1 Independent Clock Source 9.3 Time-Out Period
The WDT derives its time base from the 31 kHz The WDTPS bits of the WDTCON register set the
LFINTOSC internal oscillator. Time intervals in this time-out period from 1 ms to 256 seconds (nominal).
chapter are based on a nominal interval of 1 ms. See After a Reset, the default time-out period is two
Section 29.0 “Electrical Specifications” for the seconds.
LFINTOSC tolerances.
9.4 Clearing the WDT
9.2 WDT Operating Modes
The WDT is cleared when any of the following condi-
The Watchdog Timer module has four operating modes tions occur:
controlled by the WDTE<1:0> bits in Configuration • Any Reset
Words. See Table 9-1.
• CLRWDT instruction is executed
9.2.1 WDT IS ALWAYS ON • Device enters Sleep
When the WDTE bits of Configuration Words are set to • Device wakes up from Sleep
‘11’, the WDT is always on. • Oscillator fail
WDT protection is active during Sleep. • WDT is disabled
• Oscillator Start-up Timer (OST) is running
9.2.2 WDT IS OFF IN SLEEP See Table 9-2 for more information.
When the WDTE bits of Configuration Words are set to
‘10’, the WDT is on, except in Sleep. 9.5 Operation During Sleep
WDT protection is not active during Sleep. When the device enters Sleep, the WDT is cleared. If
the WDT is enabled during Sleep, the WDT resumes
9.2.3 WDT CONTROLLED BY SOFTWARE
counting. When the device exits Sleep, the WDT is
When the WDTE bits of Configuration Words are set to cleared again.
‘01’, the WDT is controlled by the SWDTEN bit of the
The WDT remains clear until the OST, if enabled, com-
WDTCON register.
pletes. See Section 5.0 “Oscillator Module (With
WDT protection is unchanged by Sleep. See Table 9-1 Fail-Safe Clock Monitor)” for more information on the
for more details. OST.

TABLE 9-1: WDT OPERATING MODES When a WDT time-out occurs while the device is in
Sleep, no Reset is generated. Instead, the device
Device WDT wakes up and resumes operation. The TO and PD bits
WDTE<1:0> SWDTEN
Mode Mode in the STATUS register are changed to indicate the
event. The RWDT bit in the PCON register can also be
11 X X Active used. See Section 3.0 “Memory Organization” for
Awake Active more information.
10 X
Sleep Disabled
1 X Active
01
0 X Disabled
00 X X Disabled

TABLE 9-2: WDT CLEARING CONDITIONS

Conditions WDT
WDTE<1:0> = 00
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
Cleared
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST
Change INTOSC divider (IRCF bits) Unaffected

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 PIC16(L)F1508/9
9.6 Register Definitions: Watchdog Control

REGISTER 9-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER

U-0 U-0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0
— — WDTPS<4:0> SWDTEN
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits(1)
Bit Value = Prescale Rate
11111 = Reserved. Results in minimum interval (1:32)
•
•
•
10011 = Reserved. Results in minimum interval (1:32)

10010 = 1:8388608 (223) (Interval 256s nominal)

10001 = 1:4194304 (222) (Interval 128s nominal)
10000 = 1:2097152 (221) (Interval 64s nominal)
01111 = 1:1048576 (220) (Interval 32s nominal)
01110 = 1:524288 (219) (Interval 16s nominal)
01101 = 1:262144 (218) (Interval 8s nominal)
01100 = 1:131072 (217) (Interval 4s nominal)
01011 = 1:65536 (Interval 2s nominal) (Reset value)
01010 = 1:32768 (Interval 1s nominal)
01001 = 1:16384 (Interval 512 ms nominal)
01000 = 1:8192 (Interval 256 ms nominal)
00111 = 1:4096 (Interval 128 ms nominal)
00110 = 1:2048 (Interval 64 ms nominal)
00101 = 1:1024 (Interval 32 ms nominal)
00100 = 1:512 (Interval 16 ms nominal)
00011 = 1:256 (Interval 8 ms nominal)
00010 = 1:128 (Interval 4 ms nominal)
00001 = 1:64 (Interval 2 ms nominal)
00000 = 1:32 (Interval 1 ms nominal)
bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit
If WDTE<1:0> = 1x:
This bit is ignored.
If WDTE<1:0> = 01:
1 = WDT is turned on
0 = WDT is turned off
If WDTE<1:0> = 00:
This bit is ignored.

Note 1: Times are approximate. WDT time is based on 31 kHz LFINTOSC.

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PIC16(L)F1508/9
TABLE 9-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
OSCCON — IRCF<3:0> — SCS<1:0> 60
PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 69
STATUS — — — TO PD Z DC C 19
WDTCON — — WDTPS<4:0> SWDTEN 91
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer.

TABLE 9-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER

Register
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0
on Page

13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> —

CONFIG1 42
7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.

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 PIC16(L)F1508/9
10.0 FLASH PROGRAM MEMORY 10.1.1 PMCON1 AND PMCON2
CONTROL REGISTERS
PMCON1 is the control register for Flash program
The Flash program memory is readable and writable
memory accesses.
during normal operation over the full VDD range.
Program memory is indirectly addressed using Special Control bits RD and WR initiate read and write,
Function Registers (SFRs). The SFRs used to access respectively. These bits cannot be cleared, only set, in
program memory are: software. They are cleared by hardware at completion
of the read or write operation. The inability to clear the
• PMCON1
WR bit in software prevents the accidental, premature
• PMCON2 termination of a write operation.
• PMDATL
The WREN bit, when set, will allow a write operation to
• PMDATH occur. On power-up, the WREN bit is clear. The
• PMADRL WRERR bit is set when a write operation is interrupted
• PMADRH by a Reset during normal operation. In these situations,
following Reset, the user can check the WRERR bit
When accessing the program memory, the
and execute the appropriate error handling routine.
PMDATH:PMDATL register pair forms a 2-byte word
that holds the 14-bit data for read/write, and the The PMCON2 register is a write-only register. Attempting
PMADRH:PMADRL register pair forms a 2-byte word to read the PMCON2 register will return all ‘0’s.
that holds the 15-bit address of the program memory To enable writes to the program memory, a specific
location being read. pattern (the unlock sequence), must be written to the
The write time is controlled by an on-chip timer. The PMCON2 register. The required unlock sequence
write/erase voltages are generated by an on-chip charge prevents inadvertent writes to the program memory
pump rated to operate over the operating voltage range write latches and Flash program memory.
of the device.
The Flash program memory can be protected in two 10.2 Flash Program Memory Overview
ways; by code protection (CP bit in Configuration Words) It is important to understand the Flash program memory
and write protection (WRT<1:0> bits in Configuration structure for erase and programming operations. Flash
Words). program memory is arranged in rows. A row consists of
Code protection (CP = 0)(1), disables access, reading a fixed number of 14-bit program memory words. A row
and writing, to the Flash program memory via external is the minimum size that can be erased by user software.
device programmers. Code protection does not affect After a row has been erased, the user can reprogram
the self-write and erase functionality. Code protection all or a portion of this row. Data to be written into the
can only be reset by a device programmer performing program memory row is written to 14-bit wide data write
a Bulk Erase to the device, clearing all Flash program latches. These write latches are not directly accessible
memory, Configuration bits and User IDs. to the user, but may be loaded via sequential writes to
Write protection prohibits self-write and erase to a the PMDATH:PMDATL register pair.
portion or all of the Flash program memory, as defined
Note: If the user wants to modify only a portion
by the bits WRT<1:0>. Write protection does not affect
of a previously programmed row, then the
a device programmers ability to read, write or erase the
contents of the entire row must be read
device.
and saved in RAM prior to the erase.
Note 1: Code protection of the entire Flash Then, new data and retained data can be
program memory array is enabled by written into the write latches to reprogram
clearing the CP bit of Configuration Words. the row of Flash program memory. How-
ever, any unprogrammed locations can be
10.1 PMADRL and PMADRH Registers written without first erasing the row. In this
case, it is not necessary to save and
The PMADRH:PMADRL register pair can address up rewrite the other previously programmed
to a maximum of 32K words of program memory. When locations.
selecting a program address value, the MSB of the
See Table 10-1 for Erase Row size and the number of
address is written to the PMADRH register and the LSB
write latches for Flash program memory.
is written to the PMADRL register.

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PIC16(L)F1508/9
FIGURE 10-1: FLASH PROGRAM
TABLE 10-1: FLASH MEMORY MEMORY READ
ORGANIZATION BY DEVICE FLOWCHART
Write
Row Erase
Rev. 10-000046A
7/30/2013

Device Latches
(words)
(words)
Start
PIC16(L)F1509 Read Operation
32 32
PIC16(L)F1508

Select
10.2.1 READING THE FLASH PROGRAM Program or Configuration Memory
MEMORY (CFGS)

To read a program memory location, the user must:

1. Write the desired address to the Select
PMADRH:PMADRL register pair. Word Address
(PMADRH:PMADRL)
2. Clear the CFGS bit of the PMCON1 register.
3. Then, set control bit RD of the PMCON1 register.
Once the read control bit is set, the program memory Initiate Read operation
Flash controller will use the second instruction cycle to (RD = 1)
read the data. This causes the second instruction
immediately following the “BSF PMCON1,RD” instruction
to be ignored. The data is available in the very next cycle,
in the PMDATH:PMDATL register pair; therefore, it can Instruction fetched ignored
NOP execution forced
be read as two bytes in the following instructions.
PMDATH:PMDATL register pair will hold this value until
another read or until it is written to by the user.
Instruction fetched ignored
Note: The two instructions following a program NOP execution forced
memory read are required to be NOPs.
This prevents the user from executing a
2-cycle instruction on the next instruction
after the RD bit is set. Data read now in
PMDATH:PMDATL

End
Read Operation

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 PIC16(L)F1508/9
FIGURE 10-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Flash ADDR PC PC + 1 PMADRH,PMADRL PC +3

PC+3 PC + 4 PC + 5

Flash Data INSTR (PC) INSTR (PC + 1) PMDATH,PMDATL INSTR (PC + 3) INSTR (PC + 4)

INSTR(PC + 1) INSTR(PC + 2)
INSTR(PC - 1) BSF PMCON1,RD instruction ignored instruction ignored INSTR(PC + 3) INSTR(PC + 4)
executed here executed here Forced NOP Forced NOP executed here executed here
executed here executed here

RD bit

PMDATH
PMDATL
Register

EXAMPLE 10-1: FLASH PROGRAM MEMORY READ

* This code block will read 1 word of program

* memory at the memory address:
PROG_ADDR_HI : PROG_ADDR_LO
* data will be returned in the variables;
* PROG_DATA_HI, PROG_DATA_LO

BANKSEL PMADRL ; Select Bank for PMCON registers

MOVLW PROG_ADDR_LO ;
MOVWF PMADRL ; Store LSB of address
MOVLW PROG_ADDR_HI ;
MOVWF PMADRH ; Store MSB of address

BCF PMCON1,CFGS ; Do not select Configuration Space

BSF PMCON1,RD ; Initiate read
NOP ; Ignored (Figure 10-2)
NOP ; Ignored (Figure 10-2)

MOVF PMDATL,W ; Get LSB of word

MOVWF PROG_DATA_LO ; Store in user location
MOVF PMDATH,W ; Get MSB of word
MOVWF PROG_DATA_HI ; Store in user location

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PIC16(L)F1508/9
10.2.2 FLASH MEMORY UNLOCK FIGURE 10-3: FLASH PROGRAM
SEQUENCE MEMORY UNLOCK
The unlock sequence is a mechanism that protects the SEQUENCE FLOWCHART
Flash program memory from unintended self-write pro- Rev. 10-000047A
7/30/2013

gramming or erasing. The sequence must be executed

and completed without interruption to successfully
complete any of the following operations:
Start
• Row Erase Unlock Sequence

• Load program memory write latches

• Write of program memory write latches to
program memory Write 0x55 to
• Write of program memory write latches to User PMCON2
IDs
The unlock sequence consists of the following steps:
1. Write 55h to PMCON2 Write 0xAA to
PMCON2
2. Write AAh to PMCON2
3. Set the WR bit in PMCON1
4. NOP instruction Initiate
Write or Erase operation
5. NOP instruction (WR = 1)
Once the WR bit is set, the processor will always force
two NOP instructions. When an Erase Row or Program
Row operation is being performed, the processor will stall Instruction fetched ignored
internal operations (typical 2 ms), until the operation is NOP execution forced
complete and then resume with the next instruction.
When the operation is loading the program memory write
latches, the processor will always force the two NOP
instructions and continue uninterrupted with the next Instruction fetched ignored
NOP execution forced
instruction.
Since the unlock sequence must not be interrupted,
global interrupts should be disabled prior to the unlock
sequence and re-enabled after the unlock sequence is End
completed. Unlock Sequence

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 PIC16(L)F1508/9
10.2.3 ERASING FLASH PROGRAM FIGURE 10-4: FLASH PROGRAM
MEMORY MEMORY ERASE
While executing code, program memory can only be FLOWCHART
erased by rows. To erase a row: Rev. 10-000048A
7/30/2013

1. Load the PMADRH:PMADRL register pair with

any address within the row to be erased.
Start
2. Clear the CFGS bit of the PMCON1 register. Erase Operation
3. Set the FREE and WREN bits of the PMCON1
register.
4. Write 55h, then AAh, to PMCON2 (Flash
programming unlock sequence). Disable Interrupts
(GIE = 0)
5. Set control bit WR of the PMCON1 register to
begin the erase operation.
See Example 10-2. Select
After the “BSF PMCON1,WR” instruction, the processor Program or Configuration Memory
(CFGS)
requires two cycles to set up the erase operation. The
user must place two NOP instructions immediately fol-
lowing the WR bit set instruction. The processor will
halt internal operations for the typical 2 ms erase time. Select Row Address
This is not Sleep mode as the clocks and peripherals (PMADRH:PMADRL)
will continue to run. After the erase cycle, the processor
will resume operation with the third instruction after the
PMCON1 write instruction.
Select Erase Operation
(FREE = 1)

Enable Write/Erase Operation

(WREN = 1)

Unlock Sequence
(See Note 1)

CPU stalls while

Erase operation completes
(2 ms typical)

Disable Write/Erase Operation

(WREN = 0)

Re-enable Interrupts
(GIE = 1)

End
Erase Operation

Note 1: See Figure 10-3.

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PIC16(L)F1508/9
EXAMPLE 10-2: ERASING ONE ROW OF PROGRAM MEMORY
; This row erase routine assumes the following:
; 1. A valid address within the erase row is loaded in ADDRH:ADDRL
; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)

BCF INTCON,GIE ; Disable ints so required sequences will execute properly

BANKSEL PMADRL
MOVF ADDRL,W ; Load lower 8 bits of erase address boundary
MOVWF PMADRL
MOVF ADDRH,W ; Load upper 6 bits of erase address boundary
MOVWF PMADRH
BCF PMCON1,CFGS ; Not configuration space
BSF PMCON1,FREE ; Specify an erase operation
BSF PMCON1,WREN ; Enable writes

MOVLW 55h ; Start of required sequence to initiate erase

MOVWF PMCON2 ; Write 55h
Sequence
Required

MOVLW 0AAh ;
MOVWF PMCON2 ; Write AAh
BSF PMCON1,WR ; Set WR bit to begin erase
NOP ; NOP instructions are forced as processor starts
NOP ; row erase of program memory.
;
; The processor stalls until the erase process is complete
; after erase processor continues with 3rd instruction

BCF PMCON1,WREN ; Disable writes

BSF INTCON,GIE ; Enable interrupts

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 PIC16(L)F1508/9
10.2.4 WRITING TO FLASH PROGRAM The following steps should be completed to load the
MEMORY write latches and program a row of program memory.
These steps are divided into two parts. First, each write
Program memory is programmed using the following
latch is loaded with data from the PMDATH:PMDATL
steps:
using the unlock sequence with LWLO = 1. When the
1. Load the address in PMADRH:PMADRL of the last word to be loaded into the write latch is ready, the
row to be programmed. LWLO bit is cleared and the unlock sequence
2. Load each write latch with data. executed. This initiates the programming operation,
3. Initiate a programming operation. writing all the latches into Flash program memory.
4. Repeat steps 1 through 3 until all data is written. Note: The special unlock sequence is required
Before writing to program memory, the word(s) to be to load a write latch with data or initiate a
written must be erased or previously unwritten. Pro- Flash programming operation. If the
gram memory can only be erased one row at a time. No unlock sequence is interrupted, writing to
automatic erase occurs upon the initiation of the write. the latches or program memory will not be
initiated.
Program memory can be written one or more words at
a time. The maximum number of words written at one 1. Set the WREN bit of the PMCON1 register.
time is equal to the number of write latches. See 2. Clear the CFGS bit of the PMCON1 register.
Figure 10-5 (row writes to program memory with 32 3. Set the LWLO bit of the PMCON1 register.
write latches) for more details. When the LWLO bit of the PMCON1 register is
The write latches are aligned to the Flash row address ‘1’, the write sequence will only load the write
boundary defined by the upper 10-bits of latches and will not initiate the write to Flash
PMADRH:PMADRL, (PMADRH<6:0>:PMADRL<7:5>) program memory.
with the lower five bits of PMADRL, (PMADRL<4:0>) 4. Load the PMADRH:PMADRL register pair with
determining the write latch being loaded. Write opera- the address of the location to be written.
tions do not cross these boundaries. At the completion 5. Load the PMDATH:PMDATL register pair with
of a program memory write operation, the data in the the program memory data to be written.
write latches is reset to contain 0x3FFF.
6. Execute the unlock sequence (Section 10.2.2
“Flash Memory Unlock Sequence”). The write
latch is now loaded.
7. Increment the PMADRH:PMADRL register pair
to point to the next location.
8. Repeat steps 5 through 7 until all but the last
write latch has been loaded.
9. Clear the LWLO bit of the PMCON1 register.
When the LWLO bit of the PMCON1 register is
‘0’, the write sequence will initiate the write to
Flash program memory.
10. Load the PMDATH:PMDATL register pair with
the program memory data to be written.
11. Execute the unlock sequence (Section 10.2.2
“Flash Memory Unlock Sequence”). The
entire program memory latch content is now
written to Flash program memory.
Note: The program memory write latches are
reset to the blank state (0x3FFF) at the
completion of every write or erase
operation. As a result, it is not necessary
to load all the program memory write
latches. Unloaded latches will remain in
the blank state.
An example of the complete write sequence is shown in
Example 10-3. The initial address is loaded into the
PMADRH:PMADRL register pair; the data is loaded
using indirect addressing.

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 FIGURE 10-5: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES
DS40001609C-page 100

PIC16(L)F1508/9
Rev. 10-000004A

7 6 0 7 5 4 0 7 5 0 7 0 7/30/2013

PMADRH PMADRL - - PMDATH PMDATL

- r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 c4 c3 c2 c1 c0 6 8

14

Program Memory Write Latches

10 5
14 14 14 14

Write Latch #0 Write Latch #1 Write Latch #30 Write Latch #31
PMADRL<4:0> 00h 01h 1Eh 1Fh

14 14 14 14

Row Addr Addr Addr Addr

000h 0000h 0001h 001Eh 001Fh

001h 0020h 0021h 003Eh 003Fh
002h 0040h 0041h 005Eh 005Fh
CFGS = 0
 2011-2013 Microchip Technology Inc.

3FEh 7FC0h 7FC1h 7FDEh 7FDFh

Row 3FFh 7FE0h 7FE1h 7FFEh 7FFFh
Address
PMADRH<6:0>: Decode Flash Program Memory
PMADRL<7:5>

400h 8000h - 8003h 8004h – 8005h 8006h 8007h – 8008h 8009h - 801Fh
DEVICE ID Configuration
USER ID 0 - 3 reserved reserved
CFGS = 1 Dev / Rev Words

Configuration Memory
 PIC16(L)F1508/9
FIGURE 10-6: FLASH PROGRAM MEMORY WRITE FLOWCHART
Rev. 10-000049A
7/30/2013

Start
Write Operation

Determine number of
words to be written into Enable Write/Erase
Program or Configuration Operation (WREN = 1)
Memory. The number of
words cannot exceed the
number of words per row
(word_cnt)
Load the value to write
(PMDATH:PMDATL)

Disable Interrupts
(GIE = 0)
Update the word counter Write Latches to Flash
(word_cnt--) (LWLO = 0)

Select
Program or Config.
Memory (CFGS)
Unlock Sequence
Last word to Yes (See Note 1)
write ?
Select Row Address
(PMADRH:PMADRL)
No
CPU stalls while Write
operation completes
Unlock Sequence (2 ms typical)
Select Write Operation (See Note 1)
(FREE = 0)

Load Write Latches Only No delay when writing to Disable Write/Erase

(LWLO = 1) Program Memory Latches Operation (WREN = 0)

Re-enable Interrupts
(GIE = 1)
Increment Address
(PMADRH:PMADRL++)

End
Write Operation

Note 1: See Figure 10-3.

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PIC16(L)F1508/9
EXAMPLE 10-3: WRITING TO FLASH PROGRAM MEMORY (32 WRITE LATCHES)
; This write routine assumes the following:
; 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR
; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,
; stored in little endian format
; 3. A valid starting address (the Least Significant bits = 00000) is loaded in ADDRH:ADDRL
; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
;
BCF INTCON,GIE ; Disable ints so required sequences will execute properly
BANKSEL PMADRH ; Bank 3
MOVF ADDRH,W ; Load initial address
MOVWF PMADRH ;
MOVF ADDRL,W ;
MOVWF PMADRL ;
MOVLW LOW DATA_ADDR ; Load initial data address
MOVWF FSR0L ;
MOVLW HIGH DATA_ADDR ; Load initial data address
MOVWF FSR0H ;
BCF PMCON1,CFGS ; Not configuration space
BSF PMCON1,WREN ; Enable writes
BSF PMCON1,LWLO ; Only Load Write Latches
LOOP
MOVIW FSR0++ ; Load first data byte into lower
MOVWF PMDATL ;
MOVIW FSR0++ ; Load second data byte into upper
MOVWF PMDATH ;

MOVF PMADRL,W ; Check if lower bits of address are '00000'

XORLW 0x1F ; Check if we're on the last of 32 addresses
ANDLW 0x1F ;
BTFSC STATUS,Z ; Exit if last of 32 words,
GOTO START_WRITE ;

MOVLW 55h ; Start of required write sequence:

MOVWF PMCON2 ; Write 55h
MOVLW 0AAh ;
Sequence
Required

MOVWF PMCON2 ; Write AAh

BSF PMCON1,WR ; Set WR bit to begin write
NOP ; NOP instructions are forced as processor
; loads program memory write latches
NOP ;

INCF PMADRL,F ; Still loading latches Increment address

GOTO LOOP ; Write next latches

START_WRITE
BCF PMCON1,LWLO ; No more loading latches - Actually start Flash program
; memory write

MOVLW 55h ; Start of required write sequence:

MOVWF PMCON2 ; Write 55h
MOVLW 0AAh ;
Sequence
Required

MOVWF PMCON2 ; Write AAh

BSF PMCON1,WR ; Set WR bit to begin write
NOP ; NOP instructions are forced as processor writes
; all the program memory write latches simultaneously
NOP ; to program memory.
; After NOPs, the processor
; stalls until the self-write process in complete
; after write processor continues with 3rd instruction
BCF PMCON1,WREN ; Disable writes
BSF INTCON,GIE ; Enable interrupts

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 PIC16(L)F1508/9
10.3 Modifying Flash Program Memory FIGURE 10-7: FLASH PROGRAM
MEMORY MODIFY
When modifying existing data in a program memory
FLOWCHART
row, and data within that row must be preserved, it
must first be read and saved in a RAM image. Program Rev. 10-000050A
7/30/2013

memory is modified using the following steps:

1. Load the starting address of the row to be Start
modified. Modify Operation
2. Read the existing data from the row into a RAM
image.
3. Modify the RAM image to contain the new data Read Operation
to be written into program memory. (See Note 1)
4. Load the starting address of the row to be
rewritten.
5. Erase the program memory row.
An image of the entire row
6. Load the write latches with data from the RAM read must be stored in RAM
image.
7. Initiate a programming operation.

Modify Image
The words to be modified are
changed in the RAM image

Erase Operation
(See Note 2)

Write Operation
Use RAM image
(See Note 3)

End
Modify Operation

Note 1: See Figure 10-2.

2: See Figure 10-4.
3: See Figure 10-5.

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PIC16(L)F1508/9
10.4 User ID, Device ID and
Configuration Word Access
Instead of accessing program memory, the User ID’s,
Device ID/Revision ID and Configuration Words can be
accessed when CFGS = 1 in the PMCON1 register.
This is the region that would be pointed to by
PC<15> = 1, but not all addresses are accessible.
Different access may exist for reads and writes. Refer
to Table 10-2.
When read access is initiated on an address outside
the parameters listed in Table 10-2, the
PMDATH:PMDATL register pair is cleared, reading
back ‘0’s.

TABLE 10-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)
Address Function Read Access Write Access
8000h-8003h User IDs Yes Yes
8006h Device ID/Revision ID Yes No
8007h-8008h Configuration Words 1 and 2 Yes No

EXAMPLE 10-4: CONFIGURATION WORD AND DEVICE ID ACCESS

* This code block will read 1 word of program memory at the memory address:
* PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;
* PROG_DATA_HI, PROG_DATA_LO

BANKSEL PMADRL ; Select correct Bank

MOVLW PROG_ADDR_LO ;
MOVWF PMADRL ; Store LSB of address
CLRF PMADRH ; Clear MSB of address

BSF PMCON1,CFGS ; Select Configuration Space

BCF INTCON,GIE ; Disable interrupts
BSF PMCON1,RD ; Initiate read
NOP ; Executed (See Figure 10-2)
NOP ; Ignored (See Figure 10-2)
BSF INTCON,GIE ; Restore interrupts

MOVF PMDATL,W ; Get LSB of word

MOVWF PROG_DATA_LO ; Store in user location
MOVF PMDATH,W ; Get MSB of word
MOVWF PROG_DATA_HI ; Store in user location

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10.5 Write Verify
It is considered good programming practice to verify that
program memory writes agree with the intended value.
Since program memory is stored as a full page then the
stored program memory contents are compared with
the intended data stored in RAM after the last write is
complete.

FIGURE 10-8: FLASH PROGRAM

MEMORY VERIFY
FLOWCHART
Rev. 10-000051A
7/30/2013

Start
Verify Operation

This routine assumes that the last

row of data written was from an
image saved on RAM. This image
will be used to verify the data
currently stored in Flash Program
Memory

Read Operation
(See Note 1)

PMDAT = No
RAM image ?

Yes
Fail
Verify Operation

No
Last word ?

Yes

End
Verify Operation

Note 1: See Figure 10-2.

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10.6 Register Definitions: Flash Program Memory Control

REGISTER 10-1: PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
PMDAT<7:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 PMDAT<7:0>: Read/write value for Least Significant bits of program memory

REGISTER 10-2: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER

U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — PMDAT<13:8>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 PMDAT<13:8>: Read/write value for Most Significant bits of program memory

REGISTER 10-3: PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
PMADR<7:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 PMADR<7:0>: Specifies the Least Significant bits for program memory address

REGISTER 10-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER

U-1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
—(1) PMADR<14:8>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 Unimplemented: Read as ‘1’

bit 6-0 PMADR<14:8>: Specifies the Most Significant bits for program memory address

Note 1: Unimplemented, read as ‘1’.

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REGISTER 10-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER

U-1 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W/HC-x/q(2) R/W-0/0 R/S/HC-0/0 R/S/HC-0/0
—(1) CFGS LWLO FREE WRERR WREN WR RD
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware

bit 7 Unimplemented: Read as ‘1’

bit 6 CFGS: Configuration Select bit
1 = Access Configuration, User ID and Device ID Registers
0 = Access Flash program memory
bit 5 LWLO: Load Write Latches Only bit(3)
1 = Only the addressed program memory write latch is loaded/updated on the next WR command
0 = The addressed program memory write latch is loaded/updated and a write of all program memory write latches
will be initiated on the next WR command
bit 4 FREE: Program Flash Erase Enable bit
1 = Performs an erase operation on the next WR command (hardware cleared upon completion)
0 = Performs a write operation on the next WR command
bit 3 WRERR: Program/Erase Error Flag bit
1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically
on any set attempt (write ‘1’) of the WR bit).
0 = The program or erase operation completed normally.
bit 2 WREN: Program/Erase Enable bit
1 = Allows program/erase cycles
0 = Inhibits programming/erasing of program Flash
bit 1 WR: Write Control bit
1 = Initiates a program Flash program/erase operation.
The operation is self-timed and the bit is cleared by hardware once operation is complete.
The WR bit can only be set (not cleared) in software.
0 = Program/erase operation to the Flash is complete and inactive.
bit 0 RD: Read Control bit
1 = Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set
(not cleared) in software.
0 = Does not initiate a program Flash read.
Note 1: Unimplemented bit, read as ‘1’.
2: The WRERR bit is automatically set by hardware when a program memory write or erase operation is started (WR = 1).
3: The LWLO bit is ignored during a program memory erase operation (FREE = 1).

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REGISTER 10-6: PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER

W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0
Program Memory Control Register 2
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 Flash Memory Unlock Pattern bits

To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the
PMCON1 register. The value written to this register is used to unlock the writes. There are specific
timing requirements on these writes.

TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY

Register on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Page
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76
PMCON1 (1) CFGS LWLO FREE WRERR WREN WR RD
— 107
PMCON2 Program Memory Control Register 2 108
PMADRL PMADRL<7:0> 106
(1)
PMADRH — PMADRH<6:0> 106
PMDATL PMDATL<7:0> 106
PMDATH — — PMDATH<5:0> 106
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.
Note 1: Unimplemented, read as ‘1’.

TABLE 10-4: SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY

Register
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0
on Page

13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> —

CONFIG1 42
7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>
13:8 — — LVP DEBUG LPBOR BORV STVREN —
CONFIG2 44
7:0 — — — — — — WRT<1:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.

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 PIC16(L)F1508/9
11.0 I/O PORTS FIGURE 11-1: GENERIC I/O PORT
OPERATION
Each port has three standard registers for its operation.
These registers are: Rev. 10-000052A
7/30/2013

• TRISx registers (data direction) Read LATx

• PORTx registers (reads the levels on the pins of
the device)
TRISx
• LATx registers (output latch)
D Q
Some ports may have one or more of the following
additional registers. These registers are: Write LATx
VDD
Write PORTx
• ANSELx (analog select) CK

• WPUx (weak pull-up) Data Register

In general, when a peripheral is enabled on a port pin, Data bus
that pin cannot be used as a general purpose output. I/O pin
However, the pin can still be read. Read PORTx

To digital peripherals
TABLE 11-1: PORT AVAILABILITY PER ANSELx
DEVICE
To analog peripherals
PORTB
PORTA

PORTC

VSS
Device

PIC16(L)F1509 ● ● ●
PIC16(L)F1508 ● ● ●
The Data Latch (LATx registers) is useful for
read-modify-write operations on the value that the I/O
pins are driving.
A write operation to the LATx register has the same
effect as a write to the corresponding PORTx register.
A read of the LATx register reads of the values held in
the I/O PORT latches, while a read of the PORTx
register reads the actual I/O pin value.
Ports that support analog inputs have an associated
ANSELx register. When an ANSEL bit is set, the digital
input buffer associated with that bit is disabled.
Disabling the input buffer prevents analog signal levels
on the pin between a logic high and low from causing
excessive current in the logic input circuitry. A
simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 11-1.

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11.1 Alternate Pin Function These bits have no effect on the values of any TRIS
register. PORT and TRIS overrides will be routed to the
The Alternate Pin Function Control (APFCON) register correct pin. The unselected pin will be unaffected.
is used to steer specific peripheral input and output
functions between different pins. The APFCON register
is shown in Register 11-1. For this device family, the
following functions can be moved between different
pins.
• SS
• T1G
• CLC1
• NCO1

11.2 Register Definitions: Alternate Pin Function Control

REGISTER 11-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER

U-0 U-0 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0
— — — SSSEL T1GSEL — CLC1SEL NCO1SEL
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 Unimplemented: Read as ‘0’

bit 4 SSSEL: Pin Selection bit
1 = SS function is on RA3
0 = SS function is on RC6
bit 3 T1GSEL: Pin Selection bit
1 = T1G function is on RA3
0 = T1G function is on RA4
bit 2 Unimplemented: Read as ‘0’
bit 1 CLC1SEL: Pin Selection bit
1 = CLC1 function is on RC5
0 = CLC1 function is on RA2
bit 0 NCO1SEL: Pin Selection bit
1 = NCO1 function is on RC6
0 = NCO1 function is on RC1

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11.3 PORTA Registers 11.3.4 PORTA FUNCTIONS AND OUTPUT
PRIORITIES
11.3.1 DATA REGISTER
Each PORTA pin is multiplexed with other functions. The
PORTA is a 6-bit wide, bidirectional port. The pins, their combined functions and their output priorities
corresponding data direction register is TRISA are shown in Table 11-2.
(Register 11-3). Setting a TRISA bit (= 1) will make the
When multiple outputs are enabled, the actual pin
corresponding PORTA pin an input (i.e., disable the
control goes to the peripheral with the highest priority.
output driver). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., enables Analog input functions, such as ADC and comparator
output driver and puts the contents of the output latch inputs, are not shown in the priority lists. These inputs
on the selected pin). The exception is RA3, which is are active when the I/O pin is set for Analog mode using
input-only and its TRIS bit will always read as ‘1’. the ANSELx registers. Digital output functions may
Example 11-1 shows how to initialize an I/O port. control the pin when it is in Analog mode with the
priority shown below in Table 11-2.
Reading the PORTA register (Register 11-2) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write TABLE 11-2: PORTA OUTPUT PRIORITY
operations. Therefore, a write to a port implies that the
Pin Name Function Priority(1)
port pins are read, this value is modified and then
written to the PORT data latch (LATA). RA0 ICSPDAT
DAC1OUT1
11.3.2 DIRECTION CONTROL RA0
RA1 RA1
The TRISA register (Register 11-3) controls the
PORTA pin output drivers, even when they are being RA2 DAC1OUT2
used as analog inputs. The user should ensure the bits CLC1(2)
C1OUT
in the TRISA register are maintained set when using
PWM3
them as analog inputs. I/O pins configured as analog RA2
input always read ‘0’.
RA3 None
11.3.3 ANALOG CONTROL RA4 CLKOUT
SOSCO
The ANSELA register (Register 11-5) is used to RA4
configure the Input mode of an I/O pin to analog.
RA5 SOSCI
Setting the appropriate ANSELA bit high will cause all RA5
digital reads on the pin to be read as ‘0’ and allow
Note 1: Priority listed from highest to lowest.
analog functions on the pin to operate correctly.
2: Default pin (see APFCON register).
The state of the ANSELA bits has no effect on digital 3: Alternate pin (see APFCON register).
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
Note: The ANSELA bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.

EXAMPLE 11-1: INITIALIZING PORTA

BANKSEL PORTA ;
CLRF PORTA ;Init PORTA
BANKSEL LATA ;Data Latch
CLRF LATA ;
BANKSEL ANSELA ;
CLRF ANSELA ;digital I/O
BANKSEL TRISA ;
MOVLW B'00111000' ;Set RA<5:3> as inputs
MOVWF TRISA ;and set RA<2:0> as
;outputs

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11.4 Register Definitions: PORTA

REGISTER 11-2: PORTA: PORTA REGISTER

U-0 U-0 R/W-x/x R/W-x/x R-x/x R/W-x/x R/W-x/x R/W-x/x
— — RA5 RA4 RA3 RA2 RA1 RA0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 RA<5:0>: PORTA I/O Value bits(1)
1 = Port pin is > VIH
0 = Port pin is < VIL

Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.

REGISTER 11-3: TRISA: PORTA TRI-STATE REGISTER

U-0 U-0 R/W-1/1 R/W-1/1 U-1 R/W-1/1 R/W-1/1 R/W-1/1
— — TRISA5 TRISA4 —(1) TRISA2 TRISA1 TRISA0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 TRISA<5:4>: PORTA Tri-State Control bit
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
bit 3 Unimplemented: Read as ‘1’
bit 2-0 TRISA<2:0>: PORTA Tri-State Control bit
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output

Note 1: Unimplemented, read as ‘1’.

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REGISTER 11-4: LATA: PORTA DATA LATCH REGISTER

U-0 U-0 R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u
— — LATA5 LATA4 — LATA2 LATA1 LATA0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 LATA<5:4>: RA<5:4> Output Latch Value bits(1)
bit 3 Unimplemented: Read as ‘0’
bit 2-0 LATA<2:0>: RA<2:0> Output Latch Value bits(1)

Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.

REGISTER 11-5: ANSELA: PORTA ANALOG SELECT REGISTER

U-0 U-0 U-0 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1
— — — ANSA4 — ANSA2 ANSA1 ANSA0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 Unimplemented: Read as ‘0’

bit 4 ANSA4: Analog Select between Analog or Digital Function on pins RA4, respectively
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.
bit 3 Unimplemented: Read as ‘0’
bit 2-0 ANSA<2:0>: Analog Select between Analog or Digital Function on pins RA<2:0>, respectively
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.

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REGISTER 11-6: WPUA: WEAK PULL-UP PORTA REGISTER

U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
— — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 WPUA<5:0>: Weak Pull-up Register bits(3)
1 = Pull-up enabled
0 = Pull-up disabled

Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is configured as an output.
3: For the WPUA3 bit, when MCLRE = 1, weak pull-up is internally enabled, but not reported here.

TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 113

APFCON — — — SSSEL T1GSEL — CLC1SEL NCO1SEL 110
LATA — — LATA5 LATA4 — LATA2 LATA1 LATA0 113
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 163
PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 112
TRISA — — TRISA5 TRISA4 —(1) TRISA2 TRISA1 TRISA0 112
WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 114
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
Note 1: Unimplemented, read as ‘1’.

TABLE 11-4: SUMMARY OF CONFIGURATION WORD WITH PORTA

Register
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0
on Page

13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> —

CONFIG1 42
7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.

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 PIC16(L)F1508/9
11.5 PORTB Registers 11.5.4 PORTB FUNCTIONS AND OUTPUT
PRIORITIES
11.5.1 DATA REGISTER
Each PORTB pin is multiplexed with other functions. The
PORTB is a 4-bit wide, bidirectional port. The pins, their combined functions and their output priorities
corresponding data direction register is TRISB are shown in Table 11-5.
(Register 11-8). Setting a TRISB bit (= 1) will make the
When multiple outputs are enabled, the actual pin
corresponding PORTB pin an input (i.e., disable the
control goes to the peripheral with the highest priority.
output driver). Clearing a TRISB bit (= 0) will make the
corresponding PORTB pin an output (i.e., enables Analog input functions, such as ADC and comparator
output driver and puts the contents of the output latch inputs, are not shown in the priority lists. These inputs
on the selected pin). Example 11-1 shows how to are active when the I/O pin is set for Analog mode using
initialize an I/O port. the ANSELx registers. Digital output functions may
control the pin when it is in Analog mode with the
Reading the PORTB register (Register 11-7) reads the
priority shown below in Table 11-5.
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the TABLE 11-5: PORTB OUTPUT PRIORITY
port pins are read, this value is modified and then
Pin Name Function Priority(1)
written to the PORT data latch (LATB).
RB4 SDA
11.5.2 DIRECTION CONTROL RB4
The TRISB register (Register 11-8) controls the RB5 RB5
PORTB pin output drivers, even when they are being RB6 SCL
used as analog inputs. The user should ensure the bits SCK
in the TRISB register are maintained set when using RB6
them as analog inputs. I/O pins configured as analog
RB7 CLC3
input always read ‘0’.
TX
11.5.3 ANALOG CONTROL RB7
Note 1: Priority listed from highest to lowest.
The ANSELB register (Register 11-10) is used to
configure the Input mode of an I/O pin to analog. 2: Default pin (see APFCON register).
Setting the appropriate ANSELB bit high will cause all 3: Alternate pin (see APFCON register).
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELB bits has no effect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
Note: The ANSELB bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.

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PIC16(L)F1508/9
11.6 Register Definitions: PORTB

REGISTER 11-7: PORTB: PORTB REGISTER

R/W-x/x R/W-x/x R/W-x/x R/W-x/x U-0 U-0 U-0 U-0
RB7 RB6 RB5 RB4 — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 RB<7:4>: PORTB I/O Value bits(1)

1 = Port pin is > VIH
0 = Port pin is < VIL
bit 3-0 Unimplemented: Read as ‘0’

Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
return of actual I/O pin values.

REGISTER 11-8: TRISB: PORTB TRI-STATE REGISTER

R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0
TRISB7 TRISB6 TRISB5 TRISB4 — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 RB<7:4>: PORTB Tri-State Control bits

1 = PORTB pin configured as an input (tri-stated)
0 = PORTB pin configured as an output
bit 3-0 Unimplemented: Read as ‘0’

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REGISTER 11-9: LATB: PORTB DATA LATCH REGISTER

R/W-x/u R/W-x/u R/W-x/u R/W-x/u U-0 U-0 U-0 U-0
LATB7 LATB6 LATB5 LATB4 — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 LATB<7:4>: RB<7:4> Output Latch Value bits(1)

bit 3-0 Unimplemented: Read as ‘0’

Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
return of actual I/O pin values.

REGISTER 11-10: ANSELB: PORTB ANALOG SELECT REGISTER

U-0 U-0 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0
— — ANSB5 ANSB4 — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 ANSB<5:4>: Analog Select between Analog or Digital Function on pins RB<5:4>, respectively
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.
bit 3-0 Unimplemented: Read as ‘0’

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.

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REGISTER 11-11: WPUB: WEAK PULL-UP PORTB REGISTER

R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0
WPUB7 WPUB6 WPUB5 WPUB4 — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 WPUB<7:4>: Weak Pull-up Register bits

1 = Pull-up enabled
0 = Pull-up disabled
bit 3-0 Unimplemented: Read as ‘0’

Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is configured as an output.

TABLE 11-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

ANSELB — — ANSB5 ANSB4 — — — — 117

APFCON — — — SSSEL T1GSEL — CLC1SEL NCO1SEL 110
LATB LATB7 LATB6 LATB5 LATB4 — — — — 117
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 163
PORTB RB7 RB6 RB5 RB4 — — — — 116
TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 116
WPUB WPUB7 WPUB6 WPUB5 WPUB4 — — — — 118
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.
Note 1: Unimplemented, read as ‘1’.

TABLE 11-7: SUMMARY OF CONFIGURATION WORD WITH PORTB

Register
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0
on Page

13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> —

CONFIG1 42
7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTB.

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11.7 PORTC Registers 11.7.4 PORTC FUNCTIONS AND OUTPUT
PRIORITIES
11.7.1 DATA REGISTER
Each PORTC pin is multiplexed with other functions. The
PORTC is a 8-bit wide, bidirectional port. The pins, their combined functions and their output priorities
corresponding data direction register is TRISC are shown in Table 11-8.
(Register 11-13). Setting a TRISC bit (= 1) will make
When multiple outputs are enabled, the actual pin
the corresponding PORTC pin an input (i.e., disable
control goes to the peripheral with the highest priority.
the output driver). Clearing a TRISC bit (= 0) will make
the corresponding PORTC pin an output (i.e., enable Analog input and some digital input functions are not
the output driver and put the contents of the output included in the output priority list. These input functions
latch on the selected pin). Example 11-1 shows how to can remain active when the pin is configured as an
initialize an I/O port. output. Certain digital input functions override other
port functions and are included in the output priority list.
Reading the PORTC register (Register 11-12) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write TABLE 11-8: PORTC OUTPUT PRIORITY
operations. Therefore, a write to a port implies that the
Pin Name Function Priority(1)
port pins are read, this value is modified and then written
to the PORT data latch (LATC). RC0 CLC2
RC0
11.7.2 DIRECTION CONTROL RC1 NCO1(2)
The TRISC register (Register 11-13) controls the PWM4
PORTC pin output drivers, even when they are being RC1
used as analog inputs. The user should ensure the bits in RC2 RC2
the TRISC register are maintained set when using them
RC3 PWM2
as analog inputs. I/O pins configured as analog input
RC3
always read ‘0’.
RC4 CWG1B
11.7.3 ANALOG CONTROL CLC4
C2OUT
The ANSELC register (Register 11-15) is used to
RC4
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELC bit high will cause all RC5 CWG1A
digital reads on the pin to be read as ‘0’ and allow CLC1(3)
analog functions on the pin to operate correctly. PWM1
RC5
The state of the ANSELC bits has no effect on digital out-
put functions. A pin with TRIS clear and ANSELC set will RC6 NCO1(3)
still operate as a digital output, but the Input mode will be RC6
analog. This can cause unexpected behavior when exe- RC7 SDO
cuting read-modify-write instructions on the affected RC7
port. Note 1: Priority listed from highest to lowest.
Note: The ANSELC bits default to the Analog 2: Default pin (see APFCON register).
mode after Reset. To use any pins as 3: Alternate pin (see APFCON register).
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.

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11.8 Register Definitions: PORTC

REGISTER 11-12: PORTC: PORTC REGISTER

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 RC<7:0>: PORTC General Purpose I/O Pin bits

1 = Port pin is > VIH
0 = Port pin is < VIL

REGISTER 11-13: TRISC: PORTC TRI-STATE REGISTER

R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 TRISC<7:0>: PORTC Tri-State Control bits

1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output

REGISTER 11-14: LATC: PORTC DATA LATCH REGISTER

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 LATC<7:0>: PORTC Output Latch Value bits(1)

Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is
return of actual I/O pin values.

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REGISTER 11-15: ANSELC: PORTC ANALOG SELECT REGISTER

R/W-1/1 R/W-1/1 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
ANSC7 ANSC6 — — ANSC3 ANSC2 ANSC1 ANSC0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 ANSC<7:6>: Analog Select between Analog or Digital Function on pins RC<7:6>, respectively
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.
bit 5-4 Unimplemented: Read as ‘0’
bit 3-0 ANSC<3:0>: Analog Select between Analog or Digital Function on pins RC<3:0>, respectively
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.

TABLE 11-9: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
ANSELC ANSC7 ANSC6 — — ANSC3 ANSC2 ANSC1 ANSC0 121
LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 120
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 120
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 120
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.

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NOTES:

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12.0 INTERRUPT-ON-CHANGE 12.3 Interrupt Flags
The PORTA and PORTB pins can be configured to The IOCAFx and IOCBFx bits located in the IOCAF and
operate as Interrupt-On-Change (IOC) pins. An interrupt IOCBF registers, respectively, are status flags that
can be generated by detecting a signal that has either a correspond to the interrupt-on-change pins of the
rising edge or a falling edge. Any individual port pin, or associated port. If an expected edge is detected on an
combination of port pins, can be configured to generate appropriately enabled pin, then the status flag for that pin
an interrupt. The interrupt-on-change module has the will be set, and an interrupt will be generated if the IOCIE
following features: bit is set. The IOCIF bit of the INTCON register reflects
the status of all IOCAFx and IOCBFx bits.
• Interrupt-on-Change enable (Master Switch)
• Individual pin configuration
12.4 Clearing Interrupt Flags
• Rising and falling edge detection
• Individual pin interrupt flags The individual status flags, (IOCAFx and IOCBFx bits),
can be cleared by resetting them to zero. If another edge
Figure 12-1 is a block diagram of the IOC module.
is detected during this clearing operation, the associated
status flag will be set at the end of the sequence,
12.1 Enabling the Module regardless of the value actually being written.
To allow individual port pins to generate an interrupt, the In order to ensure that no detected edge is lost while
IOCIE bit of the INTCON register must be set. If the clearing flags, only AND operations masking out known
IOCIE bit is disabled, the edge detection on the pin will changed bits should be performed. The following
still occur, but an interrupt will not be generated. sequence is an example of what should be performed.

12.2 Individual Pin Configuration EXAMPLE 12-1: CLEARING INTERRUPT

FLAGS
For each port pin, a rising edge detector and a falling
(PORTA EXAMPLE)
edge detector are present. To enable a pin to detect a
rising edge, the associated bit of the IOCxP register is MOVLW 0xff
set. To enable a pin to detect a falling edge, the XORWF IOCAF, W
associated bit of the IOCxN register is set. ANDWF IOCAF, F

A pin can be configured to detect rising and falling

edges simultaneously by setting both associated bits of 12.5 Operation in Sleep
the IOCxP and IOCxN registers, respectively.
The interrupt-on-change interrupt sequence will wake
the device from Sleep mode, if the IOCIE bit is set.
If an edge is detected while in Sleep mode, the IOCxF
register will be updated prior to the first instruction
executed out of Sleep.

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FIGURE 12-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE)
Rev. 10-000037A
7/30/2013

IOCANx D Q

R Q4Q1
edge
detect

RAx

to data bus
data bus = S
IOCAPx D Q D Q IOCAFx
0 or 1

R
write IOCAFx R

IOCIE
Q2
IOC interrupt
to CPU core
from all other
IOCnFx individual
pin detectors

FOSC

Q1 Q1 Q1

Q2 Q2 Q2

Q3 Q3 Q3

Q4 Q4 Q4

Q4Q1 Q4Q1 Q4Q1 Q4Q1

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12.6 Register Definitions: Interrupt-on-Change Control

REGISTER 12-1: IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 IOCAP<5:0>: Interrupt-on-Change PORTA Positive Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCAFx bit and IOCIF flag will be set
upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.

REGISTER 12-2: IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 IOCAN<5:0>: Interrupt-on-Change PORTA Negative Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCAFx bit and IOCIF flag will be set
upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.

REGISTER 12-3: IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER

U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
— — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 IOCAF<5:0>: Interrupt-on-Change PORTA Flag bits
1 = An enabled change was detected on the associated pin.
Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling edge was
detected on RAx.
0 = No change was detected, or the user cleared the detected change.

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REGISTER 12-4: IOCBP: INTERRUPT-ON-CHANGE PORTB POSITIVE EDGE REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0
IOCBP7 IOCBP6 IOCBP5 IOCBP4 — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 IOCBP<7:4>: Interrupt-on-Change PORTB Positive Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCBFx bit and IOCIF flag will be set
upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
bit 3-0 Unimplemented: Read as ‘0’

REGISTER 12-5: IOCBN: INTERRUPT-ON-CHANGE PORTB NEGATIVE EDGE REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0
IOCBN7 IOCBN6 IOCBN5 IOCBN4 — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 IOCBN<7:4>: Interrupt-on-Change PORTB Negative Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCBFx bit and IOCIF flag will be set
upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
bit 3-0 Unimplemented: Read as ‘0’

REGISTER 12-6: IOCBF: INTERRUPT-ON-CHANGE PORTB FLAG REGISTER

R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 U-0 U-0 U-0 U-0
IOCBF7 IOCBF6 IOCBF5 IOCBF4 — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware

bit 7-4 IOCBF<7:4>: Interrupt-on-Change PORTB Flag bits

1 = An enabled change was detected on the associated pin.
Set when IOCBPx = 1 and a rising edge was detected on RBx, or when IOCBNx = 1 and a falling edge was
detected on RBx.
0 = No change was detected, or the user cleared the detected change.
bit 3-0 Unimplemented: Read as ‘0’

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TABLE 12-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 113
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76
IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 125
IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 125
IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 125
IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 — — — — 126
IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 — — — — 126
IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 — — — — 126
—(1)
TRISA — — TRISA5 TRISA4 TRISA2 TRISA1 TRISA0 112
TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 116
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change.
Note 1: Unimplemented, read as ‘1’.

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13.0 FIXED VOLTAGE REFERENCE The ADFVR<1:0> bits of the FVRCON register are
used to enable and configure the gain amplifier settings
(FVR)
for the reference supplied to the ADC module. Refer-
The Fixed Voltage Reference (FVR) is a stable voltage ence Section 15.0 “Analog-to-Digital Converter
reference, independent of VDD, with a nominal output (ADC) Module” for additional information.
level (VFVR) of 1.024V. The output of the FVR can be The CDAFVR<1:0> bits of the FVRCON register are
configured to supply a reference voltage to the used to enable and configure the gain amplifier settings
following: for the reference supplied to the comparator modules.
• ADC input channel Reference Section 17.0 “Comparator Module” for
• Comparator positive input additional information.
• Comparator negative input To minimize current consumption when the FVR is
disabled, the FVR buffers should be turned off by
The FVR can be enabled by setting the FVREN bit of
clearing the Buffer Gain Selection bits.
the FVRCON register.

13.1 Independent Gain Amplifier 13.2 FVR Stabilization Period

When the Fixed Voltage Reference module is enabled, it
The output of the FVR supplied to the peripherals,
requires time for the reference and amplifier circuits to
(listed above), is routed through a programmable gain
stabilize. Once the circuits stabilize and are ready for use,
amplifier. Each amplifier can be programmed for a gain
the FVRRDY bit of the FVRCON register will be set. See
of 1x, 2x or 4x, to produce the three possible voltage
the FVR Stabilization Period characterization graph,
levels.
Figure 30-65.

FIGURE 13-1: VOLTAGE REFERENCE BLOCK DIAGRAM

Rev. 10-000053A
8/6/2013

2
ADFVR<1:0>

1x
FVR_buffer1
2x
4x (To ADC Module)

2
CDAFVR<1:0>

1x
FVR_buffer2
2x
4x (To Comparators)

FVREN
+
_ FVRRDY
Note 1

Note 1: Any peripheral requiring the Fixed Reference (See Table 13-1)

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TABLE 13-1: PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR)

Peripheral Conditions Description
HFINTOSC FOSC<2:0> = 010 and INTOSC is active and device is not in Sleep.
IRCF<3:0> = 000x
BOREN<1:0> = 11 BOR always enabled.
BOR BOREN<1:0> = 10 and BORFS = 1 BOR disabled in Sleep mode, BOR Fast Start enabled.
BOREN<1:0> = 01 and BORFS = 1 BOR under software control, BOR Fast Start enabled.
LDO All PIC16F1508/9 devices, when The device runs off of the Low-Power Regulator when in
VREGPM = 1 and not in Sleep Sleep mode.

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13.3 Register Definitions: FVR Control

REGISTER 13-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER

R/W-0/0 R-q/q R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
FVREN(1) FVRRDY (2)
TSEN (3)
TSRNG (3)
CDAFVR<1:0> (1)
ADFVR<1:0>(1)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 FVREN: Fixed Voltage Reference Enable bit(1)

1 = Fixed Voltage Reference is enabled
0 = Fixed Voltage Reference is disabled
bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(2)
1 = Fixed Voltage Reference output is ready for use
0 = Fixed Voltage Reference output is not ready or not enabled
bit 5 TSEN: Temperature Indicator Enable bit(3)
1 = Temperature Indicator is enabled
0 = Temperature Indicator is disabled
bit 4 TSRNG: Temperature Indicator Range Selection bit(3)
1 = VOUT = VDD - 4VT (High Range)
0 = VOUT = VDD - 2VT (Low Range)
bit 3-2 CDAFVR<1:0>: Comparator FVR Buffer Gain Selection bits(1)
11 = Comparator FVR Buffer Gain is 4x, with output voltage = 4x VFVR (4.096V nominal)(4)
10 = Comparator FVR Buffer Gain is 2x, with output voltage = 2x VFVR (2.048V nominal)(4)
01 = Comparator FVR Buffer Gain is 1x, with output voltage = 1x VFVR (2.024V nominal)
00 = Comparator FVR Buffer is off
bit 1-0 ADFVR<1:0>: ADC FVR Buffer Gain Selection bit(1)
11 = ADC FVR Buffer Gain is 4x, with output voltage = 4x VFVR (4.096V nominal)(4)
10 = ADC FVR Buffer Gain is 2x, with output voltage = 2x VFVR (2.048V nominal)(4)
01 = ADC FVR Buffer Gain is 1x, with output voltage = 1x VFVR (2.024V nominal)
00 = ADC FVR Buffer is off

Note 1: To minimize current consumption when the FVR is disabled, the FVR buffers should be turned off by
clearing the Buffer Gain Selection bits.
2: FVRRDY is always ‘1’ for the PIC16F1508/9 devices.
3: See Section 14.0 “Temperature Indicator Module” for additional information.
4: Fixed Voltage Reference output cannot exceed VDD.

TABLE 13-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE FIXED VOLTAGE REFERENCE
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on page
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR>1:0> ADFVR<1:0> 131
Legend: Shaded cells are unused by the Fixed Voltage Reference module.

 2011-2013 Microchip Technology Inc. DS40001609C-page 131

PIC16(L)F1508/9
NOTES:

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 PIC16(L)F1508/9
14.0 TEMPERATURE INDICATOR FIGURE 14-1: TEMPERATURE CIRCUIT
MODULE DIAGRAM

This family of devices is equipped with a temperature Rev. 10-000069A

7/31/2013
VDD
circuit designed to measure the operating temperature
of the silicon die. The circuit’s range of operating
temperature falls between -40°C and +85°C. The
output is a voltage that is proportional to the device TSEN
temperature. The output of the temperature indicator is
internally connected to the device ADC.
The circuit may be used as a temperature threshold
detector or a more accurate temperature indicator, TSRNG
depending on the level of calibration performed. A one-
point calibration allows the circuit to indicate a
temperature closely surrounding that point. A two-point
calibration allows the circuit to sense the entire range
of temperature more accurately. Reference Application VOUT
Note AN1333, “Use and Calibration of the Internal Temp. Indicator
To ADC
Temperature Indicator” (DS01333) for more details
regarding the calibration process.

14.1 Circuit Operation

Figure 14-1 shows a simplified block diagram of the
temperature circuit. The proportional voltage output is 14.2 Minimum Operating VDD
achieved by measuring the forward voltage drop across When the temperature circuit is operated in low range,
multiple silicon junctions. the device may be operated at any operating voltage
Equation 14-1 describes the output characteristics of that is within specifications.
the temperature indicator. When the temperature circuit is operated in high range,
the device operating voltage, VDD, must be high
EQUATION 14-1: VOUT RANGES enough to ensure that the temperature circuit is cor-
rectly biased.
High Range: VOUT = VDD - 4VT Table 14-1 shows the recommended minimum VDD vs.
range setting.
Low Range: VOUT = VDD - 2VT
TABLE 14-1: RECOMMENDED VDD VS.
RANGE
The temperature sense circuit is integrated with the
Fixed Voltage Reference (FVR) module. See Min. VDD, TSRNG = 1 Min. VDD, TSRNG = 0
Section 13.0 “Fixed Voltage Reference (FVR)” for 3.6V 1.8V
more information.
The circuit is enabled by setting the TSEN bit of the 14.3 Temperature Output
FVRCON register. When disabled, the circuit draws no
current. The output of the circuit is measured using the internal
Analog-to-Digital Converter. A channel is reserved for
The circuit operates in either high or low range. The high
the temperature circuit output. Refer to Section 15.0
range, selected by setting the TSRNG bit of the
“Analog-to-Digital Converter (ADC) Module” for
FVRCON register, provides a wider output voltage. This
detailed information.
provides more resolution over the temperature range,
but may be less consistent from part to part. This range
requires a higher bias voltage to operate and thus, a 14.4 ADC Acquisition Time
higher VDD is needed. To ensure accurate temperature measurements, the
The low range is selected by clearing the TSRNG bit of user must wait at least 200 s after the ADC input
the FVRCON register. The low range generates a lower multiplexer is connected to the temperature indicator
voltage drop and thus, a lower bias voltage is needed to output before the conversion is performed. In addition,
operate the circuit. The low range is provided for low the user must wait 200 s between sequential
voltage operation. conversions of the temperature indicator output.

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PIC16(L)F1508/9

TABLE 14-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on page
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 118
Legend: Shaded cells are unused by the temperature indicator module.

DS40001609C-page 134  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
15.0 ANALOG-TO-DIGITAL The ADC voltage reference is software selectable to be
either internally generated or externally supplied.
CONVERTER (ADC) MODULE
The ADC can generate an interrupt upon completion of
The Analog-to-Digital Converter (ADC) allows a conversion. This interrupt can be used to wake-up the
conversion of an analog input signal to a 10-bit binary device from Sleep.
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESH:ADRESL register pair).
Figure 15-1 shows the block diagram of the ADC.

FIGURE 15-1: ADC BLOCK DIAGRAM

VDD ADPREF Rev. 10-000033A

7/30/2013

Positive
VDD Reference
Select

VREF+ pin

VSS ADCS<2:0>
AN0
ANa VRNEG VRPOS
External .
Channel FOSC/n Fosc
. Divider FOSC
Inputs ADC
ADC_clk
. sampled Clock
ANz input Select FRC
FRC
Temp Indicator
Internal
Channel DACx_output ADC CLOCK SOURCE
Inputs
FVR_buffer1 ADC
Sample Circuit
CHS<4:0>
ADFM
set bit ADIF

10
complete 10-bit Result
Write to bit
GO/DONE
GO/DONE Q1 16
start
Q4
ADRESH ADRESL
Q2 Enable

Trigger Select
TRIGSEL<3:0> ADON
. . . VSS
Trigger Sources

AUTO CONVERSION
TRIGGER

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PIC16(L)F1508/9
15.1 ADC Configuration 15.1.4 CONVERSION CLOCK
When configuring and using the ADC the following The source of the conversion clock is software select-
functions must be considered: able via the ADCS bits of the ADCON1 register. There
are seven possible clock options:
• Port configuration
• FOSC/2
• Channel selection
• FOSC/4
• ADC voltage reference selection
• FOSC/8
• ADC conversion clock source
• FOSC/16
• Interrupt control
• FOSC/32
• Result formatting
• FOSC/64
15.1.1 PORT CONFIGURATION • FRC (internal RC oscillator)
The ADC can be used to convert both analog and The time to complete one bit conversion is defined as
digital signals. When converting analog signals, the I/O TAD. One full 10-bit conversion requires 11.5 TAD peri-
pin should be configured for analog by setting the ods as shown in Figure 15-2.
associated TRIS and ANSEL bits. Refer to For correct conversion, the appropriate TAD specifica-
Section 11.0 “I/O Ports” for more information. tion must be met. Refer to the ADC conversion require-
Note: Analog voltages on any pin that is defined ments in Section 29.0 “Electrical Specifications” for
as a digital input may cause the input more information. Table 15-1 gives examples of appro-
buffer to conduct excess current. priate ADC clock selections.
Note: Unless using the FRC, any changes in the
15.1.2 CHANNEL SELECTION system clock frequency will change the
There are 15 channel selections available: ADC clock frequency, which may
adversely affect the ADC result.
• AN<11:0> pins
• Temperature Indicator
• DAC1_output
• FVR_buffer1
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay (TACQ) is required
before starting the next conversion. Refer to
Section 15.2.6 “ADC Conversion Procedure” for
more information.

15.1.3 ADC VOLTAGE REFERENCE

The ADC module uses a positive and a negative
voltage reference. The positive reference is labeled
ref+ and the negative reference is labeled ref-.
The positive voltage reference (ref+) is selected by the
ADPREF bits in the ADCON1 register. The positive
voltage reference source can be:
• VREF+ pin
• VDD
The negative voltage reference (ref-) source is:
• VSS

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 PIC16(L)F1508/9
TABLE 15-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
ADC Clock Period (TAD) Device Frequency (FOSC)

ADC
ADCS<2:0
Clock 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz
>
Source
Fosc/2 000 100 ns 125 ns 250 ns 500 ns 2.0 s
Fosc/4 100 200 ns 250 ns 500 ns 1.0 s 4.0 s
Fosc/8 001 400 ns 500 ns 1.0 s 2.0 s 8.0 s
Fosc/16 101 800 ns 1.0 s 2.0 s 4.0 s 16.0 s
Fosc/32 010 1.6 s 2.0 s 4.0 s 8.0 s 32.0 s
Fosc/64 110 3.2 s 4.0 s 8.0 s 16.0 s 64.0 s
FRC x11 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s
Legend: Shaded cells are outside of recommended range.
Note: The TAD period when using the FRC clock source can fall within a specified range, (see TAD parameter).
The TAD period when using the FOSC-based clock source can be configured for a more precise TAD period.
However, the FRC clock source must be used when conversions are to be performed with the device in
Sleep mode.

FIGURE 15-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES

Rev. 10-000035A
7/30/2013

TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11

b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

THCD
Conversion Starts
TACQ On the following cycle:
Holding capacitor disconnected
from analog input (THCD).
ADRESH:ADRESL is loaded,
GO bit is cleared,
Set GO bit ADIF bit is set,
holding capacitor is reconnected to analog input.
Enable ADC (ADON bit)
and
Select channel (ACS bits)

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PIC16(L)F1508/9
15.1.5 INTERRUPTS 15.1.6 RESULT FORMATTING
The ADC module allows for the ability to generate an The 10-bit ADC conversion result can be supplied in
interrupt upon completion of an Analog-to-Digital two formats, left justified or right justified. The ADFM bit
conversion. The ADC Interrupt Flag is the ADIF bit in of the ADCON1 register controls the output format.
the PIR1 register. The ADC Interrupt Enable is the Figure 15-3 shows the two output formats.
ADIE bit in the PIE1 register. The ADIF bit must be
cleared in software.
Note 1: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
2: The ADC operates during Sleep only
when the FRC oscillator is selected.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP instruc-
tion is always executed. If the user is attempting to
wake-up from Sleep and resume in-line code execu-
tion, the GIE and PEIE bits of the INTCON register
must be disabled. If the GIE and PEIE bits of the
INTCON register are enabled, execution will switch to
the Interrupt Service Routine.

FIGURE 15-3: 10-BIT ADC CONVERSION RESULT FORMAT

Rev. 10-000054A
7/30/2013

ADRESH ADRESL

(ADFM = 0) MSB LSB

bit 7 bit 0 bit 7 bit 0

10-bit ADC Result Unimplemented: Read as ‘0’

(ADFM = 1) MSB LSB

bit 7 bit 0 bit 7 bit 0

Unimplemented: Read as ‘0’ 10-bit ADC Result

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 PIC16(L)F1508/9
15.2 ADC Operation 15.2.4 ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This
15.2.1 STARTING A CONVERSION requires the ADC clock source to be set to the FRC
To enable the ADC module, the ADON bit of the option. Performing the ADC conversion during Sleep
ADCON0 register must be set to a ‘1’. Setting the GO/ can reduce system noise. If the ADC interrupt is
DONE bit of the ADCON0 register to a ‘1’ will start the enabled, the device will wake-up from Sleep when the
Analog-to-Digital conversion. conversion completes. If the ADC interrupt is disabled,
the ADC module is turned off after the conversion com-
Note: The GO/DONE bit should not be set in the
pletes, although the ADON bit remains set.
same instruction that turns on the ADC.
Refer to Section 15.2.6 “ADC Conver- When the ADC clock source is something other than
sion Procedure”. FRC, a SLEEP instruction causes the present conver-
sion to be aborted and the ADC module is turned off,
15.2.2 COMPLETION OF A CONVERSION although the ADON bit remains set.
When the conversion is complete, the ADC module will: 15.2.5 AUTO-CONVERSION TRIGGER
• Clear the GO/DONE bit The auto-conversion trigger allows periodic ADC mea-
• Set the ADIF Interrupt Flag bit surements without software intervention. When a rising
• Update the ADRESH and ADRESL registers with edge of the selected source occurs, the GO/DONE bit
new conversion result is set by hardware.
The auto-conversion trigger source is selected with the
15.2.3 TERMINATING A CONVERSION TRIGSEL<3:0> bits of the ADCON2 register.
If a conversion must be terminated before completion, Using the auto-conversion trigger does not assure
the GO/DONE bit can be cleared in software. The proper ADC timing. It is the user’s responsibility to
ADRESH and ADRESL registers will be updated with ensure that the ADC timing requirements are met.
the partially complete Analog-to-Digital conversion
sample. Incomplete bits will match the last bit See Table 15-2 for auto-conversion sources.
converted.
Note: A device Reset forces all registers to their TABLE 15-2: AUTO-CONVERSION
Reset state. Thus, the ADC module is SOURCES
turned off and any pending conversion is Source Peripheral Signal Name
terminated.
Timer0 T0_overflow
Timer1 T1_overflow
Timer2 T2_match
Comparator C1 C1OUT_sync
Comparator C2 C2OUT_sync
CLC1 LC1_out
CLC2 LC2_out
CLC3 LC3_out
CLC4 LC4_out

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PIC16(L)F1508/9
15.2.6 ADC CONVERSION PROCEDURE EXAMPLE 15-1: ADC CONVERSION
This is an example procedure for using the ADC to ;This code block configures the ADC
perform an Analog-to-Digital conversion: ;for polling, Vdd and Vss references, FRC
;oscillator and AN0 input.
1. Configure Port:
;
• Disable pin output driver (Refer to the TRIS ;Conversion start & polling for completion
register) ; are included.
• Configure pin as analog (Refer to the ANSEL ;
register) BANKSEL ADCON1 ;
MOVLW B’11110000’ ;Right justify, FRC
2. Configure the ADC module: ;oscillator
• Select ADC conversion clock MOVWF ADCON1 ;Vdd and Vss Vref+
• Configure voltage reference BANKSEL TRISA ;
BSF TRISA,0 ;Set RA0 to input
• Select ADC input channel
BANKSEL ANSEL ;
• Turn on ADC module BSF ANSEL,0 ;Set RA0 to analog
3. Configure ADC interrupt (optional): BANKSEL ADCON0 ;
• Clear ADC interrupt flag MOVLW B’00000001’ ;Select channel AN0
MOVWF ADCON0 ;Turn ADC On
• Enable ADC interrupt CALL SampleTime ;Acquisiton delay
• Enable peripheral interrupt BSF ADCON0,ADGO ;Start conversion
• Enable global interrupt(1) BTFSC ADCON0,ADGO ;Is conversion done?
GOTO $-1 ;No, test again
4. Wait the required acquisition time(2). BANKSEL ADRESH ;
5. Start conversion by setting the GO/DONE bit. MOVF ADRESH,W ;Read upper 2 bits
6. Wait for ADC conversion to complete by one of MOVWF RESULTHI ;store in GPR space
the following: BANKSEL ADRESL ;
MOVF ADRESL,W ;Read lower 8 bits
• Polling the GO/DONE bit MOVWF RESULTLO ;Store in GPR space
• Waiting for the ADC interrupt (interrupts
enabled)
7. Read ADC Result.
8. Clear the ADC interrupt flag (required if interrupt
is enabled).

Note 1: The global interrupt can be disabled if the

user is attempting to wake-up from Sleep
and resume in-line code execution.
2: Refer to Section 15.4 “ADC Acquisi-
tion Requirements”.

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 PIC16(L)F1508/9
15.3 Register Definitions: ADC Control

REGISTER 15-1: ADCON0: ADC CONTROL REGISTER 0

U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— CHS<4:0> GO/DONE ADON
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 Unimplemented: Read as ‘0’

bit 6-2 CHS<4:0>: Analog Channel Select bits
00000 = AN0
00001 = AN1
00010 = AN2
00011 = AN3
00100 = AN4
00101 = AN5
00110 = AN6
00111 = AN7
01000 = AN8
01001 = AN9
01010 = AN10
01011 = AN11
01100 = Reserved. No channel connected.
•
•
•
11100 = Reserved. No channel connected.
11101 = Temperature Indicator(1)
11110 = DAC (Digital-to-Analog Converter)(2)
11111 = FVR (Fixed Voltage Reference) Buffer 1 Output(3)
bit 1 GO/DONE: ADC Conversion Status bit
1 = ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle.
This bit is automatically cleared by hardware when the ADC conversion has completed.
0 = ADC conversion completed/not in progress
bit 0 ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current
Note 1: See Section 14.0 “Temperature Indicator Module” for more information.
2: See Section 16.0 “5-Bit Digital-to-Analog Converter (DAC) Module” for more information.
3: See Section 13.0 “Fixed Voltage Reference (FVR)” for more information.

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PIC16(L)F1508/9
REGISTER 15-2: ADCON1: ADC CONTROL REGISTER 1
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0
ADFM ADCS<2:0> — — ADPREF<1:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 ADFM: ADC Result Format Select bit

1 = Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is
loaded.
0 = Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is
loaded.
bit 6-4 ADCS<2:0>: ADC Conversion Clock Select bits
000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
011 = FRC (clock supplied from an internal RC oscillator)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64
111 = FRC (clock supplied from an internal RC oscillator)
bit 3-2 Unimplemented: Read as ‘0’
bit 1-0 ADPREF<1:0>: ADC Positive Voltage Reference Configuration bits
00 = VRPOS is connected to VDD
01 = Reserved
10 = VRPOS is connected to external VREF+ pin(1)
11 = Reserved

Note 1: When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltage
specification exists. See Section 29.0 “Electrical Specifications” for details.

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 PIC16(L)F1508/9

REGISTER 15-3: ADCON2: ADC CONTROL REGISTER 2

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0
(1)
TRIGSEL<3:0> — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 TRIGSEL<3:0>: Auto-Conversion Trigger Selection bits(1)

0000 = No auto-conversion trigger selected
0001 = Reserved
0010 = Reserved
0011 = Timer0 – T0_overflow(2)
0100 = Timer1 – T1_overflow(2)
0101 = Timer2 – T2_match
0110 = Comparator C1 – C1OUT_sync
0111 = Comparator C2 – C2OUT_sync
1000 = CLC1 – LC1_out
1001 = CLC2 – LC2_out
1010 = CLC3 – LC3_out
1011 = CLC4 – LC4_out
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
bit 3-0 Unimplemented: Read as ‘0’

Note 1: This is a rising edge sensitive input for all sources.

2: Signal also sets its corresponding interrupt flag.

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PIC16(L)F1508/9

REGISTER 15-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
ADRES<9:2>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 ADRES<9:2>: ADC Result Register bits

Upper eight bits of 10-bit conversion result

REGISTER 15-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
ADRES<1:0> — — — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 ADRES<1:0>: ADC Result Register bits

Lower two bits of 10-bit conversion result
bit 5-0 Reserved: Do not use.

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 PIC16(L)F1508/9

REGISTER 15-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — — — — — ADRES<9:8>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-2 Reserved: Do not use.

bit 1-0 ADRES<9:8>: ADC Result Register bits
Upper two bits of 10-bit conversion result

REGISTER 15-7: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
ADRES<7:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 ADRES<7:0>: ADC Result Register bits

Lower eight bits of 10-bit conversion result

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PIC16(L)F1508/9
15.4 ADC Acquisition Requirements source impedance is decreased, the acquisition time
may be decreased. After the analog input channel is
For the ADC to meet its specified accuracy, the charge selected (or changed), an ADC acquisition must be
holding capacitor (CHOLD) must be allowed to fully done before the conversion can be started. To
charge to the input channel voltage level. The Analog calculate the minimum acquisition time, Equation 15-1
Input model is shown in Figure 15-4. The source may be used. This equation assumes that 1/2 LSb error
impedance (RS) and the internal sampling switch (RSS) is used (1,024 steps for the ADC). The 1/2 LSb error is
impedance directly affect the time required to charge the maximum error allowed for the ADC to meet its
the capacitor CHOLD. The sampling switch (RSS) specified resolution.
impedance varies over the device voltage (VDD), refer
to Figure 15-4. The maximum recommended
impedance for analog sources is 10 k. As the

EQUATION 15-1: ACQUISITION TIME EXAMPLE

Assumptions: Temperature = 50°C and external impedance of 10k  5.0V V DD

T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2µs + T C +   Temperature - 25°C   0.05µs/°C  

The value for TC can be approximated with the following equations:

1
V AP P LI ED  1 – -------------------------- = V CHOLD ;[1] VCHOLD charged to within 1/2 lsb
 n+1 
2 –1
–TC
 ----------
RC
V AP P LI ED  1 – e  = V CHOLD ;[2] VCHOLD charge response to VAPPLIED
 
– Tc
 ---------
1
V AP P LI ED  1 – e  = V A PP LIE D  1 – -------------------------- ;combining [1] and [2]
RC
  n+1 
2 –1

Note: Where n = number of bits of the ADC.

Solving for TC:

T C = – C HOLD  R IC + R SS + R S  ln(1/2047)
= – 12.5pF  1k  + 7k  + 10k   ln(0.0004885)
= 1.12 µs
Therefore:
T A CQ = 2µs + 1.12 µs +   50°C- 25°C   0.05 µs/°C  
= 4.37µs

Note 1: The reference voltage (VRPOS) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.

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 PIC16(L)F1508/9
FIGURE 15-4: ANALOG INPUT MODEL
Rev. 10-000070A
8/2/2013

VDD
Sampling
Analog switch
VT § 0.6V SS
RS Input pin RIC ” 1K RSS

ILEAKAGE(1) CHOLD = 10 pF
VA CPIN VT § 0.6V
5pF
Ref-

6V
Legend: CHOLD = Sample/Hold Capacitance 5V
CPIN = Input Capacitance VDD 4V RSS
3V
ILEAKAGE = Leakage Current at the pin due to varies injunctions 2V
RIC = Interconnect Resistance
RSS = Resistance of Sampling switch
SS = Sampling Switch 5 6 7 8 9 10 11
VT = Threshold Voltage Sampling Switch
(kŸ )

Note 1: Refer to Section 29.0 “Electrical Specifications”.

FIGURE 15-5: ADC TRANSFER FUNCTION

Full-Scale Range

3FFh
3FEh
3FDh
3FCh
ADC Output Code

3FBh

03h
02h
01h
00h
Analog Input Voltage
0.5 LSB 1.5 LSB

Ref- Zero-Scale
Transition Full-Scale
Transition Ref+

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TABLE 15-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

ADCON0 — CHS<4:0> GO/DONE ADON 141

ADCON1 ADFM ADCS<2:0> — — ADPREF<1:0> 142
ADCON2 TRIGSEL<3:0> — — — — 143
ADRESH ADC Result Register High 144, 145
ADRESL ADC Result Register Low 144, 145
ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 113
ANSELB — — ANSB5 ANSB4 — — — — 117
ANSELC ANSC7 ANSC6 — — ANSC3 ANSC2 ANSC1 ANSC0 121
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE — TMR2IE TMR1IE 77
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF — TMR2IF TMR1IF 80
—(1)
TRISA — — TRISA5 TRISA4 TRISA2 TRISA1 TRISA0 112
TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 116
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 120
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 131
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are not
used for ADC module.
Note 1: Unimplemented, read as ‘1’.

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 PIC16(L)F1508/9
16.0 5-BIT DIGITAL-TO-ANALOG The output of the DAC (DACx_output) can be selected
as a reference voltage to the following:
CONVERTER (DAC) MODULE
• Comparator positive input
The Digital-to-Analog Converter supplies a variable
• ADC input channel
voltage reference, ratiometric with the input source,
with 32 selectable output levels. • DACxOUT1 pin
• DACxOUT2 pin
The positive input source (VSOURCE+) of the DAC can
be connected to: The Digital-to-Analog Converter (DAC) can be enabled
by setting the DACEN bit of the DACxCON0 register.
• External VREF+ pin
• VDD supply voltage
The negative input source (VSOURCE-) of the DAC can
be connected to:
• Vss

FIGURE 16-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM

Rev. 10-000026A
7/30/2013

VDD 0 VSOURCE+
VREF+ 1 DACR<4:0>
5
R

DACPSS R

DACEN R

R
32-to-1 MUX

32 DACx_output
To Peripherals
Steps

R DACxOUT1 (1)

DACOE1
R
DACxOUT2 (1)

VSOURCE- DACOE2
VSS

Note 1: The unbuffered DACx_output is provided on the DACxOUT pin(s).

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16.1 Output Voltage Selection Reading the DACxOUTn pin when it has been
configured for DAC reference voltage output will
The DAC has 32 voltage level ranges. The 32 levels always return a ‘0’.
are set with the DACR<4:0> bits of the DACxCON1
register. Note: The unbuffered DAC output (DACxOUTn)
is not intended to drive an external load.
The DAC output voltage can be determined by using
Equation 16-1.
16.4 Operation During Sleep
16.2 Ratiometric Output Level When the device wakes up from Sleep through an
The DAC output value is derived using a resistor ladder interrupt or a Watchdog Timer time-out, the contents of
with each end of the ladder tied to a positive and the DACxCON0 register are not affected. To minimize
negative voltage reference input source. If the voltage current consumption in Sleep mode, the voltage
of either input source fluctuates, a similar fluctuation will reference should be disabled.
result in the DAC output value.
16.5 Effects of a Reset
The value of the individual resistors within the ladder
can be found in Table 29-16. A device Reset affects the following:
• DACx is disabled.
16.3 DAC Voltage Reference Output • DACX output voltage is removed from the
The unbuffered DAC voltage can be output to the DACxOUTn pin(s).
DACxOUTn pin(s) by setting the respective DACOEn • The DACR<4:0> range select bits are cleared.
bit(s) of the DACxCON0 register. Selecting the DAC
reference voltage for output on either DACxOUTn pin
automatically overrides the digital output buffer, the
weak pull-up and digital input threshold detector
functions of that pin.

EQUATION 16-1: DAC OUTPUT VOLTAGE

IF DACEN = 1

DACR  4:0 
DACx_output =   VSOURCE+ – VSOURCE-   ----------------------------- + VSOURCE-
 5 
2

Note: See the DACxCON0 register for the available VSOURCE+ and VSOURCE- selections.

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16.6 Register Definitions: DAC Control

REGISTER 16-1: DACxCON0: VOLTAGE REFERENCE CONTROL REGISTER 0

R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 U-0 U-0
DACEN — DACOE1 DACOE2 — DACPSS — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 DACEN: DAC Enable bit

1 = DACx is enabled
0 = DACx is disabled
bit 6 Unimplemented: Read as ‘0’
bit 5 DACOE1: DAC Voltage Output Enable bit
1 = DACx voltage level is output on the DACxOUT1 pin
0 = DACx voltage level is disconnected from the DACxOUT1 pin
bit 4 DACOE2: DAC Voltage Output Enable bit
1 = DACx voltage level is output on the DACxOUT2 pin
0 = DACx voltage level is disconnected from the DACxOUT2 pin
bit 3 Unimplemented: Read as ‘0’
bit 2 DACPSS: DAC Positive Source Select bit
1= VREF+ pin
0= VDD
bit 1-0 Unimplemented: Read as ‘0’

REGISTER 16-2: DACxCON1: VOLTAGE REFERENCE CONTROL REGISTER 1

U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — DACR<4:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 DACR<4:0>: DAC Voltage Output Select bits

TABLE 16-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on page
DAC1CON0 DACEN — DACOE1 DACOE2 — DACPSS — — 151
DAC1CON1 — — — DACR<4:0> 151
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used with the DAC module.

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NOTES:

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 PIC16(L)F1508/9
17.0 COMPARATOR MODULE 17.1 Comparator Overview
Comparators are used to interface analog circuits to a A single comparator is shown in Figure 17-2 along with
digital circuit by comparing two analog voltages and the relationship between the analog input levels and
providing a digital indication of their relative magnitudes. the digital output. When the analog voltage at VIN+ is
Comparators are very useful mixed signal building less than the analog voltage at VIN-, the output of the
blocks because they provide analog functionality comparator is a digital low level. When the analog
independent of program execution. The analog voltage at VIN+ is greater than the analog voltage at
comparator module includes the following features: VIN-, the output of the comparator is a digital high level.
• Independent comparator control The comparators available for this device are listed in
• Programmable input selection Table 17-1.
• Comparator output is available internally/externally
• Programmable output polarity TABLE 17-1: AVAILABLE COMPARATORS
• Interrupt-on-change Device C1 C2
• Wake-up from Sleep
PIC16(L)F1509 ● ●
• Programmable Speed/Power optimization
PIC16(L)F1508 ● ●
• PWM shutdown
• Programmable and fixed voltage reference

FIGURE 17-1: COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM

Rev. 10-000027A
8/5/2013

CxINTP
CxNCH<2:0> 3 CxON(1) Interrupt
Rising
CxIN0- 000 Edge set bit
CxIF
CxIN1- 001 Interrupt CxINTN

CxIN2- 010 Falling

CxON(1) Edge
CxIN3- 011
CxVN
FVR_buffer2 100 - D Q
CxOUT
MCxOUT
Cx
CxVP
CxIN+ 00 + Q1
DAC_out 01

FVR_buffer2 10 CxSP CxHYS CxPOL CxOUT_async to

peripherals
11
CxOUT_sync to
CxPCH<1:0> CxON(1)
2 peripherals
CxSYNC
CxOE
TRIS bit
0
CxOUT
D Q 1

(From Timer1 Module) T1CLK

Note 1: When CxON = 0, all multiplexer inputs are disconnected and the Comparator will produce a ‘0’ at the output.

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FIGURE 17-2: SINGLE COMPARATOR • CxIN+ analog pin
• DAC1_output
VIN+ • FVR_buffer2
+
Output • VSS
VIN- –
See Section 13.0 “Fixed Voltage Reference (FVR)”
for more information on the Fixed Voltage Reference
module.
See Section 16.0 “5-Bit Digital-to-Analog Converter
VIN- (DAC) Module” for more information on the DAC input
VIN+ signal.
Any time the comparator is disabled (CxON = 0), all
comparator inputs are disabled.

Output 17.2.3 COMPARATOR NEGATIVE INPUT

SELECTION
The CxNCH<2:0> bits of the CMxCON0 register direct
Note: The black areas of the output of the one of the input sources to the comparator inverting
comparator represents the uncertainty input.
due to input offsets and response time. Note: To use CxIN+ and CxINx- pins as analog
input, the appropriate bits must be set in
the ANSEL register and the correspond-
17.2 Comparator Control ing TRIS bits must also be set to disable
the output drivers.
Each comparator has two control registers: CMxCON0
and CMxCON1.
17.2.4 COMPARATOR OUTPUT
The CMxCON0 registers (see Register 17-1) contain SELECTION
Control and Status bits for the following:
The output of the comparator can be monitored by
• Enable reading either the CxOUT bit of the CMxCON0 register
• Output selection or the MCxOUT bit of the CMOUT register. In order to
• Output polarity make the output available for an external connection,
• Speed/Power selection the following conditions must be true:
• Hysteresis enable • CxOE bit of the CMxCON0 register must be set
• Output synchronization • Corresponding TRIS bit must be cleared
The CMxCON1 registers (see Register 17-2) contain • CxON bit of the CMxCON0 register must be set
Control bits for the following: The synchronous comparator output signal
• Interrupt enable (CxOUT_sync) is available to the following peripheral(s):
• Interrupt edge polarity • Configurable Logic Cell (CLC)
• Positive input channel selection • Analog-to-Digital Converter (ADC)
• Negative input channel selection • Timer1
The asynchronous comparator output signal
17.2.1 COMPARATOR ENABLE (CxOUT_async) is available to the following peripheral(s):
Setting the CxON bit of the CMxCON0 register enables • Complementary Waveform Generator (CWG)
the comparator for operation. Clearing the CxON bit
disables the comparator resulting in minimum current
consumption. Note 1: The CxOE bit of the CMxCON0 register
overrides the PORT data latch. Setting
17.2.2 COMPARATOR POSITIVE INPUT the CxON bit of the CMxCON0 register
SELECTION has no impact on the port override.
Configuring the CxPCH<1:0> bits of the CMxCON1 2: The internal output of the comparator is
register directs an internal voltage reference or an latched with each instruction cycle.
analog pin to the non-inverting input of the comparator: Unless otherwise specified, external
outputs are not latched.

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17.2.5 COMPARATOR OUTPUT POLARITY 17.3 Analog Input Connection
Inverting the output of the comparator is functionally Considerations
equivalent to swapping the comparator inputs. The
A simplified circuit for an analog input is shown in
polarity of the comparator output can be inverted by
Figure 17-4. Since the analog input pins share their
setting the CxPOL bit of the CMxCON0 register.
connection with a digital input, they have reverse
Clearing the CxPOL bit results in a non-inverted output.
biased ESD protection diodes to VDD and VSS. The
Table 17-2 shows the output state versus input analog input, therefore, must be between VSS and VDD.
conditions, including polarity control. If the input voltage deviates from this range by more
TABLE 17-2: COMPARATOR OUTPUT than 0.6V in either direction, one of the diodes is for-
STATE VS. INPUT CONDITIONS ward biased and a latch-up may occur.

Input Condition CxPOL CxOUT A maximum source impedance of 10 k is recommended

for the analog sources. Also, any external component
CxVN > CxVP 0 0 connected to an analog input pin, such as a capacitor or
CxVN < CxVP 0 1 a Zener diode, should have very little leakage current to
CxVN > CxVP 1 1 minimize inaccuracies introduced.
CxVN < CxVP 1 0
Note 1: When reading a PORT register, all pins
17.2.6 COMPARATOR SPEED/POWER configured as analog inputs will read as a
SELECTION ‘0’. Pins configured as digital inputs will
The trade-off between speed or power can be opti- convert as an analog input, according to
mized during program execution with the CxSP control the input specification.
bit. The default state for this bit is ‘1’ which selects the 2: Analog levels on any pin defined as a
Normal-Speed mode. Device power consumption can digital input, may cause the input buffer to
be optimized at the cost of slower comparator propaga- consume more current than is specified.
tion delay by clearing the CxSP bit to ‘0’.

FIGURE 17-3: ANALOG INPUT MODEL

Rev. 10-000071A
8/2/2013

VDD
Analog
VT § 0.6V
RS < 10K Input pin RIC
To Comparator
ILEAKAGE(1)
VA CPIN VT § 0.6V
5pF

VSS

Legend: CPIN = Input Capacitance

ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS = Source Impedance
VA = Analog Voltage
VT = Threshold Voltage

Note 1: See Section 29.0 “Electrical Specifications”.

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FIGURE 17-4: ANALOG INPUT MODEL
VDD
Analog
Input
pin VT  0.6V RIC
Rs < 10K
To Comparator

CPIN ILEAKAGE(1)
VA VT  0.6V
5 pF

Vss

Legend: CPIN = Input Capacitance

ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS = Source Impedance
VA = Analog Voltage
VT = Threshold Voltage

Note 1: See Section 29.0 “Electrical Specifications”.

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17.4 Comparator Hysteresis The associated interrupt flag bit, CxIF bit of the PIR2
register, must be cleared in software. If another edge is
A selectable amount of separation voltage can be detected while this flag is being cleared, the flag will still
added to the input pins of each comparator to provide a be set at the end of the sequence.
hysteresis function to the overall operation. Hysteresis
is enabled by setting the CxHYS bit of the CMxCON0 Note: Although a comparator is disabled, an
register. interrupt can be generated by changing
the output polarity with the CxPOL bit of
See Section 29.0 “Electrical Specifications” for
the CMxCON0 register, or by switching
more information.
the comparator on or off with the CxON bit
of the CMxCON0 register.
17.5 Timer1 Gate Operation
The output resulting from a comparator operation can 17.7 Comparator Response Time
be used as a source for gate control of Timer1. See
Section 19.6 “Timer1 Gate” for more information. The comparator output is indeterminate for a period of
This feature is useful for timing the duration or interval time after the change of an input source or the selection
of an analog event. of a new reference voltage. This period is referred to as
the response time. The response time of the comparator
It is recommended that the comparator output be syn- differs from the settling time of the voltage reference.
chronized to Timer1. This ensures that Timer1 does not Therefore, both of these times must be considered when
increment while a change in the comparator is occur- determining the total response time to a comparator
ring. input change. See the Comparator and Voltage Refer-
ence Specifications in Section 29.0 “Electrical Specifi-
17.5.1 COMPARATOR OUTPUT cations” for more details.
SYNCHRONIZATION
The output from the Cx comparator can be
synchronized with Timer1 by setting the CxSYNC bit of
the CMxCON0 register.
Once enabled, the comparator output is latched on the
falling edge of the Timer1 source clock. If a prescaler is
used with Timer1, the comparator output is latched after
the prescaling function. To prevent a race condition, the
comparator output is latched on the falling edge of the
Timer1 clock source and Timer1 increments on the
rising edge of its clock source. See the Comparator
Block Diagram (Figure 17-2) and the Timer1 Block
Diagram (Figure 19-1) for more information.

17.6 Comparator Interrupt

An interrupt can be generated upon a change in the
output value of the comparator for each comparator, a
rising edge detector and a falling edge detector are
present.
When either edge detector is triggered and its associ-
ated enable bit is set (CxINTP and/or CxINTN bits of
the CMxCON1 register), the Corresponding Interrupt
Flag bit (CxIF bit of the PIR2 register) will be set.
To enable the interrupt, you must set the following bits:
• CxON, CxPOL and CxSP bits of the CMxCON0
register
• CxIE bit of the PIE2 register
• CxINTP bit of the CMxCON1 register (for a rising
edge detection)
• CxINTN bit of the CMxCON1 register (for a falling
edge detection)
• PEIE and GIE bits of the INTCON register

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17.8 Register Definitions: Comparator Control

REGISTER 17-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0

R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 U-0 R/W-1/1 R/W-0/0 R/W-0/0
CxON CxOUT CxOE CxPOL — CxSP CxHYS CxSYNC
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 CxON: Comparator Enable bit

1 = Comparator is enabled
0 = Comparator is disabled and consumes no active power
bit 6 CxOUT: Comparator Output bit
If CxPOL = 1 (inverted polarity):
1 = CxVP < CxVN
0 = CxVP > CxVN
If CxPOL = 0 (non-inverted polarity):
1 = CxVP > CxVN
0 = CxVP < CxVN
bit 5 CxOE: Comparator Output Enable bit
1 = CxOUT is present on the CxOUT pin. Requires that the associated TRIS bit be cleared to actually
drive the pin. Not affected by CxON.
0 = CxOUT is internal only
bit 4 CxPOL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 3 Unimplemented: Read as ‘0’
bit 2 CxSP: Comparator Speed/Power Select bit
1 = Comparator mode in normal-power, higher speed
0 = Comparator mode in low-power, low-speed
bit 1 CxHYS: Comparator Hysteresis Enable bit
1 = Comparator hysteresis enabled
0 = Comparator hysteresis disabled
bit 0 CxSYNC: Comparator Output Synchronous Mode bit
1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source.
Output updated on the falling edge of Timer1 clock source.
0 = Comparator output to Timer1 and I/O pin is asynchronous

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REGISTER 17-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
CxINTP CxINTN CxPCH<1:0> — CxNCH<2:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits

1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit
0 = No interrupt flag will be set on a positive going edge of the CxOUT bit
bit 6 CxINTN: Comparator Interrupt on Negative Going Edge Enable bits
1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit
0 = No interrupt flag will be set on a negative going edge of the CxOUT bit
bit 5-4 CxPCH<1:0>: Comparator Positive Input Channel Select bits
11 = CxVP connects to VSS
10 = CxVP connects to FVR Voltage Reference
01 = CxVP connects to DAC Voltage Reference
00 = CxVP connects to CxIN+ pin
bit 3 Unimplemented: Read as ‘0’
bit 2-0 CxNCH<2:0>: Comparator Negative Input Channel Select bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = CxVN connects to FVR Voltage reference
011 = CxVN connects to CxIN3- pin
010 = CxVN connects to CxIN2- pin
001 = CxVN connects to CxIN1- pin
000 = CxVN connects to CxIN0- pin

REGISTER 17-3: CMOUT: COMPARATOR OUTPUT REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R-0/0 R-0/0
— — — — — — MC2OUT MC1OUT
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-2 Unimplemented: Read as ‘0’

bit 1 MC2OUT: Mirror Copy of C2OUT bit
bit 0 MC1OUT: Mirror Copy of C1OUT bit

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TABLE 17-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 113
ANSELC ANSC7 ANSC6 — — ANSC3 ANSC2 ANSC1 ANSC0 121
CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 158
CM2CON0 C2ON C2OUT C2OE C2POL — C2SP C2HYS C2SYNC 158
CM1CON1 C1NTP C1INTN C1PCH<1:0> — C1NCH<2:0> 159
CM2CON1 C2NTP C2INTN C2PCH<1:0> — C2NCH<2:0> 159
CMOUT — — — — — — MC2OUT MC1OUT 159
DAC1CON0 DACEN — DACOE1 DACOE2 — DACPSS — — 151
DAC1CON1 — — — DACR<4:0> 151
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 131
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76
PIE2 OSFIE C2IE C1IE — BCL1IE NCO1IE — — 78
PIR2 OSFIF C2IF C1IF — BCL1IF NCO1IF — — 81
PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 112
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 120
LATA — — LATA5 LATA4 — LATA2 LATA1 LATA0 113
LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 120
TRISA — — TRISA5 TRISA4 —(1) TRISA2 TRISA1 TRISA0 112
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 120
Legend: — = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module.
Note 1: Unimplemented, read as ‘1’.

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18.0 TIMER0 MODULE 18.1.2 8-BIT COUNTER MODE
The Timer0 module is an 8-bit timer/counter with the In 8-Bit Counter mode, the Timer0 module will
following features: increment on every rising or falling edge of the T0CKI
pin.
• 8-bit timer/counter register (TMR0)
8-Bit Counter mode using the T0CKI pin is selected by
• 3-bit prescaler (independent of Watchdog Timer)
setting the TMR0CS bit in the OPTION_REG register to
• Programmable internal or external clock source ‘1’.
• Programmable external clock edge selection
The rising or falling transition of the incrementing edge
• Interrupt on overflow for either input source is determined by the TMR0SE bit
• TMR0 can be used to gate Timer1 in the OPTION_REG register.
Figure 18-1 is a block diagram of the Timer0 module.

18.1 Timer0 Operation

The Timer0 module can be used as either an 8-bit timer
or an 8-bit counter.

18.1.1 8-BIT TIMER MODE

The Timer0 module will increment every instruction
cycle, if used without a prescaler. 8-bit Timer mode is
selected by clearing the TMR0CS bit of the
OPTION_REG register.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
Note: The value written to the TMR0 register
can be adjusted, in order to account for
the two instruction cycle delay when
TMR0 is written.

FIGURE 18-1: TIMER0 BLOCK DIAGRAM

Rev. 10-000017A

TMR0CS 8/5/2013

Fosc/4 PSA

T0CKI(1) 0 T0_overflow
1 T0CKI
TMR0
1 Prescaler 0 FOSC/2 Sync Circuit Q1
write R
to
TMR0
TMR0SE set bit
PS<2:0>
TMR0IF

Note 1: The T0CKI prescale output frequency should not exceed FOSC/8.

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18.1.3 SOFTWARE PROGRAMMABLE
PRESCALER
A software programmable prescaler is available for
exclusive use with Timer0. The prescaler is enabled by
clearing the PSA bit of the OPTION_REG register.
Note: The Watchdog Timer (WDT) uses its own
independent prescaler.
There are 8 prescaler options for the Timer0 module
ranging from 1:2 to 1:256. The prescale values are
selectable via the PS<2:0> bits of the OPTION_REG
register. In order to have a 1:1 prescaler value for the
Timer0 module, the prescaler must be disabled by set-
ting the PSA bit of the OPTION_REG register.
The prescaler is not readable or writable. All instructions
writing to the TMR0 register will clear the prescaler.

18.1.4 TIMER0 INTERRUPT

Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The TMR0IF
interrupt flag bit of the INTCON register is set every
time the TMR0 register overflows, regardless of
whether or not the Timer0 interrupt is enabled. The
TMR0IF bit can only be cleared in software. The
Timer0 interrupt enable is the TMR0IE bit of the
INTCON register.
Note: The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.

18.1.5 8-BIT COUNTER MODE

SYNCHRONIZATION
When in 8-Bit Counter mode, the incrementing edge on
the T0CKI pin must be synchronized to the instruction
clock. Synchronization can be accomplished by
sampling the prescaler output on the Q2 and Q4 cycles
of the instruction clock. The high and low periods of the
external clocking source must meet the timing
requirements as shown in Section 29.0 “Electrical
Specifications”.

18.1.6 OPERATION DURING SLEEP

Timer0 cannot operate while the processor is in Sleep
mode. The contents of the TMR0 register will remain
unchanged while the processor is in Sleep mode.

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18.2 Register Definitions: Option Register

REGISTER 18-1: OPTION_REG: OPTION REGISTER

R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 WPUEN: Weak Pull-Up Enable bit

1 = All weak pull-ups are disabled (except MCLR, if it is enabled)
0 = Weak pull-ups are enabled by individual WPUx latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5 TMR0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4 TMR0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is not assigned to the Timer0 module
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Bit Value Timer0 Rate

000 1:2
001 1:4
010 1:8
011 1 : 16
100 1 : 32
101 1 : 64
110 1 : 128
111 1 : 256

TABLE 18-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
ADCON2 TRIGSEL<3:0> — — — — 143
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 163
TMR0 Holding Register for the 8-bit Timer0 Count 161*
TRISA — — TRISA5 TRISA4 —(1) TRISA2 TRISA1 TRISA0 112
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module.
* Page provides register information.
Note 1: Unimplemented, read as ‘1’.

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19.0 TIMER1 MODULE WITH GATE • Wake-up on overflow (external clock,
Asynchronous mode only)
CONTROL
• ADC Auto-Conversion Trigger(s)
The Timer1 module is a 16-bit timer/counter with the • Selectable Gate Source Polarity
following features:
• Gate Toggle mode
• 16-bit timer/counter register pair (TMR1H:TMR1L) • Gate Single-Pulse mode
• Programmable internal or external clock source • Gate Value Status
• 2-bit prescaler • Gate Event Interrupt
• Optionally synchronized comparator out
Figure 19-1 is a block diagram of the Timer1 module.
• Multiple Timer1 gate (count enable) sources
• Interrupt on overflow

FIGURE 19-1: ( TIMER1

) (BLOCK
) DIAGRAM

T1GSS<1:0> Rev. 10-000018A

8/5/2013

T1GSPM
T1G 00
T0_overflow 01
1
C1OUT_sync 10 0 Single Pulse D Q T1GVAL
0
C2OUT_sync 11 1 Acq. Control
Q1
D Q

T1GPOL T1GGO/DONE
CK Q
TMR1ON Interrupt
set bit
R
T1GTM det TMR1GIF

TMR1GE
set flag bit
TMR1IF
TMR1ON
EN
(2)
TMR1
T1_overflow Synchronized Clock Input
TMR1H TMR1L Q D 0
1
T1CLK
T1SYNC

TMR1CS<1:0>
OUT
SOSCI/T1CKI

Secondary LFINTOSC 11
Oscillator 1
SOSCO 10 Prescaler
0 Fosc Synchronize(3)
01 1,2,4,8
Internal Clock det
EN
00
2
Fosc/4 Fosc/2
T1OSCEN Internal Clock T1CKPS<1:0> Internal Sleep
Clock Input
(1)
Secondary Clock To Clock Switching
Module

Note 1: ST Buffer is high speed type when using T1CKI.

2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.

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19.1 Timer1 Operation 19.2 Clock Source Selection
The Timer1 module is a 16-bit incrementing counter The TMR1CS<1:0> and T1OSCEN bits of the T1CON
which is accessed through the TMR1H:TMR1L register register are used to select the clock source for Timer1.
pair. Writes to TMR1H or TMR1L directly update the Table 19-2 displays the clock source selections.
counter.
19.2.1 INTERNAL CLOCK SOURCE
When used with an internal clock source, the module is
a timer and increments on every instruction cycle. When the internal clock source is selected, the
When used with an external clock source, the module TMR1H:TMR1L register pair will increment on multiples
can be used as either a timer or counter and incre- of FOSC as determined by the Timer1 prescaler.
ments on every selected edge of the external source. When the FOSC internal clock source is selected, the
Timer1 is enabled by configuring the TMR1ON and Timer1 register value will increment by four counts every
TMR1GE bits in the T1CON and T1GCON registers, instruction clock cycle. Due to this condition, a 2 LSB
respectively. Table 19-1 displays the Timer1 enable error in resolution will occur when reading the Timer1
selections. value. To utilize the full resolution of Timer1, an
asynchronous input signal must be used to gate the
Timer1 clock input.
TABLE 19-1: TIMER1 ENABLE
The following asynchronous sources may be used:
SELECTIONS
• Asynchronous event on the T1G pin to Timer1
Timer1
TMR1ON TMR1GE gate
Operation
• C1 or C2 comparator input to Timer1 gate
0 0 Off
0 1 Off 19.2.2 EXTERNAL CLOCK SOURCE
1 0 Always On When the external clock source is selected, the Timer1
1 1 Count Enabled module may work as a timer or a counter.
When enabled to count, Timer1 is incremented on the
rising edge of the external clock input T1CKI. The
external clock source can be synchronized to the
microcontroller system clock or it can run
asynchronously.

Note: In Counter mode, a falling edge must be

registered by the counter prior to the first
incrementing rising edge after any one or
more of the following conditions:
• Timer1 enabled after POR
• Write to TMR1H or TMR1L
• Timer1 is disabled
• Timer1 is disabled (TMR1ON = 0)
when T1CKI is high then Timer1 is
enabled (TMR1ON=1) when T1CKI is
low.

TABLE 19-2: CLOCK SOURCE SELECTIONS

TMR1CS<1:0> T1OSCEN Clock Source
11 x LFINTOSC
1 Secondary Oscillator Circuit on SOSCI/SOSCO Pins
10
0 External Clocking on T1CKI Pin
01 x System Clock (FOSC)
00 x Instruction Clock (FOSC/4)

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19.3 Timer1 Prescaler For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
Timer1 has four prescaler options allowing 1, 2, 4 or 8 contention may occur by writing to the timer registers,
divisions of the clock input. The T1CKPS bits of the while the register is incrementing. This may produce an
T1CON register control the prescale counter. The unpredictable value in the TMR1H:TMR1L register
prescale counter is not directly readable or writable; pair.
however, the prescaler counter is cleared upon a write to
TMR1H or TMR1L.
19.6 Timer1 Gate
19.4 Timer1 (Secondary) Oscillator Timer1 can be configured to count freely or the count
can be enabled and disabled using Timer1 gate
A dedicated low-power 32.768 kHz oscillator circuit is circuitry. This is also referred to as Timer1 Gate Enable.
built-in between pins S1OSI (input) and S1OSO (ampli-
fier output). This internal circuit is to be used in con- Timer1 gate can also be driven by multiple selectable
junction with an external 32.768 kHz crystal. The sources.
oscillator circuit is enabled by setting the T1OSCEN bit
19.6.1 TIMER1 GATE ENABLE
of the T1CON register. The oscillator will continue to
run during Sleep. The Timer1 Gate Enable mode is enabled by setting
the TMR1GE bit of the T1GCON register. The polarity
Note: The oscillator requires some time to start-up of the Timer1 Gate Enable mode is configured using
and stabilize before use. The SOSCR bit in the T1GPOL bit of the T1GCON register.
the OSCSTAT register monitors the
oscillator and indicates when the oscillator is When Timer1 Gate Enable mode is enabled, Timer1
ready for use. When T1OSCEN is set, the will increment on the rising edge of the Timer1 clock
SOSCR bit is cleared. After 1024 cycles of source. When Timer1 Gate Enable mode is disabled,
the oscillator are countered, the SOSCR bit no incrementing will occur and Timer1 will hold the
is set, indicating that the oscillator should be current count. See Figure 19-3 for timing details.
stable and ready for use.
TABLE 19-3: TIMER1 GATE ENABLE
19.5 Timer1 Operation in SELECTIONS
Asynchronous Counter Mode T1CLK T1GPOL T1G Timer1 Operation
If control bit T1SYNC of the T1CON register is set, the  0 0 Counts
external clock input is not synchronized. The timer
 0 1 Holds Count
increments asynchronously to the internal phase
clocks. If the external clock source is selected then the  1 0 Holds Count
timer will continue to run during Sleep and can  1 1 Counts
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in 19.6.2 TIMER1 GATE SOURCE
software are needed to read/write the timer (see SELECTION
Section 19.5.1 “Reading and Writing Timer1 in
Timer1 gate source selections are shown in Table 19-4.
Asynchronous Counter Mode”).
Source selection is controlled by the T1GSS<1:0> bits
Note: When switching from synchronous to of the T1GCON register. The polarity for each available
asynchronous operation, it is possible to source is also selectable. Polarity selection is controlled
skip an increment. When switching from by the T1GPOL bit of the T1GCON register.
asynchronous to synchronous operation,
it is possible to produce an additional TABLE 19-4: TIMER1 GATE SOURCES
increment.
T1GSS Timer1 Gate Source

19.5.1 READING AND WRITING TIMER1 IN 00 Timer1 Gate pin (T1G)

ASYNCHRONOUS COUNTER 01 Overflow of Timer0 (T0_overflow)
MODE (TMR0 increments from FFh to 00h)
Reading TMR1H or TMR1L while the timer is running 10 Comparator 1 Output (C1OUT_sync)(1)
from an external asynchronous clock will ensure a valid 11 Comparator 2 Output (C2OUT_sync)(1)
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two Note 1: Optionally synchronized comparator output.
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.

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19.6.2.1 T1G Pin Gate Operation 19.6.5 TIMER1 GATE VALUE STATUS
The T1G pin is one source for Timer1 gate control. It When Timer1 Gate Value Status is utilized, it is possi-
can be used to supply an external source to the Timer1 ble to read the most current level of the gate control
gate circuitry. value. The value is stored in the T1GVAL bit in the
T1GCON register. The T1GVAL bit is valid even when
19.6.2.2 Timer0 Overflow Gate Operation the Timer1 gate is not enabled (TMR1GE bit is
When Timer0 increments from FFh to 00h, a low-to- cleared).
high pulse will automatically be generated and inter-
nally supplied to the Timer1 gate circuitry. 19.6.6 TIMER1 GATE EVENT INTERRUPT
When Timer1 Gate Event Interrupt is enabled, it is pos-
19.6.3 TIMER1 GATE TOGGLE MODE sible to generate an interrupt upon the completion of a
When Timer1 Gate Toggle mode is enabled, it is pos- gate event. When the falling edge of T1GVAL occurs,
sible to measure the full-cycle length of a Timer1 gate the TMR1GIF flag bit in the PIR1 register will be set. If
signal, as opposed to the duration of a single level the TMR1GIE bit in the PIE1 register is set, then an
pulse. interrupt will be recognized.

The Timer1 gate source is routed through a flip-flop The TMR1GIF flag bit operates even when the Timer1
that changes state on every incrementing edge of the gate is not enabled (TMR1GE bit is cleared).
signal. See Figure 19-4 for timing details.
Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
Note: Enabling Toggle mode at the same time
as changing the gate polarity may result in
indeterminate operation.

19.6.4 TIMER1 GATE SINGLE-PULSE

MODE
When Timer1 Gate Single-Pulse mode is enabled, it is
possible to capture a single pulse gate event. Timer1
Gate Single-Pulse mode is first enabled by setting the
T1GSPM bit in the T1GCON register. Next, the T1GGO/
DONE bit in the T1GCON register must be set. The
Timer1 will be fully enabled on the next incrementing
edge. On the next trailing edge of the pulse, the T1GGO/
DONE bit will automatically be cleared. No other gate
events will be allowed to increment Timer1 until the
T1GGO/DONE bit is once again set in software. See
Figure 19-5 for timing details.
If the Single Pulse Gate mode is disabled by clearing the
T1GSPM bit in the T1GCON register, the T1GGO/DONE
bit should also be cleared.
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the cycle times on the Timer1
gate source to be measured. See Figure 19-6 for timing
details.

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19.7 Timer1 Interrupt 19.8.1 ALTERNATE PIN LOCATIONS
The Timer1 register pair (TMR1H:TMR1L) increments This module incorporates I/O pins that can be moved to
to FFFFh and rolls over to 0000h. When Timer1 rolls other locations with the use of the alternate pin function
over, the Timer1 interrupt flag bit of the PIR1 register is register, APFCON. To determine which pins can be
set. To enable the interrupt on rollover, you must set moved and what their default locations are upon a
these bits: Reset, see Section 11.1 “Alternate Pin Function” for
more information.
• TMR1ON bit of the T1CON register
• TMR1IE bit of the PIE1 register
• PEIE bit of the INTCON register
• GIE bit of the INTCON register
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
Note: The TMR1H:TMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.

19.8 Timer1 Operation During Sleep

Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:
• TMR1ON bit of the T1CON register must be set
• TMR1IE bit of the PIE1 register must be set
• PEIE bit of the INTCON register must be set
• T1SYNC bit of the T1CON register must be set
• TMR1CS bits of the T1CON register must be
configured
• T1OSCEN bit of the T1CON register must be
configured
The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine.
Timer1 oscillator will continue to operate in Sleep
regardless of the T1SYNC bit setting.

FIGURE 19-2: TIMER1 INCREMENTING EDGE

T1CKI = 1
when TMR1
Enabled

T1CKI = 0
when TMR1
Enabled

Note 1: Arrows indicate counter increments.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.

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FIGURE 19-3: TIMER1 GATE ENABLE MODE

TMR1GE

T1GPOL

t1g_in

T1CKI

T1GVAL

Timer1 N N+1 N+2 N+3 N+4

FIGURE 19-4: TIMER1 GATE TOGGLE MODE

TMR1GE

T1GPOL

T1GTM

t1g_in

T1CKI

T1GVAL

Timer1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8

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FIGURE 19-5: TIMER1 GATE SINGLE-PULSE MODE

TMR1GE

T1GPOL

T1GSPM
Cleared by hardware on
T1GGO/ Set by software falling edge of T1GVAL
DONE
Counting enabled on
rising edge of T1G
t1g_in

T1CKI

T1GVAL

Timer1 N N+1 N+2

Cleared by
TMR1GIF Cleared by software Set by hardware on software
falling edge of T1GVAL

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FIGURE 19-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE

TMR1GE

T1GPOL

T1GSPM

T1GTM

Cleared by hardware on
T1GGO/ Set by software falling edge of T1GVAL
DONE Counting enabled on
rising edge of T1G
t1g_in

T1CKI

T1GVAL

Timer1 N N+1 N+2 N+3 N+4

Set by hardware on Cleared by

TMR1GIF Cleared by software falling edge of T1GVAL software

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19.9 Register Definitions: Timer1 Control

REGISTER 19-1: T1CON: TIMER1 CONTROL REGISTER

R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u U-0 R/W-0/u
TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 TMR1CS<1:0>: Timer1 Clock Source Select bits

11 = Timer1 clock source is LFINTOSC
10 = Timer1 clock source is pin or oscillator:
If T1OSCEN = 0:
External clock from T1CKI pin (on the rising edge)
If T1OSCEN = 1:
Crystal oscillator on SOSCI/SOSCO pins
01 = Timer1 clock source is system clock (FOSC)
00 = Timer1 clock source is instruction clock (FOSC/4)
bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3 T1OSCEN: LP Oscillator Enable Control bit
1 = Secondary oscillator circuit enabled for Timer1
0 = Secondary oscillator circuit disabled for Timer1
bit 2 T1SYNC: Timer1 Synchronization Control bit
1 = Do not synchronize asynchronous clock input
0 = Synchronize asynchronous clock input with system clock (FOSC)
bit 1 Unimplemented: Read as ‘0’
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1 and clears Timer1 gate flip-flop

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REGISTER 19-2: T1GCON: TIMER1 GATE CONTROL REGISTER

R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x R/W-0/u R/W-0/u
TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0>
DONE
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware

bit 7 TMR1GE: Timer1 Gate Enable bit

If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1 = Timer1 counting is controlled by the Timer1 gate function
0 = Timer1 counts regardless of Timer1 gate function
bit 6 T1GPOL: Timer1 Gate Polarity bit
1 = Timer1 gate is active-high (Timer1 counts when gate is high)
0 = Timer1 gate is active-low (Timer1 counts when gate is low)
bit 5 T1GTM: Timer1 Gate Toggle Mode bit
1 = Timer1 Gate Toggle mode is enabled
0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared
Timer1 gate flip-flop toggles on every rising edge.
bit 4 T1GSPM: Timer1 Gate Single-Pulse Mode bit
1 = Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate
0 = Timer1 gate Single-Pulse mode is disabled
bit 3 T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit
1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge
0 = Timer1 gate single-pulse acquisition has completed or has not been started
bit 2 T1GVAL: Timer1 Gate Value Status bit
Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L.
Unaffected by Timer1 Gate Enable (TMR1GE).
bit 0 T1GSS<1:0>: Timer1 Gate Source Select bits
11 = Comparator 2 optionally synchronized output (C2OUT_sync)
10 = Comparator 1 optionally synchronized output (C1OUT_sync)
01 = Timer0 overflow output (T0_overflow)
00 = Timer1 gate pin (T1G)

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TABLE 19-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 113
APFCON — — — SSSEL T1GSEL — CLC1SEL NCO1SEL 110
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76
OSCSTAT SOSCR — OSTS HFIOFR — — LFIOFR HFIOFS 61
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE — TMR2IE TMR1IE 77
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF — TMR2IF TMR1IF 81
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Count 169*
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Count 169*
(1)
TRISA — — TRISA5 TRISA4 — TRISA2 TRISA1 TRISA0 112
T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 173
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> 174
DONE
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module.
* Page provides register information.
Note 1: Unimplemented, read as ‘1’.

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20.0 TIMER2 MODULE
The Timer2 module incorporates the following features:
• 8-bit Timer and Period registers (TMR2 and PR2,
respectively)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16,
and 1:64)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match with PR2
See Figure 20-1 for a block diagram of Timer2.

FIGURE 20-1: TIMER2 BLOCK DIAGRAM

Rev. 10-000019A
7/30/2013

T2_match
Prescaler To Peripherals
TMR2 R
Fosc/4 1:1, 1:4, 1:16, 1:64

2
Postscaler set bit
T2CKPS<1:0> Comparator
1:1 to 1:16 TMR2IF

PR2 T2OUTPS<3:0>

FIGURE 20-2: TIMER2 TIMING DIAGRAM

Rev. 10-000020A
7/30/2013

FOSC/4

1:4
Prescale

0x03
PR2

0x00 0x01 0x02 0x03 0x00 0x01 0x02

TMR2

T2_match Pulse Width(1)

Note 1: The Pulse Width of T2_match is equal to the scaled input of TMR2.

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PIC16(L)F1508/9
20.1 Timer2 Operation 20.3 Timer2 Output
The clock input to the Timer2 module is the system The output of TMR2 is T2_match. T2_match is available
instruction clock (FOSC/4). to the following peripherals:
TMR2 increments from 00h on each clock edge. • Configurable Logic Cell (CLC)
A 4-bit counter/prescaler on the clock input allows direct • Master Synchronous Serial Port (MSSP)
input, divide-by-4 and divide-by-16 prescale options. • Numerically Controlled Oscillator (NCO)
These options are selected by the prescaler control bits, • Pulse Width Modulator (PWM)
T2CKPS<1:0> of the T2CON register. The value of
The T2_match signal is synchronous with the system
TMR2 is compared to that of the Period register, PR2, on
clock. Figure 20-3 shows two examples of the timing of
each clock cycle. When the two values match, the
the T2_match signal relative to FOSC and prescale
comparator generates a match signal as the timer
value, T2CKPS<1:0>. The upper diagram illustrates 1:1
output. This signal also resets the value of TMR2 to 00h
prescale timing and the lower diagram, 1:X prescale
on the next cycle and drives the output counter/
timing.
postscaler (see Section 20.2 “Timer2 Interrupt”).
The TMR2 and PR2 registers are both directly readable FIGURE 20-3: T2_MATCH TIMING
and writable. The TMR2 register is cleared on any
DIAGRAM
device Reset, whereas the PR2 register initializes to
FFh. Both the prescaler and postscaler counters are Rev. 10-000021A
7/30/2013

cleared on the following events:

• a write to the TMR2 register Q1 Q2 Q3 Q4 Q1
• a write to the T2CON register FOSC
• Power-On Reset (POR) TCY1
• Brown-Out Reset (BOR)
FOSC/4
• MCLR Reset
• Watchdog Timer (WDT) Reset T2_match TMR2 = PR2 TMR2 = 0
match
• Stack Overflow Reset
PRESCALE = 1:1
• Stack Underflow Reset
(T2CKPS<1:0> = 00)
• RESET Instruction
Note: TMR2 is not cleared when T2CON is TCY1 TCY2 ... TCYX
written.
FOSC/4 ...

20.2 Timer2 Interrupt T2_match TMR2 = PR2

...
TMR2 = 0
match
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (T2_match) provides the input PRESCALE = 1:X
for the 4-bit counter/postscaler. This counter generates (T2CKPS<1:0> = 01,10,11)
the TMR2 match interrupt flag which is latched in
TMR2IF of the PIR1 register. The interrupt is enabled by
setting the TMR2 Match Interrupt Enable bit, TMR2IE of 20.4 Timer2 Operation During Sleep
the PIE1 register.
A range of 16 postscale options (from 1:1 through 1:16 Timer2 cannot be operated while the processor is in
inclusive) can be selected with the postscaler control Sleep mode. The contents of the TMR2 and PR2
bits, T2OUTPS<3:0>, of the T2CON register. registers will remain unchanged while the processor is
in Sleep mode.

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 PIC16(L)F1508/9
20.5 Register Definitions: Timer2 Control

REGISTER 20-1: T2CON: TIMER2 CONTROL REGISTER

U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— T2OUTPS<3:0> TMR2ON T2CKPS<1:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 Unimplemented: Read as ‘0’

bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscaler Select bits
0000 = 1:1 Postscaler
0001 = 1:2 Postscaler
0010 = 1:3 Postscaler
0011 = 1:4 Postscaler
0100 = 1:5 Postscaler
0101 = 1:6 Postscaler
0110 = 1:7 Postscaler
0111 = 1:8 Postscaler
1000 = 1:9 Postscaler
1001 = 1:10 Postscaler
1010 = 1:11 Postscaler
1011 = 1:12 Postscaler
1100 = 1:13 Postscaler
1101 = 1:14 Postscaler
1110 = 1:15 Postscaler
1111 = 1:16 Postscaler
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
10 = Prescaler is 16
11 = Prescaler is 64

TABLE 20-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE — TMR2IE TMR1IE 77
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF — TMR2IF TMR1IF 80
PR2 Timer2 Module Period Register 177*
T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 179
TMR2 Holding Register for the 8-bit TMR2 Count 177*
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module.
* Page provides register information.

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PIC16(L)F1508/9
NOTES:

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 PIC16(L)F1508/9
21.0 MASTER SYNCHRONOUS The SPI interface supports the following modes and
features:
SERIAL PORT (MSSP)
MODULE • Master mode
• Slave mode
21.1 MSSP Module Overview • Clock Parity
• Slave Select Synchronization (Slave mode only)
The Master Synchronous Serial Port (MSSPx) module
is a serial interface useful for communicating with other • Daisy-chain connection of slave devices
peripheral or microcontroller devices. These peripheral Figure 21-1 is a block diagram of the SPI interface
devices may be serial EEPROMs, shift registers, dis- module.
play drivers, A/D converters, etc. The MSSPx module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C™)

FIGURE 21-1: MSSP BLOCK DIAGRAM (SPI MODE)

Rev. 10-000076A
7/30/2013

Data bus

Read Write
8 8

SSPxBUF

SDI SSPxSR SDO_out

Bit 0
Shift clock
SDO

2 (CKP, CKE)
clock select
SSx
SSPM<3:0>
Control 4
Enable Edge
enable
(T2_match)
2
SCK_out
Edge Prescaler
enable
TOSC
4, 16, 64

Baud Rate
TRIS bit Generator
(SSPxADD)

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PIC16(L)F1508/9
The I2C interface supports the following modes and The PIC16(L)F1508/9 has one MSSP module.
features:
• Master mode
Note 1: In devices with more than one MSSP
• Slave mode module, it is very important to pay close
• Byte NACKing (Slave mode) attention to SSPxCONx register names.
• Limited Multi-master support SSPxCON1 and SSPxCON2 registers
• 7-bit and 10-bit addressing control different operational aspects of
• Start and Stop interrupts the same module, while SSPxCON1 and
SSP2CON1 control the same features for
• Interrupt masking
two different modules.
• Clock stretching
2: Throughout this section, generic refer-
• Bus collision detection
ences to an MSSPx module in any of its
• General call address matching operating modes may be interpreted as
• Address masking being equally applicable to MSSPx or
• Address Hold and Data Hold modes MSSP2. Register names, module I/O sig-
• Selectable SDAx hold times nals, and bit names may use the generic
designator ‘x’ to indicate the use of a
Figure 21-2 is a block diagram of the I2C interface mod- numeral to distinguish a particular module
ule in Master mode. Figure 21-3 is a diagram of the I2C when required.
interface module in Slave mode.

FIGURE 21-2: MSSPX BLOCK DIAGRAM (I2C™ MASTER MODE)

Rev. 10-000077A
7/30/2013

Internal data
bus

[SSPM <3:0>]
Read Write
8 8 4

Baud Rate
SSPxBUF Generator
(SSPxADD)

SDAx 8
SDAx in Shift clock
SSPxSR
Clock arbitrate/BCOL detect

(Hold off clock source)

MSb LSb
Clock Cntl
Receive Enable (RCEN)

Start bit, Stop bit,

Acknowledge
Generate
(SSPxCON2)
SCLx

Start bit detected

SCLx in Stop bit detected
Set/Reset: S, P, SSPxSTAT,
Write collsion detect
WCOL, SSPOV
Clock arbitration
Bus collision Reset SEN, PEN (SSPxCON2)
State counter for end
Set SSPxIF, BCLxIF
of XMIT/RCV
Address match detect

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 PIC16(L)F1508/9
FIGURE 21-3: MSSP BLOCK DIAGRAM (I2C™ SLAVE MODE)
Rev. 10-000078A
7/30/2013

Internal data bus

Read Write
8 8

SSPxBUF

8
8
SCLx
Shift clock

SDAx SSPxSR
MSb LSb
8

SSPxMSK
8

Match detect Addr Match

SSPxADD

Start and Stop Set, Reset S, P

bit Detect bits (SSPxSTAT)

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PIC16(L)F1508/9
21.2 SPI Mode Overview During each SPI clock cycle, a full-duplex data
transmission occurs. This means that while the master
The Serial Peripheral Interface (SPI) bus is a device is sending out the MSb from its shift register (on
synchronous serial data communication bus that its SDOx pin) and the slave device is reading this bit
operates in Full-Duplex mode. Devices communicate and saving it as the LSb of its shift register, that the
in a master/slave environment where the master device slave device is also sending out the MSb from its shift
initiates the communication. A slave device is register (on its SDOx pin) and the master device is
controlled through a Chip Select known as Slave reading this bit and saving it as the LSb of its shift
Select. register.
The SPI bus specifies four signal connections: After eight bits have been shifted out, the master and
• Serial Clock (SCKx) slave have exchanged register values.
• Serial Data Out (SDOx) If there is more data to exchange, the shift registers are
• Serial Data In (SDIx) loaded with new data and the process repeats itself.
• Slave Select (SSx) Whether the data is meaningful or not (dummy data),
Figure 21-1 shows the block diagram of the MSSP depends on the application software. This leads to
module when operating in SPI mode. three scenarios for data transmission:
The SPI bus operates with a single master device and • Master sends useful data and slave sends
one or more slave devices. When multiple slave dummy data.
devices are used, an independent Slave Select con- • Master sends useful data and slave sends useful
nection is required from the master device to each data.
slave device. • Master sends dummy data and slave sends use-
Figure 21-4 shows a typical connection between a ful data.
master device and multiple slave devices. Transmissions may involve any number of clock
The master selects only one slave at a time. Most slave cycles. When there is no more data to be transmitted,
devices have tri-state outputs so their output signal the master stops sending the clock signal and it dese-
appears disconnected from the bus when they are not lects the slave.
selected. Every slave device connected to the bus that has not
Transmissions involve two shift registers, eight bits in been selected through its slave select line must disre-
size, one in the master and one in the slave. With either gard the clock and transmission signals and must not
the master or the slave device, data is always shifted transmit out any data of its own.
out one bit at a time, with the Most Significant bit (MSb)
shifted out first. At the same time, a new Least
Significant bit (LSb) is shifted into the same register.
Figure 21-5 shows a typical connection between two
processors configured as master and slave devices.
Data is shifted out of both shift registers on the pro-
grammed clock edge and latched on the opposite edge
of the clock.
The master device transmits information out on its
SDOx output pin which is connected to, and received
by, the slave’s SDIx input pin. The slave device trans-
mits information out on its SDOx output pin, which is
connected to, and received by, the master’s SDIx input
pin.
To begin communication, the master device first sends
out the clock signal. Both the master and the slave
devices should be configured for the same clock polar-
ity.
The master device starts a transmission by sending out
the MSb from its shift register. The slave device reads
this bit from that same line and saves it into the LSb
position of its shift register.

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 PIC16(L)F1508/9
FIGURE 21-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION

Rev. 10-000079A
8/1/2013

SCKx SCKx
SPI Master SDOx SDIx SPI Slave
SDIx SDOx #1
General I/O SSx
General I/O
General I/O SCKx
SDIx SPI Slave
SDOx #2

SSx

SCKx
SDIx SPI Slave
SDOx #3

SSx

21.2.1 SPI MODE REGISTERS During transmission, the SSPxBUF is not buffered. A
write to SSPxBUF will write to both SSPxBUF and
The MSSP module has five registers for SPI mode SSPxSR.
operation. These are:
• MSSP STATUS register (SSPxSTAT)
• MSSP Control Register 1 (SSPxCON1)
• MSSP Control Register 3 (SSPxCON3)
• MSSP Data Buffer register (SSPxBUF)
• MSSP Address register (SSPxADD)
• MSSP Shift register (SSPxSR)
(Not directly accessible)
SSPxCON1 and SSPxSTAT are the control and
STATUS registers in SPI mode operation. The
SSPxCON1 register is readable and writable. The
lower six bits of the SSPxSTAT are read-only. The
upper two bits of the SSPxSTAT are read/write.
In SPI master mode, SSPxADD can be loaded with a
value used in the Baud Rate Generator. More informa-
tion on the Baud Rate Generator is available in
Section 21.7 “Baud Rate Generator”.
SSPxSR is the shift register used for shifting data in
and out. SSPxBUF provides indirect access to the
SSPxSR register. SSPxBUF is the buffer register to
which data bytes are written, and from which data
bytes are read.
In receive operations, SSPxSR and SSPxBUF
together create a buffered receiver. When SSPxSR
receives a complete byte, it is transferred to SSPxBUF
and the SSPxIF interrupt is set.

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PIC16(L)F1508/9
21.2.2 SPI MODE OPERATION When the application software is expecting to receive
valid data, the SSPxBUF should be read before the
When initializing the SPI, several options need to be next byte of data to transfer is written to the SSPxBUF.
specified. This is done by programming the appropriate The Buffer Full bit, BF of the SSPxSTAT register, indi-
control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). cates when SSPxBUF has been loaded with the
These control bits allow the following to be specified: received data (transmission is complete). When the
• Master mode (SCKx is the clock output) SSPxBUF is read, the BF bit is cleared. This data may
• Slave mode (SCKx is the clock input) be irrelevant if the SPI is only a transmitter. Generally,
• Clock Polarity (Idle state of SCKx) the MSSP interrupt is used to determine when the
transmission/reception has completed. If the interrupt
• Data Input Sample Phase (middle or end of data
method is not going to be used, then software polling
output time)
can be done to ensure that a write collision does not
• Clock Edge (output data on rising/falling edge of occur.
SCKx)
The SSPxSR is not directly readable or writable and
• Clock Rate (Master mode only)
can only be accessed by addressing the SSPxBUF
• Slave Select mode (Slave mode only) register. Additionally, the SSPxSTAT register indicates
To enable the serial port, SSP Enable bit, SSPEN of the various Status conditions.
the SSPxCON1 register, must be set. To reset or
reconfigure SPI mode, clear the SSPEN bit, re-initialize
the SSPxCONx registers and then set the SSPEN bit.
This configures the SDI, SDO, SCK and SS pins as
serial port pins. For the pins to behave as the serial port
function, some must have their data direction bits (in
the TRIS register) appropriately programmed as
follows:
• SDIx must have corresponding TRIS bit set
• SDOx must have corresponding TRIS bit cleared
• SCKx (Master mode) must have corresponding
TRIS bit cleared
• SCKx (Slave mode) must have corresponding
TRIS bit set
• SSx must have corresponding TRIS bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
The MSSP consists of a transmit/receive shift register
(SSPxSR) and a buffer register (SSPxBUF). The
SSPxSR shifts the data in and out of the device, MSb
first. The SSPxBUF holds the data that was written to
the SSPxSR until the received data is ready. Once the
eight bits of data have been received, that byte is
moved to the SSPxBUF register. Then, the Buffer Full
Detect bit, BF of the SSPxSTAT register, and the
interrupt flag bit, SSPxIF, are set. This double-buffering
of the received data (SSPxBUF) allows the next byte to
start reception before reading the data that was just
received. Any write to the SSPxBUF register during
transmission/reception of data will be ignored and the
write collision detect bit, WCOL of the SSPxCON1
register, will be set. User software must clear the
WCOL bit to allow the following write(s) to the
SSPxBUF register to complete successfully.

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 PIC16(L)F1508/9
FIGURE 21-5: SPI MASTER/SLAVE CONNECTION

Rev. 10-000080A
7/30/2013

SPI Master SSPM<3:0> = 00xx SPI Slave SSPM<3:0> = 010x

= 1010
SDOx SDIx

Serial Input Buffer Serial Input Buffer

(SSPxBUF) (SSPxBUF)

Shift Register SDIx SDOx Shift Register

(SSPxSR) (SSPxSR)
MSb LSb Serial clock MSb LSb
SCKx SCKx

Slave Select
General I/O SSx
Processor 1 (optional) Processor 2

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PIC16(L)F1508/9
21.2.3 SPI MASTER MODE The clock polarity is selected by appropriately
programming the CKP bit of the SSPxCON1 register
The master can initiate the data transfer at any time
and the CKE bit of the SSPxSTAT register. This then,
because it controls the SCKx line. The master
would give waveforms for SPI communication as
determines when the slave (Processor 2, Figure 21-5)
shown in Figure 21-6, Figure 21-8, Figure 21-9 and
is to broadcast data by the software protocol.
Figure 21-10, where the MSb is transmitted first. In
In Master mode, the data is transmitted/received as Master mode, the SPI clock rate (bit rate) is user
soon as the SSPxBUF register is written to. If the SPI programmable to be one of the following:
is only going to receive, the SDOx output could be dis-
• FOSC/4 (or TCY)
abled (programmed as an input). The SSPxSR register
will continue to shift in the signal present on the SDIx • FOSC/16 (or 4 * TCY)
pin at the programmed clock rate. As each byte is • FOSC/64 (or 16 * TCY)
received, it will be loaded into the SSPxBUF register as • Timer2 output/2
if a normal received byte (interrupts and Status bits • Fosc/(4 * (SSPxADD + 1))
appropriately set).
Figure 21-6 shows the waveforms for Master mode.
When the CKE bit is set, the SDOx data is valid before
there is a clock edge on SCKx. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPxBUF is loaded with the received
data is shown.

FIGURE 21-6: SPI MODE WAVEFORM (MASTER MODE)

Write to
SSPxBUF

SCKx
(CKP = 0
CKE = 0)

SCKx
(CKP = 1
CKE = 0)
4 Clock
SCKx Modes
(CKP = 0
CKE = 1)

SCKx
(CKP = 1
CKE = 1)

SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

(CKE = 0)

SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

(CKE = 1)
SDIx
(SMP = 0) bit 7 bit 0
Input
Sample
(SMP = 0)
SDIx
(SMP = 1) bit 0
bit 7

Input
Sample
(SMP = 1)
SSPxIF

SSPxSR to
SSPxBUF

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 PIC16(L)F1508/9
21.2.4 SPI SLAVE MODE 21.2.5 SLAVE SELECT
In Slave mode, the data is transmitted and received as SYNCHRONIZATION
external clock pulses appear on SCKx. When the last The Slave Select can also be used to synchronize com-
bit is latched, the SSPxIF interrupt flag bit is set. munication. The Slave Select line is held high until the
Before enabling the module in SPI Slave mode, the clock master device is ready to communicate. When the
line must match the proper Idle state. The clock line can Slave Select line is pulled low, the slave knows that a
be observed by reading the SCKx pin. The Idle state is new transmission is starting.
determined by the CKP bit of the SSPxCON1 register. If the slave fails to receive the communication properly,
While in Slave mode, the external clock is supplied by it will be reset at the end of the transmission, when the
the external clock source on the SCKx pin. This exter- Slave Select line returns to a high state. The slave is
nal clock must meet the minimum high and low times then ready to receive a new transmission when the
as specified in the electrical specifications. Slave Select line is pulled low again. If the Slave Select
line is not used, there is a risk that the slave will even-
While in Sleep mode, the slave can transmit/receive
tually become out of sync with the master. If the slave
data. The shift register is clocked from the SCKx pin
misses a bit, it will always be one bit off in future trans-
input and when a byte is received, the device will gen-
missions. Use of the Slave Select line allows the slave
erate an interrupt. If enabled, the device will wake-up
and master to align themselves at the beginning of
from Sleep.
each transmission.
21.2.4.1 Daisy-Chain Configuration The SSx pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SSx pin control
The SPI bus can sometimes be connected in a
enabled (SSPxCON1<3:0> = 0100).
daisy-chain configuration. The first slave output is con-
nected to the second slave input, the second slave When the SSx pin is low, transmission and reception
output is connected to the third slave input, and so on. are enabled and the SDOx pin is driven.
The final slave output is connected to the master input. When the SSx pin goes high, the SDOx pin is no longer
Each slave sends out, during a second group of clock driven, even if in the middle of a transmitted byte and
pulses, an exact copy of what was received during the becomes a floating output. External pull-up/pull-down
first group of clock pulses. The whole chain acts as resistors may be desirable depending on the applica-
one large communication shift register. The tion.
daisy-chain feature only requires a single Slave Select
line from the master device. Note 1: When the SPI is in Slave mode with SSx
pin control enabled (SSPxCON1<3:0> =
Figure 21-7 shows the block diagram of a typical
0100), the SPI module will reset if the SSx
daisy-chain connection when operating in SPI mode.
pin is set to VDD.
In a daisy-chain configuration, only the most recent
2: When the SPI is used in Slave mode with
byte on the bus is required by the slave. Setting the
CKE set; the user must enable SSx pin
BOEN bit of the SSPxCON3 register will enable writes
control.
to the SSPxBUF register, even if the previous byte has
not been read. This allows the software to ignore data 3: While operated in SPI Slave mode the
that may not apply to it. SMP bit of the SSPxSTAT register must
remain clear.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SSx pin to
a high level or clearing the SSPEN bit.

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PIC16(L)F1508/9
FIGURE 21-7: SPI DAISY-CHAIN CONNECTION
Rev. 10-000082A
7/30/2013

SCK SCK
SPI Master SDOx SDIx SPI Slave
SDIx SDOx #1

General I/O SSx

SCK
SDIx SPI Slave
SDOx #2
SSx

SCK
SDIx SPI Slave
SDOx #3
SSx

FIGURE 21-8: SLAVE SELECT SYNCHRONOUS WAVEFORM

SSx

SCKx
(CKP = 0
CKE = 0)

SCKx
(CKP = 1
CKE = 0)

Write to
SSPxBUF
Shift register SSPxSR
and bit count are reset
SSPxBUF to
SSPxSR

SDOx bit 7 bit 6 bit 7 bit 6 bit 0

SDIx bit 0
bit 7 bit 7
Input
Sample

SSPxIF
Interrupt
Flag

SSPxSR to
SSPxBUF

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 PIC16(L)F1508/9
FIGURE 21-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

SSx
Optional

SCKx
(CKP = 0
CKE = 0)

SCKx
(CKP = 1
CKE = 0)
Write to
SSPxBUF
Valid
SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SDIx
bit 7 bit 0
Input
Sample

SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF

Write Collision
detection active

FIGURE 21-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SSx
Not Optional

SCKx
(CKP = 0
CKE = 1)

SCKx
(CKP = 1
CKE = 1)
Write to
SSPxBUF
Valid
SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SDIx
bit 7 bit 0
Input
Sample

SSPxIF
Interrupt
Flag

SSPxSR to
SSPxBUF

Write Collision
detection active

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21.2.6 SPI OPERATION IN SLEEP MODE

In SPI Master mode, module clocks may be operating

at a different speed than when in Full-Power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the
MSSP clock is much faster than the system clock.
In Slave mode, when MSSP interrupts are enabled,
after the master completes sending data, an MSSP
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSP inter-
rupts should be disabled.
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the mod-
ule will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all eight bits have been received, the
MSSP interrupt flag bit will be set and if enabled, will
wake the device.

TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 113

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE — TMR2IE TMR1IE 77
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF — TMR2IF TMR1IF 80
SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register 185*
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 232
SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 234
SSP1STAT SMP CKE D/A P S R/W UA BF 230
TRISA — — TRISA5 TRISA4 —(1) TRISA2 TRISA1 TRISA0 112
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 120
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
* Page provides register information.
Note 1: Unimplemented, read as ‘1’.

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 PIC16(L)F1508/9
21.3 I2C MODE OVERVIEW FIGURE 21-11: I2C MASTER/
SLAVE CONNECTION
The Inter-Integrated Circuit Bus (I2C) is a multi-master
serial data communication bus. Devices communicate
Rev. 10-000085A
7/30/2013

in a master/slave environment where the master VDD

devices initiate the communication. A slave device is
controlled through addressing.
The I2C bus specifies two signal connections: SCLx SCLx
• Serial Clock (SCLx) VDD
• Serial Data (SDAx) Master Slave

Figure 21-2 and Figure 21-3 show the block diagrams

of the MSSP module when operating in I2C mode. SDAx SDAx
Both the SCLx and SDAx connections are bidirectional
open-drain lines, each requiring pull-up resistors for the
supply voltage. Pulling the line to ground is considered
The Acknowledge bit (ACK) is an active-low signal,
a logical zero and letting the line float is considered a
logical one. which holds the SDAx line low to indicate to the trans-
mitter that the slave device has received the transmit-
Figure 21-11 shows a typical connection between two ted data and is ready to receive more.
processors configured as master and slave devices.
The transition of a data bit is always performed while
The I2C bus can operate with one or more master the SCLx line is held low. Transitions that occur while
devices and one or more slave devices. the SCLx line is held high are used to indicate Start and
There are four potential modes of operation for a given Stop bits.
device: If the master intends to write to the slave, then it repeat-
• Master Transmit mode edly sends out a byte of data, with the slave responding
(master is transmitting data to a slave) after each byte with an ACK bit. In this example, the
• Master Receive mode master device is in Master Transmit mode and the
(master is receiving data from a slave) slave is in Slave Receive mode.
• Slave Transmit mode If the master intends to read from the slave, then it
(slave is transmitting data to a master) repeatedly receives a byte of data from the slave, and
• Slave Receive mode responds after each byte with an ACK bit. In this exam-
(slave is receiving data from the master) ple, the master device is in Master Receive mode and
the slave is Slave Transmit mode.
To begin communication, a master device starts out in
Master Transmit mode. The master device sends out a On the last byte of data communicated, the master
Start bit followed by the address byte of the slave it device may end the transmission by sending a Stop bit.
intends to communicate with. This is followed by a sin- If the master device is in Receive mode, it sends the
gle Read/Write bit, which determines whether the mas- Stop bit in place of the last ACK bit. A Stop bit is indi-
ter intends to transmit to or receive data from the slave cated by a low-to-high transition of the SDAx line while
device. the SCLx line is held high.

If the requested slave exists on the bus, it will respond In some cases, the master may want to maintain con-
with an Acknowledge bit, otherwise known as an ACK. trol of the bus and re-initiate another transmission. If
The master then continues in either Transmit mode or so, the master device may send another Start bit in
Receive mode and the slave continues in the comple- place of the Stop bit or last ACK bit when it is in receive
ment, either in Receive mode or Transmit mode, mode.
respectively. The I2C bus specifies three message protocols;
A Start bit is indicated by a high-to-low transition of the • Single message where a master writes data to a
SDAx line while the SCLx line is held high. Address and slave.
data bytes are sent out, Most Significant bit (MSb) first. • Single message where a master reads data from
The Read/Write bit is sent out as a logical one when the a slave.
master intends to read data from the slave, and is sent
• Combined message where a master initiates a
out as a logical zero when it intends to write data to the minimum of two writes, or two reads, or a
slave.
combination of writes and reads, to one or more
slaves.

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When one device is transmitting a logical one, or letting 21.3.2 ARBITRATION
the line float, and a second device is transmitting a log-
Each master device must monitor the bus for Start and
ical zero, or holding the line low, the first device can
Stop bits. If the device detects that the bus is busy, it
detect that the line is not a logical one. This detection,
cannot begin a new message until the bus returns to an
when used on the SCLx line, is called clock stretching.
Idle state.
Clock stretching gives slave devices a mechanism to
control the flow of data. When this detection is used on However, two master devices may try to initiate a trans-
the SDAx line, it is called arbitration. Arbitration mission on or about the same time. When this occurs,
ensures that there is only one master device communi- the process of arbitration begins. Each transmitter
cating at any single time. checks the level of the SDAx data line and compares it
to the level that it expects to find. The first transmitter to
21.3.1 CLOCK STRETCHING observe that the two levels do not match, loses arbitra-
tion, and must stop transmitting on the SDAx line.
When a slave device has not completed processing
data, it can delay the transfer of more data through the For example, if one transmitter holds the SDAx line to
process of clock stretching. An addressed slave device a logical one (lets it float) and a second transmitter
may hold the SCLx clock line low after receiving or holds it to a logical zero (pulls it low), the result is that
sending a bit, indicating that it is not yet ready to con- the SDAx line will be low. The first transmitter then
tinue. The master that is communicating with the slave observes that the level of the line is different than
will attempt to raise the SCLx line in order to transfer expected and concludes that another transmitter is
the next bit, but will detect that the clock line has not yet communicating.
been released. Because the SCLx connection is The first transmitter to notice this difference is the one
open-drain, the slave has the ability to hold that line low that loses arbitration and must stop driving the SDAx
until it is ready to continue communicating. line. If this transmitter is also a master device, it also
Clock stretching allows receivers that cannot keep up must stop driving the SCLx line. It then can monitor the
with a transmitter to control the flow of incoming data. lines for a Stop condition before trying to reissue its
transmission. In the meantime, the other device that
has not noticed any difference between the expected
and actual levels on the SDAx line continues with its
original transmission. It can do so without any compli-
cations, because so far, the transmission appears
exactly as expected with no other transmitter disturbing
the message.
Slave Transmit mode can also be arbitrated, when a
master addresses multiple slaves, but this is less com-
mon.
If two master devices are sending a message to two dif-
ferent slave devices at the address stage, the master
sending the lower slave address always wins arbitra-
tion. When two master devices send messages to the
same slave address, and addresses can sometimes
refer to multiple slaves, the arbitration process must
continue into the data stage.
Arbitration usually occurs very rarely, but it is a neces-
sary process for proper multi-master support.

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 PIC16(L)F1508/9
21.4 I2C MODE OPERATION TABLE 21-2: I2C BUS TERMS
TERM Description
All MSSP I2C communication is byte oriented and
shifted out MSb first. Six SFR registers and two Transmitter The device which shifts data out
interrupt flags interface the module with the PIC® onto the bus.
microcontroller and user software. Two pins, SDAx Receiver The device which shifts data in
and SCLx, are exercised by the module to communi- from the bus.
cate with other external I2C devices. Master The device that initiates a transfer,
generates clock signals and termi-
21.4.1 BYTE FORMAT nates a transfer.
All communication in I2C is done in 9-bit segments. A Slave The device addressed by the
byte is sent from a master to a slave or vice-versa, master.
followed by an Acknowledge bit sent back. After the Multi-master A bus with more than one device
eighth falling edge of the SCLx line, the device output- that can initiate data transfers.
ting data on the SDAx changes that pin to an input and
Arbitration Procedure to ensure that only one
reads in an acknowledge value on the next clock
master at a time controls the bus.
pulse.
Winning arbitration ensures that
The clock signal, SCLx, is provided by the master. the message is not corrupted.
Data is valid to change while the SCLx signal is low, Synchronization Procedure to synchronize the
and sampled on the rising edge of the clock. Changes clocks of two or more devices on
on the SDAx line while the SCLx line is high define the bus.
special conditions on the bus, explained below.
Idle No master is controlling the bus,
21.4.2 DEFINITION OF I2C TERMINOLOGY and both SDAx and SCLx lines are
high.
There is language and terminology in the description
Active Any time one or more master
of I2C communication that have definitions specific to
devices are controlling the bus.
I2C. That word usage is defined below and may be
used in the rest of this document without explanation. Addressed Slave device that has received a
This table was adapted from the Philips I2CTM Slave matching address and is actively
specification. being clocked by a master.
Matching Address byte that is clocked into a
21.4.3 SDAX AND SCLX PINS Address slave that matches the value
stored in SSPxADD.
Selection of any I2C mode with the SSPEN bit set,
forces the SCLx and SDAx pins to be open-drain. Write Request Slave receives a matching
These pins should be set by the user to inputs by set- address with R/W bit clear, and is
ting the appropriate TRIS bits. ready to clock in data.
Read Request Master sends an address byte with
Note: Data is tied to output zero when an I2C the R/W bit set, indicating that it
mode is enabled. wishes to clock data out of the
Slave. This data is the next and all
21.4.4 SDAX HOLD TIME following bytes until a Restart or
The hold time of the SDAx pin is selected by the Stop.
SDAHT bit of the SSPxCON3 register. Hold time is the Clock Stretching When a device on the bus hold
time SDAx is held valid after the falling edge of SCLx. SCLx low to stall communication.
Setting the SDAHT bit selects a longer 300 ns mini- Bus Collision Any time the SDAx line is sampled
mum hold time and may help on buses with large low by the module while it is out-
capacitance. putting and expected high state.

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PIC16(L)F1508/9
21.4.5 START CONDITION 21.4.7 RESTART CONDITION

The I2C specification defines a Start condition as a A Restart is valid any time that a Stop would be valid.
transition of SDAx from a high to a low state while A master can issue a Restart if it wishes to hold the
SCLx line is high. A Start condition is always gener- bus after terminating the current transfer. A Restart
ated by the master and signifies the transition of the has the same effect on the slave that a Start would,
bus from an Idle to an Active state. Figure 21-12 resetting all slave logic and preparing it to clock in an
shows wave forms for Start and Stop conditions. address. The master may want to address the same or
A bus collision can occur on a Start condition if the another slave. Figure 21-13 shows the wave form for a
module samples the SDAx line low before asserting it Restart condition.
low. This does not conform to the I2C Specification In 10-bit Addressing Slave mode a Restart is required
that states no bus collision can occur on a Start. for the master to clock data out of the addressed
slave. Once a slave has been fully addressed, match-
21.4.6 STOP CONDITION ing both high and low address bytes, the master can
A Stop condition is a transition of the SDAx line from issue a Restart and the high address byte with the
low-to-high state while the SCLx line is high. R/W bit set. The slave logic will then hold the clock
and prepare to clock out data.
Note: At least one SCLx low time must appear
After a full match with R/W clear in 10-bit mode, a prior
before a Stop is valid, therefore, if the SDAx
match flag is set and maintained. Until a Stop condi-
line goes low then high again while the SCLx
tion, a high address with R/W clear, or high address
line stays high, only the Start condition is
match fails.
detected.
21.4.8 START/STOP CONDITION INTERRUPT
MASKING

The SCIE and PCIE bits of the SSPxCON3 register

can enable the generation of an interrupt in Slave
modes that do not typically support this function. Slave
modes where interrupt on Start and Stop detect are
already enabled, these bits will have no effect.

FIGURE 21-12: I2C START AND STOP CONDITIONS

SDAx

SCLx
S P
Change of Change of
Data Allowed Data Allowed
Start Stop
Condition Condition

FIGURE 21-13: I2C RESTART CONDITION

Sr

Change of Change of

Data Allowed Data Allowed

Restart
Condition

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 PIC16(L)F1508/9
21.4.9 ACKNOWLEDGE SEQUENCE 21.5.1.1 I2C Slave 7-bit Addressing Mode
The ninth SCLx pulse for any transferred byte in I2C is In 7-bit Addressing mode, the LSb of the received data
dedicated as an Acknowledge. It allows receiving byte is ignored when determining if there is an address
devices to respond back to the transmitter by pulling match.
the SDAx line low. The transmitter must release con-
trol of the line during this time to shift in the response. 21.5.1.2 I2C Slave 10-bit Addressing Mode
The Acknowledge (ACK) is an active-low signal, pull- In 10-bit Addressing mode, the first received byte is
ing the SDAx line low indicated to the transmitter that compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9
the device has received the transmitted data and is and A8 are the two MSbs of the 10-bit address and
ready to receive more. stored in bits 2 and 1 of the SSPxADD register.
The result of an ACK is placed in the ACKSTAT bit of After the acknowledge of the high byte the UA bit is set
the SSPxCON2 register. and SCLx is held low until the user updates SSPxADD
Slave software, when the AHEN and DHEN bits are with the low address. The low address byte is clocked
set, allow the user to set the ACK value sent back to in and all eight bits are compared to the low address
the transmitter. The ACKDT bit of the SSPxCON2 reg- value in SSPxADD. Even if there is not an address
ister is set/cleared to determine the response. match; SSPxIF and UA are set, and SCLx is held low
until SSPxADD is updated to receive a high byte
Slave hardware will generate an ACK response if the
again. When SSPxADD is updated the UA bit is
AHEN and DHEN bits of the SSPxCON3 register are
cleared. This ensures the module is ready to receive
clear.
the high address byte on the next communication.
There are certain conditions where an ACK will not be
A high and low address match as a write request is
sent by the slave. If the BF bit of the SSPxSTAT regis-
required at the start of all 10-bit addressing communi-
ter or the SSPOV bit of the SSPxCON1 register are
cation. A transmission can be initiated by issuing a
set when a byte is received.
Restart once the slave is addressed, and clocking in
When the module is addressed, after the eighth falling the high address with the R/W bit set. The slave hard-
edge of SCLx on the bus, the ACKTIM bit of the ware will then acknowledge the read request and pre-
SSPxCON3 register is set. The ACKTIM bit indicates pare to clock out data. This is only valid for a slave
the acknowledge time of the active bus. The ACKTIM after it has received a complete high and low address
Status bit is only active when the AHEN bit or DHEN byte match.
bit is enabled.
21.5.2 SLAVE RECEPTION
2
21.5 I C Slave Mode Operation When the R/W bit of a matching received address byte
The MSSP Slave mode operates in one of four modes is clear, the R/W bit of the SSPxSTAT register is
selected in the SSPM bits of SSPxCON1 register. The cleared. The received address is loaded into the
modes can be divided into 7-bit and 10-bit Addressing SSPxBUF register and acknowledged.
mode. 10-bit Addressing modes operate the same as When the overflow condition exists for a received
7-bit with some additional overhead for handling the address, then not Acknowledge is given. An overflow
larger addresses. condition is defined as either bit BF of the SSPxSTAT
Modes with Start and Stop bit interrupts operate the register is set, or bit SSPOV of the SSPxCON1 register
same as the other modes with SSPxIF additionally is set. The BOEN bit of the SSPxCON3 register modi-
getting set upon detection of a Start, Restart, or Stop fies this operation. For more information see
condition. Register 21-4.
An MSSP interrupt is generated for each transferred
21.5.1 SLAVE MODE ADDRESSES data byte. Flag bit, SSPxIF, must be cleared by soft-
The SSPxADD register (Register 21-6) contains the ware.
Slave mode address. The first byte received after a When the SEN bit of the SSPxCON2 register is set,
Start or Restart condition is compared against the SCLx will be held low (clock stretch) following each
value stored in this register. If the byte matches, the received byte. The clock must be released by setting
value is loaded into the SSPxBUF register and an the CKP bit of the SSPxCON1 register, except
interrupt is generated. If the value does not match, the sometimes in 10-bit mode. See Section 21.2.3 “SPI
module goes idle and no indication is given to the soft- Master Mode” for more detail.
ware that anything happened.
The SSP Mask register (Register 21-5) affects the
address matching process. See Section 21.5.9
“SSPx Mask Register” for more information.

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21.5.2.1 7-bit Addressing Reception 21.5.2.2 7-bit Reception with AHEN and DHEN
This section describes a standard sequence of events Slave device reception with AHEN and DHEN set
for the MSSP module configured as an I2C slave in operate the same as without these options with extra
7-bit Addressing mode. Figure 21-14 and Figure 21-15 interrupts and clock stretching added after the eighth
are used as visual references for this description. falling edge of SCLx. These additional interrupts allow
This is a step by step process of what typically must the slave software to decide whether it wants to ACK
be done to accomplish I2C communication. the receive address or data byte, rather than the hard-
ware. This functionality adds support for PMBus™ that
1. Start bit detected. was not present on previous versions of this module.
2. S bit of SSPxSTAT is set; SSPxIF is set if inter-
This list describes the steps that need to be taken by
rupt on Start detect is enabled.
slave software to use these options for I2C communi-
3. Matching address with R/W bit clear is received. cation. Figure 21-16 displays a module using both
4. The slave pulls SDAx low sending an ACK to the address and data holding. Figure 21-17 includes the
master, and sets SSPxIF bit. operation with the SEN bit of the SSPxCON2 register
5. Software clears the SSPxIF bit. set.
6. Software reads received address from 1. S bit of SSPxSTAT is set; SSPxIF is set if inter-
SSPxBUF clearing the BF flag. rupt on Start detect is enabled.
7. If SEN = 1; Slave software sets CKP bit to 2. Matching address with R/W bit clear is clocked
release the SCLx line. in. SSPxIF is set and CKP cleared after the
8. The master clocks out a data byte. eighth falling edge of SCLx.
9. Slave drives SDAx low sending an ACK to the 3. Slave clears the SSPxIF.
master, and sets SSPxIF bit. 4. Slave can look at the ACKTIM bit of the
10. Software clears SSPxIF. SSPxCON3 register to determine if the SSPxIF
11. Software reads the received byte from was after or before the ACK.
SSPxBUF clearing BF. 5. Slave reads the address value from SSPxBUF,
12. Steps 8-12 are repeated for all received bytes clearing the BF flag.
from the Master. 6. Slave sets ACK value clocked out to the master
13. Master sends Stop condition, setting P bit of by setting ACKDT.
SSPxSTAT, and the bus goes idle. 7. Slave releases the clock by setting CKP.
8. SSPxIF is set after an ACK, not after a NACK.
9. If SEN = 1 the slave hardware will stretch the
clock after the ACK.
10. Slave clears SSPxIF.
Note: SSPxIF is still set after the ninth falling edge
of SCLx even if there is no clock stretching
and BF has been cleared. Only if NACK is
sent to master is SSPxIF not set
11. SSPxIF set and CKP cleared after eighth falling
edge of SCLx for a received data byte.
12. Slave looks at ACKTIM bit of SSPxCON3 to
determine the source of the interrupt.
13. Slave reads the received data from SSPxBUF
clearing BF.
14. Steps 7-14 are the same for each received data
byte.
15. Communication is ended by either the slave
sending an ACK = 1, or the master sending a
Stop condition. If a Stop is sent and Interrupt on
Stop Detect is disabled, the slave will only know
by polling the P bit of the SSPSTAT register.

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 FIGURE 21-14:

Bus Master sends

Stop condition
From Slave to Master

 2011-2013 Microchip Technology Inc.

Receiving Address Receiving Data Receiving Data ACK = 1
SDAx
A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0

SCLx
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P

SSPxIF
SSPxIF set on 9th
Cleared by software Cleared by software falling edge of
SCLx
BF
First byte
SSPxBUF is read of data is
available
in SSPxBUF
SSPOV

SSPOV set because

SSPxBUF is still full.
ACK is not sent.
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)

DS40001609C-page 199
PIC16(L)F1508/9
 FIGURE 21-15:

Bus Master sends

Stop condition

DS40001609C-page 200
Receive Address Receive Data Receive Data ACK
SDAx A7 A6 A5 A4 A3 A2 A1 R/W=0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0

SCLx S 1 2 3 4 5 6 7 8 9 SEN 1 2 3 4 5 6 7 8 9 SEN 1 2 3 4 5 6 7 8 9 P

PIC16(L)F1508/9

Clock is held low until CKP is set to ‘1’

SSPxIF

SSPxIF set on 9th

Cleared by software Cleared by software falling edge of SCLx

BF
First byte
of data is
SSPxBUF is read available
in SSPxBUF
SSPOV

SSPOV set because

SSPxBUF is still full.
ACK is not sent.
CKP

SCLx is not held

CKP is written to ‘1’ in software, CKP is written to ‘1’ in software,
low because
releasing SCLx releasing SCLx
ACK= 1
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)

 2011-2013 Microchip Technology Inc.

 Master Releases SDAx Master sends
to slave for ACK sequence Stop condition
FIGURE 21-16:

SDAx Receiving Address Receiving Data ACK Received Data ACK=1

A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SCLx
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P

 2011-2013 Microchip Technology Inc.

SSPxIF
If AHEN = 1: SSPxIF is set on
SSPxIF is set 9th falling edge of Cleared by software No interrupt
SCLx, after ACK after not ACK
BF from Slave
Address is
read from Data is read from SSPxBUF
ACKDT SSBUF

Slave software
clears ACKDT to Slave software
ACK the received sets ACKDT to
CKP byte not ACK

When AHEN=1:
When DHEN=1: CKP set by software,
CKP is cleared by hardware
CKP is cleared by SCLx is released
and SCLx is stretched hardware on 8th falling
edge of SCLx
ACKTIM

ACKTIM set by hardware ACKTIM cleared by ACKTIM set by hardware

on 8th falling edge of SCLx hardware in 9th on 8th falling edge of SCLx
rising edge of SCLx

P
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)

DS40001609C-page 201
PIC16(L)F1508/9
 Master sends
FIGURE 21-17:

Stop condition
Master releases
R/W = 0 SDAx to slave for ACK sequence

DS40001609C-page 202
Receiving Address Receive Data Receive Data ACK
SDAx ACK
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0

SCLx
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
S
PIC16(L)F1508/9

SSPxIF
Cleared by software No interrupt after
if not ACK
from Slave
BF
Received
address is loaded into Received data is SSPxBUF can be
SSPxBUF available on SSPxBUF read any time before
next byte is loaded
ACKDT

Slave software clears

Slave sends
ACKDT to ACK not ACK
the received byte
CKP
When AHEN = 1; When DHEN = 1; CKP is not cleared
on the 8th falling edge on the 8th falling edge Set by software, if not ACK
of SCLx of an address of SCLx of a received release SCLx
byte, CKP is cleared data byte, CKP is cleared

ACKTIM

ACKTIM is set by hardware ACKTIM is cleared by hardware

on 8th falling edge of SCLx on 9th rising edge of SCLx

P
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1)

 2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
21.5.3 SLAVE TRANSMISSION 21.5.3.2 7-bit Transmission
When the R/W bit of the incoming address byte is set A master device can transmit a read request to a
and an address match occurs, the R/W bit of the slave, and then clock data out of the slave. The list
SSPxSTAT register is set. The received address is below outlines what software for a slave will need to
loaded into the SSPxBUF register, and an ACK pulse is do to accomplish a standard transmission.
sent by the slave on the ninth bit. Figure 21-18 can be used as a reference to this list.
Following the ACK, slave hardware clears the CKP bit 1. Master sends a Start condition on SDAx and
and the SCLx pin is held low (see Section 21.5.6 SCLx.
“Clock Stretching” for more detail). By stretching the 2. S bit of SSPxSTAT is set; SSPxIF is set if inter-
clock, the master will be unable to assert another clock rupt on Start detect is enabled.
pulse until the slave is done preparing the transmit 3. Matching address with R/W bit set is received by
data. the slave setting SSPxIF bit.
The transmit data must be loaded into the SSPxBUF 4. Slave hardware generates an ACK and sets
register which also loads the SSPxSR register. Then SSPxIF.
the SCLx pin should be released by setting the CKP bit 5. SSPxIF bit is cleared by user.
of the SSPxCON1 register. The eight data bits are
6. Software reads the received address from
shifted out on the falling edge of the SCLx input. This
SSPxBUF, clearing BF.
ensures that the SDAx signal is valid during the SCLx
high time. 7. R/W is set so CKP was automatically cleared
after the ACK.
The ACK pulse from the master-receiver is latched on
8. The slave software loads the transmit data into
the rising edge of the ninth SCLx input pulse. This ACK
SSPxBUF.
value is copied to the ACKSTAT bit of the SSPxCON2
register. If ACKSTAT is set (not ACK), then the data 9. CKP bit is set releasing SCLx, allowing the mas-
transfer is complete. In this case, when the not ACK is ter to clock the data out of the slave.
latched by the slave, the slave goes idle and waits for 10. SSPxIF is set after the ACK response from the
another occurrence of the Start bit. If the SDAx line was master is loaded into the ACKSTAT register.
low (ACK), the next transmit data must be loaded into 11. SSPxIF bit is cleared.
the SSPxBUF register. Again, the SCLx pin must be 12. The slave software checks the ACKSTAT bit to
released by setting bit CKP. see if the master wants to clock out more data.
An MSSP interrupt is generated for each data transfer Note 1: If the master ACKs the clock will be
byte. The SSPxIF bit must be cleared by software and stretched.
the SSPxSTAT register is used to determine the status
of the byte. The SSPxIF bit is set on the falling edge of 2: ACKSTAT is the only bit updated on the
the ninth clock pulse. rising edge of SCLx (ninth) rather than the
falling.
21.5.3.1 Slave Mode Bus Collision 13. Steps 9-13 are repeated for each transmitted
A slave receives a Read request and begins shifting byte.
data out on the SDAx line. If a bus collision is detected 14. If the master sends a not ACK; the clock is not
and the SBCDE bit of the SSPxCON3 register is set, held, but SSPxIF is still set.
the BCLxIF bit of the PIRx register is set. Once a bus 15. The master sends a Restart condition or a Stop.
collision is detected, the slave goes idle and waits to be
16. The slave is no longer addressed.
addressed again. User software can use the BCLxIF bit
to handle a slave bus collision.

 2011-2013 Microchip Technology Inc. DS40001609C-page 203

 Master sends
Stop condition
FIGURE 21-18:

Receiving Address Transmitting Data Automatic Transmitting Data ACK

R/W = 1 Automatic
SDAx A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0

DS40001609C-page 204
SCLx
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P

SSPxIF

Cleared by software
PIC16(L)F1508/9

BF
BF is automatically
Received address Data to transmit is cleared after 8th falling
is read from SSPxBUF loaded into SSPxBUF edge of SCLx

CKP
When R/W is set CKP is not
SCLx is always held for not
held low after 9th SCLx Set by software ACK
falling edge
ACKSTAT

Masters not ACK

is copied to
ACKSTAT
R/W
R/W is copied from the
matching address byte
D/A
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)

Indicates an address
has been received

 2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
21.5.3.3 7-bit Transmission with Address
Hold Enabled
Setting the AHEN bit of the SSPxCON3 register
enables additional clock stretching and interrupt gen-
eration after the eighth falling edge of a received
matching address. Once a matching address has
been clocked in, CKP is cleared and the SSPxIF inter-
rupt is set.
Figure 21-19 displays a standard waveform of a 7-bit
Address Slave Transmission with AHEN enabled.
1. Bus starts idle.
2. Master sends Start condition; the S bit of
SSPxSTAT is set; SSPxIF is set if interrupt on
Start detect is enabled.
3. Master sends matching address with R/W bit
set. After the eighth falling edge of the SCLx line
the CKP bit is cleared and SSPxIF interrupt is
generated.
4. Slave software clears SSPxIF.
5. Slave software reads ACKTIM bit of SSPxCON3
register, and R/W and D/A of the SSPxSTAT
register to determine the source of the interrupt.
6. Slave reads the address value from the
SSPxBUF register clearing the BF bit.
7. Slave software decides from this information if it
wishes to ACK or not ACK and sets the ACKDT
bit of the SSPxCON2 register accordingly.
8. Slave sets the CKP bit releasing SCLx.
9. Master clocks in the ACK value from the slave.
10. Slave hardware automatically clears the CKP bit
and sets SSPxIF after the ACK if the R/W bit is
set.
11. Slave software clears SSPxIF.
12. Slave loads value to transmit to the master into
SSPxBUF setting the BF bit.
Note: SSPxBUF cannot be loaded until after the
ACK.
13. Slave sets the CKP bit, releasing the clock.
14. Master clocks out the data from the slave and
sends an ACK value on the ninth SCLx pulse.
15. Slave hardware copies the ACK value into the
ACKSTAT bit of the SSPxCON2 register.
16. Steps 10-15 are repeated for each byte trans-
mitted to the master from the slave.
17. If the master sends a not ACK the slave
releases the bus allowing the master to send a
Stop and end the communication.
Note: Master must send a not ACK on the last byte
to ensure that the slave releases the SCLx
line to receive a Stop.

 2011-2013 Microchip Technology Inc. DS40001609C-page 205

 Master sends
Master releases SDAx Stop condition
FIGURE 21-19:

to slave for ACK sequence

Receiving Address R/W = 1 Automatic Transmitting Data Automatic Transmitting Data ACK

DS40001609C-page 206
SDAx ACK
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0

SCLx
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
P

SSPxIF
Cleared by software
PIC16(L)F1508/9

BF BF is automatically
Received address Data to transmit is cleared after 8th falling
is read from SSPxBUF loaded into SSPxBUF edge of SCLx

ACKDT

Slave clears
ACKDT to ACK
address

ACKSTAT
Master’s ACK
response is copied
to SSPxSTAT
CKP
When AHEN = 1; CKP not cleared
CKP is cleared by hardware When R/W = 1; Set by software, after not ACK
after receiving matching CKP is always releases SCLx
address. cleared after ACK

ACKTIM
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)

ACKTIM is set on 8th falling ACKTIM is cleared

edge of SCLx on 9th rising edge of SCLx

R/W

D/A

 2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
21.5.4 SLAVE MODE 10-BIT ADDRESS 21.5.5 10-BIT ADDRESSING WITH ADDRESS OR
RECEPTION DATA HOLD

This section describes a standard sequence of events Reception using 10-bit addressing with AHEN or
for the MSSP module configured as an I2C slave in DHEN set is the same as with 7-bit modes. The only
10-bit Addressing mode. difference is the need to update the SSPxADD register
Figure 21-20 is used as a visual reference for this using the UA bit. All functionality, specifically when the
description. CKP bit is cleared and SCLx line is held low are the
same. Figure 21-21 can be used as a reference of a
This is a step by step process of what must be done by slave in 10-bit addressing with AHEN set.
slave software to accomplish I2C communication.
Figure 21-22 shows a standard waveform for a slave
1. Bus starts idle. transmitter in 10-bit Addressing mode.
2. Master sends Start condition; S bit of
SSPxSTAT is set; SSPxIF is set if interrupt on
Start detect is enabled.
3. Master sends matching high address with R/W
bit clear; UA bit of the SSPxSTAT register is set.
4. Slave sends ACK and SSPxIF is set.
5. Software clears the SSPxIF bit.
6. Software reads received address from
SSPxBUF clearing the BF flag.
7. Slave loads low address into SSPxADD,
releasing SCLx.
8. Master sends matching low address byte to the
slave; UA bit is set.
Note: Updates to the SSPxADD register are not
allowed until after the ACK sequence.

9. Slave sends ACK and SSPxIF is set.

Note: If the low address does not match, SSPxIF
and UA are still set so that the slave soft-
ware can set SSPxADD back to the high
address. BF is not set because there is no
match. CKP is unaffected.
10. Slave clears SSPxIF.
11. Slave reads the received matching address
from SSPxBUF clearing BF.
12. Slave loads high address into SSPxADD.
13. Master clocks a data byte to the slave and
clocks out the slaves ACK on the ninth SCLx
pulse; SSPxIF is set.
14. If SEN bit of SSPxCON2 is set, CKP is cleared
by hardware and the clock is stretched.
15. Slave clears SSPxIF.
16. Slave reads the received byte from SSPxBUF
clearing BF.
17. If SEN is set the slave sets CKP to release the
SCLx.
18. Steps 13-17 repeat for each received byte.
19. Master sends Stop to end the transmission.

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 FIGURE 21-20:

Master sends
Stop condition

DS40001609C-page 208
Receive First Address Byte Receive Second Address Byte Receive Data Receive Data
SDAx
1 1 1 1
0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

SCLx
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
S
PIC16(L)F1508/9

SCLx is held low

while CKP = 0

SSPxIF
Set by hardware Cleared by software
on 9th falling edge

BF
If address matches Receive address is Data is read
SSPxADD it is loaded into read from SSPxBUF from SSPxBUF
SSPxBUF

UA
When UA = 1; Software updates SSPxADD
SCLx is held low and releases SCLx

CKP

When SEN = 1; Set by software,

CKP is cleared after releasing SCLx
9th falling edge of received byte
I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)

 2011-2013 Microchip Technology Inc.

 Receive First Address Byte R/W = 0 Receive Second Address Byte Receive Data Receive Data
FIGURE 21-21:

SDAx 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5

SCLx S 1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 1 2

 2011-2013 Microchip Technology Inc.

SSPxIF
Set by hardware Cleared by software Cleared by software
on 9th falling edge

BF

SSPxBUF can be Received data

read anytime before is read from
the next received byte SSPxBUF
ACKDT
Slave software clears
ACKDT to ACK
the received byte

UA

Update to SSPxADD is Update of SSPxADD,

not allowed until 9th
falling edge of SCLx clears UA and releases
SCLx

CKP If when AHEN = 1;

on the 8th falling edge Set CKP with software
of SCLx of an address releases SCLx
byte, CKP is cleared
ACKTIM
ACKTIM is set by hardware
on 8th falling edge of SCLx
I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)

DS40001609C-page 209
PIC16(L)F1508/9
 FIGURE 21-22:

Master sends

DS40001609C-page 210
Master sends Stop condition
Restart event Master sends
not ACK

Receiving Address R/W = 0 Receiving Second Address Byte Receive First Address Byte Transmitting Data Byte ACK = 1
SDAx 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 ACK D7 D6 D5 D4 D3 D2 D1 D0

SCLx 1 2 3 4 5 6 7 8 9 1 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
PIC16(L)F1508/9

S 2 3 4 5 P
Sr

SSPxIF

Set by hardware Cleared by software Set by hardware

BF

SSPxBUF loaded Received address is Data to transmit is

with received address read from SSPxBUF loaded into SSPxBUF
UA
High address is loaded
UA indicates SSPxADD After SSPxADD is back into SSPxADD
must be updated updated, UA is cleared
CKP and SCLx is released

When R/W = 1; Set by software

ACKSTAT CKP is cleared on releases SCLx
9th falling edge of SCLx

Masters not ACK

is copied
R/W
R/W is copied from the
matching address byte
D/A

Indicates an address
has been received
I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)

 2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
21.5.6 CLOCK STRETCHING 21.5.6.2 10-bit Addressing Mode

Clock stretching occurs when a device on the bus In 10-bit Addressing mode, when the UA bit is set, the
holds the SCLx line low, effectively pausing communi- clock is always stretched. This is the only time the
cation. The slave may stretch the clock to allow more SCLx is stretched without CKP being cleared. SCLx is
time to handle data or prepare a response for the mas- released immediately after a write to SSPxADD.
ter device. A master device is not concerned with
Note: Previous versions of the module did not
stretching as anytime it is active on the bus and not
stretch the clock if the second address byte
transferring data it is stretching. Any stretching done
did not match.
by a slave is invisible to the master software and han-
dled by the hardware that generates SCLx. 21.5.6.3 Byte NACKing
The CKP bit of the SSPxCON1 register is used to con-
trol stretching in software. Any time the CKP bit is When the AHEN bit of SSPxCON3 is set; CKP is
cleared, the module will wait for the SCLx line to go cleared by hardware after the eighth falling edge of
low and then hold it. Setting CKP will release SCLx SCLx for a received matching address byte. When the
and allow more communication. DHEN bit of SSPxCON3 is set, CKP is cleared after
the eighth falling edge of SCLx for received data.
21.5.6.1 Normal Clock Stretching Stretching after the eighth falling edge of SCLx allows
Following an ACK if the R/W bit of SSPxSTAT is set, a the slave to look at the received address or data and
read request, the slave hardware will clear CKP. This decide if it wants to ACK the received data.
allows the slave time to update SSPxBUF with data to 21.5.7 CLOCK SYNCHRONIZATION AND
transfer to the master. If the SEN bit of SSPxCON2 is THE CKP BIT
set, the slave hardware will always stretch the clock
after the ACK sequence. Once the slave is ready, CKP Any time the CKP bit is cleared, the module will wait
is set by software and communication resumes. for the SCLx line to go low and then hold it. However,
clearing the CKP bit will not assert the SCLx output
Note 1: The BF bit has no effect on if the clock will
low until the SCLx output is already sampled low.
be stretched or not. This is different than
Therefore, the CKP bit will not assert the SCLx line
previous versions of the module that
until an external I2C master device has already
would not stretch the clock, clear CKP, if
asserted the SCLx line. The SCLx output will remain
SSPxBUF was read before the ninth fall-
low until the CKP bit is set and all other devices on the
ing edge of SCLx.
I2C bus have released SCLx. This ensures that a write
2: Previous versions of the module did not to the CKP bit will not violate the minimum high time
stretch the clock for a transmission if requirement for SCLx (see Figure 21-23).
SSPxBUF was loaded before the ninth
falling edge of SCLx. It is now always
cleared for read requests.

FIGURE 21-23: CLOCK SYNCHRONIZATION TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SDAx DX DX ‚ – 1

SCLx

Master device
CKP asserts clock

Master device
releases clock
WR
SSPxCON1

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PIC16(L)F1508/9
21.5.8 GENERAL CALL ADDRESS SUPPORT In 10-bit Address mode, the UA bit will not be set on
the reception of the general call address. The slave
The addressing procedure for the I2C bus is such that will prepare to receive the second byte as data, just as
the first byte after the Start condition usually deter- it would in 7-bit mode.
mines which device will be the slave addressed by the
master device. The exception is the general call If the AHEN bit of the SSPxCON3 register is set, just
address which can address all devices. When this as with any other address reception, the slave hard-
address is used, all devices should, in theory, respond ware will stretch the clock after the eighth falling edge
with an acknowledge. of SCLx. The slave must then set its ACKDT value and
release the clock with communication progressing as it
The general call address is a reserved address in the would normally.
I2C protocol, defined as address 0x00. When the
GCEN bit of the SSPxCON2 register is set, the slave
module will automatically ACK the reception of this
address regardless of the value stored in SSPxADD.
After the slave clocks in an address of all zeros with
the R/W bit clear, an interrupt is generated and slave
software can read SSPxBUF and respond.
Figure 21-24 shows a General Call reception
sequence.

FIGURE 21-24: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE

Address is compared to General Call Address
after ACK, set interrupt

R/W = 0 Receiving Data ACK

SDAx General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0

SCLx
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S

SSPxIF

BF (SSPxSTAT<0>)

Cleared by software
SSPxBUF is read
GCEN (SSPxCON2<7>)
’1’

21.5.9 SSPx MASK REGISTER

An SSPx Mask (SSPxMSK) register (Register 21-5) is

available in I2C Slave mode as a mask for the value
held in the SSPxSR register during an address
comparison operation. A zero (‘0’) bit in the SSPxMSK
register has the effect of making the corresponding bit
of the received address a “don’t care”.
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSPx operation until written with a mask value.
The SSPx Mask register is active during:
• 7-bit Address mode: address compare of A<7:1>.
• 10-bit Address mode: address compare of A<7:0>
only. The SSPx mask has no effect during the
reception of the first (high) byte of the address.

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 PIC16(L)F1508/9
21.6 I2C MASTER MODE 21.6.1 I2C MASTER MODE OPERATION

Master mode is enabled by setting and clearing the The master device generates all of the serial clock
appropriate SSPM bits in the SSPxCON1 register and pulses and the Start and Stop conditions. A transfer is
by setting the SSPEN bit. In Master mode, the SDAx ended with a Stop condition or with a Repeated Start
and SCKx pins must be configured as inputs. The condition. Since the Repeated Start condition is also
MSSP peripheral hardware will override the output the beginning of the next serial transfer, the I2C bus will
driver TRIS controls when necessary to drive the pins not be released.
low. In Master Transmitter mode, serial data is output
Master mode of operation is supported by interrupt through SDAx, while SCLx outputs the serial clock. The
generation on the detection of the Start and Stop con- first byte transmitted contains the slave address of the
ditions. The Stop (P) and Start (S) bits are cleared from receiving device (seven bits) and the Read/Write (R/W)
a Reset or when the MSSPx module is disabled. Con- bit. In this case, the R/W bit will be logic ‘0’. Serial data
trol of the I 2C bus may be taken when the P bit is set, is transmitted eight bits at a time. After each byte is
or the bus is idle. transmitted, an Acknowledge bit is received. Start and
Stop conditions are output to indicate the beginning
In Firmware Controlled Master mode, user code and the end of a serial transfer.
conducts all I 2C bus operations based on Start and
Stop bit condition detection. Start and Stop condition In Master Receive mode, the first byte transmitted
detection is the only active circuitry in this mode. All contains the slave address of the transmitting device
other communication is done by the user software (seven bits) and the R/W bit. In this case, the R/W bit
directly manipulating the SDAx and SCLx lines. will be logic ‘1’. Thus, the first byte transmitted is a 7-bit
slave address followed by a ‘1’ to indicate the receive
The following events will cause the SSPx Interrupt Flag bit. Serial data is received via SDAx, while SCLx out-
bit, SSPxIF, to be set (SSPx interrupt, if enabled): puts the serial clock. Serial data is received eight bits at
• Start condition detected a time. After each byte is received, an Acknowledge bit
is transmitted. Start and Stop conditions indicate the
• Stop condition detected
beginning and end of transmission.
• Data transfer byte transmitted/received
A Baud Rate Generator is used to set the clock
• Acknowledge transmitted/received
frequency output on SCLx. See Section 21.7 “Baud
• Repeated Start generated Rate Generator” for more detail.
Note 1: The MSSPx module, when configured in
I2C Master mode, does not allow queue-
ing of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPxBUF register
to initiate transmission before the Start
condition is complete. In this case, the
SSPxBUF will not be written to and the
WCOL bit will be set, indicating that a
write to the SSPxBUF did not occur
2: When in Master mode, Start/Stop detec-
tion is masked and an interrupt is gener-
ated when the SEN/PEN bit is cleared and
the generation is complete.

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PIC16(L)F1508/9
21.6.2 CLOCK ARBITRATION

Clock arbitration occurs when the master, during any

receive, transmit or Repeated Start/Stop condition,
releases the SCLx pin (SCLx allowed to float high).
When the SCLx pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCLx pin is actually sampled high. When the
SCLx pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPxADD<7:0> and
begins counting. This ensures that the SCLx high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure 21-25).

FIGURE 21-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

SDAx DX DX ‚ – 1

SCLx deasserted but slave holds SCLx allowed to transition high

SCLx low (clock arbitration)
SCLx

BRG decrements on
Q2 and Q4 cycles

BRG
03h 02h 01h 00h (hold off) 03h 02h
Value

SCLx is sampled high, reload takes

place and BRG starts its count
BRG
Reload

21.6.3 WCOL STATUS FLAG

If the user writes the SSPxBUF when a Start, Restart,

Stop, Receive or Transmit sequence is in progress, the
WCOL bit is set and the contents of the buffer are
unchanged (the write does not occur). Any time the
WCOL bit is set it indicates that an action on SSPxBUF
was attempted while the module was not idle.
Note: Because queueing of events is not
allowed, writing to the lower five bits of
SSPxCON2 is disabled until the Start
condition is complete.

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 PIC16(L)F1508/9
21.6.4 I2C MASTER MODE START by hardware; the Baud Rate Generator is suspended,
CONDITION TIMING leaving the SDAx line held low and the Start condition
is complete.
To initiate a Start condition (Figure 21-26), the user
sets the Start Enable bit, SEN bit of the SSPxCON2 Note 1: If at the beginning of the Start condition,
register. If the SDAx and SCLx pins are sampled high, the SDAx and SCLx pins are already sam-
the Baud Rate Generator is reloaded with the contents pled low, or if during the Start condition,
of SSPxADD<7:0> and starts its count. If SCLx and the SCLx line is sampled low before the
SDAx are both sampled high when the Baud Rate SDAx line is driven low, a bus collision
Generator times out (TBRG), the SDAx pin is driven occurs, the Bus Collision Interrupt Flag,
low. The action of the SDAx being driven low while BCLxIF, is set, the Start condition is
SCLx is high is the Start condition and causes the S bit aborted and the I2C module is reset into
of the SSPxSTAT1 register to be set. Following this, its Idle state.
the Baud Rate Generator is reloaded with the contents 2: The Philips I2C Specification states that a
of SSPxADD<7:0> and resumes its count. When the bus collision cannot occur on a Start.
Baud Rate Generator times out (TBRG), the SEN bit of
the SSPxCON2 register will be automatically cleared

FIGURE 21-26: FIRST START BIT TIMING

Write to SEN bit occurs here Set S bit (SSPxSTAT<3>)

At completion of Start bit,

SDAx = 1,
SCLx = 1 hardware clears SEN bit
and sets SSPxIF bit
TBRG TBRG Write to SSPxBUF occurs here
SDAx 1st bit 2nd bit

TBRG
SCLx
S
TBRG

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PIC16(L)F1508/9
21.6.5 I2C MASTER MODE REPEATED automatically cleared and the Baud Rate Generator will
START CONDITION TIMING not be reloaded, leaving the SDAx pin held low. As
soon as a Start condition is detected on the SDAx and
A Repeated Start condition (Figure 21-27) occurs when SCLx pins, the S bit of the SSPxSTAT register will be
the RSEN bit of the SSPxCON2 register is pro- set. The SSPxIF bit will not be set until the Baud Rate
grammed high and the master state machine is no lon- Generator has timed out.
ger active. When the RSEN bit is set, the SCLx pin is
asserted low. When the SCLx pin is sampled low, the Note 1: If RSEN is programmed while any other
Baud Rate Generator is loaded and begins counting. event is in progress, it will not take effect.
The SDAx pin is released (brought high) for one Baud 2: A bus collision during the Repeated Start
Rate Generator count (TBRG). When the Baud Rate condition occurs if:
Generator times out, if SDAx is sampled high, the SCLx
pin will be deasserted (brought high). When SCLx is • SDAx is sampled low when SCLx
sampled high, the Baud Rate Generator is reloaded goes from low-to-high.
and begins counting. SDAx and SCLx must be sam- • SCLx goes low before SDAx is
pled high for one TBRG. This action is then followed by asserted low. This may indicate
assertion of the SDAx pin (SDAx = 0) for one TBRG that another master is attempting to
while SCLx is high. SCLx is asserted low. Following transmit a data ‘1’.
this, the RSEN bit of the SSPxCON2 register will be

FIGURE 21-27: REPEAT START CONDITION WAVEFORM

S bit set by hardware

Write to SSPxCON2
occurs here At completion of Start bit,
SDAx = 1, SDAx = 1,
hardware clears RSEN bit
SCLx (no change) SCLx = 1 and sets SSPxIF

TBRG TBRG TBRG

SDAx 1st bit

Write to SSPxBUF occurs here

TBRG
SCLx
Sr TBRG
Repeated Start

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 PIC16(L)F1508/9
21.6.6 I2C MASTER MODE TRANSMISSION 21.6.6.3 ACKSTAT Status Flag
Transmission of a data byte, a 7-bit address or the In Transmit mode, the ACKSTAT bit of the SSPxCON2
other half of a 10-bit address is accomplished by simply register is cleared when the slave has sent an Acknowl-
writing a value to the SSPxBUF register. This action will edge (ACK = 0) and is set when the slave does not
set the Buffer Full flag bit, BF, and allow the Baud Rate Acknowledge (ACK = 1). A slave sends an Acknowl-
Generator to begin counting and start the next trans- edge when it has recognized its address (including a
mission. Each bit of address/data will be shifted out general call), or when the slave has properly received
onto the SDAx pin after the falling edge of SCLx is its data.
asserted. SCLx is held low for one Baud Rate Genera-
tor rollover count (TBRG). Data should be valid before 21.6.6.4 Typical transmit sequence:
SCLx is released high. When the SCLx pin is released 1. The user generates a Start condition by setting
high, it is held that way for TBRG. The data on the SDAx the SEN bit of the SSPxCON2 register.
pin must remain stable for that duration and some hold 2. SSPxIF is set by hardware on completion of the
time after the next falling edge of SCLx. After the eighth Start.
bit is shifted out (the falling edge of the eighth clock),
3. SSPxIF is cleared by software.
the BF flag is cleared and the master releases SDAx.
This allows the slave device being addressed to 4. The MSSPx module will wait the required start
respond with an ACK bit during the ninth bit time if an time before any other operation takes place.
address match occurred, or if data was received prop- 5. The user loads the SSPxBUF with the slave
erly. The status of ACK is written into the ACKSTAT bit address to transmit.
on the rising edge of the ninth clock. If the master 6. Address is shifted out the SDAx pin until all eight
receives an Acknowledge, the Acknowledge Status bit, bits are transmitted. Transmission begins as
ACKSTAT, is cleared. If not, the bit is set. After the ninth soon as SSPxBUF is written to.
clock, the SSPxIF bit is set and the master clock (Baud 7. The MSSPx module shifts in the ACK bit from
Rate Generator) is suspended until the next data byte the slave device and writes its value into the
is loaded into the SSPxBUF, leaving SCLx low and ACKSTAT bit of the SSPxCON2 register.
SDAx unchanged (Figure 21-28). 8. The MSSPx module generates an interrupt at
After the write to the SSPxBUF, each bit of the address the end of the ninth clock cycle by setting the
will be shifted out on the falling edge of SCLx until all SSPxIF bit.
seven address bits and the R/W bit are completed. On 9. The user loads the SSPxBUF with eight bits of
the falling edge of the eighth clock, the master will data.
release the SDAx pin, allowing the slave to respond 10. Data is shifted out the SDAx pin until all eight
with an Acknowledge. On the falling edge of the ninth bits are transmitted.
clock, the master will sample the SDAx pin to see if the
11. The MSSPx module shifts in the ACK bit from
address was recognized by a slave. The status of the
the slave device and writes its value into the
ACK bit is loaded into the ACKSTAT Status bit of the
ACKSTAT bit of the SSPxCON2 register.
SSPxCON2 register. Following the falling edge of the
ninth clock transmission of the address, the SSPxIF is 12. Steps 8-11 are repeated for all transmitted data
set, the BF flag is cleared and the Baud Rate Generator bytes.
is turned off until another write to the SSPxBUF takes 13. The user generates a Stop or Restart condition
place, holding SCLx low and allowing SDAx to float. by setting the PEN or RSEN bits of the
SSPxCON2 register. Interrupt is generated once
21.6.6.1 BF Status Flag the Stop/Restart condition is complete.
In Transmit mode, the BF bit of the SSPxSTAT register
is set when the CPU writes to SSPxBUF and is cleared
when all eight bits are shifted out.

21.6.6.2 WCOL Status Flag

If the user writes the SSPxBUF when a transmit is
already in progress (i.e., SSPxSR is still shifting out a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write does not occur).
WCOL must be cleared by software before the next
transmission.

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 FIGURE 21-28:

DS40001609C-page 218
Write SSPxCON2<0> SEN = 1 ACKSTAT in
Start condition begins SSPxCON2 = 1
From slave, clear ACKSTAT bit SSPxCON2<6>
SEN = 0
Transmitting Data or Second Half
Transmit Address to Slave R/W = 0
of 10-bit Address ACK

SDAx A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0

SSPxBUF written with 7-bit address and R/W

start transmit
PIC16(L)F1508/9

SCLx 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SCLx held low
while CPU
responds to SSPxIF
SSPxIF
Cleared by software service routine
Cleared by software from SSP interrupt
Cleared by software

BF (SSPxSTAT<0>)

SSPxBUF written SSPxBUF is written by software

SEN

After Start condition, SEN cleared by hardware

PEN

R/W
I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)

 2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
21.6.7 I2C MASTER MODE RECEPTION 21.6.7.4 Typical Receive Sequence:
Master mode reception (Figure 21-29) is enabled by 1. The user generates a Start condition by setting
programming the Receive Enable bit, RCEN bit of the the SEN bit of the SSPxCON2 register.
SSPxCON2 register. 2. SSPxIF is set by hardware on completion of the
Note: The MSSPx module must be in an Idle Start.
state before the RCEN bit is set or the 3. SSPxIF is cleared by software.
RCEN bit will be disregarded. 4. User writes SSPxBUF with the slave address to
The Baud Rate Generator begins counting and on each transmit and the R/W bit set.
rollover, the state of the SCLx pin changes 5. Address is shifted out the SDAx pin until all eight
(high-to-low/low-to-high) and data is shifted into the bits are transmitted. Transmission begins as
SSPxSR. After the falling edge of the eighth clock, the soon as SSPxBUF is written to.
receive enable flag is automatically cleared, the con- 6. The MSSP module shifts in the ACK bit from the
tents of the SSPxSR are loaded into the SSPxBUF, the slave device and writes its value into the
BF flag bit is set, the SSPxIF flag bit is set and the Baud ACKSTAT bit of the SSPxCON2 register.
Rate Generator is suspended from counting, holding 7. The MSSP module generates an interrupt at the
SCLx low. The MSSP is now in Idle state awaiting the end of the ninth clock cycle by setting the
next command. When the buffer is read by the CPU, SSPxIF bit.
the BF flag bit is automatically cleared. The user can 8. User sets the RCEN bit of the SSPxCON2 regis-
then send an Acknowledge bit at the end of reception ter and the master clocks in a byte from the slave.
by setting the Acknowledge Sequence Enable, ACKEN
9. After the eighth falling edge of SCLx, SSPxIF
bit of the SSPxCON2 register.
and BF are set.
21.6.7.1 BF Status Flag 10. Master clears SSPxIF and reads the received
byte from SSPxBUF, clears BF.
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPxBUF from SSPxSR. It 11. Master sets ACK value sent to slave in ACKDT
is cleared when the SSPxBUF register is read. bit of the SSPxCON2 register and initiates the
ACK by setting the ACKEN bit.
21.6.7.2 SSPOV Status Flag 12. Masters ACK is clocked out to the slave and
In receive operation, the SSPOV bit is set when eight SSPxIF is set.
bits are received into the SSPxSR and the BF flag bit is 13. User clears SSPxIF.
already set from a previous reception. 14. Steps 8-13 are repeated for each received byte
from the slave.
21.6.7.3 WCOL Status Flag 15. Master sends a not ACK or Stop to end
If the user writes the SSPxBUF when a receive is communication.
already in progress (i.e., SSPxSR is still shifting in a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write does not occur).

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 Write to SSPxCON2<4>
to start Acknowledge sequence
SDAx = ACKDT (SSPxCON2<5>) = 0
Write to SSPxCON2<0>(SEN = 1),
FIGURE 21-29:

begin Start condition ACK from Master Set ACKEN, start Acknowledge sequence
Master configured as a receiver SDAx = ACKDT = 0 SDAx = ACKDT = 1
by programming SSPxCON2<3> (RCEN = 1)

DS40001609C-page 220
SEN = 0
PEN bit = 1
Write to SSPxBUF occurs here, RCEN cleared RCEN = 1, start RCEN cleared
ACK from Slave next receive automatically written here
start XMIT automatically
Transmit Address to Slave Receiving Data from Slave Receiving Data from Slave
SDAx A7 A6 A5 A4 A3 A2 A1 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

Bus master
ACK is not sent terminates
transfer
3 6 7 9
PIC16(L)F1508/9

1 2 4 5 8 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCLx S P
Data shifted in on falling edge of CLK Set SSPxIF at end
of receive Set SSPxIF interrupt
Set SSPxIF interrupt at end of Acknow-
Set SSPxIF interrupt ledge sequence
at end of receive at end of Acknowledge
SSPxIF sequence

Set P bit
Cleared by software Cleared by software Cleared by software Cleared by software (SSPxSTAT<4>)
SDAx = 0, SCLx = 1 Cleared in
while CPU software and SSPxIF
responds to SSPxIF

BF
(SSPxSTAT<0>) Last bit is shifted into SSPxSR and
contents are unloaded into SSPxBUF

SSPOV

SSPOV is set because

SSPxBUF is still full

ACKEN
I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)

RCEN

Master configured as a receiver RCEN cleared ACK from Master RCEN cleared
by programming SSPxCON2<3> (RCEN = 1) automatically SDAx = ACKDT = 0 automatically

 2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
21.6.8 ACKNOWLEDGE SEQUENCE 21.6.9 STOP CONDITION TIMING
TIMING A Stop bit is asserted on the SDAx pin at the end of a
An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable
Acknowledge Sequence Enable bit, ACKEN bit of the bit, PEN bit of the SSPxCON2 register. At the end of a
SSPxCON2 register. When this bit is set, the SCLx pin is receive/transmit, the SCLx line is held low after the
pulled low and the contents of the Acknowledge data bit falling edge of the ninth clock. When the PEN bit is set,
are presented on the SDAx pin. If the user wishes to the master will assert the SDAx line low. When the
generate an Acknowledge, then the ACKDT bit should SDAx line is sampled low, the Baud Rate Generator is
be cleared. If not, the user should set the ACKDT bit reloaded and counts down to ‘0’. When the Baud Rate
before starting an Acknowledge sequence. The Baud Generator times out, the SCLx pin will be brought high
Rate Generator then counts for one rollover period and one TBRG (Baud Rate Generator rollover count)
(TBRG) and the SCLx pin is deasserted (pulled high). later, the SDAx pin will be deasserted. When the SDAx
When the SCLx pin is sampled high (clock arbitration), pin is sampled high while SCLx is high, the P bit of the
the Baud Rate Generator counts for TBRG. The SCLx pin SSPxSTAT register is set. A TBRG later, the PEN bit is
is then pulled low. Following this, the ACKEN bit is auto- cleared and the SSPxIF bit is set (Figure 21-31).
matically cleared, the Baud Rate Generator is turned off
and the MSSP module then goes into Idle mode 21.6.9.1 WCOL Status Flag
(Figure 21-30). If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
21.6.8.1 WCOL Status Flag contents of the buffer are unchanged (the write does
If the user writes the SSPxBUF when an Acknowledge not occur).
sequence is in progress, then the WCOL bit is set and
the contents of the buffer are unchanged (the write
does not occur).

FIGURE 21-30: ACKNOWLEDGE SEQUENCE WAVEFORM

Acknowledge sequence starts here, ACKEN automatically cleared
write to SSPxCON2
ACKEN = 1, ACKDT = 0
TBRG TBRG
SDAx D0 ACK

SCLx 8 9

SSPxIF

Cleared in
SSPxIF set at software
the end of receive Cleared in
software SSPxIF set at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.

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PIC16(L)F1508/9
FIGURE 21-31: STOP CONDITION RECEIVE OR TRANSMIT MODE
Write to SSPxCON2, SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG
set PEN after SDAx sampled high. P bit (SSPxSTAT<4>) is set.

Falling edge of PEN bit (SSPxCON2<2>) is cleared by

9th clock hardware and the SSPxIF bit is set
TBRG
SCLx

SDAx ACK

P
TBRG TBRG TBRG
SCLx brought high after TBRG
SDAx asserted low before rising edge of clock
to setup Stop condition

Note: TBRG = one Baud Rate Generator period.

21.6.10 SLEEP OPERATION 21.6.13 MULTI -MASTER COMMUNICATION,

While in Sleep mode, the I2C slavemodule can receive BUS COLLISION AND BUS
addresses or data and when an address match or ARBITRATION
complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus arbitra-
from Sleep (if the MSSP interrupt is enabled). tion. When the master outputs address/data bits onto
the SDAx pin, arbitration takes place when the master
21.6.11 EFFECTS OF A RESET outputs a ‘1’ on SDAx, by letting SDAx float high and
A Reset disables the MSSP module and terminates the another master asserts a ‘0’. When the SCLx pin floats
current transfer. high, data should be stable. If the expected data on
SDAx is a ‘1’ and the data sampled on the SDAx pin is
21.6.12 MULTI-MASTER MODE ‘0’, then a bus collision has taken place. The master will
In Multi-Master mode, the interrupt generation on the set the Bus Collision Interrupt Flag, BCLxIF and reset
detection of the Start and Stop conditions allows the the I2C port to its Idle state (Figure 21-32).
determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision
Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is
MSSP module is disabled. Control of the I 2C bus may cleared, the SDAx and SCLx lines are deasserted and
be taken when the P bit of the SSPxSTAT register is the SSPxBUF can be written to. When the user ser-
set, or the bus is idle, with both the S and P bits clear. vices the bus collision Interrupt Service Routine and if
When the bus is busy, enabling the SSP interrupt will the I2C bus is free, the user can resume communica-
generate the interrupt when the Stop condition occurs. tion by asserting a Start condition.
In Multi-Master mode, the SDAx line must be monitored If a Start, Repeated Start, Stop or Acknowledge condi-
for arbitration to see if the signal level is the expected tion was in progress when the bus collision occurred, the
output level. This check is performed by hardware with condition is aborted, the SDAx and SCLx lines are deas-
the result placed in the BCLxIF bit. serted and the respective control bits in the SSPxCON2
The states where arbitration can be lost are: register are cleared. When the user services the bus col-
lision Interrupt Service Routine and if the I2C bus is free,
• Address Transfer the user can resume communication by asserting a Start
• Data Transfer condition.
• A Start Condition The master will continue to monitor the SDAx and SCLx
• A Repeated Start Condition pins. If a Stop condition occurs, the SSPxIF bit will be set.
• An Acknowledge Condition A write to the SSPxBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the deter-
mination of when the bus is free. Control of the I2C bus
can be taken when the P bit is set in the SSPxSTAT
register, or the bus is idle and the S and P bits are
cleared.

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 PIC16(L)F1508/9
FIGURE 21-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Sample SDAx. While SCLx is high,
Data changes SDAx line pulled low data does not match what is driven
while SCLx = 0 by another source by the master.
Bus collision has occurred.
SDAx released
by master

SDAx

SCLx Set bus collision

interrupt (BCLxIF)

BCLxIF

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PIC16(L)F1508/9
21.6.13.1 Bus Collision During a Start If the SDAx pin is sampled low during this count, the
Condition BRG is reset and the SDAx line is asserted early
(Figure 21-35). If, however, a ‘1’ is sampled on the SDA
During a Start condition, a bus collision occurs if:
pin, the SDA pin is asserted low at the end of the BRG
a) SDA or SCL are sampled low at the beginning of count. The Baud Rate Generator is then reloaded and
the Start condition (Figure 21-33). counts down to zero; if the SCL pin is sampled as ‘0’
b) SCL is sampled low before SDAx is asserted during this time, a bus collision does not occur. At the
low (Figure 21-34). end of the BRG count, the SCL pin is asserted low.
During a Start condition, both the SDAx and the SCL Note: The reason that bus collision is not a fac-
pins are monitored. tor during a Start condition is that no two
If the SDA pin is already low, or the SCL pin is already bus masters can assert a Start condition
low, then all of the following occur: at the exact same time. Therefore, one
master will always assert SDAx before the
• the Start condition is aborted,
other. This condition does not cause a bus
• the BCL1IF flag is set and collision because the two masters must be
• the MSSP module is reset to its Idle state allowed to arbitrate the first address fol-
(Figure 21-33). lowing the Start condition. If the address is
The Start condition begins with the SDAx and SCLx the same, arbitration must be allowed to
pins deasserted. When the SDAx pin is sampled high, continue into the data portion, Repeated
the Baud Rate Generator is loaded and counts down. If Start or Stop conditions.
the SCLx pin is sampled low while SDAx is high, a bus
collision occurs because it is assumed that another
master is attempting to drive a data ‘1’ during the Start
condition.

FIGURE 21-33: BUS COLLISION DURING START CONDITION (SDAX ONLY)

SDAx goes low before the SEN bit is set.
Set BCLxIF,
S bit and SSPxIF set because
SDAx = 0, SCLx = 1.

SDAx

SCLx
Set SEN, enable Start SEN cleared automatically because of bus collision.
condition if SDAx = 1, SCLx = 1 SSP module reset into Idle state.
SEN
SDAx sampled low before
Start condition. Set BCLxIF.
S bit and SSPxIF set because
BCLxIF SDAx = 0, SCLx = 1.
SSPxIF and BCLxIF are
cleared by software

SSPxIF

SSPxIF and BCLxIF are

cleared by software

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 PIC16(L)F1508/9
FIGURE 21-34: BUS COLLISION DURING START CONDITION (SCLX = 0)
SDAx = 0, SCLx = 1

TBRG TBRG

SDAx

SCLx Set SEN, enable Start

sequence if SDAx = 1, SCLx = 1
SCLx = 0 before SDAx = 0,
bus collision occurs. Set BCLxIF.
SEN
SCLx = 0 before BRG time-out,
bus collision occurs. Set BCLxIF.
BCLxIF
Interrupt cleared
by software
S ‘0’ ‘0’

SSPxIF ‘0’ ‘0’

FIGURE 21-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDAx = 0, SCLx = 1
Set S Set SSPxIF
Less than TBRG
TBRG

SDAx SDAx pulled low by other master.

Reset BRG and assert SDAx.

SCLx S
SCLx pulled low after BRG
time-out
SEN
Set SEN, enable Start
sequence if SDAx = 1, SCLx = 1
BCLxIF ‘0’

SSPxIF
SDAx = 0, SCLx = 1, Interrupts cleared
set SSPxIF by software

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PIC16(L)F1508/9
21.6.13.2 Bus Collision During a Repeated If SDAx is low, a bus collision has occurred (i.e., another
Start Condition master is attempting to transmit a data ‘0’, Figure 21-36).
If SDAx is sampled high, the BRG is reloaded and
During a Repeated Start condition, a bus collision
begins counting. If SDAx goes from high-to-low before
occurs if:
the BRG times out, no bus collision occurs because no
a) A low level is sampled on SDAx when SCLx two masters can assert SDAx at exactly the same time.
goes from low level to high level (Case 1).
If SCLx goes from high-to-low before the BRG times
b) SCLx goes low before SDAx is asserted low, out and SDAx has not already been asserted, a bus
indicating that another master is attempting to collision occurs. In this case, another master is
transmit a data ‘1’ (Case 2). attempting to transmit a data ‘1’ during the Repeated
When the user releases SDAx and the pin is allowed to Start condition, see Figure 21-37.
float high, the BRG is loaded with SSPxADD and If, at the end of the BRG time-out, both SCLx and SDAx
counts down to zero. The SCLx pin is then deasserted are still high, the SDAx pin is driven low and the BRG
and when sampled high, the SDAx pin is sampled. is reloaded and begins counting. At the end of the
count, regardless of the status of the SCLx pin, the
SCLx pin is driven low and the Repeated Start
condition is complete.

FIGURE 21-36: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)

SDAx

SCLx

Sample SDAx when SCLx goes high.

If SDAx = 0, set BCLxIF and release SDAx and SCLx.

RSEN

BCLxIF

Cleared by software
S ‘0’

SSPxIF ‘0’

FIGURE 21-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)

TBRG TBRG

SDAx

SCLx

SCLx goes low before SDAx,

BCLxIF set BCLxIF. Release SDAx and SCLx.
Interrupt cleared
by software
RSEN

S ‘0’

SSPxIF

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 PIC16(L)F1508/9
21.6.13.3 Bus Collision During a Stop The Stop condition begins with SDAx asserted low.
Condition When SDAx is sampled low, the SCLx pin is allowed to
float. When the pin is sampled high (clock arbitration),
Bus collision occurs during a Stop condition if:
the Baud Rate Generator is loaded with SSPxADD and
a) After the SDAx pin has been deasserted and counts down to 0. After the BRG times out, SDAx is
allowed to float high, SDAx is sampled low after sampled. If SDAx is sampled low, a bus collision has
the BRG has timed out (Case 1). occurred. This is due to another master attempting to
b) After the SCLx pin is deasserted, SCLx is drive a data ‘0’ (Figure 21-38). If the SCLx pin is
sampled low before SDAx goes high (Case 2). sampled low before SDAx is allowed to float high, a bus
collision occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 21-39).

FIGURE 21-38: BUS COLLISION DURING A STOP CONDITION (CASE 1)

TBRG TBRG TBRG SDAx sampled

low after TBRG,
set BCLxIF
SDAx

SDAx asserted low

SCLx

PEN

BCLxIF

P ‘0’

SSPxIF ‘0’

FIGURE 21-39: BUS COLLISION DURING A STOP CONDITION (CASE 2)

TBRG TBRG TBRG

SDAx

Assert SDAx SCLx goes low before SDAx goes high,

set BCLxIF
SCLx

PEN

BCLxIF

P ‘0’

SSPxIF ‘0’

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PIC16(L)F1508/9
TABLE 21-3: SUMMARY OF REGISTERS ASSOCIATED WITH I2C™ OPERATION
Reset
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on
Page:

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE — TMR2IE TMR1IE 77
PIE2 OSFIE C2IE C1IE — BCL1IE NCO1IE — — 78
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF — TMR2IF TMR1IF 80
PIR2 OSFIF C2IF C1IF — BCL1IF NCO1IF — — 81
TRISA — — TRISA5 TRISA4 —(1) TRISA2 TRISA1 TRISA0 112
SSP1ADD ADD<7:0> 235
SSP1BUF MSSP Receive Buffer/Transmit Register 185*
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 232
SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 233
SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 234
SSP1MSK MSK<7:0> 235
SSP1STAT SMP CKE D/A P S R/W UA BF 230
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module in I2C™ mode.
* Page provides register information.
Note 1: Unimplemented, read as ‘1’.

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 PIC16(L)F1508/9
21.7 BAUD RATE GENERATOR module clock line. The logic dictating when the reload
signal is asserted depends on the mode the MSSP is
The MSSP module has a Baud Rate Generator avail- being operated in.
able for clock generation in both I2C and SPI Master
Table 21-4 demonstrates clock rates based on
modes. The Baud Rate Generator (BRG) reload value
instruction cycles and the BRG value loaded into
is placed in the SSPxADD register (Register 21-6).
SSPxADD.
When a write occurs to SSPxBUF, the Baud Rate Gen-
erator will automatically begin counting down.
EQUATION 21-1:
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will FOSC
remain in its last state. FCLOCK = -------------------------------------------------
 SSPxADD + 1   4 
An internal signal “Reload” in Figure 21-40 triggers the
value from SSPxADD to be loaded into the BRG
counter. This occurs twice for each oscillation of the

FIGURE 21-40: BAUD RATE GENERATOR BLOCK DIAGRAM

Rev. 10-000112A
7/30/2013

4
SSPM <3:0> SSPxADD<7:0>

8
4 Reload
SSPM <3:0>
SCLx Control Reload
8

FOSC/2 BRG Down Counter SSPxCLK

Note: Values of 0x00, 0x01 and 0x02 are not valid

for SSPxADD when used as a Baud Rate
Generator for I2C. This is an implementation
limitation.

TABLE 21-4: MSSP CLOCK RATE W/BRG

FCLOCK
FOSC FCY BRG Value
(Two Rollovers of BRG)
16 MHz 4 MHz 09h 400 kHz
16 MHz 4 MHz 0Ch 308 kHz
16 MHz 4 MHz 27h 100 kHz
4 MHz 1 MHz 09h 100 kHz
Note: Refer to the I/O port electrical specifications in Table 29-4 to ensure the system is designed to support lol
requirements.

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21.8 Register Definitions: MSSP Control
REGISTER 21-1: SSPxSTAT: SSP STATUS REGISTER
R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0
SMP CKE D/A P S R/W UA BF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 SMP: SPI Data Input Sample bit

SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
In I2 C Master or Slave mode:
1 = Slew rate control disabled
0 = Slew rate control enabled
bit 6 CKE: SPI Clock Edge Select bit (SPI mode only)
In SPI Master or Slave mode:
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
In I2 C™ mode only:
1 = Enable input logic so that thresholds are compliant with SMBus specification
0 = Disable SMBus specific inputs
bit 5 D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: Stop bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0 = Stop bit was not detected last
bit 3 S: Start bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0 = Start bit was not detected last
bit 2 R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the address match
to the next Start bit, Stop bit, or not ACK bit.
In I2 C Slave mode:
1 = Read
0 = Write
In I2 C Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode.
bit 1 UA: Update Address bit (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPxADD register
0 = Address does not need to be updated

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REGISTER 21-1: SSPxSTAT: SSP STATUS REGISTER (CONTINUED)
bit 0 BF: Buffer Full Status bit
Receive (SPI and I2 C modes):
1 = Receive complete, SSPxBUF is full
0 = Receive not complete, SSPxBUF is empty
Transmit (I2 C mode only):
1 = Data transmit in progress (does not include the ACK and Stop bits), SSPxBUF is full
0 = Data transmit complete (does not include the ACK and Stop bits), SSPxBUF is empty

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REGISTER 21-2: SSPxCON1: SSP CONTROL REGISTER 1

R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
WCOL SSPOV(1) SSPEN CKP SSPM<3:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared

bit 7 WCOL: Write Collision Detect bit

Master mode:
1 = A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a transmission to be started
0 = No collision
Slave mode:
1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit(1)
In SPI mode:
1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost.
Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPxBUF, even if only transmitting data, to avoid
setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the
SSPxBUF register (must be cleared in software).
0 = No overflow
2
In I C mode:
1 = A byte is received while the SSPxBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode
(must be cleared in software).
0 = No overflow
bit 5 SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output
In SPI mode:
1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as the source of the serial port pins(2)
0 = Disables serial port and configures these pins as I/O port pins
In I2C mode:
1 = Enables the serial port and configures the SDAx and SCLx pins as the source of the serial port pins(3)
0 = Disables serial port and configures these pins as I/O port pins
bit 4 CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I2C Slave mode:
SCLx release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I2C Master mode:
Unused in this mode
bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = FOSC/4
0001 = SPI Master mode, clock = FOSC/16
0010 = SPI Master mode, clock = FOSC/64
0011 = SPI Master mode, clock = T2_match/2
0100 = SPI Slave mode, clock = SCKx pin, SS pin control enabled
0101 = SPI Slave mode, clock = SCKx pin, SS pin control disabled, SSx can be used as I/O pin
0110 = I2C Slave mode, 7-bit address
0111 = I2C Slave mode, 10-bit address
1000 = I2C Master mode, clock = FOSC/(4 * (SSPxADD+1))(4)
1001 = Reserved
1010 = SPI Master mode, clock = FOSC/(4 * (SSPxADD+1))(5)
1011 = I2C firmware controlled Master mode (Slave idle)
1100 = Reserved
1101 = Reserved
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register.
2: When enabled, these pins must be properly configured as input or output.
3: When enabled, the SDAx and SCLx pins must be configured as inputs.
4: SSPxADD values of 0, 1 or 2 are not supported for I2C mode.
5: SSPxADD value of ‘0’ is not supported. Use SSPM = 0000 instead.

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REGISTER 21-3: SSPxCON2: SSP CONTROL REGISTER 2(1)

R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set

bit 7 GCEN: General Call Enable bit (in I2C Slave mode only)
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only)
1 = Acknowledge was not received
0 = Acknowledge was received
bit 5 ACKDT: Acknowledge Data bit (in I2C mode only)
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1 = Not Acknowledge
0 = Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDAx and SCLx pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
bit 3 RCEN: Receive Enable bit (in I2C Master mode only)
1 = Enables Receive mode for I2C
0 = Receive idle
bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only)
SCKx Release Control:
1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Stop condition idle
bit 1 RSEN: Repeated Start Condition Enable bit (in I2C Master mode only)
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Repeated Start condition idle
bit 0 SEN: Start Condition Enable/Stretch Enable bit
In Master mode:
1 = Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Start condition idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled

Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).

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REGISTER 21-4: SSPxCON3: SSP CONTROL REGISTER 3

R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
ACKTIM(3) PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3)

1 = Indicates the I2C bus is in an Acknowledge sequence, set on eighth falling edge of SCLx clock
0 = Not an Acknowledge sequence, cleared on ninth rising edge of SCLx clock
bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C mode only)
1 = Enable interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled(2)
bit 5 SCIE: Start Condition Interrupt Enable bit (I2C mode only)
1 = Enable interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled(2)
bit 4 BOEN: Buffer Overwrite Enable bit
In SPI Slave mode:(1)
1 = SSPxBUF updates every time that a new data byte is shifted in ignoring the BF bit
0 = If new byte is received with BF bit of the SSPxSTAT register already set, SSPOV bit of the
SSPxCON1 register is set, and the buffer is not updated
In I2C Master mode:
This bit is ignored.
In I2C Slave mode:
1 = SSPxBUF is updated and ACK is generated for a received address/data byte, ignoring the
state of the SSPOV bit only if the BF bit = 0.
0 = SSPxBUF is only updated when SSPOV is clear
bit 3 SDAHT: SDAx Hold Time Selection bit (I2C mode only)
1 = Minimum of 300 ns hold time on SDAx after the falling edge of SCLx
0 = Minimum of 100 ns hold time on SDAx after the falling edge of SCLx
bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If on the rising edge of SCLx, SDAx is sampled low when the module is outputting a high state, the
BCLxIF bit of the PIR2 register is set, and bus goes idle
1 = Enable slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only)
1 = Following the eighth falling edge of SCLx for a matching received address byte, CKP bit of the
SSPxCON1 register will be cleared and the SCLx will be held low.
0 = Address holding is disabled
bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only)
1 = Following the eighth falling edge of SCLx for a received data byte, slave hardware clears the CKP
bit of the SSPxCON1 register and SCLx is held low.
0 = Data holding is disabled

Note 1: For daisy-chained SPI operation, allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF.
2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.

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REGISTER 21-5: SSPxMSK: SSP MASK REGISTER

R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
MSK<7:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-1 MSK<7:1>: Mask bits

1 = The received address bit n is compared to SSPxADD<n> to detect I2C address match
0 = The received address bit n is not used to detect I2C address match
bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address
I2C Slave mode, 10-bit address (SSPM<3:0> = 0111 or 1111):
1 = The received address bit 0 is compared to SSPxADD<0> to detect I2C address match
0 = The received address bit 0 is not used to detect I2C address match
I2C Slave mode, 7-bit address, the bit is ignored

REGISTER 21-6: SSPxADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE)
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
ADD<7:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

Master mode:

bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits

SCLx pin clock period = ((ADD<7:0> + 1) *4)/FOSC
10-Bit Slave mode – Most Significant Address Byte:

bit 7-3 Not used: Unused for Most Significant Address Byte. Bit state of this register is a “don’t care”. Bit pat-
tern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits are
compared by hardware and are not affected by the value in this register.
bit 2-1 ADD<2:1>: Two Most Significant bits of 10-bit address
bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.
10-Bit Slave mode – Least Significant Address Byte:

bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address

7-Bit Slave mode:

bit 7-1 ADD<7:1>: 7-bit address

bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.

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PIC16(L)F1508/9
NOTES:

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 PIC16(L)F1508/9
22.0 ENHANCED UNIVERSAL The EUSART module includes the following capabilities:
SYNCHRONOUS • Full-duplex asynchronous transmit and receive
ASYNCHRONOUS RECEIVER • Two-character input buffer
TRANSMITTER (EUSART) • One-character output buffer
• Programmable 8-bit or 9-bit character length
The Enhanced Universal Synchronous Asynchronous
• Address detection in 9-bit mode
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock • Input buffer overrun error detection
generators, shift registers and data buffers necessary • Received character framing error detection
to perform an input or output serial data transfer • Half-duplex synchronous master
independent of device program execution. The • Half-duplex synchronous slave
EUSART, also known as a Serial Communications • Programmable clock polarity in synchronous
Interface (SCI), can be configured as a full-duplex modes
asynchronous system or half-duplex synchronous
• Sleep operation
system. Full-Duplex mode is useful for
communications with peripheral systems, such as CRT The EUSART module implements the following
terminals and personal computers. Half-Duplex additional features, making it ideally suited for use in
Synchronous mode is intended for communications Local Interconnect Network (LIN) bus systems:
with peripheral devices, such as A/D or D/A integrated • Automatic detection and calibration of the baud rate
circuits, serial EEPROMs or other microcontrollers.
• Wake-up on Break reception
These devices typically do not have internal clocks for
baud rate generation and require the external clock • 13-bit Break character transmit
signal provided by a master synchronous device. Block diagrams of the EUSART transmitter and
receiver are shown in Figure 22-1 and Figure 22-2.
The EUSART transmit output (TX_out) is available to
the TX/CK pin and internally to the following peripherals:
• Configurable Logic Cell (CLC)

FIGURE 22-1: EUSART TRANSMIT BLOCK DIAGRAM

Rev. 10-000113A
8/1/2013

Data bus

8 TXIE
Interrupt
TXREG register TXIF

MSb LSB TX/CK

Pin Buffer
(8) 0
and Control
Transmit Shift Register (TSR)

TX_out

TXEN
TRMT
Baud Rate Generator
FOSC ÷n TX9

n
BRG16 TX9D
+1 Multiplier x4 x16 x64

SYNC 1 x 0 0 0

BRGH x 1 1 0 0
SPBRGH SPBRGL
BRG16 x 1 0 1 0

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FIGURE 22-2: EUSART RECEIVE BLOCK DIAGRAM

Rev. 10-000114A
7/30/2013

CREN OERR RCIDL

SPEN

MSb RSR Register LSb

RX/DT pin
Pin Buffer Data
Stop (8) 7 1 0 Start
and Control Recovery

Baud Rate Generator

FOSC ÷n
RX9
BRG16
n
+1 Multiplier x4 x16 x64

SYNC 1 x 0 0 0

BRGH x 1 1 0 0
SPBRGH SPBRGL FIFO
BRG16 x 1 0 1 0 FERR RX9D RCREG Register
8
Data Bus

RCIF
Interrupt
RCIE

The operation of the EUSART module is controlled

through three registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCON)
These registers are detailed in Register 22-1,
Register 22-2 and Register 22-3, respectively.
When the receiver or transmitter section is not enabled
then the corresponding RX or TX pin may be used for
general purpose input and output.

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22.1 EUSART Asynchronous Mode 22.1.1.2 Transmitting Data
The EUSART transmits and receives data using the A transmission is initiated by writing a character to the
standard non-return-to-zero (NRZ) format. NRZ is TXREG register. If this is the first character, or the
implemented with two levels: a VOH mark state which previous character has been completely flushed from
represents a ‘1’ data bit, and a VOL space state which the TSR, the data in the TXREG is immediately
represents a ‘0’ data bit. NRZ refers to the fact that transferred to the TSR register. If the TSR still contains
consecutively transmitted data bits of the same value all or part of a previous character, the new character
stay at the output level of that bit without returning to a data is held in the TXREG until the Stop bit of the
neutral level between each bit transmission. An NRZ previous character has been transmitted. The pending
transmission port idles in the mark state. Each character character in the TXREG is then transferred to the TSR
transmission consists of one Start bit followed by eight in one TCY immediately following the Stop bit
or nine data bits and is always terminated by one or transmission. The transmission of the Start bit, data bits
more Stop bits. The Start bit is always a space and the and Stop bit sequence commences immediately
Stop bits are always marks. The most common data following the transfer of the data to the TSR from the
format is eight bits. Each transmitted bit persists for a TXREG.
period of 1/(Baud Rate). An on-chip dedicated
8-bit/16-bit Baud Rate Generator is used to derive 22.1.1.3 Transmit Data Polarity
standard baud rate frequencies from the system The polarity of the transmit data can be controlled with
oscillator. See Table 22-5 for examples of baud rate the SCKP bit of the BAUDCON register. The default
configurations. state of this bit is ‘0’ which selects high true transmit idle
The EUSART transmits and receives the LSb first. The and data bits. Setting the SCKP bit to ‘1’ will invert the
EUSART’s transmitter and receiver are functionally transmit data resulting in low true idle and data bits. The
independent, but share the same data format and baud SCKP bit controls transmit data polarity in
rate. Parity is not supported by the hardware, but can Asynchronous mode only. In Synchronous mode, the
be implemented in software and stored as the ninth SCKP bit has a different function. See Section 22.5.1.2
data bit. “Clock Polarity”.

22.1.1 EUSART ASYNCHRONOUS 22.1.1.4 Transmit Interrupt Flag

TRANSMITTER The TXIF interrupt flag bit of the PIR1 register is set
whenever the EUSART transmitter is enabled and no
The EUSART transmitter block diagram is shown in
character is being held for transmission in the TXREG.
Figure 22-1. The heart of the transmitter is the serial
In other words, the TXIF bit is only clear when the TSR
Transmit Shift Register (TSR), which is not directly
is busy with a character and a new character has been
accessible by software. The TSR obtains its data from
queued for transmission in the TXREG. The TXIF flag
the transmit buffer, which is the TXREG register.
bit is not cleared immediately upon writing TXREG.
22.1.1.1 Enabling the Transmitter TXIF becomes valid in the second instruction cycle
following the write execution. Polling TXIF immediately
The EUSART transmitter is enabled for asynchronous following the TXREG write will return invalid results. The
operations by configuring the following three control TXIF bit is read-only, it cannot be set or cleared by
bits: software.
• TXEN = 1 The TXIF interrupt can be enabled by setting the TXIE
• SYNC = 0 interrupt enable bit of the PIE1 register. However, the
• SPEN = 1 TXIF flag bit will be set whenever the TXREG is empty,
regardless of the state of TXIE enable bit.
All other EUSART control bits are assumed to be in
their default state. To use interrupts when transmitting data, set the TXIE
bit only when there is more data to send. Clear the
Setting the TXEN bit of the TXSTA register enables the
TXIE interrupt enable bit upon writing the last character
transmitter circuitry of the EUSART. Clearing the SYNC
of the transmission to the TXREG.
bit of the TXSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the EUSART and
automatically configures the TX/CK I/O pin as an output.
If the TX/CK pin is shared with an analog peripheral, the
analog I/O function must be disabled by clearing the
corresponding ANSEL bit.
Note: The TXIF Transmitter Interrupt flag is set
when the TXEN enable bit is set.

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22.1.1.5 TSR Status 22.1.1.7 Asynchronous Transmission Set-up:
The TRMT bit of the TXSTA register indicates the 1. Initialize the SPBRGH, SPBRGL register pair and
status of the TSR register. This is a read-only bit. The the BRGH and BRG16 bits to achieve the desired
TRMT bit is set when the TSR register is empty and is baud rate (see Section 22.4 “EUSART Baud
cleared when a character is transferred to the TSR Rate Generator (BRG)”).
register from the TXREG. The TRMT bit remains clear 2. Enable the asynchronous serial port by clearing
until all bits have been shifted out of the TSR register. the SYNC bit and setting the SPEN bit.
No interrupt logic is tied to this bit, so the user has to 3. If 9-bit transmission is desired, set the TX9 con-
poll this bit to determine the TSR status. trol bit. A set ninth data bit will indicate that the
Note: The TSR register is not mapped in data eight Least Significant data bits are an address
memory, so it is not available to the user. when the receiver is set for address detection.
4. Set SCKP bit if inverted transmit is desired.
22.1.1.6 Transmitting 9-Bit Characters 5. Enable the transmission by setting the TXEN
The EUSART supports 9-bit character transmissions. control bit. This will cause the TXIF interrupt bit
When the TX9 bit of the TXSTA register is set, the to be set.
EUSART will shift nine bits out for each character trans- 6. If interrupts are desired, set the TXIE interrupt
mitted. The TX9D bit of the TXSTA register is the ninth, enable bit of the PIE1 register. An interrupt will
and Most Significant, data bit. When transmitting 9-bit occur immediately provided that the GIE and
data, the TX9D data bit must be written before writing PEIE bits of the INTCON register are also set.
the eight Least Significant bits into the TXREG. All nine 7. If 9-bit transmission is selected, the ninth bit
bits of data will be transferred to the TSR shift register should be loaded into the TX9D data bit.
immediately after the TXREG is written.
8. Load 8-bit data into the TXREG register. This
A special 9-bit Address mode is available for use with will start the transmission.
multiple receivers. See Section 22.1.2.7 “Address
Detection” for more information on the address mode.

FIGURE 22-3: ASYNCHRONOUS TRANSMISSION

Write to TXREG
Word 1
BRG Output
(Shift Clock)
TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit
Word 1
TXIF bit
(Transmit Buffer 1 TCY
Reg. Empty Flag)

TRMT bit Word 1

Transmit Shift Reg.
(Transmit Shift
Reg. Empty Flag)

FIGURE 22-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)

Write to TXREG
Word 1 Word 2
BRG Output
(Shift Clock)
TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0
TXIF bit 1 TCY Word 1 Word 2
(Transmit Buffer
Reg. Empty Flag) 1 TCY
TRMT bit Word 1 Word 2
(Transmit Shift Transmit Shift Reg. Transmit Shift Reg.
Reg. Empty Flag)

Note: This timing diagram shows two consecutive transmissions.

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TABLE 22-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 249
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE — TMR2IE TMR1IE 77
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF — TMR2IF TMR1IF 80
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 248*
SPBRGL BRG<7:0> 250*
SPBRGH BRG<15:8> 250*
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 116
TXREG EUSART Transmit Data Register 239
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 247
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous transmission.
* Page provides register information.

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22.1.2 EUSART ASYNCHRONOUS 22.1.2.2 Receiving Data
RECEIVER The receiver data recovery circuit initiates character
The Asynchronous mode is typically used in RS-232 reception on the falling edge of the first bit. The first bit,
systems. The receiver block diagram is shown in also known as the Start bit, is always a zero. The data
Figure 22-2. The data is received on the RX/DT pin and recovery circuit counts one-half bit time to the center of
drives the data recovery block. The data recovery block the Start bit and verifies that the bit is still a zero. If it is
is actually a high-speed shifter operating at 16 times not a zero then the data recovery circuit aborts
the baud rate, whereas the serial Receive Shift character reception, without generating an error, and
Register (RSR) operates at the bit rate. When all eight resumes looking for the falling edge of the Start bit. If
or nine bits of the character have been shifted in, they the Start bit zero verification succeeds then the data
are immediately transferred to a two character recovery circuit counts a full bit time to the center of the
First-In-First-Out (FIFO) memory. The FIFO buffering next bit. The bit is then sampled by a majority detect
allows reception of two complete characters and the circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.
start of a third character before software must start This repeats until all data bits have been sampled and
servicing the EUSART receiver. The FIFO and RSR shifted into the RSR. One final bit time is measured and
registers are not directly accessible by software. the level sampled. This is the Stop bit, which is always
Access to the received data is via the RCREG register. a ‘1’. If the data recovery circuit samples a ‘0’ in the
Stop bit position then a framing error is set for this
22.1.2.1 Enabling the Receiver character, otherwise the framing error is cleared for this
The EUSART receiver is enabled for asynchronous character. See Section 22.1.2.4 “Receive Framing
operation by configuring the following three control bits: Error” for more information on framing errors.

• CREN = 1 Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
• SYNC = 0
to the EUSART receive FIFO and the RCIF interrupt
• SPEN = 1 flag bit of the PIR1 register is set. The top character in
All other EUSART control bits are assumed to be in the FIFO is transferred out of the FIFO by reading the
their default state. RCREG register.
Setting the CREN bit of the RCSTA register enables the Note: If the receive FIFO is overrun, no additional
receiver circuitry of the EUSART. Clearing the SYNC bit characters will be received until the overrun
of the TXSTA register configures the EUSART for condition is cleared. See Section 22.1.2.5
asynchronous operation. Setting the SPEN bit of the “Receive Overrun Error” for more
RCSTA register enables the EUSART. The programmer information on overrun errors.
must set the corresponding TRIS bit to configure the
RX/DT I/O pin as an input. 22.1.2.3 Receive Interrupts
Note: If the RX/DT function is on an analog pin, The RCIF interrupt flag bit of the PIR1 register is set
the corresponding ANSEL bit must be whenever the EUSART receiver is enabled and there is
cleared for the receiver to function. an unread character in the receive FIFO. The RCIF
interrupt flag bit is read-only, it cannot be set or cleared
by software.
RCIF interrupts are enabled by setting all of the
following bits:
• RCIE, Interrupt Enable bit of the PIE1 register
• PEIE, Peripheral Interrupt Enable bit of the
INTCON register
• GIE, Global Interrupt Enable bit of the INTCON
register
The RCIF interrupt flag bit will be set when there is an
unread character in the FIFO, regardless of the state of
interrupt enable bits.

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22.1.2.4 Receive Framing Error 22.1.2.7 Address Detection
Each character in the receive FIFO buffer has a A special Address Detection mode is available for use
corresponding framing error Status bit. A framing error when multiple receivers share the same transmission
indicates that a Stop bit was not seen at the expected line, such as in RS-485 systems. Address detection is
time. The framing error status is accessed via the enabled by setting the ADDEN bit of the RCSTA
FERR bit of the RCSTA register. The FERR bit register.
represents the status of the top unread character in the Address detection requires 9-bit character reception.
receive FIFO. Therefore, the FERR bit must be read When address detection is enabled, only characters
before reading the RCREG. with the ninth data bit set will be transferred to the
The FERR bit is read-only and only applies to the top receive FIFO buffer, thereby setting the RCIF interrupt
unread character in the receive FIFO. A framing error bit. All other characters will be ignored.
(FERR = 1) does not preclude reception of additional Upon receiving an address character, user software
characters. It is not necessary to clear the FERR bit. determines if the address matches its own. Upon
Reading the next character from the FIFO buffer will address match, user software must disable address
advance the FIFO to the next character and the next detection by clearing the ADDEN bit before the next
corresponding framing error. Stop bit occurs. When user software detects the end of
The FERR bit can be forced clear by clearing the SPEN the message, determined by the message protocol
bit of the RCSTA register which resets the EUSART. used, software places the receiver back into the
Clearing the CREN bit of the RCSTA register does not Address Detection mode by setting the ADDEN bit.
affect the FERR bit. A framing error by itself does not
generate an interrupt.
Note: If all receive characters in the receive
FIFO have framing errors, repeated reads
of the RCREG will not clear the FERR bit.

22.1.2.5 Receive Overrun Error

The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before the FIFO is accessed. When
this happens the OERR bit of the RCSTA register is
set. The characters already in the FIFO buffer can be
read but no additional characters will be received until
the error is cleared. The error must be cleared by either
clearing the CREN bit of the RCSTA register or by
resetting the EUSART by clearing the SPEN bit of the
RCSTA register.

22.1.2.6 Receiving 9-bit Characters

The EUSART supports 9-bit character reception. When
the RX9 bit of the RCSTA register is set the EUSART
will shift nine bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth and Most Significant data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the eight Least Significant bits
from the RCREG.

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22.1.2.8 Asynchronous Reception Set-up: 22.1.2.9 9-bit Address Detection Mode Set-up
1. Initialize the SPBRGH, SPBRGL register pair This mode would typically be used in RS-485 systems.
and the BRGH and BRG16 bits to achieve the To set up an Asynchronous Reception with Address
desired baud rate (see Section 22.4 “EUSART Detect Enable:
Baud Rate Generator (BRG)”). 1. Initialize the SPBRGH, SPBRGL register pair
2. Clear the ANSEL bit for the RX pin (if applicable). and the BRGH and BRG16 bits to achieve the
3. Enable the serial port by setting the SPEN bit. desired baud rate (see Section 22.4 “EUSART
The SYNC bit must be clear for asynchronous Baud Rate Generator (BRG)”).
operation. 2. Clear the ANSEL bit for the RX pin (if applicable).
4. If interrupts are desired, set the RCIE bit of the 3. Enable the serial port by setting the SPEN bit.
PIE1 register and the GIE and PEIE bits of the The SYNC bit must be clear for asynchronous
INTCON register. operation.
5. If 9-bit reception is desired, set the RX9 bit. 4. If interrupts are desired, set the RCIE bit of the
6. Enable reception by setting the CREN bit. PIE1 register and the GIE and PEIE bits of the
7. The RCIF interrupt flag bit will be set when a INTCON register.
character is transferred from the RSR to the 5. Enable 9-bit reception by setting the RX9 bit.
receive buffer. An interrupt will be generated if 6. Enable address detection by setting the ADDEN
the RCIE interrupt enable bit was also set. bit.
8. Read the RCSTA register to get the error flags 7. Enable reception by setting the CREN bit.
and, if 9-bit data reception is enabled, the ninth 8. The RCIF interrupt flag bit will be set when a
data bit. character with the ninth bit set is transferred
9. Get the received eight Least Significant data bits from the RSR to the receive buffer. An interrupt
from the receive buffer by reading the RCREG will be generated if the RCIE interrupt enable bit
register. was also set.
10. If an overrun occurred, clear the OERR flag by 9. Read the RCSTA register to get the error flags.
clearing the CREN receiver enable bit. The ninth data bit will always be set.
10. Get the received eight Least Significant data bits
from the receive buffer by reading the RCREG
register. Software determines if this is the
device’s address.
11. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
12. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.

FIGURE 22-5: ASYNCHRONOUS RECEPTION

Start Start Start
RX/DT pin bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop
bit bit bit
Rcv Shift
Reg
Rcv Buffer Reg.
Word 1 Word 2
RCREG RCREG
RCIDL

Read Rcv
Buffer Reg.
RCREG

RCIF
(Interrupt Flag)

OERR bit
CREN

Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.

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TABLE 22-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 249
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE — TMR2IE TMR1IE 77
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF — TMR2IF TMR1IF 80
RCREG EUSART Receive Data Register 242*
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 248*
SPBRGL BRG<7:0> 250*
SPBRGH BRG<15:8> 250*
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 116
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 247
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous reception.
* Page provides register information.

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22.2 Clock Accuracy with
Asynchronous Operation
The factory calibrates the internal oscillator block out-
put (INTOSC). However, the INTOSC frequency may
drift as VDD or temperature changes, and this directly
affects the asynchronous baud rate.
The Auto-Baud Detect feature (see Section 22.4.1
“Auto-Baud Detect”) can be used to compensate for
changes in the INTOSC frequency.
There may not be fine enough resolution when
adjusting the Baud Rate Generator to compensate for
a gradual change in the peripheral clock frequency.

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22.3 Register Definitions: EUSART Control
REGISTER 22-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-1/1 R/W-0/0
(1)
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 CSRC: Clock Source Select bit

Asynchronous mode:
Don’t care
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4 SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Don’t care
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.

Note 1: SREN/CREN overrides TXEN in Sync mode.

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REGISTER 22-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 SPEN: Serial Port Enable bit

1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled (held in Reset)
bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave
Don’t care
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Don’t care
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: Ninth bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.

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REGISTER 22-3: BAUDCON: BAUD RATE CONTROL REGISTER

R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 ABDOVF: Auto-Baud Detect Overflow bit

Asynchronous mode:
1 = Auto-baud timer overflowed
0 = Auto-baud timer did not overflow
Synchronous mode:
Don’t care
bit 6 RCIDL: Receive Idle Flag bit
Asynchronous mode:
1 = Receiver is idle
0 = Start bit has been received and the receiver is receiving
Synchronous mode:
Don’t care
bit 5 Unimplemented: Read as ‘0’
bit 4 SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
1 = Transmit inverted data to the TX/CK pin
0 = Transmit non-inverted data to the TX/CK pin
Synchronous mode:
1 = Data is clocked on rising edge of the clock
0 = Data is clocked on falling edge of the clock
bit 3 BRG16: 16-bit Baud Rate Generator bit
1 = 16-bit Baud Rate Generator is used
0 = 8-bit Baud Rate Generator is used
bit 2 Unimplemented: Read as ‘0’
bit 1 WUE: Wake-up Enable bit
Asynchronous mode:
1 = Receiver is waiting for a falling edge. No character will be received, RCIF bit will be set. WUE will
automatically clear after RCIF is set.
0 = Receiver is operating normally
Synchronous mode:
Don’t care
bit 0 ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete)
0 = Auto-Baud Detect mode is disabled
Synchronous mode:
Don’t care

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22.4 EUSART Baud Rate Generator EXAMPLE 22-1: CALCULATING BAUD
(BRG) RATE ERROR
The Baud Rate Generator (BRG) is an 8-bit or 16-bit For a device with FOSC of 16 MHz, desired baud rate
timer that is dedicated to the support of both the of 9600, Asynchronous mode, 8-bit BRG:
asynchronous and synchronous EUSART operation. F OS C
Desired Baud Rate = ------------------------------------------------------------------------
By default, the BRG operates in 8-bit mode. Setting the 64  [SPBRGH:SPBRGL] + 1 
BRG16 bit of the BAUDCON register selects 16-bit Solving for SPBRGH:SPBRGL:
mode.
FOSC
The SPBRGH, SPBRGL register pair determines the ---------------------------------------------
Desired Baud Rate
period of the free running baud rate timer. In X = --------------------------------------------- – 1
64
Asynchronous mode the multiplier of the baud rate
16000000
period is determined by both the BRGH bit of the TXSTA ------------------------
9600
register and the BRG16 bit of the BAUDCON register. In = ------------------------ – 1
64
Synchronous mode, the BRGH bit is ignored.
=  25.042  = 25
Table 22-3 contains the formulas for determining the
baud rate. Example 22-1 provides a sample calculation 16000000
Calculated Baud Rate = ---------------------------
for determining the baud rate and baud rate error. 64  25 + 1 

Typical baud rates and error values for various = 9615

asynchronous modes have been computed for your
convenience and are shown in Table 22-3. It may be Calc. Baud Rate – Desired Baud Rate
Error = --------------------------------------------------------------------------------------------
advantageous to use the high baud rate (BRGH = 1), Desired Baud Rate
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate
 9615 – 9600 
error. The 16-bit BRG mode is used to achieve slow = ---------------------------------- = 0.16%
9600
baud rates for fast oscillator frequencies.
Writing a new value to the SPBRGH, SPBRGL register
pair causes the BRG timer to be reset (or cleared). This
ensures that the BRG does not wait for a timer overflow
before outputting the new baud rate.
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
make sure that the receive operation is idle before
changing the system clock.

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TABLE 22-3: BAUD RATE FORMULAS
Configuration Bits
BRG/EUSART Mode Baud Rate Formula
SYNC BRG16 BRGH

0 0 0 8-bit/Asynchronous FOSC/[64 (n+1)]

0 0 1 8-bit/Asynchronous
FOSC/[16 (n+1)]
0 1 0 16-bit/Asynchronous
0 1 1 16-bit/Asynchronous
1 0 x 8-bit/Synchronous FOSC/[4 (n+1)]
1 1 x 16-bit/Synchronous
Legend: x = Don’t care, n = value of SPBRGH, SPBRGL register pair.

TABLE 22-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 249
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 248
SPBRGL BRG<7:0> 250*
SPBRGH BRG<15:8> 250*
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 247
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the Baud Rate Generator.
* Page provides register information.

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PIC16(L)F1508/9

TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES

SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz
BAUD
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — — — —
1200 1221 1.73 255 1200 0.00 239 1202 0.16 207 1200 0.00 143
2400 2404 0.16 129 2400 0.00 119 2404 0.16 103 2400 0.00 71
9600 9470 -1.36 32 9600 0.00 29 9615 0.16 25 9600 0.00 17
10417 10417 0.00 29 10286 -1.26 27 10417 0.00 23 10165 -2.42 16
19.2k 19.53k 1.73 15 19.20k 0.00 14 19.23k 0.16 12 19.20k 0.00 8
57.6k — — — 57.60k 0.00 7 — — — 57.60k 0.00 2
115.2k — — — — — — — — — — — —

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
BAUD
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — 300 0.16 207 300 0.00 191 300 0.16 51
1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12
2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — —
9600 9615 0.16 12 — — — 9600 0.00 5 — — —
10417 10417 0.00 11 10417 0.00 5 — — — — — —
19.2k — — — — — — 19.20k 0.00 2 — — —
57.6k — — — — — — 57.60k 0.00 0 — — —
115.2k — — — — — — — — — — — —

SYNC = 0, BRGH = 1, BRG16 = 0

BAUD FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — — — —
1200 — — — — — — — — — — — —
2400 — — — — — — — — — — — —
9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71
10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65
19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35
57.6k 56.82k -1.36 21 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11
115.2k 113.64k -1.36 10 115.2k 0.00 9 111.1k -3.55 8 115.2k 0.00 5

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 PIC16(L)F1508/9
TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 0

BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — 300 0.16 207
1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —

SYNC = 0, BRGH = 0, BRG16 = 1

BAUD FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 -0.01 4166 300.0 0.00 3839 300.03 0.01 3332 300.0 0.00 2303
1200 1200 -0.03 1041 1200 0.00 959 1200.5 0.04 832 1200 0.00 575
2400 2399 -0.03 520 2400 0.00 479 2398 -0.08 416 2400 0.00 287
9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71
10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65
19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35
57.6k 56.818 -1.36 21 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11
115.2k 113.636 -1.36 10 115.2k 0.00 9 111.11k -3.55 8 115.2k 0.00 5

SYNC = 0, BRGH = 0, BRG16 = 1

BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207
1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —

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PIC16(L)F1508/9
TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

BAUD FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 13332 300.0 0.00 9215
1200 1200 -0.01 4166 1200 0.00 3839 1200.1 0.01 3332 1200 0.00 2303
2400 2400 0.02 2082 2400 0.00 1919 2399.5 -0.02 1666 2400 0.00 1151
9600 9597 -0.03 520 9600 0.00 479 9592 -0.08 416 9600 0.00 287
10417 10417 0.00 479 10425 0.08 441 10417 0.00 383 10433 0.16 264
19.2k 19.23k 0.16 259 19.20k 0.00 239 19.23k 0.16 207 19.20k 0.00 143
57.6k 57.47k -0.22 86 57.60k 0.00 79 57.97k 0.64 68 57.60k 0.00 47
115.2k 116.3k 0.94 42 115.2k 0.00 39 114.29k -0.79 34 115.2k 0.00 23

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832
1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207
2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103
9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25
10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23
19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12
57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — —
115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —

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 PIC16(L)F1508/9
22.4.1 AUTO-BAUD DETECT and SPBRGL registers are clocked at 1/8th the BRG
base clock rate. The resulting byte measurement is the
The EUSART module supports automatic detection
average bit time when clocked at full speed.
and calibration of the baud rate.
Note 1: If the WUE bit is set with the ABDEN bit,
In the Auto-Baud Detect (ABD) mode, the clock to the
auto-baud detection will occur on the byte
BRG is reversed. Rather than the BRG clocking the
following the Break character (see
incoming RX signal, the RX signal is timing the BRG.
Section 22.4.3 “Auto-Wake-up on
The Baud Rate Generator is used to time the period of
Break”).
a received 55h (ASCII “U”) which is the Sync character
for the LIN bus. The unique feature of this character is 2: It is up to the user to determine that the
that it has five rising edges including the Stop bit edge. incoming character baud rate is within the
range of the selected BRG clock source.
Setting the ABDEN bit of the BAUDCON register starts
Some combinations of oscillator frequency
the auto-baud calibration sequence (Figure 22-6).
and EUSART baud rates are not possible.
While the ABD sequence takes place, the EUSART
state machine is held in Idle. On the first rising edge of 3: During the auto-baud process, the
the receive line, after the Start bit, the SPBRG begins auto-baud counter starts counting at 1.
counting up using the BRG counter clock as shown in Upon completion of the auto-baud
Table 22-6. The fifth rising edge will occur on the RX pin sequence, to achieve maximum accuracy,
at the end of the eighth bit period. At that time, an subtract 1 from the SPBRGH:SPBRGL
accumulated value totaling the proper BRG period is register pair.
left in the SPBRGH, SPBRGL register pair, the ABDEN
bit is automatically cleared and the RCIF interrupt flag TABLE 22-6: BRG COUNTER CLOCK RATES
is set. The value in the RCREG needs to be read to BRG Base BRG ABD
clear the RCIF interrupt. RCREG content should be BRG16 BRGH
Clock Clock
discarded. When calibrating for modes that do not use
the SPBRGH register the user can verify that the 0 0 FOSC/64 FOSC/512
SPBRGL register did not overflow by checking for 00h
0 1 FOSC/16 FOSC/128
in the SPBRGH register.
1 0 FOSC/16 FOSC/128
The BRG auto-baud clock is determined by the BRG16
and BRGH bits as shown in Table 22-6. During ABD, 1 1 FOSC/4 FOSC/32
both the SPBRGH and SPBRGL registers are used as Note: During the ABD sequence, SPBRGL and
a 16-bit counter, independent of the BRG16 bit setting. SPBRGH registers are both used as a 16-bit
While calibrating the baud rate period, the SPBRGH counter, independent of BRG16 setting.

FIGURE 22-6: AUTOMATIC BAUD RATE CALIBRATION

BRG Value XXXXh 0000h 001Ch

Edge #1 Edge #2 Edge #3 Edge #4 Edge #5
RX pin Start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Stop bit

BRG Clock

Set by User Auto Cleared

ABDEN bit

RCIDL

RCIF bit
(Interrupt)

Read
RCREG

SPBRGL XXh 1Ch

SPBRGH XXh 00h

Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.

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PIC16(L)F1508/9
22.4.2 AUTO-BAUD OVERFLOW 22.4.3.1 Special Considerations
During the course of automatic baud detection, the Break Character
ABDOVF bit of the BAUDCON register will be set if the To avoid character errors or character fragments
baud rate counter overflows before the fifth rising edge during a wake-up event, the wake-up character must
is detected on the RX pin. The ABDOVF bit indicates be all zeros.
that the counter has exceeded the maximum count that
can fit in the 16 bits of the SPBRGH:SPBRGL register When the wake-up is enabled the function works
pair. After the ABDOVF bit has been set, the counter independent of the low time on the data stream. If the
continues to count until the fifth rising edge is detected WUE bit is set and a valid non-zero character is
on the RX pin. Upon detecting the fifth RX edge, the received, the low time from the Start bit to the first rising
hardware will set the RCIF interrupt flag and clear the edge will be interpreted as the wake-up event. The
ABDEN bit of the BAUDCON register. The RCIF flag remaining bits in the character will be received as a
can be subsequently cleared by reading the RCREG fragmented character and subsequent characters can
register. The ABDOVF flag of the BAUDCON register result in framing or overrun errors.
can be cleared by software directly. Therefore, the initial character in the transmission must
To terminate the auto-baud process before the RCIF be all ‘0’s. This must be ten or more bit times, 13-bit
flag is set, clear the ABDEN bit then clear the ABDOVF times recommended for LIN bus, or any number of bit
bit of the BAUDCON register. The ABDOVF bit will times for standard RS-232 devices.
remain set if the ABDEN bit is not cleared first. Oscillator Start-up Time
Oscillator start-up time must be considered, especially
22.4.3 AUTO-WAKE-UP ON BREAK
in applications using oscillators with longer start-up
During Sleep mode, all clocks to the EUSART are intervals (i.e., LP, XT or HS/PLL mode). The Sync
suspended. Because of this, the Baud Rate Generator Break (or wake-up signal) character must be of
is inactive and a proper character reception cannot be sufficient length, and be followed by a sufficient
performed. The Auto-Wake-up feature allows the interval, to allow enough time for the selected oscillator
controller to wake-up due to activity on the RX/DT line. to start and provide proper initialization of the EUSART.
This feature is available only in Asynchronous mode.
WUE Bit
The Auto-Wake-up feature is enabled by setting the
The wake-up event causes a receive interrupt by
WUE bit of the BAUDCON register. Once set, the normal
setting the RCIF bit. The WUE bit is cleared in
receive sequence on RX/DT is disabled, and the
hardware by a rising edge on RX/DT. The interrupt
EUSART remains in an Idle state, monitoring for a
condition is then cleared in software by reading the
wake-up event independent of the CPU mode. A
RCREG register and discarding its contents.
wake-up event consists of a high-to-low transition on the
RX/DT line. (This coincides with the start of a Sync Break To ensure that no actual data is lost, check the RCIDL
or a wake-up signal character for the LIN protocol.) bit to verify that a receive operation is not in process
before setting the WUE bit. If a receive operation is not
The EUSART module generates an RCIF interrupt
occurring, the WUE bit may then be set just prior to
coincident with the wake-up event. The interrupt is
entering the Sleep mode.
generated synchronously to the Q clocks in normal CPU
operating modes (Figure 22-7), and asynchronously if
the device is in Sleep mode (Figure 22-8). The interrupt
condition is cleared by reading the RCREG register.
The WUE bit is automatically cleared by the low-to-high
transition on the RX line at the end of the Break. This
signals to the user that the Break event is over. At this
point, the EUSART module is in Idle mode waiting to
receive the next character.

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 PIC16(L)F1508/9
FIGURE 22-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Bit set by user Auto Cleared
WUE bit
RX/DT Line

RCIF
Cleared due to User Read of RCREG

Note 1: The EUSART remains in Idle while the WUE bit is set.

FIGURE 22-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP

Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4

OSC1
Bit Set by User Auto Cleared
WUE bit
RX/DT Line Note 1
RCIF
Cleared due to User Read of RCREG
Sleep Command Executed Sleep Ends

Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.

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PIC16(L)F1508/9
22.4.4 BREAK CHARACTER SEQUENCE 22.4.5 RECEIVING A BREAK CHARACTER
The EUSART module has the capability of sending the The Enhanced EUSART module can receive a Break
special Break character sequences that are required by character in two ways.
the LIN bus standard. A Break character consists of a The first method to detect a Break character uses the
Start bit, followed by 12 ‘0’ bits and a Stop bit. FERR bit of the RCSTA register and the received data
To send a Break character, set the SENDB and TXEN as indicated by RCREG. The Baud Rate Generator is
bits of the TXSTA register. The Break character trans- assumed to have been initialized to the expected baud
mission is then initiated by a write to the TXREG. The rate.
value of data written to TXREG will be ignored and all A Break character has been received when;
‘0’s will be transmitted.
• RCIF bit is set
The SENDB bit is automatically reset by hardware after
• FERR bit is set
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte • RCREG = 00h
following the Break character (typically, the Sync The second method uses the Auto-Wake-up feature
character in the LIN specification). described in Section 22.4.3 “Auto-Wake-up on
The TRMT bit of the TXSTA register indicates when the Break”. By enabling this feature, the EUSART will
transmit operation is active or idle, just as it does during sample the next two transitions on RX/DT, cause an
normal transmission. See Figure 22-9 for the timing of RCIF interrupt, and receive the next data byte followed
the Break character sequence. by another interrupt.
Note that following a Break character, the user will
22.4.4.1 Break and Sync Transmit Sequence typically want to enable the Auto-Baud Detect feature.
The following sequence will start a message frame For both methods, the user can set the ABDEN bit of
header made up of a Break, followed by an auto-baud the BAUDCON register before placing the EUSART in
Sync byte. This sequence is typical of a LIN bus Sleep mode.
master.
1. Configure the EUSART for the desired mode.
2. Set the TXEN and SENDB bits to enable the
Break sequence.
3. Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TXREG to load the Sync character
into the transmit FIFO buffer.
5. After the Break has been sent, the SENDB bit is
reset by hardware and the Sync character is
then transmitted.
When the TXREG becomes empty, as indicated by the
TXIF, the next data byte can be written to TXREG.

FIGURE 22-9: SEND BREAK CHARACTER SEQUENCE

Write to TXREG
Dummy Write

BRG Output
(Shift Clock)

TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit

Break
TXIF bit
(Transmit
Interrupt Flag)
TRMT bit
(Transmit Shift
Empty Flag)
SENDB Sampled Here Auto Cleared
SENDB
(send Break
control bit)

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 PIC16(L)F1508/9
22.5 EUSART Synchronous Mode Clearing the SCKP bit sets the Idle state as low. When
the SCKP bit is cleared, the data changes on the rising
Synchronous serial communications are typically used edge of each clock.
in systems with a single master and one or more
slaves. The master device contains the necessary cir- 22.5.1.3 Synchronous Master Transmission
cuitry for baud rate generation and supplies the clock
Data is transferred out of the device on the RX/DT pin.
for all devices in the system. Slave devices can take
The RX/DT and TX/CK pin output drivers are automat-
advantage of the master clock by eliminating the inter-
ically enabled when the EUSART is configured for syn-
nal clock generation circuitry.
chronous master transmit operation.
There are two signal lines in Synchronous mode: a bidi-
A transmission is initiated by writing a character to the
rectional data line and a clock line. Slaves use the
TXREG register. If the TSR still contains all or part of a
external clock supplied by the master to shift the serial
previous character the new character data is held in the
data into and out of their respective receive and trans-
TXREG until the last bit of the previous character has
mit shift registers. Since the data line is bidirectional,
been transmitted. If this is the first character, or the pre-
synchronous operation is half-duplex only. Half-duplex
vious character has been completely flushed from the
refers to the fact that master and slave devices can
TSR, the data in the TXREG is immediately transferred
receive and transmit data but not both simultaneously.
to the TSR. The transmission of the character com-
The EUSART can operate as either a master or slave
mences immediately following the transfer of the data
device.
to the TSR from the TXREG.
Start and Stop bits are not used in synchronous trans-
Each data bit changes on the leading edge of the mas-
missions.
ter clock and remains valid until the subsequent leading
clock edge.
22.5.1 SYNCHRONOUS MASTER MODE
The following bits are used to configure the EUSART Note: The TSR register is not mapped in data
for synchronous master operation: memory, so it is not available to the user.

• SYNC = 1 22.5.1.4 Synchronous Master Transmission

• CSRC = 1 Set-up:
• SREN = 0 (for transmit); SREN = 1 (for receive) 1. Initialize the SPBRGH, SPBRGL register pair
• CREN = 0 (for transmit); CREN = 1 (for receive) and the BRGH and BRG16 bits to achieve the
• SPEN = 1 desired baud rate (see Section 22.4 “EUSART
Baud Rate Generator (BRG)”).
Setting the SYNC bit of the TXSTA register configures
the device for synchronous operation. Setting the CSRC 2. Enable the synchronous master serial port by
bit of the TXSTA register configures the device as a setting bits SYNC, SPEN and CSRC.
master. Clearing the SREN and CREN bits of the RCSTA 3. Disable Receive mode by clearing bits SREN
register ensures that the device is in the Transmit mode, and CREN.
otherwise the device will be configured to receive. Setting 4. Enable Transmit mode by setting the TXEN bit.
the SPEN bit of the RCSTA register enables the 5. If 9-bit transmission is desired, set the TX9 bit.
EUSART.
6. If interrupts are desired, set the TXIE bit of the
22.5.1.1 Master Clock PIE1 register and the GIE and PEIE bits of the
INTCON register.
Synchronous data transfers use a separate clock line,
7. If 9-bit transmission is selected, the ninth bit
which is synchronous with the data. A device config-
should be loaded in the TX9D bit.
ured as a master transmits the clock on the TX/CK line.
The TX/CK pin output driver is automatically enabled 8. Start transmission by loading data to the
when the EUSART is configured for synchronous TXREG register.
transmit or receive operation. Serial data bits change
on the leading edge to ensure they are valid at the trail-
ing edge of each clock. One clock cycle is generated
for each data bit. Only as many clock cycles are gener-
ated as there are data bits.

22.5.1.2 Clock Polarity

A clock polarity option is provided for Microwire
compatibility. Clock polarity is selected with the SCKP
bit of the BAUDCON register. Setting the SCKP bit sets
the clock Idle state as high. When the SCKP bit is set,
the data changes on the falling edge of each clock.

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PIC16(L)F1508/9
FIGURE 22-10: SYNCHRONOUS TRANSMISSION

RX/DT
pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7
Word 1 Word 2
TX/CK pin
(SCKP = 0)

TX/CK pin
(SCKP = 1)
Write to
TXREG Reg Write Word 1 Write Word 2
TXIF bit
(Interrupt Flag)

TRMT bit

‘1’ ‘1’
TXEN bit

Note: Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.

FIGURE 22-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7

TX/CK pin

Write to
TXREG reg

TXIF bit

TRMT bit

TXEN bit

TABLE 22-7: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER

TRANSMISSION
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 249
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE — TMR2IE TMR1IE 77
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF — TMR2IF TMR1IF 80
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 248
SPBRGL BRG<7:0> 250*
SPBRGH BRG<15:8> 250*
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 116
TXREG EUSART Transmit Data Register 239*
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 247
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master transmission.
* Page provides register information.

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 PIC16(L)F1508/9
22.5.1.5 Synchronous Master Reception buffer can be read, however, no additional characters
will be received until the error is cleared. The OERR bit
Data is received at the RX/DT pin. The RX/DT pin
can only be cleared by clearing the overrun condition.
output driver is automatically disabled when the
If the overrun error occurred when the SREN bit is set
EUSART is configured for synchronous master receive
and CREN is clear then the error is cleared by reading
operation.
RCREG. If the overrun occurred when the CREN bit is
In Synchronous mode, reception is enabled by setting set then the error condition is cleared by either clearing
either the Single Receive Enable bit (SREN of the the CREN bit of the RCSTA register or by clearing the
RCSTA register) or the Continuous Receive Enable bit SPEN bit which resets the EUSART.
(CREN of the RCSTA register).
When SREN is set and CREN is clear, only as many 22.5.1.8 Receiving 9-bit Characters
clock cycles are generated as there are data bits in a The EUSART supports 9-bit character reception. When
single character. The SREN bit is automatically cleared the RX9 bit of the RCSTA register is set the EUSART
at the completion of one character. When CREN is set, will shift 9-bits into the RSR for each character
clocks are continuously generated until CREN is received. The RX9D bit of the RCSTA register is the
cleared. If CREN is cleared in the middle of a character ninth, and Most Significant, data bit of the top unread
the CK clock stops immediately and the partial charac- character in the receive FIFO. When reading 9-bit data
ter is discarded. If SREN and CREN are both set, then from the receive FIFO buffer, the RX9D data bit must
SREN is cleared at the completion of the first character be read before reading the eight Least Significant bits
and CREN takes precedence. from the RCREG.
To initiate reception, set either SREN or CREN. Data is
sampled at the RX/DT pin on the trailing edge of the 22.5.1.9 Synchronous Master Reception
TX/CK clock pin and is shifted into the Receive Shift Set-up:
Register (RSR). When a complete character is 1. Initialize the SPBRGH, SPBRGL register pair for
received into the RSR, the RCIF bit is set and the char- the appropriate baud rate. Set or clear the
acter is automatically transferred to the two character BRGH and BRG16 bits, as required, to achieve
receive FIFO. The Least Significant eight bits of the top the desired baud rate.
character in the receive FIFO are available in RCREG. 2. Clear the ANSEL bit for the RX pin (if applicable).
The RCIF bit remains set as long as there are unread
3. Enable the synchronous master serial port by
characters in the receive FIFO.
setting bits SYNC, SPEN and CSRC.
Note: If the RX/DT function is on an analog pin, 4. Ensure bits CREN and SREN are clear.
the corresponding ANSEL bit must be 5. If interrupts are desired, set the RCIE bit of the
cleared for the receiver to function. PIE1 register and the GIE and PEIE bits of the
INTCON register.
22.5.1.6 Slave Clock
6. If 9-bit reception is desired, set bit RX9.
Synchronous data transfers use a separate clock line, 7. Start reception by setting the SREN bit or for
which is synchronous with the data. A device configured continuous reception, set the CREN bit.
as a slave receives the clock on the TX/CK line. The
8. Interrupt flag bit RCIF will be set when reception
TX/CK pin output driver is automatically disabled when
of a character is complete. An interrupt will be
the device is configured for synchronous slave transmit
generated if the enable bit RCIE was set.
or receive operation. Serial data bits change on the
leading edge to ensure they are valid at the trailing edge 9. Read the RCSTA register to get the ninth bit (if
of each clock. One data bit is transferred for each clock enabled) and determine if any error occurred
cycle. Only as many clock cycles should be received as during reception.
there are data bits. 10. Read the 8-bit received data by reading the
RCREG register.
Note: If the device is configured as a slave and
11. If an overrun error occurs, clear the error by
the TX/CK function is on an analog pin, the
either clearing the CREN bit of the RCSTA
corresponding ANSEL bit must be
register or by clearing the SPEN bit which resets
cleared.
the EUSART.
22.5.1.7 Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before RCREG is read to access
the FIFO. When this happens the OERR bit of the
RCSTA register is set. Previous data in the FIFO will
not be overwritten. The two characters in the FIFO

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PIC16(L)F1508/9
FIGURE 22-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

RX/DT
pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7

TX/CK pin
(SCKP = 0)

TX/CK pin
(SCKP = 1)

Write to
bit SREN

SREN bit

CREN bit ‘0’ ‘0’

RCIF bit
(Interrupt)
Read
RCREG

Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.

TABLE 22-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER

RECEPTION
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 249
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE — TMR2IE TMR1IE 77
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF — TMR2IF TMR1IF 80
RCREG EUSART Receive Data Register 242*
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 248
SPBRGL BRG<7:0> 250*
SPBRGH BRG<15:8> 250*
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 116
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 247
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master reception.
* Page provides register information.

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 PIC16(L)F1508/9
22.5.2 SYNCHRONOUS SLAVE MODE If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
The following bits are used to configure the EUSART
for synchronous slave operation: 1. The first character will immediately transfer to
the TSR register and transmit.
• SYNC = 1
2. The second word will remain in the TXREG
• CSRC = 0
register.
• SREN = 0 (for transmit); SREN = 1 (for receive)
3. The TXIF bit will not be set.
• CREN = 0 (for transmit); CREN = 1 (for receive)
4. After the first character has been shifted out of
• SPEN = 1 TSR, the TXREG register will transfer the second
Setting the SYNC bit of the TXSTA register configures character to the TSR and the TXIF bit will now be
the device for synchronous operation. Clearing the set.
CSRC bit of the TXSTA register configures the device as 5. If the PEIE and TXIE bits are set, the interrupt
a slave. Clearing the SREN and CREN bits of the RCSTA will wake the device from Sleep and execute the
register ensures that the device is in the Transmit mode, next instruction. If the GIE bit is also set, the
otherwise the device will be configured to receive. Setting program will call the Interrupt Service Routine.
the SPEN bit of the RCSTA register enables the
EUSART. 22.5.2.2 Synchronous Slave Transmission
Set-up:
22.5.2.1 EUSART Synchronous Slave
1. Set the SYNC and SPEN bits and clear the
Transmit
CSRC bit.
The operation of the Synchronous Master and Slave 2. Clear the ANSEL bit for the CK pin (if applicable).
modes are identical (see Section 22.5.1.3
3. Clear the CREN and SREN bits.
“Synchronous Master Transmission”), except in the
case of the Sleep mode. 4. If interrupts are desired, set the TXIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
5. If 9-bit transmission is desired, set the TX9 bit.
6. Enable transmission by setting the TXEN bit.
7. If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
8. Start transmission by writing the Least
Significant eight bits to the TXREG register.

TABLE 22-9: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE

TRANSMISSION
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 249
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE — TMR2IE TMR1IE 77
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF — TMR2IF TMR1IF 80
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 248
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 116
TXREG EUSART Transmit Data Register 239*
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 247
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
* Page provides register information.

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PIC16(L)F1508/9
22.5.2.3 EUSART Synchronous Slave 22.5.2.4 Synchronous Slave Reception
Reception Set-up:
The operation of the Synchronous Master and Slave 1. Set the SYNC and SPEN bits and clear the
modes is identical (Section 22.5.1.5 “Synchronous CSRC bit.
Master Reception”), with the following exceptions: 2. Clear the ANSEL bit for both the CK and DT pins
• Sleep (if applicable).
• CREN bit is always set, therefore the receiver is 3. If interrupts are desired, set the RCIE bit of the
never idle PIE1 register and the GIE and PEIE bits of the
• SREN bit, which is a “don’t care” in Slave mode INTCON register.
4. If 9-bit reception is desired, set the RX9 bit.
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the 5. Set the CREN bit to enable reception.
word is received, the RSR register will transfer the data 6. The RCIF bit will be set when reception is
to the RCREG register. If the RCIE enable bit is set, the complete. An interrupt will be generated if the
interrupt generated will wake the device from Sleep RCIE bit was set.
and execute the next instruction. If the GIE bit is also 7. If 9-bit mode is enabled, retrieve the Most
set, the program will branch to the interrupt vector. Significant bit from the RX9D bit of the RCSTA
register.
8. Retrieve the eight Least Significant bits from the
receive FIFO by reading the RCREG register.
9. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.

TABLE 22-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE

RECEPTION
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 249
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE — TMR2IE TMR1IE 77
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF — TMR2IF TMR1IF 80
RCREG EUSART Receive Data Register 242*
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 248
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 116
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 247
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave reception.
* Page provides register information.

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 PIC16(L)F1508/9
23.0 PULSE WIDTH MODULATION Figure 23-1 shows a simplified block diagram of PWM
operation.
(PWM) MODULE
For a step-by-step procedure on how to set up this
The PWM module generates a Pulse-Width Modulated module for PWM operation, refer to Section 23.1.9
signal determined by the duty cycle, period, and reso- “Setup for PWM Operation using PWMx Pins”.
lution that are configured by the following registers:
• PR2
• T2CON
• PWMxDCH
• PWMxDCL
• PWMxCON

FIGURE 23-1: SIMPLIFIED PWM BLOCK DIAGRAM

Rev. 10-000022A
8/5/2013

Duty cycle registers PWMxDCL<7:6>

PWMxDCH

PWMx_out
To Peripherals
10-bit Latch
(Not visible to user)
PWMxOE

Comparator R Q
0
PWMx
1
S Q
TMR2 Module
R PWMxPOL TRIS Control
TMR2 (1)

Comparator
T2_match

PR2

Note 1: 8-bit timer is concatenated with two bits generated by Fosc or two bits of the internal prescaler to
create 10-bit time-base.

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23.1 PWMx Pin Configuration When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
All PWM outputs are multiplexed with the PORT data
latch. The user must configure the pins as outputs by • TMR2 is cleared
clearing the associated TRIS bits. • The PWM output is active. (Exception: When the
PWM duty cycle = 0%, the PWM output will
Note: Clearing the PWMxOE bit will relinquish remain inactive.)
control of the PWMx pin.
• The PWMxDCH and PWMxDCL register values
are latched into the buffers.
23.1.1 FUNDAMENTAL OPERATION
Note: The Timer2 postscaler has no effect on
The PWM module produces a 10-bit resolution output. the PWM operation.
Timer2 and PR2 set the period of the PWM. The
PWMxDCL and PWMxDCH registers configure the
23.1.4 PWM DUTY CYCLE
duty cycle. The period is common to all PWM modules,
whereas the duty cycle is independently controlled. The PWM duty cycle is specified by writing a 10-bit
value to the PWMxDCH and PWMxDCL register pair.
Note: The Timer2 postscaler is not used in the The PWMxDCH register contains the eight MSbs and
determination of the PWM frequency. The the PWMxDCL<7:6>, the two LSbs. The PWMxDCH
postscaler could be used to have a servo and PWMxDCL registers can be written to at any time.
update rate at a different frequency than
the PWM output. Equation 23-2 is used to calculate the PWM pulse width.

All PWM outputs associated with Timer2 are set when Equation 23-3 is used to calculate the PWM duty cycle
TMR2 is cleared. Each PWMx is cleared when TMR2 ratio.
is equal to the value specified in the corresponding
PWMxDCH (8 MSb) and PWMxDCL<7:6> (2 LSb) reg- EQUATION 23-2: PULSE WIDTH
isters. When the value is greater than or equal to PR2,
the PWM output is never cleared (100% duty cycle). Pulse Width =  PWMxDCH:PWMxDCL<7:6>  

Note: The PWMxDCH and PWMxDCL registers T OS C  (TMR2 Prescale Value)

are double buffered. The buffers are
updated when Timer2 matches PR2. Care Note: TOSC = 1/FOSC
should be taken to update both registers
before the timer match occurs.
EQUATION 23-3: DUTY CYCLE RATIO
23.1.2 PWM OUTPUT POLARITY
 PWMxDCH:PWMxDCL<7:6> 
The output polarity is inverted by setting the PWMxPOL Duty Cycle Ratio = -----------------------------------------------------------------------------------
4  PR2 + 1 
bit of the PWMxCON register.

23.1.3 PWM PERIOD The 8-bit timer TMR2 register is concatenated with the
The PWM period is specified by the PR2 register of two Least Significant bits of 1/FOSC, adjusted by the
Timer2. The PWM period can be calculated using the Timer2 prescaler to create the 10-bit time base. The
formula of Equation 23-1. system clock is used if the Timer2 prescaler is set to 1:1.
Figure 23-2 shows a waveform of the PWM signal when
EQUATION 23-1: PWM PERIOD the duty cycle is set for the smallest possible pulse.

PWM Period =   PR2  + 1   4  T OSC  FIGURE 23-2: PWM OUTPUT

(TMR2 Prescale Value)
Q1 Q2 Q3 Q4 Rev. 10-000023A
7/30/2013

Note: TOSC = 1/FOSC

FOSC

PWM Pulse Width

TMR2 = 0

TMR2 = PWMxDC

TMR2 = PR2

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 PIC16(L)F1508/9
23.1.5 PWM RESOLUTION
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit resolu-
tion will result in 1024 discrete duty cycles, whereas an
8-bit resolution will result in 256 discrete duty cycles.
The maximum PWM resolution is ten bits when PR2 is
255. The resolution is a function of the PR2 register
value as shown by Equation 23-4.

EQUATION 23-4: PWM RESOLUTION

log  4  PR2 + 1  
Resolution = ------------------------------------------ bits
log  2 

Note: If the pulse width value is greater than the

period the assigned PWM pin(s) will
remain unchanged.

TABLE 23-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)

PWM Frequency 0.31 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescale 64 4 1 1 1 1
PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 6.6

TABLE 23-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)

PWM Frequency 0.31 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz
Timer Prescale 64 4 1 1 1 1
PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09
Maximum Resolution (bits) 8 8 8 6 5 5

23.1.6 OPERATION IN SLEEP MODE

In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the
PWMx pin is driving a value, it will continue to drive that
value. When the device wakes up, TMR2 will continue
from its previous state.

23.1.7 CHANGES IN SYSTEM CLOCK

FREQUENCY
The PWM frequency is derived from the system clock
frequency (FOSC). Any changes in the system clock fre-
quency will result in changes to the PWM frequency.
Refer to Section 5.0 “Oscillator Module (With
Fail-Safe Clock Monitor)” for additional details.

23.1.8 EFFECTS OF RESET

Any Reset will force all ports to Input mode and the
PWM registers to their Reset states.

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PIC16(L)F1508/9
23.1.9 SETUP FOR PWM OPERATION
USING PWMx PINS
The following steps should be taken when configuring
the module for PWM operation using the PWMx pins:
1. Disable the PWMx pin output driver(s) by setting
the associated TRIS bit(s).
2. Clear the PWMxCON register.
3. Load the PR2 register with the PWM period
value.
4. Clear the PWMxDCH register and bits <7:6> of
the PWMxDCL register.
5. Configure and start Timer2:
• Clear the TMR2IF interrupt flag bit of the
PIR1 register. See note below.
• Configure the T2CKPS bits of the T2CON
register with the Timer2 prescale value.
• Enable Timer2 by setting the TMR2ON bit of
the T2CON register.
6. Enable PWM output pin and wait until Timer2
overflows, TMR2IF bit of the PIR1 register is set.
See note below.
7. Enable the PWMx pin output driver(s) by clear-
ing the associated TRIS bit(s) and setting the
PWMxOE bit of the PWMxCON register.
8. Configure the PWM module by loading the
PWMxCON register with the appropriate values.
Note 1: In order to send a complete duty cycle
and period on the first PWM output, the
above steps must be followed in the order
given. If it is not critical to start with a
complete PWM signal, then move Step 8
to replace Step 4.
2: For operation with other peripherals only,
disable PWMx pin outputs.

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 PIC16(L)F1508/9
23.2 Register Definitions: PWM Control

REGISTER 23-1: PWMxCON: PWM CONTROL REGISTER

R/W-0/0 R/W-0/0 R-0/0 R/W-0/0 U-0 U-0 U-0 U-0
PWMxEN PWMxOE PWMxOUT PWMxPOL — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 PWMxEN: PWM Module Enable bit

1 = PWM module is enabled
0 = PWM module is disabled
bit 6 PWMxOE: PWM Module Output Enable bit
1 = Output to PWMx pin is enabled
0 = Output to PWMx pin is disabled
bit 5 PWMxOUT: PWM Module Output Value bit
bit 4 PWMxPOL: PWMx Output Polarity Select bit
1 = PWM output is active low
0 = PWM output is active high
bit 3-0 Unimplemented: Read as ‘0’

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PIC16(L)F1508/9

REGISTER 23-2: PWMxDCH: PWM DUTY CYCLE HIGH BITS

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
PWMxDCH<7:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 PWMxDCH<7:0>: PWM Duty Cycle Most Significant bits

These bits are the MSbs of the PWM duty cycle. The two LSbs are found in the PWMxDCL register.

REGISTER 23-3: PWMxDCL: PWM DUTY CYCLE LOW BITS

R/W-x/u R/W-x/u U-0 U-0 U-0 U-0 U-0 U-0
PWMxDCL<7:6> — — — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 PWMxDCL<7:6>: PWM Duty Cycle Least Significant bits

These bits are the LSbs of the PWM duty cycle. The MSbs are found in the PWMxDCH register.
bit 5-0 Unimplemented: Read as ‘0’

TABLE 23-3: SUMMARY OF REGISTERS ASSOCIATED WITH PWM

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

PR2 Timer2 module Period Register 177*

PWM1CON PWM1EN PWM1OE PWM1OUT PWM1POL — — — — 269
PWM1DCH PWM1DCH<7:0> 270
PWM1DCL PWM1DCL<7:6> — — — — — — 270
PWM2CON PWM2EN PWM2OE PWM2OUT PWM2POL — — — — 269
PWM2DCH PWM2DCH<7:0> 270
PWM2DCL PWM2DCL<7:6> — — — — — — 270
PWM3CON PWM3EN PWM3OE PWM3OUT PWM3POL — — — — 269
PWM3DCH PWM3DCH<7:0> 270
PWM3DCL PWM3DCL<7:6> — — — — — — 270
PWM4CON PWM4EN PWM4OE PWM4OUT PWM4POL — — — — 269
PWM4DCH PWM4DCH<7:0> 270
PWM4DCL PWM4DCL<7:6> — — — — — — 270
T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 179
TMR2 Timer2 module Register 177*
TRISA — — TRISA5 TRISA4 —(1) TRISA2 TRISA1 TRISA0 112
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 120
Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the PWM.
* Page provides register information.
Note 1: Unimplemented, read as ‘1’.

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 PIC16(L)F1508/9
24.0 CONFIGURABLE LOGIC CELL Refer to Figure 24-1 for a simplified diagram showing
signal flow through the CLCx.
(CLC)
Possible configurations include:
The Configurable Logic Cell (CLCx) provides program-
mable logic that operates outside the speed limitations • Combinatorial Logic
of software execution. The logic cell takes up to 16 - AND
input signals, and through the use of configurable - NAND
gates, reduces the 16 inputs to four logic lines that - AND-OR
drive one of eight selectable single-output logic func- - AND-OR-INVERT
tions.
- OR-XOR
Input sources are a combination of the following: - OR-XNOR
• I/O pins • Latches
• Internal clocks - S-R
• Peripherals - Clocked D with Set and Reset
• Register bits - Transparent D with Set and Reset
The output can be directed internally to peripherals and - Clocked J-K with Reset
to an output pin.

FIGURE 24-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM

Rev. 10-000025A
8/1/2013

LCxOUT
D Q
MLCxOUT

Q1
LCx_in[0]
LCx_in[1]
to Peripherals
LCx_in[2]
Input Data Selection Gates(1)

LCx_in[3]
LCx_in[4] LCxEN LCxOE
LCx_in[5] lcxg1
TRIS Control
LCx_in[6] lcxg2 Logic lcxq LCx_out
LCx_in[7]
lcxg3 Function CLCx
LCx_in[8] (2)
LCx_in[9] lcxg4
LCx_in[10]
LCxPOL
LCx_in[11]
LCx_in[12]
LCxMODE<2:0> Interrupt
LCx_in[13]
LCx_in[14] det
LCx_in[15]
LCXINTP
set bit
LCXINTN CLCxIF
Interrupt
det

Note 1: See Figure 24-2.

2: See Figure 24-3.

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PIC16(L)F1508/9
24.1 CLCx Setup each case, paired with a different group. This arrange-
ment makes possible selection of up to two from a
Programming the CLCx module is performed by config- group without precluding a selection from another
uring the four stages in the logic signal flow. The four group.
stages are:
Data selection is through four multiplexers as indicated
• Data selection on the left side of Figure 24-2. Data inputs in the figure
• Data gating are identified by a generic numbered input name.
• Logic function selection Table 24-1 correlates the generic input name to the
• Output polarity actual signal for each CLC module. The columns labeled
Each stage is setup at run time by writing to the corre- lcxd1 through lcxd4 indicate the MUX output for the
sponding CLCx Special Function Registers. This has selected data input. D1S through D4S are abbreviations
the added advantage of permitting logic reconfiguration for the MUX select input codes: LCxD1S<2:0> through
on-the-fly during program execution. LCxD4S<2:0>, respectively. Selecting a data input in a
column excludes all other inputs in that column.
24.1.1 DATA SELECTION Data inputs are selected with CLCxSEL0 and
There are 16 signals available as inputs to the configu- CLCxSEL1 registers (Register 24-3 and Register 24-5,
rable logic. Four 8-input multiplexers are used to select respectively).
the inputs to pass on to the next stage. The 16 inputs Note: Data selections are undefined at power-up.
to the multiplexers are arranged in groups of four. Each
group is available to two of the four multiplexers, in

TABLE 24-1: CLCx DATA INPUT SELECTION

lcxd1 lcxd2 lcxd3 lcxd4
Data Input CLC 1 CLC 2 CLC 3 CLC 4
D1S D2S D3S D4S
LCx_in[0] 000 — — 100 CLC1IN0 CLC2IN0 CLC3IN0 CLC4IN0
LCx_in[1] 001 — — 101 CLC1IN1 CLC2IN1 CLC3IN1 CLC4IN1
LCx_in[2] 010 — — 110 C1OUT_sync C1OUT_sync C1OUT_sync C1OUT_sync
LCx_in[3] 011 — — 111 C2OUT_sync C2OUT_sync C2OUT_sync C2OUT_sync
LCx_in[4] 100 000 — — FOSC FOSC FOSC FOSC
LCx_in[5] 101 001 — — T0_overflow T0_overflow T0_overflow T0_overflow
LCx_in[6] 110 010 — — T1_overflow T1_overflow T1_overflow T1_overflow
LCx_in[7] 111 011 — — T2_match T2_match T2_match T2_match
LCx_in[8] — 100 000 — LC1_out LC1_out LC1_out LC1_out
LCx_in[9] — 101 001 — LC2_out LC2_out LC2_out LC2_out
LCx_in[10] — 110 010 — LC3_out LC3_out LC3_out LC3_out
LCx_in[11] — 111 011 — LC4_out LC4_out LC4_out LC4_out
LCx_in[12] — — 100 000 NCO1_out LFINTOSC TX_out SCK_output
(EUSART) (MSSP)
LCx_in[13] — — 101 001 HFINTOSC FRC LFINTOSC SDO_output
(MSSP)
LCx_in[14] — — 110 010 PWM3_out PWM1_out PWM2_out PWM1_out
LCx_in[15] — — 111 011 PWM4_out PWM2_out PWM3_out PWM4_out

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 PIC16(L)F1508/9
24.1.2 DATA GATING Data gating is indicated in the right side of Figure 24-2.
Only one gate is shown in detail. The remaining three
Outputs from the input multiplexers are directed to the
gates are configured identically with the exception that
desired logic function input through the data gating
the data enables correspond to the enables for that
stage. Each data gate can direct any combination of
gate.
the four selected inputs.
Note: Data gating is undefined at power-up. 24.1.3 LOGIC FUNCTION
The gate stage is more than just signal direction. The There are eight available logic functions including:
gate can be configured to direct each input signal as • AND-OR
inverted or non-inverted data. Directed signals are • OR-XOR
ANDed together in each gate. The output of each gate
• AND
can be inverted before going on to the logic function
stage. • S-R Latch
• D Flip-Flop with Set and Reset
The gating is in essence a 1-to-4 input
AND/NAND/OR/NOR gate. When every input is • D Flip-Flop with Reset
inverted and the output is inverted, the gate is an OR of • J-K Flip-Flop with Reset
all enabled data inputs. When the inputs and output are • Transparent Latch with Set and Reset
not inverted, the gate is an AND or all enabled inputs. Logic functions are shown in Figure 24-3. Each logic
Table 24-2 summarizes the basic logic that can be function has four inputs and one output. The four inputs
obtained in gate 1 by using the gate logic select bits. are the four data gate outputs of the previous stage.
The table shows the logic of four input variables, but The output is fed to the inversion stage and from there
to other peripherals, an output pin, and back to the
each gate can be configured to use less than four. If
CLCx itself.
no inputs are selected, the output will be zero or one,
depending on the gate output polarity bit. 24.1.4 OUTPUT POLARITY
TABLE 24-2: DATA GATING LOGIC The last stage in the configurable logic cell is the output
polarity. Setting the LCxPOL bit of the CLCxCON reg-
CLCxGLS0 LCxG1POL Gate Logic ister inverts the output signal from the logic stage.
0x55 1 AND Changing the polarity while the interrupts are enabled
will cause an interrupt for the resulting output transition.
0x55 0 NAND
0xAA 1 NOR
0xAA 0 OR
0x00 0 Logic 0
0x00 1 Logic 1

It is possible (but not recommended) to select both the

true and negated values of an input. When this is done,
the gate output is zero, regardless of the other inputs,
but may emit logic glitches (transient-induced pulses).
If the output of the channel must be zero or one, the
recommended method is to set all gate bits to zero and
use the gate polarity bit to set the desired level.
Data gating is configured with the logic gate select
registers as follows:
• Gate 1: CLCxGLS0 (Register 24-5)
• Gate 2: CLCxGLS1 (Register 24-6)
• Gate 3: CLCxGLS2 (Register 24-7)
• Gate 4: CLCxGLS3 (Register 24-8)
Register number suffixes are different than the gate
numbers because other variations of this module have
multiple gate selections in the same register.

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24.1.5 CLCx SETUP STEPS 24.2 CLCx Interrupts
The following steps should be followed when setting up An interrupt will be generated upon a change in the
the CLCx: output value of the CLCx when the appropriate interrupt
• Disable CLCx by clearing the LCxEN bit. enables are set. A rising edge detector and a falling
• Select desired inputs using CLCxSEL0 and edge detector are present in each CLC for this purpose.
CLCxSEL1 registers (See Table 24-1). The CLCxIF bit of the associated PIR registers will be
• Clear any associated ANSEL bits. set when either edge detector is triggered and its asso-
• Set all TRIS bits associated with inputs. ciated enable bit is set. The LCxINTP enables rising
• Clear all TRIS bits associated with outputs. edge interrupts and the LCxINTN bit enables falling
edge interrupts. Both are located in the CLCxCON
• Enable the chosen inputs through the four gates
register.
using CLCxGLS0, CLCxGLS1, CLCxGLS2, and
CLCxGLS3 registers. To fully enable the interrupt, set the following bits:
• Select the gate output polarities with the • LCxON bit of the CLCxCON register
LCxPOLy bits of the CLCxPOL register. • CLCxIE bit of the associated PIE registers
• Select the desired logic function with the • LCxINTP bit of the CLCxCON register (for a rising
LCxMODE<2:0> bits of the CLCxCON register. edge detection)
• Select the desired polarity of the logic output with • LCxINTN bit of the CLCxCON register (for a
the LCxPOL bit of the CLCxPOL register. (This falling edge detection)
step may be combined with the previous gate
• PEIE and GIE bits of the INTCON register
output polarity step).
• If driving a device, set the desired pin PPS control The CLCxIF bit of the associated PIR registers, must
register and also clear the TRIS bit corresponding be cleared in software as part of the interrupt service. If
to that output. another edge is detected while this flag is being
cleared, the flag will still be set at the end of the
• If interrupts are desired, configure the following
sequence.
bits:
- Set the LCxINTP bit in the CLCxCON register
24.3 Output Mirror Copies
for rising event.
- Set the LCxINTN bit in the CLCxCON Mirror copies of all LCxCON output bits are contained
register or falling event. in the CLCxDATA register. Reading this register reads
- Set the CLCxIE bit of the associated PIE the outputs of all CLCs simultaneously. This prevents
registers. any reading skew introduced by testing or reading the
CLCxOUT bits in the individual CLCxCON registers.
- Set the GIE and PEIE bits of the INTCON
register.
• Enable the CLCx by setting the LCxEN bit of the
24.4 Effects of a Reset
CLCxCON register. The CLCxCON register is cleared to zero as the result
of a Reset. All other selection and gating values remain
unchanged.

24.5 Operation During Sleep

The CLC module operates independently from the
system clock and will continue to run during Sleep,
provided that the input sources selected remain active.
The HFINTOSC remains active during Sleep when the
CLC module is enabled and the HFINTOSC is
selected as an input source, regardless of the system
clock source selected.
In other words, if the HFINTOSC is simultaneously
selected as the system clock and as a CLC input
source, when the CLC is enabled, the CPU will go idle
during Sleep, but the CLC will continue to operate and
the HFINTOSC will remain active.
This will have a direct effect on the Sleep mode current.

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FIGURE 24-2: INPUT DATA SELECTION AND GATING

Data Selection
LCx_in[0] 00000

Data GATE 1

lcxd1T LCxD1G1T

lcxd1N LCxD1G1N
LCx_in[31] 11111
LCxD2G1T
LCxD1S<4:0>

LCxD2G1N lcxg1
LCx_in[0] 00000
LCxD3G1T
LCxG1POL
lcxd2T
LCxD3G1N
lcxd2N
LCxD4G1T
LCx_in[31] 11111

LCxD2S<4:0> LCxD4G1N

LCx_in[0] 00000
Data GATE 2
lcxg2
lcxd3T
(Same as Data GATE 1)
lcxd3N
Data GATE 3
LCx_in[31] 11111
lcxg3
LCxD3S<4:0>
(Same as Data GATE 1)

LCx_in[0] 00000 Data GATE 4

lcxg4

lcxd4T (Same as Data GATE 1)

lcxd4N

LCx_in[31] 11111

LCxD4S<4:0>

Note: All controls are undefined at power-up.

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FIGURE 24-3: PROGRAMMABLE LOGIC FUNCTIONS
Rev. 10-000122A
7/30/2013

AND-OR OR-XOR

lcxg1 lcxg1

lcxg2 lcxg2
lcxq lcxq
lcxg3 lcxg3

lcxg4 lcxg4

LCxMODE<2:0> = 000 LCxMODE<2:0> = 001

4-input AND S-R Latch

lcxg1 lcxg1
S Q lcxq
lcxg2
lcxg2
lcxq
lcxg3
lcxg3
R
lcxg4 lcxg4

LCxMODE<2:0> = 010 LCxMODE<2:0> = 011

1-Input D Flip-Flop with S and R 2-Input D Flip-Flop with R

lcxg4
S
lcxg4
lcxg2 D Q lcxq D Q lcxq
lcxg2

lcxg1 R
lcxg1 R
lcxg3 lcxg3

LCxMODE<2:0> = 100 LCxMODE<2:0> = 101

J-K Flip-Flop with R 1-Input Transparent Latch with S and R

lcxg4
lcxg2 J Q lcxq S
lcxg2 D Q lcxq
lcxg1

lcxg4 K
R
lcxg3 LE
R
lcxg3
lcxg1

LCxMODE<2:0> = 110 LCxMODE<2:0> = 111

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24.6 Register Definitions: CLC Control

REGISTER 24-1: CLCxCON: CONFIGURABLE LOGIC CELL CONTROL REGISTER

R/W-0/0 U-0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
LCxEN — LCxOUT LCxINTP LCxINTN LCxMODE<2:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 LCxEN: Configurable Logic Cell Enable bit

1 = Configurable logic cell is enabled and mixing input signals
0 = Configurable logic cell is disabled and has logic zero output
bit 6 Unimplemented: Read as ‘0’
bit 5 LCxOUT: Configurable Logic Cell Data Output bit
Read-only: logic cell output data, after LCxPOL; sampled from lcx_out wire.
bit 4 LCxINTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit
1 = CLCxIF will be set when a rising edge occurs on lcx_out
0 = CLCxIF will not be set
bit 3 LCxINTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit
1 = CLCxIF will be set when a falling edge occurs on lcx_out
0 = CLCxIF will not be set
bit 2-0 LCxMODE<2:0>: Configurable Logic Cell Functional Mode bits
111 = Cell is 1-input transparent latch with S and R
110 = Cell is J-K flip-flop with R
101 = Cell is 2-input D flip-flop with R
100 = Cell is 1-input D flip-flop with S and R
011 = Cell is S-R latch
010 = Cell is 4-input AND
001 = Cell is OR-XOR
000 = Cell is AND-OR

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REGISTER 24-2: CLCxPOL: SIGNAL POLARITY CONTROL REGISTER

R/W-0/0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u
LCxPOL — — — LCxG4POL LCxG3POL LCxG2POL LCxG1POL
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 LCxPOL: LCOUT Polarity Control bit

1 = The output of the logic cell is inverted
0 = The output of the logic cell is not inverted
bit 6-4 Unimplemented: Read as ‘0’
bit 3 LCxG4POL: Gate 4 Output Polarity Control bit
1 = The output of gate 4 is inverted when applied to the logic cell
0 = The output of gate 4 is not inverted
bit 2 LCxG3POL: Gate 3 Output Polarity Control bit
1 = The output of gate 3 is inverted when applied to the logic cell
0 = The output of gate 3 is not inverted
bit 1 LCxG2POL: Gate 2 Output Polarity Control bit
1 = The output of gate 2 is inverted when applied to the logic cell
0 = The output of gate 2 is not inverted
bit 0 LCxG1POL: Gate 1 Output Polarity Control bit
1 = The output of gate 1 is inverted when applied to the logic cell
0 = The output of gate 1 is not inverted

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REGISTER 24-3: CLCxSEL0: MULTIPLEXER DATA 1 AND 2 SELECT REGISTER

U-0 R/W-x/u R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u
(1) (1)
— LCxD2S<2:0> — LCxD1S<2:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 Unimplemented: Read as ‘0’

bit 6-4 LCxD2S<2:0>: Input Data 2 Selection Control bits(1)
111 = LCx_in[11] is selected for lcxd2
110 = LCx_in[10] is selected for lcxd2
101 = LCx_in[9] is selected for lcxd2
100 = LCx_in[8] is selected for lcxd2
011 = LCx_in[7] is selected for lcxd2
010 = LCx_in[6] is selected for lcxd2
001 = LCx_in[5] is selected for lcxd2
000 = LCx_in[4] is selected for lcxd2
bit 3 Unimplemented: Read as ‘0’
bit 2-0 LCxD1S<2:0>: Input Data 1 Selection Control bits(1)
111 = LCx_in[7] is selected for lcxd1
110 = LCx_in[6] is selected for lcxd1
101 = LCx_in[5] is selected for lcxd1
100 = LCx_in[4] is selected for lcxd1
011 = LCx_in[3] is selected for lcxd1
010 = LCx_in[2] is selected for lcxd1
001 = LCx_in[1] is selected for lcxd1
000 = LCx_in[0] is selected for lcxd1

Note 1: See Table 24-1 for signal names associated with inputs.

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REGISTER 24-4: CLCxSEL1: MULTIPLEXER DATA 3 AND 4 SELECT REGISTER

U-0 R/W-x/u R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u
(1) (1)
— LCxD4S<2:0> — LCxD3S<2:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 Unimplemented: Read as ‘0’

bit 6-4 LCxD4S<2:0>: Input Data 4 Selection Control bits(1)
111 = LCx_in[3] is selected for lcxd4
110 = LCx_in[2] is selected for lcxd4
101 = LCx_in[1] is selected for lcxd4
100 = LCx_in[0] is selected for lcxd4
011 = LCx_in[15] is selected for lcxd4
010 = LCx_in[14] is selected for lcxd4
001 = LCx_in[13] is selected for lcxd4
000 = LCx_in[12] is selected for lcxd4
bit 3 Unimplemented: Read as ‘0’
bit 2-0 LCxD3S<2:0>: Input Data 3 Selection Control bits(1)
111 = LCx_in[15] is selected for lcxd3
110 = LCx_in[14] is selected for lcxd3
101 = LCx_in[13] is selected for lcxd3
100 = LCx_in[12] is selected for lcxd3
011 = LCx_in[11] is selected for lcxd3
010 = LCx_in[10] is selected for lcxd3
001 = LCx_in[9] is selected for lcxd3
000 = LCx_in[8] is selected for lcxd3

Note 1: See Table 24-1 for signal names associated with inputs.

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REGISTER 24-5: CLCxGLS0: GATE 1 LOGIC SELECT REGISTER

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
LCxG1D4T LCxG1D4N LCxG1D3T LCxG1D3N LCxG1D2T LCxG1D2N LCxG1D1T LCxG1D1N
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 LCxG1D4T: Gate 1 Data 4 True (non-inverted) bit

1 = lcxd4T is gated into lcxg1
0 = lcxd4T is not gated into lcxg1
bit 6 LCxG1D4N: Gate 1 Data 4 Negated (inverted) bit
1 = lcxd4N is gated into lcxg1
0 = lcxd4N is not gated into lcxg1
bit 5 LCxG1D3T: Gate 1 Data 3 True (non-inverted) bit
1 = lcxd3T is gated into lcxg1
0 = lcxd3T is not gated into lcxg1
bit 4 LCxG1D3N: Gate 1 Data 3 Negated (inverted) bit
1 = lcxd3N is gated into lcxg1
0 = lcxd3N is not gated into lcxg1
bit 3 LCxG1D2T: Gate 1 Data 2 True (non-inverted) bit
1 = lcxd2T is gated into lcxg1
0 = lcxd2T is not gated into lcxg1
bit 2 LCxG1D2N: Gate 1 Data 2 Negated (inverted) bit
1 = lcxd2N is gated into lcxg1
0 = lcxd2N is not gated into lcxg1
bit 1 LCxG1D1T: Gate 1 Data 1 True (non-inverted) bit
1 = lcxd1T is gated into lcxg1
0 = lcxd1T is not gated into lcxg1
bit 0 LCxG1D1N: Gate 1 Data 1 Negated (inverted) bit
1 = lcxd1N is gated into lcxg1
0 = lcxd1N is not gated into lcxg1

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REGISTER 24-6: CLCxGLS1: GATE 2 LOGIC SELECT REGISTER

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
LCxG2D4T LCxG2D4N LCxG2D3T LCxG2D3N LCxG2D2T LCxG2D2N LCxG2D1T LCxG2D1N
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 LCxG2D4T: Gate 2 Data 4 True (non-inverted) bit

1 = lcxd4T is gated into lcxg2
0 = lcxd4T is not gated into lcxg2
bit 6 LCxG2D4N: Gate 2 Data 4 Negated (inverted) bit
1 = lcxd4N is gated into lcxg2
0 = lcxd4N is not gated into lcxg2
bit 5 LCxG2D3T: Gate 2 Data 3 True (non-inverted) bit
1 = lcxd3T is gated into lcxg2
0 = lcxd3T is not gated into lcxg2
bit 4 LCxG2D3N: Gate 2 Data 3 Negated (inverted) bit
1 = lcxd3N is gated into lcxg2
0 = lcxd3N is not gated into lcxg2
bit 3 LCxG2D2T: Gate 2 Data 2 True (non-inverted) bit
1 = lcxd2T is gated into lcxg2
0 = lcxd2T is not gated into lcxg2
bit 2 LCxG2D2N: Gate 2 Data 2 Negated (inverted) bit
1 = lcxd2N is gated into lcxg2
0 = lcxd2N is not gated into lcxg2
bit 1 LCxG2D1T: Gate 2 Data 1 True (non-inverted) bit
1 = lcxd1T is gated into lcxg2
0 = lcxd1T is not gated into lcxg2
bit 0 LCxG2D1N: Gate 2 Data 1 Negated (inverted) bit
1 = lcxd1N is gated into lcxg2
0 = lcxd1N is not gated into lcxg2

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REGISTER 24-7: CLCxGLS2: GATE 3 LOGIC SELECT REGISTER

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
LCxG3D4T LCxG3D4N LCxG3D3T LCxG3D3N LCxG3D2T LCxG3D2N LCxG3D1T LCxG3D1N
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 LCxG3D4T: Gate 3 Data 4 True (non-inverted) bit

1 = lcxd4T is gated into lcxg3
0 = lcxd4T is not gated into lcxg3
bit 6 LCxG3D4N: Gate 3 Data 4 Negated (inverted) bit
1 = lcxd4N is gated into lcxg3
0 = lcxd4N is not gated into lcxg3
bit 5 LCxG3D3T: Gate 3 Data 3 True (non-inverted) bit
1 = lcxd3T is gated into lcxg3
0 = lcxd3T is not gated into lcxg3
bit 4 LCxG3D3N: Gate 3 Data 3 Negated (inverted) bit
1 = lcxd3N is gated into lcxg3
0 = lcxd3N is not gated into lcxg3
bit 3 LCxG3D2T: Gate 3 Data 2 True (non-inverted) bit
1 = lcxd2T is gated into lcxg3
0 = lcxd2T is not gated into lcxg3
bit 2 LCxG3D2N: Gate 3 Data 2 Negated (inverted) bit
1 = lcxd2N is gated into lcxg3
0 = lcxd2N is not gated into lcxg3
bit 1 LCxG3D1T: Gate 3 Data 1 True (non-inverted) bit
1 = lcxd1T is gated into lcxg3
0 = lcxd1T is not gated into lcxg3
bit 0 LCxG3D1N: Gate 3 Data 1 Negated (inverted) bit
1 = lcxd1N is gated into lcxg3
0 = lcxd1N is not gated into lcxg3

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REGISTER 24-8: CLCxGLS3: GATE 4 LOGIC SELECT REGISTER

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
LCxG4D4T LCxG4D4N LCxG4D3T LCxG4D3N LCxG4D2T LCxG4D2N LCxG4D1T LCxG4D1N
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 LCxG4D4T: Gate 4 Data 4 True (non-inverted) bit

1 = lcxd4T is gated into lcxg4
0 = lcxd4T is not gated into lcxg4
bit 6 LCxG4D4N: Gate 4 Data 4 Negated (inverted) bit
1 = lcxd4N is gated into lcxg4
0 = lcxd4N is not gated into lcxg4
bit 5 LCxG4D3T: Gate 4 Data 3 True (non-inverted) bit
1 = lcxd3T is gated into lcxg4
0 = lcxd3T is not gated into lcxg4
bit 4 LCxG4D3N: Gate 4 Data 3 Negated (inverted) bit
1 = lcxd3N is gated into lcxg4
0 = lcxd3N is not gated into lcxg4
bit 3 LCxG4D2T: Gate 4 Data 2 True (non-inverted) bit
1 = lcxd2T is gated into lcxg4
0 = lcxd2T is not gated into lcxg4
bit 2 LCxG4D2N: Gate 4 Data 2 Negated (inverted) bit
1 = lcxd2N is gated into lcxg4
0 = lcxd2N is not gated into lcxg4
bit 1 LCxG4D1T: Gate 4 Data 1 True (non-inverted) bit
1 = lcxd1T is gated into lcxg4
0 = lcxd1T is not gated into lcxg4
bit 0 LCxG4D1N: Gate 4 Data 1 Negated (inverted) bit
1 = lcxd1N is gated into lcxg4
0 = lcxd1N is not gated into lcxg4

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REGISTER 24-9: CLCDATA: CLC DATA OUTPUT

U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0
— — — — MLC4OUT MLC3OUT MLC2OUT MLC1OUT
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 Unimplemented: Read as ‘0’

bit 3 MLC4OUT: Mirror copy of LC4OUT bit
bit 2 MLC3OUT: Mirror copy of LC3OUT bit
bit 1 MLC2OUT: Mirror copy of LC2OUT bit
bit 0 MLC1OUT: Mirror copy of LC1OUT bit

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TABLE 24-3: SUMMARY OF REGISTERS ASSOCIATED WITH CLCx

Register
Name Bit7 Bit6 Bit5 Bit4 BIt3 Bit2 Bit1 Bit0
on Page

ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 113

ANSELB — — ANSB5 ANSB4 — — — — 117
ANSELC ANSC7 ANSC6 — — ANSC3 ANSC2 ANSC1 ANSC0 121
CLC1CON LC1EN LC1OE LC1OUT LC1INTP LC1INTN LC1MODE<2:0> 277
CLCDATA — — — — — MLC3OUT MLC2OUT MLC1OUT 285
CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N 281
CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N 282
CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N 283
CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N 284
CLC1POL LC1POL — — — LC1G4POL LC1G3POL LC1G2POL LC1G1POL 278
CLC1SEL0 — LC1D2S<2:0> — LC1D1S<2:0> 279
CLC1SEL1 — LC1D4S<2:0> — LC1D3S<2:0> 280
CLC2CON LC2EN LC2OE LC2OUT LC2INTP LC2INTN LC2MODE<2:0> 277
CLC2GLS0 LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N 281
CLC2GLS1 LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N 282
CLC2GLS2 LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N 283
CLC2GLS3 LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N 284
CLC2POL LC2POL — — — LC2G4POL LC2G3POL LC2G2POL LC2G1POL 278
CLC2SEL0 — LC2D2S<2:0> — LC2D1S<2:0> 279
CLC2SEL1 — LC2D4S<2:0> — LC2D3S<2:0> 280
CLC3CON LC3EN LC3OE LC3OUT LC3INTP LC3INTN LC3MODE<2:0> 277
CLC3GLS0 LC3G1D4T LC3G1D4N LC3G1D3T LC3G1D3N LC3G1D2T LC3G1D2N LC3G1D1T LC3G1D1N 281
CLC3GLS1 LC3G2D4T LC3G2D4N LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N LC3G2D1T LC3G2D1N 282
CLC3GLS2 LC3G3D4T LC3G3D4N LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N LC3G3D1T LC3G3D1N 283
CLC3GLS3 LC3G4D4T LC3G4D4N LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N LC3G4D1T LC3G4D1N 284
CLC3POL LC3POL — — — LC3G4POL LC3G3POL LC3G2POL LC3G1POL 278
CLC3SEL0 — LC3D2S<2:0> — LC3D1S<2:0> 279
CLC3SEL1 — LC3D4S<2:0> — LC3D3S<2:0> 280
CLC4CON LC4EN LC4OE LC4OUT LC4INTP LC4INTN LC4MODE<2:0> 277
CLC4GLS0 LC4G1D4T LC4G1D4N LC4G1D3T LC4G1D3N LC4G1D2T LC4G1D2N LC4G1D1T LC4G1D1N 281
CLC4GLS1 LC4G2D4T LC4G2D4N LC4G2D3T LC4G2D3N LC4G2D2T LC4G2D2N LC4G2D1T LC4G2D1N 282
CLC4GLS2 LC4G3D4T LC4G3D4N LC4G3D3T LC4G3D3N LC4G3D2T LC4G3D2N LC4G3D1T LC4G3D1N 283
CLC4GLS3 LC4G4D4T LC4G4D4N LC4G4D3T LC4G4D3N LC4G4D2T LC4G4D2N LC4G4D1T LC4G4D1N 284
CLC4POL LC4POL — — — LC4G4POL LC4G3POL LC4G2POL LC4G1POL 278
CLC4SEL0 — LC4D2S<2:0> — LC4D1S<2:0> 279
CLC4SEL1 — LC4D4S<2:0> — LC4D3S<2:0> 280
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76
PIE3 — — — — CLC4IE CLC3IE CLC2IE CLC1IE 79
PIR3 — — — — CLC4IF CLC3IF CLC2IF CLC1IF 82
TRISA — — TRISA5 TRISA4 —(1) TRISA2 TRISA1 TRISA0 112
TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 116
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 120
Legend: — = unimplemented read as ‘0’,. Shaded cells are not used for CLC module.
Note 1: Unimplemented, read as ‘1’.

DS40001609C-page 286  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
25.0 NUMERICALLY CONTROLLED 25.1.2 ACCUMULATOR
OSCILLATOR (NCO) MODULE The accumulator is a 20-bit register. Read and write
access to the accumulator is available through three
The Numerically Controlled Oscillator (NCOx) module registers:
is a timer that uses the overflow from the addition of an
increment value to divide the input frequency. The • NCOxACCL
advantage of the addition method over simple counter • NCOxACCH
driven timer is that the resolution of division does not • NCOxACCU
vary with the divider value. The NCOx is most useful for
25.1.3 ADDER
applications that require frequency accuracy and fine
resolution at a fixed duty cycle. The NCOx adder is a full adder, which operates
Features of the NCOx include: independently from the system clock. The addition of the
previous result and the increment value replaces the
• 16-bit increment function accumulator value on the rising edge of each input clock.
• Fixed Duty Cycle (FDC) mode
• Pulse Frequency (PF) mode 25.1.4 INCREMENT REGISTERS
• Output pulse width control
• Multiple clock input sources The increment value is stored in two 8-bit registers
• Output polarity control making up a 16-bit increment. In order of LSB to MSB
• Interrupt capability they are:

Figure 25-1 is a simplified block diagram of the NCOx • NCOxINCL

module. • NCOxINCH
When the NCO module is enabled, the NCOxINCH
25.1 NCOx Operation should be written first, then the NCOxINCL register.
The NCOx operates by repeatedly adding a fixed value Writing to the NCOxINCL register initiates the incre-
to an accumulator. Additions occur at the input clock rate. ment buffer registers to be loaded simultaneously on
The accumulator will overflow with a carry periodically, the second rising edge of the NCOx_clk signal.
which is the raw NCOx output (NCO_overflow). This The registers are readable and writable. The increment
effectively reduces the input clock by the ratio of the registers are double-buffered to allow value changes to
addition value to the maximum accumulator value. See be made without first disabling the NCOx module.
Equation 25-1. When the NCO module is disabled, the increment
The NCOx output can be further modified by stretching buffers are loaded immediately after a write to the
the pulse or toggling a flip-flop. The modified NCOx increment registers.
output is then distributed internally to other peripherals
Note: The increment buffer registers are not
and optionally output to a pin. The accumulator
user-accessible.
overflow also generates an interrupt (NCO_interrupt).
The NCOx period changes in discrete steps to create
an average frequency. This output depends on the
ability of the receiving circuit (i.e., CWG or external
resonant converter circuitry) to average the NCOx
output to reduce uncertainty.

25.1.1 NCOx CLOCK SOURCES

Clock sources available to the NCOx include:
• HFINTOSC
• FOSC
• LC1_out
• CLKIN pin
The NCOx clock source is selected by configuring the
NxCKS<2:0> bits in the NCOxCLK register.
EQUATION 25-1:

NCO Clock Frequency  Increment Value

F OVERFLOW = ---------------------------------------------------------------------------------------------------------------
n
-
2
n = Accumulator width in bits

 2011-2013 Microchip Technology Inc. DS40001609C-page 287

 FIGURE 25-1: NUMERICALLY CONTROLLED OSCILLATOR (NCOx) MODULE SIMPLIFIED BLOCK DIAGRAM
DS40001609C-page 288

PIC16(L)F1508/9
NCOxINCH NCOxINCL Rev. 10-000028A
7/30/2013
16
(1)
INCBUFH INCBUFL
16
20

NCO_overflow Adder
HFINTOSC 00
20
FOSC 01 NCOx_clk
NCOxACCU NCOxACCH NCOxACCL
LCx_out 10 20
NCO1CLK 11
NCO_interrupt set bit
NxCKS<1:0>
2 NCOxIF
Fixed Duty
Cycle Mode
Circuitry
NxOE
D Q D Q 0 TRIS bit

_ NCOx
1
Q

NxPFM NxPOL

NCOx_out
To Peripherals

EN S Q

_ D Q NxOUT
 2011-2013 Microchip Technology Inc.

Ripple
R Q
Counter

Pulse Q1
R Frequency
3 Mode Circuitry
NxPWS<2:0>

Note 1: The increment registers are double-buffered to allow for value changes to be made without first disabling the NCO module. The full increment value is loaded into the buffer registers on the
second rising edge of the NCOx_clk signal that occurs immediately after a write to NCOxINCL register. The buffers are not user-accessible and are shown here for reference.
 PIC16(L)F1508/9
25.2 Fixed Duty Cycle (FDC) Mode 25.5 Interrupts
In Fixed Duty Cycle (FDC) mode, every time the When the accumulator overflows (NCO_overflow), the
accumulator overflows (NCO_overflow), the output is NCOx Interrupt Flag bit, NCOxIF, of the PIRx register is
toggled. This provides a 50% duty cycle, provided that set. To enable the interrupt event (NCO_interrupt), the
the increment value remains constant. For more following bits must be set:
information, see Figure 25-2. • NxEN bit of the NCOxCON register
The FDC mode is selected by clearing the NxPFM bit • NCOxIE bit of the PIEx register
in the NCOxCON register. • PEIE bit of the INTCON register
• GIE bit of the INTCON register
25.3 Pulse Frequency (PF) Mode The interrupt must be cleared by software by clearing
the NCOxIF bit in the Interrupt Service Routine.
In Pulse Frequency (PF) mode, every time the accumu-
lator overflows (NCO_overflow), the output becomes
active for one or more clock periods. Once the clock 25.6 Effects of a Reset
period expires, the output returns to an inactive state. All of the NCOx registers are cleared to zero as the
This provides a pulsed output. result of a Reset.
The output becomes active on the rising clock edge
immediately following the overflow event. For more 25.7 Operation In Sleep
information, see Figure 25-2.
The value of the active and inactive states depends on The NCO module operates independently from the
the polarity bit, NxPOL in the NCOxCON register. system clock and will continue to run during Sleep,
provided that the clock source selected remains
The PF mode is selected by setting the NxPFM bit in
active.
the NCOxCON register.
The HFINTOSC remains active during Sleep when the
25.3.1 OUTPUT PULSE WIDTH CONTROL NCO module is enabled and the HFINTOSC is
When operating in PF mode, the active state of the out- selected as the clock source, regardless of the system
put can vary in width by multiple clock periods. Various clock source selected.
pulse widths are selected with the NxPWS<2:0> bits in
In other words, if the HFINTOSC is simultaneously
the NCOxCLK register.
selected as the system clock and the NCO clock
When the selected pulse width is greater than the source, when the NCO is enabled, the CPU will go idle
accumulator overflow time frame, the output of the
during Sleep, but the NCO will continue to operate and
NCOx operation is indeterminate.
the HFINTOSC will remain active.
This will have a direct effect on the Sleep mode current.
25.4 Output Polarity Control
The last stage in the NCOx module is the output polar- 25.8 Alternate Pin Locations
ity. The NxPOL bit in the NCOxCON register selects the
output polarity. Changing the polarity while the inter- This module incorporates I/O pins that can be moved to
rupts are enabled will cause an interrupt for the result- other locations with the use of the alternate pin function
ing output transition. register, APFCON. To determine which pins can be
moved and what their default locations are upon a
The NCOx output can be used internally by source
Reset, see Section 11.1 “Alternate Pin Function” for
code or other peripherals. Accomplish this by reading more information.
the NxOUT (read-only) bit of the NCOxCON register.
The NCOx output signal is available to the following
peripherals:
• CLC
• CWG

 2011-2013 Microchip Technology Inc. DS40001609C-page 289

 FIGURE 25-2: NCO – FIXED DUTY CYCLE (FDC) AND PULSE FREQUENCY MODE (PFM) OUTPUT OPERATION DIAGRAM
DS40001609C-page 290

PIC16(L)F1508/9
Rev. 10-000 029A_A0

NCOx
Clock
Source

NCOx
Increment 4000h 4000h 4000h
Value

NCOx
Accumulator 00000h 04000h 08000h FC000h 00000h 04000h 08000h FC000h 00000h 04000h 08000h
Value

NCO_overflow

NCO_interrupt

NCOx Output
 2011-2013 Microchip Technology Inc.

FDC Mode

NCOx Output
PF Mode
NCOxPWS =
000

NCOx Output
PF Mode
NCOxPWS =
00
 PIC16(L)F1508/9
25.9 Register Definitions: NCOx Control Registers
REGISTER 25-1: NCOxCON: NCOx CONTROL REGISTER
R/W-0/0 R/W-0/0 R-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0
NxEN NxOE NxOUT NxPOL — — — NxPFM
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 NxEN: NCOx Enable bit

1 = NCOx module is enabled
0 = NCOx module is disabled
bit 6 NxOE: NCOx Output Enable bit
1 = NCOx output pin is enabled
0 = NCOx output pin is disabled
bit 5 NxOUT: NCOx Output bit
1 = NCOx output is high
0 = NCOx output is low
bit 4 NxPOL: NCOx Polarity bit
1 = NCOx output signal is active low (inverted)
0 = NCOx output signal is active high (non-inverted)
bit 3-1 Unimplemented: Read as ‘0’
bit 0 NxPFM: NCOx Pulse Frequency Mode bit
1 = NCOx operates in Pulse Frequency mode
0 = NCOx operates in Fixed Duty Cycle mode

REGISTER 25-2: NCOxCLK: NCOx INPUT CLOCK CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0
NxPWS<2:0>(1, 2) — — — NxCKS<1:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 NxPWS<2:0>: NCOx Output Pulse Width Select bits(1, 2)

111 = 128 NCOx clock periods
110 = 64 NCOx clock periods
101 = 32 NCOx clock periods
100 = 16 NCOx clock periods
011 = 8 NCOx clock periods
010 = 4 NCOx clock periods
001 = 2 NCOx clock periods
000 = 1 NCOx clock periods
bit 4-2 Unimplemented: Read as ‘0’
bit 1-0 NxCKS<1:0>: NCOx Clock Source Select bits
11 = NCO1CLK pin
10 = LC1_out
01 = FOSC
00 = HFINTOSC (16 MHz)

Note 1: NxPWS applies only when operating in Pulse Frequency mode.

2: If NCOx pulse width is greater than NCO_overflow period, operation is undeterminate.

 2011-2013 Microchip Technology Inc. DS40001609C-page 291

PIC16(L)F1508/9
REGISTER 25-3: NCOxACCL: NCOx ACCUMULATOR REGISTER – LOW BYTE
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
NCOxACC<7:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 NCOxACC<7:0>: NCOx Accumulator, Low Byte

REGISTER 25-4: NCOxACCH: NCOx ACCUMULATOR REGISTER – HIGH BYTE

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
NCOxACC<15:8>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 NCOxACC<15:8>: NCOx Accumulator, High Byte

REGISTER 25-5: NCOxACCU: NCOx ACCUMULATOR REGISTER – UPPER BYTE

U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — NCOxACC<19:16>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 Unimplemented: Read as ‘0’

bit 3-0 NCOxACC<19:16>: NCOx Accumulator, Upper Byte

DS40001609C-page 292  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
REGISTER 25-6: NCOxINCL: NCOx INCREMENT REGISTER – LOW BYTE(1)
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1
NCOxINC<7:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 NCOxINC<7:0>: NCOx Increment, Low Byte

Note 1: Write the NCOxINCH register first, then the NCOxINCL register. See 25.1.4 “Increment Registers” for
more information.

REGISTER 25-7: NCOxINCH: NCOx INCREMENT REGISTER – HIGH BYTE(1)

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
NCOxINC<15:8>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 NCOxINC<15:8>: NCOx Increment, High Byte

Note 1: Write the NCOxINCH register first, then the NCOxINCL register. See 25.1.4 “Increment Registers” for
more information.

TABLE 25-1: SUMMARY OF REGISTERS ASSOCIATED WITH NCOx

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page

APFCON — — — SSSEL T1GSEL — CLC1SEL NCO1SEL 110

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76
NCO1ACCH NCO1ACC<15:8> 292
NCO1ACCL NCO1ACC<7:0> 292
NCO1ACCU — NCO1ACC<19:16> 292
NCO1CLK N1PWS<2:0> — — — N1CKS<1:0> 291
NCO1CON N1EN N1OE N1OUT N1POL — — — N1PFM 291
NCO1INCH NCO1INC<15:8> 293
NCO1INCL NCO1INC<7:0> 293
PIE2 OSFIE C2IE C1IE — BCL1IE NCO1IE — — 78
PIR2 OSFIF C2IF C1IF — BCL1IF NCO1IF — — 81
TRISA — — TRISA5 TRISA4 —(1) TRISA2 TRISA1 TRISA0 112
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 120
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are not
used for NCOx module.
Note 1: Unimplemented, read as ‘1’.

 2011-2013 Microchip Technology Inc. DS40001609C-page 293

PIC16(L)F1508/9
NOTES:

DS40001609C-page 294  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
26.0 COMPLEMENTARY WAVEFORM 26.3 Selectable Input Sources
GENERATOR (CWG) MODULE The CWG generates the output waveforms from the
The Complementary Waveform Generator (CWG) input sources in Table 26-1.
produces a complementary waveform with dead-band
delay from a selection of input sources. TABLE 26-1: SELECTABLE INPUT
The CWG module has the following features: SOURCES
• Selectable dead-band clock source control Source Peripheral Signal Name
• Selectable input sources Comparator C1 C1OUT_sync
• Output enable control
Comparator C2 C2OUT_sync
• Output polarity control
PWM1 PWM1_out
• Dead-band control with independent 6-bit rising
and falling edge dead-band counters PWM2 PWM2_out
• Auto-shutdown control with: PWM3 PWM3_out
- Selectable shutdown sources PWM4 PWM4_out
- Auto-restart enable NCO1 NCO1_out
- Auto-shutdown pin override control CLC1 LC1_out
The input sources are selected using the GxIS<2:0>
26.1 Fundamental Operation bits in the CWGxCON1 register (Register 26-2).
The CWG generates two output waveforms from the
selected input source. 26.4 Output Control
The off-to-on transition of each output can be delayed Immediately after the CWG module is enabled, the
from the on-to-off transition of the other output, thereby, complementary drive is configured with both CWGxA
creating a time delay immediately where neither output and CWGxB drives cleared.
is driven. This is referred to as dead time and is covered
in Section 26.5 “Dead-Band Control”. A typical 26.4.1 OUTPUT ENABLES
operating waveform, with dead band, generated from a Each CWG output pin has individual output enable
single input signal is shown in Figure 26-2. control. Output enables are selected with the GxOEA
It may be necessary to guard against the possibility of and GxOEB bits of the CWGxCON0 register. When an
circuit faults or a feedback event arriving too late or not output enable control is cleared, the module asserts no
at all. In this case, the active drive must be terminated control over the pin. When an output enable is set, the
before the Fault condition causes damage. This is override value or active PWM waveform is applied to
referred to as auto-shutdown and is covered in the pin per the port priority selection. The output pin
Section 26.9 “Auto-Shutdown Control”. enables are dependent on the module enable bit,
GxEN. When GxEN is cleared, CWG output enables
26.2 Clock Source and CWG drive levels have no effect.

The CWG module allows the following clock sources 26.4.2 POLARITY CONTROL
to be selected:
The polarity of each CWG output can be selected
• Fosc (system clock) independently. When the output polarity bit is set, the
• HFINTOSC (16 MHz only) corresponding output is active-high. Clearing the output
The clock sources are selected using the G1CS0 bit of polarity bit configures the corresponding output as
the CWGxCON0 register (Register 26-1). active-low. However, polarity does not affect the
override levels. Output polarity is selected with the
GxPOLA and GxPOLB bits of the CWGxCON0 register.

 2011-2013 Microchip Technology Inc. DS40001609C-page 295

 FIGURE 26-1: SIMPLIFIED CWG BLOCK DIAGRAM
DS40001609C-page 296

PIC16(L)F1508/9
2
GxASDLA

00
1
GxCS ‘0’ 10
‘1’ 11 GxASDLA = 01
FOSC
cwg_clock
CWGxDBR GxOEA
HFINTOSC
6
1
3 EN
GxIS R
= 0
TRISx CWGxA
C1OUT_async S Q GxPOLA
C2OUT_async Input Source
PWM1_out
PWM2_out R Q CWGxDBF
PWM3_out
PWM4_out 6
GxOEB
NCO1_out
LC1_out EN TRISx
R = 0

GxPOLB 1
CWGxB

GxASDLB = 01
00
CWG1FLT (INT pin) ‘0’ 10
GxASDFLT ‘1’ 11
C1OUT_async
 2011-2013 Microchip Technology Inc.

GxASDC1 GxASE
Auto-Shutdown GxASDLB
C2OUT_async Source 2
GxASDC2 S shutdown
S Q D Q
LC2_out
GxASCLC
R Q

GxASE Data Bit GxARSEN set dominate

WRITE

x = CWG module number

 PIC16(L)F1508/9
FIGURE 26-2: TYPICAL CWG OPERATION WITH PWM1 (NO AUTO-SHUTDOWN)

cwg_clock

PWM1

CWGxA

Rising Edge Rising Edge Dead Band Rising Edge D

Dead Band Falling Edge Dead Band Falling Edge Dead Band
CWGxB

26.5 Dead-Band Control 26.7 Falling Edge Dead Band

Dead-band control provides for non-overlapping output The falling edge dead band delays the turn-on of the
signals to prevent shoot-through current in power CWGxB output from when the CWGxA output is turned
switches. The CWG contains two 6-bit dead-band off. The falling edge dead-band time starts when the
counters. One dead-band counter is used for the rising falling edge of the input source goes true. When this
edge of the input source control. The other is used for happens, the CWGxA output is immediately turned off
the falling edge of the input source control. and the falling edge dead-band delay time starts. When
Dead band is timed by counting CWG clock periods the falling edge dead-band delay time is reached, the
from zero up to the value in the rising or falling dead- CWGxB output is turned on.
band counter registers. See CWGxDBR and The CWGxDBF register sets the duration of the dead-
CWGxDBF registers (Register 26-4 and Register 26-5, band interval on the falling edge of the input source sig-
respectively). nal. This duration is from 0 to 64 counts of dead band.
Dead band is always counted off the edge on the input
26.6 Rising Edge Dead Band source signal. A count of 0 (zero), indicates that no
dead band is present.
The rising edge dead-band delays the turn-on of the
CWGxA output from when the CWGxB output is turned If the input source signal is not present for enough time
off. The rising edge dead-band time starts when the for the count to be completed, no output will be seen on
rising edge of the input source signal goes true. When the respective output.
this happens, the CWGxB output is immediately turned Refer to Figure 26-3 and Figure 26-4 for examples.
off and the rising edge dead-band delay time starts.
When the rising edge dead-band delay time is reached,
the CWGxA output is turned on.
The CWGxDBR register sets the duration of the dead-
band interval on the rising edge of the input source
signal. This duration is from 0 to 64 counts of dead band.
Dead band is always counted off the edge on the input
source signal. A count of 0 (zero), indicates that no
dead band is present.
If the input source signal is not present for enough time
for the count to be completed, no output will be seen on
the respective output.

 2011-2013 Microchip Technology Inc. DS40001609C-page 297

 FIGURE 26-3: DEAD-BAND OPERATION, CWGxDBR = 01H, CWGxDBF = 02H
DS40001609C-page 298

PIC16(L)F1508/9
cwg_clock

Input Source

CWGxA

CWGxB

FIGURE 26-4: DEAD-BAND OPERATION, CWGxDBR = 03H, CWGxDBF = 04H, SOURCE SHORTER THAN DEAD BAND

cwg_clock

Input Source

CWGxA

CWGxB

source shorter than dead band

 2011-2013 Microchip Technology Inc.
 PIC16(L)F1508/9
26.8 Dead-Band Uncertainty 26.9 Auto-Shutdown Control
When the rising and falling edges of the input source Auto-shutdown is a method to immediately override the
triggers the dead-band counters, the input may be asyn- CWG output levels with specific overrides that allow for
chronous. This will create some uncertainty in the dead- safe shutdown of the circuit. The shutdown state can
band time delay. The maximum uncertainty is equal to be either cleared automatically or held until cleared by
one CWG clock period. Refer to Equation 26-1 for more software.
detail.
26.9.1 SHUTDOWN
EQUATION 26-1: DEAD-BAND The shutdown state can be entered by either of the
UNCERTAINTY following two methods:
• Software generated
• External Input
1
TDEADBAND_UNCERTAINTY = -----------------------------
Fcwg_clock 26.9.1.1 Software Generated Shutdown
Setting the GxASE bit of the CWGxCON2 register will
force the CWG into the shutdown state.
When auto-restart is disabled, the shutdown state will
Example: persist as long as the GxASE bit is set.
When auto-restart is enabled, the GxASE bit will clear
automatically and resume operation on the next rising
Fcwg_clock = 16 MHz edge event. See Figure 26-6.

26.9.1.2 External Input Source

Therefore: External shutdown inputs provide the fastest way to
safely suspend CWG operation in the event of a Fault
condition. When any of the selected shutdown inputs
goes active, the CWG outputs will immediately go to
1 the selected override levels without software delay. Any
TDEADBAND_UNCERTAINTY = -----------------------------
Fcwg_clock combination of two input sources can be selected to
cause a shutdown condition. The sources are:
• Comparator C1 – C1OUT_async
1
= ------------------- • Comparator C2 – C2OUT_async
16 MHz
• CLC2 – LC2_out
• CWG1FLT
= 62.5ns
Shutdown inputs are selected using the GxASDS0 and
GxASDS1 bits of the CWGxCON2 register.
(Register 26-3).
Note: Shutdown inputs are level sensitive, not
edge sensitive. The shutdown state can-
not be cleared, except by disabling auto-
shutdown, as long as the shutdown input
level persists.

 2011-2013 Microchip Technology Inc. DS40001609C-page 299

PIC16(L)F1508/9
26.10 Operation During Sleep 26.11.1 PIN OVERRIDE LEVELS
The levels driven to the output pins, while the shutdown
The CWG module operates independently from the
input is true, are controlled by the GxASDLA and
system clock and will continue to run during Sleep,
GxASDLB bits of the CWGxCON2 register
provided that the clock and input sources selected (Register 26-3). GxASDLA controls the CWG1A
remain active. override level and GxASDLB controls the CWG1B
The HFINTOSC remains active during Sleep, provided override level. The control bit logic level corresponds to
that the CWG module is enabled, the input source is the output logic drive level while in the shutdown state.
active, and the HFINTOSC is selected as the clock The polarity control does not apply to the override level.
source, regardless of the system clock source 26.11.2 AUTO-SHUTDOWN RESTART
selected.
After an auto-shutdown event has occurred, there are
In other words, if the HFINTOSC is simultaneously two ways to have resume operation:
selected as the system clock and the CWG clock
• Software controlled
source, when the CWG is enabled and the input
• Auto-restart
source is active, the CPU will go idle during Sleep, but
the CWG will continue to operate and the HFINTOSC The restart method is selected with the GxARSEN bit
will remain active. of the CWGxCON2 register. Waveforms of software
controlled and automatic restarts are shown in
This will have a direct effect on the Sleep mode current. Figure 26-5 and Figure 26-6.

26.11 Configuring the CWG 26.11.2.1 Software Controlled Restart

The following steps illustrate how to properly configure When the GxARSEN bit of the CWGxCON2 register is
the CWG to ensure a synchronous start: cleared, the CWG must be restarted after an auto-shut-
down event by software.
1. Ensure that the TRIS control bits corresponding
to CWGxA and CWGxB are set so that both are Clearing the shutdown state requires all selected shut-
configured as inputs. down inputs to be low, otherwise the GxASE bit will
2. Clear the GxEN bit, if not already cleared. remain set. The overrides will remain in effect until the
first rising edge event after the GxASE bit is cleared.
3. Set desired dead-band times with the CWGxDBR
The CWG will then resume operation.
and CWGxDBF registers.
4. Setup the following controls in CWGxCON2 26.11.2.2 Auto-Restart
auto-shutdown register:
When the GxARSEN bit of the CWGxCON2 register is
• Select desired shutdown source. set, the CWG will restart from the auto-shutdown state
• Select both output overrides to the desired automatically.
levels (this is necessary even if not using
The GxASE bit will clear automatically when all shut-
auto-shutdown because start-up will be from
down sources go low. The overrides will remain in
a shutdown state).
effect until the first rising edge event after the GxASE
• Set the GxASE bit and clear the GxARSEN bit is cleared. The CWG will then resume operation.
bit.
5. Select the desired input source using the
CWGxCON1 register.
6. Configure the following controls in CWGxCON0
register:
• Select desired clock source.
• Select the desired output polarities.
• Set the output enables for the outputs to be
used.
7. Set the GxEN bit.
8. Clear TRIS control bits corresponding to
CWGxA and CWGxB to be used to configure
those pins as outputs.
9. If auto-restart is to be used, set the GxARSEN
bit and the GxASE bit will be cleared automati-
cally. Otherwise, clear the GxASE bit to start the
CWG.

DS40001609C-page 300  2011-2013 Microchip Technology Inc.

 FIGURE 26-5: SHUTDOWN FUNCTIONALITY, AUTO-RESTART DISABLED (GxARSEN = 0,GxASDLA = 01, GxASDLB = 01)
 2011-2013 Microchip Technology Inc.

Shutdown Event Ceases GxASE Cleared by Software

CWG Input
Source

Shutdown Source

GxASE

CWG1A Tri-State (No Pulse)

CWG1B Tri-State (No Pulse)

No Shutdown
Shutdown Output Resumes

FIGURE 26-6: SHUTDOWN FUNCTIONALITY, AUTO-RESTART ENABLED (GxARSEN = 1,GxASDLA = 01, GxASDLB = 01)

Shutdown Event Ceases GxASE auto-cleared by hardware

CWG Input

PIC16(L)F1508/9
Source

Shutdown Source

GxASE
DS40001609C-page 301

CWG1A Tri-State (No Pulse)

CWG1B Tri-State (No Pulse)

No Shutdown
Shutdown Output Resumes
PIC16(L)F1508/9
26.12 Register Definitions: CWG Control

REGISTER 26-1: CWGxCON0: CWG CONTROL REGISTER 0

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0
GxEN GxOEB GxOEA GxPOLB GxPOLA — — GxCS0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 GxEN: CWGx Enable bit

1 = Module is enabled
0 = Module is disabled
bit 6 GxOEB: CWGxB Output Enable bit
1 = CWGxB is available on appropriate I/O pin
0 = CWGxB is not available on appropriate I/O pin
bit 5 GxOEA: CWGxA Output Enable bit
1 = CWGxA is available on appropriate I/O pin
0 = CWGxA is not available on appropriate I/O pin
bit 4 GxPOLB: CWGxB Output Polarity bit
1 = Output is inverted polarity
0 = Output is normal polarity
bit 3 GxPOLA: CWGxA Output Polarity bit
1 = Output is inverted polarity
0 = Output is normal polarity
bit 2-1 Unimplemented: Read as ‘0’
bit 0 GxCS0: CWGx Clock Source Select bit
1 = HFINTOSC
0 = FOSC

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 PIC16(L)F1508/9

REGISTER 26-2: CWGxCON1: CWG CONTROL REGISTER 1

R/W-x/u R/W-x/u R/W-x/u R/W-x/u U-0 R/W-0/0 R/W-0/0 R/W-0/0
GxASDLB<1:0> GxASDLA<1:0> — GxIS<2:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-6 GxASDLB<1:0>: CWGx Shutdown State for CWGxB

When an auto shutdown event is present (GxASE = 1):
11 = CWGxB pin is driven to ‘1’, regardless of the setting of the GxPOLB bit.
10 = CWGxB pin is driven to ‘0’, regardless of the setting of the GxPOLB bit.
01 = CWGxB pin is tri-stated
00 = CWGxB pin is driven to its inactive state after the selected dead-band interval. GxPOLB still will
control the polarity of the output.
bit 5-4 GxASDLA<1:0>: CWGx Shutdown State for CWGxA
When an auto shutdown event is present (GxASE = 1):
11 = CWGxA pin is driven to ‘1’, regardless of the setting of the GxPOLA bit.
10 = CWGxA pin is driven to ‘0’, regardless of the setting of the GxPOLA bit.
01 = CWGxA pin is tri-stated
00 = CWGxA pin is driven to its inactive state after the selected dead-band interval. GxPOLA still will
control the polarity of the output.
bit 3 Unimplemented: Read as ‘0’
bit 2-0 GxIS<2:0>: CWGx Input Source Select bits
111 = CLC1 – LC1_out
110 = NCO1 – NCO1_out
101 = PWM4 – PWM4_out
100 = PWM3 – PWM3_out
011 = PWM2 – PWM2_out
010 = PWM1 – PWM1_out
001 = Comparator C1 – C1OUT_async
000 = Comparator C2 – C2OUT_async

 2011-2013 Microchip Technology Inc. DS40001609C-page 303

PIC16(L)F1508/9

REGISTER 26-3: CWGxCON2: CWG CONTROL REGISTER 2

R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
GxASE GxARSEN — — GxASDC2 GxASDC1 GxASDFLT GxASDCLC2
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 GxASE: Auto-Shutdown Event Status bit

1 = An auto-shutdown event has occurred
0 = No auto-shutdown event has occurred
bit 6 GxARSEN: Auto-Restart Enable bit
1 = Auto-restart is enabled
0 = Auto-restart is disabled
bit 5-4 Unimplemented: Read as ‘0’
bit 3 GxASDC2: CWG Auto-shutdown on Comparator C2 Enable bit
1 = Shutdown when Comparator C2 output (C2OUT_async) is high
0 = Comparator C2 output has no effect on shutdown
bit 2 GxASDC1: CWG Auto-shutdown on Comparator C1 Enable bit
1 = Shutdown when Comparator C1 output (C1OUT_async) is high
0 = Comparator C1 output has no effect on shutdown
bit 1 GxASDFLT: CWG Auto-shutdown on FLT Enable bit
1 = Shutdown when CWG1FLT input is low
0 = CWG1FLT input has no effect on shutdown
bit 0 GxASDCLC2: CWG Auto-shutdown on CLC2 Enable bit
1 = Shutdown when CLC2 output (LC2_out) is high
0 = CLC2 output has no effect on shutdown

DS40001609C-page 304  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
REGISTER 26-4: CWGxDBR: COMPLEMENTARY WAVEFORM GENERATOR (CWGx) RISING
DEAD-BAND COUNT REGISTER
U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — CWGxDBR<5:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 CWGxDBR<5:0>: Complementary Waveform Generator (CWGx) Rising Counts
11 1111 = 63-64 counts of dead band
11 1110 = 62-63 counts of dead band





00 0010 = 2-3 counts of dead band

00 0001 = 1-2 counts of dead band
00 0000 = 0 counts of dead band

REGISTER 26-5: CWGxDBF: COMPLEMENTARY WAVEFORM GENERATOR (CWGx) FALLING

DEAD-BAND COUNT REGISTER
U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — CWGxDBF<5:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 CWGxDBF<5:0>: Complementary Waveform Generator (CWGx) Falling Counts
11 1111 = 63-64 counts of dead band
11 1110 = 62-63 counts of dead band





00 0010 = 2-3 counts of dead band

00 0001 = 1-2 counts of dead band
00 0000 = 0 counts of dead band. Dead-band generation is bypassed.

 2011-2013 Microchip Technology Inc. DS40001609C-page 305

PIC16(L)F1508/9
TABLE 26-2: SUMMARY OF REGISTERS ASSOCIATED WITH CWG
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 113
CWG1CON0 G1EN G1OEB G1OEA G1POLB G1POLA — — G1CS0 302
CWG1CON1 G1ASDLB<1:0> G1ASDLA<1:0> — — G1IS<1:0> 303
CWG1CON2 G1ASE G1ARSEN — — G1ASDC2 G1ASDC1 G1ASDSFLT G1ASDSCLC2 304
CWG1DBF — — CWG1DBF<5:0> 305
CWG1DBR — — CWG1DBR<5:0> 305
TRISA — — TRISA5 TRISA4 —(1) TRISA2 TRISA1 TRISA0 112
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 120
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by CWG.
Note 1: Unimplemented, read as ‘1’.

DS40001609C-page 306  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
27.0 IN-CIRCUIT SERIAL 27.3 Common Programming Interfaces
PROGRAMMING™ (ICSP™) Connection to a target device is typically done through
ICSP™ programming allows customers to manufacture an ICSP™ header. A commonly found connector on
circuit boards with unprogrammed devices. Programming development tools is the RJ-11 in the 6P6C (6-pin,
can be done after the assembly process allowing the 6-connector) configuration. See Figure 27-1.
device to be programmed with the most recent firmware
or a custom firmware. Five pins are needed for ICSP™ FIGURE 27-1: ICD RJ-11 STYLE
programming: CONNECTOR INTERFACE
• ICSPCLK
• ICSPDAT
• MCLR/VPP
• VDD
ICSPDAT
• VSS
2 4 6 NC
VDD
In Program/Verify mode the program memory, user IDs ICSPCLK
and the Configuration Words are programmed through 1 3 5
Target
serial communications. The ICSPDAT pin is a bidirec- VPP/MCLR PC Board
VSS
tional I/O used for transferring the serial data and the Bottom Side
ICSPCLK pin is the clock input. For more information on
ICSP™ refer to the “PIC12(L)F1501/PIC16(L)F150X
Memory Programming Specification” (DS41573). Pin Description*
1 = VPP/MCLR
27.1 High-Voltage Programming Entry 2 = VDD Target
Mode 3 = VSS (ground)

The device is placed into High-Voltage Programming 4 = ICSPDAT

Entry mode by holding the ICSPCLK and ICSPDAT 5 = ICSPCLK

pins low then raising the voltage on MCLR/VPP to VIHH. 6 = No Connect

27.2 Low-Voltage Programming Entry Another connector often found in use with the PICkit™
Mode programmers is a standard 6-pin header with 0.1 inch
spacing. Refer to Figure 27-2.
The Low-Voltage Programming Entry mode allows the
PIC® Flash MCUs to be programmed using VDD only,
without high voltage. When the LVP bit of Configuration
Words is set to ‘1’, the ICSP Low-Voltage
Programming Entry mode is enabled. To disable the
Low-Voltage ICSP mode, the LVP bit must be
programmed to ‘0’.
Entry into the Low-Voltage Programming Entry mode
requires the following steps:
1. MCLR is brought to VIL.
2. A 32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be
maintained.
If low-voltage programming is enabled (LVP = 1), the
MCLR Reset function is automatically enabled and
cannot be disabled. See Section 6.5 “MCLR” for more
information.
The LVP bit can only be reprogrammed to ‘0’ by using
the High-Voltage Programming mode.

 2011-2013 Microchip Technology Inc. DS40001609C-page 307

PIC16(L)F1508/9
FIGURE 27-2: PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE
Rev. 10-000128A
7/30/2013

Pin 1 Indicator

Pin Description*
1 = VPP/MCLR
1
2
2 = VDD Target
3
4 3 = VSS (ground)
5
6 4 = ICSPDAT
5 = ICSPCLK
6 = No connect

* The 6-pin header (0.100" spacing) accepts 0.025" square pins

For additional interface recommendations, refer to your It is recommended that isolation devices be used to
specific device programmer manual prior to PCB separate the programming pins from other circuitry.
design. The type of isolation is highly dependent on the specific
application and may include devices such as resistors,
diodes, or even jumpers. See Figure 27-3 for more
information.

FIGURE 27-3: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING

Rev. 10-000129A
7/30/2013

External Device to be
Programming VDD Programmed
Signals

VDD VDD

VPP MCLR/VPP
VSS VSS

Data ICSPDAT
Clock ICSPCLK

* * *

To Normal Connections

* Isolation devices (as required).

DS40001609C-page 308  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
28.0 INSTRUCTION SET SUMMARY 28.1 Read-Modify-Write Operations
Each instruction is a 14-bit word containing the opera- Any instruction that specifies a file register as part of
tion code (opcode) and all required operands. The the instruction performs a Read-Modify-Write (R-M-W)
opcodes are broken into three broad categories. operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
• Byte Oriented
tion, or the destination designator ‘d’. A read operation
• Bit Oriented is performed on a register even if the instruction writes
• Literal and Control to that register.
The literal and control category contains the most
varied instruction word format. TABLE 28-1: OPCODE FIELD
Table 28-3 lists the instructions recognized by the DESCRIPTIONS
MPASMTM assembler. Field Description
All instructions are executed within a single instruction f Register file address (0x00 to 0x7F)
cycle, with the following exceptions, which may take
W Working register (accumulator)
two or three cycles:
b Bit address within an 8-bit file register
• Subroutine takes two cycles (CALL, CALLW)
• Returns from interrupts or subroutines take two k Literal field, constant data or label
cycles (RETURN, RETLW, RETFIE) x Don’t care location (= 0 or 1).
• Program branching takes two cycles (GOTO, BRA, The assembler will generate code with x = 0.
BRW, BTFSS, BTFSC, DECFSZ, INCSFZ) It is the recommended form of use for
• One additional instruction cycle will be used when compatibility with all Microchip software tools.
any instruction references an indirect file register d Destination select; d = 0: store result in W,
and the file select register is pointing to program d = 1: store result in file register f.
memory. Default is d = 1.
One instruction cycle consists of 4 oscillator cycles; for n FSR or INDF number. (0-1)
an oscillator frequency of 4 MHz, this gives a nominal mm Pre-post increment-decrement mode
instruction execution rate of 1 MHz.
selection
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a TABLE 28-2: ABBREVIATION
hexadecimal digit.
DESCRIPTIONS
Field Description
PC Program Counter
TO Time-Out bit
C Carry bit
DC Digit Carry bit
Z Zero bit
PD Power-Down bit

 2011-2013 Microchip Technology Inc. DS40001609C-page 309

PIC16(L)F1508/9
FIGURE 28-1: GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13 8 7 6 0
OPCODE d f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address

Bit-oriented file register operations

13 10 9 7 6 0
OPCODE b (BIT #) f (FILE #)

b = 3-bit bit address

f = 7-bit file register address

Literal and control operations

General
13 8 7 0
OPCODE k (literal)

k = 8-bit immediate value

CALL and GOTO instructions only

13 11 10 0
OPCODE k (literal)

k = 11-bit immediate value

MOVLP instruction only

13 7 6 0
OPCODE k (literal)
k = 7-bit immediate value

MOVLB instruction only

13 5 4 0
OPCODE k (literal)

k = 5-bit immediate value

BRA instruction only

13 9 8 0
OPCODE k (literal)

k = 9-bit immediate value

FSR Offset instructions

13 7 6 5 0
OPCODE n k (literal)
n = appropriate FSR
k = 6-bit immediate value

FSR Increment instructions

13 3 2 1 0
OPCODE n m (mode)
n = appropriate FSR
m = 2-bit mode value

OPCODE only
13 0
OPCODE

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 PIC16(L)F1508/9

TABLE 28-3: ENHANCED MID-RANGE INSTRUCTION SET

Mnemonic, 14-Bit Opcode Status
Description Cycles Notes
Operands MSb LSb Affected

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF f, d Add W and f 1 00 0111 dfff ffff C, DC, Z 2
ADDWFC f, d Add with Carry W and f 1 11 1101 dfff ffff C, DC, Z 2
ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 2
ASRF f, d Arithmetic Right Shift 1 11 0111 dfff ffff C, Z 2
LSLF f, d Logical Left Shift 1 11 0101 dfff ffff C, Z 2
LSRF f, d Logical Right Shift 1 11 0110 dfff ffff C, Z 2
CLRF f Clear f 1 00 0001 lfff ffff Z 2
CLRW – Clear W 1 00 0001 0000 00xx Z
COMF f, d Complement f 1 00 1001 dfff ffff Z 2
DECF f, d Decrement f 1 00 0011 dfff ffff Z 2
INCF f, d Increment f 1 00 1010 dfff ffff Z 2
IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 2
MOVF f, d Move f 1 00 1000 dfff ffff Z 2
MOVWF f Move W to f 1 00 0000 1fff ffff 2
RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 2
RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 2
SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C, DC, Z 2
SUBWFB f, d Subtract with Borrow W from f 1 11 1011 dfff ffff C, DC, Z 2
SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 2
XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 2
BYTE ORIENTED SKIP OPERATIONS

DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1, 2

INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1, 2

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF f, b Bit Clear f 1 01 00bb bfff ffff 2

BSF f, b Bit Set f 1 01 01bb bfff ffff 2

BIT-ORIENTED SKIP OPERATIONS

BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 1, 2
BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 1, 2
LITERAL OPERATIONS
ADDLW k Add literal and W 1 11 1110 kkkk kkkk C, DC, Z
ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z
IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z
MOVLB k Move literal to BSR 1 00 0000 001k kkkk
MOVLP k Move literal to PCLATH 1 11 0001 1kkk kkkk
MOVLW k Move literal to W 1 11 0000 kkkk kkkk
SUBLW k Subtract W from literal 1 11 1100 kkkk kkkk C, DC, Z
XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one
additional instruction cycle.

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TABLE 28-3: ENHANCED MID-RANGE INSTRUCTION SET (CONTINUED)
Mnemonic, 14-Bit Opcode Status
Description Cycles Notes
Operands MSb LSb Affected

CONTROL OPERATIONS
BRA k Relative Branch 2 11 001k kkkk kkkk
BRW – Relative Branch with W 2 00 0000 0000 1011
CALL k Call Subroutine 2 10 0kkk kkkk kkkk
CALLW – Call Subroutine with W 2 00 0000 0000 1010
GOTO k Go to address 2 10 1kkk kkkk kkkk
RETFIE k Return from interrupt 2 00 0000 0000 1001
RETLW k Return with literal in W 2 11 0100 kkkk kkkk
RETURN – Return from Subroutine 2 00 0000 0000 1000
INHERENT OPERATIONS
CLRWDT – Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD
NOP – No Operation 1 00 0000 0000 0000
OPTION – Load OPTION_REG register with W 1 00 0000 0110 0010
RESET – Software device Reset 1 00 0000 0000 0001
SLEEP – Go into Standby mode 1 00 0000 0110 0011 TO, PD
TRIS f Load TRIS register with W 1 00 0000 0110 0fff
C-COMPILER OPTIMIZED
ADDFSR n, k Add Literal k to FSRn 1 11 0001 0nkk kkkk
MOVIW n mm Move Indirect FSRn to W with pre/post inc/dec 1 00 0000 0001 0nmm Z 2, 3
modifier, mm kkkk
k[n] Move INDFn to W, Indexed Indirect. 1 11 1111 0nkk 1nmm Z 2
MOVWI n mm Move W to Indirect FSRn with pre/post inc/dec 1 00 0000 0001 kkkk 2, 3
modifier, mm
k[n] Move W to INDFn, Indexed Indirect. 1 11 1111 1nkk 2
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
3: See Table in the MOVIW and MOVWI instruction descriptions.

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28.2 Instruction Descriptions

ADDFSR Add Literal to FSRn ANDLW AND literal with W

Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW k
Operands: -32  k  31 Operands: 0  k  255
n  [ 0, 1]
Operation: (W) .AND. (k)  (W)
Operation: FSR(n) + k  FSR(n)
Status Affected: Z
Status Affected: None Description: The contents of W register are
Description: The signed 6-bit literal ‘k’ is added to AND’ed with the 8-bit literal ‘k’. The
the contents of the FSRnH:FSRnL result is placed in the W register.
register pair.

FSRn is limited to the range 0000h -

FFFFh. Moving beyond these bounds
will cause the FSR to wrap-around.

ADDLW Add literal and W ANDWF AND W with f

Syntax: [ label ] ADDLW k Syntax: [ label ] ANDWF f,d
Operands: 0  k  255 Operands: 0  f  127
d 0,1
Operation: (W) + k  (W)
Operation: (W) .AND. (f)  (destination)
Status Affected: C, DC, Z
Status Affected: Z
Description: The contents of the W register are
added to the 8-bit literal ‘k’ and the Description: AND the W register with register ‘f’. If
result is placed in the W register. ‘d’ is ‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.

ADDWF Add W and f ASRF Arithmetic Right Shift

Syntax: [ label ] ADDWF f,d Syntax: [ label ] ASRF f {,d}
Operands: 0  f  127 Operands: 0  f  127
d 0,1 d [0,1]
Operation: (W) + (f)  (destination) Operation: (f<7>) dest<7>
(f<7:1>)  dest<6:0>,
Status Affected: C, DC, Z
(f<0>)  C,
Description: Add the contents of the W register
Status Affected: C, Z
with register ‘f’. If ‘d’ is ‘0’, the result is
stored in the W register. If ‘d’ is ‘1’, the Description: The contents of register ‘f’ are shifted
result is stored back in register ‘f’. one bit to the right through the Carry
flag. The MSb remains unchanged. If
‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in
register ‘f’.
ADDWFC ADD W and CARRY bit to f register f C
Syntax: [ label ] ADDWFC f {,d}
Operands: 0  f  127
d [0,1]
Operation: (W) + (f) + (C)  dest
Status Affected: C, DC, Z
Description: Add W, the Carry flag and data mem-
ory location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.

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BCF Bit Clear f BTFSC Bit Test f, Skip if Clear

Syntax: [ label ] BCF f,b Syntax: [ label ] BTFSC f,b

Operands: 0  f  127 Operands: 0  f  127

0b7 0b7

Operation: 0  (f<b>) Operation: skip if (f<b>) = 0

Status Affected: None Status Affected: None

Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the next
instruction is discarded, and a NOP is
executed instead, making this a
2-cycle instruction.

BRA Relative Branch BTFSS Bit Test f, Skip if Set

Syntax: [ label ] BRA label Syntax: [ label ] BTFSS f,b
[ label ] BRA $+k Operands: 0  f  127
Operands: -256  label - PC + 1  255 0b<7
-256  k  255 Operation: skip if (f<b>) = 1
Operation: (PC) + 1 + k  PC Status Affected: None
Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next
Description: Add the signed 9-bit literal ‘k’ to the instruction is executed.
PC. Since the PC will have incre- If bit ‘b’ is ‘1’, then the next
mented to fetch the next instruction, instruction is discarded and a NOP is
the new address will be PC + 1 + k. executed instead, making this a
This instruction is a 2-cycle instruc- 2-cycle instruction.
tion. This branch has a limited range.

BRW Relative Branch with W

Syntax: [ label ] BRW
Operands: None
Operation: (PC) + (W)  PC
Status Affected: None
Description: Add the contents of W (unsigned) to
the PC. Since the PC will have incre-
mented to fetch the next instruction,
the new address will be PC + 1 + (W).
This instruction is a 2-cycle instruc-
tion.

BSF Bit Set f

Syntax: [ label ] BSF f,b
Operands: 0  f  127
0b7
Operation: 1  (f<b>)
Status Affected: None
Description: Bit ‘b’ in register ‘f’ is set.

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CALL Call Subroutine CLRWDT Clear Watchdog Timer

Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT
Operands: 0  k  2047 Operands: None
Operation: (PC)+ 1 TOS, Operation: 00h  WDT
k  PC<10:0>, 0  WDT prescaler,
(PCLATH<6:3>)  PC<14:11> 1  TO
Status Affected: None 1  PD
Description: Call Subroutine. First, return address Status Affected: TO, PD
(PC + 1) is pushed onto the stack. Description: CLRWDT instruction resets the Watch-
The 11-bit immediate address is dog Timer. It also resets the prescaler
loaded into PC bits <10:0>. The upper of the WDT.
bits of the PC are loaded from Status bits TO and PD are set.
PCLATH. CALL is a 2-cycle instruc-
tion.

CALLW Subroutine Call With W COMF Complement f

Syntax: [ label ] CALLW Syntax: [ label ] COMF f,d

Operands: None Operands: 0  f  127

d  [0,1]
Operation: (PC) +1  TOS,
(W)  PC<7:0>, Operation: (f)  (destination)
(PCLATH<6:0>) PC<14:8> Status Affected: Z
Description: The contents of register ‘f’ are com-
Status Affected: None plemented. If ‘d’ is ‘0’, the result is
Description: Subroutine call with W. First, the stored in W. If ‘d’ is ‘1’, the result is
return address (PC + 1) is pushed stored back in register ‘f’.
onto the return stack. Then, the con-
tents of W is loaded into PC<7:0>,
and the contents of PCLATH into
PC<14:8>. CALLW is a 2-cycle
instruction.

CLRF Clear f DECF Decrement f

Syntax: [ label ] CLRF f Syntax: [ label ] DECF f,d
Operands: 0  f  127 Operands: 0  f  127
d  [0,1]
Operation: 00h  (f)
1Z Operation: (f) - 1  (destination)
Status Affected: Z Status Affected: Z
Description: The contents of register ‘f’ are cleared Description: Decrement register ‘f’. If ‘d’ is ‘0’, the
and the Z bit is set. result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h  (W)
1Z
Status Affected: Z
Description: W register is cleared. Zero bit (Z) is
set.

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DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0

Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d
Operands: 0  f  127 Operands: 0  f  127
d  [0,1] d  [0,1]
Operation: (f) - 1  (destination); Operation: (f) + 1  (destination),
skip if result = 0 skip if result = 0
Status Affected: None Status Affected: None
Description: The contents of register ‘f’ are decre- Description: The contents of register ‘f’ are incre-
mented. If ‘d’ is ‘0’, the result is placed mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’. is placed back in register ‘f’.
If the result is ‘1’, the next instruction is If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, then a executed. If the result is ‘0’, a NOP is
NOP is executed instead, making it a executed instead, making it a 2-cycle
2-cycle instruction. instruction.

GOTO Unconditional Branch IORLW Inclusive OR literal with W

Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k
Operands: 0  k  2047 Operands: 0  k  255
Operation: k  PC<10:0> Operation: (W) .OR. k  (W)
PCLATH<6:3>  PC<14:11>
Status Affected: Z
Status Affected: None Description: The contents of the W register are
Description: GOTO is an unconditional branch. The OR’ed with the 8-bit literal ‘k’. The
11-bit immediate value is loaded into result is placed in the W register.
PC bits <10:0>. The upper bits of PC
are loaded from PCLATH<4:3>. GOTO
is a 2-cycle instruction.

INCF Increment f IORWF Inclusive OR W with f

Syntax: [ label ] INCF f,d Syntax: [ label ] IORWF f,d
Operands: 0  f  127 Operands: 0  f  127
d  [0,1] d  [0,1]
Operation: (f) + 1  (destination) Operation: (W) .OR. (f)  (destination)
Status Affected: Z Status Affected: Z
Description: The contents of register ‘f’ are incre- Description: Inclusive OR the W register with regis-
mented. If ‘d’ is ‘0’, the result is placed ter ‘f’. If ‘d’ is ‘0’, the result is placed in
in the W register. If ‘d’ is ‘1’, the result the W register. If ‘d’ is ‘1’, the result is
is placed back in register ‘f’. placed back in register ‘f’.

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LSLF Logical Left Shift MOVF Move f

Syntax: [ label ] LSLF f {,d} Syntax: [ label ] MOVF f,d
Operands: 0  f  127 Operands: 0  f  127
d [0,1] d  [0,1]
Operation: (f<7>)  C Operation: (f)  (dest)
(f<6:0>)  dest<7:1>
Status Affected: Z
0  dest<0>
Description: The contents of register f is moved to
Status Affected: C, Z
a destination dependent upon the
Description: The contents of register ‘f’ are shifted status of d. If d = 0,
one bit to the left through the Carry flag. destination is W register. If d = 1, the
A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, destination is file register f itself. d = 1
the result is placed in W. If ‘d’ is ‘1’, the is useful to test a file register since
result is stored back in register ‘f’. status flag Z is affected.

C register f 0 Words: 1
Cycles: 1
Example: MOVF FSR, 0
After Instruction
LSRF Logical Right Shift
W = value in FSR register
Syntax: [ label ] LSRF f {,d} Z = 1
Operands: 0  f  127
d [0,1]
Operation: 0  dest<7>
(f<7:1>)  dest<6:0>,
(f<0>)  C,
Status Affected: C, Z
Description: The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. A ‘0’ is shifted into the MSb. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is stored back in register ‘f’.

0 register f C

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MOVIW Move INDFn to W MOVLP Move literal to PCLATH

Syntax: [ label ] MOVIW ++FSRn Syntax: [ label ] MOVLP k
[ label ] MOVIW --FSRn
Operands: 0  k  127
[ label ] MOVIW FSRn++
[ label ] MOVIW FSRn-- Operation: k  PCLATH
[ label ] MOVIW k[FSRn] Status Affected: None
Operands: n  [0,1] Description: The 7-bit literal ‘k’ is loaded into the
mm  [00,01, 10, 11] PCLATH register.
-32  k  31
Operation: INDFn  W
Effective address is determined by MOVLW Move literal to W
• FSR + 1 (preincrement)
Syntax: [ label ] MOVLW k
• FSR - 1 (predecrement)
• FSR + k (relative offset) Operands: 0  k  255
After the Move, the FSR value will be
Operation: k  (W)
either:
• FSR + 1 (all increments) Status Affected: None
• FSR - 1 (all decrements) Description: The 8-bit literal ‘k’ is loaded into W reg-
• Unchanged ister. The “don’t cares” will assemble as
Status Affected: Z ‘0’s.
Words: 1

Mode Syntax mm Cycles: 1

Preincrement ++FSRn 00 Example: MOVLW 0x5A

Predecrement --FSRn 01 After Instruction

W = 0x5A
Postincrement FSRn++ 10
Postdecrement FSRn-- 11
MOVWF Move W to f
Syntax: [ label ] MOVWF f
Description: This instruction is used to move data
between W and one of the indirect Operands: 0  f  127
registers (INDFn). Before/after this Operation: (W)  (f)
move, the pointer (FSRn) is updated by
Status Affected: None
pre/post incrementing/decrementing it.
Description: Move data from W register to register
Note: The INDFn registers are not ‘f’.
physical registers. Any instruction that Words: 1
accesses an INDFn register actually
accesses the register at the address Cycles: 1
specified by the FSRn. Example: MOVWF OPTION_REG
Before Instruction
FSRn is limited to the range 0000h -
OPTION_REG = 0xFF
FFFFh. Incrementing/decrementing it
W = 0x4F
beyond these bounds will cause it to
After Instruction
wrap-around.
OPTION_REG = 0x4F
W = 0x4F
MOVLB Move literal to BSR
Syntax: [ label ] MOVLB k
Operands: 0  k  31
Operation: k  BSR
Status Affected: None
Description: The 5-bit literal ‘k’ is loaded into the
Bank Select Register (BSR).

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 PIC16(L)F1508/9

MOVWI Move W to INDFn NOP No Operation

Syntax: [ label ] MOVWI ++FSRn Syntax: [ label ] NOP

[ label ] MOVWI --FSRn Operands: None
[ label ] MOVWI FSRn++
Operation: No operation
[ label ] MOVWI FSRn--
[ label ] MOVWI k[FSRn] Status Affected: None

Operands: n  [0,1] Description: No operation.

mm  [00,01, 10, 11] Words: 1
-32  k  31
Cycles: 1
Operation: W  INDFn
Example: NOP
Effective address is determined by
• FSR + 1 (preincrement)
• FSR - 1 (predecrement)
• FSR + k (relative offset)
After the Move, the FSR value will be
either:
Load OPTION_REG Register
OPTION
• FSR + 1 (all increments) with W
• FSR - 1 (all decrements) Syntax: [ label ] OPTION
Unchanged
Operands: None
Status Affected: None
Operation: (W)  OPTION_REG
Status Affected: None
Mode Syntax mm
Description: Move data from W register to
Preincrement ++FSRn 00 OPTION_REG register.
Predecrement --FSRn 01
Postincrement FSRn++ 10
Postdecrement FSRn-- 11
RESET Software Reset
Syntax: [ label ] RESET
Description: This instruction is used to move data
between W and one of the indirect Operands: None
registers (INDFn). Before/after this Operation: Execute a device Reset. Resets the
move, the pointer (FSRn) is updated by nRI flag of the PCON register.
pre/post incrementing/decrementing it.
Status Affected: None
Note: The INDFn registers are not Description: This instruction provides a way to
physical registers. Any instruction that execute a hardware Reset by soft-
accesses an INDFn register actually ware.
accesses the register at the address
specified by the FSRn.

FSRn is limited to the range 0000h -

FFFFh. Incrementing/decrementing it
beyond these bounds will cause it to
wrap-around.

The increment/decrement operation on

FSRn WILL NOT affect any Status bits.

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RETFIE Return from Interrupt RETURN Return from Subroutine

Syntax: [ label ] RETFIE Syntax: [ label ] RETURN
Operands: None Operands: None
Operation: TOS  PC, Operation: TOS  PC
1  GIE Status Affected: None
Status Affected: None Description: Return from subroutine. The stack is
Description: Return from Interrupt. Stack is POPed POPed and the top of the stack (TOS)
and Top-of-Stack (TOS) is loaded in is loaded into the program counter.
the PC. Interrupts are enabled by This is a 2-cycle instruction.
setting Global Interrupt Enable bit,
GIE (INTCON<7>). This is a 2-cycle
instruction.
Words: 1
Cycles: 2
Example: RETFIE
After Interrupt
PC = TOS
GIE = 1

RETLW Return with literal in W

RLF Rotate Left f through Carry
Syntax: [ label ] RETLW k
Syntax: [ label ] RLF f,d
Operands: 0  k  255
Operands: 0  f  127
Operation: k  (W);
d  [0,1]
TOS  PC
Operation: See description below
Status Affected: None
Status Affected: C
Description: The W register is loaded with the 8-bit
literal ‘k’. The program counter is Description: The contents of register ‘f’ are rotated
loaded from the top of the stack (the one bit to the left through the Carry
return address). This is a 2-cycle flag. If ‘d’ is ‘0’, the result is placed in
instruction. the W register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Words: 1
C Register f
Cycles: 2
Example: CALL TABLE;W contains table Words: 1
;offset value
• ;W now has table value Cycles: 1
TABLE • Example: RLF REG1,0
•
Before Instruction
ADDWF PC ;W = offset
REG1 = 1110 0110
RETLW k1 ;Begin table
C = 0
RETLW k2 ;
After Instruction
•
REG1 = 1110 0110
•
W = 1100 1100
•
C = 1
RETLW kn ; End of table

Before Instruction
W = 0x07
After Instruction
W = value of k8

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SUBLW Subtract W from literal

RRF Rotate Right f through Carry
Syntax: [ label ] SUBLW k
Syntax: [ label ] RRF f,d
Operands: 0 k 255
Operands: 0  f  127
d  [0,1] Operation: k - (W) W)

Operation: See description below Status Affected: C, DC, Z

Status Affected: C Description: The W register is subtracted (2’s com-

plement method) from the 8-bit literal
Description: The contents of register ‘f’ are rotated ‘k’. The result is placed in the W regis-
one bit to the right through the Carry ter.
flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is C=0 Wk
placed back in register ‘f’.
C=1 Wk
C Register f
DC = 0 W<3:0>  k<3:0>
DC = 1 W<3:0>  k<3:0>

SLEEP Enter Sleep mode SUBWF Subtract W from f

Syntax: [ label ] SLEEP Syntax: [ label ] SUBWF f,d
Operands: None Operands: 0 f 127
d  [0,1]
Operation: 00h  WDT,
0  WDT prescaler, Operation: (f) - (W) destination)
1  TO, Status Affected: C, DC, Z
0  PD
Description: Subtract (2’s complement method) W
Status Affected: TO, PD register from register ‘f’. If ‘d’ is ‘0’, the
Description: The power-down Status bit, PD is result is stored in the W
cleared. Time-out Status bit, TO is register. If ‘d’ is ‘1’, the result is stored
set. Watchdog Timer and its pres- back in register ‘f.
caler are cleared.
The processor is put into Sleep mode C=0 Wf
with the oscillator stopped. C=1 Wf
DC = 0 W<3:0>  f<3:0>
DC = 1 W<3:0>  f<3:0>

SUBWFB Subtract W from f with Borrow

Syntax: SUBWFB f {,d}
Operands: 0  f  127
d  [0,1]
Operation: (f) – (W) – (B) dest
Status Affected: C, DC, Z
Description: Subtract W and the BORROW flag
(CARRY) from register ‘f’ (2’s comple-
ment method). If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.

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SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W

Syntax: [ label ] SWAPF f,d Syntax: [ label ] XORLW k
Operands: 0  f  127 Operands: 0 k 255
d  [0,1]
Operation: (W) .XOR. k W)
Operation: (f<3:0>)  (destination<7:4>),
Status Affected: Z
(f<7:4>)  (destination<3:0>)
Description: The contents of the W register are
Status Affected: None
XOR’ed with the 8-bit
Description: The upper and lower nibbles of regis- literal ‘k’. The result is placed in the
ter ‘f’ are exchanged. If ‘d’ is ‘0’, the W register.
result is placed in the W register. If ‘d’
is ‘1’, the result is placed in register ‘f’.

TRIS Load TRIS Register with W XORWF Exclusive OR W with f

Syntax: [ label ] TRIS f Syntax: [ label ] XORWF f,d
Operands: 5f7 Operands: 0  f  127
d  [0,1]
Operation: (W)  TRIS register ‘f’
Operation: (W) .XOR. (f) destination)
Status Affected: None
Status Affected: Z
Description: Move data from W register to TRIS
register. Description: Exclusive OR the contents of the W
When ‘f’ = 5, TRISA is loaded. register with register ‘f’. If ‘d’ is ‘0’, the
When ‘f’ = 6, TRISB is loaded. result is stored in the W register. If ‘d’
When ‘f’ = 7, TRISC is loaded. is ‘1’, the result is stored back in regis-
ter ‘f’.

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 PIC16(L)F1508/9
29.0 ELECTRICAL SPECIFICATIONS
29.1 Absolute Maximum Ratings(†)
Ambient temperature under bias...................................................................................................... -40°C to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Voltage on pins with respect to VSS
on VDD pin
PIC16F1508/9 ........................................................................................................... -0.3V to +6.5V
PIC16LF1508/9 ......................................................................................................... -0.3V to +4.0V
on MCLR pin ........................................................................................................................... -0.3V to +9.0V
on all other pins ............................................................................................................ -0.3V to (VDD + 0.3V)
Maximum current
on VSS pin(1)
-40°C  TA  +85°C .............................................................................................................. 170 mA
-40°C  TA  +125°C .............................................................................................................. 70 mA
on VDD pin(1)
-40°C  TA  +85°C .............................................................................................................. 170 mA
-40°C  TA  +125°C .............................................................................................................. 70 mA
on any I/O pin ..................................................................................................................................... 25 mA
Clamp current, IK (VPIN < 0 or VPIN > VDD) ................................................................................................... 20 mA

Note 1: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be
limited by the device package power dissipation characterizations, see Table 29-6: “Thermal
Characteristics” to calculate device specifications.

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.

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PIC16(L)F1508/9
29.2 Standard Operating Conditions
The standard operating conditions for any device are defined as:
Operating Voltage: VDDMIN VDD VDDMAX
Operating Temperature: TA_MIN TA TA_MAX
VDD — Operating Supply Voltage(1)
PIC16LF1508/9
VDDMIN (Fosc  16 MHz).......................................................................................................... +1.8V
VDDMIN (16 MHz < Fosc  20 MHz) ......................................................................................... +2.5V
VDDMAX .................................................................................................................................... +3.6V
PIC16F1508/9
VDDMIN (Fosc  16 MHz).......................................................................................................... +2.3V
VDDMIN (16 MHz < Fosc  20 MHz) ......................................................................................... +2.5V
VDDMAX .................................................................................................................................... +5.5V
TA — Operating Ambient Temperature Range
Industrial Temperature
TA_MIN ...................................................................................................................................... -40°C
TA_MAX .................................................................................................................................... +85°C
Extended Temperature
TA_MIN ...................................................................................................................................... -40°C
TA_MAX .................................................................................................................................. +125°C

Note 1: See Parameter D001, DS Characteristics: Supply Voltage.

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 PIC16(L)F1508/9
FIGURE 29-1: VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C, PIC16F1508/9 ONLY

Rev. 10-000130A
8/6/2013

5.5

VDD (V)

2.5

2.3

0 16 20
Frequency (MHz)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 29-7 for each Oscillator mode’s supported frequencies.

FIGURE 29-2: VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C, PIC16LF1508/9 ONLY

Rev. 10-000131A
8/5/2013

3.6
VDD (V)

2.5

1.8

0 16 20
Frequency (MHz)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 29-7 for each Oscillator mode’s supported frequencies.

 2011-2013 Microchip Technology Inc. DS40001609C-page 325

PIC16(L)F1508/9
29.3 DC Characteristics
TABLE 29-1: SUPPLY VOLTAGE
PIC16LF1508/9 Standard Operating Conditions (unless otherwise stated)

PIC16F1508/9
Param. Sym. Characteristic Min. Typ† Max. Units Conditions
No.
D001 VDD Supply Voltage
VDDMIN VDDMAX
1.8 — 3.6 V FOSC  16 MHz
2.5 — 3.6 V FOSC  20 MHz
D001 2.3 — 5.5 V FOSC  16 MHz
2.5 — 5.5 V FOSC  20 MHz
D002* VDR RAM Data Retention Voltage(1)
1.5 — — V Device in Sleep mode
D002* 1.7 — — V Device in Sleep mode
(2)
D002A* VPOR Power-on Reset Release Voltage
— 1.6 — V
D002A* — 1.6 — V
D002B* VPORR* Power-on Reset Rearm Voltage(2)
— 0.8 — V
D002B* — 1.5 — V
D003 VFVR Fixed Voltage Reference Voltage
1x gain (1.024V nominal) VDD 2.5V, -40°C  TA  +85°C
2x gain (2.048V nominal) -4 — +4 % VDD 2.5V, -40°C  TA  +85°C
4x gain (4.096V nominal) VDD 4.75V, -40°C  TA  +85°C
D004* SVDD VDD Rise Rate(2) 0.05 — — V/ms Ensures that the Power-on Reset
signal is released properly.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2: See Figure 29-3, POR and POR REARM with Slow Rising VDD.

DS40001609C-page 326  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
FIGURE 29-3: POR AND POR REARM WITH SLOW RISING VDD

VDD

VPOR
VPORR
SVDD

VSS
NPOR(1)

POR REARM

VSS

TVLOW(2) TPOR(3)

Note 1: When NPOR is low, the device is held in Reset.

2: TPOR 1 s typical.
3: TVLOW 2.7 s typical.

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PIC16(L)F1508/9

TABLE 29-2: SUPPLY CURRENT (IDD)(1,2)

PIC16LF1508/9 Standard Operating Conditions (unless otherwise stated)

PIC16F1508/9

Param. Device Conditions

Min. Typ† Max. Units
No. Characteristics VDD Note
D010 — 8 20 A 1.8 FOSC = 32 kHz,
— 10 25 A 3.0 LP Oscillator,
-40°C  TA  +85°C
D010 — 15 31 A 2.3 FOSC = 32 kHz,
— 17 33 A 3.0 LP Oscillator,
-40°C  TA  +85°C
— 21 39 A 5.0
D011 — 60 100 A 1.8 FOSC = 1 MHz,
— 100 180 A 3.0 XT Oscillator
D011 — 100 180 A 2.3 FOSC = 1 MHz,
— 130 220 A 3.0 XT Oscillator
— 170 280 A 5.0
D012 — 140 240 A 1.8 FOSC = 4 MHz,
— 250 360 A 3.0 XT Oscillator
D012 — 210 320 A 2.3 FOSC = 4 MHz,
— 280 410 A 3.0 XT Oscillator
— 340 500 A 5.0
D013 — 30 65 A 1.8 FOSC = 1 MHz,
— 55 100 A 3.0 External Clock (ECM),
Medium-Power mode
D013 — 65 110 A 2.3 FOSC = 1 MHz,
— 85 140 A 3.0 External Clock (ECM),
Medium-Power mode
— 115 190 A 5.0
D014 — 115 190 A 1.8 FOSC = 4 MHz,
— 210 310 A 3.0 External Clock (ECM),
Medium-Power mode
D014 — 180 270 A 2.3 FOSC = 4 MHz,
— 240 365 A 3.0 External Clock (ECM),
Medium-Power mode
— 295 460 A 5.0
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave,
from rail-to-rail; all I/O pins tri-stated, pulled to VSS; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption.
3: For EXTRC oscillator configurations, current through REXT is not included. The current through the resis-
tor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k.

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 PIC16(L)F1508/9
TABLE 29-2: SUPPLY CURRENT (IDD)(1,2) (CONTINUED)
PIC16LF1508/9 Standard Operating Conditions (unless otherwise stated)

PIC16F1508/9

Param. Device Conditions

Min. Typ† Max. Units
No. Characteristics VDD Note
D015 — 3.2 12 A 1.8 FOSC = 31 kHz,
— 5.4 20 A 3.0 LFINTOSC,
-40°C  TA  +85°C
D015 — 13 28 A 2.3 FOSC = 31 kHz,
— 15 30 A 3.0 LFINTOSC,
-40°C  TA  +85°C
— 17 36 A 5.0
D016 — 215 360 A 1.8 FOSC = 500 kHz,
— 275 480 A 3.0 HFINTOSC
D016 — 270 450 A 2.3 FOSC = 500 kHz,
— 300 500 A 3.0 HFINTOSC
— 350 620 A 5.0
D017* — 410 660 A 1.8 FOSC = 8 MHz,
— 630 970 A 3.0 HFINTOSC
D017* — 530 750 A 2.3 FOSC = 8 MHz,
— 660 1100 A 3.0 HFINTOSC
— 730 1200 A 5.0
D018 — 600 940 A 1.8 FOSC = 16 MHz,
— 970 1400 A 3.0 HFINTOSC
D018 — 780 1200 A 2.3 FOSC = 16 MHz,
— 1000 1550 A 3.0 HFINTOSC
— 1090 1700 A 5.0
D019A — 1030 1500 A 3.0 FOSC = 20 MHz,
External Clock (ECH),
High-Power mode
D019A — 1060 1600 A 3.0 FOSC = 20 MHz,
— 1220 1800 A 5.0 External Clock (ECH),
High-Power mode
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave,
from rail-to-rail; all I/O pins tri-stated, pulled to VSS; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption.
3: For EXTRC oscillator configurations, current through REXT is not included. The current through the resis-
tor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k.

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PIC16(L)F1508/9
TABLE 29-2: SUPPLY CURRENT (IDD)(1,2) (CONTINUED)
PIC16LF1508/9 Standard Operating Conditions (unless otherwise stated)

PIC16F1508/9

Param. Device Conditions

Min. Typ† Max. Units
No. Characteristics VDD Note
D019B — 6 16 A 1.8 FOSC = 32 kHz,
— 8 22 A 3.0 External Clock (ECL),
Low-Power mode
D019B — 13 28 A 2.3 FOSC = 32 kHz,
— 15 31 A 3.0 External Clock (ECL),
Low-Power mode
— 16 36 A 5.0
D019C — 19 35 A 1.8 FOSC = 500 kHz,
— 32 55 A 3.0 External Clock (ECL),
Low-Power mode
D019C — 31 52 A 2.3 FOSC = 500 kHz,
— 38 65 A 3.0 External Clock (ECL),
Low-Power mode
— 44 74 A 5.0
D020 — 140 210 A 1.8 FOSC = 4 MHz,
— 250 330 A 3.0 EXTRC (Note 3)
D020 — 210 290 A 2.3 FOSC = 4 MHz,
— 280 380 A 3.0 EXTRC (Note 3)
— 350 470 A 5.0
D021 — 1135 1700 A 3.0 FOSC = 20 MHz,
HS Oscillator
D021 — 1170 1800 A 3.0 FOSC = 20 MHz,
— 1555 2300 A 5.0 HS Oscillator
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave,
from rail-to-rail; all I/O pins tri-stated, pulled to VSS; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption.
3: For EXTRC oscillator configurations, current through REXT is not included. The current through the resis-
tor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k.

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 PIC16(L)F1508/9

TABLE 29-3: POWER-DOWN CURRENTS (IPD)(1,2)

Operating Conditions: (unless otherwise stated)
PIC16LF1508/9
Low-Power Sleep Mode
PIC16F1508/9 Low-Power Sleep Mode, VREGPM = 1

Param. Max. Max. Conditions

Device Characteristics Min. Typ† Units
No. +85°C +125°C VDD Note
D022 Base IPD — 0.020 1.0 8.0 A 1.8 WDT, BOR, FVR and SOSC
— 0.025 2.0 9.0 A 3.0 disabled, all Peripherals inactive

D022 Base IPD — 0.25 3.0 10 A 2.3 WDT, BOR, FVR and SOSC
— 0.30 4.0 12 A 3.0 disabled, all Peripherals inactive,
Low-Power Sleep mode
— 0.40 6.0 15 A 5.0
D022A Base IPD — 9.8 16 18 A 2.3 WDT, BOR, FVR and SOSC
— 10.3 18 20 A 3.0 disabled, all Peripherals inactive,
Normal-Power Sleep mode,
— 11.5 21 26 A 5.0
VREGPM = 0
D023 — 0.26 2.0 9.0 A 1.8 WDT Current
— 0.44 3.0 10 A 3.0
D023 — 0.43 6.0 15 A 2.3 WDT Current
— 0.53 7.0 20 A 3.0
— 0.64 8.0 22 A 5.0
D023A — 15 28 30 A 1.8 FVR Current
— 18 30 33 A 3.0
D023A — 18 33 35 A 2.3 FVR Current
— 19 35 37 A 3.0
— 20 37 39 A 5.0
D024 — 6.0 17 20 A 3.0 BOR Current
D024 — 7.0 17 30 A 3.0 BOR Current
— 8.0 20 40 A 5.0
D24A — 0.1 4.0 10 A 3.0 LPBOR Current
D24A — 0.35 5.0 14 A 3.0 LPBOR Current
— 0.45 8.0 17 A 5.0
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The peripheral  current can be determined by subtracting the base IPD current from this limit. Max. values should be
used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS.
3: ADC clock source is FRC.

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PIC16(L)F1508/9
TABLE 29-3: POWER-DOWN CURRENTS (IPD)(1,2) (CONTINUED)
Operating Conditions: (unless otherwise stated)
PIC16LF1508/9
Low-Power Sleep Mode
PIC16F1508/9 Low-Power Sleep Mode, VREGPM = 1

Param. Max. Max. Conditions

Device Characteristics Min. Typ† Units
No. +85°C +125°C VDD Note
D025 — 0.7 4.0 9.0 A 1.8 SOSC Current
— 2.3 8.0 12 A 3.0
D025 — 1.0 6.0 11 A 2.3 SOSC Current
— 2.4 8.5 20 A 3.0
— 6.9 20 25 A 5.0
D026 — 0.11 1.5 9.0 A 1.8 ADC Current (Note 3),
— 0.12 2.7 10 A 3.0 No conversion in progress

D026 — 0.30 4.0 11 A 2.3 ADC Current (Note 3),

— 0.35 5.0 13 A 3.0 No conversion in progress

— 0.45 8.0 16 A 5.0

D026A* — 250 — — A 1.8 ADC Current (Note 3),
— 250 — — A 3.0 Conversion in progress

D026A* — 280 — — A 2.3 ADC Current (Note 3),

— 280 — — A 3.0 Conversion in progress

— 280 — — A 5.0
D027 — 7 22 25 A 1.8 Comparator,
— 8 23 27 A 3.0 CxSP = 0

D027 — 17 35 37 A 2.3 Comparator,

— 18 37 38 A 3.0 CxSP = 0

— 19 38 40 A 5.0
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The peripheral  current can be determined by subtracting the base IPD current from this limit. Max. values should be
used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS.
3: ADC clock source is FRC.

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 PIC16(L)F1508/9

TABLE 29-4: I/O PORTS

Standard Operating Conditions (unless otherwise stated)

Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
VIL Input Low Voltage
I/O PORT:
D030 with TTL buffer — — 0.8 V 4.5V  VDD  5.5V
D030A — — 0.15 VDD V 1.8V  VDD  4.5V
D031 with Schmitt Trigger buffer — — 0.2 VDD V 2.0V  VDD  5.5V
with I2C™ levels — — 0.3 VDD V
with SMbus levels — — 0.8 V 2.7V  VDD  5.5V
D032 MCLR, OSC1 (EXTRC mode) — — 0.2 VDD V (Note 1)
D033 OSC1 (HS mode) — — 0.3 VDD V
VIH Input High Voltage
I/O PORT:
D040 with TTL buffer 2.0 — — V 4.5V  VDD 5.5V
D040A 0.25 VDD + — — V 1.8V  VDD  4.5V
0.8
D041 with Schmitt Trigger buffer 0.8 VDD — — V 2.0V  VDD  5.5V
with I2C™ levels 0.7 VDD — — V
with SMbus levels 2.1 — — V 2.7V  VDD  5.5V
D042 MCLR 0.8 VDD — — V
D043A OSC1 (HS mode) 0.7 VDD — — V
D043B OSC1 (EXTRC mode) 0.9 VDD — — V VDD  2.0V (Note 1)
IIL Input Leakage Current(2)
D060 I/O Ports — ±5 ± 125 nA VSS  VPIN  VDD,
Pin at high-impedance, 85°C
— ±5 ± 1000 nA VSS  VPIN  VDD,
Pin at high-impedance, 125°C
D061 MCLR(3) — ± 50 ± 200 nA VSS  VPIN  VDD,
Pin at high-impedance, 85°C
IPUR Weak Pull-up Current
D070* 25 100 200 A VDD = 3.3V, VPIN = VSS
25 140 300 A VDD = 5.0V, VPIN = VSS
VOL Output Low Voltage(4)
D080 I/O Ports IOL = 8 mA, VDD = 5V
— — 0.6 V IOL = 6 mA, VDD = 3.3V
IOL = 1.8 mA, VDD = 1.8V
VOH Output High Voltage(4)
D090 I/O Ports IOH = 3.5 mA, VDD = 5V
VDD - 0.7 — — V IOH = 3 mA, VDD = 3.3V
IOH = 1 mA, VDD = 1.8V
D101* COSC2 Capacitive Loading Specifications on Output Pins
OSC2 pin In XT, HS, LP modes when
— — 15 pF external clock is used to drive
OSC1
D101A* CIO All I/O pins — — 50 pF
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an
external clock in EXTRC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: Excluding OSC2 in CLKOUT mode.

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PIC16(L)F1508/9

TABLE 29-5: MEMORY PROGRAMMING SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)
Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
Program Memory
Programming Specifications
D110 VIHH Voltage on MCLR/VPP pin 8.0 — 9.0 V (Note 2)
D111 IDDP Supply Current during — — 10 mA
Programming
D112 VBE VDD for Bulk Erase 2.7 — VDDMAX V
D113 VPEW VDD for Write or Row Erase VDDMIN — VDDMAX V
D114 IPPPGM Current on MCLR/VPP during — 1.0 — mA
Erase/Write
D115 IDDPGM Current on VDD during — 5.0 — mA
Erase/Write
Program Flash Memory
D121 EP Cell Endurance 10K — — E/W -40C  TA  +85C
(Note 1)
D122 VPRW VDD for Read/Write VDDMIN — VDDMAX V
D123 TIW Self-timed Write Cycle Time — 2 2.5 ms
D124 TRETD Characteristic Retention — 40 — Year Provided no other
specifications are violated
D125 EHEFC High-Endurance Flash Cell 100K — — E/W 0C  TA  +60°C, lower
byte last 128 addresses
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Self-write and Block Erase.
2: Required only if single-supply programming is disabled.

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 PIC16(L)F1508/9
TABLE 29-6: THERMAL CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)

Param.
Sym. Characteristic Typ. Units Conditions
No.

TH01 JA Thermal Resistance Junction to Ambient 62.2 C/W 20-pin DIP package
77.7 C/W 20-pin SOIC package
87.3 C/W 20-pin SSOP package
43 C/W 20-pin QFN 4X4mm package
TH02 JC Thermal Resistance Junction to Case 27.5 C/W 20-pin DIP package
23.1 C/W 20-pin SOIC package
31.1 C/W 20-pin SSOP package
5.3 C/W 20-pin QFN 4X4mm package
TH03 TJMAX Maximum Junction Temperature 150 C
TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O
TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1)
TH06 PI/O I/O Power Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH))
TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2)
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature; TJ = Junction Temperature

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PIC16(L)F1508/9
29.4 AC Characteristics
Timing Parameter Symbology has been created with one of the following formats:
1. TppS2ppS
2. TppS
T
F Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc CLKIN
ck CLKOUT rd RD
cs CS rw RD or WR
di SDIx sc SCKx
do SDO ss SS
dt Data in t0 T0CKI
io I/O PORT t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (High-impedance) V Valid
L Low Z High-impedance

FIGURE 29-4: LOAD CONDITIONS

Rev. 10-000133A
8/1/2013

Load Condition

Pin

CL

VSS

Legend: CL=50 pF for all pins

DS40001609C-page 336  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
FIGURE 29-5: CLOCK TIMING

Q4 Q1 Q2 Q3 Q4 Q1

CLKIN
OS02 OS12 OS11

OS03

CLKOUT
(CLKOUT mode)

Note 1: See Table 29-9.

TABLE 29-7: CLOCK OSCILLATOR TIMING REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.

OS01 FOSC External CLKIN Frequency(1) DC — 0.5 MHz External Clock (ECL)
DC — 4 MHz External Clock (ECM)
DC — 20 MHz External Clock (ECH)
Oscillator Frequency(1) — 32.768 — kHz LP Oscillator
0.1 — 4 MHz XT Oscillator
1 — 4 MHz HS Oscillator
1 — 20 MHz HS Oscillator, VDD > 2.7V
DC — 4 MHz EXTRC, VDD > 2.0V
OS02 TOSC External CLKIN Period(1) 27 —  µs LP Oscillator
250 —  ns XT Oscillator
50 —  ns HS Oscillator
50 —  ns External Clock (EC)
Oscillator Period(1) — 30.5 — µs LP Oscillator
250 — 10,000 ns XT Oscillator
50 — 1,000 ns HS Oscillator
250 — — ns EXTRC
OS03 TCY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC
OS04* TosH, External CLKIN High 2 — — µs LP Oscillator
TosL External CLKIN Low 100 — — ns XT Oscillator
20 — — ns HS Oscillator
OS05* TosR, External CLKIN Rise 0 — — ns LP Oscillator
TosF External CLKIN Fall 0 — — ns XT Oscillator
0 — — ns HS Oscillator
* These parameters are characterized but not tested.
†Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at “min” values with an external clock applied to CLKIN pin. When an external
clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

 2011-2013 Microchip Technology Inc. DS40001609C-page 337

PIC16(L)F1508/9
TABLE 29-8: OSCILLATOR PARAMETERS
Standard Operating Conditions (unless otherwise stated)

Param. Freq.
Sym. Characteristic Min. Typ† Max. Units Conditions
No. Tolerance
OS08 HFOSC Internal Calibrated HFINTOSC ±2% — 16.0 — MHz VDD = 3.0V, TA = 25°C,
Frequency(1) (Note 2)
OS09 LFOSC Internal LFINTOSC Frequency — — 31 — kHz (Note 3)
OS10* TIOSC ST HFINTOSC — — 5 15 s
Wake-up from Sleep Start-up Time
OS10A* TLFOSC ST LFINTOSC — — 0.5 — ms -40°C  TA  +125°C
Wake-up from Sleep Start-up Time
*These parameters are characterized but not tested.
†Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
2: See Figure 29-6: “HFINTOSC Frequency Accuracy over Device VDD and Temperature”,
Figure 30-73: “HFINTOSC Accuracy Over Temperature, VDD = 1.8V, PIC16LF1508/9 Only”, and
Figure 30-74: “HFINTOSC Accuracy Over Temperature, 2.3V  VDD 5.5V”.
3: See Figure 30-71: “LFINTOSC Frequency over VDD and Temperature, PIC16LF1508/9 Only”, and
Figure 30-72: “ LFINTOSC Frequency over VDD and Temperature, PIC16F1508/9”.

FIGURE 29-6: HFINTOSC FREQUENCY ACCURACY OVER VDD AND TEMPERATURE

Rev. 10-000135A
7/30/2013

125

±12%

85

-4.5% to +7%
Temperature (°C)

60

25
±4.5%

±12%

-40
1.8 2.3 5.5

VDD (V)

Note: See Figure 30-73: “HFINTOSC Accuracy Over Temperature, VDD = 1.8V, PIC16LF1508/9 Only”,
and Figure 30-74: “HFINTOSC Accuracy Over Temperature, 2.3V VDD  5.5V”.

DS40001609C-page 338  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
FIGURE 29-7: CLKOUT AND I/O TIMING

Cycle Write Fetch Read Execute

Q4 Q1 Q2 Q3

FOSC
OS11 OS12
OS20
CLKOUT OS21
OS19 OS16 OS18
OS13 OS17
I/O pin
(Input)

OS15 OS14
I/O pin Old Value New Value
(Output)
OS18, OS19

TABLE 29-9: CLKOUT AND I/O TIMING PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.

OS11 TosH2ckL FOSC to CLKOUT(1) — — 70 ns 3.3V  VDD 5.0V

OS12 TosH2ckH FOSC to CLKOUT(1) — — 72 ns 3.3V  VDD 5.0V
(1)
OS13 TckL2ioV CLKOUT to Port out valid — — 20 ns
OS14 TioV2ckH Port input valid before CLKOUT(1) TOSC + 200 ns — — ns
OS15 TosH2ioV Fosc (Q1 cycle) to Port out valid — 50 70* ns 3.3V  VDD 5.0V
OS16 TosH2ioI Fosc (Q2 cycle) to Port input invalid 50 — — ns 3.3V  VDD 5.0V
(I/O in setup time)
OS17 TioV2osH Port input valid to Fosc(Q2 cycle) 20 — — ns
(I/O in setup time)
OS18* TioR Port output rise time — 40 72 ns VDD = 1.8V
— 15 32 3.3V  VDD 5.0V
OS19* TioF Port output fall time — 28 55 ns VDD = 1.8V
— 15 30 3.3V  VDD 5.0V
OS20* Tinp INT pin input high or low time 25 — — ns
OS21* Tioc Interrupt-on-change new input level time 25 — — ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25C unless otherwise stated.
Note 1: Measurements are taken in EXTRC mode where CLKOUT output is 4 x TOSC.

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PIC16(L)F1508/9
FIGURE 29-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING

VDD

MCLR

30
Internal
POR
33
PWRT
Time-out 32
OSC
Start-up Time

Internal Reset(1)

Watchdog Timer
Reset(1)
31
34
34
I/O pins

Note 1: Asserted low.

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 PIC16(L)F1508/9
TABLE 29-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated)

Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.

30 TMCL MCLR Pulse Width (low) 2 — — s

31 TWDTLP Low-Power Watchdog Timer 10 16 27 ms VDD = 3.3V-5V,
Time-out Period 1:16 Prescaler used
32 TOST Oscillator Start-up Timer Period(1) — 1024 — TOSC
33* TPWRT Power-up Timer Period 40 65 140 ms PWRTE = 0
34* TIOZ I/O high-impedance from MCLR Low — — 2.0 s
or Watchdog Timer Reset
35 VBOR Brown-out Reset Voltage(2) 2.55 2.70 2.85 V BORV = 0

2.35 2.45 2.58 V BORV = 1 (PIC16F1508/9)

1.80 1.90 2.05 V BORV = 1 (PIC16LF1508/9)
36* VHYST Brown-out Reset Hysteresis 0 25 60 mV -40°C  TA  +85°C
37* TBORDC Brown-out Reset DC Response Time 1 16 35 s VDD  VBOR
38 VLPBOR Low-Power Brown-Out Reset Voltage 1.8 2.1 2.5 V LPBOR = 1
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency.
2: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.

FIGURE 29-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS

VDD
VBOR and VHYST
VBOR

(Device in Brown-out Reset) (Device not in Brown-out Reset)

37

Reset
33
(due to BOR)

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PIC16(L)F1508/9
FIGURE 29-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

T0CKI

40 41

42

T1CKI

45 46

47 49

TMR0 or
TMR1

TABLE 29-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 10 — — ns
41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 10 — — ns
42* TT0P T0CKI Period Greater of: — — ns N = prescale value
20 or TCY + 40
N
45* TT1H T1CKI High Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Time Synchronous, with Prescaler 15 — — ns
Asynchronous 30 — — ns
46* TT1L T1CKI Low Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Time Synchronous, with Prescaler 15 — — ns
Asynchronous 30 — — ns
47* TT1P T1CKI Input Synchronous Greater of: — — ns N = prescale value
Period 30 or TCY + 40
N
Asynchronous 60 — — ns
48 FT1 Secondary Oscillator Input Frequency Range 32.4 32.768 33.1 kHz
(Oscillator enabled by setting bit T1OSCEN)
49* TCKEZTMR1 Delay from External Clock Edge to Timer 2 TOSC — 7 TOSC — Timers in Sync
Increment mode
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.

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 PIC16(L)F1508/9
FIGURE 29-11: CLC PROPAGATION TIMING

Rev. 10-000031A
7/30/2013

CLC LCx_in[n](1) CLC CLC

CLCxINn
Input time Module Output time
CLCx
LCx_out(1)

CLC CLC CLC

CLCxINn
Input time Module Output time
CLCx
LCx_in[n](1) LCx_out(1)

CLC01 CLC02 CLC03

Note 1: See FIGURE 24-1: Digital-to-Analog Converter Block Diagram to identify specific CLC signals.

TABLE 29-12: CONFIGURATION LOGIC CELL (CLC) CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
CLC01* TCLCIN CLC input time — 7 — ns
CLC02* TCLC CLC module input to output progagation time — 24 — ns VDD = 1.8V
— 12 — ns VDD > 3.6V
CLC03* TCLCOUT CLC output time Rise Time — OS18 — — (Note 1)
Fall Time — OS19 — — (Note 1)
CLC04* FCLCMAX CLC maximum switching frequency — 45 — MHz
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: See Table 29-9 for OS18 and OS19 rise and fall times.

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PIC16(L)F1508/9
TABLE 29-13: ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS(1,2,3)
Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25°C
Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
AD01 NR Resolution — — 10 bit
AD02 EIL Integral Error — ±1 ±1.7 LSb VREF = 3.0V
AD03 EDL Differential Error — ±1 ±1 LSb No missing codes
VREF = 3.0V
AD04 EOFF Offset Error — ±1 ±2.5 LSb VREF = 3.0V
AD05 EGN Gain Error — ±1 ±2.0 LSb VREF = 3.0V
AD06 VREF Reference Voltage 1.8 — VDD V VREF = (VRPOS - VRNEG) (Note 4)
AD07 VAIN Full-Scale Range VSS — VREF V
AD08 ZAIN Recommended Impedance of — — 10 k Can go higher if external 0.01F capacitor is
Analog Voltage Source present on input pin.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Total Absolute Error includes integral, differential, offset and gain errors.
2: The ADC conversion result never decreases with an increase in the input voltage and has no missing codes.
3: See Section 30.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.
4: ADC VREF is selected by ADPREF<0> bit.

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 PIC16(L)F1508/9
FIGURE 29-12: ADC CONVERSION TIMING (ADC CLOCK FOSC-BASED)

BSF ADCON0, GO
1 TCY
AD133
AD131
Q4
AD130

ADC_clk

ADC Data 9 8 7 6 3 2 1 0

ADRES OLD_DATA NEW_DATA

ADIF 1 TCY

GO DONE
Sampling Stopped
Sample AD132

FIGURE 29-13: ADC CONVERSION TIMING (ADC CLOCK FROM FRC)

BSF ADCON0, GO
AD133 1 TCY
AD131
Q4
AD130
ADC_clk

ADC Data 9 8 7 6 3 2 1 0

ADRES OLD_DATA NEW_DATA

ADIF 1 TCY

GO DONE

AD132 Sampling Stopped

Sample

Note 1: If the ADC clock source is selected as FRC, a time of TCY is added before the ADC clock starts. This allows the
SLEEP instruction to be executed.

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PIC16(L)F1508/9
TABLE 29-14: ADC CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)

Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
AD130* TAD ADC Clock Period (TADC) 1.0 — 6.0 s FOSC-based
ADC Internal FRC Oscillator Period (TFRC) 1.0 2.0 6.0 s ADCS<2:0> = x11 (ADC FRC mode)
AD131 TCNV Conversion Time — 11 — TAD Set GO/DONE bit to conversion
(not including Acquisition Time)(1) complete
AD132* TACQ Acquisition Time — 5.0 — s
AD133* THCD Holding Capacitor Disconnect Time — 1/2 TAD — FOSC-based
— 1/2 TAD + — ADCS<2:0> = x11 (ADC FRC mode)
1TCY
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: The ADRES register may be read on the following TCY cycle.

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 PIC16(L)F1508/9
TABLE 29-15: COMPARATOR SPECIFICATIONS(1)
Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25°C

Param.
Sym. Characteristics Min. Typ. Max. Units Comments
No.
CM01 VIOFF Input Offset Voltage — ±7.5 ±60 mV CxSP = 1,
VICM = VDD/2
CM02 VICM Input Common Mode Voltage 0 — VDD V
CM03 CMRR Common Mode Rejection Ration — 50 — dB
CM04A Response Time Rising Edge — 400 800 ns CxSP = 1
CM04B Response Time Falling Edge — 200 400 ns CxSP = 1
TRESP(2)
CM04C Response Time Rising Edge — 1200 — ns CxSP = 0
CM04D Response Time Falling Edge — 550 — ns CxSP = 0
CM05* TMC2OV Comparator Mode Change to — — 10 s
Output Valid
CM06 CHYSTER Comparator Hysteresis — 25 — mV CxHYS = 1,
CxSP = 1
* These parameters are characterized but not tested.
Note 1: See Section 30.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.
2: Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to
VDD.

TABLE 29-16: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS(1)

Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25°C
Param.
Sym. Characteristics Min. Typ. Max. Units Comments
No.
DAC01* CLSB Step Size — VDD/32 — V
DAC02* CACC Absolute Accuracy — —  1/2 LSb
DAC03* CR Unit Resistor Value (R) — 5K — 
DAC04* CST Settling Time(2) — — 10 s
* These parameters are characterized but not tested.
Note 1: See Section 30.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.
2: Settling time measured while DACR<4:0> transitions from ‘0000’ to ‘1111’.

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PIC16(L)F1508/9
FIGURE 29-14: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

CK
US121 US121

DT

US120 US122

Note: Refer to Figure 29-4 for load conditions.

TABLE 29-17: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.
Symbol Characteristic Min. Max. Units Conditions
No.
US120 TCKH2DTV SYNC XMIT (Master and Slave) — 80 ns 3.0V  VDD  5.5V
Clock high to data-out valid — 100 ns 1.8V  VDD  5.5V
US121 TCKRF Clock out rise time and fall time — 45 ns 3.0V  VDD  5.5V
(Master mode) — 50 ns 1.8V  VDD  5.5V
US122 TDTRF Data-out rise time and fall time — 45 ns 3.0V  VDD  5.5V
— 50 ns 1.8V  VDD  5.5V

FIGURE 29-15: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

CK
US125

DT
US126

Note: Refer to Figure 29-4 for load conditions.

TABLE 29-18: USART SYNCHRONOUS RECEIVE REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.
Symbol Characteristic Min. Max. Units Conditions
No.
US125 TDTV2CKL SYNC RCV (Master and Slave)
Data-hold before CK  (DT hold time) 10 — ns
US126 TCKL2DTL Data-hold after CK  (DT hold time) 15 — ns

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 PIC16(L)F1508/9
FIGURE 29-16: SPI MASTER MODE TIMING (CKE = 0, SMP = 0)

SS

SP81
SCK
(CKP = 0)
SP71 SP72
SP78 SP79

SCK
(CKP = 1)

SP79 SP78
SP80

SDO MSb bit 6 - - - - - -1 LSb

SP75, SP76

SDI MSb In bit 6 - - - -1 LSb In

SP74
SP73

Note: Refer to Figure 29-4 for load conditions.

FIGURE 29-17: SPI MASTER MODE TIMING (CKE = 1, SMP = 1)

SS

SP81
SCK
(CKP = 0)
SP71 SP72
SP79
SP73
SCK
(CKP = 1)

SP80
SP78

SDO MSb bit 6 - - - - - -1 LSb

SP75, SP76

SDI MSb In bit 6 - - - -1 LSb In

SP74

Note: Refer to Figure 29-4 for load conditions.

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PIC16(L)F1508/9
FIGURE 29-18: SPI SLAVE MODE TIMING (CKE = 0)

SS

SP70

SCK SP83
(CKP = 0)
SP71 SP72
SP78 SP79

SCK
(CKP = 1)

SP79 SP78
SP80

SDO MSb bit 6 - - - - - -1 LSb

SP75, SP76 SP77

SDI MSb In bit 6 - - - -1 LSb In

SP74

SP73

Note: Refer to Figure 29-4 for load conditions.

FIGURE 29-19: SPI SLAVE MODE TIMING (CKE = 1)

SP82
SS

SP70
SCK SP83
(CKP = 0)

SP71 SP72

SCK
(CKP = 1)

SP80

SDO MSb bit 6 - - - - - -1 LSb

SP77
SP75, SP76

SDI
MSb In bit 6 - - - -1 LSb In

SP74

Note: Refer to Figure 29-4 for load conditions.

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 PIC16(L)F1508/9
TABLE 29-19: SPI MODE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)

Param.
Symbol Characteristic Min. Typ† Max. Units Conditions
No.

SP70* TSSL2SCH, SS to SCK or SCK input 2.25 TCY — — ns

TSSL2SCL
SP71* TSCH SCK input high time (Slave mode) 1 TCY + 20 — — ns
SP72* TSCL SCK input low time (Slave mode) 1 TCY + 20 — — ns
SP73* TDIV2SCH, Setup time of SDI data input to SCK 100 — — ns
TDIV2SCL edge
SP74* TSCH2DIL, Hold time of SDI data input to SCK 100 — — ns
TSCL2DIL edge
SP75* TDOR SDO data output rise time — 10 25 ns 3.0V  VDD  5.5V
— 25 50 ns 1.8V  VDD  5.5V
SP76* TDOF SDO data output fall time — 10 25 ns
SP77* TSSH2DOZ SS to SDO output high-impedance 10 — 50 ns
SP78* TSCR SCK output rise time — 10 25 ns 3.0V  VDD  5.5V
(Master mode) — 25 50 ns 1.8V  VDD  5.5V
SP79* TSCF SCK output fall time (Master mode) — 10 25 ns
SP80* TSCH2DOV, SDO data output valid after SCK — — 50 ns 3.0V  VDD  5.5V
TSCL2DOV edge — — 145 ns 1.8V  VDD  5.5V
SP81* TDOV2SCH, SDO data output setup to SCK edge 1 Tcy — — ns
TDOV2SCL
SP82* TSSL2DOV SDO data output valid after SS — — 50 ns
edge
SP83* TSCH2SSH, SS after SCK edge 1.5 TCY + 40 — — ns
TSCL2SSH
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.

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PIC16(L)F1508/9
FIGURE 29-20: I2C™ BUS START/STOP BITS TIMING

SCL
SP91 SP93
SP90 SP92

SDA

Start Stop
Condition Condition

Note: Refer to Figure 29-4 for load conditions.

TABLE 29-20: I2C™ BUS START/STOP BITS REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.
Symbol Characteristic Min. Typ Max. Units Conditions
No.

SP90* TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Repeated
Setup time 400 kHz mode 600 — — Start condition
SP91* THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first
Hold time 400 kHz mode 600 — — clock pulse is generated
SP92* TSU:STO Stop condition 100 kHz mode 4700 — — ns
Setup time 400 kHz mode 600 — —
SP93 THD:STO Stop condition 100 kHz mode 4000 — — ns
Hold time 400 kHz mode 600 — —
* These parameters are characterized but not tested.

FIGURE 29-21: I2C™ BUS DATA TIMING

SP103 SP100 SP102

SP101

SCL
SP90
SP106
SP107
SP91 SP92
SDA
In
SP110
SP109
SP109
SDA
Out

Note: Refer to Figure 29-4 for load conditions.

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 PIC16(L)F1508/9
TABLE 29-21: I2C™ BUS DATA REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)

Param.
Symbol Characteristic Min. Max. Units Conditions
No.
SP100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 — s Device must operate at a
minimum of 10 MHz
SSP module 1.5TCY —
SP101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 1.3 — s Device must operate at a
minimum of 10 MHz
SSP module 1.5TCY —
SP102* TR SDA and SCL rise 100 kHz mode — 1000 ns
time 400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from
10-400 pF
SP103* TF SDA and SCL fall 100 kHz mode — 250 ns
time 400 kHz mode 20 + 0.1CB 250 ns CB is specified to be from
10-400 pF
SP106* THD:DAT Data input hold time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 s
SP107* TSU:DAT Data input setup 100 kHz mode 250 — ns (Note 2)
time 400 kHz mode 100 — ns
SP109* TAA Output valid from 100 kHz mode — 3500 ns (Note 1)
clock 400 kHz mode — — ns
SP110* TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free
400 kHz mode 1.3 — s before a new transmission
can start
SP111 CB Bus capacitive loading — 400 pF
* These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A Fast mode (400 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system, but
the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does
not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal,
it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to
the Standard mode I2C bus specification), before the SCL line is released.

 2011-2013 Microchip Technology Inc. DS40001609C-page 353

PIC16(L)F1508/9
NOTES:

DS40001609C-page 354  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
30.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at 25C. “MAXIMUM”, “Max.”, “MINIMUM” or “Min.”
represents (mean + 3) or (mean - 3) respectively, where  is a standard deviation, over each
temperature range.

 2011-2013 Microchip Technology Inc. DS40001609C-page 355

PIC16(L)F1508/9
FIGURE 30-1: IDD, LP OSCILLATOR, FOSC = 32 kHz, PIC16LF1508/9 ONLY

18

16 Max: 85°C + 3ı Max.

Typical: 25°C
14

12
Typical
IDD (µA)

10

0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

VDD (V)

FIGURE 30-2: IDD, LP OSCILLATOR, FOSC = 32 kHz, PIC16F1508/9 ONLY

30
Max.
Max: 85°C + 3ı
25 Typical: 25°C
Typical
20
IDD (µA)

15

10

0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

DS40001609C-page 356  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
FIGURE 30-3: IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC16LF1508/9 ONLY

350

300 Typical: 25°C

4 MHz EXTRC
250

200 4 MHz XT
IDD (µA)

150

1 MHz XT
100

50
1 MHz EXTRC
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

VDD (V)

FIGURE 30-4: IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC16LF1508/9 ONLY

400

350 Max: 85°C + 3ı

4 MHz XT
300

250
IDD (µA)

200 4 MHz EXTRC

150 1 MHz XT

100

50
1 MHz EXTRC

0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

VDD (V)

 2011-2013 Microchip Technology Inc. DS40001609C-page 357

PIC16(L)F1508/9
FIGURE 30-5: IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC16F1508/9 ONLY

400
4 MHz EXTRC
350 Typical: 25°C

300 4 MHz XT

250
IDD (µA)

200 1 MHz XT

150

100 1 MHz EXTRC

50

0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

FIGURE 30-6: IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC16F1508/9 ONLY

500

450 Max: 85°C + 3ı 4 MHz XT

400
4 MHz EXTRC
350

300
IDD (µA)

250 1 MHz XT

200

150
1 MHz EXTRC
100

50

0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

DS40001609C-page 358  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
FIGURE 30-7: IDD, EXTERNAL CLOCK (ECL), LOW-POWER MODE, FOSC = 32 kHz,
PIC16LF1508/9 ONLY

14
Max.

12

10
Typical
8
IDD (µA)

Max: 85°C + 3ı
2 Typical: 25°C

0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

VDD (V)

FIGURE 30-8: IDD, EXTERNAL CLOCK (ECL), LOW-POWER MODE, FOSC = 32 kHz,
PIC16F1508/9 ONLY

25
Max.

20
Typical

15
IDD (µA)

10

Max: 85°C + 3ı
5 Typical: 25°C

0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

 2011-2013 Microchip Technology Inc. DS40001609C-page 359

PIC16(L)F1508/9
FIGURE 30-9: IDD, EXTERNAL CLOCK (ECL), LOW-POWER MODE, FOSC = 500 kHz,
PIC16LF1508/9 ONLY

50

45 Max: 85°C + 3ı
Typical: 25°C
40
Max.
35

30
Typical
IDD (µA)

25

20

15

10

0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

VDD (V)

FIGURE 30-10: IDD, EXTERNAL CLOCK (ECL), LOW-POWER MODE, FOSC = 500 kHz,
PIC16F1508/9 ONLY

60
Max.
50

40 Typical
IDD (µA)

30

20

Max: 85°C + 3ı
10 Typical: 25°C

0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

DS40001609C-page 360  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
FIGURE 30-11: IDD TYPICAL, EXTERNAL CLOCK (ECM), MEDIUM-POWER MODE,
PIC16LF1508/9 ONLY

300

250 Typical: 25°C

4 MHz
200
IDD (µA)

150

100
1 MHz
50

0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)

FIGURE 30-12: IDD MAXIMUM, EXTERNAL CLOCK (ECM), MEDIUM-POWER MODE,

PIC16LF1508/9 ONLY

350

300 Max: 85°C + 3ı

250 4 MHz

200
IDD (µA)

150

100
1 MHz

50

0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

VDD (V)

 2011-2013 Microchip Technology Inc. DS40001609C-page 361

PIC16(L)F1508/9
FIGURE 30-13: IDD TYPICAL, EXTERNAL CLOCK (ECM), MEDIUM-POWER MODE,
PIC16F1508/9 ONLY

350
4 MHz
300 Typical: 25°C

250
IDD (µA)

200

150
1 MHz

100

50

0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

FIGURE 30-14: IDD MAXIMUM, EXTERNAL CLOCK (ECM), MEDIUM-POWER MODE,

PIC16F1508/9 ONLY

400
4 MHz
350 Max: 85°C + 3ı

300

250
IDD (µA)

200
1 MHz
150

100

50

0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

DS40001609C-page 362  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
FIGURE 30-15: IDD TYPICAL, EXTERNAL CLOCK (ECH), HIGH-POWER MODE,
PIC16LF1508/9 ONLY

1.4
20 MHz
1.2 Typical: 25°C

1.0 16 MHz
IDD (mA)

0.8

0.6
8 MHz

0.4

0.2

0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)

FIGURE 30-16: IDD MAXIMUM, EXTERNAL CLOCK (ECH), HIGH-POWER MODE,

PIC16LF1508/9 ONLY( )

1.6

20 MHz
1.4 Max: 85°C + 3ı

1.2 16 MHz

1.0
IDD (mA)

0.8
8 MHz
0.6

0.4

0.2

0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)

 2011-2013 Microchip Technology Inc. DS40001609C-page 363

PIC16(L)F1508/9
FIGURE 30-17: IDD TYPICAL, EXTERNAL CLOCK (ECH), HIGH-POWER MODE,
PIC16F1508/9 ONLY

1.4
20 MHz
1.2 Typical: 25°C
16 MHz
1.0

0.8
IDD (mA)

8 MHz
0.6

0.4

0.2

0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

FIGURE 30-18: IDD MAXIMUM, EXTERNAL CLOCK (ECH), HIGH-POWER MODE,

PIC16F1508/9 ONLY

1.6
20 MHz
1.4 Max: 85°C + 3ı

1.2 16 MHz

1.0
IDD (mA)

0.8
8 MHz
0.6

0.4

0.2

0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

DS40001609C-page 364  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
FIGURE 30-19: IDD, LFINTOSC, FOSC = 31 kHz, PIC16LF1508/9 ONLY

12

Max: 85°C + 3ı Max.

10
Typical: 25°C

8
IDD (µA)

6 Typical

0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

VDD (V)

FIGURE 30-20: IDD, LFINTOSC, FOSC = 31 kHz, PIC16F1508/9 ONLY

25
Max.

20
Typical
IDD (µA)

15

10

Max: 85°C + 3ı
5 Typical: 25°C

0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

 2011-2013 Microchip Technology Inc. DS40001609C-page 365

PIC16(L)F1508/9
FIGURE 30-21: IDD, MFINTOSC, FOSC = 500 kHz, PIC16LF1508/9 ONLY

400
Max: 85°C + 3ı
350 Typical: 25°C Max.

300

250 Typical
IDD (µA)

200

150

100

50

0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

VDD (V)

FIGURE 30-22: IDD, MFINTOSC, FOSC = 500 kHz, PIC16F1508/9 ONLY

450
Max: 85°C + 3ı Max.
400 Typical: 25°C
350
Typical
300
IDD (µA)

250

200

150

100

50

0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

DS40001609C-page 366  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
FIGURE 30-23: IDD TYPICAL, HFINTOSC, PIC16LF1508/9 ONLY

1.4

1.2 Typical: 25°C

16 MHz
1.0
IDD (mA)

0.8
8 MHz
0.6
4 MHz
0.4

0.2

0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

VDD (V)

FIGURE 30-24: IDD MAXIMUM, HFINTOSC, PIC16LF1508/9 ONLY

1.6

1.4 Max: 85°C + 3ı

16 MHz
1.2

1.0
IDD (mA)

8 MHz
0.8

0.6 4 MHz

0.4

0.2

0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

VDD (V)

 2011-2013 Microchip Technology Inc. DS40001609C-page 367

PIC16(L)F1508/9
FIGURE 30-25: IDD TYPICAL, HFINTOSC, PIC16F1508/9 ONLY

1.2

1.0 16 MHz

0.8
IDD (mA)

8 MHz
0.6

4 MHz
0.4

0.2 Typical: 25°C

0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

FIGURE 30-26: IDD MAXIMUM, HFINTOSC, PIC16F1508/9 ONLY

1.4

1.2 16 MHz

1.0

0.8
IDD (mA)

8 MHz

0.6
4 MHz
0.4

0.2 Max: 85°C + 3ı

0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

DS40001609C-page 368  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
FIGURE 30-27: IDD TYPICAL, HS OSCILLATOR, PIC16LF1508/9 ONLY

1.6

1.4 Typical: 25°C

20 MHz
1.2

1.0
IDD (mA)

0.8

0.6 8 MHz

0.4
4 MHz
0.2

0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)

FIGURE 30-28: , IDD MAXIMUM, HS OSCILLATOR, PIC16LF1508/9 ONLY

1.8

1.6 Max: 85°C + 3ı

1.4 20 MHz

1.2

1.0
IDD (mA)

0.8
8 MHz
0.6

0.4 4 MHz

0.2

0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)

 2011-2013 Microchip Technology Inc. DS40001609C-page 369

PIC16(L)F1508/9
FIGURE 30-29: IDD TYPICAL, HS OSCILLATOR, PIC16F1508/9 ONLY

1.8
20 MHz
1.6 Typical: 25°C

1.4

1.2

1.0
IDD (mA)

0.8 8 MHz

0.6
4 MHz
0.4

0.2

0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

FIGURE 30-30: , IDD MAXIMUM, HS OSCILLATOR, PIC16F1508/9 ONLY

2.5

Max: 85°C + 3ı

2.0 20 MHz

1.5
IDD (mA)

1.0 8 MHz

4 MHz
0.5

0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

DS40001609C-page 370  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
FIGURE 30-31: IPD BASE, LOW-POWER SLEEP MODE, PIC16LF1508/9 ONLY

450
Max: 85°C + 3
M 3ı
400
Typical: 25°C Max.
350

300
D (nA)

250
IPD

200

150

100
Typical
50

0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

VDD (V)

FIGURE 30-32: IPD BASE, LOW-POWER SLEEP MODE, VREGPM = 1, PIC16F1508/9 ONLY

600
Max.
Max: 85°C + 3ı
500 Typical: 25°C

400
IPD (nA)

300
Typical
200

100

0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

 2011-2013 Microchip Technology Inc. DS40001609C-page 371

PIC16(L)F1508/9
FIGURE 30-33: IPD, WATCHDOG TIMER (WDT), PIC16LF1508/9 ONLY

2.0

1.8 Max: 85°C + 3ı

1.6 Typical: 25°C

1.4 Max.

1.2
(µA)
IPD (µA

1.0

0.8
08

0.6 Typical
0.4

0.2

0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

VDD (V)

FIGURE 30-34: IPD, WATCHDOG TIMER (WDT), PIC16F1508/9 ONLY

1.4
Max
Max.
1.2

1.0
A)

0.8
IPD (µA

Typical
0.6

0.4

Max: 85°C + 3ı
0.2
Typical: 25°C

0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

DS40001609C-page 372  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
FIGURE 30-35: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC16LF1508/9 ONLY

45
Max: 85°C + 3ı
40
Typical: 25°C
35
Max.
30

25 Typical
A)
IPD (µA

20

15

10

0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

VDD (V)

FIGURE 30-36: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC16F1508/9 ONLY

30

25 Max.

20
Typical
IPD (µA)

15

10

Max: 85°C + 3ı
5 Typical: 25°C

0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

 2011-2013 Microchip Technology Inc. DS40001609C-page 373

PIC16(L)F1508/9
FIGURE 30-37: IPD, BROWN-OUT RESET (BOR), BORV = 0, PIC16LF1508/9 ONLY

10
Max.
9
Max: 85°C + 3ı
8 Typical: 25°C

7
Typical
6
D (µA)

5
IPD

0
16
1.6 1
1.8
8 2
2.0
0 2
2.2
2 2
2.4
4 2
2.6
6 2
2.8
8 3
3.0
0 3
3.2
2 3
3.4
4 3
3.6
6 3
3.8
8

VDD (V)

FIGURE 30-38: IPD, BROWN-OUT RESET (BOR), BORV = 1, PIC16LF1508/9 ONLY

12

Max: 85°C + 3ı Max.

10 Typical: 25°C

8
Typical
IPD (µA)

0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

VDD (V)

DS40001609C-page 374  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
FIGURE 30-39: IPD, BROWN-OUT RESET (BOR), BORV = 0, PIC16F1508/9 ONLY

12

M
Max.
Max: 85°C + 3ı
10 Typical: 25°C

8
Typical
IPD (µA)

0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

FIGURE 30-40: IPD, BROWN-OUT RESET (BOR), BORV = 1, PIC16F1508/9 ONLY

14
Max
Max.
12 Max: 85°C + 3ı
Typical: 25°C

10

Typical
8
IPD (µA)

0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

 2011-2013 Microchip Technology Inc. DS40001609C-page 375

PIC16(L)F1508/9
FIGURE 30-41: IPD, SECONDARY OSCILLATOR, FOSC = 32 kHz, PIC16LF1508/9 ONLY

8.0

Max: 85°C + 3ı
7.0
Typical: 25°C

6.0
Max.
5.0
A)
IPD (µA

4.0

3.0
30
Typical
2.0

1.0

0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

VDD (V)

FIGURE 30-42: IPD, SECONDARY OSCILLATOR, FOSC = 32 kHz, PIC16F1508/9 ONLY

16
Max: 85°C + 3ı
14 Typical: 25°C
Max.
12

10
IPD (µA)

8
Typical
6

0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

DS40001609C-page 376  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
FIGURE 30-43: IPD, COMPARATOR, LOW-POWER MODE (CxSP = 0), PIC16LF1508/9 ONLY

14

12 Max.

10
IPD (µA)

8
Typical
6

Max: 85°C + 3ı
2 Typical: 25°C

0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)

FIGURE 30-44: IPD, COMPARATOR, LOW-POWER MODE (CxSP = 0), PIC16F1508/9 ONLY

30

25
Max.

20
IPD (µA)

Typical
yp
15

10

5 Max: 85°C + 3ı
Typical: 25°C

0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

 2011-2013 Microchip Technology Inc. DS40001609C-page 377

PIC16(L)F1508/9
FIGURE 30-45: IPD, COMPARATOR, NORMAL-POWER MODE (CxSP = 1), PIC16LF1508/9 ONLY

40

35 Max.

30

25
A)
IPD (µA

20 Typical

15

10

Max: 85°C + 3ı
5
Typical: 25 C
25°C
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

VDD (V)

FIGURE 30-46: IPD, COMPARATOR, NORMAL-POWER MODE (CxSP = 1), PIC16F1508/9 ONLY

60

50

Max.
40
A)
IPD (µA

30
Typical

20

Max: 85°C + 3ı
10 Typical: 25°C

0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

DS40001609C-page 378  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
FIGURE 30-47: VOH vs. IOH OVER TEMPERATURE, VDD = 5.5V, PIC16F1508/9 ONLY

Max: 125°C + 3ı
5 Typical: 25°C
Min: -40°C - 3ı

4
VOH (V)

Min. (-40°C)
3

Typical (25°C)
2
Max. (125°C)

0
-45 -40 -35 -30 -25 -20 -15 -10 -5 0
IOH (mA)

FIGURE 30-48: VOL vs. IOL OVER TEMPERATURE, VDD = 5.5V, PIC16F1508/9 ONLY

Max: 125°C + 3ı Max. (125°C)

4 Typical: 25°C
Min: -40°C - 3ı

Typical (25°C)
3
VOL (V)

Min. (-40°C)
2

0
0 10 20 30 40 50 60 70 80 90 100
IOL (mA)

 2011-2013 Microchip Technology Inc. DS40001609C-page 379

PIC16(L)F1508/9
FIGURE 30-49: VOH vs. IOH OVER TEMPERATURE, VDD = 3.0V

3.5
Max: 125°C + 3ı
3.0 Typical: 25°C
Min: -40°C - 3ı
2.5
VOH (V)

2.0

1.5

1.0
Min. (-40°C) Typical (25°C) Max. (125°C)
0.5

0.0
-15 -13 -11 -9 -7 -5 -3 -1
IOH (mA)

FIGURE 30-50: VOL vs. IOL OVER TEMPERATURE, VDD = 3.0V

3.0

Max: 125°C + 3ı
2.5 Typical: 25°C
Min: -40°C - 3ı

2.0

Min. (-40°C)
VOL (V)

Max. (125°C) Typical (25°C)

1.5

1.0

0.5

0.0
0 5 10 15 20 25 30 35 40
IOL (mA)

DS40001609C-page 380  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
FIGURE 30-51: VOH vs. IOH OVER TEMPERATURE, VDD = 1.8V, PIC16LF1508/9 ONLY

2.0

1.8 Max: 125°C + 3ı

Typical: 25°C
1.6 Min: -40°C - 3ı
1.4

1.2
VOH (V)

Min. (-40°C) Typical (25°C) Max. (125°C)

1.0

0.8

0.6

0.4

0.2

0.0
-4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0

IOH (mA)

FIGURE 30-52: VOL vs. IOL OVER TEMPERATURE, VDD = 1.8V, PIC16LF1508/9 ONLY

1.8

1.6 Max: 125°C + 3ı

Typical: 25°C
1.4 Min: -40°C - 3ı

1.2
VOL (V)

1.0

0.8
Max. (125°C) Typical (25°C) Min. (-40°C)
0.6

0.4

0.2

0.0
0 1 2 3 4 5 6 7 8 9 10
IOL (mA)

 2011-2013 Microchip Technology Inc. DS40001609C-page 381

PIC16(L)F1508/9
FIGURE 30-53: POR RELEASE VOLTAGE

1.70

1.68
Max.
1.66

1.64 Typical

1.62
Voltage (V)

Min.
1.60

1.58

1.56

1.54 Max: Typical + 3ı

Typical: 25°C
1.52 Min: Typical - 3ı

1.50
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)

FIGURE 30-54: POR REARM VOLTAGE, PIC16F1508/9 ONLY

1.54

1.52 Max: Typical + 3ı

Typical: 25°C
1.50 Min: Typical - 3ı
Max.
1.48

1.46
Voltage (V)

1.44
Typical
1.42

1.40
Min.
1.38

1.36

1.34
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)

DS40001609C-page 382  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
FIGURE 30-55: BROWN-OUT RESET VOLTAGE, BORV = 1, PIC16LF1508/9 ONLY

2.00

Max.
1.95
Voltage (V)

Typical
1.90

1.85 Min.
Max: Typical + 3ı
Min: Typical - 3ı

1.80
-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (°C)

FIGURE 30-56: BROWN-OUT RESET HYSTERESIS, BORV = 1, PIC16LF1508/9 ONLY

60

50 Max.
Max: Typical + 3ı
40 Typical: 25°C
Min: Typical - 3ı
Voltage (mV)

Typical
30

20
Min.

10

0
-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (°C)

 2011-2013 Microchip Technology Inc. DS40001609C-page 383

PIC16(L)F1508/9
FIGURE 30-57: BROWN-OUT RESET VOLTAGE, BORV = 1, PIC16F1508/9 ONLY

2.60

2.55 Max.

2.50
Typical
Voltage (V)

2.45

Min.
2.40

Max: Typical + 3ı
2.35 Min: Typical - 3ı

2.30
-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (°C)

FIGURE 30-58: BROWN-OUT RESET HYSTERESIS, BORV = 1, PIC16F1508/9 ONLY

70

Max.
60
Max: Typical + 3ı
50 Typical: 25°C
Min: Typical - 3ı
Voltage (mV)

40
Typical

30

20
Min.
10

0
-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (°C)

DS40001609C-page 384  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
FIGURE 30-59: BROWN-OUT RESET VOLTAGE, BORV = 0

2.80

2.75
Max.

2.70
Voltage (V)

Typical

2.65
Min.

Max: Typical + 3ı
2.60 Min: Typical - 3ı

2.55
-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (°C)

FIGURE 30-60: BROWN-OUT RESET HYSTERESIS, BORV = 0

90

80
Min.
70

60
Typical
Voltage (mV)

50

40 Max: Typical + 3ı
Typical: 25°C
30 Min: Typical - 3ı

20
Max.
10

0
-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (°C)

 2011-2013 Microchip Technology Inc. DS40001609C-page 385

PIC16(L)F1508/9
FIGURE 30-61: LOW-POWER BROWN-OUT RESET VOLTAGE, LPBOR = 0

2.50
Max.
Max: Typical + 3ı
2.40
Min: Typical - 3ı

2.30

Typical
Voltage (V)

2.20

2.10

2.00
Min.
1.90

1.80
-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (°C)

FIGURE 30-62: LOW-POWER BROWN-OUT RESET HYSTERESIS, LPBOR = 0

45

40 Max: Typical + 3ı Max.

Typical: 25°C
35 Min: Typical - 3ı
Typical
30
Voltage (mV)

25
Min.
20

15

10

0
-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (°C)

DS40001609C-page 386  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
FIGURE 30-63: WDT TIME-OUT PERIOD

24

22 Max.

20
Time (ms)

18 Typical

16
Min.
14

Max: Typical + 3ı (-40°C to +125°C)

12 Typical: statistical mean @ 25°C
Min: Typical - 3ı (-40°C to +125°C)
10
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

FIGURE 30-64: PWRT PERIOD

100

Max: Typical + 3ı (-40°C to +125°C)

Typical: statistical mean @ 25°C
90
Min: Typical - 3ı (-40°C to +125°C)
Max.

80
Time (ms)

70 Typical

60
Min.

50

40
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

 2011-2013 Microchip Technology Inc. DS40001609C-page 387

PIC16(L)F1508/9
FIGURE 30-65: FVR STABILIZATION PERIOD

60

Max: Typical + 3ı
50 Typical: statistical mean @ 25°C
Max.

40
Typical
Time (us)

30

20
Note:
The FVR Stabilization Period applies when:
1) coming out of RESET or exiting Sleep mode for PIC12/16LFxxxx devices.
10 2) when exiting sleep mode with VREGPM = 1 for PIC12/16Fxxxx devices
In all other cases, the FVR is stable when released from RESET.

0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)

DS40001609C-page 388  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
FIGURE 30-66: COMPARATOR HYSTERESIS, NORMAL-POWER MODE (CxSP = 1, CxHYS = 1)

40

35
Max.
30
Hysteresis (mV)

25
Typical
20

15
Min.
10 Max: Typical + 3ı
Typical: 25°C
5 Min: Typical - 3ı

0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

FIGURE 30-67: COMPARATOR HYSTERESIS, LOW-POWER MODE (CxSP = 0, CxHYS = 1)

7
Max.
6
Hysteresis (mV)

5
Typical
4

2
Max: Typical + 3ı Min.
1 Typical: 25°C
Min: Typical - 3ı
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

 2011-2013 Microchip Technology Inc. DS40001609C-page 389

PIC16(L)F1508/9
FIGURE 30-68: COMPARATOR RESPONSE TIME, NORMAL-POWER MODE (CxSP = 1)

350

300

250
Max.
Time (ns)

200
Typical
150

100

Max: Typical + 3ı
50 Typical: 25°C

0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

FIGURE 30-69: COMPARATOR RESPONSE TIME OVER TEMPERATURE,

NORMAL-POWER MODE (CxSP = 1)

400

350 Max: 125°C + 3ı

Typical: 25°C
300 Min: -45°C - 3ı

250
Time (ns)

Max. (125°C)
200

150
Typical (25°C)
100
Min. (-40°C)
50

0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

DS40001609C-page 390  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
FIGURE 30-70: COMPARATOR INPUT OFFSET AT 25°C, NORMAL-POWER MODE (CxSP = 1),
PIC16F1508/9 ONLY

50

40

30
Max.
20
Offset Voltage (mV)

10
Typical
0
Min.
-10

-20

-30 Max: Typical + 3ı

Typical: 25°C
-40 Min: Typical - 3ı

-50
0.0 1.0 2.0 3.0 4.0 5.0
Common Mode Voltage (V)

 2011-2013 Microchip Technology Inc. DS40001609C-page 391

PIC16(L)F1508/9
FIGURE 30-71: LFINTOSC FREQUENCY OVER VDD AND TEMPERATURE, PIC16LF1508/9 ONLY

36

34
Max.
32

30
Typical
Frequency (kHz)

28

26 Min.

24
Max: Typical + 3ı (-40°C to +125°C)
22 Typical: statistical mean @ 25°C
Min: Typical - 3ı (-40°C to +125°C)

20
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)

FIGURE 30-72: LFINTOSC FREQUENCY OVER VDD AND TEMPERATURE, PIC16F1508/9 ONLY

36

34
Max.
32

30
Frequency (kHz)

Typical
28

26 Min.

24
Max: Typical + 3ı (-40°C to +125°C)
22 Typical: statistical mean @ 25°C
Min: Typical - 3ı (-40°C to +125°C)

20
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

DS40001609C-page 392  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
FIGURE 30-73: HFINTOSC ACCURACY OVER TEMPERATURE, VDD = 1.8V,
PIC16LF1508/9 ONLY

8%

6% Max: Typical + 3ı
Typical: statistical mean Max.
4% Min: Typical - 3ı

2%
Accuracy (%)

0% Typical
-2%

-4%

-6% Min.

-8%

-10%
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)

FIGURE 30-74: HFINTOSC ACCURACY OVER TEMPERATURE, 2.3V  VDD 5.5V

8%

6% Max: Typical + 3ı
Typical: statistical mean
4% Min: Typical - 3ı Max.
Accuracy (%)

2%
Typical
0%

-2% Min.

-4%

-6%

-8%

-10%
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)

 2011-2013 Microchip Technology Inc. DS40001609C-page 393

PIC16(L)F1508/9
FIGURE 30-75: SLEEP MODE, WAKE PERIOD WITH HFINTOSC SOURCE, PIC16LF1508/9 ONLY

5.0

4.5
Max.
4.0

3.5

3.0 Typical
Time (us)

2.5

2.0

1.5
Max: 85°C + 3ı
1.0 Typical: 25°C
0.5

0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)

DS40001609C-page 394  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
FIGURE 30-76: LOW-POWER SLEEP MODE, WAKE PERIOD WITH HFINTOSC SOURCE,
VREGPM = 1, PIC16F1508/9 ONLY

35
Max.
30

Typical
25
Time (us)

20

15

10

5 Max: 85°C + 3ı
Typical: 25°C

0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

FIGURE 30-77: SLEEP MODE, WAKE PERIOD WITH HFINTOSC SOURCE, VREGPM = 0,
PIC16F1508/9 ONLY

12

Max.
10

8
Time (us)

Typical
6

2 Max: 85°C + 3ı
Typical: 25°C

0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

 2011-2013 Microchip Technology Inc. DS40001609C-page 395

PIC16(L)F1508/9
NOTES:

DS40001609C-page 396  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
31.0 DEVELOPMENT SUPPORT 31.1 MPLAB X Integrated Development
Environment Software
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user
of software and hardware development tools: interface for Microchip and third-party software, and
• Integrated Development Environment hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
- MPLAB® X IDE Software
MPLAB X IDE is an entirely new IDE with a host of free
• Compilers/Assemblers/Linkers software components and plug-ins for high-
- MPLAB XC Compiler performance application development and debugging.
- MPASMTM Assembler Moving between tools and upgrading from software
- MPLINKTM Object Linker/ simulators to hardware debugging and programming
MPLIBTM Object Librarian tools is simple with the seamless user interface.
- MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs,
Various Device Families a configurable watch window and a feature-rich editor
• Simulators that includes code completion and context menus,
- MPLAB X SIM Software Simulator MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
• Emulators
multiple projects with simultaneous debugging, MPLAB
- MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced
• In-Circuit Debuggers/Programmers users.
- MPLAB ICD 3 Feature-Rich Editor:
- PICkit™ 3
• Color syntax highlighting
• Device Programmers
• Smart code completion makes suggestions and
- MPLAB PM3 Device Programmer provides hints as you type
• Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined
Evaluation Kits and Starter Kits rules
• Third-party development tools • Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
• Multiple projects
• Multiple tools
• Multiple configurations
• Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker

 2011-2013 Microchip Technology Inc. DS40001609C-page 397

PIC16(L)F1508/9
31.2 MPLAB XC Compilers 31.4 MPLINK Object Linker/
The MPLAB XC Compilers are complete ANSI C
MPLIB Object Librarian
compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable
and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link
integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using
ease of use. MPLAB XC Compilers run on Windows, directives from a linker script.
Linux or MAC OS X.
The MPLIB Object Librarian manages the creation and
For easy source level debugging, the compilers provide modification of library files of precompiled code. When
debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only
IDE. the modules that contain that routine will be linked in
The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be
devices and commands, with no time or memory used efficiently in many different applications.
restrictions, and offer sufficient code optimization for The object linker/library features include:
most applications.
• Efficient linking of single libraries instead of many
MPLAB XC Compilers include an assembler, linker and smaller files
utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping
files that can then be archived or linked with other relo- related modules together
catable object files and archives to create an execut-
• Flexible creation of libraries with easy module
able file. MPLAB XC Compiler uses the assembler to
listing, replacement, deletion and extraction
produce its object file. Notable features of the assem-
bler include:
31.5 MPLAB Assembler, Linker and
• Support for the entire device instruction set
Librarian for Various Device
• Support for fixed-point and floating-point data
Families
• Command-line interface
• Rich directive set MPLAB Assembler produces relocatable machine
• Flexible macro language code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
• MPLAB X IDE compatibility
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
31.3 MPASM Assembler then be archived or linked with other relocatable object
The MPASM Assembler is a full-featured, universal files and archives to create an executable file. Notable
macro assembler for PIC10/12/16/18 MCUs. features of the assembler include:

The MPASM Assembler generates relocatable object • Support for the entire device instruction set
files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data
files, MAP files to detail memory usage and symbol • Command-line interface
reference, absolute LST files that contain source lines • Rich directive set
and generated machine code, and COFF files for • Flexible macro language
debugging.
• MPLAB X IDE compatibility
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process

DS40001609C-page 398  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
31.6 MPLAB X SIM Software Simulator 31.8 MPLAB ICD 3 In-Circuit Debugger
The MPLAB X SIM Software Simulator allows code
System
development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is
ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware
level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and
examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash
a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful,
logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB
buffer and logic analyzer display extend the power of IDE.
the simulator to record and track program execution,
The MPLAB ICD 3 In-Circuit Debugger probe is
actions on I/O, most peripherals and internal registers.
connected to the design engineer’s PC using a high-
The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target
symbolic debugging using the MPLAB XC Compilers, with a connector compatible with the MPLAB ICD 2 or
and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers.
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software 31.9 PICkit 3 In-Circuit Debugger/
development tool.
Programmer
31.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program-
Emulator System ming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is
Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full-
Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the tar-
programs all 8, 16 and 32-bit MCU, and DSC devices get via a Microchip debug (RJ-11) connector (compati-
with the easy-to-use, powerful graphical user interface of ble with MPLAB ICD 3 and MPLAB REAL ICE). The
the MPLAB X IDE. connector uses two device I/O pins and the Reset line
The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial
PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™).
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11) 31.10 MPLAB PM3 Device Programmer
or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection The MPLAB PM3 Device Programmer is a universal,
(CAT5). CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display
downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod-
significant advantages over competitive emulators ular, detachable socket assembly to support various
including full-speed emulation, run-time variable package types. The ICSP cable assembly is included
watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB
probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program
three meters) interconnection cables. PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.

 2011-2013 Microchip Technology Inc. DS40001609C-page 399

PIC16(L)F1508/9
31.11 Demonstration/Development 31.12 Third-Party Development Tools
Boards, Evaluation Kits, and Microchip also offers a great collection of tools from
Starter Kits third-party vendors. These tools are carefully selected
A wide variety of demonstration, development and to offer good value and unique functionality.
evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers
DSCs allows quick application development on fully from companies, such as SoftLog and CCS
functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel
areas for adding custom circuitry and provide applica- and Trace Systems
tion firmware and source code for examination and • Protocol Analyzers from companies, such as
modification. Saleae and Total Phase
The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as
temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex
interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies,
EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstra-
tion software for analog filter design, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.

DS40001609C-page 400  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
32.0 PACKAGING INFORMATION
32.1 Package Marking Information

20-Lead PDIP (300 mil) Example

XXXXXXXXXXXXXXXXX PIC16F1508
XXXXXXXXXXXXXXXXX -E/P e3
YYWWNNN 1120123

20-Lead SOIC (7.50 mm) Example

PIC16F1508
-E/SO e3

1120123

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

* Standard PICmicro® device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.

 2011-2013 Microchip Technology Inc. DS40001609C-page 401

PIC16(L)F1508/9
32.2 Package Marking Information

20-Lead SSOP (5.30 mm) Example

PIC16F1508
-E/SS e3
1120123

20-Lead QFN (4x4x0.9 mm) Example

PIC16
F1508
PIN 1 PIN 1

E/ML e3
120123

DS40001609C-page 402  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
32.3 Package Details
The following sections give the technical details of the packages.

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 2011-2013 Microchip Technology Inc. DS40001609C-page 403

PIC16(L)F1508/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS40001609C-page 404  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2011-2013 Microchip Technology Inc. DS40001609C-page 405

PIC16(L)F1508/9

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DS40001609C-page 406  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2011-2013 Microchip Technology Inc. DS40001609C-page 407

PIC16(L)F1508/9

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DS40001609C-page 408  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9

1RWH 6)*$)%) 7 & -$+ $$)" 7 ( ) )& )
))588---**8 7 

 2011-2013 Microchip Technology Inc. DS40001609C-page 409

PIC16(L)F1508/9
NOTES:

DS40001609C-page 410  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
APPENDIX A: DATA SHEET
REVISION HISTORY

Revision A (10/2011)
Original release.

Revision B (6/2013)
Updated Electrical Specifications and added
Characterization Data.

Revision C (8/2013)
Updated Electrical Specifications and added
Characterization Data.

 2011-2013 Microchip Technology Inc. DS40001609C-page 411

PIC16(L)F1508/9
NOTES:

DS40001609C-page 412  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
THE MICROCHIP WEB SITE CUSTOMER SUPPORT
Microchip provides online support via our WWW site at Users of Microchip products can receive assistance
www.microchip.com. This web site is used as a means through several channels:
to make files and information easily available to • Distributor or Representative
customers. Accessible by using your favorite Internet
• Local Sales Office
browser, the web site contains the following
information: • Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design Customers should contact their distributor,
resources, user’s guides and hardware support representative or Field Application Engineer (FAE) for
documents, latest software releases and archived support. Local sales offices are also available to help
software customers. A listing of sales offices and locations is
• General Technical Support – Frequently Asked included in the back of this document.
Questions (FAQ), technical support requests, Technical support is available through the web site
online discussion groups, Microchip consultant at: http://microchip.com/support
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.

 2011-2013 Microchip Technology Inc. DS40001609C-page 413

PIC16(L)F1508/9
NOTES:

DS40001609C-page 414  2011-2013 Microchip Technology Inc.

 PIC16(L)F1508/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. [X](1) - X /XX XXX
Examples:
Device Tape and Reel Temperature Package Pattern a) PIC16LF1509T - I/SO
Option Range Tape and Reel,
Industrial temperature,
SOIC package
b) PIC16F1508 - I/P
Device: PIC16LF1509, PIC16F1509, Industrial temperature
PIC16LF1508, PIC16F1508 PDIP package
c) PIC16F1509 - E/ML 298
Extended temperature,
Tape and Reel Blank = Standard packaging (tube or tray) QFN package
Option: T = Tape and Reel(1) QTP pattern #298

Temperature I = -40C to +85C (Industrial)

Range: E = -40C to +125C (Extended)

Package:(2) ML = QFN
P = Plastic DIP Note 1: Tape and Reel identifier only appears in the
SO = SOIC catalog part number description. This
SS = SSOP identifier is used for ordering purposes and is
not printed on the device package. Check
with your Microchip Sales Office for package
Pattern: QTP, SQTP, Code or Special Requirements availability with the Tape and Reel option.
(blank otherwise) 2: For other small form-factor package
availability and marking information, please
visit www.microchip.com/packaging or
contact your local sales office.

 2011-2013 Microchip Technology Inc. DS40001609C-page 415

PIC16(L)F1508/9
NOTES:

DS40001609C-page 416  2011-2013 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
ensure that your application meets with your specifications.
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
Technology Incorporated in the U.S.A. and other countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions
QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology
FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of
devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries.
the buyer’s risk, and the buyer agrees to defend, indemnify and
Analog-for-the-Digital Age, Application Maestro, BodyCom,
hold harmless Microchip from any and all damages, claims,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
suits, or expenses resulting from such use. No licenses are
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
conveyed, implicitly or otherwise, under any Microchip
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
intellectual property rights.
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2011-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620773987

QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
== ISO/TS 16949 == devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

 2011-2013 Microchip Technology Inc. DS40001609C-page 417

 Worldwide Sales and Service
AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
Corporate Office Asia Pacific Office India - Bangalore Austria - Wels
2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 91-80-3090-4444 Tel: 43-7242-2244-39
Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 91-80-3090-4123 Fax: 43-7242-2244-393
Tel: 480-792-7200 Harbour City, Kowloon Denmark - Copenhagen
India - New Delhi
Fax: 480-792-7277 Hong Kong Tel: 45-4450-2828
Tel: 91-11-4160-8631
Technical Support: Tel: 852-2401-1200 Fax: 45-4485-2829
Fax: 91-11-4160-8632
http://www.microchip.com/ Fax: 852-2401-3431
India - Pune France - Paris
support
Australia - Sydney Tel: 91-20-2566-1512 Tel: 33-1-69-53-63-20
Web Address:
Tel: 61-2-9868-6733 Fax: 91-20-2566-1513 Fax: 33-1-69-30-90-79
www.microchip.com
Fax: 61-2-9868-6755 Germany - Munich
Atlanta Japan - Osaka
China - Beijing Tel: 49-89-627-144-0
Duluth, GA Tel: 81-6-6152-7160
Tel: 86-10-8569-7000 Fax: 49-89-627-144-44
Tel: 678-957-9614 Fax: 81-6-6152-9310
Fax: 86-10-8528-2104 Italy - Milan
Fax: 678-957-1455 Japan - Tokyo
China - Chengdu Tel: 39-0331-742611
Boston Tel: 81-3-6880- 3770
Tel: 86-28-8665-5511 Fax: 39-0331-466781
Westborough, MA Fax: 81-3-6880-3771
Fax: 86-28-8665-7889 Netherlands - Drunen
Tel: 774-760-0087 Korea - Daegu
Fax: 774-760-0088 China - Chongqing Tel: 82-53-744-4301 Tel: 31-416-690399
Tel: 86-23-8980-9588 Fax: 82-53-744-4302 Fax: 31-416-690340
Chicago
Itasca, IL Fax: 86-23-8980-9500 Spain - Madrid
Korea - Seoul
Tel: 630-285-0071 China - Hangzhou Tel: 34-91-708-08-90
Tel: 82-2-554-7200
Fax: 630-285-0075 Tel: 86-571-2819-3187 Fax: 82-2-558-5932 or Fax: 34-91-708-08-91
Cleveland Fax: 86-571-2819-3189 82-2-558-5934 UK - Wokingham
Independence, OH China - Hong Kong SAR Tel: 44-118-921-5869
Malaysia - Kuala Lumpur
Tel: 216-447-0464 Tel: 852-2943-5100 Fax: 44-118-921-5820
Tel: 60-3-6201-9857
Fax: 216-447-0643 Fax: 852-2401-3431 Fax: 60-3-6201-9859
Dallas China - Nanjing Malaysia - Penang
Addison, TX Tel: 86-25-8473-2460 Tel: 60-4-227-8870
Tel: 972-818-7423 Fax: 86-25-8473-2470 Fax: 60-4-227-4068
Fax: 972-818-2924
China - Qingdao Philippines - Manila
Detroit Tel: 86-532-8502-7355 Tel: 63-2-634-9065
Farmington Hills, MI
Fax: 86-532-8502-7205 Fax: 63-2-634-9069
Tel: 248-538-2250
Fax: 248-538-2260 China - Shanghai Singapore
Tel: 86-21-5407-5533 Tel: 65-6334-8870
Indianapolis Fax: 86-21-5407-5066 Fax: 65-6334-8850
Noblesville, IN
Tel: 317-773-8323 China - Shenyang Taiwan - Hsin Chu
Fax: 317-773-5453 Tel: 86-24-2334-2829 Tel: 886-3-5778-366
Fax: 86-24-2334-2393 Fax: 886-3-5770-955
Los Angeles
Mission Viejo, CA China - Shenzhen Taiwan - Kaohsiung
Tel: 949-462-9523 Tel: 86-755-8864-2200 Tel: 886-7-213-7828
Fax: 949-462-9608 Fax: 86-755-8203-1760 Fax: 886-7-330-9305
Santa Clara China - Wuhan Taiwan - Taipei
Santa Clara, CA Tel: 86-27-5980-5300 Tel: 886-2-2508-8600
Tel: 408-961-6444 Fax: 86-27-5980-5118 Fax: 886-2-2508-0102
Fax: 408-961-6445 China - Xian Thailand - Bangkok
Toronto Tel: 86-29-8833-7252 Tel: 66-2-694-1351
Mississauga, Ontario, Fax: 86-29-8833-7256 Fax: 66-2-694-1350
Canada China - Xiamen
Tel: 905-673-0699 Tel: 86-592-2388138
Fax: 905-673-6509 Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
11/29/12
Fax: 86-756-3210049

DS40001609C-page 418  2011-2013 Microchip Technology Inc.