This document summarizes the structure and characteristics of metal-oxide-semiconductor (MOS) diodes. It describes the ideal MOS structure consisting of a metal electrode, silicon dioxide insulator, and silicon semiconductor layers. In an ideal MOS, three conditions exist under bias: accumulation, depletion, and inversion. The document then discusses real MOS diodes, noting differences from the ideal case due to the work function difference and presence of interface traps and oxide charges, including fixed oxide charge, oxide-trapped charge, and mobile ionic charge. These non-idealities affect the capacitance-voltage characteristics of the MOS diode.
This document summarizes the structure and characteristics of metal-oxide-semiconductor (MOS) diodes. It describes the ideal MOS structure consisting of a metal electrode, silicon dioxide insulator, and silicon semiconductor layers. In an ideal MOS, three conditions exist under bias: accumulation, depletion, and inversion. The document then discusses real MOS diodes, noting differences from the ideal case due to the work function difference and presence of interface traps and oxide charges, including fixed oxide charge, oxide-trapped charge, and mobile ionic charge. These non-idealities affect the capacitance-voltage characteristics of the MOS diode.
This document summarizes the structure and characteristics of metal-oxide-semiconductor (MOS) diodes. It describes the ideal MOS structure consisting of a metal electrode, silicon dioxide insulator, and silicon semiconductor layers. In an ideal MOS, three conditions exist under bias: accumulation, depletion, and inversion. The document then discusses real MOS diodes, noting differences from the ideal case due to the work function difference and presence of interface traps and oxide charges, including fixed oxide charge, oxide-trapped charge, and mobile ionic charge. These non-idealities affect the capacitance-voltage characteristics of the MOS diode.
This document summarizes the structure and characteristics of metal-oxide-semiconductor (MOS) diodes. It describes the ideal MOS structure consisting of a metal electrode, silicon dioxide insulator, and silicon semiconductor layers. In an ideal MOS, three conditions exist under bias: accumulation, depletion, and inversion. The document then discusses real MOS diodes, noting differences from the ideal case due to the work function difference and presence of interface traps and oxide charges, including fixed oxide charge, oxide-trapped charge, and mobile ionic charge. These non-idealities affect the capacitance-voltage characteristics of the MOS diode.
layers. The top layer is a conductive metal electrode, the middle layer is an insulator of glass or silicon dioxide, and the bottom layer is another conductive electrode made out of crystal silicon. This layer is a semiconductor whose conductivity changes with either doping or temperature. Structure | Cross-section of an MOS diode | d is the thickness of the oxide and V is the applied voltage on the metal field plate | V>(<)0 metal plate is positively (negatively) biased with respect to the ohmic contact Ideal MOS | A. at zero applied bias, the energy difference between the metal work function qФm and the semiconductor work function qФs is zero (in other words, the energy band is flat called flat band condition )
| B. the only charges that exit in the diode under any
biasing condition are those in the semiconductor and those with equal but opposite sign on the metal surface adjacent to the oxide | C. there is no carrier transport through the oxide under dc biasing conditions, or the resistivity of the oxide is infinite Ideal MOS Ideal MOS
When an ideal MOS diode is biased with positive
or negative voltages, three case may exist at the semiconductor surface A. accumulation
B. depletion
C. inversion Accumulation
| V<0 →excess ”+” carrier will be induced at the SiO2-Si interface
| Bands near the semiconductor surface are bent upward
| Charge distribution Qs=lQml (Qs + charge per unit area in the
semiconductor) depletion
| V>0 | Bands near the semiconductor surface are bent downward and the major carriers (holes) are depleted | Charge distribution Qsc=-qNAW (space charge per unit area) W (width of depletion region) inversion
| Larger +V is applied →Ei cross over the Fermi level
| Electrons is greater than holes
| Weak and strong inversion (electron concentration in interface equal to the substrate doping level) | After this point additional e in the n-type inversion layer(1~10nm) The surface depletion region The surface depletion region
| We can use qФ to replace E and get
this eq
| At the surface The surface depletion region Prove the depletion region width By using the one dimensional Poisson’s equation
ρs(x) is the charge density per unit volume at position x
and εs is the dielectric permittivity when the semiconductor is depleted to a width of W and the charge within the semiconductor is given by ρs=-qNA integration of Poisson’s equation we get the electrostatic potential distribution as a function of distance x in the surface depletion region Prove the depletion region width When strong inversion occurs ns=NA ns=nieq(Фs-ФB)/kT NA =nieqФB/kT
From we can get the max width of the
surface depletion region W is
m The relationship between W and NA Ideal MOS curves Ideal MOS curves
1.C=Co
2.
3.Threshold voltage The SiO2-Si MOS diode
In real case there are some difference
between the ideal MOS a. the work function difference
b. interface traps and oxide charges
The work function difference
| Flat-band voltage (VFB=Фms)
Interface traps and oxide charges | Interface-trapped charge | Fixed-oxide charge | Oxide-trapped charge | Mobile ionic charge Interface-trapped charge Qit | It is due to the SiO2-Si interface properties and dependent on the chemical composition of this interface | The interface trap density is orientation dependent for example in <100>orientation the interface trap density is about an order of magnitude smaller than that in <111>orientation | 450℃ hydrogen annealing the value of Interface-trapped charges for <100>orientation silicon can be as low as 1010cm-2 Fixed-oxide charge Qf | the fixed-oxide charge is located within approximately 3 nm of the SiO2-Si interface .this charge is fixed and cannot be charged or discharged over a wide variation of surface potential. Generally, Qf is positive and depends on oxidation and annealing conditions and on silicon orientation | It has been suggested that when the oxidation is stopped, some ionic silicon is left near the interface. It may result in the positive interface charge Qf | Typical fixed-oxide charge densities for a carefully treated SiO2-Si interface system are about 1010cm-2 for a <100>surface and about 5x 1010cm-2 for a <111>surface Oxide-trapped charge Qot
Oxide-trapped charge are associated
with defect in the silicon dioxide. These charges can be created, for example, by X-ray radiation or high – energy electron bombardment the trap are distributed inside the oxide layer. Most of process-related oxide- trapped charge can be removed by low-temperature annealing Mobile ionic charge Qm
| The mobile ionic charges Qm, such as
sodium or other alkali ion are mobile within the oxide under raise- temperature (e.g.>100℃) and high- electric field operation | It may cause stability problem in device Effect of a fixed oxide charge and interface traps on the C-V characteristics of an MOS diode
