Adum1400 Adum1401 Adum1402: Quad-Channel Digital Isolators
Adum1400 Adum1401 Adum1402: Quad-Channel Digital Isolators
Adum1400 Adum1401 Adum1402: Quad-Channel Digital Isolators
VIA 3 ENCODE DECODE 14 VOA VIA 3 ENCODE DECODE 14 VOA VIA 3 ENCODE DECODE 14 VOA
VIB 4 ENCODE DECODE 13 VOB VIB 4 ENCODE DECODE 13 VOB VIB 4 ENCODE DECODE 13 VOB
VIC 5 ENCODE DECODE 12 VOC VIC 5 ENCODE DECODE 12 VOC VOC 5 DECODE ENCODE 12 VIC
VID 6 ENCODE DECODE 11 VOD VOD 6 DECODE ENCODE 11 VID VOD 6 DECODE ENCODE 11 VID
03786-002
03786-003
TABLE OF CONTENTS
Features .............................................................................................. 1 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Applications ....................................................................................... 1 Characteristics ............................................................................ 20
Rev. L | Page 2 of 31
Data Sheet ADuM1400/ADuM1401/ADuM1402
REVISION HISTORY
12/2016—Rev. K to Rev. L 6/2007—Rev. D to Rev. E
Changes to Table 1 ............................................................................ 4 Updated VDE Certification Throughout....................................... 1
Changes to Table 2 ............................................................................ 6 Changes to Features and Note 1 ...................................................... 1
Changes to Table 3 ............................................................................ 9 Changes to Figure 1, Figure 2, and Figure 3 .................................. 1
Changes to Table 4 ..........................................................................11 Changes to Regulatory Information Section ............................... 10
Changes to Table 5 ..........................................................................13 Changes to Table 7 .......................................................................... 11
Changes to Table 6 ..........................................................................15 Added Table 10 ................................................................................ 12
Changes to Table 7 ..........................................................................17 Added Insulation Lifetime Section ............................................... 20
Changes to Table 9 and Table 10 ...................................................19 Updated Outline Dimensions........................................................ 21
Changes to Ordering Guide ...........................................................30 Changes to Ordering Guide ........................................................... 21
Rev. L | Page 3 of 31
ADuM1400/ADuM1401/ADuM1402 Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V, 105°C OPERATION1
4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. These specifications do not apply to ADuM1400W,
ADuM1401W, and ADuM1402W automotive grade versions.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q) 0.50 0.53 mA
Output Supply Current per Channel, Quiescent IDDO (Q) 0.19 0.21 mA
ADuM1400 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 2.2 2.8 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 0.9 1.4 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current IDD1 (10) 8.6 10.6 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 2.6 3.5 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current IDD1 (90) 70 100 mA 45 MHz logic signal freq.
VDD2 Supply Current IDD2 (90) 18 25 mA 45 MHz logic signal freq.
ADuM1401 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.8 2.4 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 1.2 1.8 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current IDD1 (10) 7.1 9.0 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 4.1 5.0 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current IDD1 (90) 57 82 mA 45 MHz logic signal freq.
VDD2 Supply Current IDD2 (90) 31 43 mA 45 MHz logic signal freq.
ADuM1402 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 or VDD2 Supply Current IDD1 (Q), IDD2 (Q) 1.5 2.1 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 or VDD2 Supply Current IDD1 (10), IDD2 (10) 5.6 7.0 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 or VDD2 Supply Current IDD1 (90), IDD2 (90) 44 62 mA 45 MHz logic signal freq.
For All Models
Input Currents IIA, IIB, IIC, −10 +0.01 +10 µA 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
IID, IE1, IE2 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold VIH, VEH 2.0 V
Logic Low Input Threshold VIL, VEL 0.8 V
Logic High Output Voltages VOAH, VOBH, (VDD1 or VDD2) − 0.1 5.0 V IOx = −20 µA, VIx = VIxH
VOCH, VODH (VDD1 or VDD2) − 0.4 4.8 V IOx = −3.2 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL, 0.0 0.1 V IOx = 20 µA, VIx = VIxL
VOCL, VODL 0.04 0.1 V IOx = 400 µA, VIx = VIxL
0.2 0.4 V IOx = 3.2 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM1400ARW/ADuM1401ARW/ADuM1402ARW
Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 50 65 100 ns CL = 15 pF, CMOS signal levels
Rev. L | Page 4 of 31
Data Sheet ADuM1400/ADuM1401/ADuM1402
Parameter Symbol Min Typ Max Unit Test Conditions
Pulse Width Distortion, |tPLH − tPHL|5 PWD 40 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 11 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching7 tPSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels
ADuM1400BRW/ADuM1401BRW/ADuM1402BRW
Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 20 32 50 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 15 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional tPSKCD 3 ns CL = 15 pF, CMOS signal levels
Channels7
Channel-to-Channel Matching, Opposing- tPSKOD 6 ns CL = 15 pF, CMOS signal levels
Directional Channels7
ADuM1400CRW/ADuM1401CRW/ADuM1402CRW
Minimum Pulse Width3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 18 27 32 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 10 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional tPSKCD 2 ns CL = 15 pF, CMOS signal levels
Channels7
Channel-to-Channel Matching, Opposing- tPSKOD 5 ns CL = 15 pF, CMOS signal levels
Directional Channels7
For All Models
Output Disable Propagation Delay (High/Low tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels
to High Impedance)
Output Enable Propagation Delay (High tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels
Impedance to High/Low)
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic |CMH| 25 35 kV/µs VIx = VDD1 or VDD2, VCM = 1000 V,
High Output8 transient magnitude = 800 V
Common-Mode Transient Immunity at Logic |CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V,
Low Output8 transient magnitude = 800 V
Refresh Rate fr 1.2 Mbps
Input Dynamic Supply Current per Channel9 IDDI (D) 0.19 mA/Mbps
Output Dynamic Supply Current per Channel9 IDDO (D) 0.05 mA/Mbps
1
All voltages are relative to their respective ground.
2
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. L | Page 5 of 31
ADuM1400/ADuM1401/ADuM1402 Data Sheet
ELECTRICAL CHARACTERISTICS—3 V, 105°C OPERATION1
2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V. These specifications do not apply to ADuM1400W,
ADuM1401W, and ADuM1402W automotive grade versions.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q) 0.26 0.31 mA
Output Supply Current per Channel, Quiescent IDDO (Q) 0.11 0.14 mA
ADuM1400 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.2 1.9 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 0.5 0.9 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current IDD1 (10) 4.5 6.5 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 1.4 2.0 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current IDD1 (90) 37 65 mA 45 MHz logic signal freq.
VDD2 Supply Current IDD2 (90) 11 15 mA 45 MHz logic signal freq.
ADuM1401 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.0 1.6 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 0.7 1.2 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current IDD1 (10) 3.7 5.4 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 2.2 3.0 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current IDD1 (90) 30 52 mA 45 MHz logic signal freq.
VDD2 Supply Current IDD2 (90) 18 27 mA 45 MHz logic signal freq.
ADuM1402 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 or VDD2 Supply Current IDD1 (Q), IDD2 (Q) 0.9 1.5 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 or VDD2 Supply Current IDD1 (10), IDD2 (10) 3.0 4.2 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 or VDD2 Supply Current IDD1 (90), IDD2 (90) 24 39 mA 45 MHz logic signal freq.
For All Models
Input Currents IIA, IIB, IIC, −10 +0.01 +10 µA 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
IID, IE1, IE2 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold VIH, VEH 1.6 V
Logic Low Input Threshold VIL, VEL 0.4 V
Logic High Output Voltages VOAH, VOBH, (VDD1 or VDD2) − 0.1 3.0 V IOx = −20 µA, VIx = VIxH
VOCH, VODH (VDD1 or VDD2) − 0.4 2.8 V IOx = −3.2 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL, 0.0 0.1 V IOx = 20 µA, VIx = VIxL
VOCL, VODL 0.04 0.1 V IOx = 400 µA, VIx = VIxL
0.2 0.4 V IOx = 3.2 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM1400ARW/ADuM1401ARW/ADuM1402ARW
Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 50 75 100 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 40 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 11 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching7 tPSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels
Rev. L | Page 6 of 31
Data Sheet ADuM1400/ADuM1401/ADuM1402
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM1400BRW/ADuM1401BRW/ADuM1402BRW
Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 20 38 50 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 22 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional tPSKCD 3 ns CL = 15 pF, CMOS signal levels
Channels7
Channel-to-Channel Matching, Opposing- tPSKOD 6 ns CL = 15 pF, CMOS signal levels
Directional Channels7
ADuM1400CRW/ADuM1401CRW/ADuM1402CRW
Minimum Pulse Width3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 20 34 45 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 16 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional tPSKCD 2 ns CL = 15 pF, CMOS signal levels
Channels7
Channel-to-Channel Matching, Opposing- tPSKOD 5 ns CL = 15 pF, CMOS signal levels
Directional Channels7
For All Models
Output Disable Propagation Delay (High/Low to tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels
High Impedance)
Output Enable Propagation Delay (High tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels
Impedance to High/Low)
Output Rise/Fall Time (10% to 90%) tR/tF 3 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic |CMH| 25 35 kV/µs VIx = VDD1 or VDD2, VCM = 1000 V,
High Output8 transient magnitude = 800 V
Common-Mode Transient Immunity at Logic |CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V,
Low Output8 transient magnitude = 800 V
Refresh Rate fr 1.1 Mbps
Input Dynamic Supply Current per Channel9 IDDI (D) 0.10 mA/
Mbps
Output Dynamic Supply Current per Channel9 IDDO (D) 0.03 mA/
Mbps
1
All voltages are relative to their respective ground.
2
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. L | Page 7 of 31
ADuM1400/ADuM1401/ADuM1402 Data Sheet
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V, 105°C OPERATION1
5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all
minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications
are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V or VDD1 = 5 V, VDD2 = 3.0 V. These specifications do not apply to ADuM1400W, ADuM1401W,
and ADuM1402W automotive grade versions.
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q)
5 V/3 V Operation 0.50 0.53 mA
3 V/5 V Operation 0.26 0.31 mA
Output Supply Current per Channel, Quiescent IDDO (Q)
5 V/3 V Operation 0.11 0.14 mA
3 V/5 V Operation 0.19 0.21 mA
ADuM1400 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q)
5 V/3 V Operation 2.2 2.8 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 1.2 1.9 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q)
5 V/3 V Operation 0.5 0.9 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 0.9 1.4 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current IDD1 (10)
5 V/3 V Operation 8.6 10.6 mA 5 MHz logic signal freq.
3 V/5 V Operation 4.5 6.5 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10)
5 V/3 V Operation 1.4 2.0 mA 5 MHz logic signal freq.
3 V/5 V Operation 2.6 3.5 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current IDD1 (90)
5 V/3 V Operation 70 100 mA 45 MHz logic signal freq.
3 V/5 V Operation 37 65 mA 45 MHz logic signal freq.
VDD2 Supply Current IDD2 (90)
5 V/3 V Operation 11 15 mA 45 MHz logic signal freq.
3 V/5 V Operation 18 25 mA 45 MHz logic signal freq.
ADuM1401 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q)
5 V/3 V Operation 1.8 2.4 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 1.0 1.6 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q)
5 V/3 V Operation 0.7 1.2 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 1.2 1.8 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current IDD1 (10)
5 V/3 V Operation 7.1 9.0 mA 5 MHz logic signal freq.
3 V/5 V Operation 3.7 5.4 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10)
5 V/3 V Operation 2.2 3.0 mA 5 MHz logic signal freq.
3 V/5 V Operation 4.1 5.0 mA 5 MHz logic signal freq.
Rev. L | Page 8 of 31
Data Sheet ADuM1400/ADuM1401/ADuM1402
Parameter Symbol Min Typ Max Unit Test Conditions
90 Mbps (CRW Grade Only)
VDD1 Supply Current IDD1 (90)
5 V/3 V Operation 57 82 mA 45 MHz logic signal freq.
3 V/5 V Operation 30 52 mA 45 MHz logic signal freq.
VDD2 Supply Current IDD2 (90)
5 V/3 V Operation 18 27 mA 45 MHz logic signal freq.
3 V/5 V Operation 31 43 mA 45 MHz logic signal freq.
ADuM1402 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q)
5 V/3 V Operation 1.5 2.1 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 0.9 1.5 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q)
5 V/3 V Operation 0.9 1.5 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 1.5 2.1 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current IDD1 (10)
5 V/3 V Operation 5.6 7.0 mA 5 MHz logic signal freq.
3 V/5 V Operation 3.0 4.2 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10)
5 V/3 V Operation 3.0 4.2 mA 5 MHz logic signal freq.
3 V/5 V Operation 5.6 7.0 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current IDD1 (90)
5 V/3 V Operation 44 62 mA 45 MHz logic signal freq.
3 V/5 V Operation 24 39 mA 45 MHz logic signal freq.
VDD2 Supply Current IDD2 (90)
5 V/3 V Operation 24 39 mA 45 MHz logic signal freq.
3 V/5 V Operation 44 62 mA 45 MHz logic signal freq.
For All Models
Input Currents IIA, IIB, IIC, −10 +0.01 +10 µA 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
IID, IE1, IE2 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold VIH, VEH
5 V/3 V Operation 2.0 V
3 V/5 V Operation 1.6 V
Logic Low Input Threshold VIL, VEL
5 V/3 V Operation 0.8 V
3 V/5 V Operation 0.4 V
Logic High Output Voltages VOAH, VOBH, (VDD1 or VDD2) − 0.1 (VDD1 or VDD2) V IOx = −20 µA, VIx = VIxH
VOCH, VODH (VDD1 or VDD2) − 0.4 (VDD1 or VDD2) − 0.2 V IOx = −3.2 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL, 0.0 0.1 V IOx = 20 µA, VIx = VIxL
VOCL, VODL 0.04 0.1 V IOx = 400 µA, VIx = VIxL
0.2 0.4 V IOx = 3.2 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM1400ARW/ADuM1401ARW/ADuM1402ARW
Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 50 70 100 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 40 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 11 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching7 tPSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels
ADuM1400BRW/ADuM1401BRW/ADuM1402BRW
Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 15 35 50 ns CL = 15 pF, CMOS signal levels
Rev. L | Page 9 of 31
ADuM1400/ADuM1401/ADuM1402 Data Sheet
Parameter Symbol Min Typ Max Unit Test Conditions
Pulse Width Distortion, |tPLH − tPHL|5 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 22 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional tPSKCD 3 ns CL = 15 pF, CMOS signal levels
Channels7
Channel-to-Channel Matching, Opposing- tPSKOD 6 ns CL = 15 pF, CMOS signal levels
Directional Channels7
ADuM1400CRW/ADuM1401CRW/ADuM1402CRW
Minimum Pulse Width3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 20 30 40 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 14 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional tPSKCD 2 ns CL = 15 pF, CMOS signal levels
Channels7
Channel-to-Channel Matching, Opposing- tPSKOD 5 ns CL = 15 pF, CMOS signal levels
Directional Channels7
For All Models
Output Disable Propagation Delay (High/Low tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels
to High Impedance)
Output Enable Propagation Delay (High tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels
Impedance to High/Low)
Output Rise/Fall Time (10% to 90%) tR/tF CL = 15 pF, CMOS signal levels
5 V/3 V Operation 3.0 ns
3 V/5 V Operation 2.5 ns
Common-Mode Transient Immunity at Logic |CMH| 25 35 kV/µs VIx = VDD1 or VDD2, VCM = 1000 V,
High Output8 transient magnitude = 800 V
Common-Mode Transient Immunity at Logic |CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V,
Low Output8 transient magnitude = 800 V
Refresh Rate fr
5 V/3 V Operation 1.2 Mbps
3 V/5 V Operation 1.1 Mbps
Input Dynamic Supply Current per Channel9 IDDI (D)
5 V/3 V Operation 0.19 mA/Mbps
3 V/5 V Operation 0.10 mA/Mbps
Output Dynamic Supply Current per Channel9 IDDO (D)
5 V/3 V Operation 0.03 mA/Mbps
3 V/5 V Operation 0.05 mA/Mbps
1
All voltages are relative to their respective ground.
2
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. L | Page 10 of 31
Data Sheet ADuM1400/ADuM1401/ADuM1402
ELECTRICAL CHARACTERISTICS—5 V, 125°C OPERATION1
4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. These specifications apply to ADuM1400W,
ADuM1401W, and ADuM1402W automotive grade versions.
Table 4.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q) 0.50 0.53 mA
Output Supply Current per Channel, Quiescent IDDO (Q) 0.19 0.21 mA
ADuM1400W, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 2.2 2.8 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 0.9 1.4 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current IDD1 (10) 8.6 10.6 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 2.6 3.5 mA 5 MHz logic signal freq.
ADuM1401W, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.8 2.4 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 1.2 1.8 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current IDD1 (10) 7.1 9.0 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 4.1 5.0 mA 5 MHz logic signal freq.
ADuM1402W, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 or VDD2 Supply Current IDD1 (Q), IDD2 (Q) 1.5 2.1 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 or VDD2 Supply Current IDD1 (10), IDD2 (10) 5.6 7.0 mA 5 MHz logic signal freq.
For All Models
Input Currents IIA, IIB, IIC, −10 +0.01 +10 µA 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
IID, IE1, IE2 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold VIH, VEH 2.0 V
Logic Low Input Threshold VIL, VEL 0.8 V
Logic High Output Voltages VOAH, VOBH, (VDD1 or VDD2) − 0.1 5.0 V IOx = −20 µA, VIx = VIxH
VOCH, VODH (VDD1 or VDD2) − 0.4 4.8 V IOx = −3.2 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL, 0.0 0.1 V IOx = 20 µA, VIx = VIxL
VOCL, VODL 0.04 0.1 V IOx = 400 µA, VIx = VIxL
0.2 0.4 V IOx = 3.2 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM1400WSRWZ/ADuM1401WSRWZ/
ADuM1402WSRWZ
Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 50 65 100 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 40 ns CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching7 tPSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels
Rev. L | Page 11 of 31
ADuM1400/ADuM1401/ADuM1402 Data Sheet
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM1400WTRWZ/ADuM1401WTRWZ/
ADuM1402WTRWZ
Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 18 27 34 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 15 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional tPSKCD 3 ns CL = 15 pF, CMOS signal levels
Channels7
Channel-to-Channel Matching, Opposing- tPSKOD 6 ns CL = 15 pF, CMOS signal levels
Directional Channels7
For All Models
Output Disable Propagation Delay (High/Low tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels
to High Impedance)
Output Enable Propagation Delay (High tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels
Impedance to High/Low)
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic |CMH| 25 35 kV/µs VIx = VDD1/VDD2, VCM = 1000 V,
High Output8 transient magnitude = 800 V
Common-Mode Transient Immunity at Logic |CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V,
Low Output8 transient magnitude = 800 V
Refresh Rate fr 1.2 Mbps
Input Dynamic Supply Current per Channel9 IDDI (D) 0.19 mA/Mbps
Output Dynamic Supply Current per Channel9 IDDO (D) 0.05 mA/Mbps
1
All voltages are relative to their respective ground.
2
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400W/ADuM1401W/ADuM1402W channel configurations.
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. L | Page 12 of 31
Data Sheet ADuM1400/ADuM1401/ADuM1402
ELECTRICAL CHARACTERISTICS—3 V, 125°C OPERATION1
3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V. These specifications apply to ADuM1400W,
ADuM1401W, and ADuM1402W automotive grade versions.
Table 5.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, IDDI (Q) 0.26 0.31 mA
Quiescent
Output Supply Current per Channel, IDDO (Q) 0.11 0.14 mA
Quiescent
ADuM1400W, Total Supply Current, Four
Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.2 1.9 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 0.5 0.9 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current IDD1 (10) 4.5 6.5 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 1.4 2.0 mA 5 MHz logic signal freq.
ADuM1401W, Total Supply Current, Four
Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.0 1.6 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 0.7 1.2 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current IDD1 (10) 3.7 5.4 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 2.2 3.0 mA 5 MHz logic signal freq.
ADuM1402W, Total Supply Current, Four
Channels2
DC to 2 Mbps
VDD1 or VDD2 Supply Current IDD1 (Q), IDD2 (Q) 0.9 1.5 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 or VDD2 Supply Current IDD1 (10), IDD2 (10) 3.0 4.2 mA 5 MHz logic signal freq.
For All Models
Input Currents IIA, IIB, IIC, −10 +0.01 +10 µA 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
IID, IE1, IE2 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold VIH, VEH 1.6 V
Logic Low Input Threshold VIL, VEL 0.4 V
Logic High Output Voltages VOAH, VOBH, (VDD1 or VDD2) − 0.1 3.0 V IOx = −20 µA, VIx = VIxH
VOCH, VODH (VDD1 or VDD2) − 0.4 2.8 V IOx = −3.2 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL, 0.0 0.1 V IOx = 20 µA, VIx = VIxL
VOCL, VODL 0.04 0.1 V IOx = 400 µA, VIx = VIxL
0.2 0.4 V IOx = 3.2 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM1400WSRWZ/ADuM1401WSRWZ/
ADuM1402WSRWZ
Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 50 75 100 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 40 ns CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching7 tPSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels
Rev. L | Page 13 of 31
ADuM1400/ADuM1401/ADuM1402 Data Sheet
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM1400WTRWZ/ADuM1401WTRWZ/
ADuM1402WTRWZ
Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 20 34 45 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 22 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, tPSKCD 3 ns CL = 15 pF, CMOS signal levels
Codirectional Channels7
Channel-to-Channel Matching, tPSKOD 6 ns CL = 15 pF, CMOS signal levels
Opposing-Directional Channels7
For All Models
Output Disable Propagation Delay tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels
(High/Low to High Impedance)
Output Enable Propagation Delay (High tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels
Impedance to High/Low)
Output Rise/Fall Time (10% to 90%) tR/tF 3 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at |CMH| 25 35 kV/µs VIx = VDD1/VDD2, VCM = 1000 V,
Logic High Output8 transient magnitude = 800 V
Common-Mode Transient Immunity at |CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V,
Logic Low Output8 transient magnitude = 800 V
Refresh Rate fr 1.1 Mbps
Input Dynamic Supply Current per IDDI (D) 0.10 mA/Mbps
Channel9
Output Dynamic Supply Current per IDDO (D) 0.03 mA/Mbps
Channel9
1
All voltages are relative to their respective ground.
2
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400W/ADuM1401W/ADuM1402W channel configurations.
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. L | Page 14 of 31
Data Sheet ADuM1400/ADuM1401/ADuM1402
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V, 125°C OPERATION1
4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 5 V, VDD2 = 3.0 V. These specifications apply to ADuM1400W,
ADuM1401W, and ADuM1402W automotive grade versions.
Table 6.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q) 0.50 0.53 mA
Output Supply Current per Channel, Quiescent IDDO (Q) 0.11 0.14 mA
ADuM1400W, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 2.2 2.8 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 0.5 0.9 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current IDD1 (10) 8.6 10.6 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 1.4 2.0 mA 5 MHz logic signal freq.
ADuM1401W, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.8 2.4 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 0.7 1.2 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current IDD1 (10) 7.1 9.0 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 2.2 3.0 mA 5 MHz logic signal freq.
ADuM1402W, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.5 2.1 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 0.9 1.5 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current IDD1 (10) 5.6 7.0 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 3.0 4.2 mA 5 MHz logic signal freq.
For All Models
Input Currents IIA, IIB, IIC, −10 +0.01 +10 µA 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1
IID, IE1, IE2 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1
or VDD2
Logic High Input Threshold VIH, VEH
5 V/3 V Operation 2.0 V
3 V/5 V Operation 1.6 V
Logic Low Input Threshold VIL, VEL
5 V/3 V Operation 0.8 V
3 V/5 V Operation 0.4 V
Logic High Output Voltages VOAH, VOBH, (VDD1 or VDD2) − 0.1 VDD1 or VDD2 V IOx = −20 µA, VIx = VIxH
VOCH, VODH (VDD1 or VDD2) − 0.4 VDD1, VDD2 − 0.2 V IOx = −3.2 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL, 0.0 0.1 V IOx = 20 µA, VIx = VIxL
VOCL, VODL 0.04 0.1 V IOx = 400 µA, VIx = VIxL
0.2 0.4 V IOx = 3.2 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM1400WSRWZ/ADuM1401WSRWZ/
ADuM1402WSRWZ
Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 50 70 100 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 40 ns CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching7 tPSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels
Rev. L | Page 15 of 31
ADuM1400/ADuM1401/ADuM1402 Data Sheet
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM1400WTRWZ/ADuM1401WTRWZ/
ADuM1402WTRWZ
Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 20 30 40 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 22 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional tPSKCD 3 ns CL = 15 pF, CMOS signal levels
Channels7
Channel-to-Channel Matching, Opposing- tPSKOD 6 ns CL = 15 pF, CMOS signal levels
Directional Channels7
For All Models
Output Disable Propagation Delay (High/Low tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels
to High Impedance)
Output Enable Propagation Delay (High tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels
Impedance to High/Low)
Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic |CMH| 25 35 kV/µs VIx = VDD1/VDD2, VCM = 1000 V,
High Output8 transient magnitude = 800 V
Common-Mode Transient Immunity at Logic |CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V,
Low Output8 transient magnitude = 800 V
Refresh Rate fr 1.2 Mbps
Input Dynamic Supply Current per Channel9 IDDI (D) 0.19 mA/Mbps
Output Dynamic Supply Current per Channel9 IDDO (D) 0.03 mA/Mbps
1
All voltages are relative to their respective ground.
2
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400W/ADuM1401W/ADuM1402W channel configurations.
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. L | Page 16 of 31
Data Sheet ADuM1400/ADuM1401/ADuM1402
ELECTRICAL CHARACTERISTICS—MIXED 3 V/5 V, 125°C OPERATION1
3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V. These specifications apply to ADuM1400W,
ADuM1401W, and ADuM1402W automotive grade versions.
Table 7.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q) 0.26 0.31 mA
Output Supply Current per Channel, Quiescent IDDO (Q) 0.19 0.21 mA
ADuM1400W, Total Supply Current, Four
Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.2 1.9 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 0.9 1.4 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current IDD1 (10) 4.5 6.5 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 2.6 3.5 mA 5 MHz logic signal freq.
ADuM1401W, Total Supply Current, Four
Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.0 1.6 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 1.2 1.8 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current IDD1 (10) 3.7 5.4 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 4.1 5.0 mA 5 MHz logic signal freq.
ADuM1402W, Total Supply Current, Four
Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 0.9 1.5 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 1.5 2.1 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current IDD1 (10) 3.0 4.2 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 5.6 7.0 mA 5 MHz logic signal freq.
For All Models
Input Currents IIA, IIB, IIC, −10 +0.01 +10 µA 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or
IID, IE1, IE2 VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold VIH, VEH 1.6 V
Logic Low Input Threshold VIL, VEL 0.4 V
Logic High Output Voltages VOAH, VOBH, (VDD1 or VDD2) − 0.1 VDD1, VDD2 V IOx = −20 µA, VIx = VIxH
VOCH, VODH (VDD1 or VDD2) − 0.4 VDD1, VDD2 − 0.2 V IOx = −3.2 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL, 0.0 0.1 V IOx = 20 µA, VIx = VIxL
VOCL, VODL 0.04 0.1 V IOx = 400 µA, VIx = VIxL
0.2 0.4 V IOx = 3.2 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM1400WSRWZ/ADuM1401WSRWZ/
ADuM1402WSRWZ
Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 50 70 100 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 40 ns CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching7 tPSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels
Rev. L | Page 17 of 31
ADuM1400/ADuM1401/ADuM1402 Data Sheet
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM1400WTRWZ/ADuM1401WTRWZ/
ADuM1402WTRWZ
Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 20 30 40 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 22 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, tPSKCD 3 ns CL = 15 pF, CMOS signal levels
Codirectional Channels7
Channel-to-Channel Matching, Opposing- tPSKOD 6 ns CL = 15 pF, CMOS signal levels
Directional Channels7
For All Models
Output Disable Propagation Delay tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels
(High/Low to High Impedance)
Output Enable Propagation Delay (High tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels
Impedance to High/Low)
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at |CMH| 25 35 kV/µs VIx = VDD1/VDD2, VCM = 1000 V,
Logic High Output8 transient magnitude = 800 V
Common-Mode Transient Immunity at |CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V,
Logic Low Output8 transient magnitude = 800 V
Refresh Rate fr 1.1 Mbps
Input Dynamic Supply Current per Channel9 IDDI (D) 0.10 mA/Mbps
Output Dynamic Supply Current per Channel9 IDDO (D) 0.05 mA/Mbps
1
All voltages are relative to their respective ground.
2
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400W/ADuM1401W/ADuM1402W channel configurations.
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. L | Page 18 of 31
Data Sheet ADuM1400/ADuM1401/ADuM1402
PACKAGE CHARACTERISTICS
Table 8.
Parameter Symbol Min Typ Max Unit Test Conditions
Resistance (Input to Output)1 RI-O 1012 Ω
Capacitance (Input to Output)1 CI-O 2.2 pF f = 1 MHz
Input Capacitance2 CI 4.0 pF
IC Junction to Case Thermal Resistance, Side 1 θJCI 33 °C/W Thermocouple located at
IC Junction to Case Thermal Resistance, Side 2 θJCO 28 °C/W center of package underside
1
Device is considered a 2-terminal device; Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together and Pin 9, Pin 10, Pin 11, Pin 12, Pin 13, Pin 14,
Pin 15, and Pin 16 are shorted together.
2
Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM1400/ADuM1401/ADuM1402 are approved by the organizations listed in Table 9. Refer to Table 14 and the Insulation Lifetime
section for details regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.
Table 9.
UL CSA VDE CQC TÜV
Recognized Under Approved under Certified according to Approved under Approved according to
UL 1577 Component CSA Component DIN V VDE V 0884-10 CQC11-471543-2012 IEC 61010-1:2001 (2nd Edition),
Recognition Acceptance Notice 5A (VDE V 0884-10):2006-122 EN 61010-1:2001 (2nd Edition),
Program1 UL 61010-1:2004, and
CSA C22.2.61010.1:2005
Single Protection, Basic insulation per Reinforced insulation, Basic Insulation per Reinforced insulation, 400 V rms
2500 V rms Isolation CSA 60950-1-03 and 560 V peak GB4943.1-2011, 415 V rms maximum working voltage
Voltage IEC 60950-1, 780 V rms (588 V peak) maximum
(1103 V peak) maximum working voltage, tropical
working voltage climate, altitude ≤ 5000 m
Reinforced insulation
per CSA 60950-1-03 and
IEC 60950-1, 390 V rms
(551 V peak) maximum
working voltage
File E214100 File 205078 File 2471900-4880-0001 File CQC14001114900 Certificate U8V 05 06 56232 002
1
In accordance with UL 1577, each ADuM1400/ADuM1401/ADuM1402 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage
detection limit = 5 µA).
2
In accordance with DIN V VDE V 0884-10, each ADuM1400/ADuM1401/ADuM1402 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial
discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.
Rev. L | Page 19 of 31
ADuM1400/ADuM1401/ADuM1402 Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits. The asterisk (*) marking on packages denotes DIN V VDE V 0884-10 approval.
Table 11.
Description Conditions Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to III
For Rated Mains Voltage ≤ 400 V rms I to II
Climatic Classification 40/105/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage VIORM 560 V peak
Input to Output Test Voltage, Method B1 VIORM × 1.875 = VPR, 100% production test, tm = 1 sec, VPR 1050 V peak
partial discharge < 5 pC
Input to Output Test Voltage, Method A VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VPR
After Environmental Tests Subgroup 1 896 V peak
After Input and/or Safety Test Subgroup 2 VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC 672 V peak
and Subgroup 3
Highest Allowable Overvoltage Transient overvoltage, tTR = 10 seconds VTR 4000 V peak
Safety Limiting Values Maximum value allowed in the event of a failure
(see Figure 4)
Case Temperature TS 150 °C
Side 1 Current IS1 265 mA
Side 2 Current IS2 335 mA
Insulation Resistance at TS VIO = 500 V RS >109 Ω
350
RECOMMENDED OPERATING CONDITIONS
300
Table 12.
SAFETY-LIMITING CURRENT (mA)
250
Parameter Rating
SIDE #2 Operating Temperature (TA)1 −40°C to +105°C
200 Operating Temperature (TA)2 −40°C to +125°C
Supply Voltages (VDD1, VDD2)1, 3 2.7 V to 5.5 V
150
SIDE #1
Supply Voltages (VDD1, VDD2)2, 3 3.0 V to 5.5 V
100 Input Signal Rise and Fall Times 1.0 ms
1
Does not apply to ADuM1400W, ADuM1401W, and ADuM1402W automotive
50
grade versions.
2
Applies to ADuM1400W, ADuM1401W, and ADuM1402W automotive grade
0 versions.
03786-004
Rev. L | Page 20 of 31
Data Sheet ADuM1400/ADuM1401/ADuM1402
Rev. L | Page 21 of 31
ADuM1400/ADuM1401/ADuM1402 Data Sheet
03786-005
NC = NO CONNECT
Rev. L | Page 22 of 31
Data Sheet ADuM1400/ADuM1401/ADuM1402
VDD1 1 16 VDD2
*GND1 2 15 GND2*
VIA 3 14 VOA
ADuM1401
VIB 4 TOP VIEW 13 VOB
VIC 5 (Not to Scale) 12 VOC
VOD 6 11 VID
VE1 7 10 VE2
*GND1 8 9 GND2*
03786-006
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING
BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED.
Rev. L | Page 23 of 31
ADuM1400/ADuM1401/ADuM1402 Data Sheet
VDD1 1 16 VDD2
*GND1 2 15 GND2*
VIA 3 14 VOA
ADuM1402
VIB 4 TOP VIEW 13 VOB
VOC 5 (Not to Scale) 12 VIC
VOD 6 11 VID
VE1 7 10 VE2
*GND1 8 9 GND2*
03786-007
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING
BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED.
Rev. L | Page 24 of 31
Data Sheet ADuM1400/ADuM1401/ADuM1402
70
15 60
CURRENT/CHANNEL (mA)
50
CURRENT (mA)
10 40
5V 5V
30
3V 3V
5 20
10
0 0
03786-008
03786-011
0 20 40 60 80 100 0 20 40 60 80 100
DATA RATE (Mbps) DATA RATE (Mbps)
Figure 8. Typical Input Supply Current per Channel vs. Data Rate Figure 11. Typical ADuM1400 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation for 5 V and 3 V Operation
6 25
5
20
CURRENT/CHANNEL (mA)
4
15
CURRENT (mA)
5V 10
2 5V
3V 3V
5
1
0 0
03786-009
03786-012
0 20 40 60 80 100 0 20 40 60 80 100
DATA RATE (Mbps) DATA RATE (Mbps)
Figure 9. Typical Output Supply Current per Channel vs. Data Rate Figure 12. Typical ADuM1400 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation (No Output Load) for 5 V and 3 V Operation
10 35
30
8
25
CURRENT/CHANNEL (mA)
6
CURRENT (mA)
20
15
4
5V 5V
10
3V
2 3V
5
0 0
03786-013
03786-010
0 20 40 60 80 100 0 20 40 60 80 100
DATA RATE (Mbps) DATA RATE (Mbps)
Figure 10. Typical Output Supply Current per Channel vs. Data Rate Figure 13. Typical ADuM1401 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation (15 pF Output Load) for 5 V and 3 V Operation
Rev. L | Page 25 of 31
ADuM1400/ADuM1401/ADuM1402 Data Sheet
40 40
35
30
3V
20
5V
15
30
3V
10
5V
5
0 25
03786-014
03786-016
0 20 40 60 80 100 –50 –25 0 25 50 75 100
DATA RATE (Mbps) TEMPERATURE (°C)
Figure 14. Typical ADuM1401 VDD2 Supply Current vs. Data Rate Figure 16. Propagation Delay vs. Temperature, C Grade
for 5 V and 3 V Operation
50
45
40
35
30
CURRENT (mA)
25
20
5V
15
3V
10
0
03786-015
0 20 40 60 80 100
DATA RATE (Mbps)
Figure 15. Typical ADuM1402 VDD1 or VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
Rev. L | Page 26 of 31
Data Sheet ADuM1400/ADuM1401/ADuM1402
APPLICATIONS INFORMATION
PC BOARD LAYOUT DC CORRECTNESS AND MAGNETIC FIELD
The ADuM1400/ADuM1401/ADuM1402 digital isolators IMMUNITY
require no external interface circuitry for the logic interfaces. Positive and negative logic transitions at the isolator input
Power supply bypassing is strongly recommended at the input cause narrow (~1 ns) pulses to be sent to the decoder via the
and output supply pins (see Figure 17). Bypass capacitors are transformer. The decoder is bistable and is, therefore, either set
most conveniently connected between Pin 1 and Pin 2 for VDD1 or reset by the pulses, indicating input logic transitions. In the
and between Pin 15 and Pin 16 for VDD2. The capacitor value absence of logic transitions at the input for more than ~1 µs, a
should be between 0.01 µF and 0.1 µF. The total lead length periodic set of refresh pulses indicative of the correct input state
between both ends of the capacitor and the input power supply are sent to ensure dc correctness at the output. If the decoder
pin should not exceed 20 mm. Bypassing between Pin 1 and Pin receives no internal pulses of more than about 5 µs, the input
8 and between Pin 9 and Pin 16 should also be considered, side is assumed to be unpowered or nonfunctional, in which
unless the ground pair on each package side is connected close case the isolator output is forced to a default state (see Table 15)
to the package. by the watchdog timer circuit.
VDD1 VDD2
GND1 GND2
The limitation on the magnetic field immunity of the ADuM1400/
VIA VOA ADuM1401/ADuM1402 is set by the condition in which induced
VIB VOB
VIC/VOC VOC/VIC
voltage in the receiving coil of the transformer is sufficiently large
VID/VOD VOD/VID enough to either falsely set or reset the decoder. The following
03786-017
NC/VE1 VE2
GND1 GND2 analysis defines the conditions under which this may occur. The
3 V operating condition of the ADuM1400/ADuM1401/
Figure 17. Recommended Printed Circuit Board Layout
ADuM1402 is examined because it represents the most susceptible
In applications involving high common-mode transients, care mode of operation.
should be taken to ensure that board coupling across the isolation
The pulses at the transformer output have an amplitude greater
barrier is minimized. Furthermore, the board layout should be
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus
designed such that any coupling that does occur equally affects
establishing a 0.5 V margin in which induced voltages can be
all pins on a given component side. Failure to ensure this could
tolerated. The voltage induced across the receiving coil is given by
cause voltage differentials between pins exceeding the Absolute
Maximum Ratings of the device, thereby leading to latch-up or V = (−dβ/dt)∑∏rn2; n = 1, 2, … , N
permanent damage. where:
See the AN-1109 Application Note for board layout guidelines. β is magnetic flux density (gauss).
N is the number of turns in the receiving coil.
PROPAGATION DELAY-RELATED PARAMETERS rn is the radius of the nth turn in the receiving coil (cm).
Propagation delay is a parameter that describes the time it takes
Given the geometry of the receiving coil in the ADuM1400/
a logic signal to propagate through a component. The propagation
ADuM1401/ADuM1402 and an imposed requirement that the
delay to a Logic 0 output may differ from the propagation delay
induced voltage be 50% at most of the 0.5 V margin at the
to a Logic 1 output.
decoder, a maximum allowable magnetic field is calculated as
INPUT (VIx) 50% shown in Figure 19.
tPLH tPHL 100
MAXIMUM ALLOWABLE MAGNETIC FLUX
03786-018
Rev. L | Page 27 of 31
ADuM1400/ADuM1401/ADuM1402 Data Sheet
For example, at a magnetic field frequency of 1 MHz, the POWER CONSUMPTION
maximum allowable magnetic field of 0.2 kgauss induces a The supply current at a given channel of the ADuM1400/
voltage of 0.25 V at the receiving coil. This is about 50% of the ADuM1401/ADuM1402 isolator is a function of the supply
sensing threshold and does not cause a faulty output transition. voltage, the data rate of the channel, and the output load of the
Similarly, if such an event occurs during a transmitted pulse channel.
(and has the worst-case polarity), it reduces the received pulse
from >1.0 V to 0.75 V—still well above the 0.5 V sensing For each input channel, the supply current is given by
threshold of the decoder. IDDI = IDDI (Q) f ≤ 0.5 fr
The preceding magnetic flux density values correspond to IDDI = IDDI (D) × (2f − fr) + IDDI (Q) f > 0.5 fr
specific current magnitudes at given distances from the For each output channel, the supply current is given by
ADuM1400/ADuM1401/ADuM1402 transformers. Figure 20
expresses these allowable current magnitudes as a function of IDDO = IDDO (Q) f ≤ 0.5 fr
frequency for selected distances. As shown, the ADuM1400/ IDDO = (IDDO (D) + (0.5 × 10 ) × CL × VDDO) × (2f − fr) + IDDO (Q)
−3
Rev. L | Page 28 of 31
Data Sheet ADuM1400/ADuM1401/ADuM1402
INSULATION LIFETIME In the case of unipolar ac or dc voltage, the stress on the insulation
All insulation structures eventually break down when subjected is significantly lower, which allows operation at higher working
to voltage stress over a sufficiently long period. The rate of voltages while still achieving a 50-year service life. The working
insulation degradation is dependent on the characteristics of voltages listed in Table 14 can be applied while maintaining the
the voltage waveform applied across the insulation. In addition 50-year minimum lifetime, provided the voltage conforms to either
to the testing performed by the regulatory agencies, Analog the unipolar ac or dc voltage cases. Any cross-insulation voltage
Devices carries out an extensive set of evaluations to determine waveform that does not conform to Figure 22 or Figure 23 should
the lifetime of the insulation structure within the ADuM1400/ be treated as a bipolar ac waveform, and its peak voltage should
ADuM1401/ADuM1402. be limited to the 50-year lifetime voltage value listed in Table 14.
Analog Devices performs accelerated life testing using voltage Note that the voltage presented in Figure 22 is shown as sinusoidal
levels higher than the rated continuous working voltage. Accel- for illustration purposes only. It is meant to represent any voltage
eration factors for several operating conditions are determined. waveform varying between 0 V and some limiting value. The
These factors allow calculation of the time to failure at the actual limiting value can be positive or negative, but the voltage cannot
working voltage. The values shown in Table 14 summarize the cross 0 V.
RATED PEAK VOLTAGE
peak voltage for 50 years of service life for a bipolar ac operating
condition and the maximum CSA/VDE approved working
03786-021
0V
voltages. In many cases, the approved working voltage is higher
than a 50-year service life voltage. Operation at these high working Figure 21. Bipolar AC Waveform
voltages can lead to shortened insulation life in some cases. RATED PEAK VOLTAGE
03786-022
ADuM1402 depends on the voltage waveform type imposed 0V
across the isolation barrier. The iCoupler insulation structure Figure 22. Unipolar AC Waveform
degrades at different rates depending on whether the waveform RATED PEAK VOLTAGE
is bipolar ac, unipolar ac, or dc. Figure 21, Figure 22, and Figure 23
03786-023
illustrate these different isolation voltage waveforms, respectively.
0V
Bipolar ac voltage is the most stringent environment. The goal Figure 23. DC Waveform
of a 50-year operating lifetime under the ac bipolar condition
determines the Analog Devices recommended maximum
working voltage.
Rev. L | Page 29 of 31
ADuM1400/ADuM1401/ADuM1402 Data Sheet
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
16 9
7.60 (0.2992)
7.40 (0.2913)
1 10.65 (0.4193)
8
10.00 (0.3937)
03-27-2007-B
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
ORDERING GUIDE
Number Number Maximum Maximum Maximum
of Inputs, of Inputs, Data Rate Propagation Pulse Width Temperature Package Package
Model1, 2, 3, 4 VDD1 Side VDD2 Side (Mbps) Delay, 5 V (ns) Distortion (ns) Range Description Option
ADuM1400ARW 4 0 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM1400BRW 4 0 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM1400CRW 4 0 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM1400ARWZ 4 0 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM1400BRWZ 4 0 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM1400CRWZ 4 0 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM1400WSRWZ 4 0 1 100 40 −40°C to +125°C 16-Lead SOIC_W RW-16
ADuM1400WTRWZ 4 0 10 34 3 −40°C to +125°C 16-Lead SOIC_W RW-16
ADuM1401ARW 3 1 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM1401BRW 3 1 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM1401CRW 3 1 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM1401ARWZ 3 1 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM1401BRWZ 3 1 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM1401CRWZ 3 1 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM1401WSRWZ 3 1 1 100 40 −40°C to +125°C 16-Lead SOIC_W RW-16
ADuM1401WTRWZ 3 1 10 34 3 −40°C to +125°C 16-Lead SOIC_W RW-16
ADuM1402ARW 2 2 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM1402BRW 2 2 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM1402CRW 2 2 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM1402ARWZ 2 2 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM1402BRWZ 2 2 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM1402CRWZ 2 2 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM1402WSRWZ 2 2 1 100 40 −40°C to +125°C 16-Lead SOIC_W RW-16
ADuM1402WTRWZ 2 2 10 34 3 −40°C to +125°C 16-Lead SOIC_W RW-16
EVAL-ADuMQSEBZ Evaluation Board
1
Z = RoHS Compliant Part.
2
W = Qualified for Automotive Applications.
3
Tape and reel are available. The addition of an -RL suffix designates a 13” (1,000 units) tape and reel option.
4
No tape and reel option is available for the ADuM1400CRW or ADuM1402BRW models.
Rev. L | Page 30 of 31
Data Sheet ADuM1400/ADuM1401/ADuM1402
AUTOMOTIVE PRODUCTS
The ADuM1400W/ADuM1401W/ADuM1402W models are available with controlled manufacturing to support the quality and reliability
requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial
models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products
shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product
ordering information and to obtain the specific Automotive Reliability reports for these models.
Rev. L | Page 31 of 31