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Vol. 36, No. 11 Journal of Semiconductors November 2015

Modeling and simulation of single-event effect in CMOS circuit

Yue Suge(岳素格)1; 2; Ž , Zhang Xiaolin(张晓林)1 , Zhao Yuanfu(赵元富)2 ,
Liu Lin(刘琳)2 , and Wang Hanning(王汉宁)2
1 Beijing University of Aeronautics & Astronautics, Beijing 100191, China
2 Beijing Microelectronics Technology Institute, Beijing 100076, China

Abstract: This paper reviews the status of research in modeling and simulation of single-event effects (SEE) in
digital devices and integrated circuits. After introducing a brief historical overview of SEE simulation, different
level simulation approaches of SEE are detailed, including material-level physical simulation where two primary
methods by which ionizing radiation releases charge in a semiconductor device (direct ionization and indirect ion-
ization) are introduced, device-level simulation where the main emerging physical phenomena affecting nanometer
devices (bipolar transistor effect, charge sharing effect) and the methods envisaged for taking them into account are
focused on, and circuit-level simulation where the methods for predicting single-event response about the produc-
tion and propagation of single-event transients (SETs) in sequential and combinatorial logic are detailed, as well as
the soft error rate trends with scaling are particularly addressed.

Key words: single event effect (SEE); charge collection; single event upset (SEU); multi-node upset (MNU)
DOI: 10.1088/1674-4926/36/11/111002 EEACC: 2570

1. Introduction
laterŒ3 . Soon after this first observation of SEU in the natu-
Nondestructive single-event transient (SEE) is caused by ral space environment, SEU was observed in dynamic random
charge deposition by direct ionization from heavy ions and in- access memories (DRAM’s) operating in terrestrial environ-
direct ionization from protons, neutrons and some heavy ions. mentsŒ4 , spurring a flurry of SEU-related work in the latter
The deposited charge can be collected by drift and diffusion years of the1970’sŒ5 . Given the consequences of SEU, such as
in semiconductor devices, causing current transients that can potential loss of mission for space applications, a possible show
result in circuit malfunction. stopper for increased integration density in terrestrial memory
Simulations of SEE have been crucial to developing an un- cells, the rapid development of models to explain and predict
derstanding of the mechanisms behind SEE and for suggesting radiation effects was essential.
methods for hardening devices. As devices continue to evolve Shortly following the discovery of SEU, researchers at
to smaller dimensions, device-level modeling will encounter IBM used two-dimensional (2-D) finite-element device sim-
new challenges such as the ion strike affecting more than a ulator FIELDAY to compute the response of reverse-biased
single transistor at a time. A greater level of usefulness can p/n junctions to alpha-particle strikesŒ5; 6 . An important insight
be reached when simulation tools prove to be validated and gained from these early charge-collection simulations was the
predictive. At this level, simulations become essential during existence of a transient disturbance in the junction electrostatic
the design process for reducing the number of “fab-and-test” potential, which was termed the “field funnel” as shown in
cycles that must be completed to develop radiation-hardened Figure 2Œ7 . This funneling effect can increase charge collec-
technologies. tion at the struck node by extending the junction electric field
In this paper a brief historical overview of SEE simulation away from the junction and deep into the substrate, such that
is given, and a complete suite methodology for SEE simulation charge deposited some distance from the junction can be col-
is detailed, which contains three parts: material-level physical lected through the efficient drift process. The funnel effect has
simulation, device simulation and circuit-level simulation, as been investigated in further detail by later researchersŒ8; 9 , with
shown in Figure 1. The user can use the complete Suite method- the analytical models for funneling developed by McLean and
ology to get the chip cross section, and also use any part of the OldhamŒ8 being an important early contribution to understand-
methodology respectively to get the corresponding result. ing several characteristics of funneling. Later research studied
the influence of epitaxial substrates on the transient charge-
2. A brief history of SEE simulation collection characteristicsŒ10 12 . Several important additional
insights have been gained from these studies, and the reader is
Pioneering work on one-dimensional drift–diffusion nu- referred to References [10–13] for comprehensive discussions
merical modeling was presented at the Nuclear and Space Ra- of funneling.
diation Effects Conference as early as 1967Œ1; 2 , and rewarded Fully 3-D device simulators were first reported in the lit-
the best paper award for that yearŒ1 . This early work focused erature in 1980Œ14; 15 , and some of the early work on 3-D
on transient radiation response, as single-event upset (SEU) device simulation was motivated by alpha-particle reliability
would not be observed experimentally until almost 10 years issuesŒ16 18 . An early comparison of 2-D and 3-D charge-

† Corresponding author. Email: yuesg9999@163.com

Received 11 June 2015, revised manuscript received 23 July 2015 © 2015 Chinese Institute of Electronics

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J. Semicond. 2015, 36(11) Yue Suge et al.

Figure 1. (Color online) A complete suite methodology for SEE simulation. The methodology includes GDS to a material-level physical simu-
lation, device simulation, circuit-level simulation and on-orbit error-rate prediction.

Figure 2. Charge collection mechanism in a reverse-biased pn junc-

tion.
Figure 3. Electron concentration contours inside an n-channel MOS
transistor following a heavy ion strikeŒ22 . Bipolar effect is evidenced
by the contours emanating from the source, showing that the source
collection simulations showed that while the transient re- is injecting electrons into the p-well, where they may be collected at
sponses were qualitatively similar, significant quantitative dif- the substrate or at the drain.
ferences existed, both in the magnitude of the current response
and the time scale over which collection was observedŒ19 . The
obvious implication of these results is that while 2-D simula- following the strike, the electrostatic potential in the channel
tions may provide basic insight, 3-D simulation is necessary if region is perturbed, leading to a significant (but short-lived)
truly predictive results are to be obtained. source–drain conduction current that mimics the “on” state of
In submicron devices, the charge-collection response of a the transistor. The experiments indicate that source charge in-
single p/n junction cannot be presumed to accurately depict the jection due to this mechanism increases rapidly for effective
response of the sensitive junction of a transistor, typically a gate lengths below about 0.5 m. Later work predicted that
reverse-biased drain region. Studies have indicated that a new the same direct channel conduction mechanism can occur in
charge-collection mechanism may exist for submicron MOS 0.3-m gate length MOSFETs even for normal incidence
transistors that requires considering the entire transistorŒ20 . strikes and can lead to charge multiplicationŒ21 . This mech-
This mechanism was revealed by 3-D alpha-particle simula- anism may forebode a serious vulnerability to SEU for deep
tions and has been experimentally verified. Termed the alpha- submicron MOSFETs.
particle source–drain penetration effect (ALPEN), this charge- A somewhat similar, but distinct mechanism exists when
collection mechanism results from a disturbance in the channel electrons or holes released by a particle strike are confined to a
potential that the authors referred to as a funneling effect. The well or body region in which a transistor is located. For exam-
effect is triggered by a particle strike that passes through both ple, for an n-channel MOS transistor located in a p-well, elec-
the source and the drain at near-grazing incidence. Immediately trons induced by a particle strike can be collected at either the

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J. Semicond. 2015, 36(11) Yue Suge et al.

Figure 4. (a) Schematic of SPICE simulation circuit. (b) Schematic of SEU current.

drain/well junction or the well/substrate junction. However, as to study SEU in CMOS SRAMs in 1997Œ33 and since then have
illustrated in Figure 3, holes left in the well raise the well poten- received a great deal of continued use for this purposeŒ25 .
tial and lower the source/well potential barrier, and the source With technology scaling, new phenomenon is expected to
injects electrons into the channelŒ22 24 . These electrons can be occur inside the device and SEE becomes more complex. 3-D
collected at the drain, where they add to the original particle- mixed-level simulations are used to study the new SEE mech-
induced current and can cause an increased SEU sensitivity. anism and predict upset thresholds. 3-D full-cell simulations
Because the electrons are injected over the source/well bar- are used to compute the upset cross section. These simulation
rier, this is referred to as a bipolar transistor effect, where the methods will be described in a later section.
source acts as the emitter, the channel as the base region, and
the drain as the collector. Reducing the channel length effec-
tively decreases the base width, and the effect becomes more
3. Material-level physical simulation
pronouncedŒ24 . There are two primary methods by which ionizing radia-
In the previous sections, we discussed physics-based de- tion releases charge in a semiconductor device: direct ioniza-
vice models that simulate the charge collection in a device fol- tion by the incident particle itself and ionization by secondary
lowing an ion strike. Stepping up in a hierarchical view, these particles created by nuclear reactions between the incident par-
models can be incorporated into macro-models of the devices ticle and the struck device. Both mechanisms can lead to inte-
interconnected in a sub circuit. The macro view of the circuit grated circuit malfunction.
will relate the collection of charge in individual device junc-
tions to changes in the circuit currents and voltages. 3.1. Direct ionization
A common circuit model for the charge collection at a
junction due to direct funneling or diffusion is a double- When an energetic charged particle passes through a semi-
exponential time-dependent current pulse developed by Mes- conductor material it frees electron-hole pairs along its path as
senger in 1982. The effect of the collected charge from an it loses energy. When all of its energy is lost, the particle comes
ion track is described by inserting the current generator I.t / to rest in the semiconductor, having traveled a total path length
across the sensitive junction or junctions in an IC using a com- referred to as the particle’s range. We frequently use the term
puter code program such as SYSCAP. This SPICE simulation linear energy transfer (LET) to describe the energy loss per unit
method has a fast speed, but lack of accuracy. path length of a particle as it passes through a material. LET
Recently, the simultaneous solution of device and circuit has unit of MeV
cm2 /mg, because the energy loss per unit path
equations has been increasingly used. This technique, known length (in MeV/cm) is normalized by the density of the target
as mixed-mode or mixed-level simulation, was developed by material (in mg/cm3 /, so that LET may be quoted roughly in-
Rollins at USC/Aerospace in the late 1980sŒ31 . The term dependent of the target. We can easily relate the LET of a par-
“mixed-level” is probably less confusing and more descrip- ticle to its charge deposition per unit path length. In silicon, an
tive than “mixed-mode”. In a mixed-level simulation of SEU, LET of 97 MeV
cm2 /mg corresponds to a charge deposition of
the struck device is modeled in the “device domain” (i.e., us- 1 pC/m. This conversion factor of about 100 is handy to keep
ing multi-dimensional device simulation), while the rest of in mind to convert between LET and charge deposition.
the memory cell is represented by SPICE-like compact circuit A curve of particular interest for understanding the interac-
models, as illustrated in Figure 4Œ26 . The two domains are tied tion of a given energetic particle with matter is the LET of the
together by the boundary conditions at contacts, and the solu- particle versus depth as it travels through the target material.
tions to both sets of equations are rolled into one matrix so- Figure 5 shows such a curve for a 210-MeV chlorine ion trav-
lutionŒ31; 32 . The advantage is that only the struck device is eling through silicon. Such curves are readily obtained using
modeled in multiple dimensions, while the rest of the circuit computer codes derived from the work of Ziegler et al. (e.g.,
consists of computationally efficient SPICE models. This de- the TRIM and SRIM family of codesŒ32 /. This figure shows
creases simulation times and greatly increases the complexity the basic characteristics of ion-induced charge deposition as a
of the external circuitry that can be modeled. Mixed-level ca- function of depth. The peak in charge deposition is referred to
pability has been incorporated into most of the commercially- as the Bragg peak and in general occurs as the particle reaches
available 3-D device codesŒ27 30 . These codes were first used an energy near 1 MeV/nucleon. A useful rule of thumb is that

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J. Semicond. 2015, 36(11) Yue Suge et al.

Figure 6. (Color online) Three scenarios of SEU caused by elastic scat-

tering of 1 GeV Ne ions. The red, green and blue tracks are incident
ion, recoil and scattered ion, respectively.
Figure 5. Linear energy transfer (LET) versus depth curve for
210-MeV chlorine ions in silicon. Semiconductor device technologies scaling down to sub-
90 nm induce new problems such as direct ionizing pro-
the maximum LET (in MeV
cm2 /mg) of an ion is roughly equal tonsŒ40 46 and radial ionization profile effects on SEEsŒ47 49 .
to its atomic number. A more rigorous discussion of the Bragg Thus, terrestrial neutrons and protons induced SEUs are one of
curve and the Bragg peak is found in Reference [33]. such key issues that can be a major challenge to future nano-
Direct ionization is the primary charge deposition mecha- metric technologies. Particularly, multicell upsets (MCUs),
nism for upsets caused by heavy ions, where we define a heavy which are defined as simultaneous errors induced by a single
ion as any ion with an atomic number greater than or equal to event in more than one memory cell, are particularly investi-
two (i.e., particles other than protons, electrons, neutrons, or pi- gated. Thus, soft error rate (SER) determination is still a chal-
ons). Lighter particles such as protons do not usually produce lenge to evaluate the technology sensitivity and to extrapolate
enough charge by direct ionization to cause upsets in memory the trends for future generations of devices.
circuits, but recent research has suggested that as devices be- Different simulation and experimental approaches are in
come ever more susceptible, upsets in digital ICs due to direct the literature to estimate the SER induced by terrestrial neu-
ionization by protons may occurŒ34; 35 . tron environment: accelerated testing using alpha, neutron, or
proton source/beams, real-time testing performed in the nat-
3.2. Indirect ionization ural environmentsŒ50 56 , and a combination of experimental
and simulation approachesŒ57 . An alternative approach con-
Although direct ionization by light particles does not usu- sists in using the modeling at device and/or circuit level. Each
ally produce enough charge to cause upsets, this does not mean approach has advantages and drawbacks.
that we can ignore these particles. Protons and neutrons can Hubert et al.Œ58 used MUSCA SEP3 to simultaneously
both produce significant upset rates due to indirect mecha- measure the neutron environment and the SEU response of
nisms. As a high-energy proton or neutron enters the semi- nanoscales devices (see Figure 11).
conductor lattice it may undergo an inelastic collision with a Gong et al.Œ59 and Brewster et al.Œ60 find the recoils pro-
target nucleus. Any one of several nuclear reactions may oc- duced in elastic collisions to be the reason a non-zero SEU
cur; examples for protons and neutrons can be found in Refer- cross-section under normally incident ion beams of the radi-
ences [35, 36]. Possible reactions include: (1) elastic collisions ation hardened DICE SRAM cell design (see Figure 6). Gong
that produce Si recoils; (2) the emission of alpha or gamma et al.Œ59 found three distinct scenarios considered in the elastic
particles and the recoil of a daughter nucleus (e.g., Si emits collisions of heavy ion with the target material:
alpha-particle and a recoiling Mg nucleus); and (3) spallation (1) The projectile particle hits two sensitive volumes in the
reactions, in which the target nucleus is broken into two frag- DICE latch;
ments (e.g., Si breaks into C and O ions), each of which can (2) The recoil nucleus hits two sensitive volumes;
recoil. Any of these reaction products can now deposit energy (3) The projectile and the recoil nucleus each hits a sensi-
along their paths by direct ionization. Because these particles tive volume.
are much heavier than the original proton or neutron, they de- SEU events caused by each of the three modes were found
posit higher charge densities as they travel and therefore may in the calculation, but the relative importance is dependent on
be capable of causing an SEU. the ion species, incident angle and other factors.
Inelastic collision products typically have fairly low ener-
gies and do not travel far from the particle impact site. They
also tend to be forward-scattered in the direction of the origi-
4. SEE device-level simulation in nano-
nal particle; this has consequences for the SEU sensitivity as a technology
function of the angle of incidenceŒ38; 39 . Once a nuclear reac- 4.1. Device/cell mixed-level simulation
tion has occurred, the charge deposition by secondary charged
particles is the same as from a directly ionizing heavy ion With technology scaling, a new phenomenon is expected
strike. to occur inside the device, right after the charge creation: the

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J. Semicond. 2015, 36(11) Yue Suge et al.

Figure 7. Mixed-mode simulation structure for SRAM cells. Illustra-

tion is of an n-channel “off” drain strike.

so-called charge sharing. Considering the diffusion-collection

model, charges that are created in the silicon first transport by
diffusion and when reaching the junction are collected by the
electric field. The charge sharing is defined as a modification
of the charge collected by a junction due to neighboring junc-
tions. In other words, junctions are so close that the drift collec-
tion current at a given junction can be changed by secondary
electric fields induced by neighboring junctions. As the cell
size decreases, it has been shown that a greater charge sharing
between nodes has an influence on the amount of charges col-
lected by a node inducing a decrease of the cell sensitivity. Ol-
son et al.Œ61 , Amusan et al.Œ62 and Liu et al.Œ63 explore charge
sharing effect in an HBD Sram cell using Mixed-Mode 3D de-
vice simulation. In the simulation all transistors are modeled in
HSPICE model except the struck transistors. These transistors Figure 8. (Color online) Electron concentration contours inside an n-
are simulated in 3D to make possible the study of the ion effect channel MOS transistor at (a) 0.5 ps and (b) 0.1 ns, respectivelyŒ3 .
in the device volume, as shown in Figure 7. Charge induced by incident ion diffusion to the second node where
StudiesŒ61 63 explore that charge sharing effect: charge enough charge is collected.
diffusion between NMOS sensitive node pairs (Figure 8) and
parasitic bipolar conduction between NMOS and PMOS sen-
sitive node pairs, can flip an HBD Sram cell. olds in very good agreement with measured thresholdsŒ68 . In
these simulations, the most sensitive strike location is assumed
4.2. Entire cell 3-D modeling and multiple-point simulation based on past experience. However, error rates in ICs are de-
pendent not only on the threshold LET, but also on the sensi-
A drawback of the mixed-level method is that coupling ef- tive area, which cannot be obtained from a single-point simu-
fects between adjacent transistors have been shown to exist at lation. Researchers have generated simplified step-function
the device level using 2-D simulationsŒ65 . These effects cannot cross-section curves from theoretical and simulation results by
be taken into account when only the struck device is modeled making assumptions about the sensitive areaŒ69; 70 .
at the device level. To address this difficulty, it is necessary Using a customized version of a commercial 3-D device
to simulate the entire SRAM cell in the 3-D device domainŒ66 . simulator running on a large parallel computer, researchers
An illustration of the technique is shown in Figure 9Œ64 . Figure have recently demonstrated the ability to directly compute the
9(a) shows a top–down view of the SRAM cell layout, while upset cross section of an SRAM. The Cogenda Company has
Figure 9(b) shows the actual computational mesh used for sim- developed a complete suite methodology for SEU Simulation
ulations. When compared to the results of standard mixed-level to compute the upset cross section of an SRAM, as shown in
simulations, it has been found that in cases where no coupling Figure 10Œ71 .
effects between transistors exist, mixed-level simulations are These simulations were based on full-cell simulations, but
adequate to reproduce the full SRAM cell results. For some separate simulations were performed for ion strikes incident
strike locations, however, coupling effects between adjacent every 0.5 m throughout an SRAM unit cell. One set of sim-
transistors are observedŒ66; 67 . Mixed-level simulations are in- ulations gave a map of the SEU-sensitive area of the SRAM
capable of predicting such effects. As inter device spacing de- unit cell for a given ion and energy, as shown in Figure 11.
creases with increasing integration levels, coupling effects can By repeating the simulations for several ion/energy combina-
be expected to become more important, and simulating the en- tions, the authors generated the evolution of the sensitive area
tire SRAM cell in the device domain may become routinely as a function of ion LET. Combining the information in the
necessaryŒ66 . individual upset maps, the full upset cross-section curve was
Standard single-point (i.e., one ion strike location) 3-D predicted and found to be in excellent agreement with experi-
mixed-level simulations are known to predict upset thresh- mental results.

111002-5
J. Semicond. 2015, 36(11) Yue Suge et al.

Figure 9. (Color online) (a) Layout of 256K six-transistor SRAM unit

cell (D D drain and S D source). Red box indicates the boundaries Figure 10. (Color online) A complete Suite methodology for SEU
of the unit cell, green regions are the gate polysilicon lines, and blue simulation. The methodology includes GDS to an entire SRAM cell
lines show the interconnections within the unit cell. (b) View of 3-D 3-D physical mesh, particle event generation, particle (TCAD) simu-
unit cell as laid out in device simulator. Mesh size is approximately lations and statistical analysisŒ71 .
100 000 pointsŒ64 .

5. SEE circuit-level simulation

As circuits grow exponentially in density and complexity,
comprehensive circuit simulation is impractical. Over the past
decade, other methods to track radiation vulnerability at the
circuit level have emerged, primarily in the realm of core logic.
In the mid 1990s, Baze and Buchner performed a series
of circuit simulations and laser experiments on combinational
logic to extract general properties of single-event propaga-
tionŒ72; 75 . They concluded that: (1) the soft error rate is inde- Figure 11. (Color online) Full-cell simulations to get a map of the
pendent of the frequency in latch circuits when the setup and SEU-sensitive area of the SRAM unit cellŒ71 .
hold time is much less than the clock period; (2) the soft error
rate increases linearly with the operating clock frequency in
the combinational circuits; and (3) soft errors in latch circuits circuit by the way of injecting a hardware or software form fail-
dominate in present day technologies, but the errors in the com- ure. The error and failure numbers of the circuit can be statis-
binational circuits will dominate in future technologies. tic by observing the circuit outputs. The soft error rate of the
In 1997, Massengill et al.Œ76 presented a probabilistic circuit and the sensitivity of the memory cell can be obtained
description of single-event fault generation, propagation, and by simulation, then the anti-SEE capability of the circuit can
logic error events using a high-level VHDL circuit description. be evaluated while the radiation hardening suggestion can be
This method was demonstrated in simulation code at NSREC provided to the IC designers. According to the fault type and
in 2000Œ77 . Seifert et al.Œ73; 74 have presented an analytical implementation modes, the fault injection methods can be di-
description of core logic soft error vulnerability based on the vided into three classes based on hardware, software and simu-
“window of vulnerability” of in-data-path static and dynamic lation. Table 1 summarizes and compares the main features of
latch elements, the synchronous clock, and other deterministic different SEU fault injection approaches.
elements. As the semiconductor dimension developed to nanometer,
The fault injection technique is an important form of the the impact of single event effect fault injection simulation is
single event effect simulation for integrated circuits, which can mainly reflected in the following three aspects: First, the prepa-
simulate the production process of the single event transient ration and computation workload of the simulation will be dou-
(SET) and single event upset (SEU) effects that happened in a bled due to the large scale and high frequency of the circuit. A

111002-6
J. Semicond. 2015, 36(11) Yue Suge et al.

Table 1. Abilities of different fault injection techniques.

Class Mode Commonality Precision Coverage Speed Cost
Hardware Contact High Low Low Middle Middle
Non-contact High High High High High
Software Compile Low High Low Middle Low
Real-time Low High Low High Low
Emulation Simulation Middle High High Low Middle
tools
FPGA Middle Middle High High High

Netlist representation as shown in Figure 12. SOCFIT uses the

intrinsic sensitivities of each feature of the circuit and novel
statistical analysis and fault injection algorithms. SOCFIT is a
unique simulation platform that interacts with existing static
timing analysis and simulation/verification tools (like SNPS
VCS).
Chapman et al.Œ79 presented a practical implementation of
a complete SER analysis flow applied on a complex commer-
cial chip implemented in 90 nm. IROC provided the overall
SER analysis tools and methodology:
Firstly, intrinsic (raw) cell sensitivity figures should be
Figure 12. (Color online) SOCFIT modules and environmentŒ51 . provided as a starting point. Strong and unique support has
been offered by the technology provider in the form of SER
figures for the standard and memory cells. Additional cell SER
traditional fault injection mode (like contact-mode, simulation data are provided by the IROC TFIT tool.
tools-mode, etc.) may not meet the scale requirements, while Secondly, per-circuit feature, soft-error-specific de-rating
traverse node simulation may be unacceptable due to the long must be performed. The de-rating strategy implemented in this
time. The research of optimize simulation will be carried on to project aims at evaluating the percentage of SEE faults that
reduce the time cost. Second, with the complexity and the sys- will produce an observable impact at the system level. The
tematization of the circuit function being increased, the highly main approach consists in considering the different abstrac-
integrated circuit will be difficult to change the internal sig- tion levels/representations for the SEEs: (1) the single event
nal using the program instruction. The contact-mode hardware fault is the direct manifestation of the SEE. SETs and SEUs in
fault injection simulation may be difficult to implement due to standard cells are SE faults; their effects are not yet visible at
the high density packaging (like BGA, etc.). A similar problem the system level. Moreover, there is a strong timing de-rating
may have happened in emulation mode fault injection, where (TDR) that must be applied in order to take into account the
the target circuit cannot work properly due to the signal prop- arrival instant of the SET/SEU fault and the short duration of
agation delay being increased by the insertion of fault injector SET. A TDR analysis tool that uses a static timing analysis
structure. Third, as the single event effect type is increased (like approach to painlessly evaluate the sequential logic TDR has
MBU, SEFI, etc.), the simulation form has been changed from been implemented. Combinational TDR has been computed by
one-dimensional fault injection to multi-dimensional, where the IROC SOCFIT tool. SEUs in memory blocks are directly
aspects such as position, time, effect category should be con- equivalent to soft errors; there are no supplementary condi-
sidered. The complexity of the fault injection control architec- tions or de-ratings. SEUs in sequential cells must be de-rated
ture is increased, so is the method of the SEFI fault injection in by the TDR. (2) SETs in combinational cells need to propagate
a software way. through the logic network, and then arrive at the latching in-
In summary, the fault injection simulation at nanometer put of a sequential element during a specific opportunity win-
technology needs a breakthrough of innovation. Three fault dow. Thus, SETs require an extra logic de-rating (LDR) step
injection forms should be mixed into some new simulation that models the probability of the SET propagation through the
method according to different single event effects. We need to circuit. Given the relatively low contribution of SETs, the prob-
combine the advantages of hardware-fast, software-accuracy, abilistic LDR methods from the SOCFIT tool have been used.
high automation, and emulation-wide coverage of various The methodology consists in evaluating the probability for a
forms of effect developing different fault injection structures fault appearing on the output of a combinational cell to reach
and procedures. In this way, the requirements of multiple sin- the data input of a sequential element. The overall propagation
gle event effects simulation for nanometer circuits will be met. probability is a function of the activated path combinational
As the soft error threat increases in the latest technology cells. Both the net state probabilities and the individual cells
process nodes (65 nm and below), various industries are in propagation functions are known and the tool is able to predict
need of investigating this serious reliability issue. Within these the fault propagation through any logic combinational network.
solutions is the SOCFIT software, a simulation tool that pre- (3) This visible manifestation of the SEE is a functional failure.
dicts quickly and accurately the failure rate (FIT) and various The evaluation of the soft error transformation in a functional
de-rating factors of ASIC and SoC, using either RTL or Gate failure (functional de-rating, FDR) has been performed during

111002-7
J. Semicond. 2015, 36(11) Yue Suge et al.
used in these investigations; it consists in coupling MUSCA
SEP3 with electrical simulationsŒ85 (CADENCE tool). The
transport/collection physical model is based on investigations
initiated in 2008 and was first intended for transient simula-
tionsŒ82; 86 . The main improvement consists in taking into ac-
count the dynamic coupled ambipolar diffusion and collection
velocity. The approach is based on charge sharing rules, which
depend on the distance from the strike location to collection
volume, the local electric field, and the process parameters
(substrate/well doping).
While evaluating the sensitivity of the large scale inte-
grated circuit with respect to SEEs is not an easy task, firstly
characterizing intrinsic (raw) cell sensitivity figures is a chal-
lenge by itself since the component manufacturer will ask the
Figure 13. (Color online) Overview of the global approach integrating technology provider relevant SER information about the dif-
MUSCA SEP3 and electrical simulations. ferent standard cell libraries, memory blocks, macro cells, IP
blocks, etc. The next challenge consists in taking into account
all the factors affecting the SER sensitivity in a systematic ap-
an extensive error injection and simulation campaign. The sta- proach, which include de-rating the raw SER values accord-
tistical fault injection is done on the RTL model, where a data ing to the specificities of SET and SEU and the actual func-
base of all structures required, taken from the gate level model, tion and behavior of the circuit in the typical, end-user appli-
is created. cation. Future research directions include above challenges to
Lastly, the manufactured circuit may be used in a variety get an effective methodology of evaluating the SER of the large
of scenarios. De-rating based on the activity levels of different scale integrated circuit, which consequently helps the designers
clock domains of the circuit has been performed. This approach implementing the optimal error mitigation methodology and
can be used to quickly analyze different test cases or to evalu- gives guidance to radiation experimentation.
ate the SER figures for a circuit activity factor identical to the
actual field usage.
In 2014, Hubert et al.Œ80 presented an SET predictive
6. Conclusion
methodology based on coupled MUSCA SEP3 and electri- This paper gives a brief historical overview of SEE simula-
cal simulations (CADENCE tool). These methodologies have tion and reviews the current status of simulation methodology
been validated in the case of 1000 inverters chain and for of SEE in detail, with an emphasis on significant results of re-
heavy ions and demonstrate the impact of the quenching ef- cent years. Simulations of SEE have been crucial to developing
fect. Furthermore, both the designs (respectively for same-well an understanding of the mechanisms behind SEE, which can be
and separate-well designs) were considered and the analyses used in developing new hardening techniques, the capability
are consistent with experiments and this allows for identifica- to perform comprehensive “what if’ studies that are not fea-
tion of the quenching effect as the main mechanism responsi- sible by experimentation alone and reduced heavy-ion testing
ble for the difference in SET sensitivity. The pulse quench- enabled by predictive simulation capabilities. Future research
ing mechanism is induced by the multi-collection of closed directions include an effective methodology of evaluating the
cells and electrodes which disturbs the circuit response. This SER of the large scale integrated circuit, which consequently
phenomenon has been revealed in previous works by Alhbin helps the designers implementing the optimal error mitigation
et al.Œ87 . Recent workŒ88 emphasizes the relevance of multi- methodology and gives guidance to radiation experimentation.
collection to induce pulse quenching for SET mitigation. The
prediction platform MUSCA SEP3 leads to analyzing the SET
quenching mechanisms.
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