IACSIT International Journal of Engineering and Technology, Vol.3, No.

4, August 2011

Sine/Cosine Generator Using Pipelined CORDIC

Processor

R. Ranga Teja, P. Sudhakara Reddy, IEEE, Member

possible in rotation and vectoring mode of circular, linear,

Abstract — At present, many of the computations in signal and hyperbolic coordinate systems [3][4]. CORDIC
processing and wireless communication applications are linked technique has been used in many applications, such as signal
with complex analysis of several functions. These complex
processing, linear transformations, digital filters and matrix
functions are combination of sine and cosine terms that
generally spread in the channel. Most of these functions can be based computations. Ultra low power systems can be
split into elementary functions. In this paper we present a efficiently developed by CORDIC [5][6]. More recently, the
hardware efficient architecture by using CORDIC algorithm advances in the VLSI technology and the advent of EDA
for the calculation of sine and cosine functions. This approach is tools have extended the application of CORDIC algorithm to
simulated using ModelSim simulation software, synthesized the field of biomedical signal processing, neural networks,
using Xilinx ISE design suite and the proposed architecture is
software defined radio, and MIMO systems etc [7][8].
implemented on Xilinx FPGA target device i.e. SPARTAN 3E.
Finally, the device utilization summary and timing reports are
presented.
II. PROBLEM STATEMENT AND DEFINITION
Index Terms—CORDIC, FPGA, Pipelined processor, sine There is a real need of hardware efficient algorithms in the
and cosine generator.
present generation of technologies because of the intense
signal processing requirements needed by them. Thus, the
I. INTRODUCTION current trend is back toward hardware efficient algorithms.
Among all those unveiled, shift-and-add architectures
The solutions for the design of high speed VLSI
commonly known as CORDIC have wide range of attractive
architectures for real-time digital signal processing (DSP)
features that can compute almost all elementary functions
algorithms are mapped from algorithm into hardware
with simple architecture and further study on such algorithm
efficient architectures. With the advent of low cost, low
could give more interesting results which can be best suited
power FPGA's; design of such architectures which would
for all the present world applications. Many of those
satisfy the performance requirements for the signal
applications require elementary calculations like sin and
processing applications such as Three dimensional (3D)
cosine. Hence, in this paper we are presenting a sine/cosine
graphics, video/image/ signal processing systems has become
generator using CORDIC algorithm and its performance
simple.
reports. The pipelined architecture takes the angle/phase as
Many of the DSP algorithms uses the calculation of
input and gives both sine and cosine for the given input in
elementary functions such as trigonometric, inverse
predetermined number of micro rotations. These micro
trigonometric, logarithm, exponential, multiplication, and
rotations are decided by the accuracy demanded by the
division functions which require high computational power.
application.
The commonly used software solutions for the digital
Section I gives brief introduction, section II defines the
implementation of these functions are table lookup method
problem statement. The CORDIC algorithm and architecture
and polynomial expansions, requiring number of
are briefly studied in section III, The Simulation and
multiplication and additions/subtractions.
Synthesis results are discussed in section IV and finally
In 1959, Volder [1] has proposed a special purpose digital
concluded in section V.
computing unit known as COordinate Rotation DIgital
Computer (CORDIC). This algorithm was initially developed
for trigonometric functions, using Givens rotation transform III. CORDIC ALGORITHM AND ARCHITECTURE
technique. The CORDIC algorithm computes 2D rotation
using iterative equations employing shift and add operations The CORDIC algorithm involves rotation of a vector ' v' on
which have simple architecture and consume less power. the XY-plane in circular, linear and hyperbolic coordinate
Walther has proposed a unified algorithm to compute rotation systems depending on the function to be evaluated.
in circular, linear, and hyperbolic coordinate systems [2]. The The conventional method of implementation of 2D vector
CORDIC algorithm performs various elementary functions rotation using Givens rotation transform is represented by the
equations (1) and (2).

Manuscript received May 11, 2011.

= − sin (1)
R.Ranga Teja, Student, Dept.of ECE, Srikalahasteeswara Institute of = sin + cos (2)
Technology, Srikalahasthi, Andhra Pradesh, India. Ph:09985259705,
E-mail:rangateja@gmail.com. where ( , ) and ( , ) are the initial and final
Dr.P.Sudhakara Reddy, Associate Professor, Dept.of ECE,
Srikalahasteeswara Institute of Technology, Srikalahasthi, Andhra Pradesh, coordinates of the vector, respectively. The main principle of
India. Ph:09703415601, E-mail:psr_vlsi_dsp@rediffmail.com. CORDIC algorithm is to implement every function in terms

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of addition/subtraction and shifting. So, the multiplication equations of the CORDIC algorithm for each micro iteration
terms in Givens rotation equations are removed by after rearranging givens rotation can be written as shown in
rearranging the equations (1) and (2). The single rotation is equations (3), (4) and (5).
thus decomposed into micro rotations which are realized in
terms of add/sub and shift operations. The generalized

Fig. 1. Rotations in various coordinate systems

= − , (3) such that the vector always moves closer toward required
= , + (4) angle and decrease the value of the residual angle in angle
= − , (5) accumulator. The coordinates of a vector obtained after
micro-rotations from initial position ( , ) are given by
where represents the direction of rotation, represents the equations (9), (10) and (11)
the coordinate system in which the vector is rotating = ( cos − sin ) (9)
circular( = 1), linear( = 0) and hyperbolic( = −1). = ( sin + cos ) (10)
, is non decreasing integer shift sequence, indicates the →0 (11)
radix of number system in which CORDIC is implemented
and , is the elementary rotation angle. The latter directly CORDIC can be operated in different radix, generally
depends on , through the relation (6) powers of 2. The iteration equations of the radix-2 CORDIC
algorithm in rotation mode of circular coordinate system at
, = tan √ , (6) the ( + 1) step are obtained by using = 2 in above
√
equation and are given by the equations (12),(13) and (14)
The shift sequence , depends on the coordinate system
and the radix of number system. , affects the convergence = − 2 , (12)
= 2 + , (13)
of the algorithm and n affects the accuracy of the final result.
= − (14)
refers to the mode of CORDIC in which it is used.
CORDIC can be used in two modes. One is rotation mode
and other is vectoring mode. Equation (7) gives the value of where = tan (2 ) for circular coordinate system and
in the CORDIC equations. 2 and tanh (2 ) for linear and hyperbolic coordinate
systems. refers to the direction of tracking/iteration and
( ), , given by equation (15).
= (7)
− ( ), ,
−1, < 0,
= (15)
In rotation mode, the input angle θ (8) will be decomposed 1, ℎ ,
using a finite number of elementary angles
In order to maintain a constant vector length, the obtained
= + + . . . . .+ (8) results have to be scaled by the scale factor k given by
equation (16)
where n indicates the number of micro-rotations, is the
elementary angle for iteration and is the direction of = ∏ √1 + 2 (16)
micro-rotation. In rotation mode, is the angle accumulator
initialized with the input rotation angle. The direction of This constant factor changes with radix and for radix-2
vector in every iteration must be determined to reduce the CORDIC the constant factor, k ≈ 1.65.
magnitude of the residual angle in the angle accumulator. There are number of ways to implement the CORDIC
Therefore, the direction of rotation in any iteration is processor. The ideal architecture depends upon the speed
determined using the sign of the residual angle obtained in verses area tradeoff's in the intended application. Simple
the previous iteration. Initially, the coordinates of initial among them is serial architecture. It is the direct solution for
vector are ( , ) and the micro rotations are performed the CORDIC basic equations. In serial architecture only one

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basic CORDIC block is present which contains three simple = cos (17)
adder/Subtractors and two shifters with a ROM containing a = sin (18)
look up table. ROM contains the fixed angle constants for the →0 (19)
particular coordinate system in which CORDIC architecture
is implemented. This architecture performs one micro
rotation for every clock cycle. Thus, after clock cycles the IV. SIMULATION RESULTS
output is available. Since, it contains very less components This includes the simulation and synthesis of sine cosine
involved in its architecture this type of architectures are used generator implemented on the target device XILINX
in area specific applications. The serial architecture is slow as SPARTAN-3E. The sine cosine generator uses simple
it uses clock cycles for every single calculation. pipelined architecture based on CORDIC algorithm. Area
and delay reports are also included for the corresponding
target device. The CORDIC employed uses circular
co-ordinate system and is operated in rotating mode. Hence,
only phase is given as input and x, y values are given
internally in the program or hardware.

Fig. 3. Simulation results of sine/cosine generator

The code written in verilog is simulated using modelsim

XE II/Evaluation 5.7g. After simulation of main block it has
to be functionally verified. So, a test program with arbitrary
Fig. 2. Pipeline CORDIC processor inputs is written, figure.3 shows the compilation of test bench
program by giving various test inputs to the master program.
The second one is the pipelined structure. Pipelined As it is a pipelined architecture inputs can be given at
CORDIC contains number of CORDIC blocks which are every clock pulse and the cos and sine values for
cascaded. It contains fixed shift registers at each pipelined corresponding inputs will output after eight clock cycles as it.
stage and performs fixed number of shifts every time. It The three outputs for every angle input are sin function,
contains registers at every stage to store the fixed angle for cosine function and error (eps). eps indicates the proximity to
the particular micro rotation at each block in pipeline the required angle tracked by CORDIC. In general eps
architecture. Thus, the first block always performs the first indicates .If the numbers of CORDIC blocks are increased
micro rotation i.e., 45 degrees. In the same way each block in in a pipeline architecture eps becomes less and approaches to
this performs a single micro rotation. i.e., stage performs zero.
the micro rotation. This architecture is advantageous to
serial architecture as it is fast and doesn't require a look up
table. The number of blocks is dependent on the accuracy
demanded by the application in which CORDIC is employed.
The sign of z gives the direction of iteration for every stage as
defined by the CORDIC equations and it can be clearly seen
in the figure 2.
In this paper, the sine cosine generator we developed is a
pipeline CORDIC with six cascaded stages each performing
a specific micro-rotation. It operates in circular coordinate
system in rotation mode. we use initial points of a vector as
1 , 0 and input angle . Thus, the final coordinate
equations become the required sine and cosine functions as
represented by the equations (17),(18) and (19) Fig. 4. XILINX window showing synthesized pin diagram

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After the simulation of code in ModelSim the code is REFERENCES

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V. CONCLUSION
In this paper, we developed a sine cosine generator, a R. Ranga Teja B.Tech, Department of Electronics and
common elementary trigonometric functions using one of the Communication Engineering, Sri Kalahasteeswara
hardware efficient algorithm namely CORDIC. The sine Institute of Technology, Srikalahasti, Chittoor District,
Andhra Pradesh. He received B.Tech degree in
cosine generator is targeted for SPARTAN 3E and it requires Electronics and Communications Engineering from
11% of its total number of slices with a time delay of 6.76 ns JNTU Ananthapur University. He was born on 1991 at
in which 55% of delay is for logic and rest for routing. As the Wanaparti in Andhra Pradesh. His area of research goes
with VLSI and Digital Signal Processing.
implemented design is a pipelined one, it is more efficient
than bit serial approach and is more accurate and Dr.P.Sudhakara Reddy, Associate Professor, Department of Electronics
advantageous than bit serial architecture. and Communication Engineering, Sri Kalahasteeswara Institute of
Technology, Srikalahasti, Chittoor District, Andhra Pradesh. He received
CORDIC is not only used in computation of elementary B.Tech degree in Electronics and Communications Engineering from
functions but also used for tracking of moving targets in N.B.K.R Institute of Science and Technology, Sri Venkateswara University,
space, distance between the multiple targets, reconfigurable Tirupathi, Chittoor district ,Andhra Pradesh , M.Tech degree in Digital
Systems and Computer Electronics Electronics from JNTU Hyderabad ,
systems, channel estimation computation at OFDM based Andhra Pradesh and Doctoral degree received from Sri Venkateswara
Wireless communications, MIMO based video processing University, Tirupathi, Chittoor strict , Andhra Pradesh, India. His area of
systems, etc. low power high speed CORDIC play effective research goes with VLSI Arrays for Signal/Image/Video Processing and
role in future online computations. Communications.

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