Data Sheet: CAN Serial Linked I/O Device (SLIO) With Digital and Analog Port Functions

INTEGRATED CIRCUITS
DATA SHEET
P82C150
CAN Serial Linked I/O device
(SLIO) with digital and analog port
functions
Preliminary specification 1996 Jun 19
Supersedes data of 1995 Oct 11
File under Integrated Circuits, IC18
Philips Semiconductors Preliminary specification
CAN Serial Linked I/O device (SLIO) with

P82C150
digital and analog port functions
CONTENTS
1 FEATURES
2 GENERAL DESCRIPTION
3 ORDERING INFORMATION
4 BLOCK DIAGRAM
5 FUNCTIONAL DIAGRAM
6 PINNING INFORMATION
6.1 Pinning
6.2 Pin description
7 FUNCTIONAL DESCRIPTION
7.1 I/O functions
7.2 I/O registers
7.3 CAN functions
7.4 Initialization
7.5 P82C150 operation after RESET or change of
bus mode
8 LIMITING VALUES
9 DC CHARACTERISTICS
10 AC CHARACTERISTICS
11 APPLICATION INFORMATION
11.1 Maximum bus length
11.2 Start up sequence
11.3 External oscillator mode
11.4 Using digital I/O port functions
11.5 Using DPM
11.6 Using ADC
11.7 Using analog input port functions
11.8 CAN-bus system applications
12 PACKAGE OUTLINE
13 SOLDERING
13.1 Introduction
13.2 Reflow soldering
13.3 Wave soldering
13.4 Repairing soldered joints
14 DEFINITIONS
15 LIFE SUPPORT APPLICATIONS
1996 Jun 19 2

P82C150
1 FEATURES 2 GENERAL DESCRIPTION

• Single-chip I/O device with CAN protocol controller The P82C150 is a single-chip 16-bit I/O device including a
• Meets CAN protocol specification version 2.0 A and B Controller Area Network (CAN) protocol controller with
(passive) with restricted bit timing automatic bit rate detection and calibration. It features 16
configurable I/O port pins with programmable direction,
• Fully integrated clock oscillator (no crystal required)
digital and analog modes.
• 16 configurable digital or analog I/O port pins
The P82C150 provides a configurable event capture
• Each of the port pins individually configurable via facility supporting automatic transmission caused by a
CAN-bus: port direction, port mode and event capture change on the port input pins.
facilities for inputs (event driven or polling)
The clock oscillator requires no external components,
• Up to sixteen digital inputs; automatic transmission of a
thus, the cost of the CAN link is reduced significantly.
CAN message on a change on inputs individually
selectable The P82C150 is a very cost-effective way to increase the
• Up to sixteen 3-state outputs I/O capability of a microcontroller based CAN node as well
as to reduce the amount and complexity of wiring.
• Up to two quasi-analog outputs with 10-bit accuracy Advanced safety is provided by the CAN protocol.
• 10-bit analog-to-digital converter with up to six
Applications:
multiplexed analog input channels (for accuracy see
Section 11.6) • Body electronics and instrumentation in automotive
applications
• Two general purpose comparators
• Bit rate from 20 kbit/s up to 125 kbit/s using internal • Sensor/actuator interface in automotive and general
industrial applications
oscillator
• Automatic bit rate detection and calibration • Extension of I/O capabilities of microcontroller based
CAN nodes.
• Up to sixteen P82C150 nodes for one CAN-bus system
• Four identifier bits programmable
• SLIO functions controlled by a single intelligent node
(‘host’)
• Sleep-mode with wake-up via CAN-bus
• Differential CAN-bus input comparator and CAN-bus
output driver
• Supply voltage: 5 V ±4%
• Operating temperature: two ranges −40 to +85 °C and
−40 to +125 °C.
3 ORDERING INFORMATION
PACKAGE TEMPERATURE
TYPE NUMBER
NAME DESCRIPTION VERSION RANGE (°C)
P82C150 AFT −40 to +85

SO28 plastic small outline package; 28 leads; body width 7.5 mm SOT136-1
P82C150 AHT −40 to +125
1996 Jun 19 3

P82C150
4 BLOCK DIAGRAM
+5 V +5 V P16
handbook, full pagewidth AVDD VDD
18 16 I/O
8 17
port pins
RXO 21 bus mode
OSCILLATOR clock
CAN-bus 9 to 16 P8 to P15
AND
RX1 22 input CALIBRATOR
comparator 5, 6, 7 P5 to P7
PORT
19 LOGIC P2 to P4
REFERENCE 1, 2, 3
REF 1/2 AV
VOLTAGE DD
BIT STREAM TRANSMIT/ I/O 27, 28 P0/CLK, P1

RST 23 RECEIVE
bus mode PROCESSOR LOGIC REGISTERS
TX1 26
ERROR
CAN-bus IDENTIFIER 24 XMOD
MANAGEMENT P82C150
TX0 25 LOGIC LATCH
20 4
AVSS VSS
MHA064
Fig.1 Block diagram.
1996 Jun 19 4

P82C150
5 FUNCTIONAL DIAGRAM
VDD AVDD
handbook, full pagewidth

P16
RX0 ADC feedback output
CAN-bus inputs
RX1
P15 analog-to-digital
reference REF comparator input
voltage output P14 multiplexed analog-
to-digital signal
P13 analog
TX1 input
P12
CAN-bus outputs
comparator
P11 inputs
TX0
P10 DPM1
output
P82C150 P9
P8
16-bit
P7 analog inputs, digital I/O
analog switches
P6
RST (reset)
P5
P4 DPM2
output
P3
P2
identifier
P1 programming
XMOD
P0/CLK
MHA066
VSS AVSS
Fig.2 Functional diagram.
1996 Jun 19 5

P82C150
6 PINNING INFORMATION
6.1 Pinning
handbook, halfpage
P2 1 28 P1
P3 2 27 P0/CLK
P4 3 26 TX1
V 4 25 TX0
SS
P5 5 24 XMOD
P6 6 23 RST
P7 7 22 RX1
P82C150
VDD 8 21 RX0
P8 9 20 AVSS
P9 10 19 REF
P10 11 18 AV
DD
P11 12 17 P16
P12 13 16 P15
P13 14 15 P14
MHA065
Fig.3 Pin configuration.
1996 Jun 19 6

P82C150
6.2 Pin description

Table 1 Pin description for P82C150; SO28; see note 1
SYMBOL PIN DESCRIPTION

P2 1 I/O Ports P2 to P3; Identifier programming input.
P3 2
P4 3 I/O Port 4; DPM2 output.
VSS 4 Ground, digital part (0 V; logic circuits and CAN-bus driver).
P5 5 I/O Ports P5 to P6; analog input.
P6 6
P7 7 I/O Port 7; analog input or analog-to-digital comparator 1 output.
VDD 8 Power supply, digital part (+5 V; logic circuits and CAN-bus driver).
P8 9 I/O Port 8; analog input or comparator 3 output.
P9 10 I/O Port 9; analog input or comparator 2 output.
P10 11 I/O Port 10; comparator 3 inverting input or DPM1 output.
P11 12 I/O Port 11; comparator 3 non-inverting input.
P12 13 I/O Port 12; comparator 2 inverting input.
P13 14 I/O Port 13; comparator 2 non-inverting input.
P14 15 I/O Port 14; multiplexed analog signal.
P15 16 I/O Port 15; analog-to-digital comparator input.
P16 17 Feedback output of analog-to-digital converter.
AVDD 18 Power supply, analog part (+5 V; CAN input, oscillator and reference).
REF 19 Reference voltage output (1⁄2 × AVDD).
AVSS 20 Ground, analog part (0 V; CAN input, oscillator, reference).
RX0 21 CAN-bus input.
RX1 22
RST 23 External reset input (active-HIGH) for internal oscillator mode; pulled to +5 V for external
oscillator mode (see Section 11.3).
XMOD 24 Connected to GND for internal oscillator mode; external reset input (active-LOW) for
external oscillator mode (see Section 11.3).
TX0 25 Open-drain CAN-bus output: dominant = LOW; recessive = floating.
TX1 26 Open-drain CAN-bus output: dominant = HIGH; recessive or at bus mode 2 floating.
P0/CLK 27 I/O Port P0, Identifier programming input in internal oscillator mode; clock input in external
oscillator mode (see Section 11.3).
P1 28 I/O Port P1; identifier programming input.
Note
1. In this documentation the port pins are referred to by their symbols, not by their pin number. For example P15 means
I/O Port 15 at pin 16.
1996 Jun 19 7

P82C150
7 FUNCTIONAL DESCRIPTION Analog-to-digital converted digital results are obtained by

reading the Analog-to-Digital Conversion (ADC) Register.
7.1 I/O functions Analog functions of each port pin are individually
The P82C150 provides 16 port pins (P15 to P0) which are controlled by the Analog Configuration Register.
individually configurable via CAN-bus. Besides the digital Writing the I/O registers is done serially via CAN-bus by
I/O functions some of these port pins provide analog I/O Data Frames. The first data byte contains the register
functions. address, and the second and third data bytes represent
the register contents. If a read only register is addressed,
7.1.1 DIGITAL INPUT FUNCTIONS the contents of the second and third data bytes are
Input levels HIGH and LOW on the port pins (P15 to P0) ignored.
can be read in two ways by the host node: It is recommended to set unused port pins to HIGH
• Polling: a Remote Frame is sent to the P82C150 to be (100 kΩ resistor to VDD).
answered by a Data Frame containing the Data Input
Register contents.
• Event capture: in case of edge-triggered mode, the
P82C150 sends the same Data Frame caused by the
event of a rising and/or falling edge on the
corresponding port pins (see Table 3).
handbook, halfpage
7.1.2 DIGITAL OUTPUT FUNCTIONS Px DIx
The Data Output Register is set via a CAN message.
Its content is only output when the corresponding bits of
the Output Enable Register are set to logic 1s.
DOx
7.1.3 ANALOG INPUT/OUTPUT FUNCTIONS P82C150 3-state buffer
• Up to six multiplexed analog input signals for OEx

MHA068
analog-to-digital conversion or general purpose
• Up to two quasi-analog output channels (DPM;
Distributed Pulse Modulation)
• Two input comparators, for example for window
comparator applications
Fig.4 I/O port pins.
• A separate analog-to-digital input comparator with
feedback output.
1996 Jun 19 8
Table 2 I/O register map
7.2
15 0
14 13 12 11 10 9 8 7 6 5 4 3 2 1
(MSB) (LSB)
1996 Jun 19
ADDRESS 0: DATA INPUT
DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
I/O registers
ADDRESS 1: POSITIVE EDGE

Philips Semiconductors
PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0
ADDRESS 2: NEGATIVE EDGE
NE15 NE14 NE13 NE12 NE11 NE10 NE9 NE8 NE7 NE6 NE5 NE4 NE3 NE2 NE1 NE0
ADDRESS 3: DATA OUTPUT
DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
ADDRESS 4: OUTPUT ENABLE
OE15 OE14 OE13 OE12 OE11 OE10 OE9 OE8 OE7 OE6 OE5 OE4 OE3 OE2 OE1 OE0
ADDRESS 5: ANALOG CONFIGURATION

ADC OC3 OC2 OC1 0 M3 M2 M1 SW3 SW2 SW1 0 0 0 0 0
9
ADDRESS 6: DPM1
DP9 DP8 DP7 DP6 DP5 DP4 DP3 DP2 DP1 DP0 0 0 0 0 0 0
ADDRESS 7: DPM2
DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 0 0 0 0 0 0
ADDRESS 8: ANALOG-TO-DIGITAL CONVERSION (ADC)
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 0 0 0 0 0 0
P82C150
Preliminary specification

P82C150
7.2.1 DATA INPUT REGISTER (ADDRESS 0) 7.2.3 NEGATIVE EDGE REGISTER (ADDRESS 2)
This read only register contains the states of port pins This write only register contains configuration information
P15 to P0 which are transmitted on request, or per port pin for the event capture facility.
automatically by change of one of the input levels, The corresponding NE-bit (see Table 3) has to be set to
provided that the respective input is configured to event logic 1 to enable capturing of the falling edge.
capture mode (see Table 3). When an edge is detected
The combination of PE and NE functions is possible.
the port state is loaded into the transmit buffer after the
Control Field of the triggered message is sent. Therefore a
7.2.4 DATA OUTPUT REGISTER (ADDRESS 3)
delay for input settling is provided. If between edge
detection and transmission of the data input register This write only register contains the output data for the port
another input signal change at the input port occurs, the pins. The output drivers are bitwise enabled by OE
corresponding data input register bit is overwritten by the (see Section 7.2.5). New data for the output port register
current input port value. Additionally the register content is are processed and written to the output ports directly after
sent automatically after wake-up or bus mode change, the corresponding CAN message to the P82C150 is
once the bit time has been calibrated (part of the ‘sign-on’ successfully checked and becomes valid.
message).
7.2.5 OUTPUT ENABLE REGISTER (ADDRESS 4)
7.2.2 POSITIVE EDGE REGISTER (ADDRESS 1)
This write only register controls the output drivers of the
This write only register contains configuration information port pins. The corresponding Output Enable Register bit
per port pin for the event capture facility. has to be set to logic 1 to enable an output driver. If set to
The corresponding PE-bit (see Table 3) has to be set to logic 0, the corresponding output driver is disabled
logic 1 to enable capturing of the rising edge. (floating; see Fig.7).
Table 3 Programming of the I/O registers to event capture on edge or to digital output
X = don’ t care; n = 0 to 15.
REGISTER CONTENTS OF PARTICULAR PORT PIN
FUNCTION POSITIVE EDGE NEGATIVE EDGE OUTPUT ENABLE
(BITS PEn) (BITS NEn) (BITS OEn)
Digital output X X 1
Digital input
Polling X X X
Event capture on edge
Rising 1 0 X
Falling 0 1 X
Rising and Falling 1 1 X
1996 Jun 19 10

P82C150
7.2.6 ANALOG CONFIGURATION REGISTER (ADDRESS 5) 7.2.7 DPM1 REGISTER (ADDRESS 6)

This read/write register contains the bits ADC, OC3 to This write only register contains data for a quasi-analog
OC1, M3 to M1 and SW3 to SW1 (see Fig.7). output signal on port pin P10, which is generated by
• ADC bit (analog-to-digital conversion start bit; write only Distributed Pulse Modulation (DPM; see Fig.9).
bit). The P82C150 starts an analog-to-digital conversion The Output Enable bit must be set for this functions
cycle at ADC = 1 ended with the transmission of a (OE10 = 1). The DPM1 output signal is inverted by setting
message containing the result. After that, the ADC bit is DO10 = 1. The number of output pulses during a DPM
reset automatically. period is given by the DPM1 Register value. These pulses
have 4 × tCLK length and are distributed over the DPM
• OC3 to OC1 bits (comparator output data; read only period. An analog voltage is provided after smoothing the
bits). The bits OC3 to OC1 represent the logical output
output signal by an external RC combination.
level of the analog comparators at input port pins P10,
P11, P12, P13 and P15. The P82C150 sends back the
7.2.8 DPM2 REGISTER (ADDRESS 7)
logical output value of these comparators after having
received a Data Frame (see Section 7.3.3) addressing This write only register contains data for a quasi-analog
the Analog Configuration Register. The comparator output signal on port pin P4. The function of the DPM2
outputs can be monitored at the output port pins P8, P9 corresponds to the definition of DPM1.
and P7.
• M3 to M1 bits (multiplexer control bits; write only bits). 7.2.9 ANALOG-TO- DIGITAL CONVERSION (ADC)
The logical value of the comparators is monitored on REGISTER (ADDRESS 8)
port pins P8, P9 and P7 (see Fig.7) by setting M3 to M1 This read only register contains the result of the
to logic 1, provided that these pins are configured as analog-to-digital converted level of that I/O pin which was
outputs (OE = 1). Additionally the register content is selected by the SW bits. The conversion is started by
sent automatically when the corresponding port bits in ADC-bit set to logic 1 (see Section 7.2.6), or by
the Positive Edge Register and/or Negative Edge transmitting a Data Frame addressing the ADC Register.
Register and the corresponding bits in the Output
Enable Register are set.
• SW3 to SW1 (analog switch control bits; write only bits).
One of the analog switches S1 to S6 can be closed by
setting the switch bits to the corresponding value
(see Fig.7 and Table 4).
Table 4 Analog switch selection by SW3, SW2, SW1.

SW3 SW2 SW1 SWITCH STATE
0 0 0 no switch closed (S0); note 1
0 0 1 S1 closed
0 1 0 S2 closed
0 1 1 S3 closed
1 0 0 S4 closed
1 0 1 S5 closed
1 1 0 S6 closed
1 1 1 reserved
Note
1. Evidently if P14 is driven, it may not be connected to
any other driven pin via the internal analog switches
(avoid short-circuit!).
1996 Jun 19 11

P82C150
ok, full pagewidth P16 17
R2
P15 16
+ ADC
C1 − REGISTER
R1
1/2 V
DD
1/4fCLK
15
P14 OC1
M1
DO7
S0
OE7
7 S1
P7 SW3 to SW1
P82C150
6 S2
P6
OE8
5 S3
P5 M3 DO8
9 S4
P8 M2 DO9
10 S5
P9
OE9
14 S6
P13
+ OC2
13
P12 − OE10
=1 DPM1
12
P11 + DO10 OC3
11
P10 −
OE4
3
P4 =1 DPM2
DO4
MHA067
Fig.5 Analog configuration of I/O port pins; R1, R2 and C1 are used to implement the analog-to-digital converter.
1996 Jun 19 12

P82C150

H
DPM = 0
L
H
DPM = 1
L
4 t CLK
H
DPM = 2
L
H
DPM = 3
L
H
DPM = 512
L
H
DPM = 513
L
H
DPM = 1023
L
t DPM = 1024 x 4 t CLK
MHA081
Distributed Pulse Modulation (DPM) is a special pulse count modulation.
Fig.6 DPM output pulses at DO10(4) = 0; output pulses are inverted at DO10(4) = 1.
1996 Jun 19 13

P82C150
7.3 CAN functions host node to verify that the addressed register has
correctly been written in case of writeable registers, and to
The P82C150 meets the CAN protocol specification
read the contents in case of readable registers.
version 2.0 A and B (passive) with restricted bit timing
because of the on-chip RC-oscillator and the automatic bit
7.3.1 CAN IDENTIFIER
rate detection.
Data and Remote Frames to be processed by the
In a system with P82C150 nodes there must be at least
P82C150 are of Standard Format with 11 Identifier bits
one conventional crystal-driven CAN controller (host node)
ID.10 to ID.0. Frames with extended Identifier (CAN
which is compatible to the CAN specification V1.2 or later
specification version 2.0 B) are ignored.
to control P82C150 nodes. Host nodes compatible to CAN
specification V1.1 can also be used provided that the The way of identifier programming is based on two facts:
P82C150 nodes are powered by a high-accuracy power • Each P82C150 operates with only two Identifiers
supply or they are in external oscillator mode (refer to distinguished by the LSB (see Tables 5, 6 and 7).
Section 11.3). The identifier with the higher priority is used for Data
Each time a P82C150 node receives a Data Frame, it Frame reception. An extra Identifier is used for
initiates the transmission of a Data Frame containing four calibration purposes.
bits status information, the register address (previously • There can be maximum sixteen P82C150 circuits in one
received) and the current contents of the addressed network.
register (exception: see Section 7.3.3.1). This enables the
Table 5 Message types and format

FRAME TRANSMISSION BY 82C150 RECEPTION AT 82C150
Data Frame yes (DLC = 3; DIR = 1) yes (DLC = 3; DIR = 0; calibration message
with DLC = 2 to 8 allowed, see Section 7.3.10)
Remote Frame no yes (DLC = 3; DIR = 1)
Error Frame yes yes
Overload Frame yes (only as a response) yes
Note
1. DLC = Data Length Code; DIR = LSB of Identifier (see Section 7.3.1).
Table 6 Standard Format Identifier bits ID.10 to ID.0

1 = recessive; 0 = dominant
IDENTIFIER
ID.10 ID.9 ID.8 ID.7 ID.6 ID.5 ID.4 ID.3 ID.2 ID.1 ID.0
0 1 P3 1 0 P2 P1 P0 1 0 DIR RTR
Table 7 Description of the Standard Format Identifier bits
BIT SYMBOL DESCRIPTION

ID.8 P3 Programmable identifier bits read from Port pins P3 to P0 during reset. The input levels
ID.5 to ID.3 P2 to P0 on P3 to P0, for example set by resistors to VSS or to VDD, are latched in the Identifier
latch with the falling edge of the RST input signal. They represent the variable part of
the Identifier, while the remaining bits are fixed (mask-programmed), P3 to P0 can be
used as I/O ports after reset.
ID.0 DIR DIR = 1 for transmission of Data Frames to the host. It must be set to a logic 1 in
Remote Frames and to a logic 0 in Data Frames received from the host.
RTR Remote Transmission Request bit.
1996 Jun 19 14

P82C150
7.3.2 TRANSMISSION OF DATA FRAMES 2. ADC Register: On receiving a Data Frame addressing
the ADC Register, the P82C150 starts an
Data Frames transmitted by the P82C150 contain three
analog-to-digital conversion cycle. It automatically
data bytes (see Fig.7). The first data byte contains the
returns the result of the conversion (ADC Register) by
status information and the register address A3 to A0 (see
transmitting a respective Data Frame after finishing
Tables 8 and 9), the other two data bytes contain the
the analog-to-digital conversion cycle.
content of the addressed I/O Register.
3. At normal operation, the calibration messages are
After each successful message transmission, the confirmed by returning a dominant bit in the
P82C150 delays the transmission of a possibly further acknowledge slot. There is no particular confirmation
pending message for three bit times. The reason is to give message returned by the P82C150. Only after
other CAN controllers - with a lower identifier priority - the entering the calibrated state (start-up), a Data Frame
possibility to transmit a message in case of faulty contact (‘sign-on’ message) containing the Data Input Register
at one of the edge-triggered port pins. contents is transmitted indicating to the host node, that
the P82C150 is now ready for transmission.
7.3.3 RECEPTION OF DATA FRAMES AND REMOTE
FRAMES 7.3.3.2 Remote Frame
Received Data Frames have the same format as Received Remote Frames must have the Data Length
transmitted ones, only the DIR-bit (ID.0) in the Arbitration Code DLC = 3 (Remote Frames with DLC ≠ 3 are ignored).
Field is different. The status bits RSTD, EW, BM1 and BM0 It is answered by a Data Frame containing the contents of
are ignored during reception. the Data Input Register.
The P82C150 confirms each reception of a Data Frame by
transmitting a Data Frame containing the (new) contents of
the addressed I/O Register.
7.3.3.1 Exceptions to the rule

1. Analog Configuration Register: If a P82C150 receives
a Data Frame addressing the Analog Configuration
Register and the ADC bit is set to logic 1, it will
respond with two messages. The first message returns
the contents of the Analog Configuration Register. The
control instructions are executed (e.g. next analog
input channel selected), and an analog-to-digital
conversion cycle is started after a set-up time. After
finishing the analog-to-digital conversion cycle, the
second message is transmitted containing the result
(ADC Register).
1996 Jun 19 15

P82C150
Table 8 Data Frame Byte 1

STATUS REGISTER ADDRESS
RSTD EW BM1 BM0 A3 A2 A1 A0
Table 9 Description of Data Frame Byte 1 bits
SYMBOL DESCRIPTION
Status
RSTD It is logic 1 in the first message (‘sign-on’ message) after the successful detection of the bit rate
(bit time calibrated).
EW Logic 1, if the error warning limit (32) is reached. In the “sign-on” message EW is always logic 1. The
EW status bit is set when the Receive Error Counter or the Transmit Error Counter have exceeded the
Error Warning Limit of 32, also temporarily, since the last successful transmission of a message.
BM1 Bus mode status bits.
BM0
Register address
A3 to A0 Register address bits.

SOF ARBITRATION FIELD
ID10 Identifier ID0

0 0 1 P3 1 0 P2 P1 P0 1 0 DIR RTR
CONTROL FIELD BYTE 1
reserved Data Length Code P82C150 status register address
0 0 0 0 1 1 RSTD EW BM1 BM0 A3 A2 A1 A0
BYTE 2 BYTE 3
I/O Register data(15 to 8) I/O Register data(7 to 0)
X X X X X X X X X X X X X X X X
MHA071
SOF: Start Of Frame.

RTR: Remote Transmission Request.
P3 to P0: equals programmed identifier bits.
Fig.7 P82C150 Data Frame.
1996 Jun 19 16

P82C150
7.3.4 CAN-BUS MODES After reset the P82C150 changes directly into bus mode 3
(Sleep Mode). During Sleep Mode, the internal RC
The P82C150 can pass through four CAN-bus modes
oscillator is stopped, and all the output drivers are disabled
under certain conditions (see Fig.8). In the bus modes
(I/O Register contents cleared). A P82C150 in Sleep Mode
0 to 2 (see Table 10) the P82C150 is operating with
can be woken up via CAN-bus lines (dominant level on
different input comparator configurations. Bus mode 3 is
RX0 or RX1) or by a reset condition.
the power reduced Sleep Mode.
The bus modes support:
• Communication on two balanced wires (differential columns
system) DIFFERENTIAL
MODE
• Communication on one wire in a two-wire differential Inputs: RX0, RX1
system Outputs: TX0, TX1
• Sleep Mode with wake-up via either a dominant signal '0'

on RX0 or RX1 input Condition 2
Condition 1
• Connection of a second transmission medium
(redundancy)
SLEEP ONE-WIRE
end of MODE RX1 MODE
There are two possibilities for condition 1 to switch to the RESET
Inputs: RX0, RX1 Input: RX1
next mode (see Fig.8): Outputs: TX0, TX1
Outputs: no
• Overflow of the bit counter when 8192 is reached since '3' '1'
the last calibration message
• Overflow of the Transmit Error Counter (>255; bus-off Condition 1
Condition 1
limit reached).
ONE-WIRE
RX0 MODE
When the bus mode changes, all I/O Registers are cleared
and outputs become floating (OE bits cleared). That Input: RX0
Output: TX0
means the I/O ports return to a fail-safe state whenever the
P82C150 looses connection to its host controller. This is a '2' MHA070
kind of network watchdog function. The status bits are set

Condition 1:
to the following values after a bus mode change: bit counter overflow (>8191) or Transmit Error Counter overflow (>255).
• RSTD = 1 Condition 2:
dominant bit detected on RX0 and RX1.
• EW = 0
• BMnew = BMold + 1. Fig.8 CAN-bus modes and switch-over conditions.
The programmed Identifier bits remain unchanged.
Table 10 Can-bus modes

BITS RECEPTION LEVEL TRANSMISSION
BUS MODE
BM1 BM0 RECESSIVE DOMINANT TX1 TX0
0 = Differential 0 0 RX0 > RX1 RX0 < RX1 enabled enabled
1 = One-wire RX1 0 1 RX1 < REF RX1 > REF enabled enabled
2 = One-wire RX0 1 0 RX0 > REF RX0 < REF disabled enabled
3 = Sleep 1 1 RX0 > REF RX0 < REF disabled disabled
and or
RX1 < REF RX1 > REF
Note
1. Output TX1 is disabled in bus mode 2 to tolerate short-circuit between the CAN-bus wires CAN_H and CAN_L.
1996 Jun 19 17

P82C150
7.3.5 BIT TIMING that bit timing which is provided by the crystal driven host
(calibration message).
The Nominal Bit Time of the P82C150 is subdivided into 10
Time Quanta. The Synchronization Time Segment The usable bus length at a given bit rate is reduced in
(SYNC_SEG) and the Propagation Time Segment comparison to other CAN controllers with programmable
(PROP_SEG) are each one Time Quantum long. The bit timing because the Propagation Time Segment is fixed
Phase Buffer Segment 1 (PHASE_SEG1) and the Phase to 1⁄10 length of the Nominal Bit Time. The bit segmentation
Buffer Segment 2 (PHASE_SEG2) are each four Time of the crystal driven host should be programmed like the
Quanta long. The Resynchronization Jump Width (SJW) is fixed bit segmentation of the P82C150, e.g. one bit time
four Time Quanta long. segment is 1⁄10 length of the Nominal Bit Time (refer also
to Table 15 for bit time programming).
The sample point is located at the end of the Phase Buffer
Segment 1. The Nominal Bit Time is internally adjusted to
Table 11 Bit time subdivision

1 BIT TIME
BT1 BT2 BT3 BT4 BT5 BT6 BT7 BT8 BT9 BT10
SYNC_SEG PROP_SEG PHASE_SEG1 PHASE_SEG2
7.3.6 CAN-BUS TRANSCEIVER The recessive state and the dominant state are not
equivalent and may not be mixed-up.
The transceiver of the P82C150 consists of the
configurable input comparator and of complementary The input comparator is configurable depending on the
open-drain driver outputs. The reference voltage REF is four CAN-bus modes (see Table 10), supporting
an additional output. battery-powered applications (Sleep Mode) and tolerance
against bus wiring failures.
7.3.6.1 CAN-bus input comparator (RX0, RX1)
7.3.6.2 CAN-bus output drivers (TX0, TX1)
The input comparator monitors the transient voltage on
RX1 and RX0. The output driver function is shown in Table 12. The output
driver TX1 is disabled in bus mode 2 to tolerate a
The result of the input comparator is logic 1 if the voltage
short-circuit between the CAN-bus lines in a two-wire
levels of the CAN-bus lines are regarded as recessive, and
differential CAN physical layer.
logic 0 if they are regarded as dominant.
Table 12 CAN-bus driver output function

DOMINANT RESET STATE, BUS-OFF AND
CAN OUTPUT RECESSIVE
MODES 0 AND 1 MODE 2 SLEEP MODE (MODE 3)
TX0 floating LOW LOW floating

TX1 floating HIGH floating floating
1996 Jun 19 18

P82C150
7.3.7 TRANSMIT AND RECEIVE LOGIC From this time on, the bit time is calibrated and fine-tuned
by calibration messages with a special Identifier
The transmit and receive logic stores the destuffed bit
transmitted by the crystal-controlled host.
stream which was received or is about to be transmitted.
The incoming Identifier is compared with that of the Only P82C150 nodes being calibrated by calibration
P82C150. The content of the message is transferred to the messages can transmit messages. The first message is
port logic in case of matching. transmitted directly after entering the calibrated state
(‘sign-on’ message). Since the P82C150 is not able to
At transmission, the message about to be sent is put
transmit as long as the bit time is not calibrated, it cannot
together: the Identifier, the status information, the register
wake-up other CAN nodes via the bus line. Hence to keep
address and the content of the addressed register from the
the network alive, the calibration message must be
port logic.
transmitted regularly by a crystal-controlled (host) node
with a maximum repetition period of 8192 bit (bit length
7.3.8 BIT STREAM PROCESSOR AND ERROR measured by the 82C150). It is recommended to select a
MANAGEMENT LOGIC repetition period between 3800 and maximum 8000 bit
The Bit Stream Processor (BSP) is a sequencer to control times.
the data stream between the transmit/receive logic
(parallel data) and the on-chip CAN transceiver (serial 7.3.10 CALIBRATION MESSAGE
data). Reception/transmission, bit stuffing/destuffing,
The calibration message has to meet the following
arbitration and error detection, according to CAN protocol
requirements
specification version 2.0 A and B (passive), are performed.
Further, automatic re-transmission of corrupted messages • Transmitted by a crystal-controlled node (host node)
is handled by means of continuously comparing the output • Identifier: 000 1010 1010 (1 = recessive; 0 = dominant)
bit stream with the input bit stream. Moreover, the Bit • RTR bit: 0
Stream Processor provides control information to calibrate
the internal bit time. • Allowed control field: DLC = 2 to 8
• The first recessive to dominant transition after the
The Error Management Logic is responsible for the
control field must be followed by another recessive to
complete CAN-inherent error management. dominant transition in a distance of exactly 32 bit (stuff
bits included).
7.3.9 OSCILLATOR AND CALIBRATION
Example of a suitable calibration message (there are
The P82C150 contains an on-chip RC-oscillator. The bit others using different data bytes; see Table 13):
time is automatically calibrated by messages being
received via CAN-bus. During start-up (after wake-up or • Data length code: 0010
reset) any message is used to calibrate the bit time until • 1st data byte: 1010 1010 (AAH)
the calibration is sufficient to receive messages correctly. • 2nd data byte: 0000 0100 (04H).
Table 13 Example of a suitable calibration message

The two important 1/0 transitions are marked by underlines; see note 1.
CONTROL
SOF ARBITRATION FIELD DATA BYTE 1 DATA BYTE 2 CRC FIELD
FIELD
0 000 1010 1010 0 000I010 1010 1010 0000I 0100 000I0 1011 1000 00I0
Note
1. I = stuff bit (recessive); the total length is 67 bit from start-of-frame to end-of-intermission.
1996 Jun 19 19

P82C150
7.4 Initialization After rough calibration the P82C150 can receive any valid
CAN message correctly and executes respective
7.4.1 IDENTIFIER PROGRAMMING commands without giving an acknowledge. With another
Most of the P82C150 identifier bits are fixed. Four bits are valid CAN message and additionally with one valid
programmable via port pins P3 to P0. All output drivers are calibration message the P82C150 is fully calibrated and
disabled at reset, also P3 to P0. Thus the outputs are sends its ‘sign-on’ message. As long as the P82C150 is
floating unless the input level is defined by external fully calibrated the P82C150 acts as an active CAN node.
components to define identifier bits. They are latched at The P82C150 treats any CAN message (including the
the end of reset, and P3 to P0 can be used as port pins. calibration message) as a valid message, when these
It is not allowed, according to the CAN protocol
messages are terminated by an error passive frame
specification, that multiple bus nodes transmit the same because of a missing acknowledge. This situation may
identifier bit combination. Therefore a P82C150 must have
occur whenever a host node works together with
one of the 16 possible identifier bit combinations, one that
P82C150’s and the host node doesn’t receive an
is not yet occupied. acknowledge as long as the P82C150’s are not fully
calibrated.
7.4.2 RESET FUNCTION
RST = HIGH disables all output drivers P16 to P0, TX0 7.4.3.1 Sign-on message
and TX1. All I/O Registers are automatically cleared and This special Data Frame is transmitted once by the
set to logic 0. The bit time is set greater than 50 µs. P82C150 after entering the calibrated state. It indicates to
If a particular clock period is necessary, e.g. for a the host node that the P82C150 is ready for transmission.
dedicated DPM output frequency, this can be achieved by
The sign-on message returns the contents of the Data
feeding an external clock signal into P0. RST and TEST Input Register, and can be recognized by the host mode by
must be permanently HIGH for this special mode. A reset checking the RSTD status bit:
is then performed as usual (RST = HIGH; TEST = LOW).
• Sign-on message RSTD = 1
Table 14 Situation after RESET • Other Data Frames RSTD = 0
STATUS BITS IDENTIFIER BITS Note that in the sign-on message the EW bit is logic 1.
Nevertheless the P82C150 status with the error counters
RSTD = 1 ID.8 equals P3
are set to logic 0.
EW = 1 ID.5 equals P2
BM1 = 0 ID.4 equals P1
BM0 = 0 ID.3 equals P0
7.4.3 BIT TIME CALIBRATION

The P82C150 must receive at least three messages to
calibrate its bit time after reset or change of bus mode.
The first message is used to detect the bit time length
(rough calibration) between two consecutive falling edges
at the output of the CAN input comparator. Therefore the
bit stream should contain a sequence of ‘1010’.
1996 Jun 19 20

P82C150
7.5 P82C150 operation after RESET or change of bus mode

Figure 9 illustrates the calibration procedure of the P82C150 after Power-on-reset or after a bus mode change.
andbook, full pagewidth

end of
Power-on-reset bus mode change e.g. due to
missing reception of a calibration
message within 8192 bit times
ID bits from P0-P3 latched
I/O registers cleared
P82C150 receives 1st message

(any message)
P82C150 is roughly calibrated and has

started bus-off recovery sequence
(counting 129 blocks of 11 recessive bits)
P82C150 receives 2nd message

(any message), acknowledge not
required but no active error flag allowed
Rough calibration verified
P82C150 receives calibration

message within 8192 bit times after
wake-up or bus mode change
P82C150 is fine calibrated

and I/O register cleared
P82C150 waits until bus-off recovery

sequence finished
P82C150 is on bus and ready to

send after bus-of f sequence finished
P82C150 sends 'sign-on' message
Communication with host node possible

MHA080
Fig.9 SLIO operation flow after reset and bus mode change.
1996 Jun 19 21

P82C150
8 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER MIN. MAX. UNIT
VDD supply voltage on VDD pin −0.5 +6.5 V
VI DC input voltage on any pin −0.5 VDD + 0.5 V
(RX0, RX1, TX0, TX1 excluded)
II RX1 and RX0 input current − ±2 mA
IREF reference output current − ±2 mA
IO port output current at port enabled (pins P0 to P15) − ±5 mA
port output current at analog switch enabled − 7.5 mA
(OE-bits = 0; pins P5 to P9, P13, P14)
TX0 and TX1 output current − 30 mA
POtot total power dissipation (port outputs together) − 200 mW
Tamb operating ambient temperature range: −40 +125 °C
Tstg storage temperature range −65 +150 °C
Ptot total power dissipation − 1 W
1996 Jun 19 22

P82C150
9 DC CHARACTERISTICS
VDD = 5 V ± 4%; VSS = 0 V; Tamb = −40 to +85 °C and Tamb = −40 to +125 °C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

Supply
VDD supply voltage note 1 4.8 5.2 V
IDD operating supply current VRST = VDD; all port inputs − 22 mA
connected via 1 MΩ to GND
IDD(SM) supply current Sleep mode Ports P15, P13 and P11 1 mA
connected to VDD;
Ports P12 and P10
connected to VSS;
all other port inputs
connected via 1 MΩ to GND
CAN Input comparators RX0 and RX1
VDIF differential input voltage 0.3AVDD < VI < 0.7AVDD; ±100 − mV
VHYST input voltage hysteresis note 2 8 60 mV
II input current 0.45 V < VI < VDD − 0.45 V − ±400 nA
CAN output driver TX0 and TX1; port pins P0 to P16 unloaded
VOLT TX0 output voltage LOW; IOLT = 1.5 mA − 0.1 V
note 3 IOLT = 10 mA 1.0 V
VOHT TX1 output voltage HIGH; IOHT = −1.5 mA VDD − 0.1 − V
note 4 IOHT = −10 mA VDD − 1.0 V
Reference voltage REF
VREF reference output voltage IO < ±75 µA 0.5AVDD − 0.25 0.5AVDD + 0.25 V
Control inputs RST, XMOD and digital port inputs P0/CLK, P1 to P15
VIL input voltage LOW − 0.2VDD V
VIH input voltage HIGH 0.7VDD − V
VHYST input voltage hysteresis note 2 0.5 − V
IIL1 input leakage current 0.45 V < VI < VDD − 0.45 V ±10 µA
Digital port outputs P0/CLK, P1 to P16; OE bits set
VOL output voltage LOW IOL = 4mA (sink) − 1.0 V
VOH output voltage HIGH IOH = −4mA (source) VDD − 1.0 − V
OC2 comparator P12, P13 and OC3 comparator P10, P11
VDIF1 differential input voltage 1.5 V < VI < (AVDD − 1.5 V); ±20 − mV
note 2
1996 Jun 19 23

P82C150

OC1 comparator input P15
Vi sw input switch-over voltage 1.5 V < VI < (AVDD − 1.5 V);
lower threshold note 2 0.5VDD − 0.02 V
upper threshold − 0.5VDD + 0.02 V
ILI2 input leakage current 0.45 V < VI < VDD − 0.45 V − ±400 nA
CIA analog input capacitance note 2 − 20 pF
Analog switches; ION = ±4 mA
RON On resistance between P5 to P9, P13 and 20 200 Ω
P14; note 2
Notes to the DC characteristics:
1. Alteration of VDD between two calibration messages should not exceed 0.2 V to avoid failures during CAN
message transfer. If CAN devices according to CAN specification V1.0 or V1.1 (like the 82C200 V0 or V1) are in the
same network with the 82C150, then this alteration of VDD should be limited to 0.1V for the 82C150.
2. These values are characterized but not 100% production tested.
3. The TX0 output pin is an open drain pull-down driver (no pull-up driver included).
4. The TX1 output pin is an open drain pull-up driver (no pull-down driver included).
10 AC CHARACTERISTICS
VDD = 5 V ± 4%; VSS = 0 V; CL = 100 pF (output pins); Tamb = −40 to +85 °C and Tamb = −40 to +125 °C; unless
otherwise specified.
fCLK_INT system clock frequency on-chip internal oscillator 4 10 MHz
tbit bit time on CAN-bus note 1 8 50 µs
tRST1 min. RST pulse width after power on note 2 150 − ms
tRST2 min. RST pulse width during operation note 2 1 − µs
thold ID hold time after end of reset note 2 100 − ns
td total signal delay of CAN input comparator and 0.3AVDD < VI < 0.7AVDD; − 100 ns
CAN output driver note 2
trep max. time without recalibration message − 8000 bit
Analog-to-digital comparator input P15
tcyc analog-to-digital conversion cycle time 0.4 1.1 ms
tinit initialization time of analog-to-digital conversion 0.4 2.1 ms
OC2 comparator P12, P13 and OC3 comparator P10, P11
tresp response time VDIF1 = ±100 mV; note 2 1 µs
DPM1 and DPM2 outputs
tDPM repetition time of DPM cycle 0.4 1.1 ms
Notes
1. Other bit time values are possible with the external oscillator mode (refer to Chapter 11.3).
2. These values are characterized but not 100% production tested.
1996 Jun 19 24

P82C150
11 APPLICATION INFORMATION 11.1.1 ASSUMPTIONS

11.1 Maximum bus length • The total in/out delay of external transceiver circuit is
less than 180 ns (e.g. PCA82C250 CAN transceiver;
The bit timing parameters refer to using a P8xCE598 or
see Fig.20).
P8xC592 microcontroller with on-chip CAN interface as a
host node (see Fig.20). • The propagation delay on the transmission medium is
5.0 ns/m.
Table 15 Maximum bus length for CAN-bus systems with P82C150 nodes.
INDICATION BIT TIMING (P8xCE598/P8xC592)
BIT RATE tprop(1) FOR MAXIMUM
(kbit/s) (µs) BUS LENGTH fCLK
BTR0(2) BTR1(2)
(m) (MHz)
125 0.8 25 15 C5H 34H

100 1 45 16 C7H 34H
50 2 145 16 CFH 34H
20 5 445 16 E7H 34H
Notes
1. tprop is the maximum propagation delay between two CAN-bus nodes (delays of on- and off-chip transceiver circuits
included).
2. BTR0 and BTR1 (hex values) are particular configuration registers referring to bit timing.
11.2 Start up sequence

The following start-up sequence, illustrated by
Figures 10 and 11, shows a simple example how handbook, halfpage
Power-on
P82C150 nodes can be controlled from a host node. This
application example works with different system
Initialization of host node's CAN controller
configurations:
• One conventional crystal-controlled CAN node and one
or more P82C150 nodes. Wait until all P82C150 nodes are assumed
to have finished Power-on-reset
• More than one conventional crystal-controlled CAN
node and one or more P82C150 nodes.
Start-up bit time calibration procedure
(1)
Periodic calibration
(transmit calibration message with a
repetition period of maximum 8000 bit times)
MHA077
(1) See Fig.11.
Fig.10 General start-up procedure for CAN-bus

systems with P82C150 nodes.
1996 Jun 19 25

P82C150
Load calibration message

into transmit buf fer
j := 18
if else
'Transmit Status' = 0(1)
then
Set bit 'Transmission Request' (CMR.0) in Command Register
'0'
if else
'Transmit Status' = 1(1)
then
Set bit 'Abort Transmission' (CMR.1) in Command Register
j : = j −1
else
if j = 0
then
Wait for reception of sign-on message

from P82C150 nodes
from now onwards transmit calibration message

periodically with a recommended repetition
period between 3800 and 8000 bit times
MHA079
(1) Bit SR.5 in Status Register.
Fig.11 P82C150 start-up bit time calibration procedure for host node (P8xC592, P8xCE598 or P82C200).
1996 Jun 19 26

P82C150
11.3 External oscillator mode

In this mode the P82C150 operates with an external clock +5 V
instead with the on-chip RC-oscillator. Figure 14 shows
the application with an external clock.
P82C150
In this mode the P82C150 can achieve bit rates below digital
20 kbit/s and above 125 kbit/s. The DPM pulse width is input P0 to P15
4 × tCLK of the external clock. The corresponding CAN
identifier bit at Port P0 is set to a logic 0. Therefore only
eight P82C150 based CAN nodes operate within the same
network in external oscillator mode. MHA072
11.3.1 NOTE
Fig.12 Example for digital input application.
The external oscillator mode is not the normal operation
mode.
11.4 Using digital I/O port functions

Figures 12 and 13, show the principle application for
digital input and output. P82C150
digital
11.5 Using DPM output
P0 to P15
The simplest way to generate an analog voltage using the
P82C150 is to apply an external low pass filter at one of
the DPM (Distributed Pulse Modulation) outputs. The
MHA073
simplest implementation concept is a RC-filter of the first
order (refer to Fig.15). Regarding the selection of the time
constant (edge frequency) of this filter, a trade-off between
minimizing of the ripple voltage for maximum accuracy and Fig.13 Example for digital output application.
minimum of the settling time has to be considered.
V V
handbook, halfpage P82C150

clock t t
P0/CLK
analog DPM1(2)
output P10(P4)
reset
XMOD P82C150
+5 V
RST
MHA074
MHA078
If the output is loaded by a resistive load, this will decrease the

accuracy due to the voltage drop across the series resistor. In these
cases a low value for the series resistor should be chosen.
The repetition time of one DPM cycle can be derived from:
4096
t CYC = -------------
f OSC
Fig.14 P82C150 in external oscillator mode. Fig.15 Example for DPM application.
1996 Jun 19 27

P82C150
11.6 Using ADC 11.7 Using analog input port functions

The application in Fig.16 can be used for analog-to-digital Figure 18 shows the wide range of analog input
conversion for only one analog input signal. The applications:
evaluation of ADC were done with the values • Comparison of two analog input signals.
R1 = R2 = 100 kΩ and C = 3.3 nF; under these conditions
• Comparison of one analog input signal against a fixed
the ADC may reach an accuracy of 7 to 8 bit (depends on
threshold.
application). The external components should be
connected close to the port pins P15 and P16 with short • Window comparator including monitoring the
wiring to avoid disturbances at the analog input comparator outputs at the port pins P8 and P9;
port pin P15. additional automatically generated messages, when the
corresponding port bits in the Negative Edge and/or
Using the on-chip multiplex function the P82C150 provides
Positive Edge register are set.
up to six input port pins to convert analog input signals to
digital values (see Fig.17). • Local control two-step system.
The period for one ADC cycle is identical to the length of

one DPM cycle.
handbook, halfpage
P15
P82C150
handbook, halfpage
P16 P16
feedback
one analog input signal
analog signal P14
for A/D conversion R1
P82C150 V
R2
P15
P5 SW3 to
C SW1
t
V
MHA076
P6
t
MHA075
Fig.17 Two multiplexed analog input signals

switched for analog-to-digital conversion
Fig.16 ADC implementation. (maximum 6 signals; see Fig.5).
1996 Jun 19 28

P82C150
V
dbook, full pagewidth
P82C150
comparison between two P11 (P13)

t
analog input signals OC3 (OC2)
V P10 (P12)
V
P82C150
message transmission
when analog input signal P11 (P13)
exceeds threshold voltage t
+5 V threshold P10 (P12) DO8 (DO9)
M3 (M2)
comparator
OE8 (OE9)
P8 (P9) DI8 (DI9)
output enabled and edge-triggered mode (PE and/or NE set)

+5 V
message transmission
when analog input signal
P82C150
exceeds upper respectively
lower threshold voltage P11
upper
(window comparator)
threshold
P10 DO8
M3
V
comparators OE8
sensor P13
signal
t P12 DO9
lower
M2
threshold
V OE9
P9
DI9
t output enabled and edge-triggered
V mode (PE and/or NE set)
P8
DI8
output enabled and edge-triggered
mode (PE and/or NE set)
t
V
P82C150
sensor
local two-step control signal
system P11 (P13)
t
DO8 (DO9)
+5 V threshold P10 (P12)
M3 (M2)
V comparator
OE8 (OE9)
t to actuator P8 (P9) DI8 (DI9)
output enabled
MHA082
Fig.18 Examples of comparator applications.
1996 Jun 19 29

P82C150
handbook, full pagewidth V bat V bat
linear
control
on/off with angle
control LOAD status LOAD measurement
feedback
D S D S
BUK101-50GS BUK105-50S KM110BH/21-90
I P F I VS Vo GND
+5 V +5 V
10 kΩ
+5 V V
DD PV Px Py Pz Pw
(digital out) (digital out) (DPM) (analog in)
(digital in)
V
RST SS
P82C150
RX0 REF RX1 TX0 TX1
MHA083
Fig.19 Examples of TOPFET applications with P82C150.
1996 Jun 19 30
11.8
1996 Jun 19
motor lamp analog digital
sensor
M
Philips Semiconductors
TOPFET (1) TOPFET

CAN-bus system applications
XTAL1
P8xC592 / P8xCE598
CAN-CONTROLLER
P82C150
XTAL2
CTX0 CRX0 CRX1 Px,y TX0 RX0 TX1 RX1
560 Ω 3.6 kΩ 6.8 kΩ

+5 V +5 V
31
Rext = 0
TxD RxD Vref Rs TxD RxD Vref Rs
PCA82C250 PCA82C250
CANH CANL CANH CANL
124 Ω CAN BUS 124 Ω

LINE
MHA069
(1) TOPFET = temperature and Overload-Protected Field-Effect-Transistor

Fig.20 P82C150 system application using CAN transceiver PCA82C250 (ISO/DIS 11898 standard).
P82C150
Preliminary specification

P82C150
12 PACKAGE OUTLINE
SO28: plastic small outline package; 28 leads; body width 7.5 mm SOT136-1
D E A
y HE v M A
28 15
Q
A2 A
A1 (A 3)
pin 1 index
θ
Lp
L
1 14 detail X
e w M
bp
0 5 10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z
(1)
θ
0.30 2.45 0.49 0.32 18.1 7.6 10.65 1.1 1.1 0.9
mm 2.65 0.25 1.27 1.4 0.25 0.25 0.1
0.10 2.25 0.36 0.23 17.7 7.4 10.00 0.4 1.0 0.4 8o
0.012 0.096 0.019 0.013 0.71 0.30 0.42 0.043 0.043 0.035 0o
inches 0.10 0.01 0.050 0.055 0.01 0.01 0.004
0.004 0.089 0.014 0.009 0.69 0.29 0.39 0.016 0.039 0.016
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION
91-08-13
SOT136-1 075E06 MS-013AE
95-01-24
1996 Jun 19 32

P82C150
13 SOLDERING During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be
13.1 Introduction applied by screen printing, pin transfer or syringe
There is no soldering method that is ideal for all IC dispensing. The package can be soldered after the
packages. Wave soldering is often preferred when adhesive is cured.
through-hole and surface mounted components are mixed Maximum permissible solder temperature is 260 °C, and
on one printed-circuit board. However, wave soldering is maximum duration of package immersion in solder is
not always suitable for surface mounted ICs, or for 10 seconds, if cooled to less than 150 °C within
printed-circuits with high population densities. In these 6 seconds. Typical dwell time is 4 seconds at 250 °C.
cases reflow soldering is often used.
A mildly-activated flux will eliminate the need for removal
This text gives a very brief insight to a complex technology. of corrosive residues in most applications.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
13.4 Repairing soldered joints
13.2 Reflow soldering Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
Reflow soldering techniques are suitable for all SO
(less than 24 V) applied to the flat part of the lead. Contact
packages. time must be limited to 10 seconds at up to 300 °C. When
Reflow soldering requires solder paste (a suspension of using a dedicated tool, all other leads can be soldered in
fine solder particles, flux and binding agent) to be applied one operation within 2 to 5 seconds at between 270 and
to the printed-circuit board by screen printing, stencilling or 320 °C
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from 215 to
250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
13.3 Wave soldering

Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream end.
1996 Jun 19 33

P82C150
14 DEFINITIONS
Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
15 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1996 Jun 19 34

P82C150
NOTES
1996 Jun 19 35
Philips Semiconductors – a worldwide company
Argentina: see South America Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
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Printed in The Netherlands 617021/1200/02/pp36 Date of release: 1996 Jun 19 Document order number: 9397 750 00918

Data Sheet: CAN Serial Linked I/O Device (SLIO) With Digital and Analog Port Functions

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Data Sheet: CAN Serial Linked I/O Device (SLIO) With Digital and Analog Port Functions

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INTEGRATED CIRCUITS

CAN Serial Linked I/O device (SLIO) with

CAN Serial Linked I/O device (SLIO) with

1 FEATURES 2 GENERAL DESCRIPTION

P82C150 AFT −40 to +85

CAN Serial Linked I/O device (SLIO) with

BIT STREAM TRANSMIT/ I/O 27, 28 P0/CLK, P1

Fig.1 Block diagram.

CAN Serial Linked I/O device (SLIO) with

handbook, full pagewidth

Fig.2 Functional diagram.

CAN Serial Linked I/O device (SLIO) with

Fig.3 Pin configuration.

CAN Serial Linked I/O device (SLIO) with

6.2 Pin description

SYMBOL PIN DESCRIPTION

CAN Serial Linked I/O device (SLIO) with

7 FUNCTIONAL DESCRIPTION Analog-to-digital converted digital results are obtained by

7.1.3 ANALOG INPUT/OUTPUT FUNCTIONS P82C150 3-state buffer

• Up to six multiplexed analog input signals for OEx

ADDRESS 1: POSITIVE EDGE

ADDRESS 5: ANALOG CONFIGURATION

CAN Serial Linked I/O device (SLIO) with

CAN Serial Linked I/O device (SLIO) with

7.2.6 ANALOG CONFIGURATION REGISTER (ADDRESS 5) 7.2.7 DPM1 REGISTER (ADDRESS 6)

Table 4 Analog switch selection by SW3, SW2, SW1.

CAN Serial Linked I/O device (SLIO) with

ok, full pagewidth P16 17

CAN Serial Linked I/O device (SLIO) with

handbook, full pagewidth

Distributed Pulse Modulation (DPM) is a special pulse count modulation.

CAN Serial Linked I/O device (SLIO) with

Table 5 Message types and format

Table 6 Standard Format Identifier bits ID.10 to ID.0

Table 7 Description of the Standard Format Identifier bits

BIT SYMBOL DESCRIPTION

CAN Serial Linked I/O device (SLIO) with

7.3.3.1 Exceptions to the rule

CAN Serial Linked I/O device (SLIO) with

Table 8 Data Frame Byte 1

Table 9 Description of Data Frame Byte 1 bits

handbook, full pagewidth

ID10 Identifier ID0

CONTROL FIELD BYTE 1

reserved Data Length Code P82C150 status register address

0 0 0 0 1 1 RSTD EW BM1 BM0 A3 A2 A1 A0

I/O Register data(15 to 8) I/O Register data(7 to 0)

SOF: Start Of Frame.

Fig.7 P82C150 Data Frame.

CAN Serial Linked I/O device (SLIO) with

• Sleep Mode with wake-up via either a dominant signal '0'

kind of network watchdog function. The status bits are set

The programmed Identifier bits remain unchanged.

Table 10 Can-bus modes

CAN Serial Linked I/O device (SLIO) with

Table 11 Bit time subdivision

Table 12 CAN-bus driver output function

TX0 floating LOW LOW floating

CAN Serial Linked I/O device (SLIO) with