Class Notes Course Objectives, Plans, and Lab Tools: Computer Organization Laboratory
Class Notes Course Objectives, Plans, and Lab Tools: Computer Organization Laboratory
Class Notes Course Objectives, Plans, and Lab Tools: Computer Organization Laboratory
Class Notes
Course Objectives, Plans, and
Lab Tools
Instructor: Ken Q. Yang
Dept. of ECE, URI
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Option 2 Pope’s
Inauguration
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Source : http://www.alternet.org/speakeasy/alyssa-figueroa/recording-memories-why-must-we-capture-our-every-moment
Era of Internet and Cloud
All Boil Down to One Thing
Computer
A Very Large Fraction: Embedded Computers and Systems
– End user devices
– Variety of appliances
– Network cores
– Consumer Electronics
– More and more
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*Source: Intel 2012
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What is Cortex™-M
CORTEX M-4
• Harvard Architecture
• 3 stage pipeline
• Single cycle multiply
• Hardware Divide
• Thumb-2 Instruction Set
• Vectored Interrupt
Controller
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Register Sets 2
Programmers Model 1
Low registers
Registers R0-R7 are accessible by all instructions that specify a general-purpose register.
High registers
Registers R8-R12 are accessible by all 32-bit instructions that specify a general-purpose register.
Registers R8-R12 are not accessible by any 16-bit instructions.
Registers R13, R14, and R15 have the following special functions:
Stack pointer
Register R13 is used as the Stack Pointer (SP). Because the SP ignores writes to bits [1:0], it is auto aligned
to a word, four-byte boundary.
Handler mode always uses SP_main, but you can configure Thread mode to use either SP_main or
SP_process.
Link register
Register R14 is the subroutine Link Register (LR).
The LR receives the return address from PC when a Branch and Link (BL) or Branch and Link with
• APSR – Application process status register
Exchange (BLX) instruction is executed.
The LR is also used for exception return.
• IPSR – Interrupt process status register
At all other times, you can treat R14 as a general-purpose register.
Program counter
• EPSR – Execution process status register
Register R15 is the Program Counter (PC).
Bit [0] is always 0, so instructions are always aligned to word or half word boundaries.
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