Hard wired and Micro programmed
Control Units
In H/wired, control signals are generated by a
micro instructions are used cause register
transfers and ALU operations
In Micro programmed control unit, the control
unit is specified by a micro program
Basic Idea
For each micro operation control unit has to generate set of
control signals and each control line is either ON or OFF
We can assume each control line by a binary digit.
A Control word is then formed by these bits
Then each micro operation would be represented by a different
Then each control word are saved in memory with unique
address.
Also add an address field to indicate the location of next
control word to be executed(also add few bits about the
conditions).
How can we use the concept of
microprogramming to implement a control
unit?
Consider that for each micro-operation, all that the control unit
is allowed to do is generate a set of control signals.
Thus, for any micro-operation, each control line emanating
from the control unit is either on or off. This condition can, of
course, be represented by a binary digit for each control line.
So we could construct a control word in which each bit
represents one control line. Then each micro-operation would
be represented by a different pattern of 1s and 0s in the control
word
Microinstruction address
Jump condition
System bus control signals
Internal CPU control signals
(a) Horizontal microinstruction
Microinstruction address
Jump condition
Function codes
(b) Vertical microinstruction
Figure 21.1 Typical Microinstruction Formats
Horizontal Micro instruction
Horizontal Vs. vertical Micro
instruction
In a horizontal microinstruction, every bit in
control field is attached to a control line.
In vertical microinstruction, a code is used to
each action to be performed and the decoder
translates the code into individual control
signals.
Table 21.1
Machine Instruction Set for Wilkes Example
Order Effect of Order
An C(Acc) + C(n) to Acc1
Sn C(Acc) C(n) to Acc1
Hn C(n) to Acc2
Vn C(Acc2) C(n) to Acc, where C(n) 0
Tn C(Acc1) to n, 0 to Acc
Un C(Acc1) to n
Rn C(Acc) 2 (n+1) to Acc
Ln C(Acc) 2n+1 to Acc
Gn IF C(Acc) < 0, transfer control to n; if C(Acc) 0, ignore (i.e., proceed serially)
In Read next character on input mechanism into n
On Send C(n) to output mechanism
Notation: Acc = accumulator
Acc1 = most significant half of accumulator
Acc2 = least significant half of accumulator
n = storage location n
C(X) = contents of X (X = register or storage location)
Microprogramming
This notation looks suspiciously like a programming
language. In fact it is a language, known as a
microprogramming language.
Each line describes a set of micro-operations occurring
at one time and is known as a microinstruction.
A sequence of instructions is known as a
microprogram, or firmware. This latter term reflects
the fact that a microprogram is midway between
hardware and software.
It is easier to design in firmware than hardware, but it is
more difficult to write a firmware program than a
software program.
Terminology
All the micro-operations are converted in the form of
control signals and they are stored in control memory
as a program. This program is called as microprogram.
Microprogram is written for every operation like Fetch,
Decode and execute and these are called as routines.
Routines are stored in control memory (which is
inside the control unit).
The hardware consists address sequence that must be
capable of branching not only within the routine but
also in the other routines.
Fetch
cycle
routine
Jump to indirect or execute
Indirect
cycle
routine
Jump to execute
Interrupt
cycle
routine
Jump to fetch
Jump to opcode routine Execute cycle beginning
AND routine
Jump to fetch or interrupt
ADD routine
Jump to fetch or interrupt
Jump to fetch or interrupt
IOF routine
Figure 21.2 Organization of Contr ol Memory
Operation of control unit
microarchitecture
The set of microinstructions is stored in the control memory.
The control address register contains the address of the next
microinstruction to be read.
When a microinstruction is read from the control memory, it
is transferred to a control buffer register.
The left-hand portion of that register (see Figure) connects
to the control lines emanating from the control unit.
Thus, reading a microinstruction from the control memory
is the same as executing that microinstruction.
The third element shown in the figure is a sequencing unit
that loads the control address register and issues a read
command.
Control Address Register
Sequencing
Logic
Read
Control
Memory
Control Buffer Register
Figure 21.3 Control Unit Microarchitecture
Function of control unit
Sequencing sub-steps
Instruction Register
Control
Unit Decoder
ALU
Control Address Register
Flags Sequencing
Clock Logic
Read
Control
Memory
Control Buffer Register
Next Address Control
Decoder
Control Signals Control Signals
Within CPU to System Bus
Figure 21.4 Functioning of Microprogrammed Control Unit
Function of two decoders
Figure shows two modules labeled decoder.
The upper decoder translates the opcode of the IR
into a control memory address.
The lower decoder is not used for horizontal
microinstructions but is used for vertical
microinstructions .
The advantage of vertical microinstructions is that
they are more compact (fewer bits) than
horizontal microinstructions, at the expense of a
small additional amount of logic and time delay
control unit
As was mentioned, Wilkes first proposed the
use of a microprogrammed control unit in
1951.
This proposal was subsequently elaborated
into a more detailed design. It is instructive to
examine this seminal proposal.
The configuration proposed by Wilkes is
depicted in next slide.
from
instruction
register
Register II
Clock
Register I
Control Address
signals decoder
Conditional
signal
Control signals
Figure 21.5 Wilkes's Microprogrammed Control Unit
control unit
The heart of the system is a matrix partially filled with diodes.
During a machine cycle, one row of the matrix is activated
with a pulse. This generates signals at those points where a
diode is present (indicated by a dot in the diagram).
The first part of the row generates the control signals that
control the operation of the processor.
The second part generates the address of the row to be pulsed
in the next machine cycle.
Thus, each row of the matrix is one microinstruction, and the
layout of the matrix is the control memory.
Operation of control unit
At the beginning of the cycle, the address of the row to be pulsed is
contained in Register I. This address is the input to the decoder, which,
when activated by a clock pulse, activates one row of the matrix.
Depending on the control signals, either the opcode in the instruction
register or the second part of the pulsed row is passed into Register II
during the cycle. Register II is then gated to Register I by a clock pulse.
Alternating clock pulses are used to activate a row of the matrix and to
transfer from Register II to Register I.
The two-register arrangement is needed because the decoder is simply a
combinatorial circuit; with only one register, the output would become the
input during a cycle, causing an unstable condition.
control unit-Horizontal or ??
This scheme is very similar to the horizontal
microprogramming approach described earlier.
The main difference is this: In the previous
description, the control address register could be
incremented by one to get the next address. In the
Wilkes scheme, the next address is contained in
the microinstruction.
To permit branching, a row must contain two
address parts, controlled by a conditional signal
(e.g., flag), as shown in the figure.
Microinstruction Sequencing
The two basic tasks performed by a microprogrammed control unit
are:
Microinstruction sequencing
o Get the next microinstruction from the control memory
Microinstruction execution
o Generate the control signals needed to execute the
microinstruction
o In designing a control unit, these tasks must be considered
together because both affect the format of the microinstruction and
the timing of the control unit
Design Considerations
Two concerns are involved in the design In executing a microprogram the address
of a microinstruction sequencing of the next microinstruction to be
technique: executed is in one of these categories:
The size of the microinstruction Determined by instruction register
Minimizing the size of the control memory Occurs only once per instruction cycle, just
reduces the cost of that component after an instruction is fetched
The address-generation time Next sequential address
Execute microinstruction as fast as possible Most common in most designs
Branch
Are a necessary part of a microprogram
Microinstruction sequencing
techniques
Based on the current micro instruction,
condition flags, and contents of instruction
register a control memory address is generated
for next instruction.
Based on the format of the address information
in the micro instruction it is classified in to
- Two address field
- Single address field and
- Variable format
control address
register
address
decoder
control
memory
address address control
control buffer
1 2
register
address
branch selection
flags multiplexer instruction
logic
register
Figure 21.6 Branch Control Logic: Two Address Fields
address
decoder
control
memory
control
control address
buffer control address +1
register
register
branch
flags multiplexer instruction
logic
address register
selection
Figure 21.7 Branch Control Logic: Single Address Field
address
decoder
control
memory
control
buffer
register control address
branch entire +1
control register
field
field address
field
gate and
function
logic
branch multiplexer instruction
logic address register
flags
selection
Figure 21.8 Branch Control Logic: Variable Format
Field Field Field
Decode Decode Decode
logic logic logic
Control signals
(a) Direct encoding
Field Field Field
Decode Decode Decode
logic logic logic
Decode
logic
Control signals
(b) Indirect encoding
Figure 21.11 Microinstruction Encoding
LSI-11 Microinstruction Sequencing
LSI-11 is a microcomputer version of a PDP-11, with the main
components of the system residing on a single board
The LSI-11 is implemented using a microprogrammed control unit
Makes use of a 22-bit microinstruction and a control memory of 2K
22-bit words
The next microinstruction address is determined in one of five ways:
Next sequential address
Opcode mapping
Subroutine facility
Interrupt testing
Branch
4 1 1 16
Special
Encoded micro-operations
functions
Load return register
Translate
(a) Format of the full LSI-11 microinstruction
5 11 4 8 4
Opcode Jump address Opcode Literal value A register
Unconditional jump microinstruction format Literal microinstruction format
4 4 8 8 4 4
Opcode Test code Jump address Opcode B register A register
Conditional jump microinstruction format Register jump microinstruction format
(b) Format of the encoded part of the LSI-1 1 microinstruction
Figure 21.15 LSI-11 Microinstruction Format
Table 21.5
Some LSI-11 Microinstructions
Arithmetic Operations General Operations
Add word (byte, literal) MOV word (byte)
Test word (byte, literal) Jump
Increment word (byte) by 1 Return
Increment word (byte) by 2 Conditional jump
Negate word (byte) Set (reset) flags
Conditionally increment (decrement) byte Load G low
Conditionally add word (byte) Conditionally MOV word (byte)
Add word (byte) with carry
Conditionally add digits Input/Output Operations
Subtract word (byte) Input word (byte)
Compare word (byte, literal) Input status word (byte)
Subtract word (byte) with carry Read
Decrement word (byte) by 1 Write
Read (write) and increment word (byte) by 1
Logical Operations Read (write) and increment word (byte) by 2
AND word (byte, literal) Read (write) acknowledge
Test word (byte) Output word (byte, status)
OR word (byte)
Exclusive-OR word (byte)
Bit clear word (byte)
Shift word (byte) right (left) with (without)
carry
Complement word (byte)
Control
store
11
22
22 Microinstruction
bus
18 16
Control Data
chip chip
With no number indicated,
4 a path with multiple signals
16
Bus control
and other Bus logic
procesor
board logic
LSI-11 system
bus
Figure 21.13 Simplified Block Diagram of the LSI-11 Processor
Control data register
Control
store
Control address register
Microprogram
sequence
control
Return register
Translation
array INT
Instruction register
Figure 21.14 Organization of the LSI-11 Control Unit
0 35
P AA AB AC AD AE AF AG AH AJ AK AL
A, B, C, D registers Arithmetic Shift
36 71
P BA BB BC BD BE BF BH
Next address Storage address
72 107
P BH CA CB CC CD CE CF CG CH
Shift control Local storage Miscellaneous controls
Storage address
108 125
P DA DB DC DD DE
Testing and condition code setting
Figure 21.16 IBM 3033 Microinstruction Format
ALU Control Fields
AA(3) Load A register from one of data registers
AB(3) Load B register from one of data registers
AC(3) Load C register from one of data registers
AD(3) Load D register from one of data registers
AE(4) Route specified A bits to ALU
AF(4)
AG(5)
Route specified B bits to ALU
Specifies ALU arithmetic operation on A input
Table 21.6
AH(4) Specifies ALU arithmetic operation on B input
AJ(1) Specifies D or B input to ALU on B side
AK(4) Route arithmetic output to shifter
IBM 3033 Microinstruction
CA(3) Load F register
Control
CB(1) Activate shifter Fields
CC(5) Specifies logical and carry functions
CE(7) Specifies shift amount
Sequencing and Branching Fields
AL(1) End operation and perform branch
BA(8) Set high-order bits (00 07) of control address register
BB(4) Specifies condition for setting bit 8 of control address register
BC(4) Specifies condition for setting bit 9 of control address register
BD(4) Specifies condition for setting bit 10 of control address register
BE(4) Specifies condition for setting bit 11 of control address register
BF(7) Specifies condition for setting bit 12 of control address register
(Table can be found on page 755 in the textbook.)
00 07 08 09 10 11 12
BC(4) BE(4)
BB(4) BD(4) BF(7)
BA(8)
Figure 21.9 IBM 3033 Control Address Register
Next microcode address
15
Microcode memory
32K 128 bits
128 Microinstruction
Microinstruction
pipeline register
Control and
Microinstruction 96 DA31-DA00
32
ACT8847
ACT8832 ACT8818
floating-point and
registered ALU microsequencer
integer processor
32
System Y bus
Local data
memory PC/AT
32K 32 bits interface
16
Figure 21.17 TI 8800 Block Diagram
Table 21.7 TI 8800 Microinstruction Format
Field Number
Number of Bits Description
Control of Board
1 5 Select condition code input
2 1 Enable/disable external I/O request signal
3 2 Enable/disable local data memory read/write operations
4 1 Load status/do no load status
5 2 Determine unit driving Y bus
6 2 Determine unit driving DA bus
8847 Floating Point and Integer Processing Chip
7 1 C register control: clock, do not clock
8 1 Select most significant or least significant bits for Y bus
9 1 C register data source: ALU, multiplexer
10 4 Select IEEE or FAST mode for ALU and MUL
11 8 Select sources for data operands: RA registers, RB registers, P register, 5 register, C
register
12 1 RB register control: clock, do not clock
13 1 RA register control: clock, do not clock
14 2 Data source confirmation
15 2 Enable/disable pipeline registers
16 11 8847 ALU function
8832 Registered ALU
17 2 Write enable/disable data output to selected register: most significant half, least
significant half
18 2 Select register file data source: DA bus, DB bus, ALU Y MUX output, system Y bus
19 3 Shift instruction modifier
20 1 Carry in: force, do not force
21 2 Set ALU configuration mode: 32, 16, or 8 bits
22 2 Select input to 5 multiplexer: register file, DB bus, MQ register
23 1 Select input to R multiplexer: register file, DA bus
24 6 Select register in file C for write
25 6 Select register in file B for read
26 6 Select register in file A for write
27 8 ALU function
8818 Microsequencer
28 12 Control input signals to the 8818
WCS Data Field
29 16 Most significant bits of writable control store data field
30 16 Least significant bits of writable control store data field
(Table can be found on page 758 in the textbook.)
DA31-DA16 DA15-DA00
(DRA) (DRA)
MUX
Dual
registers/counters
Stack
B3-B0
Microprogram Interrupt Y output
counter/ return multiplexer
incrementer register
Next microde
address
Figure 21.18 TI 8818 Microsequencer
Table 21.8 TI 8818 Microsequencer Microinstruction Bits (Field 28)
Mnemonic Value Description
RST8818 000000000110 Reset Instruction
BRA88181 011000111000 Branch to DRA Instruction
BRA88180 010000111110 Branch to DRA Instruction
INC88181 000000111110 Continue Instruction
INC88180 001000001000 Continue Instruction
CAL88181 010000110000 Jump to Subroutine at Address Specified by DRA
CAL88180 010000101110 Jump to Subroutine at Address Specified by DRA
RET8818 000000011010 Return from Subroutine
PUSH8818 000000110111 Push Interrupt Return Address onto Stack
POP8818 100000010000 Return from Interrupt
LOADDRA 000010111110 Load DRA Counter from DA Bus
LOADDRB 000110111110 Load DRB Counter from DA Bus
LOADDRAB 000110111100 Load DRA/DRB
DECRDRA 010001111100 Decrement DRA Counter and Branch If Not Zero
DECRDRB 010101111100 Decrement DRB Counter and Branch If Not Zero
(Table can be found on page 761 in the textbook.)
Table 21.9 TI 8832 Registered ALU Instruction Field (Field 27) (page 1 of 2)
Group 1 Function
ADD H#01 R + S + Cn
SUBR H#02 (NOT R) + S + Cn
SUBS H#03 R = (NOT S) + Cn
INSC H#04 S + Cn
INCNS H#05 (NOT S) + Cn
INCR H#06 R + Cn
INCNR H#07 (NOT R) + Cn
XOR H#09 R XOR S
AND H#0A R AND S
OR H#0B R OR S
NAND H#0C R NAND S
NOR H#0D R NOR S
ANDNR H#0E (NOT R) AND S
Group 2 Function
SRA H#00 Arithmetic right single precision shift
SRAD H#10 Arithmetic right double precision shift
SRL H#20 Logical right single precision shift
SRLD H#30 Logical right double precision shift
SLA H#40 Arithmetic left single precision shift
SLAD H#50 Arithmetic left double precision shift
SLC H#60 Circular left single precision shift
SLCD H#70 Circular left double precision shift
SRC H#80 Circular right single precision shift
SRCD H#90 Circular right double precision shift
MQSRA H#A0 Arithmetic right shift MQ register
MQSRL H#B0 Logical right shift MQ register
MQSLL H#C0 Logical left shift MQ register
MQSLC H#D0 Circular left shift MQ register
LOADMQ H#E0 Load MQ register
PASS H#F0 Pass ALU to Y (no shift operation)
Group 3 Function
SET1 H#08 Set bit 1
Set0 H#18 Set bit 0
TB1 H#28 Test bit 1
TB0 H#38 Test bit 0
ABS H#48 Absolute value
SMTC H#58 Sign magnitude/twos-complement
ADDI H#68 Add immediate
(Table can be found on page 764 in the textbook.)
Table 21.9 TI 8832 Registered ALU Instruction Field (Field 27) (page 2
of 2)
SUBI H#78 Subtract immediate
BADD H#88 Byte add R to S
BSUBS H#98 Byte subtract S from R
BSUBR H#A8 Byte subtract R from S
BINCS H#B8 Byte increment S
BINCNS H#C8 Byte increment negative S
BXOR H#D8 Byte XOR R and S
BAND H#E8 Byte AND R and S
BOR H#F8 Byte OR R and S
Group 4 Function
CRC H#00 Cyclic redundancy character accum.
SEL H#10 Select S or R
SNORM H#20 Single length normalize
DNORM H#30 Double length normalize
DIVRF H#40 Divide remainder fix
SDIVQF H#50 Signed divide quotient fix
SMULI H#60 Signed multiply iterate
SMULT H#70 Signed multiply terminate
SDIVIN H#80 Signed divide initialize
SDIVIS H#90 Signed divide start
SDIVI H#A0 Signed divide iterate
UDIVIS H#B0 Unsigned divide start
UDIVI H#C0 Unsigned divide iterate
UMULI H#D0 Unsigned multiply iterate
SDIVIT H#E0 Signed divide terminate
UDIVIT H#F0 Unsigned divide terminate
Group 5 Function
LOADFF H#0F Load divide/BCD flip-flops
CLR H#1F Clear
DUMPFF H#5F Output divide/BCD flip-flops
BCDBIN H#7F BCD to binary
EX3BC H#8F Excess -3 byte correction
EX3C H#9F Excess -3 word correction
SDIVO H#AF Signed divide overflow test
BINEX3 H#DF Binary to excess 3
NOP32 H#FF No operation
(Table can be found on page 765 in the textbook.)
Thank you for your listening
