Chapter

Control Unit Operation

Micro-Operations
• A computer executes a program
• It consists of a sequences of instruction
cycle
• Each cycle has a number of steps
• Called micro-operations
• Each instruction cycle is made up of a
number of smaller units(fetch, indirect,
execute and interrupt).
• Only fetch and execute cycles always
occurring.
• Microoperations are functional, or atomic
Constituent Elements of
Program Execution
 Fetch cycle

• fetch cycle occurs at the beginning of

each instruction cycles and causes an
instruction to be fetches from memory.
• Four register are involved in fetch cycle.
—MAR
—MBR
—PC
—IR
Fetch - 4 Registers
• Memory Address Register (MAR)
—Connected to address bus
—Specifies address for read or write op
• Memory Buffer Register (MBR)
—Connected to data bus
—Holds data to write or last data read
• Program Counter (PC)
—Holds address of next instruction to be fetched
• Instruction Register (IR)
—Holds last instruction fetched
Fetch Sequence
• Address of next instruction is in PC
• Address (MAR) is placed on address bus
• Control unit issues READ command
• Result (data from memory) appears on
data bus
• Data from data bus copied into MBR
• PC incremented by 1 (in parallel with data
fetch from memory)
• Data (instruction) moved from MBR to IR
• MBR is now free for further data fetches
Fetch Sequence (symbolic)
• t1: MAR <- (PC)
• t2: MBR <- (memory)
• PC <- (PC) +1
• t3: IR <- (MBR)
• (tx = time unit/clock cycle)
• or
• t1: MAR <- (PC)
• t2: MBR <- (memory)
• t3: PC <- (PC) +1
• IR <- (MBR)
Rules for Clock Cycle Grouping
• Proper sequence must be followed
—MAR <- (PC) must precede MBR <- (memory)
• Conflicts must be avoided
—Must not read & write same register at same
time
—MBR <- (memory) & IR <- (MBR) must not be
in same cycle
• Also: PC <- (PC) +1 involves addition
—Use ALU
—May need additional micro-operations
Indirect Cycle
• MAR <- (IRaddress) - address field of IR
• MBR <- (memory)
• IRaddress <- (MBRaddress)

• MBR contains an address

• IR is now in same state as if direct
addressing had been used
Interrupt Cycle
• t1: MBR <-(PC)
• t2: MAR <- save-address
• PC <- routine-address
• t3: memory <- (MBR)
• In the first step: the contents of the PC are
transferred to the MBR, so that they can be
saved for return from the interrupt.
• Then the MAR is loaded with the address at
which the content of the PC are to be saved, and
PC is loaded with address of the start of the
interrupt processing routine.
• Final step is store the MBR , which contains the
old value of the PC, into memory.
• Processor is now ready to begin the next cycle.
Execute Cycle (ADD)
• Different for each instruction
• e.g. ADD R1,X - add the contents of
location X to Register 1 , result in R1
• t1: MAR <- (IRaddress)
• t2: MBR <- (memory)
• t3: R1 <- R1 + (MBR)
• Note no overlap of micro-operations
Execute Cycle (ISZ)
• ISZ X - increment and skip if zero
—t1: MAR <- (IRaddress)
—t2: MBR <- (memory)
—t3: MBR <- (MBR) + 1
—t4: memory <- (MBR)
— if (MBR) == 0 then PC <- (PC) + 1
• Notes:
—if is a single micro-operation
—Micro-operations done during t4
Execute Cycle (BSA)
• BSA X - Branch and save address
—Address of instruction following BSA is saved
in X
—Execution continues from X+1
—t1: MAR <- (IRaddress)
— MBR <- (PC)
—t2: PC <- (IRaddress)
— memory <- (MBR)
—t3: PC <- (PC) + 1
Instruction Cycle
• Each phase decomposed into sequence of
elementary micro-operations
• E.g. fetch, indirect, and interrupt cycles
• Execute cycle
—One sequence of micro-operations for each
opcode
• Need to tie sequences together
• Assume new 2-bit register called the ICC.
—Instruction cycle code (ICC) designates the
state of the processor in terms of which
portion of the cycle its is in:
– 00: Fetch
– 01: Indirect
– 10: Execute
– 11: Interrupt
Flowchart for Instruction Cycle
• At the end of each the four cycle, the ICC
is set appropriately.
• The indirect cycle is always followed by
the execute cycle.
• The interrupt cycle is always followed by
the fetch cycle.
• For the both the execute and fetch cycle,
the next cycle depends on the state of the
system
Functional Requirements
• It is basic for the design and
implementation of the control unit.

—Define basic elements of processor

—Describe micro-operations
—Determine functions control unit
Basic Elements of Processor
• ALU
• Registers
• Internal data pahs
• External data paths
• Control Unit
Types of Micro-operation
• Transfer data between registers
• Transfer data from register to external
• Transfer data from external to register
• Perform arithmetic or logical ops
Functions of Control Unit
• Sequencing
—Causing the CPU to step through a series of
micro-operations in the proper sequence,
based on the program being executed.
• Execution
—Causing the performance of each micro-
operation to be performed.
• This is done using Control Signals
Control Signals
• Clock
—One micro-instruction (or set of parallel micro-
instructions) per clock cycle
• Instruction register
—Op-code for current instruction
—Determines which micro-instructions are
performed
• Flags
—State of CPU
—Results of previous operations
• From control bus
—Interrupts
—Acknowledgements
Control Signals - output
• Within CPU
—Cause data movement
—Activate specific functions
• Via control bus
—To memory
—To I/O modules
Example Control Signal Sequence -
Fetch
• MAR <- (PC)
—Control unit activates signal to open gates
between PC and MAR
• MBR <- (memory)
—Open gates between MAR and address bus
—Memory read control signal
—Open gates between data bus and MBR
• Control signals go to three separate
destinations
• Data path: the control unit controls the
internal flow of data.
• e.g instruction fetch the content of the
memory buffer register are transferred to
the instruction register.
• For each path to be controlled, there is a
gate
• The control signal from the control unit
temporarily open the gate to let data
pass.
• ALU: the control unit controls the
operations of the ALU by a set of control
signals. These signals activate various
logic device and gate with in the ALU.
• System bus: the control unit sends control
signals out onto the control lines of the
system bus(e.g memory READ)
Data Paths and Control Signals
Micro- Opreation and Control Signals
Hardwired Control Unit
• The control logic is implemented with
gates, F/Fs, decoders, and other digital
circuits
• Its input logic signals are transformed into
a set of output logic signals
• Fast operation, - Wiring change(if the
design has to be modified).
• It is not implemented in CISC machines.
• It can be optimized to produce a fast
mode operation.
Hardwired Control unit inputs

• The key inputs are the instruction

Register, the clock, flags and control bus
signals.
• Flags and control bus signals , each
individual bit typically has some meaning.
• The other two inputs are not directly
useful to the control unit
Hardwired Implementation (1)
• Instruction register
—Op-code causes different control signals for
each different instruction
—Unique logic for each op-code
—Decoder takes encoded input and produces
single output
—n binary inputs and 2n outputs
Hardwired Implementation (2)
• Clock
—Control unit issues a Repetitive sequence of
pulses.
—This is Useful for measuring duration of micro-
ops
—The period of the clock pulses must be long
enough to allow signal propagation
—Control unit emits different control signals at
different times within instruction cycle
—Need a counter with different control signals
for t1, t2 etc.
Control Unit with Decoded Inputs
Problems With Hard Wired Designs
• Complex sequencing & micro-operation
logic
• Difficult to design and test
• Inflexible design
• Difficult to add new instructions
Micro Instruction
• A set of micro operations occurring at one
time is known as a micro instruction.
• A sequence of instruction is known as a
micro program.
• There are two categories of micro
instruction
—Branching Instruction
—Non Branching instruction
Branching Micro instruction
• The branching micro instruction ,when
executed, transfers the control to the
micro instruction that is not sequence.
• A non branching instruction when
executed , transfer program control to the
very next micro instruction.
• Branching micro instruction are of the two
types
—Conditional Branch instruction
—Unconditional Branch Instruction
• Conditional Branch instruction:
—Conditional branch provides transfer of the
program control to a specified location on
fulfillment of a condition.
—The function of a branch logic in the control
unit is to provide decision making capability
—The condition are checked depending on the
bits in status word, which contains flag bits.
Unconditional Branch instruction:
 JMP instruction is an unconditional micro
instruction.
 It may be implemented by loading the
branch address from control memory into
the control address register
Micro instruction Format
• Horizontal micro Instruction Format
• Vertical Micro instruction format

Horizontal Micro instruction

 In which each bit represents a control signal
which directly controls a single bus.
 The length of such instructions is higher.
 It can be used and preferred when high speed of
operation is required.
 Each micro-instruction specifies many different
micro-operations to be performed in parallel
 It provides high degree of parallelism
• Vertical Micro instruction
—micro-instruction specifies single (or few)
micro-operations to be performed.
—A vertical micro instruction has shorter
formats but requires more instructions.
—It has limited ability to express a high degree
of parallelism.
Horizontal vs Vertical Microprogramming

Horizontal Microprogrammed
— Unpacked
— Hard
— Direct

Vertical Microprogrammed
— Packed
— Soft
— Indirect
Micro Programmed Control Unit
• The set of micro instructions is stored in
the control memory.
• The control address register contains the
address of the next instruction to be read.
• When a microinstruction is read from the
control memory, it is transferred to a
control buffer register.
• The micro programmed control unit still
has the same inputs(IR, ALU, Clock) and
outputs( control signals)
Functioning of micro programmed CU
Control Unit functions as follows
1. To execute an instruction, the sequencing logic
unit issues a READ command to the control
memory.
2. The word whose address is specified in the
control address register is read into the control
buffer register.
3. The content of the control buffer register
generates control signals and next address
information for the sequencing logic unit.
4. The sequencing logic unit loads a new address
into the control address register based on the
next address information from the control buffer
and the ALU flags.
All this happens during one clock pulse.
• Each micro instruction, the sequencing logic unit
loads a new address into the control address
register.
• depending on the value of the ALU flags and the
control buffer register, one of three decision is
made
— Get next instruction: add 1 to the control address
register.
— Jump to a new routine based on a jump micro
instruction: load the address field of the control buffer
register into the control address register.
— Jump to a machine instruction routine: load the control
address register based on the opcode in the IR
• in figure, two module decoder used.
• The upper decoder translate the opcode of the
IR into a control memory address.
• The lower decoder is used for vertical
instructions
• In a vertical micro instruction , a code is used for
each action is performed.
• The decoder translate this code into individual
control signals.
• In a horizontal micro instruction every bit in the
control field attaches to a control line.
Advantages and Disadvantages of
Microprogramming

Advantage:
• Simplifies design of control unit
— Cheaper to design
— Less error-prone
— Much easier to modify
— Supports having multiple versions / models

Disadvantage:
• Slower
• More expensive to produce in quantities
Micro instruction Sequencing
• The two basic tasks performed by a micro
programmed control unit are as follows:
—Micro instruction sequencing: get the next
micro instruction from the control memory.
—Micro instruction execution: generates the
control signals needed to execute the micro
instruction.
In designing a control unit, these tasks must be
considered together, because both affect the
format of the micro instruction and the timing
of the control unit
Design Consideration
• Two concern are involved in the design of a
micro instruction sequencing techniques:
—The size of the micro instruction.
—Address generation time.
The first concern is obvious: minimizing the size of
the control memory reduces the cost of that
component.
The second concern : simply a desire to execute
the micro instruction as fast as possible
• In executing a micro program, the address of the
next micro instruction to be executed is one of
these categories.
—Determined by instruction register
—Next sequential address
—Branch
Sequencing techniques
• It is based on current micro instruction,
condition flags, and the content of the
instruction register, a control memory
address must be generated for the next
micro instruction
• A wide variety of techniques have been
used.
• The three categories are based on the
format of the address information in the
micro instruction.
—Two address field.
—Single address field.
—Variable format.
Branch Control: Two Address Fields

Branch based upon:

• Instruction Opcode
• Address 1
• Address 2
• Two address approach is simple.
• A multiplexer is provided to select:
—Address from first address field.
—Address from second address field.
—Starting address based on the opcode field of
the current instruction.
The address selection signals are provided by a
branch logic module whose input consists of
control unit flags plus bits from control portion of
the micro instruction.
• A multiplexer is provided that serves as a
destination for both address field plus the
instruction register.
• Based on an address selection input, the
multiplexer transmit either the opcode or one of
the two addresses to the control address
register(CAR).
• The CAR is subsequently decoded to produce the
next micro instruction address.
Branch Control: Single Address Field

Branch based upon:

• Next instruction
• Address
• Opcode
• In single address field in the micro
instruction with the following option for
the next address:
—Address field.
—Based on opcode in instruction register.
—Next sequential address
 Branch Control: Variable Format

One bit determines

microinstruction
format:
• Control signal format
• Branch format

Does require even

more circuitry, and is
slowest.
• In this approach, there are two entirely different
micro instruction formats.
• One bit designates which format is being used.
• In the first format, the remaining bits are used to
activate control signals.
• In second format, some bits drive the branch
logic module
• Remaining bits provide the address.
• With the first format, the next address is either
the next sequential address or an address
derived from IR.
• The second format either a conditional or
unconditional branch is specified.
• One entire cycle is consumed with each branch
micro instruction
Organization of
Control Memory
Parallelism in micro instruction
• Micro programmed processor are frequently
characterized by the maximum number of
micro operations that a single
microinstruction can specify. This number
range from one to several hundred.
• Micro instruction that specify a single micro
operation are similar to conventional machine
instruction. They are relative short, but due
to their lack of parallelism , more micro
instruction are needed to perform a given
operation.
• Format of the IBM system/370 model 145,
is represented a micro instruction.
• It consists of 4 bytes(32 bits). The left
most byte(shaded) is an opcode that
specifies the micro operation to be
performed.
• The next 2 bytes specify operands, which
,in most cases ,are the addresses of CPU
registers.
• The right most byte contains information
used to construct the address of the next
intruction
• Micro instruction format take advantages of
the fact that, at the microprogramming level,
many operations can be performed in
parallel.
• If all useful combinations of parallel micro
operations were specified by a single opcode,
the number opcodes would, in most cases, be
enormous.
• An opcode decoder of considerable
complexity would be needed.
• To avoid these difficulties, it is usual to
divide the micro instruction specification part
of a micro instruction into k disjoint control
fields
• Each control field handles a limited set of
micro operations.
• Any one of which can be performed
simultaneously with the micro operations
specified by the remaining control fields.
• A control field often specifies the control
lines values for a single device such as
adder, a register, or a bus.
Micro instruction Addressing
• Various address generation techniques are
used.
• These can be divided into explicit and
implicit techniques.
• Explicit techniques: in which the address
is explicitly available in the micro
instruction.
• Implicit Techniques: which require
additional logic to generates the address.
• In explicit techniques we use two field
approach, single field, variable format
branch instruction for implementation.
• Several implicit techniques are also
commonly used.
• One of these , mapping is required with
virtually all design.
• Opcode portion of a machine instruction
must be mapped into micro instruction
address.
• This occur only once per instruction cycle.
• A common implicit techniques is one that
involves combining or adding two portions
of an address to form the complete
address.
• This approached was taken for the IBM
S/360 family and used on many of the
s/370 models.
• The final approach is residual control.
• This approached involves the use of a
micro instruction address that has
previously been saved in temporary
storage with in control unit
• Example: some micro instruction sets
come equipped with a subroutine facility.
• An internal register or stack of registers is
used to hold return addresses
Micro operation Timing
• We have to assumed that a micro
instruction activates a set of control
signals for an unspecified time during the
micro instruction’s execution cycle
• A single clock signal synchronizes the
control signals, and its period can be
same as the micro instruction cycle
period.
• This mode of control has been termed
monophase
• The number of micro instruction to specify
a particular operation can be reduced by
dividing the micro instruction cycle into
several sequential sub periods or clock
(phases.
• A control signals is typically active during
only one of the phases.
• The poly phase mode of operation permits
a single micro instruction to specify a
short sequence of micro operations for
some increases in the complexity of the
micro instruction format.
• R:=f(R1,R2)
• Consider a micro instruction that controls the
register transfer operation
• Where R can be R1or R2 this operation can be
performed in several phases
• Phase1: fetch the next micro instruction from
the control memory CM.
• Phase2: transfer the content of register R1
and R2 to the inputs of the f unit.
• Phase3: store the result generated by the f
unit in a temporary register
• Phase4: transfer the content of temporary
register to the destination register R.
Nano progarmming
• In most micro programmed processors,
an instruction fetched from memory is
interpreted by a micro program stored in
a single control memory.
• In a few machines, the micro instruction
do not directly issues the signals that
control the hardware.
• Instead, they are used to access a second
control memory called a nanocontrol
memory nCM that directly control
hardware.
• There are two levels of control memories,
a higher level one termed as a micro
control µCM whose content are
microinstruction .
• the lower nCM that stores nano
instructions.
• The nano programming concept was first
used in the QM-1 computer designed
around 1970 by nano data corp.
• It is also employed in the Motorola 68000
microprocessors series