Master List of Experiment

Maharashtra Institute of Technology, LABORATORY
Aurangabad MANUAL
Practical Experiment Instruction Sheet

Manual: MIT(T)/ETC/EC/EDC
Class: SY E&TC DEPARTMENT: Electronics & Telecommunication Engineering
LABORATORY: Location: Part - II Date:_ _/_ _/20_ _
MASTER LIST OF EXPERIMENT

Course Name: ETC221 Electronic Devices and Circuits Class: SY ETC
EXPT. PAGE GRADE / SIGN
EXPERIMENT NAME DATE
NO. NO. REMARK
Study of the characteristic of the NPN
01 transistor in common emitter
configuration
Study of the characteristic of the NPN
02 transistor in common base
configuration
Study of frequency responses of CE
03
amplifier.
Study of DC load line and to derive
04 Stability factor of voltage divider
biasing circuit.
Study of the operation of Class A
05
amplifier.
Study of the operation of Class B
06
amplifier.
Study of the characteristic of Class C
07
amplifier
Study of drain characteristics and
08
transfer characteristics of FET
Study of Drain characteristics and
09
transfer characteristics of MOSFET.
Study of Av, Ri, and Ro of Common
10
source JFET amplifier
11 Design test, simulate and build CE

transistor circuit using Proteus.
Design test, simulate and build CS
12 FET, MOSFET circuit using
Proteus.
Course Teacher Class Teacher Program coordinator Principal

Prepared By Approved By
Ms. P. P. Patil & Mr. J. S. Renius Dr. G. S. Sable
Department of Electronics and Telecommunication 20__ - 20__ Page | 1

Maharashtra Institute of Technology,
LABORATORY MANUAL
Aurangabad

Manual: MIT(T)/ETC/EC/EDC
LABORATORY: Location: Part - II Date:
Electronics & Telecommunication Engineering Department
Vision:
To develop the department into a full-fledged center of learning in the various fields of Electronics
and Telecommunication keeping in views the latest development and making student technologically superior
and ethically strong.
Mission:
To impart education and training in the field of electronics and telecommunication engineering and its
ailed areas by developing competencies of the students to meet social and industrial need
Program Educational Objectives
PEO1 Graduates will demonstrate professional engineering competencies.
PEO2 Graduates will apply engineering and science knowledge to solve technical problems with high
ethical standards.
PEO3 Graduates will have effective communication skills.
PEO4 Graduates will demonstrate leadership, teamwork in their profession and adapt to current trends by
engaging lifelong learning.

Program Outcomes:
1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals, and
an engineering specialization to the solution of complex engineering problems.
2. Problem analysis: Identify, formulate, review and analyze engineering problems reaching substantiated
conclusions.
3. Design/development of solutions: Design system components or processes as per need and specification.
4. Conduct investigations of complex problems: Use research-based knowledge and research methods
including design of experiments, analysis and interpretation of data in the field of electronics and
telecommunication.
5. Modern tool usage: Select, and apply appropriate techniques, modern engineering tools, skills and
equipment necessary for engineering practices.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess societal and
safety issues.
7. Environment and sustainability: Understand the impact of the professional engineering solutions in
societal and environmental contexts, and demonstrate the knowledge of, and need for sustainable
development.
8. Ethics: Apply ethical principles and commit to professional ethics, responsibilities and norms of the
engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or leader in diverse
teams, and in multidisciplinary settings.
10. Communication: Communicate effectively in both verbal and written form.

11. Project management and finance: Demonstrate knowledge and understanding of the engineering
principles and apply these to one’s own work, as a member and leader in a team, to manage projects and
in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to engage in independent
and life-long learning in the broadest context of technological change.

PROGRAM SPECIFIC OUTCOMES (PSOs)
Engineering Graduates will be able to:
1. Design analog and digital system.
2. Simulate and test communication system.
3. Design and implement embedded system.
Course Outcomes:
Course Name: ETC221 Electronic Devices and Circuits. Year of Study: 20_ _ - 20_ _
ETC221.1 Identify different biasing methods and stability factor.
ETC221.2 Analyze single stage and multistage amplifiers.
ETC221.3 Analyze multistage amplifiers using h-parameters.
ETC221.4 Classify power amplifiers.
Distinguish the constructional features and operation of FET and

ETC221.5
MOSFET.
Acquire hands on laboratory experience, utilizing oscilloscopes and

ETC221.6
other test equipment.

Aurangabad MANUAL

EXPERIMENT TITLE: Study of the characteristic of the NPN transistor in common emitter configuration
Experiment No.: MIT(T)/ETC/EC/EDC/01
LABORATORY: Location: Part - I Date:_ _/_ _/20_ _
EXPERIMENT No. 1
Aim: To Study of the characteristic of the NPN transistor in common emitter configuration.
Apparatus:-
1. Nvis-6502
2. 2mm Patch cords.
3. Digital multi-meter
Theory:-
Transistor characteristics are the curves, which represent relationship between different dc currents
and voltages of a transistor. These are helpful in studying the operation of a transistor
when connected in a circuit. The three important characteristics of a transistor are:
1. Input characteristic.
2. Output characteristic.
3. Constant current transfer characteristic.
Input Characteristic:
In common emitter configuration, it is the curve plotted between the input current (IB) versus
input voltage (VBE) for various constant values of output voltage (VCE). The approximated plot for
input characteristic is shown in Fig. 1. This characteristic reveal that for fixed value of output voltage
VCE, as the base to emitter voltage increases, the emitter current increases in a manner that closely
resembles the diode characteristics.
Fig. 1

Output Characteristic:
This is the curve plotted between the output current IC versus output voltage VCE for various constant
values of input current IB. The output characteristic has three basic region of interest as indicated in
fig.2 the active region, cutoff region and saturation region. In active region the collector base junction
is reverse biased while the base emitter junction is forward biased. This region is normally employed
for linear (undistorted) amplifier. In cutoff region the collector base junction and base emitter junction
of the transistor both are reverse biased. In this region transistor acts as an Off switch. In saturation
region the collector base junction and base emitter junction of the transistor both are forward biased.
In this region transistor acts as an On switch.
Fig. 2
Constant current transfer Characteristics:
This is the curve plotted between output collector current IC versus input base current IB for
constant value of output voltage VCE. The approximated plot for this characteristic is shown in Fig 3.
Fig. 3
Procedure:

To plot input characteristics proceed as follows:
1. Connect +5V and variable positive DC supplies at TP25 and TP19 resp.
2. Connect the circuit diagram as shown in above diagram.
3. Rotate both the potentiometer P1 and P3 fully in CCW (counter clockwise direction).
4. Connect Ammeter between test point 18 and 5 to measure input base current IB (μA).
5. Connect a 2mm patch cord between test point 4 and 20.
6. Connect voltmeter between test point 19 and ground to measure output voltage VCE.
7. Switch On the power supply.
8. Vary pot P3 and set a value of output voltage VCE at some constant value (2V, 3V...).
9. Now Connect voltmeter between test point 18 and ground to measure input voltage VBE.
10. Vary the potentiometer P1 so as to increase the value of input voltage VBE from zero to 0.8V in
steps and measure the corresponding values of input current IB for different constant value of output
voltage VCE in an observation Table 1.
11. Rotate potentiometer P1 fully in CCW direction.
12. Repeat the above procedure for different sets of output voltage VCE.
13. Plot a curve between input voltage VBE and input current IB as shown in Fig 1 using suitable
scale with the help of Observation Table l. This curve is the required input characteristic.

Observation Table 1 :
To plot output characteristics proceed as follows:
Fig. 5
1. Switch Off the power supply.

2. Connect +12 and positive variable DC supply to TP25 and TP15 resp.

7. Connect Ammeter between test point 16 and 5 to measure input current IB (μA).
9. Vary pot P3 and set a value of input current IB at some constant value (10μA, 20μA...50μA).
10. Now remove the patch cord between TP4 & TP20 and connect Ammeter between same test
point to measure output current IC (mA).
11. Short terminal TP16 & TP5.
12. Vary the potentiometer P1 so as to increase the value of output voltage VCE from zero to
maximum value in step and measure the corresponding values of output current IC for
different constant value of input current IB in an observation table 2.
14. Repeat the procedure from step 6 for different sets of input current IB.
15. Plot a curve between output voltage VCE and output current IC as shown in Fig 2 using
suitable scale with the help of observation.
Observation Table 2: This curve is the required output characteristic

To plot constant current transfer characteristics proceed as follows:
Fig. 6

2. Connect +5V and positive variable DC supply to TP25 and TP19 resp.
7. Connect Ammeter between test point 18 and 5 to measure input current IB (mA)
9. Vary potentiometer P3 and set a value of output voltage VCE at 10 V.
10. Now remove the patch cord between TP4 & TP20 connect one external Ammeter between
same test point to measure output current IC (mA).
11. Vary the potentiometer P1 so as to increase the value of input current IB from zero to 100µA
in steps and measure the corresponding values of output current IC in an observation Table 3
12. Plot a curve between output current IC and input current IB as shown in Fig 3 using suitable
scale with the help of Observation Table 3. This curve is the required Transfer
characteristic.

Observation Table 3:
Calculations :
1. Input resistance : It is the ratio of change in the input voltage VBE to change in the input current
IB at constant value of output voltage VCE or it is the reciprocal of the slope obtained from the input
characteristic.
Mathematically :
To calculate input resistance determine the slope from the input characteristic curve obtained from
observation Table 1. Reciprocal of this slope will give the required input resistance.
2. Output resistance : It is the ratio of change in the output voltage VCE to change in the output
current IC at constant value of input current IB or it is the reciprocal of the slope obtained from the
output characteristic.

Mathematically :
To calculate output resistance determine the slope from the output characteristic curve obtained from
observation Table 2. Reciprocal of this slope will give the required output resistance.
3. Current gain : It is the ratio of change in the output current IC to change in the input current IB at
constant value of output voltage VCE or it is the slope obtained from the constant current transfer
characteristic. It is denot
Mathematically :
To calculate current gain, determine the slope from the constant current transfer characteristic curve
obtained from observation Table 3. This slope is the required current gain.

Results :
Input resistance Rin= ___________
Output resistance Rout=________
Current Gain αac = ___________
Questions:
1.
__________________________________________________________________________
__________________________________________________________________________
__________________________________________________________________________
2.
__________________________________________________________________________
__________________________________________________________________________
__________________________________________________________________________
3.
__________________________________________________________________________
__________________________________________________________________________
__________________________________________________________________________
Rubrics for Practical Assessment:
Cognitive (3) Affective (3) Psychomotor (3) Total (9)
Sign of Course Teacher with Date

Aurangabad MANUAL

EXPERIMENT TITLE: Study of the characteristic of the NPN transistor in common base configuration
EXPERIMENT NO. 2
Aim: To Study of the characteristic of the NPN transistor in common base configuration.
Apparatus:-
1. Nvis-6502
2. 2mm Patch cords.
3. Digital multi-meter
Theory:-
Transistor characteristics are the curves, which represent relationship between different dc currents
and voltages of a transistor. These are helpful in studying the operation of a transistor
when connected in a circuit. The three important characteristics of a transistor are:
1. Input characteristic
2. Output characteristic
3. Constant current transfer characteristic
Input Characteristic:
In common base configuration, it is the curve plotted between the input current (IE) versus input
voltage (VEB) for various constant values of output voltage (VCB). The approximated plot for input
characteristic is shown in Fig. 1. This characteristic reveal that for fixed value of output voltage VCB,
as the base to emitter voltage increases, the emitter current increases in a manner that closely
resembles the diode characteristics.

Fig. 1
Output Characteristic:
This is the curve plotted between the output current IC versus output voltage VBC for various constant
values of input current IE. The output characteristic has three basic region of interest as indicated in fig.2
the active region, cutoff region and saturation region. In active region the collector base junction is reverse
biased while the base emitter junction if forward biased. This region is normally employed for linear
(undistorted) amplifier. In cutoff region the collector base junction and base emitter junction of the
transistor both are reverse biased. In this region transistor acts as an Off switch. In saturation region the
collector base junction and base emitter junction of the transistor both
are forward biased. In this region transistor acts as an On switch.
Fig. 2

Constant current transfer Characteristic:
This is the curve plotted between output collector current IC versus input emitter current IE for constant
value of output voltage VCB. The approximated plot for this characteristic is shown in Fig 3.
Fig. 3
Procedure:
To plot input characteristics proceed as follows:
Fig. 4

1. Connect -5V and positive variable dc supply at TP25 and TP23.
2. Connect the circuit diagram as shown in above diagram
4. Connect Ammeter between test point 14 and 6 to measure input emitter current IE (mA).
6. Connect voltmeter between test point 23 and ground to measure input voltage VBE .
8. Vary pot P3 and set a value of output voltage VCB at some constant value (2V, 3V…).
9. Now connect voltmeter between test point 14 and ground to measure output voltage VCB.
10. Vary the potentiometer P1 so as to increase the value of input voltage VBE from zero to
0.9V in steps and measure the corresponding values of input current IE for different
constant value of output voltage VCB in an Observation Table 1.
12. Repeat the above procedure for different sets of output voltage VCB.
13. Plot a curve between input voltage VBE and input current IE as shown in Fig 1 using suitable
scale with the help of Observation Table l. This curve is the required input characteristic.

To plot output characteristics proceed as follows:
Fig. 5

2. Connect +12 V and negative variable DC supply to TP25 and TP17 resp.
4. Rotate both the potentiometer P1 and P4 fully in CCW (counterclockwise direction).
5. Connect voltmeter between test point 24 and ground to measure output voltage VCB.
6. Connect one Ammeter between test point 18 and 6 to measure input current IE (mA)
9. Vary pot P4 and set a value of input current IE at some constant value (0mA, 1mA...).
10. Now remove the patch cord between Tp4 & Tp24 and connect Ammeter between same
test point to measure output current IC (mA).
12. Vary the potentiometer P1 so as to increase the value of output voltage VCB from zero to
maximum value in steps and measure the corresponding values of output current IC for
different constant value of input current IE in an observation Table 2.
14. Repeat the procedure from step 6 for different sets of input current IE.
15. Plot a curve between output voltage VCB and output current IC as shown in Fig 2 using
suitable scale with the help of observation Table 2. This curve is the required output
characteristic.

To plot constant current transfer characteristics proceed as follows:
Fig. 6

2. Connect -5V and positive variable DC supply to TP25 and TP23 resp.

6. Connect voltmeter between test point 23 and ground to measure output voltage VCB.
7. Connect one Ammeter between test point 14 and 6 to measure input current IE (mA) and
9. Vary potentiometer P3 and set a value of output voltage VCB at 10V.
10. Now remove the patch cord between TP4 & TP 24 and connect one external Ammeter between
same test points to measure output current IC (mA).
11. Vary the potentiometer P1 so as to increase the value of input current IE from zero to 10 mA
in steps and measure the corresponding values of output current IC in an observation Table 3.
12. Plot a curve between output current IC and input current IE as shown in Fig 3 using
suitable scale with the help of Observation Table 3. This curve is the required Transfer
characteristic.

Calculations :
1. Input resistance : It is the ratio of change in the input voltage VBE to change in the input current
IE at constant value of output voltage VCB or it is the reciprocal of the slope obtained from the input
characteristic.
Mathematically
To calculate input resistance determine the slope from the input characteristic curve obtained from
observation Table 1. Reciprocal of this slope will give the required input resistance.
2.Output resistance : It is the ratio of change in the output voltage VCB to change in the output
current IC at constant value of input current IE or it is the reciprocal of the slope obtained from the
output characteristic.
Mathematically
To calculate output resistance determine the slope from the output characteristic curve obtained from
observation Table 2. Reciprocal of this slope will give the required output resistance.
3. Current Gain : It is the ratio of change in the output current IC to change in the input current IE at
constant value of output voltage VCB or it is the slope obtained from the constant current transfer
characteristic. It is denoted by αac
Mathematically
To calculate current gain, determine the slope from the constant current transfer characteristic curve
obtained from observation Table 3. This slope is the required current gain.

Results :
Input resistance Rin= ___________
Output resistance Rout=________
Current Gain αac = ___________
Questions:
1.
__________________________________________________________________________
__________________________________________________________________________
__________________________________________________________________________
2.
__________________________________________________________________________
__________________________________________________________________________
__________________________________________________________________________
3.
__________________________________________________________________________
__________________________________________________________________________
__________________________________________________________________________

Aurangabad MANUAL

EXPERIMENT TITLE: To plot frequency responses of CE amplifier
EXPERIMENT No. 3
Aim: To study the Frequency Response of RC – Coupled amplifier.
Equipments Needed:
1. Analog board AB18.
2. DC power supply +12V from external source or ST2612 Analog Lab.
3. Function Generator.
4. Oscilloscope.
5. 2mm patch chords.
Circuit diagram:
Circuit used to study the Frequency Response of RC-Coupled amplifier is shown below:
Figure 1

Theory:
Single amplifier circuits, such as a common emitter, common base and common collector amplifiers
are seldom found alone, as a single stage amplifier, in any system. Generally, at least two or more than
two stages are connected in cascade combination. If the output of one amplifier is connected (coupled)
to the input of another amplifier the stages are said to be connected in "cascade". The benefit of
cascaded amplifiers is to develop an output voltage larger than either stage alone can develop. In fact,
the overall gain of the cascaded amplifiers (called system gain) is the product of each individual stage
gain, or
AV = AVl X AV2 X AVn ………….(1)
Total Voltage Gain = gain of first stage X gain of second stage X gain of any number of stages
Figure 2
Because of this the gain of a single stage is not as important as the system gain. Designers usually set
individual stage gains relatively low to reduce signal distortion. One of the very important
requirements to cascade one stage of amplifier to another is the impedance matching. When the output
impedance of pervious stage matches with the input impedance of its next stage, maximum power is
transferred. One of the coupling methods to couple the two stages is RC-coupling. RC Coupling has
the advantages of wide frequency response and relatively small cost and size.
Bandwidth of an RC - Coupled Amplifier:

Bandwidth is a term used to describe the band of frequencies a particular amplifier will effectively
amplify.
Figure 3
The f1 and f2 points are also known as half power points. The half power points are the points
at which the signal amplitude has dropped to .707 percent of the maximum signal amplitude. Any
frequency below the f1 or above the f2 point is not considered a usable output from the amplifier. The
bandwidth of the amplifier is the difference between the f1 and f2 points. It is generally accepted that
in an RC -Coupled amplifier the fl point is established by the coupling capacitor and by-pass capacitor

and the f2 point is set by the "shunt" or "stray wire" capacitance. The bandwidth of RC-Coupled
Amplifier is given by,
Bandwidth (B) = f2 – f1 …………….(2)
Procedure :
Connect +12V variable dc power supplies at their indicated position from external source or
ST-2612 Analog Lab.
1. Connect point b with d of AB18 board. This will cascade the two stages through RC coupling.
Where Cc is the coupling capacitor and the combination of R21 and R22 will act as coupling
resistance.
2. Connect 1Vp-p, 100Hz Sine wave signal at the input (between points Vin and g1) of amplifier
named Stage1 of AB18 board and observe the same on oscilloscope CH I.
3. Observe the output waveform at Stage 2 between points Vout and g4 on oscilloscope CH II.
4. Increase the amplitude of input signal to the value before the output sine wave just gets distorted.
5. Increase the input frequency value and observe the output waveform amplitude on oscilloscope.
6. Measure the maximum amplitude of the output sine wave and the frequency range for which the
output wave amplitude is 3dB down the maximum amplitude.(this will give two valves of frequency
fL and fH, the lower 3dB frequency and higher 3dB frequency respectively) as shown in fig.3.
7. Calculate Bandwidth of RC-Coupled amplifier using Eq.2.
Observation Table: VIN =
Sr.No. FREQUENCY VOUT AV= VOUT/VIN GV

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

Calculations:
Result :
f1 (lower 3dB frequency) = ……………………….
f2 (higher 3dB frequency) = ……………………….
Bandwidth (f2 – f1) = …………………….
Conclusion:

Questions:
1.
__________________________________________________________________________
__________________________________________________________________________
__________________________________________________________________________
2.
__________________________________________________________________________
__________________________________________________________________________
__________________________________________________________________________
3.
__________________________________________________________________________
__________________________________________________________________________
__________________________________________________________________________

Aurangabad MANUAL

EXPERIMENT TITLE: To plot DC load line and derive Stability factor of voltage divider biasing
circuit.
EXPERIMENT No. 4
Aim: To plot DC load line and derive Stability factor of voltage divider biasing circuit.
Equipments Needed :
1. Analog board of AB15.
2. DC power supplies +12V external source or ST2612 Analog Lab.
3. Digital Multimeter
4. 2 mm patch cords.
Circuit diagram :
Circuit used to plot different characteristics of transistor is shown in figure
Figure 1
Numerical:

Find out the Q point values of the circuit shown in figure.Find stability factor
If β=120

Procedure :
1. Connect Test point 2 and Test point 3, Test point 4 and Test point 5, Test point 6 and Test point 7, using
2mm patch cords.
2. Connect +12V DC power supply at their indicated position from external source or ST2612 Analog Lab.
3. Switch ‘On’ the power supply.
4. For the measurement of Quiescent Point measure the VCE by connecting Voltmeter between Test point 4
and Test point 6. Measure Collector current (Ic) by connecting Ammeter between Test point 4 and Test point 5.
Calculations :
Results :
Theoretical:
Practical:
Conclusion:

Questions:
1.
__________________________________________________________________________
__________________________________________________________________________
__________________________________________________________________________
2.
__________________________________________________________________________
__________________________________________________________________________
__________________________________________________________________________
3.
__________________________________________________________________________
__________________________________________________________________________
__________________________________________________________________________

Aurangabad MANUAL

EXPERIMENT TITLE: Study of the operation of class A amplifier
EXPERIMENT No. 5
Aim: To study the operation of Class A Amplifier.
Equipments Needed:
1. Analog board of NV6522.
2. Patch Cords.
3. Oscilloscope.
Circuit diagram:
Circuit used to study the operation of Class A Amplifier is shown below:
Figure 1

Theory:
The class A amplifiers are the amplifiers which deliver maximum undistorted symmetrical output
voltage swing to the low impedance load. Generally any system (like a stereo, radio or television)
consists of several stages of amplification. When the signal passes through these stages, the power
level of signal rises so much that the later stages require high power handling circuit elements such as
power transistors. Also as the load impedance of these later stages is very small (of the order of 8 ohm
for stereo amplifier speakers), heavy collector current flows. To handle this, transistors heaving power
rating of 1W or more are used in power amplifiers.
Power amplifiers are broadly classified as :
1. Class A (Voltage Amplifier)
2. Class B (Push-Pull Emitter Follower)
3. Class C Tuned Amplifier
Class A Amplifier:
Class A amplifier is basically a voltage amplifier in which transistor operates in active region for the
entire cycle of input AC signal. In other words the collector current flows for 360° of AC signal
Figure 2
For class A amplifiers the Q point is located somewhere near the middle of the AC load line and thus
offers maximum amplification of the input signal as shown below :

Figure 3
The collector current IC is non-zero even when the input signal is zero i.e. the IC flows for
100% of time. This leads to power dissipation even in quiescent condition. The Class ‘A’ amplifier is
the most common and simplest form of power amplifier that uses the switching transistor in the
standard common emitter circuit configuration. The transistor is always biased "ON" so that it
conducts during one complete cycle of the input signal waveform producing minimum distortion and
maximum amplitude to the output. This means that the Class ‘A’ Amplifier configuration operates in
the ideal operating mode, because there can be no crossover or switch-off distortion to the output
waveform even during the negative half of the cycle. Class ‘A’ power amplifier output stages may use
a single power transistor or pair of transistors connected together to share the high load current.
Consider the Class ‘A’ amplifier circuit below:

Figure 4
This is the simplest type of Class A power amplifier circuit. It uses a single-ended
transistor for its output stage with the resistive load connected directly to the collector terminal. When
the transistor switches "ON" it sinks the output current through the collector resulting in an inevitable
voltage drop across the emitter resistance thereby limiting the negative output capability. The
efficiency of this type of circuit is very low (less than 30%) and delivers small power outputs for a
large drain on the DC power supply. Class ‘A’ amplifier stage passes the load current even when no
input signal is applied. So, large heat sinks are needed for the output transistors. However, another
simple way to increase the current handling capacity of the circuit and obtain a greater power gain
simultaneously is to replace the single output transistor with a Darlington Transistor. These types of
devices comprises of basically two transistors within a single package, one small "pilot" transistor and
another larger "switching" transistor. The big advantage of these devices is that the input impedance is
suitably large while the output impedance is relatively low, thereby reducing the power loss and
therefore the heat within the switching device.

Class ‘A’ Output Waveform:
Figure 5
In this configuration, the Class A amplifier uses the same transistor for both halves
of the output waveform and due to its biasing arrangement, the output transistor always has current
flowing through it, even if there is no input signal. In other words the output transistor never turns
"OFF". This results in very low efficiency as its conversion of the DC supply power to the AC signal
power delivered to the load is usually very low. Generally, the output transistor of a Class A amplifier
gets very hot even when there is no input signal present. So some form of heat sinking is required. The
DC current flowing through the output transistor (Ic) when there is no output signal will be equal to
the current flowing through the load.
Procedure :
1. Connect the +12V DC supply to ‘+12V’ of Class ‘A’ Amplifier and also ‘Gnd’ to ground as shown
in circuit diagram.
2. Now connect the “Output” of Frequency Generator to “Vin.” of Class ‘A’ Power Amplifier and as
well as connect ground.
3. Connect CRO channel 1 to sockets ‘Vin’ & ‘Gnd’ of Class ‘A’ Power Amplifier using the CRO
probe.
4. Set the VR1 and VR2 fully anticlockwise direction.
5. Now switch On the supply.
6. Using the ‘Frequency Control’ and ‘Amplitude Control’ knobs of the Function Generator, set the
input signal at 2Vp-pVoltage, 10 KHz frequency and observe it on Oscilloscope (channel 1).
Note: Keep peak to peak voltage of input signal less than 4Vpp to avoid saturation of amplifier.
7. Connect CRO channel 2 to sockets ‘Vout’ &‘Gnd’ of Class ‘A’ Power Amplifier using CRO probe.
8. Vary VR2 gradually towards clockwise direction up to the maximum amplification of the output
signal is obtained.
9. Observe the amplified output on Oscilloscope (channel 2) with positive clipping.
10. Now vary VR1 in clockwise direction, you will observe the +ve clipping disappears which shows
that the Q-point is shifting below the DC load line (refer the theory section).
11. Observe the amplified output on Oscilloscope (channel 2) which is 4Vpp approximately and also
observe the phase shift of 180°.
Note: For observing I/P & O/P waveform simultaneously keep the Oscilloscope at Dual mode.

Results
Input ac signal amplitude (Vin) : ...................................Vp-p
Output ac signal amplitude (Vout) : ...................................Vp-p
Conclusion:
Questions:
1.
__________________________________________________________________________
__________________________________________________________________________
__________________________________________________________________________
2.
__________________________________________________________________________
__________________________________________________________________________
__________________________________________________________________________
3.
__________________________________________________________________________
__________________________________________________________________________
__________________________________________________________________________

Aurangabad MANUAL

EXPERIMENT TITLE: Study of the operation of Class B amplifier.
EXPERIMENT No. 6
Aim: Study of the operation of Class B Amplifier
Equipments Needed:
1. Analog board of Nvis6522
2. Oscilloscope Caddo 802 or equivalent
3. Patch cords
Circuit diagram:
Circuit used to study the operation of Class A Amplifier is shown below:
Figure 1

Theory
Class B Amplifier :
Class B amplifier is a circuit in which transistor conducts (collector current flows) for only 180° of
input AC signal. When a signal is applied, one half cycle will forward bias the base-emitter junction
and IC will flow. The other half cycle will reverse bias the base-emitter junction and IC will be cut
off.
Figure 2
For class B amplifiers the Q point is located near the cutoff point of the AC load line. Thus, to amplify
entire input AC signal a combination of two Class - B amplifiers are used. One of which amplifies
positive half cycle of input AC signal and the other amplifies negative half cycle of input AC signal.
This amplifier configuration is known as push-pull or complementary symmetry. In the push-pull
configuration it is important to match the two transistors carefully for the proper amplification of both
the halves. While the input signal being amplified through class B amplifier the input signal has to rise
to about 0.7V to overcome the barrier potential of amplifying transistor. During this period no current
flows through the circuit and output is zero. The action is similar for both the transistors. Thus,
following characteristic is obtained for input and output voltages:

Figure 3
The output signal no longer remains sine wave and gets distorted. Since the clipping occurs between
the time when one transistor cuts off and at the time when other one comes on. We call it crossover
distortion.
Input and output waveforms illustrating the zone/crossover distortion
Figure 4

Class B: Output Characteristics Curves:
Figure 5
Class B Amplifiers have the advantage over their Class A amplifier cousins in that no current flows
through the transistors when they are in their quiescent state (i.e. with no input signal), therefore no
power is dissipated in the output transistors or transformer when there is no signal present unlike Class
A amplifier stages that require significant base bias thereby dissipating lots of heat - even with no
input signal. So the overall conversion efficiency (η) of the amplifier is greater than that of the
equivalent Class A with efficiencies reaching as high as 75% possible resulting in nearly all modern
types of push-pull amplifiers operated in this Class B mode.
Complementary-Symmetry Class B Push-Pull Amplifier:
Class B push-pull amplifier also called as Complementary-Symmetry Class B Amplifier circuit it is
shown below. While Class B amplifiers have a much high gain than the Class A types, one of the main
disadvantages of class B type push-pull amplifiers is that they suffer from an effect known commonly
as Crossover Distortion. This occurs during the transition when the transistors are switching over from
one to the other as each transistor does not stop or start conducting exactly at the zero crossover point
even if they are specially matched pairs. This is because the output transistors require a base-emitter
voltage greater than 0.7V for the bipolar transistor to start conducting which results in both transistors
being "OFF" at the same time. This then would give us what is commonly called a Class AB
Amplifier circuit.
Figure 6

Procedure :
1. Connect +5V and -5V DC power supplies at their indicated position from DC Voltage Supply to
Class ‘B’ Power Amplifier & also ‘Gnd’ to ground.
2. Now connect the “Output” of Frequency Generator to “Vin.” of Class ‘B’ Power Amplifier and as
well as connect ground.
3. Connect CRO channel 1 to sockets ‘Vin’ and ‘Gnd’ of Class ‘B’ Power Amplifier using the CRO
probe.
4. Put the VR3 to its minimum position i.e. rotate it fully anticlockwise. (This is the condition when no
bias voltage is applied to the emitter diodes of both the transistors.)
input signal at 2VppVoltage, 10 KHz frequency and observe it on Oscilloscope (channel 1).
7. Connect Oscilloscope (channel 2) at the ‘Vout’ and ‘Gnd’ terminals of Class ‘B’ Power Amplifier
and observe the output waveform. The crossover distortion can be clearly observed on the
oscilloscope.
8. Gradually increase the bias voltage by increasing bias resistance VR3 (i.e. rotate the VR3 in
clockwise direction) up to the value when the crossover distortion is completely removed and
maximum amplification of the input signal is obtained.
9. Now observe the amplitude of input & output signal and calculate the voltage gain. (The class B
amplifier has unity voltage gain)
Results :
Amplitude of Input Signal (VIN) = ………..Vpp
Amplitude of Output Signal (Vout) =……..Vpp
Voltage Gain (Av) = Vout/Vin........
Conclusion:

Questions:
1.
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2.
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3.
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Aurangabad MANUAL

EXPERIMENT TITLE: Study of the characteristic of Class C amplifier
EXPERIMENT NO. 7
Aim: To Plot frequency response of Class C power amplifier.
Equipments Needed:
1. Oscilloscope
2. Patch Cords
Circuit diagram:
Circuit used to study the operation of Class C Amplifier is shown below:
Figure 1

Theory
Class B Amplifier :
Class C amplifier is a power amplifier in which collector current of the amplifying transistor flows for
less than 180° of input AC signal..
Figure 2
In short a class C amplifier is one in which the operating point is chosen so that the output current (or
voltage) is zero for more than one half of an input sinusoidal signal. The output signal would be
distorted if this nonsinusoidal current flows through the resistive load. To avoid the distortion that
would occur due to purely resistive load, load is usually a resonant tank circuit (LC circuit), which
therefore has a high resistive value at the frequency of interest. Hence, the selected signal output is
free from nonlinear distortions. The resonant tank circuit is tuned to the frequency of input signal.
When the circuit has a high quality factor (Q), parallel resonance occurs at approximately.
Where,
L = inductance
C = capacitance
The AC equivalent circuit of base-emitter junction is as shown in Fig.3 when Q of the circuit is high
enough.

Figure 3
As shown the input capacitor is a part of a negative clamper and hence the signal is negatively
clamped. On the positive half cycle of the input signal the coupling capacitor charges to approx. VP
with polarity shown as the base-emitter diode conducts. On the negative half cycle, capacitor
discharges through R1. Capacitor continues to discharge till the period T of the input signal is less
than time constant R1C. As the base voltage swings slightly above 0.7V the base-emitter diode turns
on, thus recharging the capacitor.
Figure 4

Figure 5
At the output side the collector current source drives a parallel resonant tank circuit. At resonance, the
AC load impedance is purely resistive and the collector current is minimum and the peak-to-peak load
voltage reaches a maximum. Above and below the resonance, AC load impedance decreases and the
collector current increases, thus reducing the amplification level or introducing distortion in the output
signal. A class C amplifier is a narrowband circuit it amplifies only the signals of resonant frequency
and near to it. As the amplification level reduces when input frequency is moved up and down the
resonant frequency, we can find out the bandwidth of the amplifier. The bandwidth of the Class C
amplifier can be find out as follows,
BW = FH - FL
Where,
FH = upper half power frequency
FL = lower half power frequency
The half power frequencies are identical frequencies at which the voltage gain equals 0.707 times the
maximum gain. The smaller the difference, narrower is the bandwidth of amplifier.
The dc collector current depends on the conduction angle and hence the overall efficiency of the
amplifier. In short as the duty cycle increases the efficiency of the amplifier decreases. For the
conduction angle of 180° the amplifier efficiency is 78.5%. If we further reduce the conduction angle
the stage efficiency will increase. The class C amplifier efficiency can be 100% at the maximum.
Class C Power Amplifier

Procedure :
Connect +12V power supply at their indicated position from DC Voltage Supply to LC tank circuit
(L1C6) of Class ‘C’ Power Amplifier and as well as connect ground.
2. Set the VR4 fully anticlockwise direction.
3. Connect the A terminal of LC tank circuit (L1C6) to C terminal of transistor T4.
input signal at 2VppVoltage, 15.9 KHz frequency and observe it on Oscilloscope channel 1.
6. Now connect the “Output” of Frequency Generator to “Vin” of Class ‘C’ Power Amplifier and
aswell as connect ground without disturbing the ‘Frequency Control’ and ‘Amplitude Control’
knobs of the generator.
7. Now connect the Oscilloscope channel 2 with output (Vout) of Class ‘C’ Power Amplifier &
ground
and observe the output signal.
8. For the maximum amplified output adjust the VR4, but due to adjusting VR4 given input signal
should not be distorted.
9. Note the amplitude of input & output signal from Oscilloscope & also you can observe the phase
shifting.
10. Now remove the first LC tank (L1C6) from circuit & “Output” of Frequency Generator from
Class ‘C’ Power Amplifier.
11. Connect +12V power supply at their indicated position from DC Voltage Supply to another LC
tank circuit (L2C7) of Class ‘C’ Power Amplifier and as well as connect ground.
12. Connect the B terminal of LC tank circuit (L2C7) to C terminal of transistor T4.
13. Using the ‘Frequency Control’ and ‘Amplitude Control’ knobs of the Function Generator, set
the input signal at 2VppVoltage, 23.2 KHz frequency and observe it on Oscilloscope channel 1.
14. Now connect the “Output” of Frequency Generator to “Vin.” of Class ‘C’ Power Amplifier and as
well as connect ground without disturbing the ‘Frequency Control’ and ‘Amplitude Control’ knobs
of the Generator.
15. Now connect the Oscilloscope channel 2 with output (Vout) of Class ‘C’ Power Amplifier and
ground & observe the output signal.
16. For the maximum amplified output adjust the VR4, but due to adjusting VR4 given input signal
should not be distorted.
17. Note the amplitude of input & output signal from Oscilloscope & also you can observe the phase
shifting.
Note: L1=L2=10mH, C6=10nF & C7=4.7nF

Observation Table: VIN =
Sr.No. FREQUENCY VOUT AV= VOUT/VIN GV

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Calculations:
Results :
Input AC signal amplitude (Vin) : ........................................... Vp-p
Output AC signal amplitude (Vout) :........................................ Vp-p
Resonant Frequency (Fr) : (Practical value) : ........................ Hz
Resonant Frequency (fr) : (Theoretical value) : .....................Hz (From Eq.l)
Input AC Power (Pi(ac) = Vp-p2 /8 * Rs) : ..................................W.
Output AC Power (Po(ac) = Vp-p2 / 8 * RL):...............................W.
Conclusion:

Questions:
1.
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2.
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3.
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Aurangabad MANUAL

EXPERIMENT TITLE: Study of drain characteristics and transfer characteristics of FET
EXPERIMENT No. 8
Aim: Study of the characteristics of JFET (Junction field effect transistor) in common
source configuration and evaluation of:
1. AC drain resistance
2. Transconductance
3. Amplification factor
4. Drain Resistance.
Equipments Needed:
1. Analog board of AB08.
2. DC power supplies +12V, +5V from external source or ST2612 Analog Lab.
3. Digital Multimeter (3 numbers).
4. 2 mm patch cords.
Circuit diagram:
Circuit used to plot different characteristics of transistor is shown in figure 1
Figure 1
Theory

FET is a voltage controlled current device so its characteristics are the curves which represent
relationship between different DC currents and voltages. These are helpful in studying different region
of operation of a Field effect transistor when connected in a circuit. The two important characteristics
of a Field Effect Transistor are:
1. Output /Drain characteristic.
2. Transfer characteristic.
Output / Drain Characteristics :
It is the curve plotted between output drain current ID versus output drain to source voltage VDS for
constant values of input Gate to source voltage VGS as shown in figure2.
Figure 2
It can be subdivided into following four regions:
Ohmic region OA :
This part of the characteristic is linear indicating that for low values of V DS, current varies directly with
voltage following Ohm's Law. It means that JFET behaves like an ordinary resistor till point A (called
knee) is reached.
Curve AB :
In this region, ID increases at inverse square law rate upto point B which is called Pinch-off point. This
progressive fall in the rate of increase of ID is caused by the square law increase in the depletion region at
each gate up to point B where the two regions are closest without touching each other. The drain to source
voltage VDS corresponding to point B is called pinch-off voltage VPO.
Pinch-off region BC :
It is also known as saturation region or 'amplifier' region. Here, JFET operates as a constant-current device
because ID is relatively independent of VDS. It is due to the fact that as VDS increases channel resistance also
increases proportionally thereby keeping ID practically constant at IDSS. Drain current in this region is given
by Shockley's equation It is the normal operating region of the JFET when used as an amplifier.
Breakdown region :
If VDS is increased beyond its value corresponding to point C (called avalanche breakdown voltage),
JFET enters the breakdown region where ID increases to an extensive value. This happens because the
reversed biased gate channel PN junction undergoes avalanche breakdown when small change in VDS
produce very large change in ID.
JFET characteristics with External Bias :
Figure 3 shows a family of ID versus VDS curves for different values of VGS. It is seen that as the
negative gate bias voltage is increased: Pinch-off voltage VP is reached at a lower value of VDS than
VGS = 0. Value of VDS for breakdown is decreased.

Figure 3
Transfer Characteristic :
It is the curve plotted between output drain current versus input Gate to source voltage for constant
values of output drain to source voltage as shown in figure 4.
Figure 4
It is similar to the transconductance characteristics of a vacuum tube or a transistor. It shows that when
VGS = 0, ID = IDSS and when ID = 0, VGS = VPO. The transfer characteristic approximately follows
the equation
The above equation can be written as

These characteristics can also be obtained from the drain/output characteristics by reading off VGS
and IDSS values for different values of VDS. The various parameters of a JFET can be obtained from
its two characteristics. The main parameters of a JFET when connected in common source mode are
AC Drain Resistance, rd:
It is the AC resistance between drain and source terminals when JFET is operating in the pinch-off
region. It is given by
rd = change in VDS/( change in ID ) at VGS constant or rd = VDS / ID | VGS
An alternative name is dynamic drain resistance. It is given by the slope of the drain characteristics in
the pinch off region. It is sometimes written as rds emphasizing the fact that it is the resistance from
drain to source. Since rd is usually the output resistance of a JFET, it may also be expressed as an
output admittance yos. Obviously, yos = 1/rd. It has a very high value.

Transconductance, gm:
It is simply the slope of transfer characteristics
gm = change in ID at VDS constant or rd = ID / VGS | VDS
change in VGS
Its unit is siemens (S) /Mho. It is also called forward transconductance (gfs) or forward
transadmittance Yfs. The transconductance measured at IDSS is written as gmo.
Mathematically
gm = gmo [1- (VGS / VP)]
Amplification factor, µ:
It is given by
µ = change in VDS at ID constant or µ = VDS / VGS | IDS
change in VGS
It can be proved from above that µ = gm × rd = gfs × rd
DC drain resistance, RDS:
It is also called the static or ohmic resistance of the channel. It is given by
RDS = VDS / ID
Drain Characteristics:
Connection Diagram:
Procedure:
1. Make the connections as shown in the above figure.

2. Connect the +15V DC supply to terminal 22 of Potentiometer P2 and terminal 24 to ground.
3. Now connect terminal 23 of Potentiometer P2 to terminal 5 of Resistance R3.

4. Now connect +ve terminal of Ammeter to terminal 6 of Resistance R3 and –ve terminal to Drain (D) of
FET to measure Drain Current.
5. Connect the -5V DC supply to terminal 19 of Potentiometer P1 and terminal 21 to ground.
6. Now connect terminal 20 of Potentiometer P1 to terminal 1 of R1.
7. Connect terminal 2 of R1 to gate (G) of FET to give a supply of -5V.
8. Connect Source (S) of FET to Ground.
9. Connect +ve terminal of voltmeter to Gate (G) of FET and -ve terminal to ground to measure gate
voltage VGS.
Note: As Source (S) of FET is already connected to ground so we can connect –ve terminal of Voltmeter
to ground or Source of FET.
10. Rotate both potentiometers P1 & P2 in fully anti-clock wise direction.
11. Now connect the mains cord to the Supply & switch „On‟ the power supply.
12. Now rotate potentiometer P1 and set the value of input gate to source voltage at some constant value
(0V, -1V, -2V).
13. Now Remove Voltmeter between Gate (G) and ground, and connect between Drain (D) and ground to
measure Drain Voltage VDS.
14. Now vary the potentiometer P2 so as to increase the value of drain voltage VDS from zero to 15 V in
step and measure the corresponding values of drain current ID for different constant value of gate voltage
VGS.
15. Note down the readings in given observation table.
16. Repeat the above procedure for different value of gate voltage VGS.
17. Plot a curve between drain voltage VDS and drain current ID, using suitable scale with the help of
observation table. This curve is the required drain characteristic.
Observation Table:

Transfer Characteristics:
Connection Diagram:
Procedure:
1. Connect the -5V DC supply to terminal 22 of Potentiometer P2 and terminal 24 to ground.
2. Now connect terminal 23 of Potentiometer P2 to terminal 1 of Resistance R1 and terminal 2 of
Resistance R1 to Gate (G) of FET.
3. Connect Source (S) of FET to Ground.
4. Select +14V variable DC power supply (by selecting the toggle switch at upward position) and
connect to terminal 5 of Resistance R3.
5. Now connect +ve terminal of Ammeter to terminal 6 of Resistance R3 and –ve terminal to Drain
(D) of FET to measure Drain Current ID (mA).
6. Rotate the potentiometer P2 and VR1 fully in anti-clockwise direction.
7. Connect +ve terminal of voltmeter to Drain (D) of FET and -ve terminal to ground or Source to
measure drain voltage VDS.
8. Now connect mains cord to the supply and Switch „On‟ the power supply.
9. Vary potentiometer VR1 and set a value of drain voltage VDS at some constant value (3, 4, 5V…..)
10. Disconnect voltmeter between drain (D) and ground and connect between Gate (G) and ground.
11. Vary the potentiometer P2 so as to increase the value of gate voltage VGS from zero to -5 V in
step and measure the corresponding values of drain current ID for different constant value of drain
voltage VDS.
13. Plot a curve between gate voltage VGS and drain current ID, using suitable scale with the help of

observation table. This curve is the required transfer characteristic.
14. Repeat the above procedure for different values of drain voltage VDS.
Observation Table:
Calculations:
AC Drain Resistance, rd:
It is the AC resistance between drain and source terminals when JFET is operating in the pinch-off
region. To calculate AC drain resistance calculate the slope of the drain characteristics in the pinch off
region obtained from Observation Table 1.
rd = change in VDS at VGS constant or rd = VDS / ID | VGS
change in ID
It has a very high value.
Transconductance, gm:
To calculate transconductance determine slope of the transfer characteristics obtained from
Observation Table 2
gm = change in ID at VDS constant or rd = ID / VGS | VDS
change in VGS
Its unit is siemens (S) / mho.
Amplification factor, µ:
It is given by
µ = change in VDS at ID constant or µ = VDS / VGS | IDS
change in VGS
or µ = gm * rd

DC drain resistance, RDS:
It is also called the static or ohmic resistance of the channel. It is given by
RDS = VDS /ID
Results:
AC Drain Resistance rd = ___________________

Transconductance, gm = _________________
Amplification factor µ = _________________
DC drain resistance, RDS= _______________
Conclusion:
Questions:
1.
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2.
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3.
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__________________________________________________________________________

Aurangabad MANUAL

EXPERIMENT TITLE: Drain characteristics and transfer characteristics of MOSFET.
EXPERIMENT No. 9
Aim: Study Drain characteristics and transfer characteristics of MOSFET.
Equipments Needed:
1. Analog board of Nvis 6512A.
2. DC power supplies +12V, +5V from external source or Nvis6512A Analog Lab.
3. Digital Multimeter (3 numbers).
4. 2 mm patch cords
Theory:
Circuit diagram:
A MOSFET transistor is a semiconductor device which is widely used to switch the

amplification signals in the electronic devices. MOSFET can be expanded metal-oxide-semiconductor
field-effect transistor that is used to influence the flow of electric charges by influencing the flow of the
charges to greater extent. MOSFETs are found in all the modern electronic devices which have four
terminals namely the source, gate, drain and the body. The body as the name suggests is the main plot
where the source and the drain are spaced while the gate is above these terminals and a special kind of
separating material is used as an insulation layer between the gate and the source, drain and body. It is
referred to as the modern integrated circuit because it is economic when used for mass production and can
be used for solving complex problems. MOSFET transistors are made up of silicon alloy with germanium
so that it possesses both the properties of silicon and germanium. Doping is the process of adding some
impurities to the semiconducting material so that the properties of the material is altered and by the process
of doping certain small impurities are added with the above mentioned semi conducting materials so that

its properties can be altered to suit our requirements and the common impurities added are the boron,
phosphorus, arsenic and gallium. The metal–oxide–semiconductor field-effect transistor (MOSFET) is a
device used for amplifying or switching electronic signals. In MOSFETs, a voltage on the oxide-insulated
gate electrode can induce a conducting channel between the two other contacts called source and drain.
The channel can be of n-type or p-type and is accordingly called an nMOSFET or a pMOSFET (also
commonly nMOS, pMOS). It is by far the most common transistor in both digital and analog circuits,
though the bipolar junction
Figure: Schematic Symbol of N-channel and P-channel MOSFET
Figure: Schematic Symbol and IC View
Types of MOSFET: There are two basic types of MOSFETs

 Depletion MOSFETs, or D-MOSFETs, can be operated in either the depletion mode or the
enhancement mode.
 Enhancement MOSFETs, or E-MOSFETs, can be operated only in the enhancement mode.
The differences between the two are a result of the physical construction of each. MOSFET construction
can be represented as shown in below Figure.

Depletion-mode MOSFET:
Figure: Structure of Depletion-mode MOSFET

Depletion-mode MOSFET is a piece of N-type material with a small P-type region on the right, and on the
left side of the channel a thin layer of silicon dioxide (insulator) is deposited to create an insulated gate.
The electrons flowing from source to drain must travel through the channel between the gate and the
substrate.
Figure: Depletion-mode MOSFET with a negative gate voltage
The VDD supplies free electrons to flow from the source to drain. These electrons flow through the narrow
channel on the left of the P-type substrate. (The gate voltage controls the width of the channel, and as a
result it controls the flow of the source, drain current of the device.)
Enhancement-mode MOSFET (E-MOSFET)

An E-MOSFET does not have an N-channel between the source and the drain.
Figure: Structure of Enhancement-mode MOSFET

When the gate is positive it will attract free electrons into the P-type region. The free electrons

willcombine with the holes located next to the silicon dioxide.
At the time that the gate becomes positive enough, all the holes touching the silicon dioxide are filled with
free electrons, and they begin to flow from the source to the drain of the device. This effect is the same as
creating a thin layer of N-type material next to the silicon dioxide that the gate is connected to. The thin
conducting layer that is created is called the N-type inversion layer. While the N-type inversion layer
exists, free electrons can flow easily from source to drain. The amount of the minimum gate voltage that is
required to create the N-type inversion layer is called the threshold voltage, (Vth).
Metal–oxide–semiconductor structure and channel formation:
A metal–oxide–semiconductor field-effect transistor (MOSFET) is based on the modulation of charge
concentration by a MOS capacitance between a body electrode and a gate electrode located above the body
and insulated from all other device regions by a gate dielectric layer which in the case of a MOSFET is an
oxide, such as silicon dioxide. If dielectrics other than an oxide such as silicon dioxide (often referred to as
oxide) are employed the device may be referred to as a metal–insulator semiconductor FET. Compared to
the MOS capacitor, the MOSFET includes two additional terminals (source and drain), each connected to
individual highly doped regions that are separated by the body region. These regions can be either p or n
type, but they must both be of the same type, and of opposite type to the body region. The source and drain
(unlike the body) are highly doped as signified by a '+' sign after the type of doping.
Figure: Cross section of an NMOS without channel formed: OFF state

Figure: Cross section of an NMOS with channel formed: ON state
If the MOSFET is an n-channel or nMOSFET, then the source and drain are 'n+' regions and the body is a
'p' region. As described above, with sufficient gate voltage, holes from the body are driven away from the
gate, forming an inversion layer or n-channel at the interface between the p region and the oxide. This
conducting channel extends between the source and the drain, and current is conducted through it when a
voltage is applied between source and drain. For gate voltages below the threshold value, the channel is
lightly populated, and only a very small subthreshold leakage can flow between the source and the drain. If
the MOSFET is a p-channel current or pMOS FET, then the source and drain are 'p+' regions and the body
is a 'n' region. When a negative gate-source voltage (positive source-gate) is applied, it creates a p-channel
at the surface of the n region, analogous to the n-channel case, but with opposite polarities of charges and
voltages. When a voltage less negative than the threshold value (a negative voltage for p-channel) is
applied between gate and source, the channel disappears and only a very small subthreshold current can
flow between the source and the drain. The source is so named because it is the source of the charge
carriers (electrons for n-channel, holes for p-channel) that flow through the channel; similarly, the drain is
where the charge carriers leave the channel. The device may comprise a Silicon On Insulator (SOI) device
in which a Buried OXide (BOX) is formed below a thin semiconductor layer. If the channel region
between the gate dielectric and a Buried Oxide (BOX) region is very thin, the very thin channel region is
referred to as an Ultra Thin Channel (UTC) region with the source and drain regions formed on either side
thereof in and/or above the thin semiconductor layer. Alternatively, the device may comprise a
SEMiconductor On Insulator (SEMOI) device in which semiconductors other than silicon are employed.
Many alternative semiconductor materials may be employed. When the source and drain regions are
formed above the channel in whole or in part, they are referred to as Raised Source/Drain (RSD) regions.
The 'metal' in the name is now often a misnomer because the previously metal gate material is now often a
layer of polysilicon (polycrystalline silicon). Aluminium had been the gate material until the mid 1970s,
when polysilicon became dominant, due to its capability to form self-aligned gates. Metallic gates
areregaining popularity, since it is difficult to increase the speed of operation of transistors without metal
gates. IGFET is a related term meaning insulated-gate field-effect transistor, and is almost synonymous
with MOSFET, though it can refer to FETs with a gate insulator that is not oxide. Another synonym is
MISFET for metal–insulator–semiconductor FET. FET with an oxide coating between gate and channel is
called a MOSFET (metal- oxide semiconductor field effect transistor) the figure below shows the oxide,
insulating the gate from the channel. MOSFET is voltage controlled device & required only small input
current. Its switching speed is very high; it is used in low power high frequency converter. But it has the
problem of electrostatic discharge so require special care in handling.
Modes of operation: The operation of a MOSFET can be separated into three different modes,
depending on the voltages at the terminals. In the following discussion, a simplified algebraic model is

used that is accurate only for old technology. Modern MOSFET characteristics require computer
models that have rather more complex behavior. For an enhancement-mode, n-channel MOSFET, the
three operational modes are: Cutoff, subthreshold, or weak-inversion mode: When VGS <Vth Where
Vth is the threshold voltage of the device. According to the basic threshold model, the transistor is
turned off, and there is no conduction between drain and source. In reality, the Boltzmann distribution
of electron energies allows some of the more energetic electrons at the source to enter the channel and
flow to the drain, resulting in a subthreshold current that is an exponential function of gate–source
voltage. While the current between drain and source should ideally be zero when the transistor is
being used as a turned-off switch, there is a weak-inversion current, sometimes called sub threshold
leakage. In weak inversion the current varies exponentially with gate-to-source bias VGS as given
approximately by:
Where ID0 = current at VGS = Vth and the slope factor n is given by n = 1 + CD / COX,
With CD = capacitance of the depletion layer COx= capacitance of the oxide layer. In a long-channel
device, there is no drain voltage dependence of the current once VDS >>VT, but as channel length is
reduced drain-induced barrier lowering introduces drain voltage dependence that depends in a
complex way upon the device geometry (for example, the channel doping, the junction doping and so
on).
Triode mode or linear region (also known as the ohmic mode When VGS > Vth and VDS < (VGS– Vth)
The transistor is turned on, and a channel has been created which allows current to flow between the
drain and the source. The MOSFET operates like a resistor, controlled by the gate voltage relative to
both the source and drain voltages. As here, the voltage between transistor gate and source (VGS)
exceeds the threshold voltage (Vth), it is known as Overdrive voltage. The current from drain to
source is modeled as:
Where is the charge-carrier effective mobility, is the gate width, is the gate length and is the gate oxide
capacitance per unit area. The transition from the exponential sub-threshold region to the triode region
is not as sharp as the equations suggest. Saturation or active mode When VGS> Vth and VDS ≥ (VGS–
Vth) The switch is turned on, and a channel has been created, which allows current to flow between
the drain and source. Since the drain voltage is higher than the gate voltage, the electrons spread out,
and conduction is not through a narrow channel but through a broader, two- or three-dimensional
current distribution extending away from the interface and deeper in the substrate. The onset of this
region is also known as pinch-off to indicate the lack of channel region near the drain. The drain
current is now weakly dependent upon drain voltage and controlled primarily by the gate–source
voltage, and modeled approximately as:
The additional factor involving λ, the channel-length modulation parameter, models current
dependence on drain voltage due to the early effect, or channel length modulation. According to this
equation, a key design parameter, the MOSFET transconductance is:
Where the combination Vov= VGS – Vth is called the overdrive voltage, and where VDSsat= VGS –
Vth ) accounts for a small discontinuity in which would otherwise appear at the transition between the
triode and saturation regions. Another key design parameter is the MOSFET output resistance rout
given by:

Drain Characteristics:
Connection Diagram:
Figure: Connection diagram for drain Characteristics of NMOS Enhancement

Characteristics of an EMOSFET
Figure: Drain Characteristics of NMOS Enhancement

Drain characteristics of an N-channel E-MOSFET are shown in figure. The lowest curve is the VGST
curve. When VGS is lesser than VGST, ID is approximately zero. When VGS is greater than VGST,
the device turns- on and the drain current ID is controlled by the gate voltage. The characteristic
curves have almost vertical and almost horizontal parts. The almost vertical components of the curves
correspond to the ohmic region, and the horizontal components correspond to the constant current
region. Thus E-MOSFET can be operated in either of these regions i.e. it can be used as a variable-
voltage resistor (WR) or as a constant current source.
Figure shows a typical transconductance curve. The current IDSS at VGS <=0 is very small, being of
the order of a few nano-amperes. When the VGS is made positive, the drain current ID increases
slowly at first, and then much more rapidly with an increase in VGS. The manufacturer sometimes
indicates the gate-source threshold voltage VGST at which the drain current ID attains some defined
small value, say 10uA. A current ID (corresponding approximately to the maximum value given on
the drain characteristics and the values of VGS required to give this current VGs ON are also usually
given on the manufacturers data sheet
Advantages of Mosfet:
1. High input impedance, Voltage controlled device, Easy to drive: To maintain on-state, base drive
current which is 1/5 or 1/10 of collector current is required, and larger reverse base drive current is
needed for the high speed turn-off for the current controlled device, BJT. Due to these characteristics
base drive circuit design becomes complicated, and becomes expensive. On the other hand, voltage
controlled device MOSFET is a switching device which is driven by channel at the semiconductor
surface due to the field effect produced by the voltage applied to the gate electrode, which is isolated

from the semiconductor surface. And as the required gate current during switching transient as well as
on, off state is small, the drive circuit design is simple and the cost of it can be reduced.
2. Unipolar device, Majority carrier device, Fast switching speed: As there are no delay due to storage
and recombination of minority carrier as in BJT, the switching speed is faster than the BJT in the
orders of magnitude. So it has advantage in the high frequency operation circuit where the switching
power loss is dominant.
3. Wide SOA (safe operating area):
It has a wider SOA than BJT as it is applicable in short period of time with high voltage and high
current without any destructive device failure due to second breakdown.
4. Forward voltage drop with positive temperature coefficient, Easy to use in parallel: When the
temperature increases, the forward voltage drop also increases, and because of this, the current flows
equally through each device when the devices are in parallel. So, the MOSFET is more easy to use in
parallel than the BJT which has forward voltage drop with negative temperature coefficient. The
major advantage of the MOSFET transistor is that it uses low power for accomplishing its purpose and
the dissipation of power in terms of loss is very little, which makes it a major component in the
modern computers and electronic devices like the cell phones, digital watches, small robotic toys and
calculators.
Disadvantages of MOSFET
1. High resistance channels: In normal operation, the source is electrically connected to the substrate.
With no gate bias, the depletion region extends out from the N+ drain in a pseudo hemispherical
shape. The channel length L cannot be made shorter than the minimum depletion width required to
support the rated voltage of the device.
2. Channel resistance may be decreased by creating wider channels but this is costly since it uses up
valuable silicon real estate. It also slows down the switching speed of the device by increasing its gate
capacitance.
Application of MOSFET- MOSFET as Amplifier MOSFETs can be used to make single stage class
"A" amplifier circuits with the Enhancement mode N-channel MOSFET common source amplifier
being the most popular circuit. The depletion mode MOSFET amplifiers are very similar to the JFET
amplifiers, except that the MOSFET has much higher input impedance. This high input impedance is
controlled by the gate biasing resistive network formed by R1 and R2. Also, the output signal for the
enhancement mode common source MOSFET amplifier is inverted because when VG is low the
transistor is switched "OFF" and VD (Vout) is high. When VG is high the transistor is switched "ON"
and VD (Vout) is low as shown.
Procedure:
1. Make the connections as shown in the above figure.
3. Now connect terminal 23 of Potentiometer P2 to terminal 5 of Resistance R3.
4. Now connect +veterminal of Ammeter to terminal 6 of Resistance R3 and –veterminal to Drain (D)
of MOSFET to measure Drain Current.
6. Now connect terminal 20 of P1 to terminal 17 of R9.
7. Connect terminal 18 of R9 to gate (G) of MOSFET to give a supply of 15V for gate.
8. Connect Source (S) of MOSFET to Ground.
9. Connect +veterminal of voltmeter to Gate (G) of MOSFET and -veterminal to ground to measure
drain voltage VGS.
Note: As Source (S) of MOSFET is already connected to ground so we can connect –veterminal of
Voltmeter to ground or Source of MOSFET.
10. Rotate both potentiometers P1 and P2 in fully anti clockwise direction.
11. Before performing experiment first connect the power cable to Power Supply box.
12. Connect the Power Supply with Techbook using given connectors of Power Supply Box.
13. Now switch On the power (press the rocker switch) from Power Supply box.
14. Now vary potentiometer P1 and set a value of gate voltage VGS at some constant value (5, 6, 7 &

8 V).
15. Now Remove Voltmeter between Gate (G) and ground, and connect between Drain (D) and
ground as shown in following figure to measure Drain Voltage VDS.
16. Now vary the potentiometer P2 so as to increase the value of drain voltage VDS from zero to 30 V
in step and measure the corresponding values of drain current ID for different constant value of gate
voltage VGS.
18. Repeat the above procedure for different value of gate voltage VGS.
19. Plot a curve between drain voltage VDS and drain current ID, using suitable scale with the help of
observation table. This curve is the required drain characteristic.

Transfe
r Characteristics:
Connection diagram:
Procedure:
2. Now connect terminal 23 of Potentiometer P2 to terminal 17 of Resistance R9 and terminal 18 of
Resistance R9 to Gate (G) of MOSFET.
3. Connect Source (S) of MOSFET to Ground.
4. Select +35V variable DC power supply (by selecting the toggle switch at downward position) and
connect to terminal 5 of Resistance R3.

5. Now connect +veterminal of Ammeter to terminal 6 of Resistance R3 and –veterminal to Drain (D)
of MOSFET to measure Drain Current ID (mA).
6. Rotate both of the potentiometer P2 and VR1 fully in anti-clockwise direction.
7. Connect +veterminal of voltmeter to Drain (D) of MOSFET and -ve terminal to ground to measure
drain voltage VDS.
8. Now connect mains cord to the supply and Switch „On‟ the power supply.
9. Vary potentiometer VR1 and set a value of drain voltage VDS at some constant value (10, 20 &
28V).
10. Disconnect voltmeter between drain (D) and ground and connect between Gate (G) and ground as
shown in below figure.
11. Vary the potentiometer P2 so as to increase the value of gate voltage VGS from zero to 15 V in
step and measure the corresponding values of drain current ID for different constant value of drain
voltage VDS.
13. Plot a curve between gate voltage VGS and drain current ID, using suitable scale with the help of
observation table. This curve is the required transfer characteristic.
14. Repeat the above procedure for different values of drain voltage VDS.
Conclusion:
Questions:
1.

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2.
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3.
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Maharashtra Institute of Technology, LABORATORY

Practical Experiment Instruction Sheet