Spartan-3E FPGA Family: Complete Data Sheet: Introduction and Ordering Information DC and Switching Characteristics

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R Spartan-3E FPGA Family:

Complete Data Sheet
DS312 March 21, 2005 0 0
Module 1: Module 3:
Introduction and Ordering Information DC and Switching Characteristics
DS312-1 (v1.1) March 21, 2005 DS312-3 (v1.0) March 1, 2005
6 pages 18 pages
• Introduction • DC Electrical Characteristics
• Features - Absolute Maximum Ratings
• Architectural Overview - Supply Voltage Specifications
• Package Marking - Recommended Operating Conditions
• Ordering Information - DC Characteristics
• Switching Characteristics
Module 2: - DCM Timing
Functional Description - Configuration and JTAG Timing
DS312-2 (v1.1) March 21, 2005

96 pages
Module 4:
Pinout Descriptions
• Input/Output Blocks (IOBs)
- Overview DS312-4 (v1.1) March 21, 2005
72 pages
- SelectIO™ Signal Standards
• Configurable Logic Block (CLB) • Pin Descriptions
• Block RAM • Package Overview
• Dedicated Multipliers • Pinout Tables
• Digital Clock Manager (DCM) • Footprint Diagrams
• Clock Network
• Configuration
• Powering Spartan-3E FPGAs
IMPORTANT NOTE: The Spartan™-3E FPGA data sheet is created and published in separate modules. This complete
version is provided for easy downloading and searching of the complete document. Page, figure, and table numbers begin
at 1 for each module, and each module has its own Revision History at the end. Use the PDF "Bookmarks" for easy
navigation in this volume.
© 2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc.
All other trademarks are the property of their respective owners.
DS312 March 21, 2005 www.xilinx.com 1

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Spartan-3E FPGA Family:
Introduction and Ordering
Information
DS312-1 (v1.1) March 21, 2005 0 0 Advance Product Specification
Introduction
The Spartan™-3E family of Field-Programmable Gate - True LVDS, RSDS, mini-LVDS differential I/O
Arrays (FPGAs) is specifically designed to meet the needs - 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
of high volume, cost-sensitive consumer electronic applica- - Enhanced Double Data Rate (DDR) support
tions. The five-member family offers densities ranging from • Abundant, flexible logic resources
100,000 to 1.6 million system gates, as shown in Table 1. - Densities up to 33,192 logic cells, including
The Spartan-3E family builds on the success of the earlier optional shift register or distributed RAM support
Spartan-3 family by increasing the amount of logic per I/O, - Efficient wide multiplexers, wide logic
significantly reducing the cost per logic cell. New features - Fast look-ahead carry logic
improve system performance and reduce the cost of config- - Enhanced 18 x 18 multipliers with optional pipeline
uration. These Spartan-3E enhancements, combined with
- IEEE 1149.1/1532 JTAG programming/debug port
advanced 90 nm process technology, deliver more function-
ality and bandwidth per dollar than was previously possible, • Hierarchical SelectRAM™ memory architecture
setting new standards in the programmable logic industry. - Up to 648 Kbits of fast block RAM
- Up to 231 Kbits of efficient distributed RAM
Because of their exceptionally low cost, Spartan-3E FPGAs
• Up to eight Digital Clock Managers (DCMs)
are ideally suited to a wide range of consumer electronics
applications, including broadband access, home network- - Clock skew elimination (delay locked loop)
ing, display/projection, and digital television equipment. - Frequency synthesis, multiplication, division
- High-resolution phase shifting
The Spartan-3E family is a superior alternative to mask pro-
- Wide frequency range (5 MHz to over 300 MHz)
grammed ASICs. FPGAs avoid the high initial cost, the
lengthy development cycles, and the inherent inflexibility of • Eight global clocks and eight clocks for each half of
conventional ASICs. Also, FPGA programmability permits device, plus abundant low-skew routing
design upgrades in the field with no hardware replacement • Configuration interface to industry-standard PROMs
necessary, an impossibility with ASICs. - Low-cost, space-saving SPI serial Flash PROM
- x8 or x8/x16 parallel NOR Flash PROM
Features - Low-cost Xilinx Platform Flash with JTAG
• Very low cost, high-performance logic solution for • Complete Xilinx ISE™, WebPACK™ development
high-volume, consumer-oriented applications system support
• Proven advanced 90-nanometer process technology • MicroBlaze™, PicoBlaze™ embedded processor cores
• Multi-voltage, multi-standard SelectIO™ interface pins • Fully compliant 32-/64-bit 33/66 MHz PCI support
- Up to 376 I/O pins or 156 differential signal pairs • Low-cost QFP and BGA packaging options
- LVCMOS, LVTTL, HSTL, and SSTL single-ended - Common footprints support easy density migration
signal standards - Pb-free packaging options
Table 1: Summary of Spartan-3E FPGA Attributes
CLB Array
Equivalent (One CLB = Four Slices) Block Maximum
System Logic Total Total Distributed RAM Dedicated Maximum Differential
Device Gates Cells Rows Columns CLBs Slices RAM bits(1) bits(1) Multipliers DCMs User I/O I/O Pairs
XC3S100E 100K 2,160 22 16 240 960 15K 72K 4 2 108 40
XC3S250E 250K 5,508 34 26 612 2,448 38K 216K 12 4 172 68
XC3S500E 500K 10,476 46 34 1,164 4,656 73K 360K 20 4 232 92
XC3S1200E 1200K 19,512 60 46 2,168 8,672 136K 504K 28 8 304 124
XC3S1600E 1600K 33,192 76 58 3,688 14,752 231K 648K 36 8 376 156
Notes:
1. By convention, one Kb is equivalent to 1,024 bits.
DS312-1 (v1.1) March 21, 2005 www.xilinx.com 1

Advance Product Specification
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Introduction and Ordering Information
Architectural Overview
The Spartan-3E family architecture consists of five funda- • Digital Clock Manager (DCM) Blocks provide
mental programmable functional elements: self-calibrating, fully digital solutions for distributing,
• Configurable Logic Blocks (CLBs) contain flexible delaying, multiplying, dividing, and phase-shifting clock
Look-Up Tables (LUTs) that implement logic plus signals.
storage elements used as flip-flops or latches. CLBs These elements are organized as shown in Figure 1. A ring
perform a wide variety of logical functions as well as of IOBs surrounds a regular array of CLBs. Each device has
store data. two columns of block RAM except for the XC3S100E, which
• Input/Output Blocks (IOBs) control the flow of data has one column. Each RAM column consists of several
between the I/O pins and the internal logic of the 18-Kbit RAM blocks. Each block RAM is associated with a
device. Each IOB supports bidirectional data flow plus dedicated multiplier. The DCMs are positioned in the center
3-state operation. Supports a variety of signal with two at the top and two at the bottom of the device. The
standards, including four high-performance differential XC3S100E has only one DCM at the top and bottom, while
standards. Double Data-Rate (DDR) registers are the XC3S1200E and XC3S1600E add two DCMs in the
included. middle of the left and right sides.
• Block RAM provides data storage in the form of The Spartan-3E family features a rich network of traces that
18-Kbit dual-port blocks. interconnect all five functional elements, transmitting sig-
• Multiplier Blocks accept two 18-bit binary numbers as nals among them. Each functional element has an associ-
inputs and calculate the product. ated switch matrix that permits multiple connections to the
routing.
Notes:
1. The XC3S1200E and XC3S1600E have two additional DCMs on both the left and right sides as
indicated by the dashed lines. The XC3S100E has only one DCM at the top and one at the bottom.
Figure 1: Spartan-3E Family Architecture
2 www.xilinx.com DS312-1 (v1.1) March 21, 2005

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Configuration I/O Capabilities

Spartan-3E FPGAs are programmed by loading configura- The Spartan-3E FPGA SelectIO interface supports many
tion data into robust, reprogrammable, static CMOS config- popular single-ended and differential standards. Table 2
uration latches (CCLs) that collectively control all functional shows the number of user I/Os as well as the number of dif-
elements and routing resources. The FPGA’s configuration ferential I/O pairs available for each device/package combi-
data is stored externally in a PROM or some other non-vol- nation.
atile medium, either on or off the board. After applying Spartan-3E FPGAs support the following single-ended
power, the configuration data is written to the FPGA using standards:
any of seven different modes:
• 3.3V, low-voltage TTL, LVTTL
• Master Serial from a Xilinx Platform Flash PROM
• Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
• Serial Peripheral Interface (SPI) from an 1.5V, or 1.2V
industry-standard SPI serial Flash
• 3.3V PCI at 33 MHz and 66 MHz
• Byte Peripheral Interface (BPI) Up or Down from an
• HSTL I and III at 1.8V, typically for memory applications
industry-standard x8 or x8/x16 parallel NOR Flash
• SSTL I at 1.8V and 2.5V, typically for memory
• Slave Serial, typically downloaded from a processor
applications
• Slave Parallel, typically downloaded from a processor
Spartan-3E FPGAs support the following differential stan-
• Boundary Scan (JTAG), typically downloaded from a
dards:
processor or system tester.
• LVDS
• Bus LVDS
• mini-LVDS
• RSDS
Table 2: Available User I/Os and Differential (Diff) I/O Pairs

VQ100 CP132 TQ144 PQ208 FT256 FG320 FG400 FG484
VQG100 CPG132 TQG144 PQG208 FTG256 FGG320 FGG400 FGG484
Device User Diff User Diff User Diff User Diff User Diff User Diff User Diff User Diff
XC3S100E 66 30 - - 108 40 - - - - - - - - - -
XC3S250E 66 30 92 41 108 40 158 65 172 68 - - - - - -
XC3S500E - - 92 41 - - 158 65 190 77 232 92 - - - -
XC3S1200E - - - - - - - - 190 77 250 99 304 124 - -
XC3S1600E - - - - - - - - - - 250 99 304 124 376 156
Notes:
1. All Spartan-3E devices in the same package are pin-compatible.

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Package Marking
Figure 2 provides a top marking example for Spartan-3E the top marking for Spartan-3E FPGAs in the CP132 and
FPGAs in the quad-flat packages. Figure 3 shows the top CPG132 packages.
marking for Spartan-3E FPGAs in BGA packages except Use the seven digits of the Lot Code to access additional
the 132-ball chip-scale package (CP132 and CPG132). The information for a specific device using the Xilinx web-based
markings for the BGA packages are nearly identical to those Genealogy Viewer.
for the quad-flat packages, except that the marking is
rotated with respect to the ball A1 indicator. Figure 4 shows
Mask Revision Code
Fabrication Code
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SPARTAN Process Technology

Device Type XC3S250E TM
Package PQ208AGQ0525 Date Code
D1234567A Lot Code
Speed Grade 4C
Temperature Range
Pin P1 DS312-1_06_032105
Figure 2: Spartan-3E QFP Example Package Marking
Mask Revision Code

BGA Ball A1 R
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Fabrication Code
SPARTAN Process Code
Device Type XC3S250ETM
Package FT256AGQ0525 Date Code
D1234567A Lot Code
4C
Speed Grade
Temperature Range
DS312-1_02_032105
Figure 3: Spartan-3E BGA Example Package Marking
Ball A1 3S250E Device Type
Lot Code F1234567-0525 Date Code
PHILIPPINES
Temperature Range
Package C5AGQ 4C
C5 = CP132
C6 = CPG132 Speed Grade
Process Code
Mask Revision Code Fabrication Code
DS312-1_05_032105
Figure 4: Spartan-3E CP132 and CPG132 Example Package Marking

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Ordering Information
Spartan-3E FPGAs are available in both standard and Pb-free packaging options for all device/package combinations. The
Pb-free packages include a ‘G’ character in the ordering code.
Standard Packaging
Example: XC3S250E -4 FT 256 C

Device Type Temperature Range:
C = Commercial (TJ = 0oC to 85oC)
Speed Grade I = Industrial (TJ = -40oC to 100oC)
Package Type Number of Pins DS312_03_011405
Pb-Free Packaging
Example: XC3S250E -4 FT G 256 C

Device Type Temperature Range:
C = Commercial (TJ = 0oC to 85oC)
Speed Grade I = Industrial (TJ = -40oC to 100oC)
Number of Pins
Package Type
Pb-free DS312_04_011405
Device Speed Grade Package Type / Number of Pins Temperature Range (TJ )
XC3S100E –4 Standard Performance VQ(G)100 100-pin Very Thin Quad Flat Pack (VQFP) C Commercial (0°C to 85°C)
XC3S250E –5 High Performance CP(G)132 132-ball Chip-Scale Package (CSP) I Industrial (–40°C to 100°C)
XC3S500E TQ(G)144 144-pin Thin Quad Flat Pack (TQFP)
XC3S1200E PQ(G)208 208-pin Plastic Quad Flat Pack (PQFP)
XC3S1600E FT(G)256 256-ball Fine-Pitch Thin Ball Grid Array (FTBGA)
FG(G)320 320-ball Fine-Pitch Ball Grid Array (FBGA)
Notes:
1. The –5 speed grade is exclusively available in the Commercial temperature range.

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Revision History
The following table shows the revision history for this document.
Date Version Revision

03/01/05 1.0 Initial Xilinx release.
03/21/05 1.1 Added XC3S250E in CP132 package to Table 2. Corrected number of differential I/O pairs
for CP132 package. Added package markings for QFP packages (Figure 2) and
CP132/CPG132 packages (Figure 4).
The Spartan-3E Family Data Sheet

DS312-1, Spartan-3E FPGA Family: Introduction and Ordering Information (Module 1)
DS312-2, Spartan-3E FPGA Family: Functional Description (Module 2)
DS312-3, Spartan-3E FPGA Family: DC and Switching Characteristics (Module 3)
DS312-4, Spartan-3E FPGA Family: Pinout Descriptions (Module 4)

096

Functional Description
Introduction the delay element, there are alternate routes through a

pair of storage elements to the IQ1 and IQ2 lines. The
As described in Architectural Overview, the Spartan™-3E
IOB outputs I, IQ1, and IQ2 lead to the FPGA’s internal
FPGA architecture consists of five fundamental functional
logic. The delay element can be set to ensure a hold
elements:
time of zero (see Input Delay Functions).
• Input/Output Blocks (IOBs) • The output path, starting with the O1 and O2 lines,
• Configurable Logic Block (CLB) and Slice carries data from the FPGA’s internal logic through a
Resources multiplexer and then a three-state driver to the IOB
• Block RAM pad. In addition to this direct path, the multiplexer
• Dedicated Multipliers provides the option to insert a pair of storage elements.
• Digital Clock Managers (DCMs) • The 3-state path determines when the output driver is
high impedance. The T1 and T2 lines carry data from
The following sections provide detailed information on each the FPGA’s internal logic through a multiplexer to the
of these functions. In addition, this section also describes output driver. In addition to this direct path, the
the following functions: multiplexer provides the option to insert a pair of
• Clocking Infrastructure storage elements.
• Interconnect • All signal paths entering the IOB, including those
• Configuration associated with the storage elements, have an inverter
• Powering Spartan-3E FPGAs option. Any inverter placed on these paths is
automatically absorbed into the IOB.
Input/Output Blocks (IOBs)
IOB Overview
The Input/Output Block (IOB) provides a programmable,
unidirectional or bidirectional interface between a package
pin and the FPGA’s internal logic. The IOB is similar to that
of the Spartan-3 family with the following differences:
• Input-only blocks are added
• Programmable input delays are added to all blocks
• DDR flip-flops can be shared between adjacent IOBs
The unidirectional input-only block has a subset of the full
IOB capabilities. Thus there are no connections or logic for
an output path. The following paragraphs assume that any
reference to output functionality does not apply to the
input-only blocks. The number of input-only blocks varies
with device size, but is never more than 25% of the total IOB
count.
Figure 1, page 2 is a simplified diagram of the IOB’s internal
structure. There are three main signal paths within the IOB:
the output path, input path, and 3-state path. Each path has
its own pair of storage elements that can act as either regis-
ters or latches. For more information, see Storage Element
Functions. The three main signal paths are as follows:
• The input path carries data from the pad, which is
bonded to a package pin, through an optional
programmable delay element directly to the I line. After

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T
TFF1
T1 D Q
CE
CK
SR REV
DDR
MUX
TCE
T2 D Q
TFF2
CE
CK
SR REV
Three-state Path
ODDROUT1
VCCO
O1 OFF1
D Q
ODDRIN1 CE
OTCLK1 CK Pull-Up ESD
SR REV
DDR I/O
MUX Pin
OCE
Program- Pull-
O2 Q mable ESD
D Down
ODDRIN2 OFF2 Output
CE Driver
OTCLK2 CK
SR REV
Keeper
Latch
ODDROUT2 Output Path
I
IQ1 LVCMOS, LVTTL, PCI
Programmable
Delay
IDDRIN1 D Q Single-ended Standards
IDDRIN2 IFF1 using VREF
CE
VREF
ICLK1 CK Pin
ICE SR REV
Differential Standards
IQ2 I/O Pin
D Q from
Adjacent
IFF2
CE IOB
ICLK2 CK
SR REV
SR
REV Input Path DS312-2_19_030105
Notes:
1. All IOB signals communicating with the FPGA’s internal logic have the option of inverting polarity inside the IOB.
2. Signals shown with dashed lines connect to the adjacent IOB in a differential pair only, not to the FPGA fabric.
Figure 1: Simplified IOB Diagram

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Input Delay Functions The delay values are set up in the silicon once at configura-
tion time—they are non-modifiable in device operation.
Each IOB has a programmable delay block that can delay
the input signal from 0 to nominally 4000 ps. In Figure 2, the The primary use for the input delay element is as an ade-
signal is first delayed by either 0 or 2000 ps (nominal) and is quate delay to ensure that there is no hold time requirement
then applied to an 8 tap delay line. This delay line has a when using the input flip-flop(s) with a global clock. The
nominal value of 250 ps per tap. All 8 taps are available via necessary value for this function is chosen by the Xilinx soft-
a multiplexer for use as an asynchronous input directly into ware tools and depends on device size. If the design is
the FPGA fabric. In this way, the delay is programmable using a DCM in the clock path, then the delay element can
from 0 to 4000 ps in 250 ps steps. Four of the 8 taps are be safely set to zero in the user's design, and there is still no
also available via a multiplexer to the D inputs of the syn- hold time requirement.
chronous storage elements. The delay inserted in the path Both asynchronous and synchronous values can be modi-
to the storage element can be varied from 0 to 4000 ps in fied by the user, which is useful where extra delay is
500 ps steps. The first, coarse delay element is common to required on clock or data inputs, for example, in interfaces to
both asynchronous and synchronous paths, and must be various types of RAM.
either used or not used for both paths.
See Module 3 of the Spartan-3E data sheet for exact values
for the delay elements.
Synchronous input (IQ1)

D Q
Synchronous input (IQ2)

D Q
PAD
Asynchronous input (I) DS312-2_18_022205
Figure 2: Input Delay Elements

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Storage Element Functions This is accomplished by taking data synchronized to the

clock signal’s rising edge and converting it to bits syn-
There are three pairs of storage elements in each IOB, one
chronized on both the rising and the falling edge. The com-
pair for each of the three paths. It is possible to configure
bination of two registers and a multiplexer is referred to as a
each of these storage elements as an edge-triggered
Double-Data-Rate D-type flip-flop (ODDR2).
D-type flip-flop (FD) or a level-sensitive latch (LD).
Table 1 describes the signal paths associated with the stor-
The storage-element pair on either the Output path or the
age element.
Three-State path can be used together with a special multi-
plexer to produce Double-Data-Rate (DDR) transmission.
Table 1: Storage Element Signal Description

Storage
Element
Signal Description Function
D Data input Data at this input is stored on the active edge of CK and enabled by CE. For latch
operation when the input is enabled, data passes directly to the output Q.
Q Data output The data on this output reflects the state of the storage element. For operation as a latch
in transparent mode, Q mirrors the data at D.
CK Clock input Data is loaded into the storage element on this input’s active edge with CE asserted.
CE Clock Enable input When asserted, this input enables CK. If not connected, CE defaults to the asserted
state.
SR Set/Reset input This input forces the storage element into the state specified by the SRHIGH/SRLOW
attributes. The SYNC/ASYNC attribute setting determines if the SR input is
synchronized to the clock or not. If both SR and REV are active at the same time, the
storage element gets a value of 0.
REV Reverse input This input is used together with SR. It forces the storage element into the state opposite
from what SR does. The SYNC/ASYNC attribute setting determines whether the REV
input is synchronized to the clock or not. If both SR and REV are active at the same time,
the storage element gets a value of 0.
As shown in Figure 1, the upper registers in both the output trols the CE inputs for the register pair on the three-state
and three-state paths share a common clock. The OTCLK1 path and ICE does the same for the register pair on the
clock signal drives the CK clock inputs of the upper registers input path.
on the output and three-state paths. Similarly, OTCLK2 The Set/Reset (SR) line entering the IOB controls all six
drives the CK inputs for the lower registers on the output registers, as is the Reverse (REV) line.
and three-state paths. The upper and lower registers on the In addition to the signal polarity controls described in IOB
input path have independent clock lines: ICLK1 and ICLK2. Overview, each storage element additionally supports the
The OCE enable line controls the CE inputs of the upper controls described in Table 2.
and lower registers on the output path. Similarly, TCE con-
Table 2: Storage Element Options

Option Switch Function Specificity
FF/Latch Chooses between an edge-triggered flip-flop Independent for each storage element
or a level-sensitive latch
SYNC/ASYNC Determines whether the SR set/reset control is Independent for each storage element
synchronous or asynchronous

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Table 2: Storage Element Options

Option Switch Function Specificity
SRHIGH/SRLOW Determines whether SR acts as a Set, which Independent for each storage element, except
forces the storage element to a logic "1" when using ODDR2. In the latter case, the selection
(SRHIGH) or a Reset, which forces a logic "0" for the upper element will apply to both elements.
(SRLOW)
INIT1/INIT0 When Global Set/Reset (GSR) is asserted or Independent for each storage element, except
after configuration this option specifies the when using ODDR2, which uses two IOBs. In the
initial state of the storage element, either set ODDR2 case, selecting INIT0 for one IOBs applies
(INIT1) or reset (INIT0). By default, choosing to both elements within the IOB, although INIT1
SRLOW also selects INIT0; choosing SRHIGH could be selected for the elements in the other IOB.
also selects INIT1.
Double-Data-Rate Transmission The storage-element pair on the Three-State path (TFF1

and TFF2) also can be combined with a local multiplexer to
Double-Data-Rate (DDR) transmission describes the tech-
form a DDR primitive. This permits synchronizing the output
nique of synchronizing signals to both the rising and falling
enable to both the rising and falling edges of a clock. This
edges of the clock signal. Spartan-3E devices use register
DDR operation is realized in the same way as for the output
pairs in all three IOB paths to perform DDR operations.
path.
The pair of storage elements on the IOB’s Output path
The storage-element pair on the input path (IFF1 and IFF2)
(OFF1 and OFF2), used as registers, combine with a spe-
allows an I/O to receive a DDR signal. An incoming DDR
cial multiplexer to form a DDR D-type flip-flop (ODDR2).
clock signal triggers one register, and the inverted clock sig-
This primitive permits DDR transmission where output data
nal triggers the other register. The registers take turns cap-
bits are synchronized to both the rising and falling edges of
turing bits of the incoming DDR data signal. The primitive to
a clock. DDR operation requires two clock signals (usually
allow this functionality is called IDDR2.
50% duty cycle), one the inverted form of the other. These
signals trigger the two registers in alternating fashion, as Aside from high bandwidth data transfers, DDR outputs also
shown in Figure 3. The Digital Clock Manager (DCM) gen- can be used to reproduce, or mirror, a clock signal on the
erates the two clock signals by mirroring an incoming signal, output. This approach is used to transmit clock and data sig-
and then shifting it 180 degrees. This approach ensures nals together (source synchronously). A similar approach is
minimal skew between the two signals. Alternatively, the used to reproduce a clock signal at multiple outputs. The
inverter inside the IOB can be used to invert the clock sig- advantage for both approaches is that skew across the out-
nal, thus only using one clock line and both rising and falling puts is minimal.
edges of that clock line as the two clocks for the DDR
flip-flops.
DCM DCM
180˚ 0˚ 0˚
FDDR FDDR
D1 D1
Q1 Q1
CLK1 CLK1
DDR MUX Q DDR MUX Q
D2 D2
Q2 Q2
CLK2 CLK2
DS312-2_20_021105
Figure 3: Two Methods for Clocking the DDR Register

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Register Cascade Feature

In the Spartan-3E family, one of the IOBs in a differential D Q D1
pair can cascade either its input or output storage elements
with those in the other IOB of the differential pair. This is PAD
intended to make DDR operation at high speed much sim- To Fabric
pler to implement. The new DDR connections that are avail- IDDRIN2
IQ2
able are shown in Figure 1 (dashed lines), and are only D Q D Q D2
available for routing between IOBs and are not accessible to
the FPGA fabric. Note that this feature is only available
when using differential I/O.
ICLK1
IDDR2
ICLK2
As a DDR input pair, the master IOB registers incoming
data on the rising edge of ICLK1 (= D1) and the rising edge
of ICLK2 (= D2), which is typically the same as the falling ICLK1
edge of ICLK1. This data is then transferred into the FPGA ICLK2
fabric. At some point, both signals must be brought into the
same clock domain, typically ICLK1. This can be difficult at PAD d d+1 d+2 d+3 d+4 d+5 d+6 d+7 d+8
high frequencies because the available time is only one half D1 d d+2 d+4 d+6 d+8
of a clock cycle assuming a 50% duty cycle. See Figure 4
D2 d-1 d+1 d+3 d+5 d+7
for a graphical illustration of this function.
DS312-2_22_030105
In the Spartan-3E device, the signal D2 can be cascaded
into the storage element of the adjacent slave IOB. There it Figure 5: Input DDR Using Spartan-3E Cascade Feature
is re-registered to ICLK1, and only then fed to the FPGA
ODDR2
fabric where it is now already in the same time domain as
D1. Here, the FPGA fabric uses only the clock ICLK1 to pro- As a DDR output pair, the master IOB registers data coming
cess the received data. See Figure 5 for a graphical illustra- from the FPGA fabric on the rising edge of OCLK1 (= D1)
tion of this function. and the rising edge of OCLK2 (= D2), which is typically the
same as the falling edge of OCLK1. These two bits of data
are multiplexed by the DDR mux and forwarded to the out-
D Q D1 put pin. At some point in the FPGA fabric, the signal D2
must be brought into the clock domain OCLK2 from the
PAD domain OCLK1. This can be difficult at high frequencies,
To Fabric
because the time available is only one half a clock cycle.
See Figure 6 for a graphical illustration of this function.
D Q D2
In the Spartan-3E device, the signal D2 can be cascaded
via the storage element of the adjacent slave IOB. Here, it is
ICLK2 registered by OCLK1 and then forwarded to the master IOB
ICLK1 where it is re-registered to OCLK2, selected as usual by the
DDR multiplexer, and then forwarded to the output pin. This
way the data for transmission can be processed using just
ICLK1 the clock OCLK1 in the FPGA fabric. See Figure 7 for a
ICLK2 graphical illustration of this function.
PAD d d+1 d+2 d+3 d+4 d+5 d+6 d+7 d+8

D1 d d+2 d+4 d+6 d+8
D2 d-1 d+1 d+3 d+5 d+7
DS312-2_21_021105
Figure 4: Input DDR (without Cascade Feature)

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D1 D Q D1 D Q
PAD PAD
From From
Fabric Fabric
ODDROUT1
D2 D Q D2 D Q D Q
ODDRIN2
OCLK1 OCLK1
OCLK2 OCLK2
OCLK1 OCLK1
OCLK2 OCLK2
D1 d d+2 d+4 d+6 d+8 d+10 D1 d d+2 d+4 d+6 d+8
D2 d+1 d+3 d+5 d+7 d+9 D2 d+1 d+3 d+5 d+7 d+9
PAD d+5 d+6 d+7 d+8 PAD d d+1 d+2 d+3 d+4 d+5 d+6 d+7 d+8
d d+1 d+2 d+3 d+4
DS312-2_23_030105 DS312-2_36_030105
Figure 6: Output DDR (without Cascade Feature) Figure 7: Output DDR Using Spartan-3E Cascade
Feature
SelectIO Signal Standards

The Spartan-3E I/Os feature inputs and outputs that sup-
port a wide range of I/O signaling standards (Table 3 and
Table 4). The majority of the I/Os also can be used to form
differential pairs to support any of the differential signaling
standards (Table 4).
To define the I/O signaling standard in a design, set the
IOSTANDARD attribute to the appropriate setting. Xilinx
provides a variety of different methods for applying the
IOSTANDARD for maximum flexibility. For a full description
of different methods of applying attributes to control
IOSTANDARD, refer to “Entry Strategies for Xilinx Con-
straints” in the Xilinx Software Manuals and Help.
Spartan-3E FPGAs provide additional input flexibility by
allowing I/O standards to be mixed in different banks. Spe-
cial care must be taken to ensure the input voltages do not
exceed VCCO (see Module 3 for the specifications). For a
particular VCCO voltage, Table 3 and Table 4 list all of the
IOSTANDARDs that can be combined and if the IOSTAN-
DARD is supported as an input only or can be used for both
inputs and outputs.

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Table 3: Single-Ended IOSTANDARD Bank Compatibility

VCCO Supply/Compatibility Input Requirements
Board
VREF for
Single-Ended Termination
Inputs
IOSTANDARD 1.2 V 1.5 V 1.8 V 2.5 V 3.0 V 3.3 V Voltage (VTT)
Input/
LVTTL - - - - - N/R N/R
Output
Input/
LVCMOS33 - - - - - N/R N/R
Output
Input/
LVCMOS25 - - - Input Input N/R N/R
Output
Input/
LVCMOS18 - - Input Input Input N/R N/R
Output
Input/
LVCMOS15 - Input Input Input Input N/R N/R
Output
Input/
LVCMOS12 Input Input Input Input Input N/R(1) N/R
Output
Input/
PCI33_3 - - - - Input N/R N/R
Output
Input/
PCI66_3 - - - - Input N/R N/R
Output
Input/
PCIX Input N/R N/R
Output
Input/
HSTL_I_18 - - Input Input Input 0.9 0.9
Output
Input/
HSTL_III_18 - - Input Input Input 1.1 1.8
Output
Input/
SSTL18_I - - Input Input Input 0.9 0.9
Output
Input/
SSTL2_I - - - Input Input 1.25 1.25
Output
Notes:
1. N/R - Not required for input operation.

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Table 4: Differential IOSTANDARD Bank Compatibility

Differential VCCO Supply
Input Requirements: VREF
IOSTANDARD 2.5V 3.3V
Input,
LVDS_25 On-chip Differential Termination, Input
Output(1)
Input,
RSDS_25 On-chip Differential Termination, Input
Output(1)
Input, N/R
MINI_LVDS_25 On-chip Differential Termination, Input (Not Required)
Output(1)
Input,
LVPECL_25 Input
On-chip Differential Termination
Input,
BLVDS_25 On-chip Differential Termination, Input
Output
Notes:
1. Each bank can support any two of the following: LVDS_25 outputs, MINI_LVDS_25 outputs, RSDS_25 outputs.
HSTL and SSTL inputs use the Reference Voltage (VREF) to (See Module 3 for the specific range). The on-chip input dif-
bias the input-switching threshold. Once a configuration ferential termination in Spartan-3E devices eliminates the
data file is loaded into the FPGA that calls for the I/Os of a external 100Ω termination resistor commonly found in dif-
given bank to use HSTL/SSTL, a few specifically reserved ferential receiver circuits. Use differential termination for
I/O pins on the same bank automatically convert to VREF LVDS, mini-LVDS, and BLVDS as applications permit.
inputs. For banks that do not contain HSTL or SSTL, VREF On-chip Differential Termination is available in banks with
pins remain available for user I/Os or input pins. VCCO = 2.5V and is not supported on dedicated input pins.
Differential standards employ a pair of signals, one the Set the DIFF_TERM attribute to TRUE to enable Differential
opposite polarity of the other. The noise canceling proper- Termination on a differential I/O pin pair.
ties (for example, Common-Mode Rejection) of these stan- The DIFF_TERM attribute uses the following syntax in the
dards permit exceptionally high data transfer rates. This UCF file:
subsection introduces the differential signaling capabilities
INST <I/O_BUFFER_INSTANTIATION_NAME>
of Spartan-3E devices.
DIFF_TERM = “<TRUE/FALSE>”;
Each device-package combination designates specific I/O
pairs specially optimized to support differential standards.
Differential pairs can be shown in the Pin and Area Con- Spartan-3E Z0 = 50Ω Spartan-3E
Differential Differential Input
straints Editor (PACE) with the “Show Differential Pairs” Output
100Ω
option. A unique L-number, part of the pin name, identifies

the line-pairs associated with each bank (see Module 4).
For each pair, the letters P and N designate the true and Z0 = 50Ω
inverted lines, respectively. For example, the pin names
IO_L43P_3 and IO_L43N_3 indicate the true and inverted Spartan-3E
lines comprising the line pair L43 on Bank 3. Differential Input
Spartan-3E with On-Chip
Z0 = 50Ω Differential
VCCO provides current to the outputs and additionally pow- Differential
Output Terminator
ers the On-Chip Differential Termination. VCCO must be
100Ω
2.5V when using the On-Chip Differential Termination. The

VREF lines are not required for differential operation.
Z0 = 50Ω
To further understand how to combine multiple IOSTAN- DS312-2_24_021505
DARDs within a bank, refer to IOBs Organized into Banks,
page 10. Figure 8: Differential Inputs and Outputs
On-Chip Differential Termination Pull-Up and Pull-Down Resistors

Spartan-3E devices provide an on-chip 100Ω differential Pull-up and pull-down resistors inside each IOB optionally
termination across the input differential receiver terminals force a floating I/O pin to a determined state. Pull-up and

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pull-down resistors are commonly applied to unused I/Os, To adjust the drive strength for each output set the DRIVE
inputs, and three-state outputs, but can be used on any I/O. attribute to the desired drive strength: 2, 4, 6, 8, 12, and 16.
The pull-up resistor connects an I/O to VCCO through a
resistor. The resistance value depends on the VCCO voltage
Table 5: Programmable Output Drive Current
(see Module 3 for the specifications). The pull-down resistor
similarly connects an I/O to ground with a resistor. The PUL- Output Drive Current (mA)
Signal
LUP and PULLDOWN attributes and library primitives turn
Standard 2 4 6 8 12 16
on these optional resistors.
By default, PULLDOWN resistors terminate all unused I/Os. LVTTL
Unused I/Os can alternatively be set to PULLUP or FLOAT.
LVCMOS33
To change the unused I/O Pad setting, set the Bitstream
Generator (BitGen) option UnusedPin to PULLUP, PULL- LVCMOS25 -
DOWN, or FLOAT. The UnusedPin option is accessed
through the Properties for Generate Programming File in LVCMOS18 - -
ISE. LVCMOS15 - - -
During configuration a Low logic level on HSWAP activates
LVCMOS12 - - - - -
the pull-up resistors for all I/Os not used directly in the
selected configuration mode.
High output current drive strength and FAST output slew
rates generally result in fastest I/O performance. However,
Keeper Circuit these same settings generally also result in transmission
Each I/O has an optional keeper circuit (see Figure 9) that line effects on the printed circuit board (PCB) for all but the
keeps bus lines from floating when not being actively driven. shortest board traces. Each IOB has independent slew rate
The KEEPER circuit retains the last logic level on a line after and drive strength controls. Use the slowest slew rate and
all drivers have been turned off. Apply the KEEPER lowest output drive current that meets the performance
attribute or use the KEEPER library primitive to use the requirements for the end application.
KEEPER circuitry. Pull-up and pull-down resistors override
Likewise, due to lead inductance, a given package supports
the KEEPER settings.
a limited number of simultaneous switching outputs (SSOs)
when using fast, high-drive outputs. Only use fast,
Weak Pull-up high-drive outputs when required by the application.
IOBs Organized into Banks

Output Path The Spartan-3E architecture organizes IOBs into four I/O
Input Path banks as shown in Figure 10. Each bank maintains sepa-
rate VCCO and VREF supplies. The separate supplies allow
Keeper each bank to independently set VCCO. Similarly, the VREF
Weak Pull-down supplies may be set for each bank. Refer to Table 3 and
Table 4 for VCCO and VREF requirements.
DS312-2_25_022805
When working with Spartan-3E devices, most of the differ-
Figure 9: Keeper Circuit
ential I/O standards are compatible and can be combined
within any given bank. Each bank can support any two of
Slew Rate Control and Drive Strength the following differential standards: LVDS_25 outputs,
Each IOB has a slew-rate control that sets the output MINI_LVDS_25 outputs, and RSDS_25 outputs. As an
switching edge-rate for LVCMOS and LVTTL outputs. The example, LVDS_25 outputs, RSDS_25 outputs, and any
SLEW attribute controls the slew rate and can either be set other differential inputs while using on-chip differential ter-
to SLOW (default) or FAST. mination are a valid combination. A combination not allowed
Each LVCMOS and LVTTL output additionally supports up is a single bank with LVDS_25 outputs, RSDS_25 outputs,
to six different drive current strengths as shown in Table 5. and MINI_LVDS_25 outputs.

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are outlined for each package, such as pins that are uncon-
nected on one device but connected on another in the same
Bank 0
package or pins that are dedicated inputs on one package
but full I/O on another. When designing the printed circuit
board (PCB), plan for potential future upgrades and pack-
Bank 3 age migration.
Bank 1
The Spartan-3E family is not pin-compatible with any previ-
ous Xilinx FPGA family.
Dedicated Inputs
Bank 2
Dedicated Inputs are IOBs used only as inputs. Pin names
DS312-2_26_021205 designate a Dedicated Input if the name starts with IP, for
Figure 10: Spartan-3E I/O Banks (top view) example, IP or IP_Lxxx_x. Dedicated inputs retain the full
functionality of the IOB for input functions with a single
I/O Banking Rules exception for differential inputs (IP_Lxxx_x). For the differ-
ential Dedicated Inputs, the on-chip differential termination
When assigning I/Os to banks, these VCCO rules must be
is not available. To replace the on-chip differential termina-
followed:
tion, choose a differential pair that supports outputs
1. All VCCO pins on the FPGA must be connected even if a (IO_Lxxx_x) or use an external 100Ω termination resistor on
bank is unused. the board.
2. All VCCO lines associated within a bank must be set to
the same voltage level. ESD Protection
3. The VCCO levels used by all standards assigned to the Clamp diodes protect all device pads against damage from
I/Os of any given bank must agree. The Xilinx Electro-Static Discharge (ESD) as well as excessive voltage
development software checks for this. Table 3 and transients. Each I/O has two clamp diodes: one diode
Table 4 describe how different standards use the VCCO extends P-to-N from the pad to VCCO and a second diode
supply. extends N-to-P from the pad to GND. During operation,
these diodes are normally biased in the off state. These
4. If a bank does not have any VCCO requirements,
clamp diodes are always connected to the pad, regardless
connect VCCO to an available voltage, such as 2.5V or
of the signal standard selected. The presence of diodes lim-
3.3V. Some configuration modes might place additional
its the ability of Spartan-3E I/Os to tolerate high signal volt-
VCCO requirements. Refer to Configuration, page 56
ages. The VIN absolute maximum rating in Table 1 of
for more information.
Module 3 specifies the voltage range that I/Os can tolerate.
If any of the standards assigned to the Inputs of the bank
use VREF, then the following additional rules must be Supply Voltages for the IOBs
observed:
The IOBs are powered by three supplies:
1. All VREF pins must be connected within a bank.
1. The VCCO supplies, one for each of the FPGA’s I/O
2. All VREF lines associated with the bank must be set to banks, power the output drivers. The voltage on the
the same voltage level. VCCO pins determines the voltage swing of the output
3. The VREF levels used by all standards assigned to the signal.
Inputs of the bank must agree. The Xilinx development 2. VCCINT is the main power supply for the FPGA’s internal
software checks for this. Table 3 describes how different logic.
standards use the VREF supply.
3. VCCAUX is an auxiliary source of power, primarily to
If VREF is not required to bias the input switching thresholds, optimize the performance of various FPGA functions
all associated VREF pins within the bank can be used as such as I/O switching.
user I/Os or input pins.
The I/Os During Power-On, Configuration, and
Package Footprint Compatibility User Mode
Sometimes, applications outgrow the logic capacity of a All I/Os have ESD clamp diodes to their respective VCCO
specific Spartan-3E FPGA. Fortunately, the Spartan-3E supply and from GND, as shown in Figure 1. The VCCINT
family is designed so that multiple part types are available in (1.2V), VCCAUX (2.5V), and VCCO supplies can be applied in
pin-compatible package footprints, as described in Module any order. Before the FPGA can start its configuration pro-
4. In some cases, there are subtle differences between cess, VCCINT, VCCO Bank 2, and VCCAUX must have
devices available in the same footprint. These differences reached their respective minimum recommended operating

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levels (see Table 2 of Module 3). At this time, all I/O drivers loaded design reverses the polarity of their respective SR
are in a high-impedance state. VCCO Bank 2, VCCINT, and inputs.
VCCAUX serve as inputs to the internal Power-On Reset cir- The Global Three State (GTS) net is released during
cuit (POR). Start-Up, marking the end of configuration and the begin-
A Low level applied to the HSWAP input enables pull-up ning of design operation in the User mode. After the GTS
resistors on User I/Os from power-on throughout configura- net is released, all user I/Os go active while all unused I/Os
tion. A High level on HSWAP disables the pull-up resistors, are weakly pulled down (PULLDOWN). The designer can
allowing the I/Os to float. HSWAP contains a weak pull-up control how the unused I/Os are terminated after GTS is
and defaults to High if left floating. As soon as power is released by setting the Bitstream Generator (BitGen) option
applied, the FPGA begins initializing its configuration mem- UnusedPin to PULLUP, PULLDOWN, or FLOAT.
ory. At the same time, the FPGA internally asserts the Glo- One clock cycle later (default), the Global Write Enable
bal Set-Reset (GSR), which asynchronously resets all IOB (GWE) net is released allowing the RAM and registers to
storage elements to a default Low state. change states. Once in User mode, any pull-up resistors
Upon the completion of initialization and the beginning of enabled by HSWAP revert to the user settings and HSWAP
configuration, INIT_B goes High, sampling the M0, M1, and is available as a general-purpose I/O. For more information
M2 inputs to determine the configuration mode. At this point on PULLUP and PULLDOWN, see Pull-Up and Pull-Down
in time, the configuration data is loaded into the FPGA. The Resistors.
I/O drivers remain in a high-impedance state (with or with-
out pull-up resistors, as determined by the HSWAP input) JTAG Boundary-Scan Capability
throughout configuration. All Spartan-3E IOBs support boundary-scan testing com-
At the end of configuration, the GSR net is released, placing patible with IEEE 1149.1/1532 standards. See JTAG Mode,
the IOB registers in a Low state by default, unless the page 86 for more information on programming via JTAG.

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Configurable Logic Block (CLB) and and additional multiplexers and carry logic simplify wide
Slice Resources logic and arithmetic functions. Most general-purpose logic
in a design is automatically mapped to the slice resources in
CLB Overview the CLBs. Each CLB is identical, and the Spartan-3E family
CLB structure is identical to that for the Spartan-3 family.
The Configurable Logic Blocks (CLBs) constitute the main
logic resource for implementing synchronous as well as CLB Array
combinatorial circuits. Each CLB contains four slices, and
each slice contains two Look-Up Tables (LUTs) to imple- The CLBs are arranged in a regular array of rows and col-
ment logic and two dedicated storage elements that can be umns as shown in Figure 11.
used as flip-flops or latches. The LUTs can be used as a Each density varies by the number of rows and columns of
16x1 memory (RAM16) or as a 16-bit shift register (SRL16), CLBs (see Table 6).
X0Y3 X1Y3 X2Y3 X3Y3
X0Y2 X1Y2 X2Y2 X3Y2
X0Y1 X1Y1 X2Y1 X3Y1

Spartan-3E
FPGA
X0Y0 X1Y0 X2Y0 X3Y0
IOBs
Slice
CLB DS312-2_31_021205
Figure 11: CLB Locations
Table 6: Spartan-3E CLB Resources

CLB CLB CLB LUTs / Equivalent RAM16 / Distributed
Device Rows Columns Total(1) Slices Flip-Flops Logic Cells SRL16 RAM Bits
XC3S100E 22 16 240 960 1920 2160 960 15360
XC3S250E 34 26 612 2448 4896 5508 2448 39168
XC3S500E 46 34 1164 4656 9312 10476 4656 74496
XC3S1200E 60 46 2168 8672 17344 19512 8672 138752
XC3S1600E 76 58 3688 14752 29504 33192 14752 236032
Notes:
1. The number of CLBs is less than the multiple of the rows and columns because the block RAM/multiplier blocks and the DCMs are
embedded in the array (see Module 1, Figure 1).
Slices LUTs support both logic and memory (including both

RAM16 and SRL16 shift registers) while half support logic
Each CLB comprises four interconnected slices, as shown
only, and the two types alternate throughout the array col-
in Figure 13. These slices are grouped in pairs. Each pair is
umns. The SLICEL reduces the size of the CLB and lowers
organized as a column with an independent carry chain.
the cost of the device, and can also provide a performance
The left pair supports both logic and memory functions and
advantage over the SLICEM.
its slices are called SLICEM. The right pair supports logic
only and its slices are called SLICEL. Therefore half the

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WF[4:1]
DS312-2_32_021205
Notes:
1. Options to invert signal polarity as well as other options that enable lines for various functions are not shown.
2. The index i can be 6, 7, or 8, depending on the slice. The upper SLICEL has an F8MUX, and the upper SLICEM has
an F7MUX. The lower SLICEL and SLICEM both have an F6MUX.
Figure 12: Simplified Diagram of the Left-Hand SLICEM

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Left-Hand SLICEM Right-Hand SLICEL

(Logic or Distributed RAM (Logic Only)
or Shift Register)
COUT
CLB
SLICE
X1Y1
SLICE
X1Y0
COUT
Switch Interconnect
Matrix CIN to Neighbors
SLICE
X0Y1
SHIFTOUT
SHIFTIN
SLICE
X0Y0
CIN DS099-2_05_082104
Figure 13: Arrangement of Slices within the CLB
Slice Location Designations Slice Overview

The Xilinx development software designates the location of A slice includes two LUT function generators and two stor-
a slice according to its X and Y coordinates, starting in the age elements, along with additional logic, as shown in
bottom left corner, as shown in Figure 11. The letter ’X’ fol- Figure 14.
lowed by a number identifies columns of slices, increment-
Both SLICEM and SLICEL have the following elements in
ing from the left side of the die to the right. The letter ’Y’
common to provide logic, arithmetic, and ROM functions:
followed by a number identifies the position of each slice in
a pair as well as indicating the CLB row, incrementing from • Two 4-input LUT function generators, F and G
the bottom of the die. Figure 13 shows the CLB located in • Two storage elements
the lower left-hand corner of the die. The SLICEM always • Two wide-function multiplexers, F5MUX and FiMUX
has an even ’X’ number, and the SLICEL always has an odd • Carry and arithmetic logic
’X’ number.
SRL16 FiMUX FiMUX

RAM16
LUT4 (G)
Carry LUT4 (G)
Carry
Register Register
F5MUX F5MUX
SRL16
RAM16 Carry Register Carry Register
LUT4 (F) LUT4 (F)
Arithmetic Logic Arithmetic Logic
SLICEM SLICEL DS312-2_13_020905
Figure 14: Resources in a Slice

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The SLICEM pair supports two additional functions: Enable (CE), Slice Write Enable (SLICEWE1), and
• Two 16x1 distributed RAM blocks, RAM16 Reset/Set (RS) are shared in common between the two
halves.
• Two 16-bit shift registers, SRL16
The LUTs located in the top and bottom portions of the slice
Each of these elements is described in more detail in the fol-
are referred to as "G" and "F", respectively, or the "G-LUT"
lowing sections.
and the "F-LUT". The storage elements in the top and bot-
tom portions of the slice are called FFY and FFX, respec-
Logic Cells
tively.
The combination of a LUT and a storage element is known
Each slice has two multiplexers with F5MUX in the bottom
as a "Logic Cell". The additional features in a slice, such as
portion of the slice and FiMUX in the top portion. Depending
the wide multiplexers, carry logic, and arithmetic gates, add
on the slice, the FiMUX takes on the name F6MUX,
to the capacity of a slice, implementing logic that would oth-
F7MUX, or F8MUX, according to its position in the multi-
erwise require additional LUTs. Benchmarks have shown
plexer chain. The lower SLICEL and SLICEM both have an
that the overall slice is equivalent to 2.25 simple logic cells.
F6MUX. The upper SLICEM has an F7MUX, and the upper
This calculation provides the equivalent logic cell count
SLICEL has an F8MUX.
shown in Table 6.
The carry chain enters the bottom of the slice as CIN and
Slice Details exits at the top as COUT. Five multiplexers control the chain:
CYINIT, CY0F, and CYMUXF in the bottom portion and
Figure 16 is a detailed diagram of the SLICEM. It represents
CY0G and CYMUXG in the top portion. The dedicated arith-
a superset of the elements and connections to be found in
metic logic includes the exclusive-OR gates XORF and
all slices. The dashed and gray lines (blue when viewed in
XORG (bottom and top portions of the slice, respectively)
color) indicate the resources found only in the SLICEM and
as well as the AND gates FAND and GAND (bottom and top
not in the SLICEL.
portions, respectively).
Each slice has two halves, which are differentiated as top
See Table 7 for a description of all the slice input and output
and bottom to keep them distinct from the upper and lower
signals.
slices in a CLB. The control inputs for the clock (CLK), Clock
Table 7: Slice Inputs and Outputs

Name Location Direction Description
F[4:1] SLICEL/M Bottom Input F-LUT and FAND inputs
G[4:1] SLICEL/M Top Input G-LUT and GAND inputs or Write Address (SLICEM)
BX SLICEL/M Bottom Input Bypass to or output (SLICEM) or storage element, or control input to
F5MUX, input to carry logic, or data input to RAM (SLICEM)
BY SLICEL/M Top Input Bypass to or output (SLICEM) or storage element, or control input to
FiMUX, input to carry logic, or data input to RAM (SLICEM)
BXOUT SLICEM Bottom Output BX bypass output
BYOUT SLICEM Top Output BY bypass output
ALTDIG SLICEM Top Input Alternate data input to RAM
DIG SLICEM Top Output ALTDIG or SHIFTIN bypass output
SLICEWE1 SLICEM Common Input RAM Write Enable
F5 SLICEL/M Bottom Output Output from F5MUX; direct feedback to FiMUX
FXINA SLICEL/M Top Input Input to FiMUX; direct feedback from F5MUX or another FiMUX
FXINB SLICEL/M Top Input Input to FiMUX; direct feedback from F5MUX or another FiMUX
Fi SLICEL/M Top Output Output from FiMUX; direct feedback to another FiMUX
CE SLICEL/M Common Input FFX/Y Clock Enable
SR SLICEL/M Common Input FFX/Y Set or Reset or RAM Write Enable (SLICEM)

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Table 7: Slice Inputs and Outputs (Continued)

Name Location Direction Description
CLK SLICEL/M Common Input FFX/Y Clock or RAM Clock (SLICEM)
SHIFTIN SLICEM Top Input Data input to G-LUT RAM
SHIFTOUT SLICEM Bottom Output Shift data output from F-LUT RAM
CIN SLICEL/M Bottom Input Carry chain input
COUT SLICEL/M Top Output Carry chain output
X SLICEL/M Bottom Output Combinatorial output
Y SLICEL/M Top Output Combinatorial output
XB SLICEL/M Bottom Output Combinatorial output from carry or F-LUT SRL16 (SLICEM)
YB SLICEL/M Top Output Combinatorial output from carry or G-LUT SRL16 (SLICEM)
XQ SLICEL/M Bottom Output FFX output
YQ SLICEL/M Top Output FFY output
Main Logic Paths BY in the top half) can take any of several possible
branches:
Central to the operation of each slice are two nearly identi-
cal data paths at the top and bottom of the slice. The 1. Bypass both the LUT and the storage element, and
description that follows uses names associated with the bot- then exit the slice as BXOUT (or BYOUT) and return to
tom path. (The top path names appear in parentheses.) The interconnect.
basic path originates at an interconnect switch matrix out- 2. Bypass the LUT, and then pass through a storage
side the CLB. See Interconnect for more information on the element via the D input before exiting as XQ (or YQ).
switch matrix and the routing connections.
3. Control the wide function multiplexer F5MUX (or
Four lines, F1 through F4 (or G1 through G4 on the upper FiMUX).
path), enter the slice and connect directly to the LUT. Once
4. Via multiplexers, serve as an input to the carry chain.
inside the slice, the lower 4-bit path passes through a LUT
"F" (or "G") that performs logic operations. The LUT Data 5. Drive the DI input of the LUT.
output, "D", offers five possible paths: 6. BY can control the REV inputs of both the FFY and FFX
1. Exit the slice via line "X" (or "Y") and return to storage elements. See Storage Element Functions.
interconnect. 7. Finally, the DIG_MUX multiplexer can switch BY onto
2. Inside the slice, "X" (or "Y") serves as an input to the the DIG line, which exits the slice.
DXMUX (or DYMUX) which feeds the data input, "D", of The control inputs CLK, CE, SR, BX and BY have program-
the FFY (or FFX) storage element. The "Q" output of mable polarity. The LUT inputs do not need programmable
the storage element drives the line XQ (or YQ) which polarity because their function can be inverted inside the
exits the slice. LUT.
3. Control the CYMUXF (or CYMUXG) multiplexer on the The sections that follow provide more detail on individual
carry chain. functions of the slice.
4. With the carry chain, serve as an input to the XORF (or
XORG) exclusive-OR gate that performs arithmetic Look-Up Tables
operations, producing a result on "X" (or "Y"). The Look-Up Table or LUT is a RAM-based function gener-
5. Drive the multiplexer F5MUX to implement logic ator and is the main resource for implementing logic func-
functions wider than four bits. The "D" outputs of both tions. Furthermore, the LUTs in each SLICEM pair can be
the F-LUT and G-LUT serve as data inputs to this configured as Distributed RAM or a 16-bit shift register, as
multiplexer. described later.
In addition to the main logic paths described above, there Each of the two LUTs (F and G) in a slice have four logic
are two bypass paths that enter the slice as BX and BY. inputs (A1-A4) and a single output (D). Any four-variable
Once inside the FPGA, BX in the bottom half of the slice (or Boolean logic operation can be implemented in one LUT.
Functions with more inputs can be implemented by cascad-

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ing LUTs or by using the wide function multiplexers that are Wide Multiplexers
described later.
Wide-function multiplexers effectively combine LUTs in
The output of the LUT can connect to the wide multiplexer order to permit more complex logic operations. Each slice
logic, the carry and arithmetic logic, or directly to a CLB out- has two of these multiplexers with F5MUX in the bottom por-
put or to the CLB storage element. See Figure 15. tion of the slice and FiMUX in the top portion. The F5MUX
multiplexes the two LUTs in a slice. The FiMUX multiplexes
Y
two CLB inputs which connect directly to the F5MUX and
FiMUX results from the same slice or from other slices. See
Figure 16.
G[4:1] A[4:1] D YQ
FFY
G-LUT
4
F[4:1] A[4:1] D XQ
FFX
F-LUT
DS312-2_33_022205
Figure 15: LUT Resources in a Slice
FiMUX
FXINA 1
FX (Local Feedback to FXIN)
FXINB 0
Y (General Interconnect)
BY
D Q YQ
F5MUX
F[4:1] LUT 1
F5 (Local Feedback to FXIN)
G[4:1] LUT 0
X (General Interconnect)
BX
D Q XQ
x312-2_34_021205
Figure 16: Dedicated Multiplexers in Spartan-3E CLB
Depending on the slice, FiMUX takes on the name F6MUX, ate any function of five inputs, with four inputs duplicated to
F7MUX, or F8MUX. The designation indicates the number two LUTs and the fifth input controlling the mux. Because
of inputs possible without restriction on the function. For each LUT can implement independent 2:1 muxes, the
example, an F7MUX can generate any function of seven F5MUX can combine them to create a 4:1 mux, which is a
inputs. Figure 17 shows the names of the multiplexers in six-input function. If the two LUTs have completely indepen-
each position in the Spartan-3E CLB. The figure also dent sets of inputs, some functions of all nine inputs can be
includes the direct connections within the CLB, along with implemented. Table 8 shows the connections for each mul-
the F7MUX connection to the CLB below. tiplexer and the number of inputs possible for different types
Each mux can create logic functions of more inputs than of functions.
indicated by its name. The F5MUX, for example, can gener-

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FXINB
F8 X
FXINA
F5 F5
FXINB FX
F6
FXINA
F5
F5
FXINB
FX
F7
FXINA
F5 F5
FXINB
F6 FX
FXINA
F5 F5
DS312-2_38_021305
Figure 17: Muxes and Dedicated Feedback in

Spartan-3E CLB
Table 8: Mux Capabilities

Total Number of Inputs per Function
For Any For Limited
Mux Usage Input Source Function For Mux Functions
F5MUX F5MUX LUTs 5 6 (4:1 mux) 9
FiMUX F6MUX F5MUX 6 11 (8:1 mux) 19
F7MUX F6MUX 7 20 (16:1 mux) 39
F8MUX F7MUX 8 37 (32:1 mux) 79

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The wide multiplexers can be used by the automatic tools or Table 10: F5MUX Function
instantiated in a design using a component such as the
F5MUX. The symbol, signals, and function are described Inputs Outputs
below. The description is similar for the F6MUX, F7MUX, S I0 I1 O LO
and F8MUX. Each has versions with a general output, local
output, or both. 0 1 X 1 1
0 0 X 0 0
I0 0 LO 1 X 1 1 1
I1 1 O
1 X 0 0 0
S
DS312-2_35_021205
For more details on using the multiplexers, see XAPP466:
Figure 18: F5MUX with Local and General Outputs "Using Dedicated Multiplexers in Spartan-3 FPGAs".
Carry and Arithmetic Logic

Table 9: F5MUX Inputs and Outputs
The carry chain, together with various dedicated arithmetic
Signal Function logic gates, support fast and efficient implementations of
I0 Input selected when S is Low math operations. The carry logic is automatically used for
most arithmetic functions in a design. The gates and multi-
I1 Input selected when S is High plexers of the carry and arithmetic logic can also be used for
general-purpose logic, including simple wide Boolean func-
S Select input
tions.
LO Local Output that connects to the F5 or FX CLB The carry chain enters the slice as CIN and exits as COUT,
pins, which use local feedback to the FXIN controlled by several multiplexers. The carry chain connects
inputs to the FiMUX for cascading directly from one CLB to the CLB above. The carry chain
O General Output that connects to the can be initialized at any point from the BX (or BY) inputs.
general-purpose combinatorial or registered The dedicated arithmetic logic includes the exclusive-OR
outputs of the CLB gates XORF and XORG (upper and lower portions of the
slice, respectively) as well as the AND gates GAND and
FAND (upper and lower portions, respectively). These gates
work in conjunction with the LUTs to implement efficient
arithmetic functions, including counters and multipliers, typ-
ically at two bits per slice. See Figure 19 and Table 11.

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COUT
YB
CYMUXG Y
G[4:1] A[4:1] CYSELG
G1 G2 G-LUT
D YQ
XORG FFY
CY0G
GAND 1
0
BY
XB
1
4 CYMUXF X
F[4:1] A[4:1] CYSELF
F1 F2 F-LUT
D XQ
XORF FFX
CY0F
FAND CYINIT
1
0
BX
CIN DS312-2_14_021305
Figure 19: Carry Logic
Table 11: Carry Logic Functions

Function Description
CYINIT Initializes carry chain for a slice. Fixed selection of:
• CIN carry input from the slice below
• BX input
CY0F Carry generation for bottom half of slice. Fixed selection of:
• F1 or F2 inputs to the LUT (both equal 1 when a carry is to be generated)
• FAND gate for multiplication
• BX input for carry initialization
• Fixed "1" or "0" input for use as a simple Boolean function
CY0G Carry generation for top half of slice. Fixed selection of:
• G1 or G2 inputs to the LUT (both equal 1 when a carry is to be generated)
• GAND gate for multiplication
• BY input for carry initialization
• Fixed "1" or "0" input for use as a simple Boolean function
CYMUXF Carry generation or propagation mux for bottom half of slice. Dynamic selection via CYSELF of:
• CYINIT carry propagation (CYSELF = 1)
• CY0F carry generation (CYSELF = 0)

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Table 11: Carry Logic Functions (Continued)

Function Description
CYMUXG Carry generation or propagation mux for top half of slice. Dynamic selection via CYSELF of:
• CYMUXF carry propagation (CYSELG = 1)
• CY0G carry generation (CYSELG = 0)
CYSELF Carry generation or propagation select for bottom half of slice. Fixed selection of:
• F-LUT output (typically XOR result)
• Fixed "1" to always propagate
CYSELG Carry generation or propagation select for top half of slice. Fixed selection of:
• G-LUT output (typically XOR result)
• Fixed "1" to always propagate
XORF Sum generation for bottom half of slice. Inputs from:
• F-LUT
• CYINIT carry signal from previous stage
Result is sent to either the combinatorial or registered output for the top of the slice.
XORG Sum generation for top half of slice. Inputs from:
• G-LUT
• CYMUXF carry signal from previous stage
Result is sent to either the combinatorial or registered output for the top of the slice.
FAND Multiplier partial product for bottom half of slice. Inputs:
• F-LUT F1 input
• F-LUT F2 input
Result is sent through CY0F to become the carry generate signal into CYMUXF
GAND Multiplier partial product for top half of slice. Inputs:
• G-LUT G1 input
• G-LUT G2 input
Result is sent through CY0G to become the carry generate signal into CYMUXG
The basic usage of the carry logic is to generate a half-sum The FAND (or GAND) gate is used for partial product multi-
in the LUT via an XOR function, which generates or propa- plication and can be instantiated using the MULT_AND
gates a carry out COUT via the carry mux CYMUXF (or component. Partial products are generated by two-input
CYMUXG), and then complete the sum with the dedicated AND gates and then added. The carry logic is efficient for
XORF (or XORG) gate and the carry input CIN. This struc- the adder, but one of the inputs must be outside the LUT as
ture allows two bits of an arithmetic function in each slice. shown in Figure 20. The FAND (or GAND) gate is used to
The CYMUXF (or CYMUXG) can be instantiated using the duplicate one of the partial products, while the LUT gener-
MUXCY element, and the XORF (or XORG) can be instan- ates both partial products and the XOR function, as shown
tiated using the XORCY element. in Figure 21.
LUT COUT LUT

B COUT
Am
Bn+1
MUXCY
A
Am+1
Sum Bn
XORCY Pm+1
CIN
DS312-2_37_021305 MULT_AND CIN DS312-2_39_021305
Figure 20: Using the MUXCY and XORCY in the Carry
Logic Figure 21: Using the MULT_AND for Multiplication in
Carry Logic

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The MULT_AND is useful for small multipliers. Larger multi- tom portions of the slice are called FFY and FFX, respec-
pliers can be built using the dedicated 18x18 multiplier tively. FFY has a fixed multiplexer on the D input selecting
blocks (see Dedicated Multipliers). either the combinatorial output Y or the bypass signal BY.
FFX selects between the combinatorial output X or the
Storage Elements bypass signal BX.
The storage element, which is programmable as either a The functionality of a slice storage element is identical to
D-type flip-flop or a level-sensitive transparent latch, pro- that described earlier for the I/O storage elements. All sig-
vides a means for synchronizing data to a clock signal, nals have programmable polarity; the default active-High
among other uses. The storage elements in the top and bot- function is described.
Table 12: Storage Element Signals

Signal Description
D Input. For a flip-flop data on the D input is loaded when R and S (or CLR and PRE) are Low and CE is High
during the Low-to-High clock transition. For a latch, Q reflects the D input while the gate (G) input and gate
enable (GE) are High and R and S (or CLR and PRE) are Low. The data on the D input during the High-to-Low
gate transition is stored in the latch. The data on the Q output of the latch remains unchanged as long as G or
GE remains Low.
Q Output. Toggles after the Low-to-High clock transition for a flip-flop and immediately for a latch.
C Clock for edge-triggered flip-flops.
G Gate for level-sensitive latches.
CE Clock Enable for flip-flops.
GE Gate Enable for latches.
S Synchronous Set (Q = High). When the S input is High and R is Low, the flip-flop is set, output High, during the
Low-to-High clock (C) transition. A latch output is immediately set, output High.
R Synchronous Reset (Q = Low); has precedence over Set.
PRE Asynchronous Preset (Q = High). When the PRE input is High and CLR is Low, the flip-flop is set, output High,
during the Low-to-High clock (C) transition. A latch output is immediately set, output High.
CLR Asynchronous Clear (Q = Low); has precedence over Preset to reset Q output Low
SR CLB input for R, S, CLR, or PRE
REV CLB input for opposite of SR. Must be asynchronous or synchronous to match SR.
The control inputs R, S, CE, and C are all shared between Table 13: FD Flip-Flop Functionality with Synchronous
the two flip-flops in a slice. Reset, Set, and Clock Enable
Inputs Outputs
S
R S CE D C Q
FDRSE
D Q 1 X X X ↑ 0
CE
C 0 1 X X ↑ 1
R 0 0 0 X X No Change
DS312-2_40_021305
Figure 22: FD Flip-Flop Component with Synchronous 0 0 1 1 ↑ 1

Reset, Set, and Clock Enable 0 0 1 0 ↑ 0

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Initialization ing a 16x1 configuration in one LUT. Multiple SLICEM LUTs

can be combined in various ways to store larger amounts of
The CLB storage elements are initialized at power-up, dur-
data, including 16x4, 32x2, or 64x1 configurations in one
ing configuration, by the global GSR signal, and by the indi-
CLB. The fifth and sixth address lines required for the
vidual SR or REV inputs to the CLB.
32-deep and 64-deep configurations, respectively, are
Table 14: Slice Storage Element Initialization implemented using the BX and BY inputs, which connect to
the write enable logic for writing and the F5MUX and
Signal Description F6MUX for reading.
SR Set/Reset input. Forces the storage element Writing to distributed RAM is always synchronous to the
into the state specified by the attribute SRHIGH SLICEM clock (WCLK for distributed RAM) and enabled by
or SRLOW. SRHIGH forces a logic “1” when SR the SLICEM SR input which functions as the active-High
is asserted. SRLOW forces a logic “0”. For each Write Enable (WE). The read operation is asynchronous,
slice, set and reset can be set to be and, therefore, during a write, the output initially reflects the
synchronous or asynchronous. old data at the address being written.
REV Reverse of Set/Reset input. A second input The distributed RAM outputs can be captured using the
(BY) forces the storage element into the flip-flops within the SLICEM element. The WE write-enable
opposite state. The reset condition is control for the RAM and the CE clock-enable control for the
predominant over the set condition if both are flip-flop are independent, but the WCLK and CLK clock
active. Same synchronous/asynchronous inputs are shared. Because the RAM read operation is
setting as for SR. asynchronous, the output data always reflects the currently
GSR Global Set/Reset. GSR defaults to active High addressed RAM location.
but can be inverted by adding an inverter in A dual-port option combines two LUTs so that memory
front of the GSR input of the access is possible from two independent data lines. The
STARTUP_SPARTAN3E element. The initial same data is written to both 16x1 memories but they have
state after configuration or GSR is defined by a independent read address lines and outputs. The dual-port
separate INIT0 and INIT1 attribute. By default, function is implemented by cascading the G-LUT address
setting the SRLOW attribute sets INIT0, and lines, which are used for both read and write, to the F-LUT
setting the SRHIGH attribute sets INIT1. write address lines (WF[4:1] in Figure 12), and by cascad-
ing the G-LUT data input D1 through the DIF_MUX in
Distributed RAM Figure 12 and to the D1 input on the F-LUT. One CLB pro-
vides a 16x1 dual-port memory as shown in Figure 23.
The LUTs in the SLICEM can be programmed as distributed
RAM. This type of memory affords moderate amounts of Any write operation on the D input and any read operation
data buffering anywhere along a data path. One SLICEM on the SPO output can occur simultaneously with and inde-
LUT stores 16 bits (RAM16). The four LUT inputs F[4:1] or pendently from a read operation on the second read-only
G[4:1] become the address lines labeled A[4:1] in the port, DPO.
device model and A[3:0] in the design components, provid-
SLICEM
D 16x1 SPO
LUT
A[3:0] RAM
(Read/
Write) Optional
WE Register
WCLK
DPO
16x1
LUT
RAM
DPRA[3:0] (Read Optional
Only) Register
DS312-2_41_021305
Figure 23: RAM16X1D Dual-Port Usage

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Table 16: Distributed RAM Signals (Continued)

RAM16X1D
WE SPO Signal Description
D
WCLK DPO A0, A1, A2, A3 The address inputs select the memory
A0 (A4, A5) cells for read or write. The width of the
A1 port determines the required address
A2
A3 inputs.
DPRA0
DPRA1 D The data input provides the new data
DPRA2 value to be written into the RAM.
DPRA3
O, SPO, and The data output O on single-port RAM
DS312-2_42_021305
DPO or the SPO and DPO outputs on
Figure 24: Dual-Port RAM Component dual-port RAM reflects the contents of
the memory cells referenced by the
address inputs. Following an active
Table 15: Dual-Port RAM Function write clock edge, the data out (O or
SPO) reflects the newly written data.
Inputs Outputs
WE (mode) WCLK D SPO DPO The INIT attribute can be used to preload the memory with
data during FPGA configuration. The default initial contents
0 (read) X X data_a data_d
for RAM is all zeros. If the WE is held Low, the element can
1 (read) 0 X data_a data_d be considered a ROM. The ROM function is possible even
in the SLICEL.
1 (read) 1 X data_a data_d
The global write enable signal, GWE, is asserted automati-
1 (write) ↑ D D data_d cally at the end of device configuration to enable all writable
elements. The GWE signal guarantees that the initialized
1 (read) ↓ X data_a data_d
distributed RAM contents are not disturbed during the con-
Notes: figuration process.
1. data_a = word addressed by bits A3-A0. The distributed RAM is useful for smaller amounts of mem-
2. data_d = word addressed by bits DPRA3-DPRA0. ory. Larger memory requirements can use the dedicated
18Kbit RAM blocks (see Block RAM).
For more information on distributed RAM, see XAPP464:
Table 16: Distributed RAM Signals
"Using Look-Up Tables as Distributed RAM in Spartan-3
Signal Description FPGAs".
WCLK The clock is used for synchronous
Shift Registers
writes. The data and the address input
pins have setup times referenced to the It is possible to program each SLICEM LUT as a 16-bit shift
WCLK pin. Active on the positive edge register (see Figure 25). Used in this way, each LUT can
by default with built-in programmable delay serial data anywhere from 1 to 16 clock cycles without
polarity. using any of the dedicated flip-flops. The resulting program-
mable delays can be used to balance the timing of data
WE The enable pin affects the write pipelines.
functionality of the port. An inactive
The SLICEM LUTs cascade from the G-LUT to the F-LUT
Write Enable prevents any writing to
through the DIFMUX (see Figure 12). SHIFTIN and
memory cells. An active Write Enable
SHIFTOUT lines cascade a SLICEM to the SLICEM below
causes the clock edge to write the data
to form larger shift registers. The four SLICEM LUTs of a
input signal to the memory location
single CLB can be combined to produce delays up to 64
pointed to by the address inputs. Active
clock cycles. It is also possible to combine shift registers
High by default with built-in
across more than one CLB.
programmable polarity.

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SHIFTIN SRLC16 SRLC16E

D Q
CE Q15
SHIFT-REG CLK
4 A0
A[3:0] A[3:0] D Output
A1
MC15 Registered A2
D Q A3
WS DI Output
DS312-2_43_021305
DI (BY)
WSG (optional) Figure 26: SRL16 Shift Register Component with
CE (SR)
Cascade and Clock Enable
WE
CLK CK
The functionality of the shift register is shown in Table 17.
The SRL16 shifts on the rising edge of the clock input when
SHIFTOUT the Clock Enable control is High. This shift register cannot
or YB X465_03_040203 be initialized either during configuration or during operation
except by shifting data into it. The clock enable and clock
Figure 25: Logic Cell SRL16 Structure inputs are shared between the two LUTs in a SLICEM. The
clock enable input is automatically kept active if unused.
Each shift register provides a shift output MC15 for the last
bit in each LUT, in addition to providing addressable access Table 17: SRL16 Shift Register Function
to any bit in the shift register through the normal D output.
Inputs Outputs
The address inputs A[3:0] are the same as the distributed
RAM address lines, which come from the LUT inputs F[4:1] Am CLK CE D Q Q15
or G[4:1]. At the end of the shift register, the CLB flip-flop
can be used to provide one more shift delay for the addres- Am X 0 X Q[Am] Q[15]
sable bit. Am ↑ 1 D Q[Am-1] Q[15]
The shift register element is known as the SRL16 (Shift
Register LUT 16-bit), with a ‘C’ added to signify a cascade Notes:
ability (Q15 output) and ‘E’ to indicate a Clock Enable. See 1. m = 0, 1, 2, 3.
Figure 26 for an example of the SRLC16E component.
For more information on the SRL16, refer to XAPP465:
"Using Look-Up Tables as Shift Registers (SRL16) in
Spartan-3 FPGAs".

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Block RAM block RAM’s shared connectivity with the multipliers are
located in XAPP463.
Spartan-3E devices incorporate 4 to 36 dedicated block
RAMs, which are organized as dual-port configurable The Internal Structure of the Block RAM
18 Kbit blocks. Functionally, the block RAM is identical to
the Spartan-3 architecture block RAM. Block RAM synchro- The block RAM has a dual port structure. The two identical
nously stores large amounts of data while distributed RAM, data ports called A and B permit independent access to the
previously described, is better suited for buffering small common block RAM, which has a maximum capacity of
amounts of data anywhere along signal paths. This section 18,432 bits, or 16,384 bits with no parity bits (see parity bits
describes basic block RAM functions. For detailed imple- description in Table 19). Each port has its own dedicated
mentation information, refer to XAPP463: "Using Block set of data, control, and clock lines for synchronous read
RAM in Spartan-3 Series FPGAs". and write operations. There are four basic data paths, as
shown in Figure 27:
Each block RAM is configurable by setting the content’s ini-
tial values, default signal value of the output registers, port 1. Write to and read from Port A
aspect ratios, and write modes. Block RAM can be used in 2. Write to and read from Port B
single-port or dual-port modes.
3. Data transfer from Port A to Port B
Arrangement of RAM Blocks on Die 4. Data transfer from Port B to Port A
The block RAMs are located together with the multipliers on
the die in one or two columns depending on the size of the
device. The XC3S100E has one column of block RAM. The Write Read 3
Spartan-3E devices ranging from the XC3S250E to 4 Read Write
XC3S1600E have two columns of block RAM. Table 18
Port B
Port A
shows the number of RAM blocks, the data storage capac- Spartan-3E
ity, and the number of columns for each device. Row(s) of Dual-Port
CLBs are located above and below each block RAM col- Block RAM
umn. Write Write
1 2
Read Read
Table 18: Number of RAM Blocks by Device
DS312-2_01_020705
Total Total
Number of Addressable Number Figure 27: Block RAM Data Paths
RAM Locations of
Device Blocks (bits) Columns Number of Ports
A choice among primitives determines whether the block
XC3S100E 4 73,728 1 RAM functions as dual- or single-port memory. A name of
XC3S250E 12 221,184 2 the form RAMB16_S[wA]_S[wB] calls out the dual-port prim-
itive, where the integers wA and wB specify the total data
XC3S500E 20 368,640 2 path width at ports A and B, respectively. Thus, a
XC3S1200E 28 516,096 2 RAMB16_S9_S18 is a dual-port RAM with a 9-bit Port A
and an 18-bit Port B. A name of the form RAMB16_S[w]
XC3S1600E 36 663,552 2 identifies the single-port primitive, where the integer w
specifies the total data path width of the lone port A. A
Immediately adjacent to each block RAM is an embedded RAMB16_S18 is a single-port RAM with an 18-bit port.
18x18 hardware multiplier. The upper 16 bits of the block
RAM's Port A Data input bus are shared with the upper 16 Port Aspect Ratios
bits of the A multiplicand input bus of the multiplier. Similarly,
Each port of the block RAM can be configured indepen-
the upper 16 bits of Port B's data input bus are shared with
dently to select a number of different possible widths for the
the B multiplicand input bus of the multiplier. Details on the
data input (DI) and data output (DO) signals as shown in
Table 19.

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Table 19: Port Aspect Ratios

DIP/DOP ADDR
Total Data DI/DO Data Parity Bus Bus No. of Block RAM
Path Width Bus Width Width Width DI/DO DIP/DOP ADDR Addressable Capacity
(w bits) (w-p bits)1 (p bits) (r bits)2 [w-p-1:0] [p-1:0] [r-1:0] Locations (n)3 (w*n bits)4
1 1 0 14 [0:0] - [13:0] 16,384 16,384
2 2 0 13 [1:0] - [12:0] 8,192 16,384
4 4 0 12 [3:0] - [11:0] 4,096 16,384
9 8 1 11 [7:0] [0:0] [10:0] 2,048 18,432
18 16 2 10 [15:0] [1:0] [9:0] 1,024 18,432
36 32 4 9 [31:0] [3:0] [8:0] 512 18,432
Notes:
1. The width of the total data path (w) is the sum of the DI/DO bus width (w-p) and any parity bits (p).
2. The width selection made for the DI/DO bus determines the number of address lines (r) according to the relationship expressed as:
r = 14 – [log(w–p)/log(2)].
3. The number of address lines delimits the total number (n) of addressable locations or depth according to the following equation: n = 2r.
4. The product of w and n yields the total block RAM capacity.
If the data bus width of Port A differs from that of Port B, the ity bits are not available if the data port width is configured
block RAM automatically performs a bus-matching function as x4, x2, or x1. For example, if a x36 data word (32 data, 4
as described in Figure 28. When data is written to a port parity) is addressed as two x18 halfwords (16 data, 2 par-
with a narrow bus and then read from a port with a wide bus, ity), the parity bits associated with each data byte are
the latter port effectively combines “narrow” words to form mapped within the block RAM to the appropriate parity bits.
“wide” words. Similarly, when data is written into a port with The same effect happens when the x36 data word is
a wide bus and then read from a port with a narrow bus, the mapped as four x9 words.
latter port divides “wide” words to form “narrow” words. Par-

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Parity Data Address
35 34 33 32 31 24 23 16 15 8 7 0
512x36 P3 P2 P1 P0 Byte 3 Byte 2 Byte 1 Byte 0 0

17 16 15 8 7 0
P3 P2 Byte 3 Byte 2 1
1Kx18
P1 P0 Byte 1 Byte 0 0
Pa
r
(16 ity O
2K bits ption
K 8 7 0
bits d a
pa ata, l P3 Byte 3 3
r ity
) P2 Byte 2 2
2Kx9
P1 Byte 1 1
P0 Byte 0 0
3 2 1 0
7 6 5 34 7
y te1 0
3B 2 6
4Kx4
7 6 5 04 1
te
3B2y 1 0 0
1 0
7 6 F
Byte 3
5 4 E
3 2 D
1 0 C
(16Kbits data) 8Kx2
No Parity
7 6 3
Byte 0
5 4 2
3 2 1
1 0 0
0
7 1F
Byte 3
6 1E
5 1D
4 1C
16Kx1
3 3
Byte 0
2 2
1 1
0 0
DS312-2_02_020705
Figure 28: Data Organization and Bus-matching Operation with Different Port Widths on Port A and Port B
Block RAM Port Signal Definitions defined in Table 20. The control signals (WE, EN, CLK, and
SSR) on the block RAM are active High. However, optional
Representations of the dual-port primitive
inverters on the control signals change the polarity of the
RAMB16_S[wA]_S[wB] and the single-port primitive
active edge to active Low.
RAMB16_S[w] with their associated signals are shown in
Figure 29a and Figure 29b, respectively. These signals are

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WEA RAMB16_wA_wB
ENA
SSRA
DOPA[pA–1:0]
CLKA
ADDRA[rA–1:0] DOA[wA–pA–1:0]
DIA[wA–pA–1:0]
DIPA[pA–1:0]
WEB WE RAMB16_Sw
ENB EN
SSRB DOPB[pB–1:0] SSR
DOP[p–1:0]
CLKB CLK
DOB[wB–pB–1:0] DO[w–p–1:0]
ADDRB[rB–1:0] ADDR[r–1:0]
DIB[wB–pB–1:0] DI[w–p–1:0]
DIPB[pB–1:0] DIP[p–1:0]
(a) Dual-Port (b) Single-Port

DS312-2_03_021305
Notes:
1. wA and wB are integers representing the total data path width (i.e., data bits plus parity bits) at Ports A and B, respectively.
2. pA and pB are integers that indicate the number of data path lines serving as parity bits.
3. rA and rB are integers representing the address bus width at ports A and B, respectively.
4. The control signals CLK, WE, EN, and SSR on both ports have the option of inverted polarity.
Figure 29: Block RAM Primitives
Table 20: Block RAM Port Signals

Port A Port B
Signal Signal Signal
Description Name Name Direction Function
Address Bus ADDRA ADDRB Input The Address Bus selects a memory location for read or write
operations. The width (w) of the port’s associated data path
determines the number of available address lines (r), as per
Table 18.
Data Input Bus DIA DIB Input Data at the DI input bus is written to the RAM location specified
by the address input bus (ADDR) during the active edge of the
CLK input, when the clock enable (EN) and write enable (WE)
inputs are active.
It is possible to configure a port’s DI input bus width (w-p) based
on Table 18. This selection applies to both the DI and DO paths
of a given port.
Parity Data DIPA DIPB Input Parity inputs represent additional bits included in the data input
Input(s) path. Although referred to herein as “parity” bits, the parity inputs
and outputs have no special functionality for generating or
checking parity and can be used as additional data bits. The
number of parity bits ‘p’ included in the DI (same as for the DO
bus) depends on a port’s total data path width (w). See Table 18.

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Table 20: Block RAM Port Signals (Continued)

Port A Port B
Signal Signal Signal
Description Name Name Direction Function
Data Output Bus DOA DOB Output Data is written to the DO output bus from the RAM location
specified by the address input bus, ADDR. See the DI signal
description for DO port width configurations.
Basic data access occurs on the active edge of the CLK when
WE is inactive and EN is active. The DO outputs mirror the data
stored in the address ADDR memory location. Data access with
WE active if the WRITE_MODE attribute is set to the value:
WRITE_FIRST, which accesses data after the write takes place.
READ_FIRST accesses data before the write occurs. A third
attribute, NO_CHANGE, latches the DO outputs upon the
assertion of WE. See Block RAM Data Operations for details on
the WRITE_MODE attribute.
Parity Data DOPA DOPB Output Parity outputs represent additional bits included in the data input
Output(s) path. The number of parity bits ‘p’ included in the DI bus (same
as for the DO bus) depends on a port’s total data path width (w).
See the DIP signal description for configuration details.
Write Enable WEA WEB Input When asserted together with EN, this input enables the writing of
data to the RAM. When WE is inactive with EN asserted, read
operations are still possible. In this case, a latch passes data
from the addressed memory location to the DO outputs.
Clock Enable ENA ENB Input When asserted, this input enables the CLK signal to perform
read and write operations to the block RAM. When inactive, the
block RAM does not perform any read or write operations.
Set/Reset SSRA SSRB Input When asserted, this pin forces the DO output latch to the value
of the SRVAL attribute. It is synchronized to the CLK signal.
Clock CLKA CLKB Input This input accepts the clock signal to which read and write
operations are synchronized. All associated port inputs are
required to meet setup times with respect to the clock signal’s
active edge. The data output bus responds after a clock-to-out
delay referenced to the clock signal’s active edge.
Block RAM Attribute Definitions

A block RAM has a number of attributes that control its
behavior as shown in Table 21.
Table 21: Block RAM Attributes

Function Attribute Possible Values
Initial Content for Data Memory, Loaded INITxx (INIT_00 through Each initialization string defines 32 hex values
during Configuration INIT3F) of the 16384-bit data memory of the block RAM.
Initial Content for Parity Memory, Loaded INITPxx (INITP_00 Each initialization string defines 32 hex values
during Configuration through INITP0F) of the 2048-bit parity data memory of the block
RAM.
Data Output Latch Initialization INIT (single-port) Hex value the width of the chosen port.
INITA, INITB (dual-port)

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Table 21: Block RAM Attributes (Continued)

Function Attribute Possible Values
Data Output Latch Synchronous SRVAL (single-port) Hex value the width of the chosen port.
Set/Reset Value SRVAL_A, SRVAL_B
(dual-port)
Data Output Latch Behavior during Write WRITE_MODE WRITE_FIRST, READ_FIRST, NO_CHANGE
(see Block RAM Data Operations)
Block RAM Data Operations The waveforms for the write operation are shown in the top
half of Figure 30, Figure 31, and Figure 32. When the WE
Writing data to and accessing data from the block RAM are
and EN signals enable the active edge of CLK, data at the
synchronous operations that take place independently on
DI input bus is written to the block RAM location addressed
each of the two ports. Table 22 describes the data opera-
by the ADDR lines.
tions of each port as a result of the block RAM control sig-
nals in their default active-High edges.
Table 22: Block RAM Function Table

Input Signals Output Signals RAM Data
GSR EN SSR WE CLK ADDR DIP DI DOP DO Parity Data
Immediately After Configuration
Loaded During Configuration X X INITP_xx INIT_xx
Global Set/Reset Immediately After Configuration
1 X X X X X X X INIT INIT No Chg No Chg
RAM Disabled
0 0 X X X X X X No Chg No Chg No Chg No Chg
Synchronous Set/Reset
0 1 1 0 ↑ X X X SRVAL SRVAL No Chg No Chg
Synchronous Set/Reset During Write RAM
0 1 1 1 ↑ addr pdata Data SRVAL SRVAL RAM(addr) RAM(addr)
← pdata ← data
Read RAM, no Write Operation
0 1 0 0 ↑ addr X X RAM(pdata) RAM(data) No Chg No Chg
Write RAM, Simultaneous Read Operation
0 1 0 1 ↑ addr pdata Data WRITE_MODE = WRITE_FIRST
pdata data RAM(addr) RAM(addr)
← pdata ← data
WRITE_MODE = READ_FIRST
RAM(data) RAM(data) RAM(addr) RAM(addr)
← pdata ← pdata
WRITE_MODE = NO_CHANGE
No Chg No Chg RAM(addr) RAM(addr)
← pdata ← pdata

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There are a number of different conditions under which data portions of Figure 30, Figure 31, and Figure 32 during
can be accessed at the DO outputs. Basic data access which WE is Low.
always occurs when the WE input is inactive. Under this Data also can be accessed on the DO outputs when assert-
condition, data stored in the memory location addressed by ing the WE input based on the value of the WRITE_MODE
the ADDR lines passes through a output latch to the DO attribute as described in Table 23.
outputs. The timing for basic data access is shown in the
Table 23: WRITE_MODE Effect on Data Output Latches During Write Operations
Effect on Opposite Port
Write Mode Effect on Same Port
(dual-port only with same address)
WRITE_FIRST Data on DI and DIP inputs is written into Invalidates data on DO and DOP outputs.
Read After Write specified RAM location and simultaneously
appears on DO and DOP outputs.
READ_FIRST Data from specified RAM location appears on Data from specified RAM location appears on
Read Before Write DO and DOP outputs. DO and DOP outputs.
Data on DI and DIP inputs is written into
specified location.
NO_CHANGE Data on DO and DOP outputs remains Invalidates data on DO and DOP outputs.
No Read on Write unchanged.
Data on DI and DIP inputs is written into
specified location.
Internal
Data_in DI DO Data_out = Data_in
Memory
CLK
WE
DI XXXX 1111 2222 XXXX
ADDR aa bb cc dd
DO 0000 MEM(aa) 1111 2222 MEM(dd)
EN
DISABLED READ WRITE WRITE READ

MEM(bb)=1111 MEM(cc)=2222
DS312-2_05_020905
Figure 30: Waveforms of Block RAM Data Operations with WRITE_FIRST Selected
Setting the WRITE_MODE attribute to a value of Setting the WRITE_MODE attribute to a value of
WRITE_FIRST, data is written to the addressed memory READ_FIRST, data already stored in the addressed loca-
location on an enabled active CLK edge and is also passed tion passes to the DO outputs before that location is over-
to the DO outputs. WRITE_FIRST timing is shown in the written with new data from the DI inputs on an enabled
portion of Figure 30 during which WE is High. active CLK edge. READ_FIRST timing is shown in the por-
tion of Figure 31 during which WE is High.

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Internal
Data_in DI DO Prior stored data
Memory
CLK
WE
ADDR aa bb cc dd
DO 0000 MEM(aa) old MEM(bb) old MEM(cc) MEM(dd)
EN

DS312-2_06_020905
Figure 31: Waveforms of Block RAM Data Operations with READ_FIRST Selected
Internal
Data_in DI DO No change during write
Memory
CLK
WE
ADDR aa bb cc dd
DO 0000 MEM(aa) MEM(dd)
EN

DS312-2_07_020905
Figure 32: Waveforms of Block RAM Data Operations with NO_CHANGE Selected
Setting the WRITE_MODE attribute to a value of the data driven just before WE is asserted. NO_CHANGE
NO_CHANGE, puts the DO outputs in a latched state when timing is shown in the portion of Figure 32 during which WE
asserting WE. Under this condition, the DO outputs retain is High.

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Dedicated Multipliers Implement multipliers with inputs less than 18 bits by

sign-extending the inputs (i.e., replicating the most-signifi-
The Spartan-3E devices provide 4 to 36 dedicated multiplier
cant bit). Wider multiplication operations are performed by
blocks per device. The multipliers are located together with
combining the dedicated multipliers and slice-based logic in
the block RAM in one or two columns depending on device
any viable combination or by time-sharing a single multi-
density. See Arrangement of RAM Blocks on Die for
plier. Perform unsigned multiplication by restricting the
details on the location of these blocks and their connectivity.
inputs to the positive range. Tie the most-significant bit Low
The multiplier blocks primarily perform two’s complement and represent the unsigned value in the remaining 17
numerical multiplication but can also perform some less lesser-significant bits.
obvious applications such as simple data storage and barrel As shown in Figure 33, each multiplier block has optional
shifting. Logic slices also implement efficient small multipli- registers on each of the multiplier inputs and the output. The
ers and thereby supplement the dedicated multipliers. The registers are named AREG, BREG, and PREG and can be
Spartan-3E dedicated multiplier blocks have additional fea- used in any combination. The clock input is common to all
tures beyond those provided in Spartan-3 FPGAs. the registers within a block, but each register has an inde-
Each multiplier performs the principle operation P = A × B, pendent clock enable and synchronous reset controls mak-
where ‘A’ and ‘B’ are 18-bit words in two’s complement ing them ideal for storing data samples and coefficients.
form, and ‘P’ is the full-precision 36-bit product, also in two’s When used for pipelining, the registers boost the multiplier
complement form. The 18-bit inputs represent values rang- clock rate, beneficial for higher performance applications.
ing from -131,07210 to +131,07110 with a resulting product
Figure 33 illustrates the principle features of the multiplier
ranging from -17,179,738,11210 to +17,179,869,18410.
block.
AREG
(Optional)
CEA CE
A[17:0] D Q
PREG
(Optional)
RST
CEP CE
RSTA X D Q P[35:0]
BREG
(Optional)
RST
CEB CE
B[17:0] D Q RSTP
RST
RSTB
DS312-2_27_021205
CLK
Figure 33: Principle Ports and Functions of Dedicated Multiplier Blocks
Use the MULT18X18SIO primitive shown in Figure 34 to to the MULT18X18SIO multiplier ports and set the individual
instantiate a multiplier within a design. Although high-level AREG, BREG, and PREG attributes to ‘1’ to insert the asso-
logic synthesis software usually automatically infers a multi- ciated register, or to 0 to remove it and make the signal path
plier, adding the pipeline registers usually requires the combinatorial.
MULT18X18SIO primitive. Connect the appropriate signals

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The MULT18X18SIO primitive has two additional ports

MULT18X18SIO called BCIN and BCOUT to cascade or share the multi-
A[17:0] P[35:0] plier’s ‘B’ input among several multiplier bocks. The 18-bit
B[17:0] BCIN "cascade" input port offers an alternate input source
CEA from the more typical ‘B’ input. The B_INPUT attribute spec-
ifies whether the specific implementation uses the BCIN or
CEB
‘B’ input path. Setting B_INPUT to DIRECT chooses the ‘B’
CEP
input. Setting B_INPUT to CASCADE selects the alternate
CLK BCIN input. The BREG register then optionally holds the
RSTA selected input value, if required.
RSTB
BCOUT is an 18-bit output port that always reflects the
RSTP value that is applied to the multiplier’s second input, which is
BCIN[17:0] BCOUT[17:0] either the ‘B’ input, the cascaded value from the BCIN input,
DS312-2_28_021205
or the output of the BREG if it is inserted.
Figure 34: MULT18X18SIO Primitive Figure 35 illustrates the four possible configurations using
different settings for the B_INPUT attribute and the BREG
attribute.
BCOUT[17:0] BCOUT[17:0]
BREG
CEB CE
X X
D Q
CLK BREG = 0
RST B_INPUT = CASCADE
BREG = 1
RSTB B_INPUT = CASCADE
BCIN[17:0] BCIN[17:0]
BCOUT[17:0]
BCOUT[17:0]
BREG
X
CEB CE
X
B[17:0]
B[17:0] D Q
BREG = 0
CLK B_INPUT = DIRECT
RST
BREG = 1
RSTB B_INPUT = DIRECT DS312-2_29_021505
Figure 35: Four Configurations of the B Input

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The BCIN and BCOUT ports have associated dedicated

routing that connects adjacent multipliers within the same
column. Via the cascade connection, the BCOUT port of BCOUT
one multiplier block drives the BCIN port of the multiplier A
block directly above it. There is no connection to the BCIN P
port of the bottom-most multiplier block in a column or a B
connection from the BCOUT port of the top-most block in a
B_INPUT = CASCADE BCIN
column. As an example, Figure 36 shows the multiplier cas-
cade capability within the XC3S100E FPGA, which has a
single column of multiplier, four blocks tall. For clarity, the BCOUT
figure omits the register control inputs. A
P
B
BCOUT
A
P
B
BCOUT
A
P
B
B_INPUT = DIRECT BCIN
DS312-2_30_021505
Figure 36: Multiplier Cascade Connection

When using the BREG register, the cascade connection
forms a shift register structure typically used in DSP algo-
rithms such as direct-form FIR filters. When the BREG reg-
ister is omitted, the cascade structure essentially feeds the
same input value to more than one multiplier. This parallel
connection serves to create wide-input multipliers, imple-
ment transpose FIR filters, and is used in any application
that requires that several multipliers have the same input
value.

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Table 24 defines each port of the MULT18X18SIO primitive.
Table 24: MULT18X18SIO Embedded Multiplier Primitives Description

Signal Name Direction Function
A[17:0] Input The primary 18-bit two’s complement value for multiplication. The block multiplies by
this value asynchronously if the optional AREG and PREG registers are omitted.
When AREG and/or PREG are used, the value provided on this port is qualified by
the rising edge of CLK, subject to the appropriate register controls.
B[17:0] Input The second 18-bit two’s complement value for multiplication if the B_INPUT attribute
is set to DIRECT. The block multiplies by this value asynchronously if the optional
BREG and PREG registers are omitted. When BREG and/or PREG are used, the
value provided on this port is qualified by the rising edge of CLK, subject to the
appropriate register controls.
BCIN[17:0] Input The second 18-bit two’s complement value for multiplication if the B_INPUT attribute
is set to CASCADE. The block multiplies by this value asynchronously if the optional
BREG and PREG registers are omitted. When BREG and/or PREG are used, the
value provided on this port is qualified by the rising edge of CLK, subject to the
appropriate register controls.
P[35:0] Output The 36-bit two’s complement product resulting from the multiplication of the two input
values applied to the multiplier. If the optional AREG, BREG and PREG registers are
omitted, the output operates asynchronously. Use of PREG causes this output to
respond to the rising edge of CLK with the value qualified by CEP and RSTP. If PREG
is omitted, but AREG and BREG are used, this output responds to the rising edge of
CLK with the value qualified by CEA, RSTA, CEB, and RSTB. If PREG is omitted and
only one of AREG or BREG is used, this output responds to both asynchronous and
synchronous events.
BCOUT[17:0] Output The value being applied to the second input of the multiplier. When the optional
BREG register is omitted, this output responds asynchronously in response to
changes at the B[17:0] or BCIN[17:0] ports according to the setting of the B_INPUT
attribute. If BREG is used, this output responds to the rising edge of CLK with the
value qualified by CEB and RSTB.
CEA Input Clock enable qualifier for the optional AREG register. The value provided on the
A[17:0] port is captured by AREG in response to a rising edge of CLK when this
signal is High, provided that RSTA is Low.
RSTA Input Synchronous reset for the optional AREG register. AREG content is forced to the
value zero in response to a rising edge of CLK when this signal is High.
CEB Input Clock enable qualifier for the optional BREG register. The value provided on the
B[17:0] or BCIN[17:0] port is captured by BREG in response to a rising edge of CLK
when this signal is High, provided that RSTB is Low.
RSTB Input Synchronous reset for the optional BREG register. BREG content is forced to the
CEP Input Clock enable qualifier for the optional PREG register. The value provided on the
output of the multiplier port is captured by PREG in response to a rising edge of CLK
when this signal is High, provided that RSTP is Low.
RSTP Input Synchronous reset for the optional PREG register. PREG content is forced to the
Notes:
1. The control signals CLK, CEA, RSTA, CEB, RSTB, CEP, and RSTP have the option of inverted polarity.

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Digital Clock Managers (DCMs) The DCM supports three major functions:
• Clock-skew Elimination: Clock skew describes the
Differences from the Spartan-3 Architecture extent to which clock signals may, under normal
• Spartan-3E FPGAs have two, four, or eight DCMs, circumstances, deviate from zero-phase alignment. It
depending on device size. occurs when slight differences in path delays cause the
• The Spartan-3E DCM has a maximum phase shift clock signal to arrive at different points on the die at
range of ±180°. The Spartan-3 DCM range is ±360°. different times. This clock skew can increase set-up
• The Spartan-3E DLL supports lower input frequencies, and hold time requirements as well as clock-to-out
down to 5 MHz. Spartan-3 DLLs supports down to 24 time, which may be undesirable in applications
MHz. operating at a high frequency, when timing is critical.
The DCM eliminates clock skew by aligning the output
Overview clock signal it generates with another version of the
clock signal that is fed back. As a result, the two clock
Spartan-3E Digital Clock Managers (DCMs) provide flexi- signals establish a zero-phase relationship. This
ble, complete control over clock frequency, phase shift and effectively cancels out clock distribution delays that
skew. To accomplish this, the DCM employs a Delay-Locked might lie in the signal path leading from the clock
Loop (DLL), a fully digital control system that uses feedback
output of the DCM to its feedback input.
to maintain clock signal characteristics with a high degree of
precision despite normal variations in operating tempera- • Frequency Synthesis: Provided with an input signal,
ture and voltage. This section provides a fundamental the DCM can generate a wide range of different output
description of the DCM. See XAPP462: "Using Digital Clock clock frequencies. This is accomplished by either
Managers (DCMs) in Spartan-3 Series FPGAs" for further multiplying and/or dividing the frequency of the input
information. clock signal by any of several different factors.
• Phase Shifting: The DCM provides the ability to shift
The XC3S100E FPGA has two DCMs, one at the top and
the phase of all its output clock signals with respect to
one at the bottom of the device. The XC3S250E and
its input clock signal.
XC3S500E FPGAs each include four DCMs, two at the top
and two at the bottom. The XC3S1200E and XC3S1600E The DCM has four functional components: the
FPGAs contain eight DCMs with two on each edge (see Delay-Locked Loop (DLL), the Digital Frequency Synthe-
also Figure 42). The DCM in Spartan-3E FPGAs is sur- sizer (DFS), the Phase Shifter (PS), and the Status Logic.
rounded by CLBs within the logic array and is no longer Each component has its associated signals, as shown in
located at the top and bottom of a column of block RAM as Figure 37.
in the Spartan-3 architecture,. The Digital Clock Manager is
instantiated into a design as the “DCM” primitive.
DCM
PSINCDEC Phase
PSEN Shifter PSDONE
PSCLK
CLK0 Clock
CLKIN Distribution
Output Stage
CLK90
Input Stage
Delay
Delay Taps
CLK180
CLK270
CLKFB CLK2X
CLK2X180
CLKDV
CLKFX
DFS
DLL CLKFX180
Status LOCKED
RST 8
Logic STATUS [7:0]
DS099-2_07_040103
Figure 37: DCM Functional Blocks and Associated Signals

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CLK0
Output Section
CLK90
CLK180
CLK270
CLK2X
Delay Delay Delay Delay
CLKIN 1 2 n-1 n CLK2X180
CLKDV
Control LOCKED
CLKFB Phase
Detection
RST DS099-2_08_041103
Figure 38: Simplified Functional Diagram of DLL
Table 25: DLL Signals

Signal Direction Description
CLKIN Input Accepts original clock signal.
CLKFB Input Accepts either CLK0 or CLK2X as the feedback signal. (Set CLK_FEEDBACK attribute
accordingly).
CLK0 Output Generates a clock signal with same frequency and phase as CLKIN.
CLK90 Output Generates a clock signal with same frequency as CLKIN, only phase-shifted 90°.
CLK2X Output Generates a clock signal with same phase as CLKIN, only twice the frequency.
CLK2X180 Output Generates a clock signal with twice the frequency of CLKIN, phase-shifted 180° with
respect to CLKIN.
CLKDV Output Divides the CLKIN frequency by CLKDV_DIVIDE value to generate lower frequency
clock signal that is phase-aligned to CLKIN.
Delay-Locked Loop (DLL) neously. Signals that initialize and report the state of the
DLL are discussed in the Status Logic Component section.
The most basic function of the DLL component is to elimi-
nate clock skew. The main signal path of the DLL consists of The clock signal supplied to the CLKIN input serves as a
an input stage, followed by a series of discrete delay ele- reference waveform. The DLL seeks to align the rising-edge
ments or taps, which in turn leads to an output stage. This of feedback signal at the CLKFB input with the rising-edge
path together with logic for phase detection and control of CLKIN input. When eliminating clock skew, the common
forms a system complete with feedback as shown in approach to using the DLL is as follows: The CLK0 signal is
Figure 38. In Spartan-3E FPGAs, the DLL is implemented passed through the clock distribution network to all the reg-
using a counter-based delay line. isters it synchronizes. These registers are either internal or
external to the FPGA. After passing through the clock distri-
The DLL component has two clock inputs, CLKIN and
bution network, the clock signal returns to the DLL via a
CLKFB, as well as seven clock outputs, CLK0, CLK90,
feedback line called CLKFB. The control block inside the
CLK180, CLK270, CLK2X, CLK2X180, and CLKDV as
DLL measures the phase error between CLKFB and CLKIN.
described in Table 25. The clock outputs drive simulta-

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This phase error is a measure of the clock skew that the DLL Attributes and Related Functions
clock distribution network introduces. The control block acti-
A number of different functional options can be set for the
vates the appropriate number of delay elements to cancel
DLL component through the use of the attributes described
out the clock skew. Once the DLL has brought the CLK0 sig-
in Table 26. Each attribute is described in detail in the sec-
nal in phase with the CLKIN signal, it asserts the LOCKED
tions that follow:
output, indicating a lock on to the CLKIN signal.
Table 26: DLL Attributes

Attribute Description Values
CLK_FEEDBACK Chooses either the CLK0 or CLK2X output to NONE, 1X, 2X
drive the CLKFB input
CLKIN_DIVIDE_BY_2 Halves the frequency of the CLKIN signal just TRUE, FALSE
as it enters the DCM
CLKDV_DIVIDE Selects the constant used to divide the CLKIN 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6.0,
input frequency to generate the CLKDV 6.5, 7.0, 7.5, 8, 9, 10, 11, 12, 13, 14,
output frequency 15, and 16
DUTY_CYCLE_CORRECTION Enables 50% duty cycle correction for the TRUE, FALSE
CLK0, CLK90, CLK180, and CLK270 outputs
DLL Clock Input Connections The feedback loop is essential for DLL operation and is
An external clock source enters the FPGA using a Global established by driving the CLKFB input with either the CLK0
Clock Input Buffer (IBUFG), which directly accesses the glo- or the CLK2X signal so that any undesirable clock distribu-
bal clock network or via an Input Buffer (IBUF). Clock sig- tion delay is included in the loop. It is possible to use either
nals within the FPGA drive a global clock net using a Global of these two signals for synchronizing any of the seven DLL
Clock Multiplexer Buffer (BUFGMUX). The global clock net outputs: CLK0, CLK90, CLK180, CLK270, CLKDV, CLK2X,
connects directly to the CLKIN input. The internal and exter- or CLK2X180. The value assigned to the CLK_FEEDBACK
nal connections are shown in Figure 39a and Figure 39c, attribute must agree with the physical feedback connection:
respectively. A differential clock (e.g., LVDS) can serve as a value of 1X for the CLK0 case, 2X for the CLK2X case. If
an input to CLKIN. the DCM is used in an application that does not require the
DLL — that is, only the DFS is used — then there is no
DLL Clock Output and Feedback Connections required feedback loop so CLK_FEEDBACK is set to
As many as four of the nine DCM clock outputs can simulta- NONE.
neously drive four of the BUFGMUX buffers on the same die There are two basic cases that determine how to connect
edge. All DCM clock outputs can simultaneously drive gen- the DLL clock outputs and feedback connections: on-chip
eral routing resources, including interconnect leading to synchronization and off-chip synchronization, which are
OBUF buffers. illustrated in Figure 39a through Figure 39d.

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FPGA FPGA
BUFGMUX BUFGMUX
BUFG CLK90 BUFG CLK0
CLK180 CLK90
CLKIN CLK270 CLKIN CLK180
CLKDV CLK270
DCM Clock DCM Clock
CLK2X CLKDV Net Delay
Net Delay
CLK2X180 CLK2X180
CLKFB CLK0 CLKFB CLK2X
BUFGMUX BUFGMUX
CLK0 CLK2X
(a) On-Chip with CLK0 Feedback (b) On-Chip with CLK2X Feedback
FPGA FPGA
IBUFG CLK90 OBUF IBUFG CLK0 OBUF
CLK180 CLK90
CLKIN CLK270 CLKIN CLK180
CLKDV CLK270
DCM Clock Clock
CLK2X Net Delay DCM CLKDV
Net Delay
CLK2X180 CLK2X180
CLKFB CLK0 CLKFB CLK2X
IBUFG OBUF IBUFG OBUF
CLK0 CLK2X
(c) Off-Chip with CLK0 Feedback (d) Off-Chip with CLK2X Feedback
DS099-2_09_082104
Figure 39: Input Clock, Output Clock, and Feedback Connections for the DLL
In the on-chip synchronization case in Figure 39a and Coarse Phase Shift Outputs of the DLL Compo-
Figure 39b, it is possible to connect any of the DLL’s seven nent
output clock signals through general routing resources to
In addition to CLK0 for zero-phase alignment to the CLKIN
the FPGA’s internal registers. Either a Global Clock Buffer
signal, the DLL also provides the CLK90, CLK180, and
(BUFG) or a BUFGMUX affords access to the global clock
CLK270 outputs for 90°, 180°, and 270° phase-shifted sig-
network. As shown in Figure 39a, the feedback loop is cre-
nals, respectively. These signals are described in Table 25.
ated by routing CLK0 (or CLK2X, in Figure 39b to a global
Their relative timing is shown in Figure 40. For control in
clock net, which in turn drives the CLKFB input.
finer increments than 90°, see Phase Shifter (PS).
In the off-chip synchronization case in Figure 39c and
Figure 39d, CLK0 (or CLK2X) plus any of the DLL’s other Basic Frequency Synthesis Outputs of the DLL
output clock signals exit the FPGA using output buffers Component
(OBUF) to drive an external clock network plus registers on The DLL component provides basic options for frequency
the board. As shown in Figure 39c, the feedback loop is multiplication and division in addition to the more flexible
formed by feeding CLK0 (or CLK2X, in Figure 39d) back synthesis capability of the DFS component, described in a
into the FPGA using an IBUFG, which directly accesses the later section. These operations result in output clock signals
global clock network, or an IBUF. Then, the global clock net with frequencies that are either a fraction (for division) or a
is connected directly to the CLKFB input. multiple (for multiplication) of the incoming clock frequency.
Accommodating High Input Frequencies The CLK2X output produces an in-phase signal that is twice
the frequency of CLKIN. The CLK2X180 output also dou-
If the frequency of the CLKIN signal is high such that it bles the frequency, but is 180° out-of-phase with respect to
exceeds the maximum permitted, divide it down to an CLKIN. The CLKDIV output generates a clock frequency
acceptable value using the CLKIN_DIVIDE_BY_2 attribute. that is a predetermined fraction of the CLKIN frequency.
When this attribute is set to TRUE, the CLKIN frequency is The CLKDV_DIVIDE attribute determines the factor used to
divided by a factor of two just as it enters the DCM. divide the CLKIN frequency. The attribute can be set to var-

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ious values as described in Table 26. The basic frequency 2. The fCLKFX frequency calculated from the above
synthesis outputs are described in Table 25. expression accords with the DCM’s operating frequency
specifications.
Duty Cycle Correction of DLL Clock Outputs
For example, if CLKFX_MULTIPLY = 5 and CLKFX_DIVIDE
The CLK2X(1), CLK2X180, and CLKDV(2) output signals = 3, then the frequency of the output clock signal is 5/3 that
ordinarily exhibit a 50% duty cycle – even if the incoming of the input clock signal.
CLKIN signal has a different duty cycle. Fifty-percent duty
cycle means that the High and Low times of each clock
cycle are equal. The DUTY_CYCLE_CORRECTION o o o o o o o o o
Phase: 0 90 180 270 0 90 180 270 0
attribute determines whether or not duty cycle correction is
applied to the CLK0, CLK90, CLK180, and CLK270 outputs.
If DUTY_CYCLE_CORRECTION is set to TRUE, then the Input Signal (30% Duty Cycle)
duty cycle of these four outputs is corrected to 50%. If t
DUTY_CYCLE_CORRECTION is set to FALSE, then these
CLKIN
outputs exhibit the same duty cycle as the CLKIN signal.
Figure 40 compares the characteristics of the DLL’s output
signals to those of the CLKIN signal.
The CLK2X output generates a 25% duty cycle clock at the Output Signal - Duty Cycle is Always Corrected
same frequency as the CLKIN signal until the DLL has
CLK2X
achieved lock.
The duty cycle of the CLKDV outputs may differ somewhat
CLK2X180
from 50% (i.e., the signal is High for less than 50% of the
period) when the CLKDV_DIVIDE attribute is set to a
(1)
non-integer value and the DLL is operating in the High Fre- CLKDV
quency mode.
Digital Frequency Synthesizer (DFS) Output Signal - Attribute Corrects Duty Cycle
The DFS component generates clock signals the frequency DUTY_CYCLE_CORRECTION = FALSE
of which is a product of the clock frequency at the CLKIN CLK0
input and a ratio of two user-determined integers. Because
of the wide range of possible output frequencies such a ratio
permits, the DFS feature provides still further flexibility than CLK90
the DLL’s basic synthesis options as described in the pre-
ceding section. The DFS component’s two dedicated out- CLK180
puts, CLKFX and CLKFX180, are defined in Table 28.
The signal at the CLKFX180 output is essentially an inver- CLK270
sion of the CLKFX signal. These two outputs always exhibit
a 50% duty cycle. This is true even when the CLKIN signal DUTY_CYCLE_CORRECTION = TRUE
does not. These DFS clock outputs are driven at the same
time as the DLL’s seven clock outputs. CLK0
The numerator of the ratio is the integer value assigned to

the attribute CLKFX_MULTIPLY and the denominator is the CLK90
integer value assigned to the attribute CLKFX_DIVIDE.
These attributes are described in Table 27. CLK180
The output frequency (fCLKFX) can be expressed as a func-
tion of the incoming clock frequency (fCLKIN) as follows:
CLK270
fCLKFX = fCLKIN*(CLKFX_MULTIPLY/CLKFX_DIVIDE) (3) DS099-2_10_031303
Regarding the two attributes, it is possible to assign any Figure 40: Characteristics of the DLL Clock Outputs
combination of integer values, provided that two conditions
are met: DFS With or Without the DLL
1. The two values fall within their corresponding ranges, The DFS component can be used with or without the DLL
as specified in Table 27. component: Without the DLL, the DFS component multi-
plies or divides the CLKIN signal frequency according to the
respective CLKFX_MULTIPLY and CLKFX_DIVIDE values,

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generating a clock with the new target frequency on the DFS Clock Output Connections
CLKFX and CLKFX180 outputs. Though classified as
There are two basic cases that determine how to connect
belonging to the DLL component, the CLKIN input is shared
the DFS clock outputs: on-chip and off-chip, which are illus-
with the DFS component. This case does not employ feed-
trated in Figure 39a and Figure 39c, respectively. This is
back loop. Therefore, it cannot correct for clock distribution
similar to what has already been described for the DLL com-
delay.
ponent. See DLL Clock Output and Feedback Connec-
With the DLL, the DFS operates as described in the preced- tions.
ing case, only with the additional benefit of eliminating the
In the on-chip case, it is possible to connect either of the
clock distribution delay. In this case, a feedback loop from
DFS’s two output clock signals through general routing
the CLK0 output to the CLKFB input must be present.
resources to the FPGA’s internal registers. Either a Global
The DLL and DFS components work together to achieve Clock Buffer (BUFG) or a BUFGMUX affords access to the
this phase correction as follows: Given values for the global clock network. The optional feedback loop is formed
CLKFX_MULTIPLY and CLKFX_DIVIDE attributes, the DLL in this way, routing CLK0 to a global clock net, which in turn
selects the delay element for which the output clock edge drives the CLKFB input.
coincides with the input clock edge whenever mathemati- In the off-chip case, the DFS’s two output clock signals, plus
cally possible. For example, when CLKFX_MULTIPLY = 5
CLK0 for an optional feedback loop, can exit the FPGA
and CLKFX_DIVIDE = 3, the input and output clock edges
using output buffers (OBUF) to drive a clock network plus
coincide every three input periods, which is equivalent in
registers on the board. The feedback loop is formed by
time to five output periods.
feeding the CLK0 signal back into the FPGA using an
Smaller CLKFX_MULTIPLY and CLKFX_DIVIDE values IBUFG, which directly accesses the global clock network, or
achieve faster lock times. With no factors common to the an IBUF. Then the global clock net is connected directly to
two attributes, alignment occurs once with every number of the CLKFB input.
cycles equal to the CLKFX_DIVIDE value. Therefore, it is
recommended that the user reduce these values by factor- Phase Shifter (PS)
ing wherever possible. For example, given
The DCM provides two approaches to controlling the phase
CLKFX_MULTIPLY = 9 and CLKFX_DIVIDE = 6, removing
of a DCM clock output signal relative to the CLKIN signal:
a factor of three yields CLKFX_MULTIPLY = 3 and
First, there are nine clock outputs that employ the DLL to
CLKFX_DIVIDE = 2. While both value-pairs result in the
achieve a desired phase relationship: CLK0, CLK90,
multiplication of clock frequency by 3/2, the latter value-pair
CLK180, CLK270, CLK2X, CLK2X180, CLKDV CLKFX, and
enables the DLL to lock more quickly.
CLKFX180. These outputs afford “coarse” phase control.
Table 27: DFS Attributes The second approach uses the PS component described in
this section to provide a still finer degree of control. The PS
Attribute Description Values component accomplishes this by introducing a "fine phase
CLKFX_MULTIPLY Frequency Integer from shift" (TPS) between the CLKFB and CLKIN signals inside
multiplier 2 to 32, the DLL component. The user can control this fine phase
constant inclusive shift down to a resolution of 1/512 of a CLKIN cycle or one
tap delay (DCM_TAP), whichever is greater. When in use,
CLKFX_DIVIDE Frequency divisor Integer from the PS component shifts the phase of all nine DCM clock
constant 1 to 32, output signals together. If the PS component is used
inclusive together with a DCM clock output such as the CLK90,
CLK180, CLK270, CLK2X180, and CLKFX180, then the
Table 28: DFS Signals fine phase shift of the former gets added to the coarse
phase shift of the latter.
PS Component Enabling and Mode Selection
CLKFX Output Multiplies the CLKIN frequency
The CLKOUT_PHASE_SHIFT attribute enables the PS
by the attribute-value ratio
component for use in addition to selecting between two
(CLKFX_MULTIPLY/
operating modes. As described in Table 29, this attribute
CLKFX_DIVIDE) to generate a
has three possible values: NONE, FIXED, and VARIABLE.
clock signal with a new target
When CLKOUT_PHASE_SHIFT is set to NONE, the PS
frequency.
component is disabled and its inputs, PSEN, PSCLK, and
CLKFX180 Output Generates a clock signal with PSINCDEC, must be tied to GND. The set of waveforms in
same frequency as CLKFX, Figure 41a shows the disabled case, where the DLL main-
only shifted 180° out-of-phase. tains a zero-phase alignment of signals CLKFB and CLKIN
upon which the PS component has no effect. The PS com-

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ponent is enabled by setting the attribute to either the mode and the Variable Phase mode, respectively. These
FIXED or VARIABLE values, which select the Fixed Phase two modes are described in the sections that follow.
Table 29: PS Attributes

Attribute Description Values
CLKOUT_PHASE_SHIFT Disables the PS component or chooses between NONE, FIXED, VARIABLE
Fixed Phase and Variable Phase modes.
PHASE_SHIFT Determines size and direction of initial fine phase Integers from –255 to +255
shift.
Determining the Fine Phase Shift The Fixed Phase Mode

The user controls the phase shift of CLKFB relative to This mode fixes the desired fine phase shift to a fraction of
CLKIN by setting and/or adjusting the value of the the TCLKIN, as determined by Equation (4) and its
PHASE_SHIFT attribute. This value must be an integer user-selected PHASE_SHIFT value P. The set of wave-
ranging from –255 to +255. This corresponds to a phase forms in Figure 41b illustrates the relationship between
shift range of –180 to +180 degrees, which is different from CLKFB and CLKIN in the Fixed Phase mode. In the Fixed
the original Spartan-3 DCM. The PS component uses this Phase mode, the PSEN, PSCLK, and PSINCDEC inputs
value to calculate the desired fine phase shift (TPS) as a are not used and must be tied to GND.
fraction of the CLKIN period (TCLKIN). Given values for In Figure 41:
PHASE_SHIFT and TCLKIN, it is possible to calculate TPS
as follows: • P represents the integer value ranging from –255 to
+255 to which the PHASE_SHIFT attribute is assigned.
TPS = (PHASE_SHIFT/512) * TCLKIN (4) (P = approximately -90 as shown)
Both the Fixed Phase and Variable Phase operating modes • N is an integer value ranging from (P – 255) to
employ this calculation. If the PHASE_SHIFT value is zero, (+255 – P) that represents the net phase shift effect
then CLKFB and CLKIN are in phase, the same as when the from a series of increment and/or decrement
PS component is disabled. When the PHASE_SHIFT value operations.
is positive, the CLKFB signal is shifted later in time with • N = {Total number of increments} – {Total number of
respect to CLKIN. If the attribute value is negative, the decrements} provided the user does not try to
CLKFB signal is shifted earlier in time with respect to increment past + 255 or decrement past -255. A
CLKIN. positive value for N indicates a net increment; a
negative value indicates a net decrement.

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a. CLKOUT_PHASE_SHIFT = NONE
CLKIN
CLKFB
b. CLKOUT_PHASE_SHIFT = FIXED
CLKIN
Shift Range over all P Values: –255 0 +255

P
512 * TCLKIN
CLKFB
c. CLKOUT_PHASE_SHIFT = VARIABLE
CLKIN
Shift Range over all P Values: –255 0 +255

P
* TCLKIN
512
CLKFB before
Increment
Shift Range over all N Values:
N
*T
512 CLKIN
CLKFB after
Increment
DS312-2_61_021505
Figure 41: Phase Shifter Waveforms
The Variable Phase Mode nent (PSEN, PSCLK, and PSINCDEC), as defined in
The Variable Phase mode dynamically adjusts the fine Table 30.
phase shift over time using three inputs to the PS compo-
Table 30: Signals for Variable Phase Mode

PSEN(1) Input Enables PSCLK for variable phase adjustment.
PSCLK(1) Input Clock to synchronize phase shift adjustment.
PSINCDEC(1) Input Chooses between increment and decrement for phase adjustment. It is
synchronized to the PSCLK signal.
PSDONE Output Goes High to indicate that present phase adjustment is complete and PS component
is ready for next phase adjustment request. It is synchronized to the PSCLK signal.
Notes:
1. It is possible to program this input for either a true or inverted polarity.

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Just following device configuration, the PS component ini- Asserting the Reset (RST) input, returns TPS to its original
tially determines TPS by evaluating Equation (4) for the shift time, as determined by the PHASE_SHIFT attribute
value assigned to the PHASE_SHIFT attribute. Then to value. The set of waveforms in Figure 41c illustrates the
dynamically adjust that phase shift, use the three PS inputs relationship between CLKFB and CLKIN in the Variable
to increase or decrease the fine phase shift. Phase mode.
PSINCDEC is synchronized to the PSCLK clock signal,
which is enabled by asserting PSEN. It is possible to drive The Status Logic Component
the PSCLK input with the CLKIN signal or any other clock The Status Logic component not only reports on the state of
signal. A request for phase adjustment is entered as follows: the DCM but also provides a means of resetting the DCM to
For each PSCLK cycle that PSINCDEC is High, the PS an initial known state. The signals associated with the Sta-
component adds 1/512 of a CLKIN cycle to TPS. Similarly, tus Logic component are described in Table 31.
for each enabled PSCLK cycle that PSINCDEC is Low, the As a rule, the Reset (RST) input is asserted only upon con-
PS component subtracts 1/512 of a CLKIN cycle from TPS. figuring the device or changing the CLKIN frequency. A
The phase adjustment may require as many as 100 CLKIN DCM reset does not affect attribute values (e.g.,
cycles plus three PSCLK cycles to take effect, at which CLKFX_MULTIPLY and CLKFX_DIVIDE). If not used, tie
point the output PSDONE goes High for one PSCLK cycle. RST to GND.
This pulse indicates that the PS component has finished the
present adjustment and is now ready for the next request. The eight bits of the STATUS bus are defined in Table 32.
Table 31: Status Logic Signals

RST Input A High resets the entire DCM to its initial power-on state. Initializes the DLL taps for
a delay of zero. Sets the LOCKED output Low. This input is asynchronous.
STATUS[7:0] Output The bit values on the STATUS bus provide information regarding the state of DLL and
PS operation
LOCKED Output Indicates that the CLKIN and CLKFB signals are in phase by going High. The two
signals are out-of-phase when Low.
Table 32: DCM Status Bus

Bit Name Description
0 Reserved -
1 CLKIN Stopped A value of 1 indicates that the CLKIN input signal is not toggling. A value of 0 indicates toggling.
This bit functions only when the CLKFB input is connected.(1)
2 CLKFX Stopped A value of 1 indicates that the CLKFX output is not toggling. A value of 0 indicates toggling.
This bit functions only when the CLKFX or CLKFX180 output are connected.
3-6 Reserved -
Notes:
1. If only the DFS clock outputs are used, but none of the DLL clock outputs, this bit does not go High when the CLKIN signal stops.

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Stabilizing DCM Clocks Before User Mode Clock Buffers/Multiplexers

The STARTUP_WAIT attribute shown in Table 33 optionally Clock Buffers/Multiplexers either drive clock input signals
delays the end of the FPGA’s configuration process until directly onto a clock line (BUFG) or optionally provide a mul-
after the DCM locks to the incoming clock frequency. This tiplexer to switch between two unrelated, possibly asynchro-
option ensures that the FPGA remains in the Startup phase nous clock signals (BUFGMUX).
of configuration until all clock outputs generated by the Each BUFGMUX element, shown in Figure 43, is a 2-to-1
DCM are stable. When all the DCMs with their multiplexer. The select line, S, chooses which of the two
STARTUP_WAIT attribute set to TRUE assert the LOCKED inputs, I0 or I1, drives the BUFGMUX’s output signal, O, as
signal, then the FPGA completes its configuration process described in Table 34. The switching from one clock to the
and proceeds to user mode. The associated bitstream gen- other is glitch-less, and done in such a way that the output
erator (BitGen) option LCK_cycle specifies one of the six High and Low times are never shorter than the shortest
cycles in the Startup phase. The selected cycle defines the High or Low time of either input clock.
point at which configuration halts until the all the LOCKED
outputs go High. Also see Start-Up, page 91. Table 34: BUFGMUX Select Mechanism
Table 33: STARTUP_WAIT Attribute S Input O Output
Attribute Description Values 0 I0 Input
STARTUP_WAIT Delays transition TRUE, FALSE 1 I1 Input
from configuration
to user mode until
DCM locks to The BUFG clock buffer primitive drives a single clock signal
input clock. onto the clock network and is essentially the same element
as a BUFGMUX, just without the clock select mechanism.
Similarly, the BUFGCE primitive creates an enabled clock
Clocking Infrastructure buffer using the BUFGMUX select mechanism.
The Spartan-3E clocking infrastructure, shown in Figure 42, The I0 and I1 inputs to an BUFGMUX element originate
provides a series of low-capacitance, low-skew interconnect from clock input pins, DCMs, or Double-Line interconnect,
lines well-suited to carrying high-frequency signals through- as shown in Figure 43. As shown in Figure 42, there are 24
out the FPGA. The infrastructure also includes the clock BUFGMUX elements distributed around the four edges of
inputs and BUFGMUX clock buffers/multiplexers. The Xilinx the device. Clock signals from the four BUFGMUX elements
Place-and-Route (PAR) software automatically routes at the top edge and the four at the bottom edge are truly glo-
high-fanout clock signals using these resources. bal and connect to all clocking quadrants. The eight
left-edge BUFGMUX elements only connect to the two clock
Clock Inputs quadrants in the left half of the device. Similarly, the eight
Clock pins accept external clock signals and connect directly right-edge BUFGMUX elements only connect to the right
to DCMs and BUFGMUX elements. Each Spartan-3E FPGA half of the device.
has:
BUFGMUX elements are organized in pairs and share I0
• 16 Global Clock inputs (GCLK0 through GCLK15) and I1 connections with adjacent BUFGMUX elements from
located along the top and bottom edges of the FPGA a common clock switch matrix as shown in Figure 43. For
• 8 Right-Half Clock inputs (RHCLK0 through RHCLK7) example, the input on I0 of one BUFGMUX also a shared
located along the right edge input to I1 of the adjacent BUFGMUX.
• 8 Left-Half Clock inputs (LHCLK0 through LHCLK7) The clock switch matrix for the left- and right-edge BUFG-
located along the left edge MUX elements receive signals from any of the three follow-
Clock inputs optionally connect directly to DCMs using ded- ing sources: an LHCLK or RHCLK pin as appropriate, a
icated connections. Table 35 shows the clock inputs that Double-Line interconnect, or a DCM in the XC3S1200E and
feed a specific DCM within a given Spartan-3E part number. XC3S1600E devices.
Different Spartan-3E FPGA densities have different num- By contrast, the clock switch matrixes on the top and bottom
bers of DCMs. edges receive signals from any of the five following sources:
Each clock input is also optionally a user-I/O pin and con- two GCLK pins, two DCM outputs, or one Double-Line inter-
nects to internal interconnect. Some clock pad pins are connect.
input-only pins as indicated in Module 4 of the Spartan-3E Table 36 indicates permissible connections between clock
Data Sheet. inputs and BUFGMUX elements. The four BUFGMUX ele-
ments on the top edge are paired together and share inputs
from the eight global clock inputs along the top edge. Each

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BUFGMUX pair connects to four of the eight global clock The connections for the bottom-edge BUFGMUX elements
inputs, as shown in Figure 42. This optionally allows differ- is similar to the top-edge connections.
ential inputs to the global clock inputs without wasting a On the left and right edges, only two clock inputs feed each
BUFGMUX element. pair of BUFGMUX elements.
Global Clock Inputs

GCLK11 GCLK7 GCLK9 GCLK5
BUFGMUX DCM
pair DCM Clock Line
XC3S250E (X0Y1) XC3S100E (X0Y1) in Quadrant
4 X1Y10 X1Y11 X2Y10 X2Y11 4 XC3S250E (X1Y1)
BUFGMUX XC3S500E (X0Y1)
XC3S500E (X1Y1)
XC3S1200E (X1Y3) 4 4
LHCLK1 LHCLK0
XC3S1200E (X2Y3)
RHCLK7 RHCLK6
XC3S1600E (X1Y3) H G F E
X0Y9
H H
X3Y9 X3Y8
XC3S1600E (X2Y3)
X0Y8
Top Left Quadrant (TL) Top Right Quadrant (TR)

G 4 G
4
4 • • 4
4
Top Spine
DCM 8 8 DCM
XC3S1200E (X0Y2) XC3S1200E (X3Y2)
XC3S1600E (X0Y2) XC3S1600E (X3Y2)
4 • • 4
4 4
LHCLK3 LHCLK2
RHCLK5 RHCLK4 RHCLK3 RHCLK2

X3Y7
X0Y6 X0Y7
F F
Left-Half Clock Inputs
Right-Half Clock Inputs

• •
X3Y6
E Figure 44a Figure 44b
E
Left Spine 8 8 Horizontal Spine 8 8 Right Spine
LHCLK5 LHCLK4
D D
X0Y5
X3Y5 X3Y4
Figure 44a Figure 44b
• •
X0Y4
C C
Bottom Spine
4 8 8 4
4 4
DCM
XC3S1200E (X0Y1)
• • DCM
XC3S1200E (X3Y1)
XC3S1600E (X0Y1) XC3S1600E (X3Y1)
4 4
4 4
• •
LHCLK7 LHCLK6
RHCLK1 RHCLK0
X3Y3
B B
X0Y2 X0Y3
X3Y2
4
A Bottom Left Quadrant (BL) Bottom Right Quadrant (BR) A
4 4 DCM
DCM D C B A
XC3S250E (X0Y0) XC3S100E (X0Y0)
4 4 XC3S250E (X1Y0)
XC3S500E (X0Y0)
XC3S1200E (X1Y0) X1Y0 X1Y1 X2Y0 X2Y1 XC3S500E (X1Y0)
XC3S1600E (X1Y0) XC3S1200E (X2Y0)
XC3S1600E (X2Y0)

Global Clock Inputs DS312-2_04_030205
Notes:
1. Number of DCMs and locations of these DCM varies for different device densities.
2. The left and right DCMs are only in the XC3S1200E and XC3S1600E. The XC3S100E has only two DCMs, one on the top right
and one on the bottom right of the die.
Figure 42: Spartan-3E Internal Quadrant-Based Clock Network (Top View)

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Table 35: Direct Connections from Clock Inputs to DCMs and Associated DCM Location String
Clock Input XC3S100E XC3S250E/XC3S500E XC3S1200E/XC3S1600E
GCLK[3:0] DCM_X0Y0 DCM_X1Y0 DCM_X2Y0
RHCLK[3:0] N/A N/A DCM_X3Y1
RHCLK[7:4] N/A N/A DCM_X3Y2
GCLK[7:4] DCM_X0Y1 DCM_X1Y1 DCM_X2Y2
GCLK[11:8] N/A DCM_X0Y1 DCM_X1Y3
LHCLK[3:0] N/A N/A DCM_X0Y2
LHCLK[7:4] N/A N/A DCM_X0Y1
GCLK[15:12] N/A DCM_X0Y0 DCM_X1Y0
Table 36: Connections from Clock Inputs to BUFGMUX Elements and Associated Quadrant Clock
Quadrant Left-Half BUFGMUX Top or Bottom BUFGMUX Right-Half BUFGMUX
Clock
Line(1) Location(2) I0 Input I1 Input Location(2) I0 Input I1 Input Location(2) I0 Input I1 Input
GCLK0 or GCLK1 or
A X0Y2 LHCLK7 LHCLK6 X2Y1 X3Y2 RHCLK0 RHCLK1
GCLK12 GCLK13
GCLK1 or GCLK0 or
B X0Y3 LHCLK6 LHCLK7 X2Y0 X3Y3 RHCLK1 RHCLK0
GCLK13 GCLK12
GCLK2 or GCLK3 or
C X0Y4 LHCLK5 LHCLK4 X1Y1 X3Y4 RHCLK2 RHCLK3
GCLK14 GCLK15
GCLK3 or GCLK2 or
D X0Y5 LHCLK4 LHCLK5 X1Y0 X3Y5 RHCLK3 RHCLK2
GCLK15 GCLK14
GCLK4 or GCLK5 or
E X0Y6 LHCLK3 LHCLK2 X2Y11 X3Y6 RHCLK4 RHCLK5
GCLK8 GCLK9
GCLK5 or GCLK4 or
F X0Y7 LHCLK2 LHCLK3 X2Y10 X3Y7 RHCLK5 RHCLK4
GCLK9 GCLK8
GCLK6 or GCLK7 or
G X0Y8 LHCLK1 LHCLK0 X1Y11 X3Y8 RHCLK6 RHCLK7
GCLK10 GCLK11
GCLK7 or GCLK6 or
H X0Y9 LHCLK0 LHCLK1 X1Y10 X3Y9 RHCLK7 RHCLK6
GCLK11 GCLK10
Notes:
1. See Quadrant Clock Routing for connectivity details for the eight quadrant clocks.
2. See Figure 42 for specific BUFGMUX locations and Figure 44 for information on how BUFGMUX elements drive onto a specific clock line
within a quadrant.

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Left-/Right-Half BUFGMUX Top/Bottom (Global) BUFGMUX
CLK Switch CLK Switch

Matrix Matrix
BUFGMUX BUFGMUX
S S
I0 I0
0 O 0 O
I1 I1
1 1
I0 0 I0
O 0 O
I1 I1
1 1
S S
LHCLK or
RHCLK input 1st GCLK pin
Double Line 1st DCM output

Double Line
DCM output*
*(XC3S1200E and 2nd DCM output
and XC3S1600E only)
2nd GCLK pin
DS312-2_16_022505
Figure 43: Clock Switch Matrix to BUFGMUX Pair Connectivity
Quadrant Clock Routing The four quadrants of the device are:

The clock routing within the FPGA is quadrant-based, as • Top Right (TR)
shown in Figure 42. Each clock quadrant supports eight • Bottom Right (BR)
total clock signals, labeled ‘A’ through ‘H’ in Table 36 and • Bottom Left (BL)
Figure 44. The clock source for an individual clock line orig- • Top Left (TL)
inates either from a global BUFGMUX element along the
top and bottom edges or from a BUFGMUX element along Note that the quadrant clock notation (TR, BR, BL, TL) is
the associated edge, as shown in Figure 44. The clock lines separate from that used for similar IOB placement con-
feed the synchronous resource elements (CLBs, IOBs, straints.
block RAM, multipliers, and DCMs) within the quadrant.

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BUFGMUX Output Clock Line BUFGMUX Output Clock Line

X2Y1 (Global) X2Y1 (Global)
X0Y2 (Left Half)
A X3Y2 (Right Half)
A

B B
X0Y3 (Left Half) X3Y3 (Right Half)

C C

D D

X0Y6 (Left Half)
E X3Y6 (Right Half)
E

X0Y7 (Left Half)
F X3Y7 (Right Half)
F

G G

X0Y9 (Left Half)
H X3Y9 (Right Half)
H
a. Left (TL and BL Quadrants) Half of Die b. Right (TR and BR Quadrants) Half of Die
DS312-2_17_030105
Figure 44: Clock Sources for the Eight Clock Lines within a Clock Quadrant
The outputs of the top or bottom BUFGMUX elements con- in a single clock quadrant. Figure 44 shows how the clock
nect to two vertical spines, each comprising four vertical lines in each quadrant are selected from associated BUFG-
clock lines as shown in Figure 42. At the center of the die, MUX sources. For example, if quadrant clock ‘A’ in the bot-
these clock signals connect to the eight-line horizontal clock tom left (BL) quadrant originates from BUFGMUX_X2Y1,
spine. then the clock signal from BUFGMUX_X0Y2 is unavailable
Outputs of the left and right BUFGMUX elements are routed in the bottom left quadrant. However, the top left (TL) quad-
onto the left or right horizontal spines, each comprising rant clock ‘A’ can still solely use the output from either
eight horizontal clock lines. BUFGMUX_X2Y1 or BUFGMUX_X0Y2 as the source.
Each of the eight clock signals in a clock quadrant derives To minimize the dynamic power dissipation of the clock net-
either from a global clock signal or a half clock signal. In work, the Xilinx development software automatically dis-
other words, there are up to 24 total potential clock inputs to ables all clock segments not in use.
the FPGA, eight of which can connect to clocked elements

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Interconnect The switch matrix connects to the different kinds of intercon-

nects across the device. An interconnect tile, shown in
Interconnect is the programmable network of signal path-
Figure 45, is defined as a single switch matrix connected to
ways between the inputs and outputs of functional elements
a functional element, such as a CLB, IOB, or DCM. If a func-
within the FPGA, such as IOBs, CLBs, DCMs, block RAM,
tional element spans across multiple switch matrices such
etc.
as the block RAM or multipliers, then an interconnect tile is
Interconnect, also called routing, is segmented for optimal defined by the number of switch matrices connected to that
connectivity. Functionally, interconnect resources are identi- functional element. A Spartan-3E device can be repre-
cal to that of the Spartan-3 architecture. There are four sented as an array of interconnect tiles where interconnect
kinds of interconnects: long lines, hex lines, double lines, resources are for the channel between any two adjacent
and direct lines. The Xilinx Place and Route (PAR) software interconnect tile rows or columns as shown in Figure 46.
exploits the rich interconnect array to deliver optimal system
performance and the fastest compile times.
Switch
Switch
CLB Matrix
Matrix
Switch
Matrix
Switch 18Kb MULT
IOB
Matrix Block 18 x 18
Switch RAM
Matrix
Switch
DCM
Matrix Switch
Matrix
DS312_08_020905
Figure 45: Four Types of Interconnect Tiles (CLBs, IOBs, DCMs, and Block RAM/Multiplier)
Switch Switch Switch Switch Switch

IOB IOB IOB IOB
Matrix Matrix Matrix Matrix Matrix

IOB CLB CLB CLB

IOB CLB CLB CLB

IOB CLB CLB CLB

IOB CLB CLB CLB
DS312_09_020905
Figure 46: Array of Interconnect Tiles in Spartan-3E FPGA

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There are four type of general-purpose interconnect avail- Global Controls (STARTUP_SPARTAN3E)
able in each channel, as shown in Figure 47 and described
In addition to the general-purpose interconnect, Spartan-3E
below.
FPGAs have two global logic control signals, as described
in Table 37. These signals are available to the FPGA appli-
Long Lines
cation via the STARTUP_SPARTAN3E primitive.
Each set of 24 long line signals spans the die both horizon-
tally and vertically and connects to one out of every six inter- Table 37: Spartan-3E Global Logic Control Signals
connect tiles. At any tile, four of the long lines drive or
Global
receive signals from a switch matrix. Because of their low Description
Control Input
capacitance, these lines are well-suited for carrying
high-frequency signals with minimal loading effects (e.g. When driven High, asynchronously
skew). If all global clock lines are already committed and places all registers and flip-flops in their
additional clock signals remain to be assigned, long lines initial state (see Initialization, page 24).
serve as a good alternative. GSR
Asserted automatically during the FPGA
configuration process (see Start-Up,
Hex Lines page 91).
Each set of eight hex lines are connected to one out of When driven High, asynchronously
every three tiles, both horizontally and vertically. Thirty-two GTS forces all I/O pins to a high-impedance
hex lines are available between any given interconnect tile. state (Hi-Z, three-state).
Hex lines are only driven from one end of the route.
Double Lines The Global Set/Reset (GSR) signal replaces the global
reset signal included in many ASIC-style designs. Use the
Each set of eight double lines are connected to every other GSR control instead of a separate global reset signal in the
tile, both horizontally and vertically. in all four directions. design to free up CLB inputs, resulting in a smaller, more
Thirty-two double lines available between any given inter- efficient design. Similarly, the GSR signal is asserted auto-
connect tile. Double lines are more connections and more matically during the FPGA configuration process, guaran-
flexibility, compared to long line and hex lines. teeing that the FPGA starts-up in a known state.
Direct Connections The STARTUP_SPARTAN3E primitive also includes two
other signals used specifically during configuration. The
Direct connect lines route signals to neighboring tiles: verti- MBT signals are for Dynamically Loading Multiple Con-
cally, horizontally, and diagonally. These lines most often figuration Images Using MultiBoot Option, page 78. The
drive a signal from a "source" tile to a double, hex, or long CLK input is an alternate clock for configuration Start-Up,
line and conversely from the longer interconnect back to a page 91.
direct line accessing a "destination" tile.
Horizontal and 24
Vertical Long Lines
(horizontal channel
shown as an example) CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB
••
•
••
•
••
•
••
•
••
•
6 6 6 6 6
DS312-2_10_022305
Horizontal and 8
Vertical Hex Lines
(horizontal channel
shown as an example) CLB CLB CLB CLB CLB CLB CLB
DS312-2_11_020905
Figure 47: Interconnect Types between Two Adjacent Interconnect Tiles

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Horizontal and 8
Vertical Double
Lines
(horizontal channel CLB CLB CLB
shown as an example)
DS312-2_15_022305
Direct Connections
CLB CLB CLB
CLB CLB CLB
CLB CLB CLB
DS312-2_12_020905
Figure 47: Interconnect Types between Two Adjacent Interconnect Tiles

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Configuration borrowed and returned to the application as general-pur-

pose user I/Os after configuration completes.
Differences from Spartan-3 FPGAs Spartan-3E FPGAs offer several configuration options to
In general, Spartan-3E FPGA configuration modes are a minimize the impact of configuration on the overall system
superset to those available in Spartan-3 FPGAs. Two new design. In some configuration modes, the FPGA generates
modes added in Spartan-3E FPGAs provide a glue-less a clock and loads itself from an external memory source,
configuration interface to industry-standard parallel NOR either serially or via a byte-wide data path. Alternatively, an
Flash and SPI serial Flash memories. Unlike Spartan-3 external host such as a microprocessor downloads the
FPGAs, nearly all of the Spartan-3E configuration pins FPGA’s configuration data using a simple synchronous
become available as user I/Os after configuration. serial interface or via a byte-wide peripheral-style interface.
Furthermore, multiple-FPGA designs share a single config-
Configuration Process uration memory source, creating a structure called a daisy
chain.
The function of a Spartan-3E FPGA is defined by loading
application-specific configuration data into the FPGA’s Three FPGA pins—M2, M1, and M0—select the desired
internal, reprogrammable CMOS configuration latches configuration mode. The mode pin settings appear in
(CCLs), similar to the way a microprocessor’s function is Table 38. The mode pin values are sampled during the start
defined by its application program. For FPGAs, this configu- of configuration when the FPGA’s INIT_B output goes High.
ration process uses a subset of the device pins, some of After the FPGA completes configuration, the mode pins are
which are dedicated to configuration; other pins are merely available as user I/Os.
Table 38: Spartan-3E Configuration Mode Pin Settings

Master
Serial SPI BPI Slave Parallel Slave Serial JTAG
M[2:0] mode pin <0:0:0> <0:0:1> <0:1:0>=Up <1:1:0> <1:1:1> <1:0:1>

settings <0:1:1>=Down
Data width Serial Serial Byte-wide Byte-wide Serial Serial
Configuration memory Xilinx Industry-standard Industry-standard Any source via Any source via Any source via
source Platform SPI Serial Flash parallel NOR microcontroller, microcontroller, microcontroller,
Flash Flash CPU, Xilinx CPU, Xilinx CPU, etc. and
parallel Platform Flash, System Ace CF
Platform Flash, etc.
etc.
Clock source Internal Internal oscillator Internal oscillator External clock External clock External clock
oscillator on CCLK pin on CCLK pin on TCK pin
Total I/O pins

borrowed during 8 13 46 21 8 0
configuration
Configuration mode Slave Serial Slave Serial Slave Parallel Slave Parallel Slave Serial JTAG
for downstream or Memory
daisy-chained FPGAs Mapped
Self-configuring Possible using Possible using

applications (no XCFxxP Platform XCFxxP Platform
external download Flash, which Flash, which
host) optionally optionally
generates CCLK generates CCLK
Uses low-cost,
industry-standard
Flash

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A specific Spartan-3E part type always requires a constant Pin Behavior During Configuration
number of configuration bits, regardless of design complex-
Table 40 shows how various pins behave during the FPGA
ity, as shown in Table 39. The configuration file size for a
configuration process. The actual behavior depends on the
multiple-FPGA daisy-chain design equals the sum of the
values applied to the M2, M1, and M0 mode select pins and
individual file sizes.
the HSWAP pin. The mode select pins determine which of
the I/O pins are borrowed during configuration and how they
Table 39: Number of Bits to Program a Spartan-3E function. In JTAG configuration mode, no user-I/O pins are
FPGA (Uncompressed Bitstreams) borrowed for configuration.
Number of Configuration All I/O pins are high impedance (floating, three-stated, Hi-Z)
Device Bits during the configuration process. These pins are indicated
in Table 40 as shaded table entries or cells. If the HSWAP
XC3S100E 581,344 input is Low, these pins have a pull-up resistor to their asso-
XC3S250E 1,352,192 ciated VCCO supply that is active throughout configuration.
After configuration, pull-up and pull-down resistors are
XC3S500E 2,267,136 available in the FPGA application as described in Pull-Up
and Pull-Down Resistors, page 9.
XC3S1200E 3,832,320
Spartan-3E FPGAs have only six dedicated configuration
XC3S1600E 5,957,760 pins, including the DONE and PROG_B pins, and the four
JTAG boundary-scan pins: TDI, TDO, TMS, and TCK.
Table 40: Pin Behavior during Configuration

Master SPI (Serial BPI (Parallel Slave Supply/
Pin Name Serial Flash) NOR Flash) JTAG Parallel Slave Serial I/O Bank
TDI TDI TDI TDI TDI TDI TDI VCCAUX
TMS TMS TMS TMS TMS TMS TMS VCCAUX
TCK TCK TCK TCK TCK TCK TCK VCCAUX
TDO TDO TDO TDO TDO TDO TDO VCCAUX
PROG_B PROG_B PROG_B PROG_B PROG_B PROG_B PROG_B VCCAUX
DONE DONE DONE DONE DONE DONE DONE VCCAUX
HSWAP HSWAP HSWAP HSWAP HSWAP HSWAP HSWAP 0
M2 0 0 0 1 1 1 2
M1 0 0 1 0 1 1 2
M0 0 1 0 = Up 1 0 1 2
1 = Down
CCLK CCLK (O) CCLK (O) CCLK (O) CCLK (I) CCLK (I) 2
INIT_B INIT_B INIT_B INIT_B INIT_B INIT_B 2
CSO_B CSO_B CSO_B CSO_B 2
DOUT/BUSY DOUT DOUT BUSY BUSY DOUT 2
MOSI/CSI_B MOSI CSI_B CSI_B 2
D7 D7 D7 2
D6 D6 D6 2
D5 D5 D5 2
D4 D4 D4 2

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Table 40: Pin Behavior during Configuration (Continued)

Master SPI (Serial BPI (Parallel Slave Supply/
Pin Name Serial Flash) NOR Flash) JTAG Parallel Slave Serial I/O Bank
D3 D3 D3 2
D2 D2 D2 2
D1 D1 D1 2
D0/DIN DIN DIN D0 D0 DIN 2
RDWR_B RDWR_B RDWR_B 2
A23 A23 2
A22 A22 2
A21 A21 2
A20 A20 2
A19/VS2 VS2 A19 2
A18/VS1 VS1 A18 2
A17/VS0 VS0 A17 2
A16 A16 1
A15 A15 1
A14 A14 1
A13 A13 1
A12 A12 1
A11 A11 1
A10 A10 1
A9 A9 1
A8 A8 1
A7 A7 1
A6 A6 1
A5 A5 1
A4 A4 1
A3 A3 1
A2 A2 1
A1 A1 1
A0 A0 1
LDC0 LDC0 LDC0 1
LDC1 LDC1 LDC1 1
LDC2 LDC2 LDC2 1
HDC HDC HDC 1

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Table 41 shows the default I/O standard setting for the vari- drive characteristics. For example, with VCCO = 3.3V, the
ous configuration pins during the configuration process. The output current when driving High, IOH, increases to approx-
configuration interface is designed primarily for 2.5V opera- imately 12 to 16 mA, while the current when driving Low,
tion when the VCCO_2 (and VCCO_1 in BPI mode) con- IOL, remains 8 mA. At VCCO = 1.8V, the output current
nects to 2.5V. when driving High, IOH, decreases slightly to approximately
The configuration pins also operate at other voltages by set- 6 to 8 mA. Again, the current when driving Low, IOL, remains
ting VCCO_2 (and VCCO_1 in BPI mode) to either 3.3V or 8 mA.
1.8V. The change on the VCCO supply also changes the I/O
Table 41: Default I/O Standard Setting During Configuration (VCCO_2 = 2.5V)
Pin(s) I/O Standard Output Drive Slew Rate
All, including CCLK LVCMOS25 8 mA Slow
Master Serial Mode attached Platform Flash PROM. In response, the Platform
Flash PROM supplies bit-serial data to the FPGA’s DIN
In Master Serial mode (M[2:0] = <0:0:0>), the Spartan-3E
input and the FPGA accepts this data on each rising CCLK
FPGA configures itself from an attached Xilinx Platform
edge.
Flash PROM, as illustrated in Figure 48. The FPGA sup-
plies the CCLK output clock from its internal oscillator to the
+1.2V
V XCFxxS = +3.3V
VCCINT XCFxxP = +1.8V
P HSWAP VCCO_0 VCCO_0
4.7k
VCCO_2 V VCCINT
Serial Master DIN D0 VCCO V
Mode CCLK CLK
‘0’ M2 DOUT
‘0’ M1 INIT_B OE/RESET
‘0’ M0 +2.5V
Spartan-3E Platform Flash

4.7k
330
XCFxx
CE CEO
CF
+2.5V
JTAG VCCAUX +2.5V VCCJ +2.5V
TDI TDI TDO TDI TDO
TMS TMS TMS
TCK TCK TCK
TDO GND
PROG_B DONE
GND
PROG_B
Recommend
open-drain
driver
DS312-2_44_021405
Figure 48: Master Serial Mode using Platform Flash PROM

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The mode select pins, M[2:0], must all be Low when sam- FPGA configuration. After configuration, when the FPGA’s
pled, when the FPGA’s INIT_B output goes High. After con- DONE output goes High, the HSWAP pin is available as
figuration, when the FPGA’s DONE output goes High, the full-featured user-I/O pin and is powered by the VCCO_0
mode select pins are available as full-featured user-I/O pins. supply.
P Similarly, the FPGA’s HSWAP pin must be Low to The FPGA's DOUT pin is used in daisy-chain applications,
enable pull-up resistors on all user-I/O pins during configu- described later. In a single-FPGA application, the FPGA’s
ration or High to disable the pull-up resistors. The HSWAP DOUT pin is not used but is actively driving during the con-
control must remain at a constant logic level throughout figuration process.
Table 42: Serial Master Mode Connections

Pin Name FPGA Direction Description During Configuration After Configuration
HSWAP Input User I/O Pull-Up Control. When Low Drive at valid logic level User I/O
P during configuration, enables pull-up throughout configuration.
resistors in all I/O pins to respective I/O
bank VCCO input.
0: Pull-ups during configuration
1: No pull-ups
M[2:0] Input Mode Select. Selects the FPGA M2 = 0, M1 = 0, M0 = 0. User I/O
configuration mode. Sampled when INIT_B goes
High.
DIN Input Serial Data Input. Receives serial data from User I/O
PROM’s D0 output.
CCLK Output Configuration Clock. Generated by Drives PROM’s CLK clock User I/O
FPGA internal oscillator. Frequency input.
controlled by ConfigRate bitstream
generator option. If CCLK PCB trace is
long or has multiple connections,
terminate this output to maintain signal
integrity.
DOUT Output Serial Data Output. Actively drives. Not used in User I/O
single-FPGA designs. In a
daisy-chain configuration,
this pin connects to DIN input
of the next FPGA in the chain.
INIT_B Open-drain Initialization Indicator. Active Low. Goes Connects to PROM’s User I/O
bidirectional I/O Low at start of configuration during OE/RESET input. FPGA
Initialization memory clearing process. clears PROM’s address
Released at end of memory clearing, counter at start of
when mode select pins are sampled. configuration, enables
Requires external 4.7 kΩ pull-up resistor outputs during configuration.
to VCCO_2. PROM also holds FPGA in
Initialization state until PROM
reaches Power-On Reset
(POR) state. If CRC error
detected during
configuration, FPGA drives
INIT_B Low.

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Table 42: Serial Master Mode Connections (Continued)

DONE Open-drain FPGA Configuration Done. Low during Connects to PROM’s Pulled High via
bidirectional I/O configuration. Goes High when FPGA chip-enable (CE) input. external pull-up.
successfully completes configuration. Enables PROM during When High, indicates
Requires external 330 Ω pull-up resistor configuration. Disables that the FPGA
to 2.5V. PROM after configuration.
successfully
configured.
PROG_B Input Program FPGA. Active Low. When Must be High during Drive PROG_B Low
asserted Low for 300 ns or longer, forces configuration to allow and release to
the FPGA to restart its configuration configuration to start. reprogram FPGA.
process by clearing configuration Connects to PROM’s CF pin,
memory and resetting the DONE and allowing JTAG PROM
INIT_B pins once PROG_B returns High. programming algorithm to
Requires external 4.7 kΩ pull-up resistor reprogram the FPGA.
to 2.5V. If driving externally, use an
open-drain or open-collector driver.
Voltage Compatibility The XC3S1600E requires an 8 Mbit PROM. There are two
possible solutions. Either use a single 8 Mbit XCF08P par-
The PROM’s VCCINT supply must be either 3.3V for the
allel/serial PROM or cascade two 4 Mbit XCF04S serial
serial XCFxxS Platform Flash PROMs or 1.8V for the
PROMs. The two XCF04S PROMs use a 3.3V VCCINT sup-
serial/parallel XCFxxP PROMs.
ply while the XCF08P requires a 1.8V VCCINT supply. If the
V The FPGA’s VCCO_2 supply input and the Platform
board does not already have a 1.8V supply available, the
Flash PROM’s VCCO supply input must be the same volt- two cascaded XCF04S PROM solution is recommended.
age, ideally +2.5V. Both devices also support 1.8V and 3.3V
interfaces but the FPGA’s PROG_B and DONE pins require CCLK Frequency
special attention as they are powered by the FPGA’s In Master Serial mode, the FPGA’s internal oscillator gener-
VCCAUX supply, nominally 2.5V. See application note ates the configuration clock frequency. The FPGA provides
XAPP453: "The 3.3V Configuration of Spartan-3 FPGAs" this clock on its CCLK output pin, driving the PROM’s CLK
for additional information. input pin. The FPGA starts configuration at its lowest fre-
Supported Platform Flash PROMs quency and increases its frequency for the remainder of the
configuration process if so specified in the configuration bit-
Table 43 shows the smallest available Platform Flash stream. The maximum frequency is specified using the
PROM to program a single Spartan-3E FPGA. A multi- ConfigRate bitstream generator option. Table 44 shows the
ple-FPGA daisy-chain application requires a Platform Flash maximum ConfigRate settings, approximately equal to
PROM large enough to contain the sum of the various MHz, for various Platform Flash devices and I/O voltages.
FPGA file sizes. For the serial XCFxxS PROMs, the maximum frequency
also depends on the interface voltage.
Table 43: Number of Bits to Program a Spartan-3E
FPGA and Smallest Platform Flash PROM Table 44: Maximum ConfigRate Settings for Platform
Number of Flash
Configuration Smallest Available Maximum
Device Bits Platform Flash Platform Flash I/O Voltage ConfigRate
XC3S100E 581,344 XCF01S Part Number (VCCO_2, VCCO) Setting
XC3S250E 1,352,192 XCF02S XCF01S 3.3V or 2.5V 25

XCF02S
XC3S500E 2,267,136 XCF04S XCF04S 1.8V 12
XC3S1200E 3,832,320 XCF04S XCF08P

XCF16P 3.3V, 2.5V, or 1.8V 25
XC3S1600E 5,957,760 XCF08P
XCF32P
or 2 x XCF04S

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CCLK
+1.2V +1.2V
XCFxxS = +3.3V
VCCINT XCFxxP = +1.8V VCCINT
P HSWAP VCCO_0 VCCO_0 P HSWAP VCCO_0 VCCO_0
VCCO_2 V VCCINT
Slave
VCCO_2 V
Serial Master DIN D0 VCCO V Serial
Mode CCLK CLK Mode
‘0’ M2 DOUT ‘1’ M2 DOUT DOUT
‘0’ M1 INIT_B OE/RESET ‘1’ M1 INIT_B
‘0’ M0 ‘1’ M0
Spartan-3E Platform Flash Spartan-3E

XCFxx
FPGA CE CEO CCLK FPGA
CF DIN
+2.5V
JTAG VCCAUX +2.5V VCCJ +2.5V VCCAUX +2.5V
TDI TDI TDO TDI TDO TDI TDO
TMS TMS TMS TMS
TCK TCK TCK V TCK
+2.5V
TDO GND
PROG_B DONE PROG_B DONE
GND GND
4.7k
4.7k
330
PROG_B PROG_B
Recommend
open-drain TCK
driver TMS
DONE
INIT_B
DS312-2_45_021405
Figure 49: Daisy-Chaining from Master Serial Mode
Daisy-Chaining provided by the Xilinx iMPACT programming software and

the associated Xilinx Parallel Cable IV, MultiPRO, or Plat-
If the application requires multiple FPGAs with different con-
form Cable USB programming cables.
figurations, then configure the FPGAs using a daisy chain,
as shown in Figure 49. Use Master Serial mode Storing Additional User Data in Platform Flash
(M[2:0] = <0:0:0>) for the FPGA connected to the Platform
After configuration, the FPGA application can continue to
Flash PROM and Slave Serial mode (M[2:0] = <1:1:1>) for
use the Master Serial interface pins to communicate with
all other FPGAs in the daisy-chain. After the master
the Platform Flash PROM. If desired, use a larger Platform
FPGA—the FPGA on the left in the diagram—finishes load-
Flash PROM to hold additional non-volatile application data,
ing its configuration data from the Platform Flash, the mas-
such as MicroBlaze processor code, or other user data such
ter device supplies data using its DOUT output pin to the
as serial numbers and Ethernet MAC IDs. The FPGA first
next device in the daisy-chain, on the falling CCLK edge.
configures from Platform Flash PROM. Then using FPGA
JTAG Interface logic after configuration, the FPGA copies MicroBlaze code
Both the Spartan-3E FPGA and the Platform Flash PROM from Platform Flash into external DDR SDRAM for code
have a four-wire IEEE 1149.1/1532 JTAG port. Both devices execution.
share the TCK clock input and the TMS mode select input. See XAPP694: "Reading User Data from Configuration
The devices may connect in either order on the JTAG chain PROMs" and XAPP482: "MicroBlaze Platform Flash/PROM
with the TDO output of one device feeding the TDI input of Boot Loader and User Data Storage" for specific details on
the following device in the chain. The TDO output of the last how to implement such an interface.
device in the JTAG chain drives the JTAG connector.
The JTAG interface on Spartan-3E FPGAs is powered by
SPI Serial Flash Mode
the 2.5V VCCAUX supply. Consequently, the PROM’s VCCJ In SPI Serial Flash mode (M[2:0] = <0:0:0>), the Spartan-3E
supply input must also be 2.5V. To create a 3.3V JTAG inter- FPGA configures itself from an attached industry-standard
face, please refer to application note XAPP453: "The 3.3V SPI serial Flash PROM, as illustrated in Figure 50 and
Configuration of Spartan-3 FPGAs" for additional informa- Figure 52. The FPGA supplies the CCLK output clock from
tion. its internal oscillator to the clock input of the attached SPI
Flash PROM.
In-System Programming Support
Both the FPGA and the Platform Flash PROM are in-system
programmable via the JTAG chain. Download support is

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+1.2V +3.3V
SPI
VCCINT
Serial
P Flash
4.7k
I
VCCO_2 +3.3V VCC
MOSI DATA_IN
SPI Mode DIN DATA_OUT
‘0’ M2 CSO_B SELECT
‘0’ M1 W WR_PROTECT
‘1’ M0 ‘1’ HOLD
CLOCK
Variant Select Spartan-3E
GND
‘1’ VS2 FPGA
+3.3V
S VS1
‘1’ VS0 CCLK
4.7k
DOUT
INIT_B
+2.5V +2.5V
JTAG VCCAUX +2.5V
TDI TDI TDO
TMS TMS
4.7k
330
TCK TCK
TDO
PROG_B DONE
GND
PROG_B
Recommend
open-drain
driver DS312-2_46_021405
Figure 50: SPI Flash PROM Interface for PROMs Supporting READ (0x03) and FAST_READ (0x0B)
S Although SPI is a standard four-wire interface, various Figure 50 shows the general connection diagram for those
available SPI Flash PROMs use different command proto- SPI Flash PROMs that support the 0x03 READ command
cols. The FPGA’s variant select pins, VS[2:0], define how or the 0x0B FAST READ commands.
the FPGA communicates with the SPI Flash, including Figure 51 shows the connection diagram for Atmel
which SPI Flash command the FPGA issues to start the DataFlash serial PROMs, which also use an SPI-based pro-
read operation and the number of dummy bytes inserted tocol.
before the FPGA expects to receive valid data from the SPI
Flash. Table 45 shows the available SPI Flash PROMs Figure 54 demonstrates how to configure multiple FPGAs
expected to operate with Spartan-3E FPGAs. Other com- with different configurations, all stored in a single SPI Flash.
patible devices might work but have not been tested for suit- The diagram uses standard SPI Flash memories but the
ability with Spartan-3E FPGAs. All other VS[2:0] values are same general technique applies for Atmel DataFlash.
reserved for future use.

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+1.2V +3.3V
Atmel
VCCINT
AT45DB
P DataFlash
4.7k
I
VCCO_2 +3.3V VCC
MOSI SI
SPI Mode Power-on monitor is only required if
DIN SO +3.3V (VCCO_2) supply is last supply
‘0’ M2 CSO_B CS in power-on sequence, after VCCINT
and VCCAUX. Must delay FPGA
‘0’ M1 W WP configuration for > 20 ms after SPI
‘1’ M0 ‘1’ RESET DataFlash reaches its minimum VCC.
Force FPGA INIT_B input or PROG_B
RDY/BUSY input Low with an open-drain or open-
Variant Select Spartan-3E SCK collector driver.
‘1’ VS2 FPGA
+3.3V GND
‘1’ VS1 +3.3V
4.7kΩ
‘0’ VS0 CCLK
DOUT
INIT_B Power-On
INIT_B
+2.5V Monitor
VCCAUX +2.5V +2.5V
JTAG
TDI TDI TDO
TMS TMS
4.7kΩ
330Ω
TCK TCK
TDO or
PROG_B DONE
GND +3.3V
Power-On
PROG_B PROG_B
Monitor
Recommend
open-drain
driver
DS312-2_50a_022305
Figure 51: Atmel SPI-based DataFlash Configuration Interface

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Table 45: Variant Select Codes for SPI Serial Flash PROMs
SPI Read Dummy
VS2 VS1 VS0 Command Bytes SPI Serial Flash Vendor SPI Flash Family
STMicroelectronics (ST) M25Pxx
NexFlash NX25Pxx
FAST READ (0x0B)
1 1 1 1 SST25LFxxxA
(see Figure 50) Silicon Storage Technology (SST)
SST25VFxxxA
Programmable Microelectronics Corp. (PMC) Pm25LVxxx
STMicroelectronics (ST) M25Pxx
NexFlash NX25Pxx
READ (0x03) SST25LFxxxA
1 0 1 0
(see Figure 50) Silicon Storage Technology (SST) SST25VFxxxA
SST25VFxxx
Programmable Microelectronics Corp. (PMC) Pm25LVxxx
READ ARRAY
1 1 0 (0xE8) 3 Atmel Corporation AT45DB DataFlash
(see Figure 51)
Others Reserved
W Table 46 shows the connections between the SPI Flash are not used by the FPGA during configuration. However,
PROM and the FPGA’s SPI configuration interface. Each the HOLD pin must be High during the configuration pro-
SPI Flash PROM vendor uses slightly different signal nam- cess. The PROM’s write protect input must be High in order
ing. The SPI Flash PROM’s write protect and hold controls to write or program the Flash memory.
Table 46: SPI Flash PROM Connections and Pin Naming

Silicon
Storage Atmel
SPI Flash Pin FPGA Connection STMicro NexFlash Technology DataFlash
DATA_IN MOSI D DI SI SI
DATA_OUT DIN Q DO SO SO
SELECT CSO_B S CS CE# CS
CLOCK CCLK C CLK SCK SCK
Not required for FPGA configuration. Must be
WR_PROTECT High to program SPI Flash. Optional
W WP WP# WP
W connection to FPGA user I/O after
configuration.
Not required for FPGA configuration but must
HOLD be High during configuration. Optional
connection to FPGA user I/O after HOLD HOLD HOLD# N/A
(see Figure 50) configuration. Not applicable to Atmel
DataFlash.

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Table 46: SPI Flash PROM Connections and Pin Naming (Continued)
Silicon
Storage Atmel
SPI Flash Pin FPGA Connection STMicro NexFlash Technology DataFlash
Only applicable to Atmel DataFlash. Not
required for FPGA configuration but must be
RESET High during configuration. Optional
connection to FPGA user I/O after N/A N/A N/A RESET
(see Figure 51) configuration. Do not connect to FPGA’s
PROG_B as this will prevent direct
programming of the DataFlash.
Only applicable to Atmel DataFlash and only
RDY/BUSY available on certain packages. Not required
for FPGA configuration. Output from N/A N/A N/A RDY/BUSY
(see Figure 51) DataFlash PROM. Optional connection to
FPGA user I/O after configuration.
The mode select pins, M[2:0], and the variant select pins, able the pull-up resistors. The HSWAP control must remain
VS[2:0] are sampled when the FPGA’s INIT_B output goes at a constant logic level throughout FPGA configuration.
High and must be at defined logic levels during this time. After configuration, when the FPGA’s DONE output goes
After configuration, when the FPGA’s DONE output goes High, the HSWAP pin is available as full-featured user-I/O
High, these pins are all available as full-featured user-I/O pin and is powered by the VCCO_0 supply.
pins. In a single-FPGA application, the FPGA’s DOUT pin is not
P Similarly, the FPGA’s HSWAP pin must be Low to used but is actively driving during the configuration process.
enable pull-up resistors on all user-I/O pins or High to dis-
Table 47: Serial Peripheral Interface (SPI) Connections

HSWAP Input User I/O Pull-Up Control. When Drive at valid logic level User I/O
Low during configuration, enables throughout configuration.
P
pull-up resistors in all I/O pins to
respective I/O bank VCCO input.
1: No pull-ups
M[2:0] Input Mode Select. Selects the FPGA M2 = 0, M1 = 0, M0 = 1. User I/O

configuration mode. Sampled when INIT_B goes
High.
VS[2:0] Input Variant Select. Instructs the Must be at the logic levels User I/O
FPGA how to communicate with shown in Table 45. Sampled
S
the attached SPI Flash PROM. when INIT_B goes High.
MOSI Output Serial Data Output. FPGA sends SPI Flash memory User I/O
read commands and starting
address to the PROM’s serial
data input.
DIN Input Serial Data Input. FPGA receives serial data from User I/O
PROM’s serial data output.

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Table 47: Serial Peripheral Interface (SPI) Connections (Continued)

CSO_B Output Chip Select Output. Active Low. Connects to the SPI Flash Drive CSO_B High after
PROM’s chip-select input. If configuration to disable the
HSWAP = 1, connect this signal SPI Flash and reclaim the
to a 4.7 kΩ pull-up resistor to MOSI, DIN, and CCLK pins.
3.3V.
Optionally, re-use this pin
and MOSI, DIN, and CCLK
to continue communicating
with SPI Flash.
CCLK Output Configuration Clock. Generated Drives PROM’s clock input. User I/O
by FPGA internal oscillator.
Frequency controlled by
ConfigRate bitstream generator
option. If CCLK PCB trace is long
or has multiple connections,
terminate this output to maintain
signal integrity.
DOUT Output Serial Data Output. Actively drives. Not used in User I/O
single-FPGA designs. In a
daisy-chain configuration, this
pin connects to DIN input of the
next FPGA in the chain.
INIT_B Open-drain Initialization Indicator. Active Active during configuration. If User I/O
bidirectional I/O Low. Goes Low at start of SPI Flash PROM requires > 2
configuration during Initialization ms to awake after powering on,
memory clearing process. hold INIT_B Low until PROM is
Released at end of memory ready. If CRC error detected
clearing, when mode select pins during configuration, FPGA
are sampled. In daisy-chain drives INIT_B Low.
applications, this signal requires
an external 4.7 kΩ pull-up resistor
to VCCO_2.
DONE Open-drain FPGA Configuration Done. Low Low indicates that the FPGA is Pulled High via external
bidirectional I/O during configuration. Goes High not yet configured. pull-up. When High,
when FPGA successfully indicates that the FPGA
completes configuration. Requires successfully configured.
external 330 Ω pull-up resistor to
2.5V.
PROG_B Input Program FPGA. Active Low. Must be High to allow Drive PROG_B Low and
When asserted Low for 300 ns or configuration to start. release to reprogram
longer, forces the FPGA to restart FPGA. Hold PROG_B to
its configuration process by force FPGA I/O pins into
clearing configuration memory and
Hi-Z, allowing direct
resetting the DONE and INIT_B
programming access to SPI
pins once PROG_B returns High.
Requires external 4.7 kΩ pull-up Flash PROM pins.
resistor to 2.5V. If driving
externally, use an open-drain or
open-collector driver.
Voltage Compatibility I/O Bank 2. Consequently, the FPGA’s VCCO_2 supply volt-
age must also be 3.3V to match the SPI Flash PROM.
Available SPI Flash PROMs use a single 3.3V supply volt-
age. All of the FPGA’s SPI Flash interface signals are within

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Power-On Precautions if 3.3V Supply is Last in The SPI Flash PROM is powered by the same voltage sup-
Sequence ply feeding the FPGA's VCCO_2 voltage input, typically
3.3V. SPI Flash PROMs specify that they cannot be
Spartan-3E FPGAs have a built-in power-on reset (POR)
accessed until their VCC supply reaches its minimum data
circuit, as shown in Figure 63. The FPGA waits for its three
sheet voltage, followed by an additional delay. For some
power supplies — VCCINT, VCCAUX, and VCCO to I/O
devices, this additional delay is as little as 10 µs as shown in
Bank 2 (VCCO_2) — to reach their respective power-on
Table 48. For other vendors, it is as much as 20 ms.
thresholds before beginning the configuration process.
Table 48: Example Minimum Power-On to Select Times for Various SPI Flash PROMs
SPI Flash PROM Data Sheet Minimum Time from VCC, min. to Select = Low
Vendor
Part Number Symbol Value Units
STMicroelectronics M25Pxx TVSL 10 µs
NexFlash NX25xx TVSL 10 µs
Silicon Storage Technology SST25LFxx TPU-READ 10 µs
Programmable
Pm25LVxxx TVCS 50 µs
Microelectronics Corporation
Atmel Corporation AT45DBxx 20 ms
In many systems, the 3.3V supply feeding the FPGA's minimum in Module 3), after which the FPGA deasserts
VCCO_2 input is valid before the FPGA's other VCCINT INIT_B, selects the SPI Flash PROM, and starts sending
and VCCAUX supplies, and consequently, there is no issue. the appropriate read command. The SPI Flash PROM must
However, if the 3.3V supply feeding the FPGA's VCCO_2 be ready for read operations at this time.
supply is last in the sequence, a potential race occurs If the 3.3V supply is last in the sequence and does not ramp
between the FPGA and the SPI Flash PROM, as shown in fast enough, or if the SPI Flash PROM cannot be ready
Figure 52. when required by the FPGA, delay the FPGA configuration
If the FPGA's VCCINT and VCCAUX supplies are already process by holding either the FPGA's PROG_B input or
valid, then the FPGA waits for VCCO_2 to reach its mini- INIT_B input Low, as highlighted in Figure 51. Release the
mum threshold voltage before starting configuration. This FPGA when the SPI Flash PROM is ready. For example, a
threshold voltage is labeled as VCCO2T in Module 3 and simple R-C delay circuit attached to the INIT_B pin forces
ranges from approximately 0.4V to 1.0V, substantially lower the FPGA to wait for a preselected amount of time. Alter-
than the SPI Flash PROM's minimum voltage. Once all nately, a Power Good signal from the 3.3V supply or a sys-
three FPGA supplies reach their respective Power On tem reset signal accomplishes the same purpose. Use an
Reset (POR) thresholds, the FPGA starts the configuration open-drain or open-collector output when driving PROG_B
process and begins initializing its internal configuration or INIT_B.
memory. Initialization requires approximately 1 ms (TPOR,
3.3V Supply
SPI Flash cannot be selected
SPI Flash PROM SPI Flash available for

minimum voltage read operations
SPI Flash
PROM CS SPI Flash PROM must
delay (tVSL ) be ready for FPGA
FPGA VCCO_2 minimum access otherwise delay
Power On Reset Voltage FPGA configuration
(VCCO2T )
(VCCINT, VCCAUX FPGA initializes configuration FPGA accesses

already valid) memory (TPOR) SPI Flash PROM
Time DS312-2_50b_022405
Figure 52: SPI Flash PROM/FPGA Power-On Timing if 3.3V Supply is Last in Power-On Sequence

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SPI Flash PROM Density Requirements ing for the SPI Flash device. Without examining the timing
for a specific SPI Flash PROM, use ConfigRate = 12,
Table 49 shows the smallest usable SPI Flash PROM to
which is approximately 12 MHz. SPI Flash PROMs that sup-
program a single Spartan-3E FPGA. Commercially avail-
port the FAST READ command support higher data rates.
able SPI Flash PROMs range in density from 1 Mbit to 128
Some such PROMs support up to ConfigRate = 25 and
Mbits. A multiple-FPGA daisy-chained application requires
beyond but require careful data sheet analysis.
a SPI Flash PROM large enough to contain the sum of the
FPGA file sizes. An application can also use a larger-den- Using the SPI Flash Interface after Configuration
sity SPI Flash PROM to hold additional data beyond just
After the FPGA successfully completes configuration, all of
FPGA configuration data. For example, the SPI Flash
the pins connected to the SPI Flash PROM are available as
PROM can also store application code for a MicroBlaze™
user-I/O pins.
RISC processor core integrated in the Spartan-3E FPGA.
See Using the SPI Flash Interface after Configuration. If not using the SPI Flash PROM after configuration, drive
CSO_B High to disable the PROM. The MOSI, DIN, and
CCLK pins are then available to the FPGA application.
Table 49: Number of Bits to Program a Spartan-3E
FPGA and Smallest SPI Flash PROM Because all the interface pins are user I/O after configura-
tion, the FPGA application can continue to use the SPI
Number of Flash interface pins to communicate with the SPI Flash
Configuration Smallest Usable PROM, as shown in Figure 53. SPI Flash PROMs offer ran-
Device Bits SPI Flash PROM dom-accessible, byte-addressable, read/write, non-volatile
XC3S100E 581,344 1 Mbit storage to the FPGA application.
SPI Flash PROMs are available in densities ranging from
XC3S250E 1,352,192 2 Mbit 1 Mbit up to 128 Mbits. However, a single Spartan-3E FPGA
XC3S500E 2,267,136 4 Mbit requires less than 6 Mbits. If desired, use a larger SPI Flash
PROM to contain additional non-volatile application data,
XC3S1200E 3,832,320 4 Mbit such as MicroBlaze processor code, or other user data such
as serial numbers and Ethernet MAC IDs. In the example
XC3S1600E 5,957,760 8 Mbit
shown in Figure 53, the FPGA configures from SPI Flash
PROM. Then using FPGA logic after configuration, the
CCLK Frequency
FPGA copies MicroBlaze code from SPI Flash into external
In SPI Flash mode, the FPGA’s internal oscillator generates DDR SDRAM for code execution. Similarly, the FPGA appli-
the configuration clock frequency. The FPGA provides this cation can store non-volatile application data within the SPI
clock on its CCLK output pin, driving the PROM’s clock input Flash PROM.
pin. The FPGA starts configuration at its lowest frequency
The FPGA configuration data is stored starting at location 0.
and increases its frequency for the remainder of the config-
Store any additional data beginning in the next available SPI
uration process if so specified in the configuration bitstream.
Flash PROM sector or page. Do not mix configuration data
The maximum frequency is specified using the ConfigRate
and user data in the same sector or page.
bitstream generator option. The maximum frequency sup-
ported by the FPGA configuration logic depends on the tim-

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Spartan-3E FPGA
SPI Serial Flash PROM
FFFFF
User Data
DDR SDRAM
MOSI DATA_IN
DIN DATA_OUT MicroBlaze
FPGA-based Code
SPI Master CCLK CLOCK
CSO_B SELECT FPGA
Configuration
User-I/O +3.3V 0
4.7kΩ
SPI Peripherals
• A/D Converter
DATA_IN • D/A Converter
• CAN Controller
DATA_OUT • Temperature Sensor
CLOCK • Displays
SELECT • Temperature Sensor
• Microcontroller
• ASSP
To other SPI slave peripherals DS312-2_47_022205
Figure 53: Using the SPI Flash Interface After Configuration
Similarly, the SPI bus can be expanded to additional SPI peripheral data sheet for specific interface and communica-
peripherals. Because SPI is a common industry-standard tion protocol requirements.
interface, there are a variety of SPI-based peripherals avail-
able, including analog-to-digital (A/D) converters, digi-
Daisy-Chaining
tal-to-analog (D/A) converters, CAN controllers, and If the application requires multiple FPGAs with different con-
temperature sensors. figurations, then configure the FPGAs using a daisy chain,
as shown in Figure 54. Use SPI Flash mode
The MOSI, DIN, and CCLK pins are common to all SPI
(M[2:0] = <0:0:1>) for the FPGA connected to the Platform
peripherals. Connect the select input on each additional SPI
Flash PROM and Slave Serial mode (M[2:0] = <1:1:1>) for
peripheral to one of the FPGA user I/O pins. If HSWAP = 0
all other FPGAs in the daisy-chain. After the master
during configuration, the FPGA holds the select line High. If
FPGA—the FPGA on the left in the diagram—finishes load-
HSWAP = 1, connect the select line to +3.3V via an external
ing its configuration data from the SPI Flash PROM, the
4.7 kΩ pull-up resistor to avoid spurious read or write oper-
master device uses its DOUT output pin to supply data to
ations. After configuration, drive the select line Low to select
the next device in the daisy-chain, on the falling CCLK edge.
the desired SPI peripheral. Refer to the individual SPI

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CCLK
+1.2V +3.3V +1.2V
SPI
VCCINT
Serial VCCINT
P Flash
4.7k
I
VCCO_2 +3.3V VCC VCCO_2 +3.3V
Slave
MOSI DATA_IN Serial
SPI Mode DIN DATA_OUT Mode
‘0’ M2 CSO_B SELECT ‘1’ M2
‘0’ M1 W WR_PROTECT ‘1’ M1
‘1’ M0 ‘1’ HOLD ‘1’ M0
CLOCK
Variant Select
Spartan-3E GND Spartan-3E
‘1’ VS2 FPGA FPGA
S VS1
‘1’ VS0 CCLK CCLK
DOUT DIN DOUT DOUT
INIT_B INIT_B
+2.5V
JTAG VCCAUX +2.5V VCCAUX +2.5V
TDI TDI TDO TDI TDO
TMS TMS TMS
TCK TCK TCK
+2.5V +3.3V
TDO
GND GND
4.7k
4.7k
330
PROG_B PROG_B
Recommend
open-drain TCK
driver TMS
DONE
INIT_B
DS312-2_48_021405
Figure 54: Daisy-Chaining from SPI Flash Mode
In-System Programming Support to a 24-bit address lines to access an attached parallel

I In a production application, the SPI Flash PROM is usu- Flash. Only 20 address lines are generated for Spartan-3E
FPGAs in the TQ144 package. The BPI mode is not avail-
ally pre-programmed before it is mounted on the printed cir-
able for Spartan-3E FPGAs in the VQ100 package.
cuit board. In-system programming support is available
from some third-party PROM programmers using a socket The interface is designed for standard parallel NOR Flash
adapter with attached wires. To gain access to the SPI PROMs and supports both byte-wide (x8) and
Flash signals, drive the FPGA’s PROG_B input Low with an byte-wide/halfword (x8/x16) PROMs. The interface does not
open-drain driver. This action places all FPGA I/O pins, support halfword-only (x16) PROMs. The interface works
including those attached to the SPI Flash, in high-imped- equally wells with other memories that use a similar inter-
ance (Hi-Z). If the HSWAP input is High, the I/Os have face such as SRAM, NVRAM, EEPROM, EPROM, or
pull-up resistors to the VCCO input on their respective I/O masked ROM but is primarily designed for Flash memory.
bank. The external programming hardware then has direct There is another type of Flash memory called NAND Flash,
access to the SPI Flash pins. The programming access which is commonly used in memory cards for digital cam-
points are highlighted in the gray box in Figure 50, eras, etc. Spartan-3E FPGAs do not configure directly from
Figure 51, and Figure 54. NAND Flash memories.
Byte-Wide Peripheral Interface (BPI) Parallel The FPGA’s internal oscillator controls the interface timing
and the FPGA supplies the clock on the CCLK output pin.
Flash Mode However, the CCLK signal is not used in single FPGA appli-
In Byte-wide Peripheral Interface (BPI) mode cations. Similarly, the FPGA drives three pins Low during
(M[2:0] = <0:1:0> or <0:1:1>), a Spartan-3E FPGA config- configuration (LDC[2:0]) and one pin High during configura-
ures itself from an industry-standard parallel NOR Flash tion (HDC) to the PROM’s control inputs.
PROM, as illustrated in Figure 55. The FPGA generates up

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+1.2V
V
VCCINT
I
VCCO_1 V VCCO
LDC0 CE# x8 or
LDC1 OE# x8/x16
HDC WE#
Flash
PROM
Not available LDC2 BYTE#
in VQ100 A[16:0] D
package
DQ[15:7]
BPI Mode VCCO_2 V
‘0’ M2 D[7:0] DQ[7:0]
‘1’ M1 A[23:17] A[n:0]
A M0 GND
V
Spartan-3E BUSY
4.7kΩ
FPGA CCLK
‘0’ CSI_B CSO_B
‘0’ RDWR_B INIT_B
+2.5V
JTAG VCCAUX +2.5V +2.5V
TDI TDI TDO
TMS TMS
4.7kΩ
330Ω
TCK TCK
TDO
PROG_B DONE
GND
PROG_B
Recommend
open-drain
driver DS312-2_49_022305
Figure 55: Byte-wide Peripheral Interface (BPI) Mode Configured from Parallel NOR Flash PROMs
A During configuration, the value of the M0 mode pin Depending on the specific processor architecture, the pro-
determines how the FPGA generates addresses, as shown cessor boots either from the top or bottom of memory. The
Table 50. When M0 = 0, the FPGA generates addresses FPGA is flexible and boots from the opposite end of mem-
starting at 0 and increments the address on every falling ory from the processor. Only the processor or the FPGA can
CCLK edge. Conversely, when M0 = 1, the FPGA gener- boot at any given time. The FPGA can configure first, hold-
ates addresses starting at 0xFF_FFFF (all ones) and decre- ing the processor in reset or the processor can boot first,
ments the address on every falling CCLK edge. asserting the FPGA’s PROG_B pin.
The mode select pins, M[2:0], are sampled when the
Table 50: BPI Addressing Control FPGA’s INIT_B output goes High and must be at defined
logic levels during this time. After configuration, when the
M2 M1 M0 Start Address Addressing FPGA’s DONE output goes High, the mode pins are avail-
0 0 Incrementing able as full-featured user-I/O pins.
0 1 P Similarly, the FPGA’s HSWAP pin must be Low to
1 0xFF_FFFF Decrementing
enable pull-up resistors on all user-I/O pins or High to dis-
able the pull-up resistors. The HSWAP control must remain
This addressing flexibility allows the FPGA to share the par-
at a constant logic level throughout FPGA configuration.
allel Flash PROM with an external or embedded processor.
After configuration, when the FPGA’s DONE output goes

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High, the HSWAP pin is available as full-featured user-I/O actively drives during configuration and is available as a
pin and is powered by the VCCO_0 supply. user I/O after configuration.
The RDWR_B and CSI_B must be Low throughout the con- After configuration, all of the interface pins except DONE
figuration process. After configuration, these pins also and PROG_B are available as user I/Os. Furthermore, the
become user I/O. bidirectional SelectMAP configuration peripheral interface
In a single-FPGA application, the FPGA’s CSO_B and (see Slave Parallel Mode) is available after configuration.
CCLK pins are not used but are actively driving during the To continue using SelectMAP mode, set the Persist bit-
configuration process. The BUSY pin is not used but also stream generator option to Yes. An external host can then
read and verify configuration data.
Table 51: Byte-Wide Peripheral Interface (BPI) Connections
P Low during configuration, enables throughout configuration.
1: No pull-ups
M[2:0] Input Mode Select. Selects the FPGA M2 = 0, M1 = 1. Set M0 = 0 to User I/O
configuration mode. start at address 0, increment
A
addresses. Set M0 = 1 to start at
address 0xFFFFFF and
decrement addresses. Sampled
when INIT_B goes High.
CSI_B Input Chip Select Input. Active Low. Must be Low throughout User I/O. If bitstream
configuration. option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
RDWR_B Input Read/Write Control. Active Low Must be Low throughout User I/O. If bitstream
write enable. Read functionality configuration. option Persist=Yes,
typically only used after becomes part of
configuration, if bitstream option SelectMap parallel
Persist=Yes. peripheral interface.
LDC0 Output PROM Chip Enable Connect to PROM chip-select User I/O
input (CE#). FPGA drives this
signal Low throughout
configuration.
LDC1 Output PROM Output Enable Connect to PROM output-enable User I/O
input (OE#). FPGA drives this
signal Low throughout
configuration.
HDC Output PROM Write Enable Connect to PROM write-enable User I/O
input (WE#). FPGA drives this
signal High throughout
configuration.
LDC2 Output PROM Byte Mode This signal is not used for x8 User I/O. Drive this pin
D PROMs. For PROMs with a High after configuration to
x8/x16 data width control, use a x8/x16 PROM in
connect to PROM byte-mode x16 mode.
input (BYTE#). See Precautions
Using x8/x16 Flash PROMs.
FPGA drives this signal Low
throughout configuration.

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Table 51: Byte-Wide Peripheral Interface (BPI) Connections (Continued)

A[23:0] Output Address Connect to PROM address User I/O

inputs. High order address lines
may not be available in all
packages and not all may be
required. Number of address
lines required depends on the
size of the attached Flash PROM.
FPGA address generation
controlled by M0 mode pin.
Addresses presented on falling
CCLK edge.
Only 20 address lines are
available in TQ144 package.
D[7:0] Input Data Input FPGA receives byte-wide data on User I/O If bitstream
these pins in response the option Persist=Yes,
address presented on A[23:0]. becomes part of
Data captured by FPGA SelectMap parallel
CSO_B Output Chip Select Output. Active Low. Not used in single FPGA User I/O
applications. In a daisy-chain
configuration, this pin connects to
the CSI_B pin of the next FPGA in
the chain. Actively drives.
BUSY Output Busy Indicator. Typically only Not used during configuration but User I/O. If bitstream
used after configuration, if actively drives. option Persist=Yes,
bitstream option Persist=Yes. becomes part of
SelectMap parallel
CCLK Output Configuration Clock. Generated Not used in single FPGA User I/O If bitstream
by FPGA internal oscillator. applications but actively drives. In option Persist=Yes,
Frequency controlled by a daisy-chain configuration, becomes part of
ConfigRate bitstream generator drives the CCLK inputs of all other SelectMap parallel
option. If CCLK PCB trace is long FPGAs in the daisy-chain. peripheral interface.
or has multiple connections,
terminate this output to maintain
signal integrity.
bidirectional I/O Low. Goes Low at start of CRC error detected during
configuration during Initialization configuration, FPGA drives
memory clearing process. INIT_B Low.
Released at end of memory
clearing, when mode select pins
are sampled. In daisy-chain
to VCCO_2.

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Table 51: Byte-Wide Peripheral Interface (BPI) Connections (Continued)

2.5V.
longer, forces the FPGA to restart FPGA. Hold PROG_B to
its configuration process by force FPGA I/O pins into
clearing configuration memory and Hi-Z, allowing direct
resetting the DONE and INIT_B programming access to
pins once PROG_B returns High. Flash PROM pins.
Requires external 4.7 kΩ pull-up
resistor to 2.5V. If driving
externally, use an open-drain or
open-collector driver.
Voltage Compatibility shows the minimum required number of address lines

V The FPGA’s parallel Flash interface signals are within between the FPGA and parallel Flash PROM. The actual
I/O Banks 1 and 2. The majority of parallel Flash PROMs number of address line required depends on the density of
use a single 3.3V supply voltage. Consequently, in most the attached parallel Flash PROM.
cases, the FPGA’s VCCO_1 and VCCO_2 supply voltages A multiple-FPGA daisy-chained application requires a par-
must also be 3.3V to match the parallel Flash PROM. There allel Flash PROM large enough to contain the sum of the
are some 1.8V parallel Flash PROMs available and the FPGA file sizes. An application may also use a larger-den-
FPGA interfaces with these devices if the VCCO_1 and sity parallel Flash PROM to hold additional data beyond just
VCCO_2 supplies are also 1.8V. FPGA configuration data. For example, the parallel Flash
PROM could also contain the application code for a Micro-
Supported Parallel NOR Flash PROM Densities Blaze RISC processor core implemented within the Spar-
Table 52 indicates the smallest usable parallel Flash PROM tan-3E FPGA. After configuration, the MicroBlaze processor
to program a single Spartan-3E FPGA. Parallel Flash den- could execute directly from external Flash or could copy the
sity is specified in bits but addressed as bytes. The FPGA code to other, faster system memory before executing the
presents up to 24 address lines during configuration but not code.
all are required for single FPGA applications. Table 52
Table 52: Number of Bits to Program a Spartan-3E FPGA and Smallest Parallel Flash PROM
Uncompressed Smallest Usable Parallel Minimum Required Address
Device File Sizes (bits) Flash PROM Lines
XC3S100E 581,344 1 Mbit A[16:0]
XC3S250E 1,352,192 2 Mbit A[17:0]
XC3S500E 2,267,136 4 Mbit A[18:0]
XC3S1200E 3,832,320 4 Mbit A[18:0]
XC3S1600E 5,957,760 8 Mbit A[19:0]
CCLK Frequency stream. The maximum frequency is specified using the

In BPI mode, the FPGA’s internal oscillator generates the ConfigRate bitstream generator option. Table 53 shows the
configuration clock frequency that controls all the interface maximum ConfigRate settings, approximately equal to
timing. The FPGA starts configuration at its lowest fre- MHz, for various PROM read access times. Despite using
quency and increases its frequency for the remainder of the slower ConfigRate settings, BPI mode is equally fast as the
configuration process if so specified in the configuration bit- other configuration modes. In BPI mode, data is accessed

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at the ConfigRate frequency and internally serialized with ous read or write operations. After configuration, drive the
an 8X clock frequency. select line Low to select the desired peripheral. Refer to the
individual peripheral data sheet for specific interface and
Table 53: Maximum ConfigRate Settings for Parallel
communication protocol requirements.
Flash PROMs
The FPGA optionally supports a 16-bit peripheral interface
Maximum ConfigRate by driving the LDC2 (BYTE#) control pin High after configu-
Flash Read Access Time Setting ration. See Precautions Using x8/x16 Flash PROMs for
< 200 ns 3 additional information.
The FPGA provides up to 24 address lines during configu-
< 90 ns 6
ration, addressing up to 128 Mbits (16 Mbytes). If using a
larger parallel PROM, connect the upper address lines to
Using the BPI Interface after Configuration FPGA user I/O. During configuration, the upper address
After the FPGA successfully completes configuration, all of lines will be pulled High if HSWAP = 0. Otherwise, use
the pins connected to the parallel Flash PROM are available external pull-up or pull-down resistors on these address
as user I/Os. lines to define their values during configuration.
If not using the parallel Flash PROM after configuration, Precautions Using x8/x16 Flash PROMs
drive LDC0 High to disable the PROM’s chip-select input.
D Most low- to mid-density PROMs are byte-wide (x8)
The remainder of the BPI pins then become available to the
FPGA application, including all 24 address lines, the eight only. Many higher-density Flash PROMs support both
data lines, and the LDC2, LDC1, and HDC control pins. byte-wide (x8) and halfword-wide (x16) data paths and
include a mode input called BYTE# that switches between
Because all the interface pins are user I/Os after configura- x8 or x16. During configuration, Spartan-3E FPGAs only
tion, the FPGA application can continue to use the interface support byte-wide data. However, after configuration, the
pins to communicate with the parallel Flash PROM. Parallel FPGA supports either x8 or x16 modes. In x16 mode, up to
Flash PROMs are available in densities ranging from 1 Mbit eight additional user I/O pins are required for the upper data
up to 128 Mbits and beyond. However, a single Spartan-3E bits, D[15:8].
FPGA requires less than 6 Mbits for configuration. If
desired, use a larger parallel Flash PROM to contain addi- Connecting a Spartan-3E FPGA to a x8/x16 Flash PROM is
tional non-volatile application data, such as MicroBlaze pro- simple, but does require a precaution. Various Flash PROM
cessor code, or other user data such as serial numbers, vendors use slightly different interfaces to support both x8
Ethernet MAC IDs, etc. In such an example, the FPGA con- and x16 modes. Some vendors (Intel, Micron, some STMi-
figures from parallel Flash PROM. Then using FPGA logic croelectronics devices) use a straightforward interface with
after configuration, a MicroBlaze processor embedded pin naming that matches the FPGA connections. However,
within the FPGA can either execute code directly from par- the PROM’s A0 pin is wasted in x16 applications and a sep-
allel Flash PROM or copy the code to external DDR arate FPGA user-I/O pin is required for the D15 data line.
SDRAM and execute from DDR SDRAM. Similarly, the Fortunately, the FPGA A0 pin is still available as a user I/O
FPGA application can store non-volatile application data after configuration, even though it connects to the Flash
within the parallel Flash PROM. PROM.
The FPGA configuration data is stored starting at either at Other vendors (AMD, Atmel, Silicon Storage Technology,
location 0 or the top of memory (addresses all ones) or at some STMicroelectronics devices) use a pin-efficient inter-
both locations for MultiBoot mode. Store any additional data face but change the function of one pin, called IO15/A-1,
beginning in other available parallel Flash PROM sectors. depending if the PROM is in x8 or x16 mode. In x8 mode,
Do not mix configuration data and user data in the same BYTE# = 0, this pin is the least-significant address line. The
sector. A0 address line selects the halfword location. The A-1
address line selects the byte location. When in x16 mode,
Similarly, the parallel Flash PROM interface can be BYTE# = 1, the IO15/A-1 pin becomes the most-significant
expanded to additional parallel peripherals. data bit, D15 because byte addressing is not required in this
The address, data, and LDC1 (OE#) and HDC (WE#) con- mode. Check to see if the Flash PROM has a pin named
trol signals are common to all parallel peripherals. Connect “IO15/A-1" or "DQ15/A-1". If so, be careful to connect
the chip-select input on each additional peripheral to one of x8/x16 Flash PROMs correctly, as shown in Table 54. Also,
the FPGA user I/O pins. If HSWAP = 0 during configuration, remember that the D[14:8] data connections require FPGA
the FPGA holds the chip-select line High via an internal user I/O pins but that the D15 data is already connected for
pull-up resistor. If HSWAP = 1, connect the select line to the FPGA’s A0 pin.
+3.3V via an external 4.7 kΩ pull-up resistor to avoid spuri-

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Table 54: FPGA Connections to Flash PROM with "IO15/A-1" Pin

Connection to Flash PROM with x8 Flash PROM Interface After x16 Flash PROM Interface After
FPGA Pin IO15/A-1 Pin FPGA Configuration FPGA Configuration
LDC2 BYTE# Drive LDC2 Low or leave Drive LCD2 High
unconnected and tie PROM
BYTE# input to GND
LDC1 OE# Active-Low Flash PROM Active-Low Flash PROM
output-enable control output-enable control
LDC0 CS# Active-Low Flash PROM Active-Low Flash PROM
chip-select control chip-select control
HDC WE# Flash PROM write-enable Flash PROM write-enable control
control
A[23:1] A[n:0] A[n:0] A[n:0]
A0 IO15/A-1 IO15/A-1 is least-significant IO15/A-1 is most-significant data
address input line, IO15
D[7:0] IO[7:0] IO[7:0] IO[7:0]
User I/O Upper data lines IO[14:8] not Upper data lines IO[14:8] not IO[14:8]
required unless used as x16 Flash required
interface after configuration
Daisy-Chaining next FPGA in the daisy-chain. The next FPGA then receives
parallel configuration data from the Flash PROM. The mas-
If the application requires multiple FPGAs with different con-
ter FPGA’s CCLK output synchronizes data capture.
figurations, then configure the FPGAs using a daisy chain,
as shown in Figure 56. Use BPI mode (M[2:0] = <0:1:0> or The downstream devices in Slave Parallel mode also
<0:1:1>) for the FPGA connected to the parallel NOR Flash actively drive their LDC[2:0] and HDC outputs during config-
PROM and Slave Parallel mode (M[2:0] = <1:1:0>) for all uration, although these signal are not used for configura-
other FPGAs in the daisy-chain. After the master tion. These pins are in I/O Bank 1, powered by VCCO_1.
FPGA—the FPGA on the left in the diagram—finishes load- Because these pins do not connect elsewhere in the config-
ing its configuration data from the parallel Flash PROM, the uration circuit, the voltage on VCCO_1 can be whatever is
master device continues generating addresses to the Flash required by the end application.
PROM and asserts its CSO_B output Low, enabling the

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CCLK
D[7:0]
+1.2V +1.2V
V
VCCINT VCCINT
I
VCCO_1 V VCC VCCO_1 VCCO_1
LDC0 CE# x8 or LDC0
LDC1 OE# x8/x16 LDC1
HDC WE#
Flash HDC
PROM
Not available LDC2 BYTE# LDC2
in VQ100 A[16:0] D
package Slave
DQ[15:7]
Parallel
BPI Mode VCCO_2 V Mode VCCO_2 V
‘0’ M2 D[7:0] DQ[7:0] ‘1’ M2 D[7:0]
‘1’ M1 A[23:17] A[n:0] ‘1’ M1
A M0 GND ‘0’ M0
Spartan-3E BUSY Spartan-3E BUSY
FPGA CCLK CCLK FPGA
‘0’ CSI_B CSO_B CSI_B CSO_B CSO_B
‘0’ RDWR_B INIT_B ‘0’ RDWR_B INIT_B
2.5V
JTAG VCCAUX +2.5V VCCAUX +2.5V
TDI TDI TDO TDI TDO
TMS TMS TMS
TCK TCK V TCK
+2.5V
TDO
GND GND
4.7k
4.7k
330
PROG_B PROG_B
Recommend
open-drain TCK
driver TMS
DONE
INIT_B
DS312-2_50_021405
Figure 56: Daisy-Chaining from BPI Flash Mode
In-System Programming Support Dynamically Loading Multiple Configuration

I In a production application, the parallel Flash PROM is Images Using MultiBoot Option
usually preprogrammed before it is mounted on the printed After the FPGA configures itself using BPI mode from one
circuit board. In-system programming support is available end of the parallel Flash PROM, then the FPGA can trigger
from third-party boundary-scan tool vendors and from some a MultiBoot event and reconfigure itself from the opposite
third-party PROM programmers using a socket adapter with end of the parallel Flash PROM. MultiBoot is only available
attached wires. To gain access to the parallel Flash signals, when using BPI mode and only for applications with a single
drive the FPGA’s PROG_B input Low with an open-drain Spartan-3E FPGA.
driver. This action places all FPGA I/O pins, including those
By default, MultiBoot mode is disabled. To trigger a Multi-
attached to the parallel Flash, in high-impedance (Hi-Z). If
Boot event, assert a Low pulse lasting at least 300 ns on the
the HSWAP input is High, the I/Os have pull-up resistors to
MultiBoot Trigger (MBT) input to the STARTUP_SPARTAN3E
the VCCO input on their respective I/O bank. The external
library primitive. Figure 57 shows an example usage. At
programming hardware then has direct access to the paral-
power up, the FPGA loads itself from the attached parallel
lel Flash pins. The programming access points are high-
Flash PROM. In this example, the M0 mode pin is Low so
lighted in the gray boxes in Figure 55 and Figure 56.
the FPGA starts at address 0 and increments through the
The FPGA itself can also be used as a parallel Flash PROM Flash PROM memory locations. After the FPGA completes
programmer during development and test phases. Initially, configuration, the application loaded into the FPGA per-
an FPGA-based programmer is downloaded into the FPGA forms a board-level or system test using FPGA logic. If the
via JTAG. Then the FPGA performs the Flash PROM pro- test is successful, the FPGA triggers a MultiBoot event,
gramming algorithms and receives programming data from causing the FPGA to reconfigure from the opposite end of
the host via the FPGA’s JTAG interface. See Chapter 11 in the Flash PROM memory. This second configuration con-
"Embedded System Tools Reference Manual". tains the FPGA application for normal operation.

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Parallel Flash PROM Parallel Flash PROM

FFFFFF FFFFFF
General General
FPGA FPGA
Application STARTUP_SPARTAN3E Application
GSR
User Area GTS User Area
MBT
> 300 ns CLK
Diagnostics Diagnostics
FPGA Reconfigure FPGA
Application Application
0 0
First Configuration Second Configuration
DS312-2_51_021405
Figure 57: Use MultiBoot to Load Alternate Configuration Images
Similarly, the general FPGA application could trigger a ever, the FPGA does not assert the PROG_B pin. The sys-
MultiBoot event at any time to reload the diagnostics design. tem design must ensure that no other device drives on
In another potential application, the initial design loaded into these same pins during the reconfiguration process. The
the FPGA image contains a “golden” or “fail-safe” configura- FPGA’s DONE, LDC[2:0], or HDC pins can temporarily dis-
tion image, which then communicates with the outside world able any conflicting drivers during reconfiguration.
and checks for a newer image. If there is a new configura-
tion revision and the new image verifies as good, the Slave Parallel Mode
“golden” configuration triggers a MultiBoot event to load the In Slave Parallel mode (M[2:0] = <1:1:0>), an external host
new image. such as a microprocessor or microcontroller writes
When a MultiBoot event is triggered, the FPGA then again byte-wide configuration data into the FPGA, using a typical
drives its configuration pins as described in Table 51. How- peripheral interface as shown in Figure 58.

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+1.2V
VCCINT
VCCO_1 VCCO_1
LDC0
LDC1
HDC
Slave LDC2
Parallel
Mode VCCO_2 V
V ‘1’ M2
Intelligent
‘1’ M1
Download Host V
‘0’ M0
VCC
Spartan-3E
D[7:0] D[7:0]
4.7k
Configuration FPGA
Memory BUSY BUSY
Source SELECT CSI_B CSO_B
READ/WRITE RDWR_B INIT_B
• Internal memory CLOCK CCLK
• Disk drive
• Over network PROG_B
• Over RF link DONE VCCAUX +2.5V
INIT_B TDI TDO
GND TMS
TCK
+2.5V
• Microcontroller
• Processor PROG_B DONE
• Tester
4.7kΩ
330Ω
GND
• Computer
PROG_B
Recommend
open-drain +2.5V
driver JTAG
TDI
TMS
TCK
TDO DS312-2_52_022205
Figure 58: Slave Parallel Configuration Mode
The external download host starts the configuration process is 50 MHz or below, the BUSY pin may be ignored but
by pulsing PROG_B and monitoring that the INIT_B pin actively drives during configuration.
goes High, indicating that the FPGA is ready to receive its The configuration process requires more clock cycles than
first data. The host asserts the active-Low chip-select signal indicated from the configuration file size. Additional clocks
(CSI_B) and the active-Low Write signal (RDWR_B). The are required during the FPGA’s start-up sequence, espe-
host then continues supplying data and clock signals until cially if the FPGA is programmed to wait for selected Digital
either the FPGA’s DONE pin goes High, indicating a suc- Clock Managers (DCMs) to lock to their respective clock
cessful configuration, or until the FPGA’s INIT_B pin goes inputs (see Start-Up, page 91).
Low, indicating a configuration error.
If the Slave Parallel interface is only used to configure the
The FPGA captures data on the rising CCLK edge. If the FPGA, never to read data back, then the RDWR_B signal
CCLK frequency exceeds 50 MHz, then the host must also can also be eliminated from the interface. However,
monitor the FPGA’s BUSY output. If the FPGA asserts RDWR_B must remain Low during configuration.
BUSY High, the host must hold the data for an additional
clock cycle, until BUSY returns Low. If the CCLK frequency

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After configuration, all of the interface pins except DONE The Slave Parallel mode is also used with BPI mode to cre-
and PROG_B are available as user I/Os. Alternatively, the ate multi-FPGA daisy-chains. The lead FPGA is set for BPI
bidirectional SelectMAP configuration interface is available mode configuration; all the downstream daisy-chain FPGAs
after configuration. To continue using SelectMAP mode, set are set for Slave Parallel configuration, as highlighted in
the Persist bitstream generator option to Yes. The external Figure 56.
host can then read and verify configuration data.
Table 55: Slave Parallel Mode Connections

1: No pull-ups
M[2:0] Input Mode Select. Selects the FPGA M2 = 1, M1 = 1, M0 = 0 Sampled User I/O
configuration mode. when INIT_B goes High.
D[7:0] Input Data Input. Byte-wide data provided by host. User I/O. If bitstream
FPGA captures data on rising option Persist=Yes,
CCLK edge. becomes part of
SelectMap parallel
BUSY Output Busy Indicator. If CCLK frequency is < 50 MHz, User I/O. If bitstream
this pin may be ignored. When option Persist=Yes,
High, indicates that the FPGA is becomes part of
not ready to receive additional SelectMap parallel
configuration data. Host must peripheral interface.
hold data an additional clock
cycle.
CSI_B Input Chip Select Input. Active Low. Must be Low throughout User I/O. If bitstream
configuration. option Persist=Yes,
becomes part of
SelectMap parallel
RDWR_B Input Read/Write Control. Active Low Must be Low throughout User I/O. If bitstream
write enable. configuration. option Persist=Yes,
becomes part of
SelectMap parallel
CCLK Input Configuration Clock. If CCLK External clock. User I/O If bitstream
PCB trace is long or has multiple option Persist=Yes,
connections, terminate this output becomes part of
to maintain signal integrity. SelectMap parallel
LDC[2:0] Output Low During Configuration. These pins are not used during User I/O
configuration. Low throughout
configuration.
HDC Output High During Configuration. This pin is not used during User I/O
configuration. High throughout
configuration.

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Table 55: Slave Parallel Mode Connections (Continued)

CSO_B Output Chip Select Output. Active Low. Not used in single FPGA User I/O
applications. In a daisy-chain
configuration, this pin connects
to the CSI_B pin of the next
FPGA in the chain. Actively
drives.
INIT_B Open-drain Initialization Indicator. Active Low. Active during configuration. If User I/O
bidirectional I/O Goes Low at start of configuration CRC error detected during
during Initialization memory configuration, FPGA drives
clearing process. Released at end INIT_B Low.
of memory clearing, when mode
select pins are sampled. In
daisy-chain applications, this signal
requires an external 4.7 kΩ pull-up
resistor to VCCO_2.
2.5V.
PROG_B Input Program FPGA. Active Low. When Must be High to allow Drive PROG_B Low and
asserted Low for 300 ns or longer, configuration to start. release to reprogram
forces the FPGA to restart its FPGA.
configuration process by clearing
configuration memory and resetting
the DONE and INIT_B pins once
PROG_B returns High. Requires
external 4.7 kΩ pull-up resistor to
2.5V. If driving externally, use an
open-drain or open-collector driver.
Voltage Compatibility Daisy-Chaining

V Most Slave Parallel interface signals are within the If the application requires multiple FPGAs with different con-
FPGA’s I/O Bank 2, supplied by the VCCO_2 supply input. figurations, then configure the FPGAs using a daisy chain.
The VCCO_2 voltage can be 1.8V, 2.5V, or 3.3V to match Use Slave Parallel mode (M[2:0] = <1:1:0>) for all FPGAs in
the requirements of the external host, ideally 2.5V. Using the daisy-chain. The schematic in Figure 59 is optimized for
1.8V or 3.3V requires additional design considerations as FPGA downloading and does not support the SelectMAP
the DONE and PROG_B pins are powered by the FPGA’s read interface. The FPGA’s RDWR_B pin must be Low dur-
2.5V VCCAUX supply. See application note XAPP453: "The ing configuration.
3.3V Configuration of Spartan-3 FPGAs" for additional infor- After the lead FPGA is filled with its configuration data, the
mation. lead FPGA enables the next FPGA in the daisy-chain by
The LDC[2:0] and HDC signal are active in I/O Bank 1 but asserting is chip-select output, CSO_B.
are not used in the interface. Consequently, VCCO_1 can
be set the appropriate voltage for the application.

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D[7:0]
CCLK
+1.2V +1.2V
VCCINT VCCINT
VCCO_1 VCCO_1 VCCO_1 VCCO_1
LDC0 LDC0
LDC1 LDC1
HDC HDC
Slave LDC2 Slave LDC2
Parallel Parallel
Mode VCCO_2 V Mode VCCO_2 V
V ‘1’ M2 ‘1’ M2
Intelligent
‘1’ M1 ‘1’ M1
Download Host V
‘0’ M0 ‘0’ M0
VCC
Spartan-3E Spartan-3E
4.7kΩ
DATA[7:0] D[7:0] D[7:0]
Configuration FPGA FPGA
Memory BUSY BUSY BUSY
Source SELECT CSI_B CSO_B CSI_B CSO_B CSO_B
READ/WRITE ‘0’ RDWR_B INIT_B ‘0’ RDWR_B INIT_B
• Internal memory CLOCK CCLK CCLK
• Disk drive
• Over network PROG_B
• Over RF link DONE VCCAUX +2.5V VCCAUX +2.5V
INIT_B TDI TDO TDI TDO
GND TMS TMS
TCK TCK
+2.5V
• Microcontroller PROG_B DONE PROG_B DONE
• Processor
• Tester
4.7kΩ
330Ω
GND GND
PROG_B PROG_B
Recommend
open-drain 2.5V DONE
driver JTAG INIT_B
TDI
TMS TMS
TCK TCK
TDO
DS312-2_53_022305
Figure 59: Daisy-Chaining using Slave Parallel Mode
Slave Serial Mode indicating that the FPGA is ready to receive its first data.
The host then continues supplying data and clock signals
In Slave Serial mode (M[2:0] = <1:1:1>), an external host
until either the DONE pin goes High, indicating a successful
such as a microprocessor or microcontroller writes serial
configuration, or until the INIT_B pin goes Low, indicating a
configuration data into the FPGA, using the synchronous
configuration error. The configuration process requires
serial interface shown in Figure 60. The serial configuration
more clock cycles than indicated from the configuration file
data is presented on the FPGA’s DIN input pin with suffi-
size. Additional clocks are required during the FPGA’s
cient setup time before each rising edge of the externally
start-up sequence, especially if the FPGA is programmed to
generated CCLK clock input.
wait for selected Digital Clock Managers (DCMs) to lock to
The intelligent host starts the configuration process by puls- their respective clock inputs (see Start-Up, page 91).
ing PROG_B and monitoring that the INIT_B pin goes High,

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+1.2V
VCCINT
Slave
VCCO_2 V
Serial V
Mode
‘1’ M2
Intelligent V ‘1’ M1
Download Host
4.7kΩ
‘1’ M0
VCC Spartan-3E
Configuration
Memory CLOCK CCLK FPGA
Source SERIAL_OUT DIN DOUT
PROG_B INIT_B
• Internal memory DONE
• Disk drive VCCAUX +2.5V
INIT_B
• Over network TDI TDO
• Over RF link GND TMS
TCK
+2.5V
• Microcontroller
• Processor PROG_B DONE
• Tester
4.7kΩ
330Ω
• Computer GND
PROG_B
Recommend
open-drain
driver
+2.5V
JTAG
TDI
TMS
TCK
TDO DS312-2_54_022305
Figure 60: Slave Serial Configuration
The mode select pins, M[2:0], are sampled when the P Similarly, the FPGA’s HSWAP pin must be Low to
FPGA’s INIT_B output goes High and must be at defined enable pull-up resistors on all user-I/O pins or High to dis-
logic levels during this time. After configuration, when the able the pull-up resistors. The HSWAP control must remain
FPGA’s DONE output goes High, the mode pins are avail- at a constant logic level throughout FPGA configuration.
able as full-featured user-I/O pins. After configuration, when the FPGA’s DONE output goes
High, the HSWAP pin is available as full-featured user-I/O
pin and is powered by the VCCO_0 supply.

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Table 56: Slave Serial Mode Connections

0: Pull-up during configuration
1: No pull-ups
M[2:0] Input Mode Select. Selects the FPGA M2 = 1, M1 = 1, M0 = 1 Sampled User I/O
configuration mode. when INIT_B goes High.
DIN Input Data Input. Serial data provided by host. User I/O
FPGA captures data on rising
CCLK edge.
CCLK Input Configuration Clock. If CCLK External clock. User I/O
PCB trace is long or has multiple
connections, terminate this output
to maintain signal integrity.
bidirectional I/O Low. Goes Low at start of CRC error detected during
configuration during Initialization configuration, FPGA drives
memory clearing process. INIT_B Low.
Released at end of memory
clearing, when mode select pins
are sampled. In daisy-chain
to VCCO_2.
completes configuration. successfully configured.
Requires external 330 Ω pull-up
resistor to 2.5V.
longer, forces the FPGA to restart FPGA.
its configuration process by
clearing configuration memory
and resetting the DONE and
INIT_B pins once PROG_B
returns High. Requires external
4.7 kΩ pull-up resistor to 2.5V. If
driving externally, use an
open-drain or open-collector
driver.
Voltage Compatibility Daisy-Chaining

V Most Slave Serial interface signals are within the If the application requires multiple FPGAs with different con-
FPGA’s I/O Bank 2, supplied by the VCCO_2 supply input. figurations, then configure the FPGAs using a daisy chain,
The VCCO_2 voltage can be 3.3V, 2.5V, or 1.8V to match as shown in Figure 61. Use Slave Serial mode
the requirements of the external host, ideally 2.5V. Using (M[2:0] = <1:1:1>) for all FPGAs in the daisy-chain. After
3.3V or 1.8V requires additional design considerations as the lead FPGA is filled with its configuration data, the lead
the DONE and PROG_B pins are powered by the FPGA’s FPGA passes configuration data via its DOUT output pin to
2.5V VCCAUX supply. See application note XAPP453: "The the next FPGA on the falling CCLK edge.
3.3V Configuration of Spartan-3 FPGAs" for additional infor-
mation.

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CCLK
+1.2V +1.2V
VCCINT VCCINT
Slave
VCCO_2 V Slave
VCCO_2 VCCO_2
Serial V Serial
Mode Mode
‘1’ M2 ‘1’ M2
Intelligent V ‘1’ M1 ‘1’ M1
Download Host
4.7k
‘1’ M0 ‘1’ M0
VCC Spartan-3E Spartan-3E

Configuration
Memory CLOCK CCLK FPGA CCLK FPGA
Source SERIAL_OUT DIN DOUT DIN DOUT DOUT
PROG_B INIT_B INIT_B
• Internal memory DONE
• Disk drive VCCAUX +2.5V VCCAUX +2.5V
• Over network INIT_B TDI TDO TDI TDO
• Over RF link GND TMS TMS
TCK TCK
+2.5V
• Microcontroller
• Processor PROG_B DONE PROG_B DONE
• Tester
• Computer GND GND
4.7k
330
PROG_B PROG_B
Recommend DONE
open-drain
driver INIT_B
+2.5V
JTAG
TDI
TMS TMS
TCK TCK
TDO
DS312-2_55_022305
Figure 61: Daisy-Chaining using Slave Serial Mode
JTAG Mode other configuration modes. No other pins are required as

part of the configuration interface.
The Spartan-3E FPGA has a dedicated four-wire IEEE
1149.1/1532 JTAG port that is always available any time the Figure 62 illustrates a JTAG-only configuration interface.
FPGA is powered and regardless of the mode pin settings. The JTAG interface is easily cascaded to any number of
However, when the FPGA mode pins are set for JTAG mode FPGAs by connecting the TDO output of one device to the
(M[2:0] = <1:0:1>), the FPGA waits to be configured via the TDI input of the next device in the chain. The TDO output of
JTAG port after a power-on event or when PROG_B is the last device in the chain loops back to the port connector.
asserted. Selecting the JTAG mode simply disables the

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+1.2V +1.2V
VCCINT VCCINT
VCCO_2 VCCO_2 VCCO_2 VCCO_2
JTAG JTAG
Mode Mode
‘1’ M2 ‘1’ M2
Spartan-3E Spartan-3E
‘0’ M1 ‘0’ M1
FPGA FPGA
‘1’ M0 ‘1’ M0
VCCAUX +2.5V VCCAUX +2.5V
TDI TDO TDI TDO
TMS TMS
TCK TCK

GND GND
+2.5V
JTAG
TDI
TMS TMS
TCK TCK
TDO
DS312-2_56_021405
Figure 62: JTAG Configuration Mode
Voltage Compatibility or after the PROG_B input is asserted. Power-On Reset

(POR) occurs after the VCCINT, VCCAUX, and the VCCO Bank
The 2.5V VCCAUX supply powers the JTAG interface. All of
2 supplies reach their respective input threshold levels.
the user I/Os are separately powered by their respective
After either a POR or PROG_B event, the three-stage con-
VCCO_# supplies.
figuration process begins.
When connecting the Spartan-3E JTAG port to a 3.3V inter-
1. The FPGA clears (initializes) the internal configuration
face, the JTAG input pins must be current-limited to 10 mA
memory.
or less using series resistors. Similarly, the TDO pin is a
CMOS output powered from +2.5V. The TDO output can 2. Configuration data is loaded into the internal memory.
directly drive a 3.3V input but with reduced noise immunity. 3. The user-application is activated by a start-up process.
See application note XAPP453: "The 3.3V Configuration of
Figure 63 is a generalized block diagram of the Spartan-3E
Spartan-3 FPGAs" for additional information.
configuration logic, showing the interaction of different
Maximum Bitstream Size for Daisy-Chains device inputs and Bitstream Generator (BitGen) options. A
flow diagram for the configuration sequence of the Serial
The maximum bitstream length supported by Spartan-3E and Parallel modes appears in Figure 64. Figure 65 shows
FPGAs in serial daisy-chains is 4,294,967,264 bits (4 the Boundary-Scan or JTAG configuration sequence.
Gbits), roughly equivalent to a daisy-chain with 720
XC3S1600E FPGAs. This is a limit only for serial Initialization
daisy-chains where configuration data is passed via the Configuration automatically begins after power-on or after
FPGA’s DOUT pin. There is no such limit for JTAG chains. asserting the FPGA PROG_B pin, unless delayed using the
FPGA’s INIT_B pin. The FPGA holds the open-drain INIT_B
Configuration Sequence signal Low while it clears its internal configuration memory.
The Spartan-3E configuration process is three-stage pro- Externally holding the INIT_B pin Low forces the configura-
cess that begins after the FPGA powers on (a POR event) tion sequencer to wait until INIT_B again goes High.

88
DriveDone
LOCKED
DCM in User
STARTUP
Option = Bitstream Generator (BitGen) Option EN
Application
DCMs_LOCKED DONE DONE
Option = Design Attribute
STARTUP_WAIT=TRUE All DCMs LCK_cycle
DONE_cycle
Enable application logic and
I/O pins
INITIALIZATION CONFIGURATION
Power On Reset (POR) ENABLE DONE ENABLE DONE ENABLE GTS Force all I/Os Hi-Z
GTS_cycle
Clear internal CMOS Load application
VCCO_2 configuration latches USER * GTS_IN Hold all storage
data into CMOS GSR elements reset
V CCO2T configuration latches USER * GSR_IN
CLEARING_MEMORY
Disable write
GWE operations to
VCCINT POWER_GOOD RESET WAIT RESET RESET WAIT GWE_cycle storage elements
VCCINTT
DonePipe
VCCAUX
V CCAUXT EN
INIT_B
www.xilinx.com
PROG_B Glitch Filter
USER_CLOCK *
JTAG_CLOCK These connections are available via the
* STARTUP_SPARTAN3E library primitive.
CCLK 1
StartupClk
1
TCK 0 INTERNAL_CONFIGURATION_CLOCK
ConfigRate
0
Internal CRC ENABLE ERROR

M1 Oscillator
Configuration Error
Detection
M2 (CRC Checker)
Figure 63: Generalized Spartan-3E FPGA Configuration Logic Block Diagram

DS312-2_57_022405
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DS312-2 (v1.1) March 21, 2005
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Set PROG_B Low

Power-On
after Power-On
VCCINT >1V
and VCCAUX > 2V No
and VCCO Bank 4 > 1V
Yes
Clear configuration Yes

PROG_B = Low
memory
No
No
INIT_ B = High?
Yes
M[2:0] and VS[2:0]

Sample mode pins pins are sampled on
INIT_B rising edge
Load configuration
data frames
CRC No INIT_B goes Low.

correct? Abort Start-Up
Yes
DONE pin goes High,

Start-Up
sequence signaling end of
configuration
User mode
No Yes
Reconfigure?
DS312-2_58_021404
Figure 64: General Configuration Process

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Set PROG_B Low

Power-On after Power-On
VCCINT >1V
and VCCAUX > 2V No
and VCCO Bank 4 > 1V
Load Yes
JPROG
instruction
Clear Yes
configuration PROG_B = Low
memory
No
No
INIT_B = High?
Yes
Sample
mode pins
(JTAG port becomes
available)
Load CFG_IN
instruction
Load configuration
data frames
CRC No INIT_B goes Low.

correct? Abort Start-Up
Yes
Synchronous
TAP reset
(Clock five 1's
on TMS)
Load JSTART
instruction
Start-Up
sequence
User mode
Yes No
Reconfigure?
DS312-2_59_022505
Figure 65: Boundary-Scan Configuration Flow Diagram

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The FPGA signals when the memory-clearing phase is Start-Up

complete by releasing the open-drain INIT_B pin, allowing
At the end of configuration, the Global Set/Reset (GSR) sig-
the pin to go High via the external pull-up resistor to
nal is pulsed, placing all flip-flops in a known state. After
VCCO_2.
configuration completes, the FPGA switches over to the
Loading Configuration Data user application loaded into the FPGA. The sequence and
timing of how the FPGA switches over is programmable as
Configuration data is then written to the FPGA’s internal
is the clock source controlling the sequence.
memory. The FPGA holds the Global Set/Reset (GSR) sig-
nal active throughout configuration, holding all FPGA The default start-up sequence appears in Figure 66, where
flip-flops in a reset state. The FPGA signals when the entire the Global Three-State signal (GTS) is released one clock
configuration process completes be releasing the DONE cycle after DONE goes High. This sequence allows the
pin, allowing it to go High. DONE signal to enable or disable any external logic used
during configuration before the user application in the FPGA
The FPGA configuration sequence can also be initiated by
starts driving output signals. One clock cycle later, the Glo-
asserting the PROG_B. Once release, the FPGA begins
bal Write Enable (GWE) signal is released. This allows sig-
clearing its internal configuration memory, and progresses
nals to propagate within the FPGA before any clocked
through the remainder of the configuration process.
storage elements such as flip-flops and block ROM are
enabled.
Default Cycles
Start-Up Clock
Phase 0 1 2 3 4 5 6 7
DONE
GTS
GWE
Sync-to-DONE
Start-Up Clock
Phase 0 1 2 3 4 5 6 7
DONE High
DONE
GTS
GWE
DS312-2_60_022305
Figure 66: Default Start-Up Sequence

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The relative timing of configuration events is programmed Along with the configuration data, it is possible to read back
via the Bitstream Generator (BitGen) options in the Xilinx the contents of all registers, distributed RAM, and block
development software. For example, the GTS and GWE RAM resources. This capability is used for real-time debug-
events can be programmed to wait for all the DONE pins to ging.
High on all the devices in a multiple-FPGA daisy-chain, forc- To synchronously control when registers values are cap-
ing the FPGAs to start synchronously. Similarly, the start-up tured for readback, using the CAPTURE_SPARTAN3 library
sequence can be paused at any stage, waiting for selected primitive, which applies for both Spartan-3 and Spartan-3E
DCMs to lock to their respective input clock signals. See FPGA families.
also Stabilizing DCM Clocks Before User Mode, page 48.
The start-up sequence can by synchronized to a clock Bitstream Generator (BitGen) Options
within the FPGA application using the Various Spartan-3E FPGA functions are controlled by spe-
STARTUP_SPARTAN3E library primitive and by setting the cific bits in the configuration bitstream image. These values
StartupClk bitstream generator option. The FPGA applica- are specified when creating the bitstream image with the
tion can optionally assert the Global Set/Reset (GSR) and Bitstream Generator (BitGen) software.
Global Three-State signal (GTS) signals via the
STARTUP_SPARTAN3E primitive. Table 57 provides a list of all BitGen options for Spartan-3E
FPGAs.
Readback
Using Slave Parallel mode, configuration data from the
FPGA can be read back. Readback is supported only in the
Slave Parallel and JTAG modes.
Table 57: Spartan-3E FPGA Bitstream Generator (BitGen) Options

Pins/Function Values
Option Name Description
Affected (default)
ConfigRate CCLK, 3, 6, Sets the approximate frequency, in MHz, of the internal oscillator using for Master
Configuration 12, 25 Serial, SPI, and BPI configuration modes. The internal oscillator powers up at its lowest
frequency and the new setting is loaded as part of the configuration bitstream. The
software default value is 6 (~6 MHz).
StartupClk Configuration, Cclk Default. The CCLK signal (internally or externally generated) controls the startup
Startup sequence when the FPGA transitions from configuration mode to the user mode. See
Start-Up, page 91.
UserClk A clock signal from within the FPGA application controls the startup sequence when
the FPGA transitions from configuration mode to the user mode. See Start-Up,
page 91. The FPGA application supplies the user clock on the CLK pin on the
STARTUP_SPARTAN3E primitive.
Jtag The JTAG TCK input controls the startup sequence when the FPGA transitions from
configuration mode to the user mode. See Start-Up, page 91.
UnusedPin Unused I/O Pulldown Default. All unused I/O pins have a pull-down resistor to GND.
Pins
Pullup All unused I/O pins have a pull-up resistor to the VCCO_# supply for its associated I/O
bank.
Pullnone All unused I/O pins are left floating (Hi-Z, high-impedance, three-state). Use external
pull-up or pull-down resistors or logic to apply a valid signal level.
DONE_cycle DONE pin, 1, 2, 3, 4, Selects the Configuration Startup phase that activates the FPGA’s DONE pin. See
Configuration 5, 6 Start-Up, page 91.
Startup

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Table 57: Spartan-3E FPGA Bitstream Generator (BitGen) Options (Continued)

Affected (default)
GWE_cycle All flip-flops, 1, 2, 3, 4, Selects the Configuration Startup phase that asserts the internal write-enable signal to
LUT RAMs, 5, 6 all flip-flops, LUT RAMs and shift registers (SRL16). It also enables block RAM read
and SRL16 and write operations. See Start-Up, page 91.
shift registers,
Block RAM, Done Waits for the DONE pin input to go High before asserting the internal write-enable
Configuration signal to all flip-flops, LUT RAMs and shift registers (SRL16). Block RAM read and
Startup write operations are enabled at this time.
Keep Retains the current GWE_cycle setting for partial reconfiguration applications.
GTS_cycle All I/O pins, 1, 2, 3, 4, Selects the Configuration Startup phase that releases the internal three-state control,
Configuration 5, 6 holding all I/O buffers in high-impedance (Hi-Z). Output buffers actively drive, if so
configured, after this point. See Start-Up, page 91.
Done Waits for the DONE pin input to go High before releasing the internal three-state
control, holding all I/O buffers in high-impedance (Hi-Z). Output buffers actively drive,
if so configured, after this point.
Keep Retains the current GTS_cycle setting for partial reconfiguration applications.
LCK_cycle DCMs, NoWait The FPGA does not wait for selected DCMs to lock before completing configuration.
Configuration
Startup 0, 1, 2, 3, If one or more DCMs in the design have the STARTUP_WAIT attribute set to TRUE,
4, 5, 6 the FPGA waits for such DCMs to acquire their respective input clock and assert their
LOCKED output. This setting selects the Configuration Startup phase where the FPGA
waits for the DCMs to lock.
DonePin DONE pin Pullup Internally connects a pull-up resistor between DONE pin and VCCAUX. An external
330 Ω pull-up resistor to VCCAUX is still recommended.
Pullnone No internal pull-up resistor on DONE pin. An external 330 Ω pull-up resistor to
VCCAUX is required.
DriveDone DONE pin No When configuration completes, the DONE pin stops driving Low and relies on an
external 330 Ω pull-up resistor to VCCAUX for a valid logic High.
Yes When configuration completes, the DONE pin actively drives High. When using this
option, an external pull-up resistor is no longer required. Only one device in an FPGA
daisy-chain should use this setting.
DonePipe DONE pin No The input path from DONE pin input back to the Startup sequencer is not pipelined.
Yes This option adds a pipeline register stage between the DONE pin input and the Startup
sequencer. Used for high-speed daisy-chain configurations when DONE cannot rise in
a single CCLK cycle. Releases GWE and GTS signals on the first rising edge of
StartupClk after the DONE pin input goes High.
ProgPin PROG_B pin Pullup Internally connects a pull-up resistor or between PROG_B pin and VCCAUX. An
external 4.7 kΩ pull-up resistor to VCCAUX is still recommended.
Pullnone No internal pull-up resistor on PROG_B pin. An external 4.7 kΩ pull-up resistor to
VCCAUX is required.
TckPin JTAG TCK pin Pullup Internally connects a pull-up resistor between JTAG TCK pin and VCCAUX.
Pulldown Internally connects a pull-down resistor between JTAG TCK pin and GND.
Pullnone No internal pull-up resistor on JTAG TCK pin.
TdiPin JTAG TDI pin Pullup Internally connects a pull-up resistor between JTAG TDI pin and VCCAUX.
Pulldown Internally connects a pull-down resistor between JTAG TDI pin and GND.
Pullnone No internal pull-up resistor on JTAG TDI pin.

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Table 57: Spartan-3E FPGA Bitstream Generator (BitGen) Options (Continued)

Affected (default)
TdoPin JTAG TDO pin Pullup Internally connects a pull-up resistor between JTAG TDO pin and VCCAUX.
Pulldown Internally connects a pull-down resistor between JTAG TDO pin and GND.
Pullnone No internal pull-up resistor on JTAG TDO pin.
TmsPin JTAG TMS pin Pullup Internally connects a pull-up resistor between JTAG TMS pin and VCCAUX.
Pulldown Internally connects a pull-down resistor between JTAG TMS pin and GND.
Pullnone No internal pull-up resistor on JTAG TMS pin.
UserID JTAG User ID User The 32-bit JTAG User ID register value is loaded during configuration. The default
register string value is all ones, 0xFFFF_FFFF hexadecimal. To specify another value, enter an
8-character hexadecimal value.
Security JTAG, None Readback and partial reconfiguration are available via the JTAG port or via the
SelectMAP, SelectMAP interface, if the Persist option is set to Yes.
Readback,
Partial Level1 Readback function is disabled. Partial reconfiguration is still available via the JTAG port
reconfiguration or via the SelectMAP interface, if the Persist option is set to Yes.
Level Readback function is disabled. Partial reconfiguration is disabled.
CRC Configuration Enable Default. Enable CRC checking on the FPGA bitstream. If error detected, FPGA
asserts INIT_B Low and DONE pin stays Low.
Disable Turn off CRC checking.
Persist SelectMAP No All BPI and Slave mode configuration pins are available as user-I/O after configuration.
interface pins,
BPI mode, Yes This option is required for Readback and partial reconfiguration using the SelectMAP
Slave mode, interface. The SelectMAP interface pins (see Slave Parallel Mode, page 79) are
Configuration reserved after configuration and are not available as user-I/O.

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Powering Spartan-3E FPGAs VCCAUX. Each of the four I/O banks has a separate VCCO
supply input that powers the output buffers within the asso-
Voltage Supplies ciated I/O bank. All of the VCCO connections to a specific I/O
bank must be connected and must connect to the same
Like Spartan-3 FPGAs, Spartan-3E FPGAs have multiple
voltage.
voltage supply inputs, as shown in Table 58. There are two
supply inputs for internal logic functions, VCCINT and
Table 58: Spartan-3E Voltage Supplies

Supply Nominal Supply
Description
Input Voltage
VCCINT Internal core supply voltage. Supplies all internal logic functions such as 1.2V
CLBs, block RAM, multipliers, etc. Input to Power-On Reset (POR) circuit.
VCCAUX Auxiliary supply voltage. Supplies Digital Clock Managers (DCMs), 2.5V
differential drivers, dedicated configuration pins, JTAG interface. Input to
Power-On Reset (POR) circuit.
VCCO_0 Supplies the output buffers in I/O Bank 0, the bank along the top edge of the Selectable, 3.3V, 3.0V,
FPGA. 2.5V, 1.8, 1.5V, or 1.2V.
VCCO_1 Supplies the output buffers in I/O Bank 1, the bank along the right edge of the Selectable, 3.3V, 3.0V,
FPGA. In Byte-Wide Peripheral Interface (BPI) Parallel Flash Mode, 2.5V, 1.8, 1.5V, or 1.2V.
connects to the save voltage as the Flash PROM.
VCCO_2 Supplies the output buffers in I/O Bank 2 the bank along the bottom edge of Selectable, 3.3V, 3.0V,
the FPGA. Connects to the same voltage as the FPGA configuration source. 2.5V, 1.8, 1.5V, or 1.2V.
Input to Power-On Reset (POR) circuit.
VCCO_3 Supplies the output buffers in I/O Bank 0, the bank along the top edge of the Selectable, 3.3V, 3.0V,
FPGA. 2.5V, 1.8, 1.5V, or 1.2V.
In a 3.3V-only application, all four VCCO supplies connect to three-rail regulators specifically designed for Spartan-3 and
3.3V. However, Spartan-3E FPGAs provide the ability to Spartan-3E FPGAs. The Xilinx Power Corner web site pro-
bridge between different I/O voltages and standards by vides links to vendor solution guides and Xilinx power esti-
applying different voltages to the VCCO inputs of different mation and analysis tools.
banks. Refer to I/O Banking Rules for which I/O standards
can be intermixed within a single I/O bank. Power Distribution System (PDS) Design and
Each I/O bank also has an separate, optional input voltage Decoupling/Bypass Capacitors
reference supply, called VREF. If the I/O bank includes an Good power distribution system (PDS) design is important
I/O standard that requires a voltage reference such as for all FPGA designs, but especially so for high performance
HSTL or SSTL, then all VREF pins within the I/O bank must applications, greater than 100 MHz. Proper design results in
be connected to the same voltage. better overall performance, lower clock and DCM jitter, and
a generally more robust system. Before designing the
Voltage Regulators printed circuit board (PCB) for the FPGA design, please
Various power supply manufacturers offer complete power review XAPP623: "Power Distribution System (PDS)
solutions for Xilinx FPGAs including some with integrated Design: Using Bypass/Decoupling Capacitors".

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Revision History

03/21/05 1.1 Updated Figure 42. Modified title on Table 33 and Table 39.


018
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Spartan-3E FPGA Family:
DC and Switching
Characteristics
DC Electrical Characteristics
In this section, specifications may be designated as All parameter limits are representative of worst-case supply
Advance, Preliminary, or Production. These terms are voltage and junction temperature conditions. The following
defined as follows: applies unless otherwise noted: The parameter values
Advance: Initial estimates are based on simulation, early published in this module apply to all Spartan™-3E
characterization, and/or extrapolation from the characteris- devices. AC and DC characteristics are specified using
tics of other families. Values are subject to change. Use as the same numbers for both commercial and industrial
estimates, not for production. grades.
Preliminary: Based on characterization. Further changes If a particular Spartan-3E FPGA differs in functional
are not expected. behavior or electrical characteristic from this data
sheet, those differences are described in a separate
Production: These specifications are approved once the errata document. The errata documents for Spartan-3E
silicon has been characterized over numerous production FPGAs are living documents and are available online.
lots. Parameter values are considered stable with no future
changes expected.
Table 1: Absolute Maximum Ratings

Symbol Description Conditions Min Max Units
VCCINT Internal supply voltage –0.5 1.32 V
VCCAUX Auxiliary supply voltage –0.5 3.00 V
VCCO Output driver supply voltage –0.5 3.75 V
VREF Input reference voltage –0.5 VCCO + 0.5(3) V
VIN(2) Voltage applied to all User I/O pins and Driver in a high-impedance state –0.5 VCCO + 0.5(3) V
Dual-Purpose pins
Voltage applied to all Dedicated pins –0.5 VCCAUX + 0.5(4) V
VESD Electrostatic Discharge Voltage Human body model –2000 +2000 V
Charged device model –500 +500 V
Machine model –200 +200 V
TJ Junction temperature - 125 °C
TSTG Storage temperature –65 150 °C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only;
functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions is not
implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time adversely affects device reliability.
2. As a rule, the VIN limits apply to both the DC and AC components of signals. Simple application solutions are available that show how to
handle overshoot/undershoot as well as achieve PCI compliance. Refer to the following application notes: "Virtex™-II Pro and Spartan-3
3.3V PCI Reference Design" (XAPP653) and "Using 3.3V I/O Guidelines in a Virtex-II Pro Design" (XAPP659).
3. Each of the User I/O and Dual-Purpose pins is associated with one of the four banks’ VCCO rails. Meeting the VIN max limit ensures that the
internal diode junctions that exist between these pins and their associated VCCO rails do not turn on. Table 4 specifies the VCCO range used
to determine the max limit. When VCCO is at its maximum recommended operating level (3.45V), VIN max is 3.95V. The maximum voltage
that avoids oxide stress is VINX = 4.05V. As long as the VIN max specification is met, oxide stress is not possible.
4. All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) draw power from the VCCAUX rail (2.5V). Meeting the VIN max limit ensures
that the internal diode junctions that exist between each of these pins and the VCCAUX rail do not turn on. Table 4 specifies the VCCAUX range
used to determine the max limit. When VCCAUX is at its maximum recommended operating level (2.625V), VIN max < 3.125V. As long as the
VIN max specification is met, oxide stress is not possible.
5. For soldering guidelines, see "Device Packaging and Thermal Characteristics" at www.xilinx.com/bvdocs/userguides/ug112.pdf. Also see
"Implementation and Solder Reflow Guidelines for Pb-Free Packages" at www.xilinx.com/bvdocs/appnotes/xapp427.pdf.

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DC and Switching Characteristics
Table 2: Supply Voltage Thresholds for Power-On Reset

Symbol Description Min Max Units
VCCINTT Threshold for the VCCINT supply 0.4 1.0 V
VCCAUXT Threshold for the VCCAUX supply 0.8 2.0 V
VCCO2T Threshold for the VCCO Bank 2 supply 0.4 1.0 V
Notes:
1. VCCINT, VCCAUX, and VCCO supplies may be applied in any order.
2. To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with
no dips at any point.
Table 3: Power Voltage Levels Necessary for Preserving RAM Contents

Symbol Description Min Units
VDRINT VCCINT level required to retain RAM data 1.0 V
VDRAUX VCCAUX level required to retain RAM data 2.0 V
VDRO VCCO level required to retain RAM data 1.0 V
Notes:
1. RAM contents include configuration data.
Table 4: General Recommended Operating Conditions

Symbol Description Min Nom Max Units
TJ Junction temperature Commercial 0 - 85 °C
Industrial –40 - 100 °C
VCCINT Internal supply voltage 1.140 1.200 1.260 V
VCCO (1) Output driver supply voltage 1.140 - 3.450 V
VCCAUX (2) Auxiliary supply voltage 2.375 2.500 2.625 V
Notes:
1. The VCCO range given here spans the lowest and highest operating voltages of all supported I/O standards. The recommended VCCO range
specific to each of the single-ended I/O standards is given in Table 7, and that specific to the differential standards is given in Table 9.
2. Only during DCM operation, it is recommended that the rate of change of VCCAUX not exceed 10 mV/ms.

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Table 5: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins

Symbol Description Test Conditions Min Typ Max Units
IL(2) Leakage current at User I/O, Driver is in a high-impedance state, –10 - +10 µA
Dual-Purpose, and Dedicated pins VIN = 0V or VCCO max, sample-tested
IRPU(3) Current through pull-up resistor at VIN = 0V, VCCO = 3.3V mA
User I/O, Dual-Purpose, and
VIN = 0V, VCCO = 3.0V mA
Dedicated pins
IRPD(3) Current through pull-down resistor at VIN = VCCO mA
User I/O, Dual-Purpose, and
Dedicated pins
IREF VREF current per pin All VCCO levels –10 - +10 µA
CIN Input capacitance 3 - 10 pF
Notes:
1. The numbers in this table are based on the conditions set forth in Table 4.
2. The IL specification applies to every I/O pin throughout power-on as long as the voltage on that pin stays between the absolute VIN minimum
and maximum values (Table 1). For hot-swap applications, at the time of card connection, be sure to keep all I/O voltages within this range
before applying VCCO power. Also consider applying VCCO power before the connection of data lines occurs. When the FPGA is completely
unpowered, the impedance at the I/O pins is high.
3. This parameter is based on characterization. The pull-up resistance RPU = VCCO / IRPU. The pull-down resistance RPD = VIN / IRPD.

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Table 6: Quiescent Supply Current Characteristics

Symbol Description Device Typ(4) Max Units
ICCINTQ Quiescent VCCINT supply current XC3S100E 15 mA
XC3S250E 38 mA
XC3S500E 68 mA
XC3S1200E 98 mA
XC3S1600E 108 mA
ICCOQ Quiescent VCCO supply current XC3S100E 1.0 mA
XC3S250E 1.5 mA
XC3S500E 1.7 mA
XC3S1200E 1.8 mA
XC3S1600E 2.2 mA
ICCAUXQ Quiescent VCCAUX supply current XC3S100E 10 mA
XC3S250E 15 mA
XC3S500E 25 mA
XC3S1200E 35 mA
XC3S1600E 45 mA
Notes:
1. The numbers in this table are based on the conditions set forth in Table 4. Quiescent supply current is measured with all I/O drivers in a
high-impedance state and with all pull-up/pull-down resistors at the I/O pads disabled. For typical values, the ambient temperature (TA) is
25°C with VCCINT = 1.2V, VCCO = 2.5V, and VCCAUX = 2.5V. The FPGA is programmed with a "blank" configuration data file (i.e., a design
with no functional elements instantiated). For conditions other than those described above, (e.g., a design including functional elements),
measured quiescent current levels may be higher than the values in the table.
2. There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) The
Spartan-3E Web Power Tool, a future web-based application, provides quick, approximate, typical estimates, and does not require a netlist
of the design. b) XPower, which will be included in a future release of the Xilinx development software, takes a netlist as input to provide
more accurate maximum and typical estimates.
3. The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power-on successfully.
4. All typical quiescent current values are early estimates.

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Table 7: Recommended Operating Conditions for User I/Os Using Single-Ended Standards
VCCO for Drivers(2) VREF VIL VIH
IOSTANDARD
Attribute Min (V) Nom (V) Max (V) Min (V) Nom (V) Max (V) Max (V) Min (V)
HSTL_I_18 1.7 1.8 1.9 0.8 0.9 1.1 VREF - 0.1 VREF + 0.1
HSTL_III_18 1.7 1.8 1.9 - 1.1 - VREF - 0.1 VREF + 0.1
LVCMOS12(4) 1.1 1.2 1.3 - - - 0.38 0.8
LVCMOS15(4) 1.4 1.5 1.6 - - - 0.38 0.8
LVCMOS18(4) 1.65 1.8 1.95 - - - 0.38 0.8
LVCMOS25(4,5) 2.3 2.5 2.7 - - - 0.7 1.7
LVCMOS33(4) 3.0 3.3 3.45 - - - 0.8 2.0
LVTTL 3.0 3.3 3.45 - - - 0.8 2.0
PCI33_3(7) - 3.0 - - - - 0.9 1.5
PCI66_3(7) - 3.0 - - - - 0.9 1.5
PCIX(7) - TBD - - - - TBD TBD
SSTL18_I 1.70 1.80 1.90 0.833 0.900 0.969 VREF - 0.125 VREF + 0.125
SSTL2_I 2.3 2.5 2.7 1.15 1.25 1.35 VREF - 0.15 VREF + 0.15
Notes:
1. Descriptions of the symbols used in this table are as follows:
VCCO -- the supply voltage for output drivers
VREF -- the reference voltage for setting the input switching threshold
VIL -- the input voltage that indicates a Low logic level
VIH -- the input voltage that indicates a High logic level
2. The VCCO rails supply only output drivers, not input circuits.
3. For device operation, the maximum signal voltage (VIH max) may be as high as VIN max. See Table 1.
4. There is approximately 100 mV of hysteresis on inputs using any LVCMOS standard.
5. All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) use the LVCMOS25 standard and draw power from the VCCAUX rail (2.5V).
The Dual-Purpose configuration pins use the LVCMOS25 standard before the User mode. When using these pins as part of a standard 2.5V
configuration interface, apply 2.5V to the VCCO lines of Banks 0, 1, and 2 at power-on as well as throughout configuration.
6. The Global Clock Inputs (GCLK0-GCLK15, RHCLK0-RHCLK7, and LHCLK0-LHCLK7) are Dual-Purpose pins to which any signal standard
may be assigned.
7. For more information, see "Virtex-II Pro and Spartan-3 3.3V PCI Reference Design" (XAPP653).

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Table 8: DC Characteristics of User I/Os Using Single-Ended Standards

Test Conditions Logic Level Characteristics
IOL IOH VOL VOH
IOSTANDARD Attribute (mA) (mA) Max (V) Min (V)
HSTL_I_18 8 –8 0.4 VCCO - 0.4
HSTL_III_18 24 –8 0.4 VCCO - 0.4
LVCMOS12(3) 2 2 –2 0.4 VCCO - 0.4
LVCMOS15(3) 2 2 –2 0.4 VCCO - 0.4
4 4 –4
6 6 –6
LVCMOS18(3) 2 2 –2 0.4 VCCO - 0.4
4 4 –4
6 6 –6
8 8 –8
LVCMOS25(3,4) 2 2 –2 0.4 VCCO - 0.4
4 4 –4
6 6 –6
8 8 –8
12 12 –12
LVCMOS33(3) 2 2 –2 0.4 VCCO - 0.4
4 4 –4
6 6 –6
8 8 –8
12 12 –12
16 16 –16
LVTTL(3) 2 2 –2 0.4 2.4
4 4 –4
6 6 –6
8 8 –8
12 12 –12
16 16 –16
PCI33_3(5) 1.5 –0.5 0.10VCCO 0.90VCCO
PCI66_3(5) 1.5 –0.5 0.10VCCO 0.90VCCO
PCIX TBD TBD TBD TBD
SSTL18_I 6.7 –6.7 VTT - 0.475 VTT + 0.475

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Table 8: DC Characteristics of User I/Os Using Single-Ended Standards (Continued)

Test Conditions Logic Level Characteristics
IOL IOH VOL VOH
IOSTANDARD Attribute (mA) (mA) Max (V) Min (V)
SSTL2_I 8.1 –8.1 VTT - 0.61 VTT + 0.61
Notes:
1. The numbers in this table are based on the conditions set forth in Table 4 and Table 7.
2. Descriptions of the symbols used in this table are as follows:
IOL -- the output current condition under which VOL is tested
IOH -- the output current condition under which VOH is tested
VOL -- the output voltage that indicates a Low logic level
VOH -- the output voltage that indicates a High logic level
VIL -- the input voltage that indicates a Low logic level
VIH -- the input voltage that indicates a High logic level
VCCO -- the supply voltage for output drivers
VREF -- the reference voltage for setting the input switching threshold
VTT -- the voltage applied to a resistor termination
3. For the LVCMOS and LVTTL standards: the same VOL and VOH limits apply for both the Fast and Slow slew attributes.
4. All Dedicated output pins (DONE and TDO) as well as Dual-Purpose totem-pole output pins (CCLK, D0-D7, BUSY/DOUT, CSO_B, MOSI,
HDC, LDC0-LDC2, and A0-A23) exhibit the characteristics of LVCMOS25 with Slow slew rate; all have 8 mA drive except CCLK, which has
12 mA drive.
5. Tested according to the relevant PCI specifications. For more information, see "Virtex-II Pro and Spartan-3 3.3V PCI Reference Design"
(XAPP653).

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VINP
P Differential
Internal N I/O Pair Pins
VINN
Logic
VINN
50% VID
VINP
VICM
GND level
VINP + VINN
VICM = Input common mode voltage =
2
VID = Differential input voltage = VINP - VINN

DS099-3_01_012304
Figure 1: Differential Input Voltages
Table 9: Recommended Operating Conditions for User I/Os Using Differential Signal Standards
VCCO for Drivers(1) VID VICM VIH VIL
IOSTANDARD Min Nom Max Min Nom Max Min Nom Max Min Max Min Max
Attribute (V) (V) (V) (mV) (mV) (mV) (V) (V) (V) (V) (V) (V) (V)
LVDS_25 2.375 2.50 2.625 100 350 600 0.30 1.25 2.20 - - - -
BLVDS_25 2.375 2.50 2.625 100 350 600 0.30 1.25 2.20 - - - -
MINI_LVDS_25 2.375 2.50 2.625 200 - 600 0.30 - 2.2
LVPECL_25(2) Inputs Only 100 800 1000 0.3 1.2 2.2 0.8 2.0 0.5 1.7
RSDS_25 2.375 2.50 2.625 100 200 - 0.3 1.20 1.4 - - - -
Notes:
1. The VCCO rails supply only differential output drivers, not input circuits.
2. Spartan-3E devices support this standard for inputs only, not for outputs.
3. VREF inputs are not used for any of the differential I/O standards.

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VOUTP
P Differential
Internal N I/O Pair Pins
VOUTN
Logic
VOH
VOUTN
50% VOD
VOUTP
VOL
VOCM
GND level
VOUTP + VOUTN
VOCM = Output common mode voltage =
2
VOD = Output differential voltage = VOUTP - VOUTN
VOH = Output voltage indicating a High logic level
VOL = Output voltage indicating a Low logic level DS312-3_03_021505
Figure 2: Differential Output Voltages
Table 10: DC Characteristics of User I/Os Using Differential Signal Standards

VOD ∆VOD VOCM ∆VOCM VOH VOL
IOSTANDARD Min Typ Max Min Max Min Min Max Min Max
Attribute (mV) (mV) (mV) (mV) (mV) (V) Typ (V) Max (V) (mV) (mV) (V) (V)
LVDS_25 250 350 450 - - 1.125 - 1.375 - - 1.25 1.25
BLVDS_25 250 350 450 - - - 1.20 - - - - -
MINI_LVDS_25 300 - 600 - 50 1.0 - 1.4 - 50 1.15 1.25
RSDS_25 100 - 400 - - 1.1 - 1.4 - - 1.15 1.35
Notes:
1. The numbers in this table are based on the conditions set forth in Table 4 and Table 9.
2. Output voltage measurements for all differential standards are made with a termination resistor (RT) of 100Ω across the N and P pins of the
differential signal pair.
3. At any given time, no more than two differential standards may be assigned to each bank.

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Switching Characteristics
All Spartan-3E FPGAs ship in two speed grades: –4 and the data, use the values reported by the Xilinx static timing ana-
higher performance –5. Switching characteristics in this lyzer (TRACE in the Xilinx development software) and
document may be designated as Advance, Preliminary, or back-annotated to the simulation netlist.
Production, as shown in Table 11. Each category is defined
as follows: Table 11: Spartan-3E v1.10 Speed Grade Designations
Advance: These specifications are based on simulations Device Preview Advance Preliminary Production
only and are typically available soon after establishing XC3S100E –4
FPGA specifications. Although speed grades with this des-
ignation are considered relatively stable and conservative, XC3S250E –4
some under-reporting might still occur. XC3S500E –4
Preliminary: These specifications are based on complete XC3S1200E –4
early silicon characterization. Devices and speed grades
XC3S1600E –4
with this designation are intended to give a better indication
of the expected performance of production silicon. The System
probability of under-reporting preliminary delays is greatly Prototyping Only Production
Usage
reduced compared to Advance data.
Production: These specifications are approved once Digital Clock Manager (DCM) Timing
enough production silicon of a particular device family mem-
ber has been characterized to provide full correlation For specification purposes, the DCM consists of three key
between speed files and devices over numerous production components: the Delay-Locked Loop (DLL), the Digital Fre-
lots. There is no under-reporting of delays, and customers quency Synthesizer (DFS), and the Phase Shifter (PS).
receive formal notification of any subsequent changes. Typ- Aspects of DLL operation play a role in all DCM applica-
ically, the slowest speed grades transition to Production tions. All such applications inevitably use the CLKIN and the
before faster speed grades. CLKFB inputs connected to either the CLK0 or the CLK2X
Production-quality systems must use FPGA designs com- feedback, respectively. Thus, specifications in the DLL
piled using a speed file designated as Production status. tables (Table 12 and Table 13) apply to any application that
FPGAs designs using a less mature speed file designation only employs the DLL component. When the DFS and/or
should only be used during system prototyping or pre-pro- the PS components are used together with the DLL, then
duction qualification. FPGA designs with speed files desig- the specifications listed in the DFS and PS tables super-
nated as Preview, Advance, or Preliminary should not be sede any corresponding ones in the DLL tables. (See
used in a production-quality system. Table 14 and Table 15 for the DFS; tables for the PS are not
yet available.) DLL specifications that do not change with
Whenever a speed file designation changes, as a device the addition of DFS or PS functions are presented in
matures toward Production status, Xilinx recommends Table 12 and Table 13.
rerunning the Xilinx ISE software on the FPGA design. This
ensures that the FPGA design incorporates the latest timing All DCM clock output signals exhibit an approximate duty
information and software updates. cycle of 50%.
All specified limits are representative of worst-case supply Period jitter and cycle-cycle jitter are two (of many) different
voltage and junction temperature conditions. Unless other- ways of characterizing clock jitter. Both specifications
wise noted, the following applies: Parameter values apply to describe statistical variation from a mean value.
all Spartan-3E devices. All parameters representing volt- Period jitter is the worst-case deviation from the average
ages are measured with respect to GND. clock period of all clock cycles in the collection of clock peri-
Timing parameters and their representative values are ods sampled (usually from 100,000 to more than a million
selected for inclusion below either because they are impor- samples for specification purposes). In a histogram of
tant as general design requirements or they indicate funda- period jitter, the mean value is the clock period.
mental device performance characteristics. The Spartan-3E Cycle-cycle jitter is the worst-case difference in clock period
speed files (v1.10), part of the Xilinx Development Software, between adjacent clock cycles in the collection of clock peri-
are the original source for many but not all of the values. ods sampled. In a histogram of cycle-cycle jitter, the mean
The speed grade designations for these files are shown in value is zero.
Table 11. For more complete, more precise, and worst-case

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Table 12: Recommended Operating Conditions for the DLL

Speed Grade
-5 -4
Symbol Description Min Max Min Max Units
Input Frequency Ranges
FCLKIN CLKIN_FREQ_DLL Frequency for the CLKIN input 5 326 5(2) 280 MHz
Notes:
1. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
2. Use of the DFS permits lower FCLKIN frequencies. See Table 14.
Table 13: Switching Characteristics for the DLL

Speed Grade
-5 -4
Output Frequency Ranges
CLKOUT_FREQ_1X Frequency for the CLK0 and CLK180 outputs 5 326 5 280 MHz
Frequency for the CLK90 and CLK270 outputs 5 165 5 165 MHz
CLKOUT_FREQ_2X Frequency for the CLK2X and CLK2X180 10 400 10 330 MHz
outputs
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 4 and Table 12.
2. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.

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Table 14: Recommended Operating Conditions for the DFS

Speed Grade
-5 -4
Input Frequency Ranges(2)
FCLKIN CLKIN_FREQ_FX Frequency for the CLKIN input 0.2 326 0.2 326 MHz
Notes:
1. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are in use.
2. If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 12.
Table 15: Switching Characteristics for the DFS

Speed Grade
-5 -4
Output Frequency Ranges
CLKOUT_FREQ_FX Frequency for the CLKFX and CLKFX180 outputs 5 326 5 280 MHz
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 4 and Table 14.
2. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) is in use.

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Configuration and JTAG Timing
VCCINT 1.2V
(Supply) 1.0V
VCCAUX 2.5V
(Supply) 2.0V
VCCO Bank 2
(Supply) 1.0V
TPOR
PROG_B
(Input)
TPROG TPL
INIT_B
(Open-Drain)
TICCK
CCLK
(Output)
DS312-3_01_020505
Notes:
1. The VCCINT, VCCAUX, and VCCO supplies may be applied in any order.
2. The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle.
3. The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).
Figure 3: Waveforms for Power-On and the Beginning of Configuration
Table 16: Power-On Timing and the Beginning of Configuration

All Speed Grades
Symbol Description Device Min Max Units
TPOR(2) The time from the application of VCCINT, VCCAUX, and VCCO XC3S100E - 5 ms
Bank 2 supply voltage ramps (whichever occurs last) to the XC3S250E - 5 ms
rising transition of the INIT_B pin
XC3S500E - 5 ms
XC3S1200E - 5 ms
XC3S1600E - 7 ms
TPROG The width of the low-going pulse on the PROG_B pin All 0.3 - µs
TPL (2) The time from the rising edge of the PROG_B pin to the XC3S100E - 2 ms
rising transition on the INIT_B pin XC3S250E - 2 ms
XC3S500E - 2 ms
XC3S1200E - 2 ms
XC3S1600E - 3 ms
TICCK(3) The time from the rising edge of the INIT_B pin to the All 0.5 4.0 µs
generation of the configuration clock signal at the CCLK
output pin
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 4. This means power must be applied to all VCCINT, VCCO,
and VCCAUX lines.
2. Power-on reset and the clearing of configuration memory occurs during this period.
3. This specification applies only to the Master Serial, SPI, BPI-Up, and BPI-Down modes.

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PROG_B
(Input)
INIT_B
(Open-Drain)
TCCL TCCH
CCLK
(Input/Output)
TDCC TCCD 1/FCCSER
DIN
(Input) Bit 0 Bit 1 Bit n Bit n+1
TCCO
DOUT
Bit n-64 Bit n-63
(Output)
DS099-3_04_071604
Figure 4: Waveforms for Master and Slave Serial Configuration
Table 17: Timing for the Master and Slave Serial Configuration Modes
All Speed Grades
Slave/
Symbol Description Master Min Max Units
Clock-to-Output Times
TCCO The time from the falling transition on the CCLK pin to data Both 1.5 12.0 ns
appearing at the DOUT pin
Setup Times
TDCC The time from the setup of data at the DIN pin to the rising transition Both 10.0 - ns
at the CCLK pin
Hold Times
TCCD The time from the rising transition at the CCLK pin to the point when Both 0 - ns
data is last held at the DIN pin
Clock Timing
TCCH The High pulse width at the CCLK input pin Slave 5.0 - ns
TCCL The Low pulse width at the CCLK input pin 5.0 - ns
FCCSER Frequency of the clock signal at No bitstream compression - 66(2) MHz
the CCLK input pin
With bitstream compression - 20 MHz
∆FCCSER Variation from the CCLK output frequency set using the ConfigRate Master –50% +50% -
BitGen option
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 4.
2. For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.

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PROG_B
(Input)
INIT_B
(Open-Drain)
TSMCSCC TSMCCCS
CS_B
(Input)
TSMCCW
TSMWCC
RDWR_B
(Input)
TCCH TCCL
CCLK
(Input)
TSMDCC TSMCCD 1/FCCPAR
D0 - D7 Byte 0 Byte 1 Byte n Byte n+1

(Inputs)
TSMCKBY TSMCKBY
BUSY High-Z High-Z

(Output) BUSY
DS312-3_02_020805
Notes:
1. It is possible to abort configuration by pulling CS_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent
cycle for which CS_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0 - D7 bus. When RDWR_B
switches High, be careful to avoid contention on the D0 - D7 bus.
Figure 5: Waveforms for Slave Parallel Configuration
Table 18: Timing for the Slave Parallel Configuration Mode

All Speed Grades
TSMCKBY The time from the rising transition on the CCLK pin to a signal transition at the - 12.0 ns
BUSY pin
Setup Times
TSMDCC The time from the setup of data at the D0-D7 pins to the rising transition at the 10.0 - ns
CCLK pin
TSMCSCC The time from the setup of a logic level at the CS_B pin to the rising transition 10.0 - ns
at the CCLK pin
TSMCCW(2) The time from the setup of a logic level at the RDWR_B pin to the rising 10.0 - ns
transition at the CCLK pin

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Table 18: Timing for the Slave Parallel Configuration Mode (Continued)
All Speed Grades
Hold Times
TSMCCD The time from the rising transition at the CCLK pin to the point when data is 0 - ns
last held at the D0-D7 pins
TSMCCCS The time from the rising transition at the CCLK pin to the point when a logic 0 - ns
level is last held at the CS_B pin
TSMWCC The time from the rising transition at the CCLK pin to the point when a logic 0 - ns
level is last held at the RDWR_B pin
Clock Timing
TCCH The High pulse width at the CCLK input pin 5 - ns
TCCL The Low pulse width at the CCLK input pin 5 - ns
FCCPAR Frequency of the clock No bitstream Not using the BUSY pin(2) - 50 MHz
signal at the CCLK input compression
pin Using the BUSY pin - 66 MHz
With bitstream compression - 20 MHz
Notes:
2. In the Slave Parallel mode, it is necessary to use the BUSY pin when the CCLK frequency exceeds this maximum specification.
3. Some Xilinx documents may refer to Parallel modes as "SelectMAP" modes.

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TCCH TCCL
TCK
(Input)
1/FTCK
TTMSTCK TTCKTMS
TMS
(Input)
TTDITCK TTCKTDI
TDI
(Input)
TTCKTDO
TDO
(Output)
DS099_06_040703
Figure 6: JTAG Waveforms
Table 19: Timing for the JTAG Test Access Port

All Speed Grades
TTCKTDO The time from the falling transition on the TCK pin 1.0 11.0 ns
to data appearing at the TDO pin
Setup Times
TTDITCK The time from the setup of data at the TDI pin to 7.0 - ns
the rising transition at the TCK pin
TTMSTCK The time from the setup of a logic level at the TMS 7.0 - ns
pin to the rising transition at the TCK pin
Hold Times
TTCKTDI The time from the rising transition at the TCK pin 0 - ns
to the point when data is last held at the TDI pin
TTCKTMS The time from the rising transition at the TCK pin 0 - ns
to the point when a logic level is last held at the
TMS pin
Clock Timing
TCCH The High pulse width at the TCK pin 5 - ns
TCCL The Low pulse width at the TCK pin 5 - ns
FTCK Frequency of the TCK signal - 33 MHz
Notes:

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Revision History



072

Pinout Descriptions
Introduction Pin Types

This section describes the various pins on a Spartan™-3E A majority of the pins on a Spartan-3E FPGA are gen-
FPGA and how they connect within the supported compo- eral-purpose, user-defined I/O pins. There are, however, up
nent packages. to 11 different functional types of pins on Spartan-3E pack-
ages, as outlined in Table 1. In the package footprint draw-
ings that follow, the individual pins are color-coded
according to pin type as in the table.
Table 1: Types of Pins on Spartan-3E FPGAs

Type /
Color Code Description Pin Name(s) in Type
I/O Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to IO
form differential I/Os. IO_Lxxy_#
INPUT Unrestricted, general-purpose input-only pin. This pin does not have an output IP
structure. IP_Lxxy_#
DUAL Dual-purpose pin used in some configuration modes during the configuration M[2:0]
process and then usually available as a user I/O after configuration. If the pin is HSWAP
not used during configuration, this pin behaves as an I/O-type pin. Some of the CCLK
dual-purpose pins are also global or edge clock inputs (GCLK). MOSI/CSI_B
D[7:1]
D0/DIN
CSO_B
RDWR_B
BUSY/DOUT
INIT_B
A[23:20]
A19/VS2
A18/VS1
A17/VS0
A[16:0]
LDC[2:0]
HDC
VREF Dual-purpose pin that is either a user-I/O pin or, along with all other VREF pins IP/VREF_#
in the same bank, provides a reference voltage input for certain I/O standards. IP_Lxx_#/VREF_#
If used for a reference voltage within a bank, all VREF pins within the bank must
be connected.
GCLK Either a user-I/O pin or an input to a specific clock buffer driver. Every package GCLK[15:0],
LHCLK has 16 global clock inputs that optionally clock the entire device. The RHCLK LHCLK[7:0],
RHCLK inputs optionally clock the right-hand side of the device. The LHCLK inputs RHCLK[7:0]
optionally clock the left-hand side of the device. Some of the clock pins are
shared with the dual-purpose configuration pins and are considered DUAL-type.
CONFIG Dedicated configuration pin. Not available as a user-I/O pin. Every package has DONE, PROG_B
two dedicated configuration pins. These pins are powered by VCCAUX.

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Pinout Descriptions
Table 1: Types of Pins on Spartan-3E FPGAs

Type /
Color Code Description Pin Name(s) in Type
JTAG Dedicated JTAG pin. Not available as a user-I/O pin. Every package has four TDI, TMS, TCK, TDO
dedicated JTAG pins. These pins are powered by VCCAUX.
GND Dedicated ground pin. The number of GND pins depends on the package used. GND
All must be connected.
VCCAUX Dedicated auxiliary power supply pin. The number of VCCAUX pins depends on VCCAUX
the package used. All must be connected to +2.5V.
VCCINT Dedicated internal core logic power supply pin. The number of VCCINT pins VCCINT
depends on the package used. All must be connected to +1.2V.
VCCO Along with all the other VCCO pins in the same bank, this pin supplies power to VCCO_#
the output buffers within the I/O bank and sets the input threshold voltage for
some I/O standards.
N.C. This package pin is not connected in this specific device/package combination N.C.
but may be connected in larger devices in the same package.
Notes:
1. # = I/O bank number, an integer between 0 and 3.
I/Os with Lxxy_# are part of a differential output pair. ‘L’ indi- significance. Figure 1 provides a specific example showing
cates differential output capability. The “xx” field is a a differential input to and a differential output from Bank 1.
two-digit integer, unique to each bank that identifies a differ- ‘L’ indicates that the pin is part of a differentiaL pair.
ential pin-pair. The ‘y’ field is either ‘P’ for the true signal or
‘N’ for the inverted signal in the differential pair. The ‘#’ field "xx" is a two-digit integer, unique for each bank, that
is the I/O bank number. identifies a differential pin-pair.
‘y’ is replaced by ‘P’ for the true signal or ‘N’ for the
Differential Pair Labeling inverted. These two pins form one differential pin-pair.
A pin supports differential standards if the pin is labeled in
‘#’ is an integer, 0 through 3, indicating the associated
the format “Lxxy_#”. The pin name suffix has the following
I/O bank.
Pair Number
Bank 0 Bank Number

IO_L38P_1
IO_L38N_1
Bank 1
Positive Polarity,
Bank 3
True Driver
IO_L39P_1
Spartan-3E
FPGA IO_L39N_1
Negative Polarity,
Inverted Driver
Bank 2 DS312-4_00_022305
Figure 1: Differential Pair Labeling

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Pinout Descriptions
Package Overview mechanical dimensions of the standard and Pb-free pack-

ages are similar, as shown in the mechanical drawings pro-
Table 2 shows the eight low-cost, space-saving production
vided in Table 4.
package styles for the Spartan-3E family. Each package
style is available as a standard and an environmen- Not all Spartan-3E densities are available in all packages.
tally-friendly lead-free (Pb-free) option. The Pb-free pack- For a specific package, however, there is a common foot-
ages include an extra ‘G’ in the package style name. For print that supports all the devices available in that package.
example, the standard "VQ100" package becomes See the footprint diagrams that follow.
"VQG100" when ordered as the Pb-free option. The
Table 2: Spartan-3E Family Package Options

Maximum Pitch Height
Package Leads Type I/O (mm) Area (mm) (mm)
VQ100 / VQG100 100 Very-thin Quad Flat Pack (VQFP) 66 0.5 16 x 16 1.20
CP132 / CPG132 132 Chip-Scale Package (CSP) 92 0.5 8x8 1.10
TQ144 / TQG144 144 Thin Quad Flat Pack (TQFP) 108 0.5 22 x 22 1.60
PQ208 / PQG208 208 Plastic Quad Flat Pack (PQFP) 158 0.5 30.6 x 30.6 4.10
FT256 / FTG256 256 Fine-pitch, Thin Ball Grid Array (FBGA) 190 1.0 17 x 17 1.55
FG320 / FGG320 320 Fine-pitch Ball Grid Array (FBGA) 250 1.0 19 x 19 2.00
Selecting the Right Package Option packages are superior in almost every other aspect, as
summarized in Table 3. Consequently, Xilinx recommends
Spartan-3 FPGAs are available in both quad-flat pack
using BGA packaging whenever possible.
(QFP) and ball grid array (BGA) packaging options. While
QFP packaging offers the lowest absolute cost, the BGA
Table 3: QFP and BGA Comparison

Characteristic Quad Flat Pack (QFP) Ball Grid Array (BGA)
Maximum User I/O 158 376
Packing Density (Logic/Area) Good Better
Signal Integrity Fair Better
Simultaneous Switching Output (SSO) Support Limited Better
Thermal Dissipation Fair Better
Minimum Printed Circuit Board (PCB) Layers 4 6
Hand Assembly/Rework Possible Difficult

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Pinout Descriptions
Mechanical Drawings
Detailed mechanical drawings for each package type are
available from the Xilinx website at the specified location in
Table 4.
Table 4: Xilinx Package Mechanical Drawings

Package Web Link (URL)
VQ100 / VQG100 http://www.xilinx.com/bvdocs/packages/vq100.pdf
CP132 / CPG132 http://www.xilinx.com/bvdocs/packages/cp132.pdf
TQ144 / TQG144 http://www.xilinx.com/bvdocs/packages/tq144.pdf
PQ208 / PQG208 http://www.xilinx.com/bvdocs/packages/pq208.pdf
FT256 / FTG256 http://www.xilinx.com/bvdocs/packages/ft256.pdf
FG320 / FGG320 http://www.xilinx.com/bvdocs/packages/fg320.pdf
Package Pins by Type A majority of package pins are user-defined I/O or input
pins. However, the numbers and characteristics of these I/O
Each package has three separate voltage supply
depend on the device type and the package in which it is
inputs—VCCINT, VCCAUX, and VCCO—and a common
available, as shown in Table 6. The table shows the maxi-
ground return, GND. The numbers of pins dedicated to
mum number of single-ended I/O pins available, assuming
these functions vary by package, as shown in Table 5.
that all I/O-, INPUT-, DUAL-, VREF-, and GCLK-type pins
Table 5: Power and Ground Supply Pins by Package are used as general-purpose I/O. Likewise, the table shows
the maximum number of differential pin-pairs available on
Package VCCINT VCCAUX VCCO GND the package. Finally, the table shows how the total maxi-
mum user-I/Os are distributed by pin type, including the
VQ100 4 4 8 12
number of unconnected—i.e., N.C.—pins on the device.
CP132 6 4 8 16
TQ144 4 4 9 13
PQ208 4 8 12 20
FT256 8 8 16 28
FG320 8 8 20 28
FG400 16 8 24 42
FG484 16 10 28 48

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Pinout Descriptions
Table 6: Maximum User I/O by Package

Maximum All Possible I/Os by Type
Maximum Differential
Device Package User I/Os Pairs I/O INPUT DUAL VREF GCLK N.C.
XC3S100E 66 30 16 1 21 4 24 0
VQ100
XC3S250E 66 30 16 1 21 4 24 0
XC3S250E 92 41 22 0 46 8 16 0
CP132
XC3S500E 92 41 22 0 46 8 16 0
XC3S100E 108 40 22 19 42 9 16 0
TQ144
XC3S250E 108 40 20 21 42 9 16 0
XC3S250E 158 65 58 25 46 13 16 0
PQ208
XC3S500E 158 65 58 25 46 13 16 0
XC3S250E 172 68 62 33 46 15 16 16
XC3S500E FT256 190 77 76 33 46 19 16 0
XC3S1200E 190 77 78 31 46 19 16 0
XC3S500E 232 92 102 48 46 20 16 18
XC3S1200E FG320 250 99 120 47 46 21 16 0
XC3S1600E 250 99 119 48 46 21 16 0
XC3S1200E 304 124 156 62 46 24 16 0
FG400
XC3S1600E 304 124 156 62 46 24 16 0
XC3S1600E FG484 376 156 214 72 46 28 16 0
Electronic versions of the package pinout tables and foot- ted according to any specific needs. Similarly, the
prints are available for download from the Xilinx web site. ASCII-text file is easily parsed by most scripting programs.
Download the files from the following location: Using a http://www.xilinx.com/bvdocs/publications/s3e_pin.zip
spreadsheet program, the data can be sorted and reformat-

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Pinout Descriptions
VQ100: 100-lead Very-thin Quad Flat Table 7: VQ100 Package Pinout

Package XC3S100E VQ100
XC3S250E Pin
The XC3S100E and the XC3S250E devices are available in
Bank Pin Name Number Type
the 100-lead very-thin quad flat package, VQ100. Both
devices share a common footprint for this package as 0 VCCO_0 P97 VCCO
shown in Table 7 and Figure 2.
1 IO_L01N_1 P54 I/O
Table 7 lists all the package pins. They are sorted by bank
number and then by pin name of the largest device. Pins 1 IO_L01P_1 P53 I/O
that form a differential I/O pair appear together in the table. 1 IO_L02N_1 P58 I/O
The table also shows the pin number for each pin and the
pin type, as defined earlier. 1 IO_L02P_1 P57 I/O
The VQ100 package does not support the Byte-wide 1 IO_L03N_1/RHCLK1 P61 RHCLK
Peripheral Interface (BPI) configuration mode. Conse- 1 IO_L03P_1/RHCLK0 P60 RHCLK
quently, the VQ100 footprint has fewer DUAL-type pins than
other packages. 1 IO_L04N_1/RHCLK3 P63 RHCLK
An electronic version of this package pinout table and foot- 1 IO_L04P_1/RHCLK2 P62 RHCLK
print diagram is available for download from the Xilinx web
1 IO_L05N_1/RHCLK5 P66 RHCLK
site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
1 IO_L05P_1/RHCLK4 P65 RHCLK
Pinout Table
1 IO_L06N_1/RHCLK7 P68 RHCLK
Table 7 shows the pinout for production Spartan-3E FPGAs
in the VQ100 package. The XC3S100 engineering samples 1 IO_L06P_1/RHCLK6 P67 RHCLK
have a slightly different pinout, as described in Table 9. 1 IO_L07N_1 P71 I/O
Table 7: VQ100 Package Pinout 1 IO_L07P_1 P70 I/O
XC3S100E VQ100 1 IP/VREF_1 P69 VREF

XC3S250E Pin
1 VCCO_1 P55 VCCO
Bank Pin Name Number Type
1 VCCO_1 P73 VCCO
0 IO P92 I/O
2 IO/D5 P34 DUAL
0 IO_L01N_0 P79 I/O
2 IO/M1 P42 DUAL
0 IO_L01P_0 P78 I/O
2 IO_L01N_2/INIT_B P25 DUAL
0 IO_L02N_0/GCLK5 P84 GCLK
2 IO_L01P_2/CSO_B P24 DUAL
0 IO_L02P_0/GCLK4 P83 GCLK
2 IO_L02N_2/MOSI/CSI_B P27 DUAL
2 IO_L02P_2/DOUT/BUSY P26 DUAL
2 IO_L03N_2/D6/GCLK13 P33 DUAL/GCLK
2 IO_L03P_2/D7/GCLK12 P32 DUAL/GCLK
0 IO_L06N_0/VREF_0 P95 VREF
0 IO_L06P_0 P94 I/O
0 IO_L07N_0/HSWAP P99 DUAL
0 IO_L07P_0 P98 I/O
2 IO_L07N_2/DIN/D0 P44 DUAL
0 IP_L04N_0/GCLK9 P89 GCLK
2 IO_L07P_2/M0 P43 DUAL
0 IP_L04P_0/GCLK8 P88 GCLK
2 IO_L08N_2/VS1 P48 DUAL
0 VCCO_0 P82 VCCO
2 IO_L08P_2/VS2 P47 DUAL

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Pinout Descriptions
Table 7: VQ100 Package Pinout Table 7: VQ100 Package Pinout

XC3S100E VQ100 XC3S100E VQ100
XC3S250E Pin XC3S250E Pin
Bank Pin Name Number Type Bank Pin Name Number Type
2 IO_L09N_2/CCLK P50 DUAL GND GND P87 GND
2 IO_L09P_2/VS0 P49 DUAL GND GND P93 GND
2 IP/VREF_2 P30 VREF VCCAUX DONE P51 CONFIG
2 IP_L05N_2/M2/GCLK1 P39 DUAL/GCLK VCCAUX PROG_B P1 CONFIG
2 IP_L05P_2/RDWR_B/ P38 DUAL/GCLK VCCAUX TCK P77 JTAG

GCLK0
VCCAUX TDI P100 JTAG
2 VCCO_2 P31 VCCO
VCCAUX TDO P76 JTAG
2 VCCO_2 P45 VCCO
VCCAUX TMS P75 JTAG
3 IO_L01N_3 P3 I/O
VCCAUX VCCAUX P21 VCCAUX
3 IO_L01P_3 P2 I/O
3 IO_L02N_3/VREF_3 P5 VREF
3 IO_L02P_3 P4 I/O
3 IO_L03N_3/LHCLK1 P10 LHCLK
VCCINT VCCINT P6 VCCINT
3 IO_L03P_3/LHCLK0 P9 LHCLK
3 IO_L07N_3 P23 I/O
3 IO_L07P_3 P22 I/O
3 IP P13 INPUT
3 VCCO_3 P8 VCCO
3 VCCO_3 P20 VCCO
GND GND P7 GND
GND GND P14 GND
GND GND P19 GND
GND GND P29 GND
GND GND P37 GND
GND GND P52 GND
GND GND P59 GND
GND GND P64 GND
GND GND P72 GND
GND GND P81 GND

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Pinout Descriptions
User I/Os by Bank

Table 8 indicates how the 66 available user-I/O pins are dis-
tributed between the four I/O banks on the VQ100 package.
Table 8: User I/Os Per Bank for XC3S100E and XC3S250E in the VQ100 Package
All Possible I/O Pins by Type
Package Maximum
Edge I/O Bank I/O I/O INPUT DUAL VREF GCLK
Top 0 15 5 0 1 1 8
Right 1 15 6 0 0 1 8
Bottom 2 19 0 0 18 1 0
Left 3 17 5 1 2 1 8
TOTAL 66 16 1 21 4 24
Footprint Migration Differences Table 9: XC3S100E Pinout Changes between

The production XC3S100E and XC3S250E FPGAs have Production Devices and Engineering Samples
identical footprints in the VQ100 package. Designs can XC3S100E XC3S100E
migrate between the XC3S100E and XC3S250E without Production Engineering
further consideration. VQ100 Pin Devices Samples
The pinout changed slightly between the XC3S100E engi- P40 D2/GCLK2 M1/GCLK2
neering samples and the production devices, as shown in
Table 9. In the engineering samples, the mode select pins P41 D1/GCLK3 M0/GCLK3
M1 and M0 overlap with two global clock inputs feeding the
P42 M1 D2
bottom-edge global buffers and DCMs. In the production
devices, the mode pins are swapped with parallel mode P43 M0 D1
data pins, D1 and D2. This way, these two mode pins do not
interfere with global clock inputs.

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Pinout Descriptions
VQ100 Footprint
In Figure 2, note pin 1 indicator in top-left corner and logo
orientation. The engineering sample footprint is slightly dif-
ferent.
IO_L05N_0/GCLK11
IO_L06N_0/VREF_0
IO_L05P_0/GCLK10
IO_L07N_0/HSWAP
IO_L03N_0/GCLK7
IO_L02N_0/GCLK5
IO_L03P_0/GCLK6
IO_L02P_0/GCLK4
IP_L04N_0/GCLK9
IP_L04P_0/GCLK8
IO_L01N_0
IO_L07P_0
IO_L06P_0
IO_L01P_0
VCCAUX
VCCO_0
VCCO_0
VCCINT
GND
GND
GND
TDO
TCK
TDI
IO
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PROG_B 1 75 TMS
IO_L01P_3 2 Bank 0 74 VCCAUX
IO_L01N_3 3 73 VCCO_1
IO_L02P_3 4 72 GND
IO_L02N_3/VREF_3 5 71 IO_L07N_1
VCCINT 6 70 IO_L07P_1
GND 7 69 IP/VREF_1
VCCO_3 8 68 IO_L06N_1/RHCLK7
IO_L03P_3/LHCLK0 9 67 IO_L06P_1/RHCLK6
IO_L03N_3/LHCLK1 10 66 IO_L05N_1/RHCLK5
IO_L04P_3/LHCLK2 11 65 IO_L05P_1/RHCLK4
Bank 3
Bank 1
IO_L04N_3/LHCLK3 12 64 GND
IP 13 63 IO_L04N_1/RHCLK3
GND 14 62 IO_L04P_1/RHCLK2
IO_L05P_3/LHCLK4 15 61 IO_L03N_1/RHCLK1
IO_L05N_3/LHCLK5 16 60 IO_L03P_1/RHCLK0
IO_L06P_3/LHCLK6 17 59 GND
IO_L06N_3/LHCLK7 18 58 IO_L02N_1
GND 19 57 IO_L02P_1
VCCO_3 20 56 VCCINT
VCCAUX 21 55 VCCO_1
IO_L07P_3 22 54 IO_L01N_1
IO_L07N_3 23 53 IO_L01P_1
IO_L01P_2/CSO_B 24 52 GND
IO_L01N_2/INIT_B 25
Bank 2 51 DONE
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GND
GND
IP/VREF_2
VCCO_2
IO_L03P_2/D7/GCLK12
IO_L03N_2/D6/GCLK13
IO/D5
IO_L04P_2/D4/GCLK14
IO_L04N_2/D3/GCLK15
IP_L05P_2/RDWR_B/GCLK0
IP_L05N_2/M2/GCLK1
IO_L06P_2/D2/GCLK2
IO_L06N_2/D1/GCLK3
IO/M1
IO_L07P_2/M0
IO_L07N_2/DIN/D0
VCCO_2
IO_L08P_2/VS2
IO_L08N_2/VS1
IO_L09P_2/VS0
VCCINT
VCCAUX
IO_L02N_2/MOSI/CSI_B
IO_L02P_2/DOUT/BUSY
IO_L09N_2/CCLK
DS312-4_02_030705
Figure 2: VQ100 Package Production Footprint (top view). Engineering Samples have slightly different footprint.
I/O: Unrestricted, DUAL: Configuration pin, then VREF: User I/O or input
16 general-purpose user I/O
21 possible user-I/O
4 voltage reference for bank
INPUT: Unrestricted, GCLK: User I/O, input, or VCCO: Output voltage supply
1 general-purpose input pin
24 global buffer input
8 for bank
CONFIG: Dedicated JTAG: Dedicated JTAG port VCCINT: Internal core supply
2 configuration pins
4 pins
4 voltage (+1.2V)
N.C.: Not connected GND: Ground VCCAUX: Auxiliary supply

0 12 4 voltage (+2.5V)

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Pinout Descriptions
CP132: 132-ball Chip-scale Package Table 10: CP132 Package Pinout

The XC3S250E and the XC3S500E FPGAs are available in XC3S250E
the 132-lead chip-scale package, CP132. Both devices XC3S500E CP132
share a common footprint for this package as shown in Bank Pin Name Ball Type
Table 10 and Figure 3. 0 IP_L06N_0/GCLK9 C8 GCLK
Table 10 lists all the CP132 package pins. They are sorted 0 IP_L06P_0/GCLK8 B8 GCLK
by bank number and then by pin name. Pins that form a dif-
ferential I/O pair appear together in the table. The table also 0 VCCO_0 A6 VCCO
shows the pin number for each pin and the pin type, as 0 VCCO_0 B10 VCCO
defined earlier.
1 IO/A0 F12 DUAL
Physically, the D14 and K2 balls on the XC3S250E FPGA
are not connected but should be connected to VCCINT to 1 IO/VREF_1 K13 VREF
maintain density migration compatibility.
1 IO_L01N_1/A15 N14 DUAL
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web- 1 IO_L01P_1/A16 N13 DUAL
site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip. 1 IO_L02N_1/A13 M13 DUAL
Pinout Table 1 IO_L02P_1/A14 M12 DUAL
1 IO_L03N_1/A11 L14 DUAL

Table 10: CP132 Package Pinout 1 IO_L03P_1/A12 L13 DUAL
XC3S250E 1 IO_L04N_1/A9/RHCLK1 J12 RHCLK/
XC3S500E CP132 DUAL
Bank Pin Name Ball Type
1 IO_L04P_1/A10/RHCLK0 K14 RHCLK/
0 IO_L01N_0 C12 I/O DUAL
0 IO_L01P_0 A13 I/O 1 IO_L05N_1/A7/RHCLK3/ J14 RHCLK/
0 IO_L02N_0 A12 I/O TRDY1 DUAL
0 IO_L02P_0 B12 I/O 1 IO_L05P_1/A8/RHCLK2 J13 RHCLK/

DUAL
0 IO_L03N_0/VREF_0 B11 VREF
1 IO_L06N_1/A5/RHCLK5 H12 RHCLK/
0 IO_L03P_0 C11 I/O DUAL
0 IO_L04N_0/GCLK5 C9 GCLK 1 IO_L06P_1/A6/RHCLK4/ H13 RHCLK/
IRDY1 DUAL
0 IO_L04P_0/GCLK4 A10 GCLK
1 IO_L07N_1/A3/RHCLK7 G13 RHCLK/
0 IO_L05N_0/GCLK7 A9 GCLK DUAL
0 IO_L05P_0/GCLK6 B9 GCLK 1 IO_L07P_1/A4/RHCLK6 G14 RHCLK/
0 IO_L07N_0/GCLK11 B7 GCLK DUAL
0 IO_L07P_0/GCLK10 A7 GCLK 1 IO_L08N_1/A1 F13 DUAL
0 IO_L08N_0/VREF_0 C6 VREF 1 IO_L08P_1/A2 F14 DUAL
0 IO_L08P_0 B6 I/O 1 IO_L09N_1/LDC0 D12 DUAL
0 IO_L09N_0 C5 I/O 1 IO_L09P_1/HDC D13 DUAL
0 IO_L09P_0 B5 I/O 1 IO_L10N_1/LDC2 C13 DUAL
0 IO_L10N_0 C4 I/O 1 IO_L10P_1/LDC1 C14 DUAL
0 IO_L10P_0 B4 I/O 1 IP/VREF_1 G12 VREF
0 IO_L11N_0/HSWAP B3 DUAL 1 VCCO_1 E13 VCCO
0 IO_L11P_0 A3 I/O 1 VCCO_1 M14 VCCO
2 IO/D5 P4 DUAL

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Pinout Descriptions
Table 10: CP132 Package Pinout Table 10: CP132 Package Pinout
XC3S250E XC3S250E
XC3S500E CP132 XC3S500E CP132
Bank Pin Name Ball Type Bank Pin Name Ball Type
2 IO/M1 N7 DUAL 3 IO_L01P_3 B2 I/O
2 IO/VREF_2 P11 VREF 3 IO_L02N_3 C2 I/O
2 IO_L01N_2/INIT_B N1 DUAL 3 IO_L02P_3 C3 I/O
2 IO_L01P_2/CSO_B M2 DUAL 3 IO_L03N_3 D1 I/O
2 IO_L02N_2/MOSI/CSI_B N2 DUAL 3 IO_L03P_3 D2 I/O
2 IO_L02P_2/DOUT/BUSY P1 DUAL 3 IO_L04N_3/LHCLK1 F2 LHCLK
2 IO_L03N_2/D6/GCLK13 N4 DUAL/ 3 IO_L04P_3/LHCLK0 F3 LHCLK

GCLK
3 IO_L05N_3/LHCLK3/IRDY2 G1 LHCLK
2 IO_L03P_2/D7/GCLK12 M4 DUAL/
GCLK 3 IO_L05P_3/LHCLK2 F1 LHCLK
2 IO_L04N_2/D3/GCLK15 N5 DUAL/ 3 IO_L06N_3/LHCLK5 H1 LHCLK

GCLK 3 IO_L06P_3/LHCLK4/TRDY2 G3 LHCLK
2 IO_L04P_2/D4/GCLK14 M5 DUAL/ 3 IO_L07N_3/LHCLK7 H3 LHCLK
GCLK
3 IO_L07P_3/LHCLK6 H2 LHCLK
2 IO_L06N_2/D1/GCLK3 P7 DUAL/
GCLK 3 IO_L08N_3 L2 I/O
2 IO_L06P_2/D2/GCLK2 P6 DUAL/ 3 IO_L08P_3 L1 I/O

GCLK
3 IO_L09N_3 M1 I/O
2 IO_L07N_2/DIN/D0 N8 DUAL
3 IO_L09P_3 L3 I/O
2 IO_L07P_2/M0 P8 DUAL
3 IP/VREF_3 E2 VREF
2 IO_L08N_2/A22 M9 DUAL
3 VCCO_3 E1 VCCO
2 IO_L08P_2/A23 N9 DUAL
3 VCCO_3 J2 VCCO
2 IO_L09N_2/A20 M10 DUAL
GND GND A4 GND
2 IO_L09P_2/A21 N10 DUAL
GND GND A8 GND
2 IO_L10N_2/VS1/A18 M11 DUAL
GND GND C1 GND
2 IO_L10P_2/VS2/A19 N11 DUAL
GND GND C7 GND
2 IO_L11N_2/CCLK N12 DUAL
GND GND C10 GND
2 IO_L11P_2/VS0/A17 P12 DUAL
GND GND E3 GND
2 IP/VREF_2 N3 VREF
GND GND E14 GND
2 IP_L05N_2/M2/GCLK1 N6 DUAL/
GND GND G2 GND
GCLK
GND GND H14 GND
2 IP_L05P_2/RDWR_B/ M6 DUAL/
GCLK0 GCLK GND GND J1 GND
2 VCCO_2 M8 VCCO GND GND K12 GND
2 VCCO_2 P3 VCCO GND GND M3 GND
3 IO J3 I/O GND GND M7 GND
3 IO/VREF_3 K3 VREF GND GND P5 GND
3 IO_L01N_3 B1 I/O

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Pinout Descriptions
Table 10: CP132 Package Pinout Table 10: CP132 Package Pinout
XC3S250E XC3S250E
XC3S500E CP132 XC3S500E CP132
GND GND P10 GND VCCAUX VCCAUX P9 VCCAUX
GND GND P14 GND VCCINT VCCINT A11 VCCINT
VCCAUX DONE P13 CONFIG VCCINT VCCINT D3 VCCINT
VCCAUX PROG_B A1 CONFIG VCCINT VCCINT D14 VCCINT
VCCAUX TCK B13 JTAG VCCINT VCCINT K2 VCCINT
VCCAUX TDI A2 JTAG VCCINT VCCINT L12 VCCINT
VCCAUX TDO A14 JTAG VCCINT VCCINT P2 VCCINT
VCCAUX TMS B14 JTAG

User I/Os by Bank
VCCAUX VCCAUX A5 VCCAUX
Table 20 indicates how the 92 available user-I/O pins are
VCCAUX VCCAUX E12 VCCAUX distributed between the four I/O banks on the CP132 pack-
VCCAUX VCCAUX K1 VCCAUX age.
Table 11: User I/Os Per Bank for the XC3S250E and XC3S500E in the CP132 Package
Package Maximum
Top 0 22 11 0 1 2 8
Right 1 23 0 0 21 2 0
Bottom 2 26 0 0 24 2 0
Left 3 21 11 0 0 2 8
TOTAL 92 22 0 46 8 16
Footprint Migration Differences migrate between the XC3S250E and XC3S500E without
further consideration.
The production XC3S250E and XC3S500E FPGAs have
identical footprints in the CP132 package. Designs can

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Pinout Descriptions
CP132 Footprint
Bank 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14
I/O I/O I/O
I/O I/O I/O
A PROG_B TDI
L11P_0
GND VCCAUX VCCO_0 L07P_0 GND L05N_0 L04P_0 VCCINT
L02N_0 L01P_0
TDO
GCLK10 GCLK7 GCLK4
I/O I/O INPUT I/O I/O

I/O I/O I/O I/O I/O I/O
B L01N_3 L01P_3
L11N_0
L10P_0 L09P_0 L08P_0
L07N_0 L06P_0 L05P_0 VCCO_0 L03N_0
L02P_0
TCK TMS
HSWAP GCLK11 GCLK8 GCLK6 VREF_0
I/O INPUT I/O I/O I/O

C GND
L02N_3 L02P_3 L10N_0 L09N_0
L08N_0 GND L06N_0 L04N_0 GND L03P_0 L01N_0
L10N_1 L10P_1
VREF_0 GCLK9 GCLK5 LDC2 LDC1
I/O I/O
I/O I/O
D L03N_3 L03P_3
VCCINT L09N_1 L09P_1 VCCINT
LDC0 HDC
INPUT
E VCCO_3 GND VCCAUX VCCO_1 GND
VREF_3
I/O I/O I/O I/O I/O

I/O
F L05P_3 L04N_3 L04P_3
A0
L08N_1 L08P_1
LHCLK2 LHCLK1 LHCLK0 A1 A2
Bank 3
I/O I/O I/O I/O

L05N_3 L06P_3 INPUT L07N_1 L07P_1
G LHCLK3
GND
LHCLK4 VREF_1 A3 A4
IRDY2 TRDY2 RHCLK7 RHCLK6
Bank 1
I/O I/O I/O I/O I/O
L06N_1 L06P_1
H L06N_3 L07P_3 L07N_3
A5
A6 GND
LHCLK5 LHCLK6 LHCLK7 RHCLK4
RHCLK5 IRDY1
I/O I/O I/O
L04N_1 L05P_1 L05N_1
J GND VCCO_3 I/O
A9 A8
A7
RHCLK3
RHCLK1 RHCLK2 TRDY1
I/O
I/O I/O L04P_1
K VCCAUX VCCINT GND
A10
VREF_3 VREF_1
RHCLK0
I/O I/O
I/O I/O I/O
L L08P_3 L08N_3 L09P_3
VCCINT L03P_1 L03N_1
A12 A11
I/O I/O I/O INPUT I/O I/O I/O I/O I/O

I/O L03P_2 L04P_2 L05P_2 L10N_2
M L09N_3
L01P_2 GND
D7 D4 RDWR_B
GND VCCO_2 L08N_2 L09N_2
VS1
L02P_1 L02N_1 VCCO_1
CSO_B GCLK12 GCLK14 GCLK0 A22 A20 A18 A14 A13
I/O I/O I/O I/O INPUT I/O I/O I/O I/O I/O I/O I/O
L02N_2 INPUT L03N_2 L04N_2 L05N_2 I/O L07N_2 L10P_2
N L01N_2
MOSI D6 D3 M2 M1 DIN
L08P_2 L09P_2
VS2
L11N_2 L01P_1 L01N_1
VREF_2
INIT_B CSI_B GCLK13 GCLK15 GCLK1 D0 A23 A21 A19 CCLK A16 A15
I/O I/O I/O I/O I/O

L02P_2 I/O L06P_2 L06N_2 I/O L11P_2
P DOUT
VCCINT VCCO_2
D5
GND
D2 D1
L07P_2 VCCAUX GND
VREF_2 VS0
DONE GND
BUSY GCLK2 GCLK3 M0 A17
Bank 2
DS312-4_07_031105
Figure 3: CP132 Package Footprint (top view)
42 possible user I/O
8 for bank
4 pins
6 voltage (+1.2V)

0 16 4 voltage (+2.5V)

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Pinout Descriptions
TQ144: 144-lead Thin Quad Flat mode. In larger packages, there are 24 BPI address out-
Package puts.
The XC3S100E and the XC3S250E FPGAs are available in
print diagram is available for download from the Xilinx web
the 144-lead thin quad flat package, TQ144. Both devices
share a common footprint for this package as shown in
Table 12 and Figure 4.
Pinout Table
Table 12 lists all the package pins. They are sorted by bank
number and then by pin name of the largest device. Pins Table 12 shows the pinout for production Spartan-3E
that form a differential I/O pair appear together in the table. FPGAs in the VQ100 package. The XC3S100 engineering
The table also shows the pin number for each pin and the samples have a slightly different pinout, as described in
pin type, as defined earlier. Table 15.
The TQ144 package only supports 20 address output pins

in the Byte-wide Peripheral Interface (BPI) configuration
Table 12: TQ144 Package Pinout

Bank XC3S100E Pin Name XC3S250E Pin Name TQ144 Pin Type
0 IO IO P132 I/O
0 IO/VREF_0 IO/VREF_0 P124 VREF
0 IO_L01N_0 IO_L01N_0 P113 I/O
0 IO_L01P_0 IO_L01P_0 P112 I/O
0 IO_L02N_0 IO_L02N_0 P117 I/O
0 IO_L02P_0 IO_L02P_0 P116 I/O
0 IO_L04N_0/GCLK5 IO_L04N_0/GCLK5 P123 GCLK
0 IO_L04P_0/GCLK4 IO_L04P_0/GCLK4 P122 GCLK
0 IO_L08N_0/VREF_0 IO_L08N_0/VREF_0 P135 VREF
0 IO_L08P_0 IO_L08P_0 P134 I/O
0 IO_L09N_0 IO_L09N_0 P140 I/O

0 IO_L09P_0 IO_L09P_0 P139 I/O
0 IO_L10N_0/HSWAP IO_L10N_0/HSWAP P143 DUAL
0 IO_L10P_0 IO_L10P_0 P142 I/O
0 IP IP P111 INPUT
0 IP IP P114 INPUT
0 IP IP P136 INPUT
0 IP IP P141 INPUT
0 IP_L03N_0 IP_L03N_0 P120 INPUT
0 IP_L03P_0 IP_L03P_0 P119 INPUT
0 IP_L06N_0/GCLK9 IP_L06N_0/GCLK9 P129 GCLK
0 IP_L06P_0/GCLK8 IP_L06P_0/GCLK8 P128 GCLK

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Pinout Descriptions
Table 12: TQ144 Package Pinout (Continued)

0 VCCO_0 VCCO_0 P121 VCCO
1 IO/A0 IO/A0 P98 DUAL

1 IO/VREF_1 IO/VREF_1 P83 VREF
1 IO_L01N_1/A15 IO_L01N_1/A15 P75 DUAL
1 IO_L01P_1/A16 IO_L01P_1/A16 P74 DUAL
1 IO_L04N_1/A9/RHCLK1 IO_L04N_1/A9/RHCLK1 P86 RHCLK/DUAL

1 IO_L04P_1/A10/RHCLK0 IO_L04P_1/A10/RHCLK0 P85 RHCLK/DUAL
1 IO_L05N_1/A7/RHCLK3/TRDY1 IO_L05N_1/A7/RHCLK3 P88 RHCLK/DUAL
1 IO_L06P_1/A6/RHCLK4/IRDY1 IO_L06P_1/A6/RHCLK4 P91 RHCLK/DUAL
1 IO_L09N_1/LDC0 IO_L09N_1/LDC0 P104 DUAL
1 IO_L09P_1/HDC IO_L09P_1/HDC P103 DUAL
1 IO_L10N_1/LDC2 IO_L10N_1/LDC2 P106 DUAL
1 IO_L10P_1/LDC1 IO_L10P_1/LDC1 P105 DUAL
1 IP IP P78 INPUT
1 IP IP P84 INPUT
1 IP IP P89 INPUT
1 IP IP P101 INPUT
1 IP IP P107 INPUT
1 IP/VREF_1 IP/VREF_1 P95 VREF
2 IO/D5 IO/D5 P52 DUAL
2 IO/M1 IO/M1 P60 DUAL
2 IP/VREF_2 IO/VREF_2 P66 100E: VREF(INPUT)

250E: VREF(I/O)

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Pinout Descriptions

2 IO_L01N_2/INIT_B IO_L01N_2/INIT_B P40 DUAL
2 IO_L01P_2/CSO_B IO_L01P_2/CSO_B P39 DUAL
2 IO_L02N_2/MOSI/CSI_B IO_L02N_2/MOSI/CSI_B P44 DUAL

2 IO_L02P_2/DOUT/BUSY IO_L02P_2/DOUT/BUSY P43 DUAL
2 IO_L04N_2/D6/GCLK13 IO_L04N_2/D6/GCLK13 P51 DUAL/GCLK
2 IO_L04P_2/D7/GCLK12 IO_L04P_2/D7/GCLK12 P50 DUAL/GCLK
2 IO_L08N_2/DIN/D0 IO_L08N_2/DIN/D0 P63 DUAL

2 IO_L08P_2/M0 IO_L08P_2/M0 P62 DUAL
2 IO_L09N_2/VS1/A18 IO_L09N_2/VS1/A18 P68 DUAL
2 IO_L09P_2/VS2/A19 IO_L09P_2/VS2/A19 P67 DUAL
2 IO_L10N_2/CCLK IO_L10N_2/CCLK P71 DUAL
2 IO_L10P_2/VS0/A17 IO_L10P_2/VS0/A17 P70 DUAL
2 IP IP P38 INPUT
2 IP IP P41 INPUT
2 IP IP P69 INPUT
2 IP_L03N_2/VREF_2 IP_L03N_2/VREF_2 P48 VREF
2 IP_L03P_2 IP_L03P_2 P47 INPUT
2 IP_L06N_2/M2/GCLK1 IP_L06N_2/M2/GCLK1 P57 DUAL/GCLK
2 IP_L06P_2/RDWR_B/GCLK0 IP_L06P_2/RDWR_B/GCLK0 P56 DUAL/GCLK

3 IP/VREF_3 IO/VREF_3 P31 100E: VREF(INPUT)

250E: VREF(I/O)
3 IO_L01N_3 IO_L01N_3 P3 I/O
3 IO_L01P_3 IO_L01P_3 P2 I/O
3 IO_L02N_3/VREF_3 IO_L02N_3/VREF_3 P5 VREF
3 IO_L02P_3 IO_L02P_3 P4 I/O

3 IO_L03N_3 IO_L03N_3 P8 I/O
3 IO_L03P_3 IO_L03P_3 P7 I/O
3 IO_L04N_3/LHCLK1 IO_L04N_3/LHCLK1 P15 LHCLK
3 IO_L04P_3/LHCLK0 IO_L04P_3/LHCLK0 P14 LHCLK

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Pinout Descriptions

3 IO_L05N_3/LHCLK3/IRDY2 IO_L05N_3/LHCLK3 P17 LHCLK

3 IO_L06P_3/LHCLK4/TRDY2 IO_L06P_3/LHCLK4 P20 LHCLK
3 IO_L08N_3 IO_L08N_3 P26 I/O
3 IO_L08P_3 IO_L08P_3 P25 I/O
3 IO_L09N_3 IO_L09N_3 P33 I/O
3 IO_L09P_3 IO_L09P_3 P32 I/O
3 IO_L10N_3 IO_L10N_3 P35 I/O

3 IO_L10P_3 IO_L10P_3 P34 I/O
3 IP IP P6 INPUT
3 IO IP P10 100E: I/O

250E: INPUT
3 IP IP P18 INPUT
3 IP IP P24 INPUT
3 IO IP P29 100E: I/O

250E: INPUT
3 IP IP P36 INPUT
3 IP/VREF_3 IP/VREF_3 P12 VREF
GND GND GND P11 GND
GND GND GND P19 GND
GND GND GND P27 GND
GND GND GND P37 GND
GND GND GND P46 GND
GND GND GND P55 GND
GND GND GND P61 GND
GND GND GND P73 GND
GND GND GND P90 GND
GND GND GND P99 GND
GND GND GND P118 GND

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Pinout Descriptions

VCCAUX DONE DONE P72 CONFIG
VCCAUX PROG_B PROG_B P1 CONFIG
VCCAUX TCK TCK P110 JTAG

VCCAUX TDI TDI P144 JTAG
VCCAUX TDO TDO P109 JTAG
VCCAUX TMS TMS P108 JTAG
VCCAUX VCCAUX VCCAUX P30 VCCAUX
VCCINT VCCINT VCCINT P9 VCCINT

User I/Os by Bank

Table 13 and Table 14 indicate how the 108 available
user-I/O pins are distributed between the four I/O banks on
the TQ144 package.
Table 13: User I/Os Per Bank for the XC3S100E in the TQ144 Package
Package Maximum
Top 0 26 9 6 1 2 8
Right 1 28 0 5 21 2 0
Bottom 2 26 0 4 20 2 0
Left 3 28 13 4 0 3 8
TOTAL 108 22 19 42 9 16
Table 14: User I/Os Per Bank for the XC3S250E in TQ144 Package
Package Maximum
Top 0 26 9 6 1 2 8
Right 1 28 0 5 21 2 0
Bottom 2 26 0 4 20 2 0
Left 3 28 11 6 0 3 8
TOTAL 108 20 21 42 9 16

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Pinout Descriptions
Footprint Migration Differences The arrows indicate the direction for easy migration. For
example, a left-facing arrow indicates that the pin on the
Table 15 summarizes any footprint and functionality differ-
XC3S250E unconditionally migrates to the pin on the
ences between the XC3S100E and the XC3S250E FPGAs
XC3S100E. It may be possible to migrate the opposite
that may affect easy migration between devices. There are
direction depending on the I/O configuration. For example,
four such pins. All other pins not listed in Table 15 uncondi-
an I/O pin (Type = I/O) can migrate to an input-only pin
tionally migrate between Spartan-3E devices available in
(Type = INPUT) if the I/O pin is configured as an input.
the TQ144 package.
Table 15: TQ144 Footprint Migration Differences

TQ144 Pin Bank XC3S100E Type Migration XC3S250E Type
P10 3 I/O INPUT
P29 3 I/O INPUT
P31 3 VREF(INPUT) VREF(I/O)
P66 2 VREF(INPUT) VREF(I/O)
DIFFERENCES 4
Legend:
This pin can unconditionally migrate from the device on the left to the device on the right. Migration in the other direction may be
possible depending on how the pin is configured for the device on the right.
This pin can unconditionally migrate from the device on the right to the device on the left. Migration in the other direction may be
possible depending on how the pin is configured for the device on the left.
The pinout changed slightly between the XC3S100E engi- Table 16: XC3S100E Pinout Changes between
neering samples and the production devices, as shown in Production Devices and Engineering Samples
Table 16. In the engineering samples, the mode select pins
M1 and M0 overlap with two global clock inputs feeding the XC3S100E XC3S100E
bottom edge global buffers and DCMs. In the production Production Engineering
devices, the mode pins are swapped with parallel mode TQ144 Pin Devices Samples
data pins, D1 and D2. This way, these two mode pins do not P58 D2/GCLK2 M1/GCLK2
interfere with global clock inputs.
P59 D1/GCLK3 M0/GCLK3
P60 M1 D2
P62 M0 D1

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Pinout Descriptions
TQ144 Footprint between the XC3S100E and XC3S250E. Engineering sam-

ple footprint is slightly different.
Note pin 1 indicator in top-left corner and logo orientation.
Double arrows ( ) indicates a pinout migration difference
131 IO_L07N_0/GCLK11
135 IO_L08N_0/VREF_0
130 IO_L07P_0/GCLK10
143 IO_L10N_0/HSWAP
126 IO_L05N_0/GCLK7
123 IO_L04N_0/GCLK5
125 IO_L05P_0/GCLK6
122 IO_L04P_0/GCLK4
129 IP_L06N_0/GCLK9
128 IP_L06P_0/GCLK8
140 IO_L09N_0
117 IO_L02N_0
113 IO_L01N_0
124 IO/VREF_0
142 IO_L10P_0
139 IO_L09P_0
134 IO_L08P_0
116 IO_L02P_0
112 IO_L01P_0
120 IP_L03N_0
119 IP_L03P_0
137 VCCAUX
138 VCCO_0
121 VCCO_0
115 VCCINT
133 GND
127 GND
118 GND
109 TDO
110 TCK
144 TDI
132 IO
141 IP
136 IP
114 IP
111 IP
PROG_B 1 108 TMS
IO_L01P_3 2 Bank 0 107 IP
IO_L01N_3 3 106 IO_L10N_1/LDC2
IO_L02P_3 4 105 IO_L10P_1/LDC1
IO_L02N_3/VREF_3 5 104 IO_L09N_1/LDC0
IP 6 103 IO_L09P_1/HDC
IO_L03P_3 7 102 VCCAUX
IO_L03N_3 8 101 IP
VCCINT 9 100 VCCO_1
( ) IP 10 99 GND
GND 11 98 IO/A0
IP/VREF_3 12 97 IO_L08N_1/A1
VCCO_3 13 96 IO_L08P_1/A2
IO_L04P_3/LHCLK0 14 95 IP/VREF_1
IO_L04N_3/LHCLK1 15 94 IO_L07N_1/A3/RHCLK7
IO_L05P_3/LHCLK2 16 93 IO_L07P_1/A4/RHCLK6
Bank 1
Bank 3
IP 18 91 IO_L06P_1/A6/RHCLK4
GND 19 90 GND
IO_L06P_3/LHCLK4 20 89 IP
IO_L07P_3/LHCLK6 22 87 IO_L05P_1/A8/RHCLK2
IP 24 85 IO_L04P_1/A10/RHCLK0
IO_L08P_3 25 84 IP
IO_L08N_3 26 83 IO/VREF_1
GND 27 82 IO_L03N_1/A11
VCCO_3 28 81 IO_L03P_1/A12
( ) IP 29 80 VCCINT
VCCAUX 30 79 VCCO_1
( ) IO/VREF_3 31 78 IP
IO_L09P_3 32 77 IO_L02N_1/A13
IO_L09N_3 33 76 IO_L02P_1/A14
IO_L10P_3 34 75 IO_L01N_1/A15
IO_L10N_3 35 74 IO_L01P_1/A16
IP 36 Bank 2 73 GND
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
GND
VCCINT
GND
GND
GND
IP_L03P_2
IP
IO_L01P_2/CSO_B
IO_L01N_2/INIT_B
IP
VCCO_2
IO_L02P_2/DOUT/BUSY
VCCO_2
IP_L03N_2/VREF_2
IO_L04P_2/D7/GCLK12
IO_L04N_2/D6/GCLK13
IO/D5
IO_L05P_2/D4/GCLK14
IO_L05N_2/D3/GCLK15
IP_L06N_2/M2/GCLK1
IO_L07P_2/D2/GCLK2
IO_L07N_2/D1/GCLK3
IO/M1
IO_L08P_2/M0
IO_L08N_2/DIN/D0
VCCO_2
VCCAUX
) IO/VREF_2
IO_L09P_2/VS2/A19
IO_L09N_2/VS1/A18
IP
IO_L10P_2/VS0/A17
IO_L10N_2/CCLK
DONE
(
DS312-4_01_030705
Figure 4: TQ144 Package Production Footprint (top view)
42 possible user I/O
9 for bank
4 pins
4 voltage (+1.2V)

0 13 4 voltage (+2.5V)

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Pinout Descriptions
PQ208: 208-pin Plastic Quad Flat Table 17: PQ208 Package Pinout
Package XC3S250E
XC3S500E PQ208
The 208-pin plastic quad flat package, PQ208, supports two
Bank Pin Name Pin Type
different Spartan-3E FPGAs, including the XC3S250E and
the XC3S500E. 0 IO_L13P_0 P196 I/O
Table 17 lists all the PQ208 package pins. They are sorted 0 IO_L14N_0/VREF_0 P200 VREF
by bank number and then by pin name. Pairs of pins that
form a differential I/O pair appear together in the table. The 0 IO_L14P_0 P199 I/O
table also shows the pin number for each pin and the pin 0 IO_L15N_0 P203 I/O
type, as defined earlier.
0 IO_L15P_0 P202 I/O
print diagram is available for download from the Xilinx web- 0 IO_L16N_0/HSWAP P206 DUAL
site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip. 0 IO_L16P_0 P205 I/O
Pinout Table 0 IP P159 INPUT
0 IP P169 INPUT
Table 17: PQ208 Package Pinout 0 IP P194 INPUT
XC3S250E
0 IP P204 INPUT
XC3S500E PQ208
Bank Pin Name Pin Type 0 IP_L06N_0 P175 INPUT
0 IO P187 I/O 0 IP_L06P_0 P174 INPUT
0 IO/VREF_0 P179 VREF 0 IP_L09N_0/GCLK9 P184 GCLK
0 IO_L01N_0 P161 I/O 0 IP_L09P_0/GCLK8 P183 GCLK
0 IO_L01P_0 P160 I/O 0 VCCO_0 P176 VCCO
0 IO_L02N_0/VREF_0 P163 VREF 0 VCCO_0 P191 VCCO
0 IO_L03N_0 P165 I/O 1 IO_L01N_1/A15 P107 DUAL
0 IO_L03P_0 P164 I/O 1 IO_L01P_1/A16 P106 DUAL
0 IO_L04N_0/VREF_0 P168 VREF 1 IO_L02N_1/A13 P109 DUAL
0 IO_L04P_0 P167 I/O 1 IO_L02P_1/A14 P108 DUAL
0 IO_L05N_0 P172 I/O 1 IO_L03N_1/VREF_1 P113 VREF
0 IO_L05P_0 P171 I/O 1 IO_L03P_1 P112 I/O
0 IO_L07N_0/GCLK5 P178 GCLK 1 IO_L04N_1 P116 I/O
0 IO_L07P_0/GCLK4 P177 GCLK 1 IO_L04P_1 P115 I/O
0 IO_L08N_0/GCLK7 P181 GCLK 1 IO_L05N_1/A11 P120 DUAL
0 IO_L08P_0/GCLK6 P180 GCLK 1 IO_L05P_1/A12 P119 DUAL
0 IO_L10N_0/GCLK11 P186 GCLK 1 IO_L06N_1/VREF_1 P123 VREF
0 IO_L10P_0/GCLK10 P185 GCLK 1 IO_L06P_1 P122 I/O
0 IO_L11N_0 P190 I/O 1 IO_L07N_1/A9/RHCLK1 P127 RHCLK/DUAL
0 IO_L11P_0 P189 I/O 1 IO_L07P_1/A10/RHCLK0 P126 RHCLK/DUAL
0 IO_L12N_0/VREF_0 P193 VREF 1 IO_L08N_1/A7/RHCLK3 P129 RHCLK/DUAL
0 IO_L12P_0 P192 I/O 1 IO_L08P_1/A8/RHCLK2 P128 RHCLK/DUAL
0 IO_L13N_0 P197 I/O

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Pinout Descriptions
Table 17: PQ208 Package Pinout Table 17: PQ208 Package Pinout
XC3S250E XC3S250E
XC3S500E PQ208 XC3S500E PQ208
Bank Pin Name Pin Type Bank Pin Name Pin Type
1 IO_L09N_1/A5/RHCLK5 P133 RHCLK/DUAL 2 IO_L04N_2 P63 I/O
1 IO_L09P_1/A6/RHCLK4 P132 RHCLK/DUAL 2 IO_L04P_2 P62 I/O
1 IO_L10N_1/A3/RHCLK7 P135 RHCLK/DUAL 2 IO_L05N_2 P65 I/O
1 IO_L10P_1/A4/RHCLK6 P134 RHCLK/DUAL 2 IO_L05P_2 P64 I/O
1 IO_L11N_1/A1 P138 DUAL 2 IO_L06N_2 P69 I/O
1 IO_L11P_1/A2 P137 DUAL 2 IO_L06P_2 P68 I/O
1 IO_L12N_1/A0 P140 DUAL 2 IO_L08N_2/D6/GCLK13 P75 DUAL/GCLK
1 IO_L12P_1 P139 I/O 2 IO_L08P_2/D7/GCLK12 P74 DUAL/GCLK
1 IO_L13N_1 P145 I/O 2 IO_L09N_2/D3/GCLK15 P78 DUAL/GCLK
1 IO_L14N_1 P147 I/O 2 IO_L11N_2/D1/GCLK3 P83 DUAL/GCLK
1 IO_L15N_1/LDC0 P151 DUAL 2 IO_L12N_2/DIN/D0 P87 DUAL
1 IO_L15P_1/HDC P150 DUAL 2 IO_L12P_2/M0 P86 DUAL
1 IO_L16N_1/LDC2 P153 DUAL 2 IO_L13N_2 P90 I/O
1 IO_L16P_1/LDC1 P152 DUAL 2 IO_L13P_2 P89 I/O
1 IP P110 INPUT 2 IO_L14N_2/A22 P94 DUAL
1 IP P118 INPUT 2 IO_L14P_2/A23 P93 DUAL
1 IP P124 INPUT 2 IO_L15N_2/A20 P97 DUAL
1 IP P130 INPUT 2 IO_L15P_2/A21 P96 DUAL
1 IP P142 INPUT 2 IO_L16N_2/VS1/A18 P100 DUAL
1 IP P148 INPUT 2 IO_L16P_2/VS2/A19 P99 DUAL
1 IP P154 INPUT 2 IO_L17N_2/CCLK P103 DUAL
1 IP/VREF_1 P136 VREF 2 IO_L17P_2/VS0/A17 P102 DUAL
1 VCCO_1 P114 VCCO 2 IP P54 INPUT
2 IO/D5 P76 DUAL 2 IP_L02N_2 P58 INPUT
2 IO/M1 P84 DUAL 2 IP_L02P_2 P57 INPUT
2 IO/VREF_2 P98 VREF 2 IP_L07N_2/VREF_2 P72 VREF
2 IO_L01N_2/INIT_B P56 DUAL 2 IP_L07P_2 P71 INPUT
2 IO_L01P_2/CSO_B P55 DUAL 2 IP_L10N_2/M2/GCLK1 P81 DUAL/GCLK
2 IO_L03N_2/MOSI/CSI_B P61 DUAL 2 IP_L10P_2/RDWR_B/ P80 DUAL/GCLK

GCLK0
2 IO_L03P_2/DOUT/BUSY P60 DUAL
2 VCCO_2 P59 VCCO

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Pinout Descriptions
XC3S250E XC3S250E
2 VCCO_2 P73 VCCO 3 IO_L16P_3 P49 I/O
3 IO/VREF_3 P45 VREF 3 IP P14 INPUT
3 IO_L01N_3 P3 I/O 3 IP P26 INPUT
3 IO_L01P_3 P2 I/O 3 IP P32 INPUT
3 IO_L02N_3/VREF_3 P5 VREF 3 IP P43 INPUT
3 IO_L03N_3 P9 I/O 3 IP/VREF_3 P20 VREF
3 IO_L04N_3 P12 I/O 3 VCCO_3 P38 VCCO
3 IO_L05N_3 P16 I/O GND GND P10 GND
3 IO_L05P_3 P15 I/O GND GND P17 GND
3 IO_L07N_3/LHCLK1 P23 LHCLK GND GND P52 GND
3 IO_L07P_3/LHCLK0 P22 LHCLK GND GND P53 GND
3 IO_L15N_3 P48 I/O VCCAUX DONE P104 CONFIG
3 IO_L15P_3 P47 I/O VCCAUX PROG_B P1 CONFIG
3 IO_L16N_3 P50 I/O VCCAUX TCK P158 JTAG

R
Pinout Descriptions
XC3S250E XC3S250E
VCCAUX TDI P207 JTAG VCCINT VCCINT P67 VCCINT
VCCAUX TDO P157 JTAG VCCINT VCCINT P117 VCCINT
VCCAUX TMS P155 JTAG VCCINT VCCINT P170 VCCINT

User I/Os by Bank
VCCAUX VCCAUX P66 VCCAUX distributed between the four I/O banks on the PQ208 pack-
VCCAUX VCCAUX P92 VCCAUX age.
VCCAUX VCCAUX P111 VCCAUX Footprint Migration Differences

VCCAUX VCCAUX P149 VCCAUX The XC3S250E and XC3S500E FPGAs have identical foot-
prints in the PQ208 package. Designs can migrate between
the XC3S250E and XC3S500E without further consider-
VCCAUX VCCAUX P195 VCCAUX ation.
Table 18: User I/Os Per Bank for the XC3S250E and XC3S500E in the PQ208 Package
Package Maximum
Top 0 38 18 6 1 5 8
Right 1 40 9 7 21 3 0
Bottom 2 40 8 6 24 2 0
Left 3 40 23 6 0 3 8
TOTAL 158 58 25 46 13 16

R
Pinout Descriptions
PQ208 Footprint (Left)
186 IO_L10N_0/GCLK11
185 IO_L10P_0/GCLK10
IO_L16N_0/HSWAP
184 IP_L09N_0/GCLK9
183 IP_L09P_0/GCLK8
203 IO_L15N_0
197 IO_L13N_0
190 IO_L11N_0
IO_L16P_0
202 IO_L15P_0
199 IO_L14P_0
196 IO_L13P_0
192 IO_L12P_0
189 IO_L11P_0
195 VCCAUX
201 VCCO_0
191 VCCO_0
GND
198 GND
188 GND
182 GND
TDI
187 IO
IP
194 IP
208
207
206
205
204
PROG_B 1
IO_L01P_3 2 Bank 0
IO_L01N_3 3
IO_L02P_3 4
IO_L02N_3/VREF_3 5
IP 6
VCCAUX 7
IO_L03P_3 8
IO_L03N_3 9
GND 10
IO_L04P_3 11
IO_L04N_3 12
VCCINT 13
IP 14
IO_L05P_3 15
IO_L05N_3 16
GND 17
IO_L06P_3 18
IO_L06N_3 19
IP/VREF_3 20
VCCO_3 21
IO_L07P_3/LHCLK0 22
IO_L07N_3/LHCLK1 23
IO_L08P_3/LHCLK2 24
Bank 3
IO_L08N_3/LHCLK3 25
IP 26
GND 27
IO_L09P_3/LHCLK4 28
IO_L09N_3/LHCLK5 29
IO_L10P_3/LHCLK6 30
IO_L10N_3/LHCLK7 31
IP 32
IO_L11P_3 33
IO_L11N_3 34
IO_L12P_3 35
IO_L12N_3 36
GND 37
VCCO_3 38
IO_L13P_3 39
IO_L13N_3 40
IO_L14P_3 41
IO_L14N_3 42
IP 43
VCCAUX 44
IO/VREF_3 45
VCCO_3 46
IO_L15P_3 47
IO_L15N_3 48
IO_L16P_3 49
IO_L16N_3 50
IP 51
GND 52 Bank 2
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
GND
IP_L02P_2
IP_L02N_2
VCCO_2
IO_L04P_2
IO_L04N_2
IO_L05P_2
IO_L05N_2
IO_L06P_2
IO_L06N_2
GND
IP_L07P_2
IP_L07N_2/VREF_2
VCCO_2
IO_L08P_2/D7/GCLK12
IO_L08N_2/D6/GCLK13
IO/D5
IO_L09P_2/D4/GCLK14
IO_L09N_2/D3/GCLK15
GND
VCCINT
IP
IO_L01P_2/CSO_B
IO_L01N_2/INIT_B
IO_L03P_2/DOUT/BUSY
VCCAUX
DS312-4_03_030705
Figure 5: PQ208 Footprint (Left)

R
Pinout Descriptions
PQ208 Footprint (Right)
IO_L04N_0/VREF_0
IO_L02N_0/VREF_0
181 IO_L08N_0/GCLK7
178 IO_L07N_0/GCLK5
180 IO_L08P_0/GCLK6
177 IO_L07P_0/GCLK4
179 IO/VREF_0
172 IO_L05N_0
IO_L03N_0
161 IO_L01N_0
IO_L05P_0
IO_L04P_0
IO_L03P_0
IO_L02P_0
160 IO_L01P_0
175 IP_L06N_0
174 IP_L06P_0
VCCAUX
176 VCCO_0
VCCINT
173 GND
157 TDO
158 TCK
IP
159 IP
171
170
169
168
167
166
165
164
163
162
156 GND
Bank 0 155 TMS
154 IP
153 IO_L16N_1/LDC2
152 IO_L16P_1/LDC1
151 IO_L15N_1/LDC0
150 IO_L15P_1/HDC
149 VCCAUX
148 IP
147 IO_L14N_1
146 IO_L14P_1
145 IO_L13N_1
144 IO_L13P_1
143 VCCO_1
142 IP
141 GND
140 IO_L12N_1/A0
139 IO_L12P_1
138 IO_L11N_1/A1
137 IO_L11P_1/A2
136 IP/VREF_1
135 IO_L10N_1/A3/RHCLK7
134 IO_L10P_1/A4/RHCLK6
Bank 1
131 GND
130 IP
126 IO_L07P_1/A10/RHCLK
125 VCCO_1
124 IP
122 IO_L06P_1
121 GND
120 IO_L05N_1/A11
119 IO_L05P_1/A12
118 IP
117 VCCINT
116 IO_L04N_1
115 IO_L04P_1
114 VCCO_1
112 IO_L03P_1
111 VCCAUX
110 IP
109 IO_L02N_1/A13
108 IO_L02P_1/A14
107 IO_L01N_1/A15
106 IO_L01P_1/A16
Bank 2 105 GND
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
IO_L16N_2/VS1/A18 100
IP 101
IO_L17P_2/VS0/A17 102
IO_L17N_2/CCLK 103
DONE 104
IO_L11P_2/D2/GCLK2
IP_L10N_2/M2/GCLK1
IO_L11N_2/D1/GCLK3
IO/M1
GND
IO_L12P_2/M0
IO_L12N_2/DIN/D0
VCCO_2
IO_L13P_2
IO_L13N_2
IO_L14P_2/A23
IO_L14N_2/A22
GND
IO_L15P_2/A21
IO_L15N_2/A20
IO/VREF_2
IO_L16P_2/VS2/A19
IP
VCCAUX
DS312-4_04_030705
Figure 6: PQ208 Footprint (Right)

R
Pinout Descriptions
FT256: 256-ball Fine-pitch, Thin Ball If the table row is highlighted in tan, then this is an instance
Grid Array where an unconnected pin on the XC3S250E FPGA maps
to a VREF pin on the XC3S500E and XC3S1200E FPGA. If
The 256-lead fine-pitch, thin ball grid array package, FT256, the FPGA application uses an I/O standard that requires a
supports three different Spartan-3E FPGAs, including the VREF voltage reference, connect the highlighted pin to the
XC3S250E, the XC3S500E, and the XC3S1200E. VREF voltage supply, even though this does not actually
Table 19 lists all the package pins. They are sorted by bank connect to the XC3S250E FPGA. This VREF connection on
number and then by pin name of the largest device. Pins the board allows future migration to the larger devices with-
that form a differential I/O pair appear together in the table. out modifying the printed-circuit board.
The table also shows the pin number for each pin and the All other balls have nearly identical functionality on all three
pin type, as defined earlier. devices. Table 23 summarizes the Spartan-3E footprint
The highlighted rows indicate pinout differences between migration differences for the FT256 package.
the XC3S250E, the XC3S500E, and the XC3S1200E An electronic version of this package pinout table and foot-
FPGAs. The XC3S250E has 18 unconnected balls, indi- print diagram is available for download from the Xilinx web
cated as N.C. (No Connection) in Table 19 and with the site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
black diamond character ( ) in both Table 19 and in
Figure 7. Pinout Table
Table 19: FT256 Package Pinout

FT256
Bank XC3S250E Pin Name XC3S500E Pin Name XC3S1200E Pin Name Ball Type
0 IO IO IO A7 I/O
0 IO IO IO A12 I/O
0 IO IO IO B4 I/O
0 IP IP IO B6 250E: INPUT
500E: INPUT
1200E: I/O
0 IP IP IO B10 250E: INPUT
500E: INPUT
1200E: I/O
0 IO/VREF_0 IO/VREF_0 IO/VREF_0 D9 VREF
0 IO_L01N_0 IO_L01N_0 IO_L01N_0 A14 I/O

0 IO_L01P_0 IO_L01P_0 IO_L01P_0 B14 I/O
0 IO_L03N_0/VREF_0 IO_L03N_0/VREF_0 IO_L03N_0/VREF_0 A13 VREF
0 IO_L04N_0 IO_L04N_0 IO_L04N_0 E11 I/O
0 IO_L04P_0 IO_L04P_0 IO_L04P_0 D11 I/O
0 IO_L05N_0/VREF_0 IO_L05N_0/VREF_0 IO_L05N_0/VREF_0 B11 VREF
0 IO_L05P_0 IO_L05P_0 IO_L05P_0 C11 I/O
0 IO_L08N_0/GCLK5 IO_L08N_0/GCLK5 IO_L08N_0/GCLK5 F9 GCLK
0 IO_L08P_0/GCLK4 IO_L08P_0/GCLK4 IO_L08P_0/GCLK4 E9 GCLK
0 IO_L09N_0/GCLK7 IO_L09N_0/GCLK7 IO_L09N_0/GCLK7 A9 GCLK

R
Pinout Descriptions
Table 19: FT256 Package Pinout (Continued)

FT256
0 IO_L09P_0/GCLK6 IO_L09P_0/GCLK6 IO_L09P_0/GCLK6 A10 GCLK
0 IO_L11N_0/GCLK11 IO_L11N_0/GCLK11 IO_L11N_0/GCLK11 D8 GCLK
0 IO_L11P_0/GCLK10 IO_L11P_0/GCLK10 IO_L11P_0/GCLK10 C8 GCLK
0 IO_L12N_0 IO_L12N_0 IO_L12N_0 F8 I/O
0 IO_L12P_0 IO_L12P_0 IO_L12P_0 E8 I/O
0 N.C. ( ) IO_L13N_0 IO_L13N_0 C7 250E: N.C.

500E: I/O
1200E: I/O
0 N.C. ( ) IO_L13P_0 IO_L13P_0 B7 250E: N.C.
500E: I/O
1200E: I/O
0 IO_L14N_0/VREF_0 IO_L14N_0/VREF_0 IO_L14N_0/VREF_0 D7 VREF
0 IO_L15N_0 IO_L15N_0 IO_L15N_0 D6 I/O
0 IO_L17N_0/VREF_0 IO_L17N_0/VREF_0 IO_L17N_0/VREF_0 A4 VREF
0 IO_L17P_0 IO_L17P_0 IO_L17P_0 A5 I/O
0 IO_L18N_0 IO_L18N_0 IO_L18N_0 C4 I/O
0 IO_L19N_0/HSWAP IO_L19N_0/HSWAP IO_L19N_0/HSWAP B3 DUAL
0 IP IP IP A3 INPUT
0 IP IP IP C13 INPUT
0 IP_L02N_0 IP_L02N_0 IP_L02N_0 C12 INPUT
0 IP_L02P_0 IP_L02P_0 IP_L02P_0 D12 INPUT
0 IP_L07N_0 IP_L07N_0 IP_L07N_0 C9 INPUT
0 IP_L07P_0 IP_L07P_0 IP_L07P_0 C10 INPUT
0 IP_L10N_0/GCLK9 IP_L10N_0/GCLK9 IP_L10N_0/GCLK9 B8 GCLK
0 IP_L10P_0/GCLK8 IP_L10P_0/GCLK8 IP_L10P_0/GCLK8 A8 GCLK
0 IP_L16N_0 IP_L16N_0 IP_L16N_0 E6 INPUT
0 IP_L16P_0 IP_L16P_0 IP_L16P_0 D5 INPUT
0 VCCO_0 VCCO_0 VCCO_0 B5 VCCO
0 VCCO_0 VCCO_0 VCCO_0 B12 VCCO
0 VCCO_0 VCCO_0 VCCO_0 F7 VCCO
1 IO_L01N_1/A15 IO_L01N_1/A15 IO_L01N_1/A15 R15 DUAL

R
Pinout Descriptions

FT256
1 IO_L01P_1/A16 IO_L01P_1/A16 IO_L01P_1/A16 R16 DUAL
1 IO_L02N_1/A13 IO_L02N_1/A13 IO_L02N_1/A13 P15 DUAL
1 IO_L02P_1/A14 IO_L02P_1/A14 IO_L02P_1/A14 P16 DUAL
1 N.C. ( ) IO_L03N_1/VREF_1 IO_L03N_1/VREF_1 N15 250E: N.C.

500E: VREF
1200E: VREF
1 N.C. ( ) IO_L03P_1 IO_L03P_1 N14 250E: N.C.
500E: I/O
1200E: I/O
1 IO_L04N_1/VREF_1 IO_L04N_1/VREF_1 IO_L04N_1/VREF_1 M16 VREF
1 IO_L04P_1 IO_L04P_1 IO_L04P_1 N16 I/O
1 N.C. ( ) IO_L05N_1 IO_L05N_1 L13 250E: N.C.

500E: I/O
1200E: I/O
1 N.C. ( ) IO_L05P_1 IO_L05P_1 L12 250E: N.C.
500E: I/O
1200E: I/O
1 IO_L06N_1 IO_L06N_1 IO_L06N_1 L15 I/O
1 IO_L06P_1 IO_L06P_1 IO_L06P_1 L14 I/O
1 IO_L07N_1/A11 IO_L07N_1/A11 IO_L07N_1/A11 K12 DUAL
1 IO_L07P_1/A12 IO_L07P_1/A12 IO_L07P_1/A12 K13 DUAL
1 IO_L08N_1/VREF_1 IO_L08N_1/VREF_1 IO_L08N_1/VREF_1 K14 VREF
1 IO_L08P_1 IO_L08P_1 IO_L08P_1 K15 I/O
1 IO_L09N_1/A9/RHCLK1 IO_L09N_1/A9/RHCLK1 IO_L09N_1/A9/RHCLK1 J16 RHCLK/DUAL
1 IO_L09P_1/A10/RHCLK0 IO_L09P_1/A10/RHCLK0 IO_L09P_1/A10/RHCLK0 K16 RHCLK/DUAL

1 IO_L10N_1/A7/RHCLK3/ IO_L10N_1/A7/RHCLK3/ IO_L10N_1/A7/RHCLK3/ J13 RHCLK/DUAL
TRDY1 TRDY1 TRDY1
1 IO_L10P_1/A8/RHCLK2 IO_L10P_1/A8/RHCLK2 IO_L10P_1/A8/RHCLK2 J14 RHCLK/DUAL
1 IO_L11N_1/A5/RHCLK5 IO_L11N_1/A5/RHCLK5 IO_L11N_1/A5/RHCLK5 H14 RHCLK/DUAL
1 IO_L11P_1/A6/RHCLK4/ IO_L11P_1/A6/RHCLK4/ IO_L11P_1/A6/RHCLK4/ H15 RHCLK/DUAL

IRDY1 IRDY1 IRDY1
1 IO_L12N_1/A3/RHCLK7 IO_L12N_1/A3/RHCLK7 IO_L12N_1/A3/RHCLK7 H11 RHCLK/DUAL
1 IO_L12P_1/A4/RHCLK6 IO_L12P_1/A4/RHCLK6 IO_L12P_1/A4/RHCLK6 H12 RHCLK/DUAL
1 IO_L13N_1/A1 IO_L13N_1/A1 IO_L13N_1/A1 G16 DUAL
1 IO_L13P_1/A2 IO_L13P_1/A2 IO_L13P_1/A2 G15 DUAL
1 IO_L14N_1/A0 IO_L14N_1/A0 IO_L14N_1/A0 G14 DUAL
1 IO_L14P_1 IO_L14P_1 IO_L14P_1 G13 I/O

R
Pinout Descriptions

FT256
1 IO_L15P_1 IO_L15P_1 IO_L15P_1 F14 I/O
1 N.C. ( ) IO_L17N_1 IO_L17N_1 E16 250E: N.C.

500E: I/O
1200E: I/O
1 N.C. ( ). IO_L17P_1 IO_L17P_1 E13 250E: N.C.
500E: I/O
1200E: I/O
1 IO_L18N_1/LDC0 IO_L18N_1/LDC0 IO_L18N_1/LDC0 D14 DUAL
1 IO_L18P_1/HDC IO_L18P_1/HDC IO_L18P_1/HDC D15 DUAL
1 IO_L19N_1/LDC2 IO_L19N_1/LDC2 IO_L19N_1/LDC2 C15 DUAL
1 IO_L19P_1/LDC1 IO_L19P_1/LDC1 IO_L19P_1/LDC1 C16 DUAL
1 IP IP IP B16 INPUT
1 IP IP IP E14 INPUT
1 IP IP IP G12 INPUT
1 IP IP IP H16 INPUT
1 IP IP IP J11 INPUT
1 IP IP IP J12 INPUT
1 IP IP IP M13 INPUT
1 IO IO IP M14 250E: I/O

500E: I/O
1200E: INPUT
1 IO/VREF_1 IP/VREF_1 IP/VREF_1 D16 250E: VREF(I/O)
500E:
VREF(INPUT)
1200E:
VREF(INPUT)
1 IP/VREF_1 IP/VREF_1 IP/VREF_1 H13 VREF
1 VCCO_1 VCCO_1 VCCO_1 E15 VCCO
1 VCCO_1 VCCO_1 VCCO_1 G11 VCCO
1 VCCO_1 VCCO_1 VCCO_1 K11 VCCO
1 VCCO_1 VCCO_1 VCCO_1 M15 VCCO
2 IP IP IO M7 250E: INPUT
500E: INPUT
1200E: I/O
2 IP IP IO T12 250E: INPUT
500E: INPUT
1200E: I/O

R
Pinout Descriptions

FT256
2 IO/D5 IO/D5 IO/D5 T8 DUAL
2 IO/M1 IO/M1 IO/M1 T10 DUAL
2 IO/VREF_2 IO/VREF_2 IO/VREF_2 P13 VREF
2 IO/VREF_2 IO/VREF_2 IO/VREF_2 R4 VREF
2 IO_L01N_2/INIT_B IO_L01N_2/INIT_B IO_L01N_2/INIT_B P4 DUAL
2 IO_L01P_2/CSO_B IO_L01P_2/CSO_B IO_L01P_2/CSO_B P3 DUAL
2 IO_L03N_2/MOSI/CSI_B IO_L03N_2/MOSI/CSI_B IO_L03N_2/MOSI/CSI_B N5 DUAL
2 IO_L03P_2/DOUT/BUSY IO_L03P_2/DOUT/BUSY IO_L03P_2/DOUT/BUSY P5 DUAL
2 IO_L04N_2 IO_L04N_2 IO_L04N_2 T5 I/O
2 IO_L04P_2 IO_L04P_2 IO_L04P_2 T4 I/O

2 IO_L05N_2 IO_L05N_2 IO_L05N_2 N6 I/O
2 IO_L05P_2 IO_L05P_2 IO_L05P_2 M6 I/O
2 IO_L06N_2 IO_L06N_2 IO_L06N_2 P6 I/O
2 IO_L06P_2 IO_L06P_2 IO_L06P_2 R6 I/O
2 N.C. ( ) IO_L07N_2 IO_L07N_2 P7 250E: N.C.

500E: I/O
1200E: I/O
2 N.C. ( ) IO_L07P_2 IO_L07P_2 N7 250E: N.C.
500E: I/O
1200E: I/O
2 IO_L09N_2/D6/GCLK13 IO_L09N_2/D6/GCLK13 IO_L09N_2/D6/GCLK13 L8 DUAL/GCLK
2 IO_L09P_2/D7/GCLK12 IO_L09P_2/D7/GCLK12 IO_L09P_2/D7/GCLK12 M8 DUAL/GCLK
2 IO_L10N_2/D3/GCLK15 IO_L10N_2/D3/GCLK15 IO_L10N_2/D3/GCLK15 P8 DUAL/GCLK
2 IO_L10P_2/D4/GCLK14 IO_L10P_2/D4/GCLK14 IO_L10P_2/D4/GCLK14 N8 DUAL/GCLK
2 IO_L12N_2/D1/GCLK3 IO_L12N_2/D1/GCLK3 IO_L12N_2/D1/GCLK3 N9 DUAL/GCLK
2 IO_L12P_2/D2/GCLK2 IO_L12P_2/D2/GCLK2 IO_L12P_2/D2/GCLK2 P9 DUAL/GCLK
2 IO_L13N_2/DIN/D0 IO_L13N_2/DIN/D0 IO_L13N_2/DIN/D0 M9 DUAL
2 IO_L13P_2/M0 IO_L13P_2/M0 IO_L13P_2/M0 L9 DUAL
2 N.C. ( ) IO_L14N_2/VREF_2 IO_L14N_2/VREF_2 R10 250E: N.C.

500E: VREF
1200E: VREF
2 N.C. ( ) IO_L14P_2 IO_L14P_2 P10 250E: N.C.
500E: I/O
1200E: I/O
2 IO_L15N_2 IO_L15N_2 IO_L15N_2 M10 I/O
2 IO_L16N_2/A22 IO_L16N_2/A22 IO_L16N_2/A22 P11 DUAL

R
Pinout Descriptions

FT256
2 IO_L18N_2/A20 IO_L18N_2/A20 IO_L18N_2/A20 N12 DUAL
2 IO_L19N_2/VS1/A18 IO_L19N_2/VS1/A18 IO_L19N_2/VS1/A18 R13 DUAL
2 IO_L19P_2/VS2/A19 IO_L19P_2/VS2/A19 IO_L19P_2/VS2/A19 T13 DUAL
2 IO_L20N_2/CCLK IO_L20N_2/CCLK IO_L20N_2/CCLK R14 DUAL
2 IO_L20P_2/VS0/A17 IO_L20P_2/VS0/A17 IO_L20P_2/VS0/A17 P14 DUAL
2 IP IP IP T2 INPUT
2 IP IP IP T14 INPUT
2 IP_L02N_2 IP_L02N_2 IP_L02N_2 R3 INPUT

2 IP_L02P_2 IP_L02P_2 IP_L02P_2 T3 INPUT
2 IP_L08N_2/VREF_2 IP_L08N_2/VREF_2 IP_L08N_2/VREF_2 T7 VREF
2 IP_L08P_2 IP_L08P_2 IP_L08P_2 R7 INPUT
2 IP_L11N_2/M2/GCLK1 IP_L11N_2/M2/GCLK1 IP_L11N_2/M2/GCLK1 R9 DUAL/GCLK
2 IP_L11P_2/RDWR_B/ IP_L11P_2/RDWR_B/ IP_L11P_2/RDWR_B/ T9 DUAL/GCLK

GCLK0 GCLK0 GCLK0
2 IP_L17N_2 IP_L17N_2 IP_L17N_2 M11 INPUT
2 IP_L17P_2 IP_L17P_2 IP_L17P_2 N11 INPUT
2 VCCO_2 VCCO_2 VCCO_2 L7 VCCO
2 VCCO_2 VCCO_2 VCCO_2 R5 VCCO
2 VCCO_2 VCCO_2 VCCO_2 R12 VCCO
3 IO_L01N_3 IO_L01N_3 IO_L01N_3 B2 I/O
3 IO_L02N_3/VREF_3 IO_L02N_3/VREF_3 IO_L02N_3/VREF_3 C2 VREF
3 N.C. ( ) IO_L04N_3/VREF_3 IO_L04N_3/VREF_3 F4 250E: N.C.

500E: VREF
1200E: VREF
3 N.C. ( ) IO_L04P_3 IO_L04P_3 F3 250E: N.C.
500E: I/O
1200E: I/O

R
Pinout Descriptions

FT256
3 IO_L06N_3 IO_L06N_3 IO_L06N_3 G4 I/O
3 IO_L08N_3/LHCLK1 IO_L08N_3/LHCLK1 IO_L08N_3/LHCLK1 H6 LHCLK
3 IO_L08P_3/LHCLK0 IO_L08P_3/LHCLK0 IO_L08P_3/LHCLK0 H5 LHCLK
3 IO_L09N_3/LHCLK3/ IO_L09N_3/LHCLK3/ IO_L09N_3/LHCLK3/ H4 LHCLK

IRDY2 IRDY2 IRDY2
3 IO_L09P_3/LHCLK2 IO_L09P_3/LHCLK2 IO_L09P_3/LHCLK2 H3 LHCLK
3 IO_L10N_3/LHCLK5 IO_L10N_3/LHCLK5 IO_L10N_3/LHCLK5 J3 LHCLK
3 IO_L10P_3/LHCLK4/ IO_L10P_3/LHCLK4/ IO_L10P_3/LHCLK4/ J2 LHCLK

TRDY2 TRDY2 TRDY2
3 IO_L11P_3/LHCLK6 IO_L11P_3/LHCLK6 IO_L11P_3/LHCLK6 J5 LHCLK
3 IO_L12N_3 IO_L12N_3 IO_L12N_3 K1 I/O
3 IO_L12P_3 IO_L12P_3 IO_L12P_3 J1 I/O
3 IO_L13N_3 IO_L13N_3 IO_L13N_3 K3 I/O
3 N.C. ( ) IO_L14N_3/VREF_3 IO_L14N_3/VREF_3 L2 250E: N.C.

500E: VREF
1200E: VREF
3 N.C. ( ) IO_L14P_3 IO_L14P_3 L3 250E: N.C.
500E: I/O
1200E: I/O
3 N.C. ( ) IO_L17N_3 IO_L17N_3 L4 250E: N.C.

500E: I/O
1200E: I/O
3 N.C. ( ) IO_L17P_3 IO_L17P_3 M4 250E: N.C.
500E: I/O
1200E: I/O
3 IO_L18P_3 IO_L18P_3 IO_L18P_3 P2 I/O
3 IO_L19N_3 IO_L19N_3 IO_L19N_3 R1 I/O

R
Pinout Descriptions

FT256
3 IP IP IP D2 INPUT
3 IP IP IP F2 INPUT
3 IO IO IP F5 250E: I/O
500E: I/O
1200E: INPUT
3 IP IP IP H1 INPUT
3 IP IP IP J6 INPUT
3 IP IP IP K4 INPUT
3 IP IP IP M3 INPUT
3 IP IP IP N3 INPUT
3 IP/VREF_3 IP/VREF_3 IP/VREF_3 G1 VREF
3 IO/VREF_3 IO/VREF_3 IP/VREF_3 N2 250E: VREF(I/O)

500E: VREF(I/O)
1200E:
VREF(INPUT)
3 VCCO_3 VCCO_3 VCCO_3 E2 VCCO
GND GND GND GND A1 GND
GND GND GND GND B9 GND
GND GND GND GND F6 GND
GND GND GND GND F11 GND
GND GND GND GND G7 GND

GND GND GND GND H2 GND
GND GND GND GND J7 GND

R
Pinout Descriptions

FT256
GND GND GND GND K7 GND
GND GND GND GND L6 GND
GND GND GND GND R8 GND
GND GND GND GND T1 GND

VCCAUX DONE DONE DONE T15 CONFIG
VCCAUX PROG_B PROG_B PROG_B D3 CONFIG
VCCAUX TCK TCK TCK A15 JTAG
VCCAUX TDI TDI TDI A2 JTAG
VCCAUX TDO TDO TDO C14 JTAG
VCCAUX TMS TMS TMS B15 JTAG
VCCAUX VCCAUX VCCAUX VCCAUX A6 VCCAUX
VCCAUX VCCAUX VCCAUX VCCAUX A11 VCCAUX
VCCAUX VCCAUX VCCAUX VCCAUX F1 VCCAUX
VCCAUX VCCAUX VCCAUX VCCAUX F16 VCCAUX
VCCAUX VCCAUX VCCAUX VCCAUX L1 VCCAUX
VCCAUX VCCAUX VCCAUX VCCAUX L16 VCCAUX
VCCAUX VCCAUX VCCAUX VCCAUX T6 VCCAUX
VCCAUX VCCAUX VCCAUX VCCAUX T11 VCCAUX
VCCINT VCCINT VCCINT VCCINT D4 VCCINT
VCCINT VCCINT VCCINT VCCINT D13 VCCINT
VCCINT VCCINT VCCINT VCCINT E5 VCCINT
VCCINT VCCINT VCCINT VCCINT M5 VCCINT
VCCINT VCCINT VCCINT VCCINT M12 VCCINT

VCCINT VCCINT VCCINT VCCINT N4 VCCINT

R
Pinout Descriptions
User I/Os by Bank The XC3S250E FPGA in the FT256 package has 18 uncon-
nected balls, labeled with an “N.C.” type. These pins are
Table 20, Table 21, and Table 22 indicate how the available
also indicated with the black diamond ( ) symbol in
Figure 7.
the FT256 package.
Table 20: User I/Os Per Bank on XC3S250E in the FT256 Package
Package Maximum
Top 0 44 20 10 1 5 8
Right 1 42 10 7 21 4 0
Bottom 2 44 8 9 24 3 0
Left 3 42 24 7 0 3 8
TOTAL 172 62 33 46 15 16
Package Maximum
Top 0 46 22 10 1 5 8
Right 1 48 15 7 21 5 0
Bottom 2 48 11 9 24 4 0
Left 3 48 28 7 0 5 8
TOTAL 190 76 33 46 19 16
Package Maximum
Top 0 46 24 8 1 5 8
Right 1 48 14 8 21 5 0
Bottom 2 48 13 7 24 4 0
Left 3 48 27 8 0 5 8
TOTAL 190 78 31 46 19 16

R
Pinout Descriptions
Footprint Migration Differences and the XC3S1200E. The arrows indicate the direction for
easy migration. A double-ended arrow ( ) indicates that
the two pins have identical functionality. A left-facing arrow
ences between the XC3S250E, the XC3S500E, and the
( ) indicates that the pin on the device on the right uncon-
XC3S1200E FPGAs that may affect easy migration
ditionally migrates to the pin on the device on the left. It may
between devices in the FG256 package. There are 26 such
be possible to migrate the opposite direction depending on
balls. All other pins not listed in Table 23 unconditionally
the I/O configuration. For example, an I/O pin (Type = I/O)
migrate between Spartan-3E devices available in the FT256
can migrate to an input-only pin (Type = INPUT) if the I/O
package.
pin is configured as an input.
The XC3S250E is duplicated on both the left and right sides
of the table to show migrations to and from the XC3S500E
Table 23: FT256 Footprint Migration Differences

FT256 XC3S250E XC3S500E XC3S1200E XC3S250E
Ball Bank Type Migration Type Migration Type Migration Type
B6 0 INPUT INPUT I/O INPUT
B7 0 N.C. I/O I/O N.C.
B10 0 INPUT INPUT I/O INPUT
C7 0 N.C. I/O I/O N.C.
D16 1 VREF(I/O) VREF(INPUT) VREF(INPUT) VREF(I/O)
E13 1 N.C. I/O I/O N.C.
E16 1 N.C. I/O I/O N.C.
F3 3 N.C. I/O I/O N.C.
F4 3 N.C. VREF VREF N.C.
F5 3 I/O I/O INPUT I/O
L2 3 N.C. VREF VREF N.C.
L3 3 N.C. I/O I/O N.C.
L4 3 N.C. I/O I/O N.C.
L12 1 N.C. I/O I/O N.C.
L13 1 N.C. I/O I/O N.C.
M4 3 N.C. I/O I/O N.C.
M7 2 INPUT INPUT I/O INPUT
M14 1 I/O I/O INPUT I/O
N2 3 VREF(I/O) VREF(I/O) VREF(INPUT) VREF(I/O)
N7 2 N.C. I/O I/O N.C.
N14 1 N.C. I/O I/O N.C.
N15 1 N.C. VREF VREF N.C.
P7 2 N.C. I/O I/O N.C.
P10 2 N.C. I/O I/O N.C.
R10 2 N.C. VREF VREF N.C.
T12 2 INPUT INPUT I/O INPUT
DIFFERENCES 19 7 26
Legend:
This pin is identical on both the device on the left and the right.
This pin can unconditionally migrate from the device on the left to the device on the right. Migration in the other direction may be possible
depending on how the pin is configured for the device on the right.
This pin can unconditionally migrate from the device on the right to the device on the left. Migration in the other direction may be possible
depending on how the pin is configured for the device on the left.

R
Pinout Descriptions
FT256 Footprint
Bank 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
I/O I/O
A GND TDI INPUT L17N_0
L17P_0
VCCAUX I/O L10P_0 L09N_0 L09P_0 VCCAUX I/O L03N_0
L01N_0
TCK GND
VREF_0 GCLK8 GCLK7 GCLK6 VREF_0
I/O I/O INPUT I/O

I/O I/O INPUT INPUT I/O I/O
B L01P_3 L01N_3
L19N_0 I/O VCCO_0 L13P_0 L10N_0 GND L05N_0 VCCO_0
L03P_0 L01P_0
TMS INPUT
HSWAP GCLK9 VREF_0
I/O I/O I/O I/O I/O

I/O I/O I/O I/O I/O L13N_0 INPUT INPUT I/O INPUT
C L02P_3
L02N_3
L19P_0 L18N_0 L18P_0 L15P_0
L11P_0
L07N_0 L07P_0 L05P_0 L02N_0
INPUT TDO L19N_1 L19P_1
VREF_3 GCLK10 LDC2 LDC1
I/O I/O I/O I/O INPUT

I/O INPUT I/O I/O I/O I/O INPUT
D L05P_3
INPUT PROG_B VCCINT
L16P_0 L15N_0
L14N_0 L11N_0
VREF_0 L06P_0 L04P_0 L02P_0
VCCINT L18N_1 L18P_1 VREF_1
VREF_0 GCLK11 LDC0 HDC
I/O I/O I/O

I/O I/O I/O INPUT I/O I/O I/O I/O
E L05N_3
VCCO_3
L03P_3 L03N_3
VCCINT
L16N_0 L14P_0 L12P_0
L08P_0
L06N_0 L04N_0
VCCINT L17P_1 INPUT VCCO_1 L17N_1
GCLK4
I/O I/O I/O

L04N_3 INPUT I/O I/O I/O I/O I/O
F VCCAUX INPUT L04P_3
VREF_3
GND VCCO_0
L12N_0
L08N_0 VCCO_0 GND
L16N_1 L16P_1 L15P_1 L15N_1
VCCAUX
GCLK5
I/O I/O I/O

INPUT I/O I/O I/O I/O I/O
G VREF_3 L07N_3 L07P_3 L06N_3 L06P_3
VCCO_3 GND GND GND GND VCCO_1 INPUT
L14P_1
L14N_1 L13P_1 L13N_1
A0 A2 A1
I/O I/O I/O I/O I/O I/O I/O I/O

L09N_3 L12N_1 L12P_1 INPUT L11N_1 L11P_1
H INPUT GND L09P_3 L08P_3 L08N_3 GND GND GND GND A6 INPUT
Bank 3
Bank 1
LHCLK3 A3 A4 VREF_1 A5 RHCLK4
LHCLK2 IRDY2 LHCLK0 LHCLK1 RHCLK7 RHCLK6 RHCLK5 IRDY1
I/O I/O I/O I/O
I/O I/O I/O L10N_1
I/O L10P_3 L10P_1 L09N_1
J L12P_3 LHCLK4
L10N_3 L11N_3 L11P_3 INPUT GND GND GND GND INPUT INPUT A7
A8
GND
A9
LHCLK5 LHCLK7 LHCLK6 RHCLK3
TRDY2 TRDY1 RHCLK2 RHCLK1
I/O I/O I/O I/O

I/O I/O I/O I/O I/O L09P_1
K L12N_3 L13P_3 L13N_3
INPUT
L15P_3
VCCO_3 GND GND GND GND VCCO_1 L07N_1 L07P_1 L08N_1
L08P_1 A10
A11 A12 VREF_1 RHCLK0
I/O I/O I/O I/O I/O I/O I/O
L14N_3 I/O L09N_2 I/O I/O
L VCCAUX
VREF_3
L14P_3 L17N_3
L15N_3
GND VCCO_2
D6
L13P_2 VCCO_2 GND L05P_1 L05N_1
L06P_1 L06N_1
VCCAUX
GCLK13 M0
I/O I/O I/O I/O
I/O I/O INPUT L09P_2 L13N_2 I/O INPUT INPUT
M L16P_3
VCCO_3 INPUT L17P_3 VCCINT
L05P_2 D7 DIN L15N_2 L17N_2
VCCINT INPUT VCCO_1 L04N_1
GCLK12 D0 VREF_1
INPUT I/O I/O I/O I/O I/O I/O I/O

I/O I/O I/O INPUT L03N_1 I/O
N VREF_3 INPUT VCCINT L03N_2 L07P_2 L10P_2 L12N_2 L18N_2 VCCINT L03P_1 VREF_1
L16N_3 MOSI L05N_2 D4 D1 L15P_2 L17P_2 L04P_1
CSI_B GCLK14 GCLK3 A20
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
I/O I/O L03P_2 I/O L10N_2 L12P_2 I/O L20P_2
P L18N_3 L18P_3
L01P_2 L01N_2
DOUT L06N_2
L07N_2
D3 D2
L14P_2 L16N_2 L18P_2
VREF_2 VS0
L02N_1 L02P_1
CSO_B INIT_B BUSY GCLK15 GCLK2 A22 A21 A17 A13 A14
INPUT I/O I/O I/O I/O I/O I/O

I/O I/O INPUT I/O I/O INPUT L11N_2 L14N_2 L19N_2
R L19N_3 L19P_3 L02N_2 VREF_2
VCCO_2
L06P_2 L08P_2
GND
M2 VREF_2 L16P_2 VCCO_2
VS1
L20N_2 L01N_1 L01P_1
GCLK1 A23 A18 CCLK A15 A16
INPUT INPUT INPUT I/O

INPUT I/O I/O I/O L11P_2 I/O L19P_2
T GND INPUT
L02P_2 L04P_2 L04N_2
VCCAUX L08N_2
D5 RDWR_B M1
VCCAUX
VS2
INPUT DONE GND
VREF_2 GCLK0 A19
Bank 2
DS312-4_05_021705
Figure 7: FT256 Package Footprint (top view)
4 pins
8 voltage (+1.2V)
GND: Ground VCCO: Output voltage supply VCCAUX: Auxiliary supply

28 16 for bank
8 voltage (+2.5V)
6 Migration Difference: For 18 Unconnected pins on

flexible package migration, XC3S250E
use these pins as inputs.

R
Pinout Descriptions
FG320: 320-ball Fine-pitch Ball Grid If the table row is highlighted in tan, then this is an instance
Array where an unconnected pin on the XC3S500E FPGA maps
to a VREF pin on the XC3S1200E and XC3S1600E FPGA.
The 320-lead fine-pitch ball grid array package, FG320, If the FPGA application uses an I/O standard that requires a
supports three different Spartan-3E FPGAs, including the VREF voltage reference, connect the highlighted pin to the
XC3S500E, the XC3S1200E, and the XC3S1600E, as VREF voltage supply, even though this does not actually
shown in Table 24 and Figure 8. connect to the XC3S500E FPGA. This VREF connection on
The FG320 package is an 18 x 18 array of solder balls the board allows future migration to the larger devices with-
minus the four center balls. out modifying the printed-circuit board.
Table 24 lists all the package pins. They are sorted by bank All other balls have nearly identical functionality on all three
number and then by pin name of the largest device. Pins devices. Table 23 summarizes the Spartan-3E footprint
that form a differential I/O pair appear together in the table. migration differences for the FG320 package.
The table also shows the pin number for each pin and the An electronic version of this package pinout table and foot-
pin type, as defined earlier. print diagram is available for download from the Xilinx web
The highlighted rows indicate pinout differences between site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
the XC3S500E, the XC3S1200E, and the XC3S1600E
FPGAs. The XC3S500E has 18 unconnected balls, indi- Pinout Table
cated as N.C. (No Connection) in Table 24 and with the
black diamond character ( ) in both Table 24 and in
Figure 8.
Table 24: FG320 Package Pinout

FG320
0 IP IO IO A7 500E: INPUT
1200E: I/O
1600E: I/O
0 IO IO IO A8 I/O
0 IO IO IO A11 I/O
0 IO IO IO C4 I/O
0 IP IO IO D13 500E: INPUT

1200E: I/O
1600E: I/O
0 IO IO IO E13 I/O
0 IO IO IO G9 I/O
0 IO/VREF_0 IO/VREF_0 IO/VREF_0 B11 VREF
0 IO_L03N_0/VREF_0 IO_L03N_0/VREF_0 IO_L03N_0/VREF_0 C14 VREF

0 IO_L05N_0/VREF_0 IO_L05N_0/VREF_0 IO_L05N_0/VREF_0 B13 VREF

R
Pinout Descriptions
Table 24: FG320 Package Pinout (Continued)

FG320
0 IO_L09N_0 IO_L09N_0 IO_L09N_0 D11 I/O
0 IO_L11N_0/GCLK5 IO_L11N_0/GCLK5 IO_L11N_0/GCLK5 E10 GCLK
0 IO_L11P_0/GCLK4 IO_L11P_0/GCLK4 IO_L11P_0/GCLK4 D10 GCLK
0 IO_L12N_0/GCLK7 IO_L12N_0/GCLK7 IO_L12N_0/GCLK7 A10 GCLK
0 IO_L12P_0/GCLK6 IO_L12P_0/GCLK6 IO_L12P_0/GCLK6 B10 GCLK
0 IO_L14N_0/GCLK11 IO_L14N_0/GCLK11 IO_L14N_0/GCLK11 D9 GCLK
0 IO_L14P_0/GCLK10 IO_L14P_0/GCLK10 IO_L14P_0/GCLK10 C9 GCLK

0 IO_L19N_0/VREF_0 IO_L19N_0/VREF_0 IO_L19N_0/VREF_0 E7 VREF
0 N.C. ( ) IO_L21N_0 IO_L21N_0 E6 500E: N.C.

1200E: I/O
1600E: I/O
0 N.C. ( ) IO_L21P_0 IO_L21P_0 D6 500E: N.C.

1200E: I/O
1600E: I/O
0 IO_L24N_0 IO_L24N_0 IO_L24N_0 B4 I/O
0 IO_L25N_0/HSWAP IO_L25N_0/HSWAP IO_L25N_0/HSWAP B3 DUAL
0 IP IP IP A3 INPUT
0 N.C. ( ) IO IP A12 500E: N.C.

1200E: I/O
1600E: INPUT

R
Pinout Descriptions

FG320
0 IP IP IP C15 INPUT
0 IP_L02N_0 IP_L02N_0 IP_L02N_0 A15 INPUT
0 IP_L02P_0 IP_L02P_0 IP_L02P_0 B15 INPUT
0 IP_L07N_0 IP_L07N_0 IP_L07N_0 D12 INPUT
0 IP_L10N_0 IP_L10N_0 IP_L10N_0 G10 INPUT
0 IP_L10P_0 IP_L10P_0 IP_L10P_0 F10 INPUT
0 IP_L13N_0/GCLK9 IP_L13N_0/GCLK9 IP_L13N_0/GCLK9 B9 GCLK
0 IP_L13P_0/GCLK8 IP_L13P_0/GCLK8 IP_L13P_0/GCLK8 B8 GCLK
0 IP_L16N_0 IP_L16N_0 IP_L16N_0 D8 INPUT

0 IP_L22N_0 IP_L22N_0 IP_L22N_0 B5 INPUT
0 IP_L22P_0 IP_L22P_0 IP_L22P_0 A5 INPUT
0 VCCO_0 VCCO_0 VCCO_0 A9 VCCO
0 VCCO_0 VCCO_0 VCCO_0 C6 VCCO
0 VCCO_0 VCCO_0 VCCO_0 C13 VCCO
1 N.C. ( ) IO IO P16 500E: N.C.

1200E: I/O
1600E: I/O
1 IO_L01N_1/A15 IO_L01N_1/A15 IO_L01N_1/A15 T17 DUAL
1 IO_L01P_1/A16 IO_L01P_1/A16 IO_L01P_1/A16 U18 DUAL

1 IO_L02N_1/A13 IO_L02N_1/A13 IO_L02N_1/A13 T18 DUAL
1 IO_L03N_1/VREF_1 IO_L03N_1/VREF_1 IO_L03N_1/VREF_1 R16 VREF
1 N.C. ( ) IO_L04N_1 IO_L04N_1 N14 500E: N.C.

1200E: I/O
1600E: INPUT
1 N.C. ( ) IO_L04P_1 IO_L04P_1 N15 500E: N.C.
1200E: I/O
1600E: INPUT
1 IO_L05N_1/VREF_1 IO_L05N_1/VREF_1 IO_L05N_1/VREF_1 M13 VREF

R
Pinout Descriptions

FG320
1 IO_L09N_1/A11 IO_L09N_1/A11 IO_L09N_1/A11 L15 DUAL
1 IO_L09P_1/A12 IO_L09P_1/A12 IO_L09P_1/A12 L16 DUAL
1 IO_L10N_1/VREF_1 IO_L10N_1/VREF_1 IO_L10N_1/VREF_1 L17 VREF
1 IO_L11N_1/A9/RHCLK1 IO_L11N_1/A9/RHCLK1 IO_L11N_1/A9/RHCLK1 K12 RHCLK/DUAL

1 IO_L12N_1/A7/RHCLK3/ IO_L12N_1/A7/RHCLK3/ IO_L12N_1/A7/RHCLK3/ K14 RHCLK/DUAL

TRDY1 TRDY1 TRDY1
1 IO_L13P_1/A6/RHCLK4/ IO_L13P_1/A6/RHCLK4/ IO_L13P_1/A6/RHCLK4/ J17 RHCLK/DUAL

IRDY1 IRDY1 IRDY1
1 IO_L14P_1/A4/RHCLK6 IO_L14P_1/A4/RHCLK6 IO_L14P_1/A4/RHCLK6 J15 RHCLK/DUAL
1 IO_L15N_1/A1 IO_L15N_1/A1 IO_L15N_1/A1 J13 DUAL
1 IO_L15P_1/A2 IO_L15P_1/A2 IO_L15P_1/A2 J12 DUAL
1 IO_L16N_1/A0 IO_L16N_1/A0 IO_L16N_1/A0 H17 DUAL
1 IO_L16P_1 IO_L16P_1 IO_L16P_1 H16 I/O
1 IO_L17N_1 IO_L17N_1 IO_L17N_1 H15 I/O

1 N.C. ( ) IO_L22N_1 IO_L22N_1 E16 500E: N.C.

1200E: I/O
1600E: I/O

R
Pinout Descriptions

FG320
1 N.C. ( ) IO_L22P_1 IO_L22P_1 E15 500E: N.C.

1200E: I/O
1600E: I/O
1 IO_L23N_1/LDC0 IO_L23N_1/LDC0 IO_L23N_1/LDC0 D16 DUAL
1 IO_L23P_1/HDC IO_L23P_1/HDC IO_L23P_1/HDC D17 DUAL
1 IO_L24N_1/LDC2 IO_L24N_1/LDC2 IO_L24N_1/LDC2 C17 DUAL
1 IO_L24P_1/LDC1 IO_L24P_1/LDC1 IO_L24P_1/LDC1 C18 DUAL
1 IP IP IP B18 INPUT
1 IO IP IP E17 500E: I/O

1200E: INPUT
1600E: INPUT
1 IP IP IP E18 INPUT
1 IP IP IP G18 INPUT
1 IP IP IP H13 INPUT
1 IP IP IP K17 INPUT
1 IP IP IP K18 INPUT
1 IP IP IP L13 INPUT
1 IP IP IP L14 INPUT
1 IP IP IP N17 INPUT
1 IO IP IP P15 500E: I/O

1200E: INPUT
1600E: INPUT
1 IP IP IP R17 INPUT
1 IP/VREF_1 IP/VREF_1 IP/VREF_1 D18 VREF
1 IP/VREF_1 IP/VREF_1 IP/VREF_1 H18 VREF
1 VCCO_1 VCCO_1 VCCO_1 H12 VCCO
1 VCCO_1 VCCO_1 VCCO_1 J18 VCCO
1 VCCO_1 VCCO_1 VCCO_1 N16 VCCO
2 IO IO IO P9 I/O
2 IO IO IO R11 I/O
2 IP IO IO U6 500E: INPUT
1200E: I/O
1600E: I/O

R
Pinout Descriptions

FG320
2 IP IO IO U13 500E: INPUT

1200E: I/O
1600E: I/O
2 N.C. ( ) IO IO V7 500E: N.C.

1200E: I/O
1600E: I/O
2 IO/D5 IO/D5 IO/D5 R9 DUAL
2 IO/M1 IO/M1 IO/M1 V11 DUAL
2 IO/VREF_2 IO/VREF_2 IO/VREF_2 T15 VREF
2 IO/VREF_2 IO/VREF_2 IO/VREF_2 U5 VREF
2 IO_L01N_2/INIT_B IO_L01N_2/INIT_B IO_L01N_2/INIT_B T3 DUAL
2 IO_L01P_2/CSO_B IO_L01P_2/CSO_B IO_L01P_2/CSO_B U3 DUAL
2 IO_L03N_2/MOSI/CSI_B IO_L03N_2/MOSI/CSI_B IO_L03N_2/MOSI/CSI_B T4 DUAL
2 IO_L03P_2/DOUT/BUSY IO_L03P_2/DOUT/BUSY IO_L03P_2/DOUT/BUSY U4 DUAL
2 N.C. ( ) IO_L06N_2/VREF_2 IO_L06N_2/VREF_2 V6 500E: N.C.

1200E: VREF
1600E: VREF
2 N.C. ( ) IO_L06P_2 IO_L06P_2 V5 500E: N.C.
1200E: I/O
1600E: I/O

2 IO_L12N_2/D6/GCLK13 IO_L12N_2/D6/GCLK13 IO_L12N_2/D6/GCLK13 M9 DUAL/GCLK
2 IO_L12P_2/D7/GCLK12 IO_L12P_2/D7/GCLK12 IO_L12P_2/D7/GCLK12 N9 DUAL/GCLK
2 IO_L13N_2/D3/GCLK15 IO_L13N_2/D3/GCLK15 IO_L13N_2/D3/GCLK15 V9 DUAL/GCLK
2 IO_L13P_2/D4/GCLK14 IO_L13P_2/D4/GCLK14 IO_L13P_2/D4/GCLK14 U9 DUAL/GCLK
2 IO_L15N_2/D1/GCLK3 IO_L15N_2/D1/GCLK3 IO_L15N_2/D1/GCLK3 P10 DUAL/GCLK
2 IO_L15P_2/D2/GCLK2 IO_L15P_2/D2/GCLK2 IO_L15P_2/D2/GCLK2 R10 DUAL/GCLK
2 IO_L16N_2/DIN/D0 IO_L16N_2/DIN/D0 IO_L16N_2/DIN/D0 N10 DUAL

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Pinout Descriptions

FG320
2 IO_L16P_2/M0 IO_L16P_2/M0 IO_L16P_2/M0 M10 DUAL
2 IO_L19N_2/VREF_2 IO_L19N_2/VREF_2 IO_L19N_2/VREF_2 V13 VREF
2 IO_L19P_2 IO_L19P_2 IO_L19P_2 V12 I/O
2 N.C. ( ) IO_L21N_2 IO_L21N_2 P12 500E: N.C.

1200E: I/O
1600E: I/O
2 N.C. ( ) IO_L21P_2 IO_L21P_2 N12 500E: N.C.
1200E: I/O
1600E: I/O
2 IO_L24P_2/A21 IO_L24P_2/A21 IO_L24P_2/A21 T14 DUAL
2 IO_L25N_2/VS1/A18 IO_L25N_2/VS1/A18 IO_L25N_2/VS1/A18 U15 DUAL
2 IO_L25P_2/VS2/A19 IO_L25P_2/VS2/A19 IO_L25P_2/VS2/A19 V15 DUAL
2 IO_L26N_2/CCLK IO_L26N_2/CCLK IO_L26N_2/CCLK U16 DUAL
2 IO_L26P_2/VS0/A17 IO_L26P_2/VS0/A17 IO_L26P_2/VS0/A17 T16 DUAL
2 IP IP IP V2 INPUT
2 IP IP IP V16 INPUT
2 IP_L02N_2 IP_L02N_2 IP_L02N_2 V3 INPUT
2 IP_L02P_2 IP_L02P_2 IP_L02P_2 V4 INPUT
2 IP_L08N_2 IP_L08N_2 IP_L08N_2 R7 INPUT
2 IP_L11N_2/VREF_2 IP_L11N_2/VREF_2 IP_L11N_2/VREF_2 V8 VREF
2 IP_L11P_2 IP_L11P_2 IP_L11P_2 U8 INPUT
2 IP_L14N_2/M2/GCLK1 IP_L14N_2/M2/GCLK1 IP_L14N_2/M2/GCLK1 T10 DUAL/GCLK
2 IP_L14P_2/RDWR_B/ IP_L14P_2/RDWR_B/ IP_L14P_2/RDWR_B/ U10 DUAL/GCLK

GCLK0 GCLK0 GCLK0
2 IP_L17N_2 IP_L17N_2 IP_L17N_2 U11 INPUT
2 IP_L23N_2 IP_L23N_2 IP_L23N_2 U14 INPUT
2 IP_L23P_2 IP_L23P_2 IP_L23P_2 V14 INPUT

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Pinout Descriptions

FG320
2 VCCO_2 VCCO_2 VCCO_2 T6 VCCO
2 VCCO_2 VCCO_2 VCCO_2 T13 VCCO
2 VCCO_2 VCCO_2 VCCO_2 V10 VCCO
3 N.C. ( ) IO IO D4 500E: N.C.

1200E: I/O
1600E: I/O
3 IO_L01N_3 IO_L01N_3 IO_L01N_3 C2 I/O

3 N.C. ( ) IO_L04N_3 IO_L04N_3 E3 500E: N.C.

1200E: I/O
1600E: I/O
3 N.C. ( ) IO_L04P_3 IO_L04P_3 E4 500E: N.C.
1200E: I/O
1600E: I/O
3 IO_L06N_3/VREF_3 IO_L06N_3/VREF_3 IO_L06N_3/VREF_3 G4 VREF

3 IO_L12N_3/LHCLK3/ IO_L12N_3/LHCLK3/ IO_L12N_3/LHCLK3/ J2 LHCLK

IRDY2 IRDY2 IRDY2

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Pinout Descriptions

FG320
3 IO_L13N_3/LHCLK5 IO_L13N_3/LHCLK5 IO_L13N_3/LHCLK5 K4 LHCLK
3 IO_L13P_3/LHCLK4/ IO_L13P_3/LHCLK4/ IO_L13P_3/LHCLK4/ K3 LHCLK

TRDY2 TRDY2 TRDY2
3 IO_L14N_3/LHCLK7 IO_L14N_3/LHCLK7 IO_L14N_3/LHCLK7 K5 LHCLK
3 IO_L14P_3/LHCLK6 IO_L14P_3/LHCLK6 IO_L14P_3/LHCLK6 K6 LHCLK
3 IO_L17N_3/VREF_3 IO_L17N_3/VREF_3 IO_L17N_3/VREF_3 L5 VREF
3 N.C. ( ) IO_L22N_3 IO_L22N_3 P4 500E: N.C.

1200E: I/O
1600E: I/O
3 N.C. ( ) IO_L22P_3 IO_L22P_3 P3 500E: N.C.
1200E: I/O
1600E: I/O
3 IP IP IP D3 INPUT
3 IO IP IP F4 500E: I/O
1200E: INPUT
1600E: INPUT
3 IP IP IP F5 INPUT
3 IP IP IP G1 INPUT
3 IP IP IP J7 INPUT
3 IP IP IP K2 INPUT

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Pinout Descriptions

FG320
3 IP IP IP K7 INPUT
3 IP IP IP M1 INPUT
3 IP IP IP N1 INPUT
3 IP IP IP N2 INPUT
3 IP IP IP R1 INPUT
3 IP IP IP U1 INPUT
3 IP/VREF_3 IP/VREF_3 IP/VREF_3 J6 VREF
3 IO/VREF_3 IP/VREF_3 IP/VREF_3 R4 500E: VREF(I/O)

1200E:
VREF(INPUT)
1600E:
VREF(INPUT)
3 VCCO_3 VCCO_3 VCCO_3 H7 VCCO
3 VCCO_3 VCCO_3 VCCO_3 N3 VCCO
GND GND GND GND C10 GND

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Pinout Descriptions

FG320
GND GND GND GND M7 GND
GND GND GND GND M12 GND
GND GND GND GND U2 GND
GND GND GND GND U17 GND
GND GND GND GND V1 GND
GND GND GND GND V18 GND
VCCAUX DONE DONE DONE V17 CONFIG

VCCAUX PROG_B PROG_B PROG_B B1 CONFIG
VCCAUX TCK TCK TCK A17 JTAG
VCCAUX TDI TDI TDI A2 JTAG
VCCAUX TDO TDO TDO C16 JTAG
VCCAUX TMS TMS TMS D15 JTAG
VCCAUX VCCAUX VCCAUX VCCAUX B7 VCCAUX
VCCAUX VCCAUX VCCAUX VCCAUX B12 VCCAUX
VCCAUX VCCAUX VCCAUX VCCAUX G2 VCCAUX
VCCAUX VCCAUX VCCAUX VCCAUX G17 VCCAUX
VCCAUX VCCAUX VCCAUX VCCAUX M2 VCCAUX
VCCAUX VCCAUX VCCAUX VCCAUX M17 VCCAUX
VCCAUX VCCAUX VCCAUX VCCAUX U7 VCCAUX
VCCAUX VCCAUX VCCAUX VCCAUX U12 VCCAUX
VCCINT VCCINT VCCINT VCCINT F6 VCCINT
VCCINT VCCINT VCCINT VCCINT F13 VCCINT
VCCINT VCCINT VCCINT VCCINT P5 VCCINT
VCCINT VCCINT VCCINT VCCINT P14 VCCINT

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Pinout Descriptions
User I/Os by Bank

Table 25, Table 26, and Table 27 indicate how the available
the FG320 package.
Table 25: User I/Os Per Bank for XC3S500E in the FG320 Package
Package Maximum
Top 0 58 29 14 1 6 8
Right 1 58 22 10 21 5 0
Bottom 2 58 17 13 24 4 0
Left 3 58 34 11 0 5 8
TOTAL 232 102 48 46 20 16
Package Maximum
Top 0 61 34 12 1 6 8
Right 1 63 25 12 21 5 0
Bottom 2 63 23 11 24 5 0
Left 3 63 38 12 0 5 8
TOTAL 250 120 47 46 21 16
Package Maximum
Top 0 61 33 13 1 6 8
Right 1 63 25 12 21 5 0
Bottom 2 63 23 11 24 5 0
Left 3 63 38 12 0 5 8
TOTAL 250 119 48 46 21 16
Footprint Migration Differences The XC3S500E is duplicated on both the left and right sides
of the table to show migrations to and from the XC3S1200E
and the XC3S1600E. The arrows indicate the direction for
ences between the XC3S500E, the XC3S1200E, and the
easy migration. A double-ended arrow ( ) indicates that
XC3S1600E FPGAs that may affect easy migration
the two pins have identical functionality. A left-facing arrow
between devices available in the FG320 package. There are
( ) indicates that the pin on the device on the right uncon-
26 such balls. All other pins not listed in Table 28 uncondi-
ditionally migrates to the pin on the device on the left. It may
tionally migrate between Spartan-3E devices available in
be possible to migrate the opposite direction depending on
the FG320 package.
the I/O configuration. For example, an I/O pin (Type = I/O)

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Pinout Descriptions
can migrate to an input-only pin (Type = INPUT) if the I/O

pin is configured as an input.
Table 28: FG320 Footprint Migration Differences

Pin Bank XC3S500E Migration XC3S1200E Migration XC3S1600E Migration XC3S500E
A7 0 INPUT I/O I/O INPUT
A12 0 N.C. I/O INPUT N.C.
D4 3 N.C. I/O I/O N.C.
D6 0 N.C. I/O I/O N.C.
D13 0 INPUT I/O I/O INPUT
E3 3 N.C. I/O I/O N.C.
E15 1 N.C. I/O I/O N.C.

E16 1 N.C. I/O I/O N.C.
E17 1 I/O INPUT INPUT I/O
F4 3 I/O INPUT INPUT I/O
N12 2 N.C. I/O I/O N.C.
N14 1 N.C. I/O I/O N.C.
N15 1 N.C. I/O I/O N.C.
P12 2 N.C. I/O I/O N.C.
P15 1 I/O INPUT INPUT I/O
P16 1 N.C. I/O I/O N.C.
R4 3 VREF(I/O) VREF(INPUT) VREF(INPUT) VREF(I/O)
U6 2 INPUT I/O I/O INPUT
U13 2 INPUT I/O I/O INPUT
V5 2 N.C. I/O I/O N.C.
V6 2 N.C. VREF VREF N.C.
V7 2 N.C. I/O I/O N.C.
DIFFERENCES 26 1 26
Legend:
This pin is identical on both the device on the left and the right.
This pin can unconditionally migrate from the device on the left to the device on the right. Migration in the other direction may be possible
depending on how the pin is configured for the device on the right.
This pin can unconditionally migrate from the device on the right to the device on the left. Migration in the other direction may be possible
depending on how the pin is configured for the device on the left.

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Pinout Descriptions
FG320 Footprint
Bank 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
I/O INPUT
I/O INPUT I/O INPUT I/O I/O INPUT I/O
A GND TDI INPUT
L24P_0 L22P_0 L20N_0
I/O VCCO_0 L12N_0 I/O
L05P_0 L04N_0 L02N_0 L01N_0
TCK GND
GCLK7
I/O INPUT INPUT I/O I/O

I/O INPUT I/O I/O I/O INPUT I/O
B PROG_B GND L25N_0
L24N_0 L22N_0 L20P_0
VCCAUX L13P_0 L13N_0 L12P_0
VREF_0
VCCAUX L05N_0
L04P_0 L02P_0 L01P_0
GND INPUT
HSWAP GCLK8 GCLK9 GCLK6 VREF_0
I/O I/O I/O I/O

I/O I/O I/O I/O I/O INPUT I/O INPUT
C L01P_3 L01N_3 L25P_0
I/O
L23P_0
VCCO_0
L18P_0 L16P_0
L14P_0 GND
L09P_0 L07P_0
VCCO_0 L03N_0 INPUT TDO L24N_1 L24P_1
GCLK10 VREF_0 LDC2 LDC1

I/O I/O INPUT I/O INPUT INPUT I/O INPUT
D L02P_3
L02N_3 INPUT L23N_0 L21P_0 L18N_0
L16N_0
L14N_0 L11P_0
L09N_0 L07N_0 L03P_0
TMS L23N_1 L23P_1
VREF_1
VREF_3 VREF_0 VREF_0 GCLK11 GCLK4 LDC0 HDC

I/O I/O I/O I/O I/O I/O INPUT
E L03N_3 L03P_3
L04N_3 L04P_3 VCCINT L21N_0 L19N_0
L17P_0 L15P_0
L11N_0
L08P_0 L06N_0
I/O VCCINT L22P_1 L22N_1 INPUT
VREF_0 GCLK5
I/O I/O INPUT I/O I/O I/O INPUT I/O I/O I/O I/O I/O I/O
F L05P_3 L05N_3
VCCO_3 INPUT VCCINT
L19P_0 L17N_0 L15N_0 L10P_0 L08N_0 L06P_0
VCCINT
L21N_1 L21P_1
VCCO_1
L19N_1 L19P_1
I/O
I/O I/O I/O INPUT I/O I/O I/O I/O
G INPUT VCCAUX
L06P_3
L06N_3
L07N_3 L07P_3
GND VCCO_0 I/O
L10N_0
VCCO_0 GND
L20N_1 L20P_1 L18P_1 L18N_1
VCCAUX INPUT
VREF_3
I/O
I/O I/O I/O I/O I/O I/O I/O I/O I/O INPUT
H L10N_3 L10P_3 L09N_3 L09P_3 L08N_3 L08P_3
VCCO_3 GND GND GND GND VCCO_1 INPUT
L17P_1 L17N_1 L16P_1
L16N_1
VREF_1
A0
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
INPUT L13P_1
L12N_3 L14N_1 L14P_1 L13N_1
Bank 1
J L12P_3
LHCLK3
GND L11N_3 L11P_3
VREF_3
INPUT GND GND L15P_1 L15N_1
A3 A4
4 A5
A6 VCCO_1
LHCLK2 LHCLK1 LHCLK0 A2 A1 RHCLK4
IRDY2 RHCLK7 RHCLK6 RHCLK5 IRDY1
Bank 3

L12N_1
K VCCO_3 INPUT L13P_3 L13N_3 L14N_3 L14P_3 INPUT GND GND L11N_1 L11P_1 A7 L12P_1 GND INPUT INPUT
LHCLK4 A9 A10 RHCLK3 A8
TRDY2 LHCLK5 LHCLK7 LHCLK6 RHCLK1 RHCLK0 RHCLK2
TRDY1
I/O I/O I/O I/O
L L15P_3 L15N_3 L16P_3 L16N_3
L17N_3
L17P_3
VCCO_3 GND GND GND GND VCCO_1 INPUT INPUT L09N_1 L09P_1 L10N_1
L10P_1
VREF_3 A11 A12 VREF_1
I/O I/O I/O

I/O I/O I/O I/O L12N_2 I/O I/O I/O I/O
M INPUT VCCAUX
L18N_3 L18P_3 L19P_3 L19N_3
GND VCCO_2
D6
L16P_2 VCCO_2 GND L05N_1
L05P_1 L07P_1 L07N_1
VCCAUX
L08N_1
GCLK13 M0 VREF_1
I/O I/O I/O I/O I/O

I/O I/O I/O I/O L12P_2 L16N_2 I/O I/O
N INPUT INPUT VCCO_3
L20P_3 L20N_3
VCCINT
L07P_2 L09N_2 D7 DIN L18N_2
L21P_2 VCCINT L04N_1 L04P_1 VCCO_1 INPUT
L08P_1
GCLK12 D0
I/O I/O I/O I/O I/O
I/O I/O I/O I/O I/O L15N_2 I/O INPUT I/O I/O I/O
P L21N_3 L21P_3
L22P_3 L22N_3 VCCINT
L05N_2 L07N_2 L09P_2
I/O
D1 L18P_2
L21N_2 L22P_2 VCCINT
L06P_1 L06N_1
GCLK3 A23

I/O I/O I/O I/O INPUT I/O I/O L15P_2 I/O I/O
R INPUT
L23N_3 L23P_3
VREF_3
L04P_2 L05P_2 L08N_2 L10P_2 D5 D2
I/O
L20N_2
L22N_2 L24N_2
L03P_1
L03N_1 INPUT L02P_1
GCLK2 A22 A20 VREF_1 A14
I/O I/O INPUT I/O I/O I/O I/O

I/O I/O L03N_2 I/O INPUT I/O L14N_2 INPUT I/O I/O L26P_2
T L24N_3 L24P_3
L01N_2
MOSI L04N_2
VCCO_2
L08P_2 L10N_2
GND
M2 L17P_2 L20P_2
VCCO_2 L24P_2
VREF_2 VS0
L01N_1 L02N_1
INIT_B CSI_B GCLK1 A21 A17 A15 A13
I/O I/O I/O INPUT I/O I/O I/O

L03P_2 I/O INPUT INPUT L13P_2 L14P_2 INPUT INPUT INPUT L25N_2
U INPUT GND L01P_2
DOUT VREF_2
VCCAUX
L11P_2 D4 RDWR_B L17N_2
VCCAUX
L23N_2 VS1
L26N_2 GND L01P_1
CSO_B BUSY GCLK14 GCLK0 A18 CCLK A16
I/O I/O INPUT I/O I/O I/O

INPUT INPUT L06N_2 I/O L13N_2 I/O I/O INPUT L25P_2
V GND INPUT
L02N_2 L02P_2
L06P_2
VREF_2 L11N_2
D3
VCCO_2
M1 L19P_2
L19N_2
L23P_2 VS2
INPUT DONE GND
VREF_2 GCLK15 VREF_2 A19
Bank 2
DS312-4_06_021605
Figure 8: FG320 Package Footprint (top view)
general-purpose user I/O
46 possible user-I/O voltage reference for bank
general-purpose input pin
20 for bank
4 pins
8 voltage (+1.2V)

0 28 8 voltage (+2.5V)

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Pinout Descriptions
FG400: 400-ball Fine-pitch Ball Grid Array

The 400-ball fine-pitch ball grid array, FG400, supports two Table 29: FG400 Package Pinout
different Spartan-3E FPGAs, including the XC3S1200E and
XC3S1200E
the XC3S1600E. Both devices share a common footprint for XC3S1600E FG400
this package as shown in Table 29 and Figure 9. Bank Pin Name Ball Type
Table 29 lists all the FG400 package pins. They are sorted
0 IO_L09P_0 A14 I/O
form a differential I/O pair appear together in the table. The 0 IO_L10N_0 B13 I/O
table also shows the pin number for each pin and the pin
0 IO_L10P_0 C13 I/O
0 IO_L11N_0 C12 I/O
print diagram is available for download from the Xilinx web- 0 IO_L11P_0 D12 I/O
0 IO_L12N_0 E12 I/O
Pinout Table 0 IO_L12P_0 F12 I/O
0 IO_L14N_0/GCLK5 G11 GCLK

Table 29: FG400 Package Pinout
0 IO_L14P_0/GCLK4 F11 GCLK
XC3S1200E
XC3S1600E FG400 0 IO_L15N_0/GCLK7 E10 GCLK
Bank Pin Name Ball Type 0 IO_L15P_0/GCLK6 E11 GCLK
0 IO A3 I/O 0 IO_L17N_0/GCLK11 A9 GCLK
0 IO A8 I/O 0 IO_L17P_0/GCLK10 A10 GCLK
0 IO A12 I/O 0 IO_L18N_0 F9 I/O
0 IO C7 I/O 0 IO_L18P_0 E9 I/O
0 IO C10 I/O 0 IO_L20N_0 C9 I/O
0 IO E8 I/O 0 IO_L20P_0 D9 I/O
0 IO E13 I/O 0 IO_L21N_0/VREF_0 B8 VREF
0 IO E16 I/O 0 IO_L21P_0 B9 I/O
0 IO F13 I/O 0 IO_L23N_0/VREF_0 F7 VREF
0 IO F14 I/O 0 IO_L23P_0 F8 I/O
0 IO G7 I/O 0 IO_L24N_0 A6 I/O
0 IO/VREF_0 C11 VREF 0 IO_L24P_0 A7 I/O
0 IO_L01N_0 B17 I/O 0 IO_L26N_0 B5 I/O
0 IO_L01P_0 C17 I/O 0 IO_L26P_0 B6 I/O
0 IO_L03N_0/VREF_0 A18 VREF 0 IO_L27N_0 D6 I/O
0 IO_L03P_0 A19 I/O 0 IO_L27P_0 C6 I/O
0 IO_L04N_0 A17 I/O 0 IO_L29N_0/VREF_0 C5 VREF
0 IO_L04P_0 A16 I/O 0 IO_L29P_0 D5 I/O
0 IO_L06N_0 A15 I/O 0 IO_L30N_0 A2 I/O
0 IO_L06P_0 B15 I/O 0 IO_L30P_0 B2 I/O
0 IO_L07N_0 C14 I/O 0 IO_L31N_0/HSWAP D4 DUAL
0 IO_L07P_0 D14 I/O 0 IO_L31P_0 C4 I/O
0 IO_L09N_0/VREF_0 A13 VREF

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Pinout Descriptions
Table 29: FG400 Package Pinout Table 29: FG400 Package Pinout
XC3S1200E XC3S1200E
XC3S1600E FG400 XC3S1600E FG400
0 IP B18 INPUT 1 IO_L04N_1 W20 I/O
0 IP E5 INPUT 1 IO_L04P_1 V20 I/O
0 IP_L02N_0 C16 INPUT 1 IO_L05N_1 R18 I/O
0 IP_L02P_0 D16 INPUT 1 IO_L05P_1 R17 I/O
0 IP_L05N_0 D15 INPUT 1 IO_L06N_1 T20 I/O
0 IP_L05P_0 C15 INPUT 1 IO_L06P_1 U20 I/O
0 IP_L08N_0 E14 INPUT 1 IO_L07N_1 P18 I/O
0 IP_L08P_0 E15 INPUT 1 IO_L07P_1 P17 I/O
0 IP_L10N_0 G14 INPUT 1 IO_L08N_1/VREF_1 P20 VREF
0 IP_L10P_0 G13 INPUT 1 IO_L08P_1 R20 I/O
0 IP_L13N_0 B11 INPUT 1 IO_L09N_1 P16 I/O
0 IP_L13P_0 B12 INPUT 1 IO_L09P_1 N16 I/O
0 IP_L16N_0/GCLK9 G10 GCLK 1 IO_L10N_1 N19 I/O
0 IP_L16P_0/GCLK8 H10 GCLK 1 IO_L10P_1 N18 I/O
0 IP_L19N_0 G9 INPUT 1 IO_L11N_1 N15 I/O
0 IP_L19P_0 G8 INPUT 1 IO_L11P_1 M15 I/O
0 IP_L22N_0 C8 INPUT 1 IO_L12N_1/A11 M18 DUAL
0 IP_L22P_0 D8 INPUT 1 IO_L12P_1/A12 M17 DUAL
0 IP_L25N_0 E6 INPUT 1 IO_L13N_1/VREF_1 L19 VREF
0 IP_L25P_0 E7 INPUT 1 IO_L13P_1 M19 I/O
0 IP_L28N_0 A4 INPUT 1 IO_L14N_1/A9/RHCLK1 L16 RHCLK/

DUAL
0 IP_L28P_0 A5 INPUT
1 IO_L14P_1/A10/RHCLK0 M16 RHCLK/
0 VCCO_0 B4 VCCO DUAL
0 VCCO_0 B10 VCCO 1 IO_L15N_1/A7/RHCLK3/ L14 RHCLK/
0 VCCO_0 B16 VCCO TRDY1 DUAL
0 VCCO_0 D7 VCCO 1 IO_L15P_1/A8/RHCLK2 L15 RHCLK/

DUAL
0 VCCO_0 D13 VCCO
1 IO_L16N_1/A5/RHCLK5 K14 RHCLK/
0 VCCO_0 F10 VCCO DUAL
1 IO_L01N_1/A15 U18 DUAL 1 IO_L16P_1/A6/RHCLK4/ K13 RHCLK/
IRDY1 DUAL
1 IO_L01P_1/A16 U17 DUAL
1 IO_L17N_1/A3/RHCLK7 J20 RHCLK/
1 IO_L02N_1/A13 T18 DUAL
DUAL
1 IO_L02P_1/A14 T17 DUAL
1 IO_L17P_1/A4/RHCLK6 K20 RHCLK/
1 IO_L03N_1/VREF_1 V19 VREF DUAL
1 IO_L03P_1 U19 I/O 1 IO_L18N_1/A1 K16 DUAL
1 IO_L18P_1/A2 J16 DUAL

R
Pinout Descriptions
XC3S1200E XC3S1200E
XC3S1600E FG400 XC3S1600E FG400
1 IO_L19N_1/A0 J13 DUAL 1 IP R16 INPUT
1 IO_L19P_1 J14 I/O 1 IP R19 INPUT
1 IO_L20N_1 J17 I/O 1 IP/VREF_1 E19 VREF
1 IO_L20P_1 J18 I/O 1 IP/VREF_1 K18 VREF
1 IO_L21N_1 H19 I/O 1 VCCO_1 D19 VCCO
1 IO_L21P_1 J19 I/O 1 VCCO_1 G17 VCCO
1 IO_L22N_1 H15 I/O 1 VCCO_1 K15 VCCO
1 IO_L22P_1 H16 I/O 1 VCCO_1 K19 VCCO
1 IO_L23N_1 H18 I/O 1 VCCO_1 N17 VCCO
1 IO_L23P_1 H17 I/O 1 VCCO_1 T19 VCCO
1 IO_L24N_1/VREF_1 H20 VREF 2 IO P8 I/O
1 IO_L24P_1 G20 I/O 2 IO P13 I/O
1 IO_L25N_1 G16 I/O 2 IO R9 I/O
1 IO_L25P_1 F16 I/O 2 IO R13 I/O
1 IO_L26N_1 F19 I/O 2 IO W15 I/O
1 IO_L26P_1 F20 I/O 2 IO Y5 I/O
1 IO_L27N_1 F18 I/O 2 IO Y7 I/O
1 IO_L27P_1 F17 I/O 2 IO Y13 I/O
1 IO_L28N_1 D20 I/O 2 IO/D5 N11 DUAL
1 IO_L28P_1 E20 I/O 2 IO/M1 T11 DUAL
1 IO_L29N_1/LDC0 D18 DUAL 2 IO/VREF_2 Y3 VREF
1 IO_L29P_1/HDC E18 DUAL 2 IO/VREF_2 Y17 VREF
1 IO_L30N_1/LDC2 C19 DUAL 2 IO_L01N_2/INIT_B V4 DUAL
1 IO_L30P_1/LDC1 C20 DUAL 2 IO_L01P_2/CSO_B U4 DUAL
1 IP B20 INPUT 2 IO_L03N_2/MOSI/CSI_B V5 DUAL
1 IP G15 INPUT 2 IO_L03P_2/DOUT/BUSY U5 DUAL
1 IP G18 INPUT 2 IO_L04N_2 Y4 I/O
1 IP H14 INPUT 2 IO_L04P_2 W4 I/O
1 IP J15 INPUT 2 IO_L06N_2 T6 I/O
1 IP L18 INPUT 2 IO_L06P_2 T5 I/O
1 IP M20 INPUT 2 IO_L07N_2 U7 I/O
1 IP N14 INPUT 2 IO_L07P_2 V7 I/O
1 IP N20 INPUT 2 IO_L09N_2/VREF_2 R7 VREF
1 IP P15 INPUT 2 IO_L09P_2 T7 I/O

R
Pinout Descriptions
XC3S1200E XC3S1200E
XC3S1600E FG400 XC3S1600E FG400
2 IO_L10N_2 V8 I/O 2 IO_L32P_2/VS0/A17 Y19 DUAL
2 IO_L10P_2 W8 I/O 2 IP T16 INPUT
2 IO_L12N_2 U9 I/O 2 IP W3 INPUT
2 IO_L12P_2 V9 I/O 2 IP_L02N_2 Y2 INPUT
2 IO_L13N_2 Y8 I/O 2 IP_L02P_2 W2 INPUT
2 IO_L13P_2 Y9 I/O 2 IP_L05N_2 V6 INPUT
2 IO_L15N_2/D6/GCLK13 W10 DUAL/ 2 IP_L05P_2 U6 INPUT

GCLK
2 IP_L08N_2 Y6 INPUT
2 IO_L15P_2/D7/GCLK12 W9 DUAL/
GCLK 2 IP_L08P_2 W6 INPUT
2 IO_L16N_2/D3/GCLK15 P10 DUAL/ 2 IP_L11N_2 R8 INPUT

GCLK 2 IP_L11P_2 T8 INPUT
2 IO_L16P_2/D4/GCLK14 R10 DUAL/ 2 IP_L14N_2/VREF_2 T10 VREF
GCLK
2 IP_L14P_2 T9 INPUT
2 IO_L18N_2/D1/GCLK3 V11 DUAL/
GCLK 2 IP_L17N_2/M2/GCLK1 P12 DUAL/
GCLK
2 IO_L18P_2/D2/GCLK2 V10 DUAL/
GCLK 2 IP_L17P_2/RDWR_B/ P11 DUAL/
GCLK0 GCLK
2 IO_L19N_2/DIN/D0 Y12 DUAL
2 IP_L20N_2 T12 INPUT
2 IO_L19P_2/M0 Y11 DUAL
2 IP_L20P_2 R12 INPUT
2 IO_L21N_2 U12 I/O
2 IP_L23N_2/VREF_2 T13 VREF
2 IO_L21P_2 V12 I/O
2 IP_L23P_2 T14 INPUT
2 IO_L22N_2/VREF_2 W12 VREF
2 IP_L26N_2 V14 INPUT
2 IO_L22P_2 W13 I/O
2 IP_L26P_2 V15 INPUT
2 IO_L24N_2 U13 I/O
2 IP_L29N_2 W16 INPUT
2 IO_L24P_2 V13 I/O
2 IP_L29P_2 Y16 INPUT
2 IO_L25N_2 P14 I/O
2 VCCO_2 R11 VCCO
2 IO_L25P_2 R14 I/O
2 VCCO_2 U8 VCCO
2 IO_L27N_2/A22 Y14 DUAL
2 VCCO_2 U14 VCCO
2 IO_L27P_2/A23 Y15 DUAL
2 VCCO_2 W5 VCCO
2 IO_L28N_2 T15 I/O
2 VCCO_2 W11 VCCO
2 IO_L28P_2 U15 I/O
2 VCCO_2 W17 VCCO
2 IO_L30N_2/A20 V16 DUAL
3 IO_L01N_3 D2 I/O
2 IO_L30P_2/A21 U16 DUAL
3 IO_L01P_3 D3 I/O
2 IO_L31N_2/VS1/A18 Y18 DUAL
3 IO_L02N_3/VREF_3 E3 VREF
2 IO_L31P_2/VS2/A19 W18 DUAL
3 IO_L02P_3 E4 I/O
2 IO_L32N_2/CCLK W19 DUAL

R
Pinout Descriptions
XC3S1200E XC3S1200E
XC3S1600E FG400 XC3S1600E FG400
3 IO_L03N_3 C1 I/O 3 IO_L20N_3/VREF_3 N6 VREF
3 IO_L03P_3 B1 I/O 3 IO_L20P_3 M6 I/O
3 IO_L04N_3 E1 I/O 3 IO_L21N_3 N2 I/O
3 IO_L04P_3 D1 I/O 3 IO_L21P_3 N1 I/O
3 IO_L05N_3 F3 I/O 3 IO_L22N_3 P7 I/O
3 IO_L05P_3 F4 I/O 3 IO_L22P_3 N7 I/O
3 IO_L06N_3 F1 I/O 3 IO_L23N_3 N4 I/O
3 IO_L06P_3 F2 I/O 3 IO_L23P_3 N3 I/O
3 IO_L07N_3 G4 I/O 3 IO_L24N_3 R1 I/O
3 IO_L07P_3 G3 I/O 3 IO_L24P_3 P1 I/O
3 IO_L08N_3 G5 I/O 3 IO_L25N_3 R5 I/O
3 IO_L08P_3 H5 I/O 3 IO_L25P_3 P5 I/O
3 IO_L09N_3/VREF_3 H3 VREF 3 IO_L26N_3 T2 I/O
3 IO_L09P_3 H2 I/O 3 IO_L26P_3 R2 I/O
3 IO_L10N_3 H7 I/O 3 IO_L27N_3 R4 I/O
3 IO_L10P_3 H6 I/O 3 IO_L27P_3 R3 I/O
3 IO_L11N_3 J4 I/O 3 IO_L28N_3/VREF_3 T1 VREF
3 IO_L11P_3 J3 I/O 3 IO_L28P_3 U1 I/O
3 IO_L12N_3 J1 I/O 3 IO_L29N_3 T3 I/O
3 IO_L12P_3 J2 I/O 3 IO_L29P_3 U3 I/O
3 IO_L13N_3 J6 I/O 3 IO_L30N_3 V1 I/O
3 IO_L13P_3 K6 I/O 3 IO_L30P_3 V2 I/O
3 IO_L14N_3/LHCLK1 K2 LHCLK 3 IP F5 INPUT
3 IO_L14P_3/LHCLK0 K3 LHCLK 3 IP G1 INPUT
3 IO_L15N_3/LHCLK3/IRDY2 L7 LHCLK 3 IP G6 INPUT
3 IO_L15P_3/LHCLK2 K7 LHCLK 3 IP H1 INPUT
3 IO_L16N_3/LHCLK5 L1 LHCLK 3 IP J5 INPUT
3 IO_L16P_3/LHCLK4/TRDY2 M1 LHCLK 3 IP L5 INPUT
3 IO_L17N_3/LHCLK7 L3 LHCLK 3 IP L8 INPUT
3 IO_L17P_3/LHCLK6 M3 LHCLK 3 IP M2 INPUT
3 IO_L18N_3 M7 I/O 3 IP N5 INPUT
3 IO_L18P_3 M8 I/O 3 IP P3 INPUT
3 IO_L19N_3 M4 I/O 3 IP T4 INPUT
3 IO_L19P_3 M5 I/O 3 IP W1 INPUT

R
Pinout Descriptions
XC3S1200E XC3S1200E
XC3S1600E FG400 XC3S1600E FG400
3 IP/VREF_3 K5 VREF GND GND M10 GND
3 IP/VREF_3 P6 VREF GND GND M12 GND
3 VCCO_3 E2 VCCO GND GND N13 GND
3 VCCO_3 H4 VCCO GND GND P2 GND
3 VCCO_3 L2 VCCO GND GND P9 GND
3 VCCO_3 L6 VCCO GND GND P19 GND
3 VCCO_3 P4 VCCO GND GND R6 GND
3 VCCO_3 U2 VCCO GND GND R15 GND
GND GND A1 GND GND GND U11 GND
GND GND A11 GND GND GND V3 GND
GND GND A20 GND GND GND V18 GND
GND GND B7 GND GND GND W7 GND
GND GND B14 GND GND GND W14 GND
GND GND C3 GND GND GND Y1 GND
GND GND D10 GND GND GND Y20 GND
GND GND F6 GND VCCAUX DONE V17 CONFIG
GND GND F15 GND VCCAUX PROG_B C2 CONFIG
GND GND G2 GND VCCAUX TCK D17 JTAG
GND GND G12 GND VCCAUX TDI B3 JTAG
GND GND G19 GND VCCAUX TDO B19 JTAG
GND GND H8 GND VCCAUX TMS E17 JTAG
GND GND J9 GND VCCAUX VCCAUX D11 VCCAUX
GND GND J11 GND VCCAUX VCCAUX H12 VCCAUX
GND GND K1 GND VCCAUX VCCAUX J7 VCCAUX
GND GND K8 GND VCCAUX VCCAUX K4 VCCAUX
GND GND K10 GND VCCAUX VCCAUX L17 VCCAUX
GND GND K12 GND VCCAUX VCCAUX M14 VCCAUX
GND GND K17 GND VCCAUX VCCAUX N9 VCCAUX
GND GND L4 GND VCCAUX VCCAUX U10 VCCAUX
GND GND L9 GND VCCINT VCCINT H9 VCCINT
GND GND L20 GND VCCINT VCCINT J8 VCCINT

R
Pinout Descriptions
XC3S1200E XC3S1200E
XC3S1600E FG400 XC3S1600E FG400
VCCINT VCCINT J10 VCCINT VCCINT VCCINT M13 VCCINT
VCCINT VCCINT J12 VCCINT VCCINT VCCINT N8 VCCINT
VCCINT VCCINT K9 VCCINT VCCINT VCCINT N10 VCCINT
VCCINT VCCINT L10 VCCINT

User I/Os by Bank
VCCINT VCCINT M9 VCCINT distributed between the four I/O banks on the FG400 pack-
VCCINT VCCINT M11 VCCINT age.
Table 30: User I/Os Per Bank for the XC3S250E and XC3S500E in the FG400 Package
Package Maximum
Top 0 78 43 20 1 6 8
Right 1 74 35 12 21 6 0
Bottom 2 78 30 18 24 6 0
Left 3 74 48 12 0 6 8
TOTAL 304 156 62 46 24 16
Footprint Migration Differences between the XC3S1200E and XC3S1600E FPGAs without
further consideration.
The XC3S1200E and XC3S1600E FPGAs have identical
footprints in the FG400 package. Designs can migrate

R
Pinout Descriptions
FG400 Footprint
Bank 0
Left Half of Package 1 2 3 4 5 6 7 8 9 10
(top view) I/O I/O
A GND
L30N_0
I/O
L28N_0 L28P_0 L24N_0 L24P_0
I/O L17N_0 L17P_0
GCLK11 GCLK10
I/O
I/O I/O I/O I/O I/O
B L03P_3 L30P_0
TDI VCCO_0
L26N_0 L26P_0
GND L21N_0
L21P_0
VCCO_0
I/O: Unrestricted, VREF_0
I/O
I/O I/O I/O INPUT I/O
C L03N_3
PROG_B GND
L31P_0
L29N_0
L27P_0
I/O
L22N_0 L20N_0
I/O
INPUT: User I/O or VREF_0
62 reference resistor input for
I/O
bank I/O I/O I/O I/O I/O INPUT I/O
D L04P_3 L01N_3 L01P_3
L31N_0
L29P_0 L27N_0
VCCO_0
L22P_0 L20P_0
GND
HSWAP
DUAL: Configuration pin,
46 then possible user I/O I/O
I/O
I/O INPUT INPUT I/O
I/O
E L04N_3
VCCO_3 L02N_3
L02P_3
INPUT
L25N_0 L25P_0
I/O
L18P_0
L15N_0
VREF_3 GCLK7
VREF: User I/O or input
24 voltage reference for bank I/O I/O I/O I/O
I/O
I/O I/O
F L06N_3 L06P_3 L05N_3 L05P_3
INPUT GND L23N_0
L23P_0 L18N_0
VCCO_0
VREF_0
GCLK: User I/O, input, or
16 clock buffer input I/O I/O I/O INPUT INPUT
INPUT
G INPUT GND
L07P_3 L07N_3 L08N_3
INPUT I/O
L19P_0 L19N_0
L16N_0
GCLK9
CONFIG: Dedicated
2 configuration pins I/O
I/O
I/O I/O I/O
INPUT
H INPUT
L09P_3
L09N_3 VCCO_3
L08P_3 L10P_3 L10N_3
GND VCCINT L16P_0
VREF_3 GCLK8
JTAG: Dedicated JTAG
4 port pins I/O I/O I/O I/O I/O
J L12N_3 L12P_3 L11P_3 L11N_3
INPUT
L13N_3
VCCAUX VCCINT GND VCCINT
GND: Ground I/O I/O I/O

42 INPUT I/O
K
Bank 3
GND L14N_3 L14P_3 VCCAUX L15P_3 GND VCCINT GND

VREF_3 L13P_3
LHCLK1 LHCLK0 LHCLK2
VCCO: Output voltage I/O I/O I/O
24 supply for bank L15N_3
L L16N_3 VCCO_3 L17N_3 GND INPUT VCCO_3
LHCLK3
INPUT GND VCCINT
LHCLK5 LHCLK7 IRDY2
VCCINT: Internal core I/O I/O
16 supply voltage (+1.2V) L16P_3 I/O I/O I/O I/O I/O
M LHCLK4
INPUT L17P_3
L19N_3 L19P_3 L20P_3 L18N_3 L18P_3
VCCINT GND
TRDY2 LHCLK6
VCCAUX: Auxiliary supply I/O

8 voltage (+2.5V) N
I/O I/O I/O I/O
INPUT L20N_3
I/O
VCCINT VCCAUX VCCINT
L21P_3 L21N_3 L23P_3 L23N_3 L22P_3
VREF_3
N.C.: Not connected I/O

0 P
I/O
GND INPUT VCCO_3
I/O INPUT I/O
I/O GND L16N_2
L24P_3 L25P_3 VREF_3 L22N_3 D3
GCLK15
I/O I/O
I/O I/O I/O I/O I/O INPUT L16P_2
R L24N_3 L26P_3 L27P_3 L27N_3 L25N_3
GND L09N_2
L11N_2
I/O
D4
VREF_2 GCLK14
I/O INPUT
I/O I/O I/O I/O I/O INPUT INPUT
T L28N_3
L26N_3 L29N_3
INPUT
L06P_2 L06N_2 L09P_2 L11P_2 L14P_2
L14N_2
VREF_3 VREF_2
I/O I/O
I/O I/O L03P_2 INPUT I/O I/O
U L28P_3
VCCO_3
L29P_3
L01P_2
DOUT L05P_2 L07N_2
VCCO_2
L12N_2
VCCAUX
CSO_B BUSY
I/O I/O I/O

I/O I/O L03N_2 INPUT I/O I/O I/O L18P_2
V L30N_3 L30P_3
GND L01N_2
MOSI L05N_2 L07P_2 L10N_2 L12P_2 D2
INIT_B CSI_B GCLK2
I/O I/O
INPUT I/O INPUT I/O L15P_2 L15N_2
W INPUT
L02P_2
INPUT
L04P_2
VCCO_2
L08P_2
GND
L10P_2 D7 D6
GCLK12 GCLK13
INPUT I/O I/O INPUT I/O I/O

Y GND
L02N_2 VREF_2 L04N_2
I/O
L08N_2
I/O
L13N_2 L13P_2
GND
Bank 2 DS312-4_08_031105

R
Pinout Descriptions
Bank 0
11 12 13 14 15 16 17 18 19 20 Right Half of Package
I/O I/O (top view)
I/O I/O I/O I/O I/O
GND I/O L09N_0
L09P_0 L06N_0 L04P_0 L04N_0
L03N_0
L03P_0
GND A
VREF_0 VREF_0
INPUT INPUT I/O I/O I/O

L13N_0 L13P_0 L10N_0
GND
L06P_0
VCCO_0
L01N_0
INPUT TDO INPUT B
I/O I/O
I/O I/O I/O I/O INPUT INPUT I/O
VREF_0 L11N_0 L10P_0 L07N_0 L05P_0 L02N_0 L01P_0
GND L30N_1 L30P_1 C
LDC2 LDC1
I/O
I/O I/O INPUT INPUT I/O
VCCAUX
L11P_0
VCCO_0
L07P_0 L05N_0 L02P_0
TCK L29N_1 VCCO_1
L28N_1
D
LDC0
I/O I/O
I/O INPUT INPUT INPUT I/O
L15P_0
L12N_0
I/O
L08N_0 L08P_0
I/O TMS L29P_1
VREF_1 L28P_1
E
GCLK6 HDC
I/O
L14P_0
L12P_0
I/O I/O GND
L25P_1 L27P_1 L27N_1 L26N_1 L26P_1
F
GCLK4
I/O
INPUT INPUT I/O I/O
L14N_0 GND
L10P_0 L10N_0
INPUT
L25N_1
VCCO_1 INPUT GND
L24P_1
G
GCLK5
I/O
I/O I/O I/O I/O I/O
VCCINT VCCAUX VCCINT INPUT
L22N_1 L22P_1 L23P_1 L23N_1 L21N_1
L24N_1 H
VREF_1
I/O I/O I/O

I/O I/O I/O I/O L17N_1
GND VCCINT L19N_1
L19P_1
INPUT L18P_1
L20N_1 L20P_1 L21P_1 A3
J
A0 A2 RHCLK7
I/O I/O I/O I/O
L16P_1 INPUT
L16N_1 L17P_1 K
Bank 1
VCCINT GND A6 VCCO_1 L18N_1 GND VCCO_1
RHCLK4 A5 VREF_1 A4
RHCLK5 A1 RHCLK6
IRDY1
I/O I/O I/O I/O
L15N_1
GND VCCINT GND A7 L15P_1 L14N_1 VCCAUX INPUT L13N_1 GND L
RHCLK3 A8 A9
RHCLK2 RHCLK1 VREF_1
TRDY1
I/O I/O I/O
I/O L14P_1 I/O
VCCINT GND VCCINT VCCAUX
L11P_1 A10
L12P_1 L12N_1
L13P_1
INPUT M
RHCLK0 A12 A11
I/O I/O I/O I/O I/O

D5
VCCINT GND INPUT
L11N_1 L09P_1
VCCO_1
L10P_1 L10N_1
INPUT N
INPUT INPUT I/O

L17P_2 L17N_2 I/O I/O I/O I/O
RDWR_B M2
I/O
L25N_2
INPUT
L09N_1 L07P_1 L07N_1
GND L08N_1 P
GCLK0 GCLK1 VREF_1
INPUT I/O I/O I/O I/O

VCCO_2
L20P_2
I/O
L25P_2
GND INPUT
L05P_1 L05N_1
INPUT
L08P_1
R
INPUT I/O I/O

M1 L20N_2
L23N_2
L23P_2 L28N_2
INPUT L02P_1 L02N_1 VCCO_1
L06N_1
T
VREF_2 A14 A13
I/O I/O I/O

I/O I/O I/O I/O I/O
GND
L21N_2 L24N_2
VCCO_2
L28P_2
L30P_2 L01P_1 L01N_1
L03P_1 L06P_1
U
A21 A16 A15
I/O I/O I/O

L18N_2 I/O I/O INPUT INPUT I/O
D1 L21P_2 L24P_2 L26N_2 L26P_2
L30N_2 DONE GND L03N_1
L04P_1
V
GCLK3 A20 VREF_1
I/O I/O I/O

I/O INPUT L31P_2 I/O
VCCO_2 L22N_2
L22P_2
GND I/O
L29N_2
VCCO_2
VS2
L32N_2
L04N_1
W
VREF_2 A19 CCLK

L19N_2 INPUT I/O L31N_2 L32P_2
L19P_2
DIN
I/O L27N_2 L27P_2
L29P_2 VREF_2 VS1 VS0
GND Y
M0 D0 A22 A23 A18 A17
Bank 2 DS312-4_09_031105

R
Pinout Descriptions
FG484: 484-ball Fine-pitch Ball Grid Array

The 484-ball fine-pitch ball grid array, FG484, supports the Table 31: FG484 Package Pinout
XC3S1600E FPGA.
XC3S1600E FG484
Table 31 lists all the FG484 package pins. They are sorted Bank Pin Name Ball Type
0 IO_L10P_0 F15 I/O
form a differential I/O pair appear together in the table. The
table also shows the pin number for each pin and the pin 0 IO_L11N_0 D14 I/O
0 IO_L11P_0 E14 I/O
print diagram is available for download from the Xilinx web- 0 IO_L12N_0/VREF_0 A14 VREF
site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip. 0 IO_L12P_0 A15 I/O
Pinout Table 0 IO_L13N_0 H14 I/O
0 IO_L13P_0 G14 I/O

Table 31: FG484 Package Pinout 0 IO_L15N_0 G13 I/O
XC3S1600E FG484 0 IO_L15P_0 F13 I/O
Bank Pin Name Ball Type
0 IO_L16N_0 J13 I/O
0 IO B6 I/O
0 IO_L16P_0 H13 I/O
0 IO B13 I/O
0 IO_L18N_0/GCLK5 E12 GCLK
0 IO C5 I/O
0 IO_L18P_0/GCLK4 F12 GCLK
0 IO C14 I/O
0 IO_L19N_0/GCLK7 C12 GCLK
0 IO E16 I/O
0 IO_L19P_0/GCLK6 B12 GCLK
0 IO F9 I/O
0 IO_L21N_0/GCLK11 B11 GCLK
0 IO F16 I/O
0 IO_L21P_0/GCLK10 C11 GCLK
0 IO G8 I/O
0 IO_L22N_0 D11 I/O
0 IO H10 I/O
0 IO_L22P_0 E11 I/O
0 IO H15 I/O
0 IO_L24N_0 A9 I/O
0 IO J11 I/O
0 IO_L24P_0 A10 I/O
0 IO/VREF_0 G12 VREF
0 IO_L25N_0/VREF_0 D10 VREF
0 IO_L01N_0 C18 I/O
0 IO_L25P_0 C10 I/O
0 IO_L01P_0 C19 I/O
0 IO_L27N_0 H8 I/O
0 IO_L03N_0/VREF_0 A20 VREF
0 IO_L27P_0 H9 I/O
0 IO_L03P_0 A21 I/O
0 IO_L28N_0 C9 I/O
0 IO_L04N_0 A19 I/O
0 IO_L28P_0 B9 I/O
0 IO_L04P_0 A18 I/O
0 IO_L29N_0 E9 I/O
0 IO_L06N_0 C16 I/O
0 IO_L29P_0 D9 I/O
0 IO_L06P_0 D16 I/O
0 IO_L30N_0 B8 I/O
0 IO_L07N_0 A16 I/O
0 IO_L30P_0 A8 I/O
0 IO_L07P_0 A17 I/O
0 IO_L32N_0/VREF_0 F7 VREF
0 IO_L09N_0/VREF_0 B15 VREF
0 IO_L32P_0 F8 I/O
0 IO_L09P_0 C15 I/O
0 IO_L33N_0 A6 I/O
0 IO_L10N_0 G15 I/O

R
Pinout Descriptions
XC3S1600E FG484 XC3S1600E FG484
0 IO_L33P_0 A7 I/O 0 VCCO_0 B5 VCCO
0 IO_L35N_0 A4 I/O 0 VCCO_0 B10 VCCO
0 IO_L35P_0 A5 I/O 0 VCCO_0 B14 VCCO
0 IO_L36N_0 E7 I/O 0 VCCO_0 B18 VCCO
0 IO_L36P_0 D7 I/O 0 VCCO_0 E8 VCCO
0 IO_L38N_0/VREF_0 D6 VREF 0 VCCO_0 F14 VCCO
0 IO_L38P_0 D5 I/O 0 VCCO_0 G11 VCCO
0 IO_L39N_0 B4 I/O 1 IO_L01N_1/A15 Y22 DUAL
0 IO_L39P_0 B3 I/O 1 IO_L01P_1/A16 AA22 DUAL
0 IO_L40N_0/HSWAP D4 DUAL 1 IO_L02N_1/A13 W21 DUAL

0 IO_L40P_0 C4 I/O 1 IO_L02P_1/A14 Y21 DUAL
0 IP B19 INPUT 1 IO_L03N_1/VREF_1 W20 VREF
0 IP E6 INPUT 1 IO_L03P_1 V20 I/O
0 IP_L02N_0 D17 INPUT 1 IO_L04N_1 U19 I/O
0 IP_L02P_0 D18 INPUT 1 IO_L04P_1 V19 I/O
0 IP_L05N_0 C17 INPUT 1 IO_L05N_1 V22 I/O
0 IP_L05P_0 B17 INPUT 1 IO_L05P_1 W22 I/O
0 IP_L08N_0 E15 INPUT 1 IO_L06N_1 T19 I/O
0 IP_L08P_0 D15 INPUT 1 IO_L06P_1 T18 I/O
0 IP_L14N_0 D13 INPUT 1 IO_L07N_1/VREF_1 U20 VREF
0 IP_L14P_0 C13 INPUT 1 IO_L07P_1 U21 I/O
0 IP_L17N_0 A12 INPUT 1 IO_L08N_1 T22 I/O
0 IP_L17P_0 A13 INPUT 1 IO_L08P_1 U22 I/O
0 IP_L20N_0/GCLK9 H11 GCLK 1 IO_L09N_1 R19 I/O
0 IP_L20P_0/GCLK8 H12 GCLK 1 IO_L09P_1 R18 I/O
0 IP_L23N_0 F10 INPUT 1 IO_L10N_1 R16 I/O
0 IP_L23P_0 F11 INPUT 1 IO_L10P_1 T16 I/O
0 IP_L26N_0 G9 INPUT 1 IO_L11N_1 R21 I/O
0 IP_L26P_0 G10 INPUT 1 IO_L11P_1 R20 I/O
0 IP_L31N_0 C8 INPUT 1 IO_L12N_1/VREF_1 P18 VREF
0 IP_L31P_0 D8 INPUT 1 IO_L12P_1 P17 I/O

0 IP_L34N_0 C7 INPUT 1 IO_L13N_1 P22 I/O
0 IP_L34P_0 C6 INPUT 1 IO_L13P_1 R22 I/O
0 IP_L37N_0 A3 INPUT 1 IO_L14N_1 P15 I/O
0 IP_L37P_0 A2 INPUT 1 IO_L14P_1 P16 I/O

R
Pinout Descriptions
XC3S1600E FG484 XC3S1600E FG484
1 IO_L15N_1 N18 I/O 1 IO_L30N_1 H17 I/O
1 IO_L15P_1 N19 I/O 1 IO_L30P_1 G17 I/O
1 IO_L16N_1/A11 N16 DUAL 1 IO_L31N_1 F22 I/O
1 IO_L16P_1/A12 N17 DUAL 1 IO_L31P_1 G22 I/O
1 IO_L17N_1/VREF_1 M20 VREF 1 IO_L32N_1 F20 I/O
1 IO_L17P_1 N20 I/O 1 IO_L32P_1 G20 I/O
1 IO_L18N_1/A9/RHCLK1 M22 RHCLK/ 1 IO_L33N_1 G18 I/O

DUAL
1 IO_L33P_1 G19 I/O
1 IO_L18P_1/A10/RHCLK0 N22 RHCLK/
DUAL 1 IO_L34N_1 D22 I/O
1 IO_L19N_1/A7/RHCLK3/ M16 RHCLK/ 1 IO_L34P_1 E22 I/O

TRDY1 DUAL 1 IO_L35N_1 F19 I/O
1 IO_L19P_1/A8/RHCLK2 M15 RHCLK/ 1 IO_L35P_1 F18 I/O
DUAL
1 IO_L36N_1 E20 I/O
1 IO_L20N_1/A5/RHCLK5 L21 RHCLK/
DUAL 1 IO_L36P_1 E19 I/O
1 IO_L20P_1/A6/RHCLK4/ L20 RHCLK/ 1 IO_L37N_1/LDC0 C21 DUAL

IRDY1 DUAL
1 IO_L37P_1/HDC C22 DUAL
1 IO_L21N_1/A3/RHCLK7 L19 RHCLK/
1 IO_L38N_1/LDC2 B21 DUAL
DUAL
1 IO_L38P_1/LDC1 B22 DUAL
1 IO_L21P_1/A4/RHCLK6 L18 RHCLK/
DUAL 1 IP D20 INPUT
1 IO_L22N_1/A1 K22 DUAL 1 IP F21 INPUT
1 IO_L22P_1/A2 L22 DUAL 1 IP G16 INPUT
1 IO_L23N_1/A0 K17 DUAL 1 IP H16 INPUT
1 IO_L23P_1 K16 I/O 1 IP J16 INPUT
1 IO_L24N_1 K19 I/O 1 IP J22 INPUT
1 IO_L24P_1 K18 I/O 1 IP K20 INPUT
1 IO_L25N_1 K15 I/O 1 IP L15 INPUT
1 IO_L25P_1 J15 I/O 1 IP M18 INPUT
1 IO_L26N_1 J20 I/O 1 IP N15 INPUT
1 IO_L26P_1 J21 I/O 1 IP N21 INPUT
1 IO_L27N_1 J17 I/O 1 IP P20 INPUT
1 IO_L27P_1 J18 I/O 1 IP R15 INPUT
1 IO_L28N_1/VREF_1 H21 VREF 1 IP T17 INPUT
1 IO_L28P_1 H22 I/O 1 IP T20 INPUT
1 IO_L29N_1 H20 I/O 1 IP U18 INPUT
1 IO_L29P_1 H19 I/O 1 IP/VREF_1 D21 VREF

R
Pinout Descriptions
XC3S1600E FG484 XC3S1600E FG484
1 IP/VREF_1 L17 VREF 2 IO_L11P_2 AA8 I/O
1 VCCO_1 E21 VCCO 2 IO_L12N_2 W9 I/O
1 VCCO_1 H18 VCCO 2 IO_L12P_2 V9 I/O
1 VCCO_1 K21 VCCO 2 IO_L13N_2/VREF_2 R9 VREF
1 VCCO_1 L16 VCCO 2 IO_L13P_2 T9 I/O
1 VCCO_1 P21 VCCO 2 IO_L14N_2 AB9 I/O
1 VCCO_1 R17 VCCO 2 IO_L14P_2 AB10 I/O
1 VCCO_1 V21 VCCO 2 IO_L16N_2 U10 I/O
2 IO Y8 I/O 2 IO_L16P_2 T10 I/O
2 IO Y9 I/O 2 IO_L17N_2 R10 I/O

2 IO AA10 I/O 2 IO_L17P_2 P10 I/O
2 IO AB5 I/O 2 IO_L19N_2/D6/GCLK13 U11 DUAL/

GCLK
2 IO AB13 I/O
2 IO_L19P_2/D7/GCLK12 V11 DUAL/
2 IO AB14 I/O GCLK
2 IO AB16 I/O 2 IO_L20N_2/D3/GCLK15 T11 DUAL/
2 IO AB18 I/O GCLK
2 IO/D5 AB11 DUAL 2 IO_L20P_2/D4/GCLK14 R11 DUAL/

GCLK
2 IO/M1 AA12 DUAL
2 IO_L22N_2/D1/GCLK3 W12 DUAL/
2 IO/VREF_2 AB4 VREF GCLK
2 IO/VREF_2 AB21 VREF 2 IO_L22P_2/D2/GCLK2 Y12 DUAL/
GCLK
2 IO_L01N_2/INIT_B AB3 DUAL
2 IO_L23N_2/DIN/D0 U12 DUAL
2 IO_L01P_2/CSO_B AA3 DUAL
2 IO_L23P_2/M0 V12 DUAL
2 IO_L03N_2/MOSI/CSI_B Y5 DUAL
2 IO_L25N_2 Y13 I/O
2 IO_L03P_2/DOUT/BUSY W5 DUAL
2 IO_L25P_2 W13 I/O
2 IO_L04N_2 W6 I/O
2 IO_L26N_2/VREF_2 U14 VREF
2 IO_L04P_2 V6 I/O
2 IO_L26P_2 U13 I/O
2 IO_L06N_2 W7 I/O
2 IO_L27N_2 T14 I/O
2 IO_L06P_2 Y7 I/O
2 IO_L27P_2 R14 I/O
2 IO_L07N_2 U7 I/O
2 IO_L28N_2 Y14 I/O
2 IO_L07P_2 V7 I/O
2 IO_L28P_2 AA14 I/O
2 IO_L09N_2/VREF_2 V8 VREF
2 IO_L29N_2 W14 I/O
2 IO_L09P_2 W8 I/O
2 IO_L29P_2 V14 I/O
2 IO_L10N_2 T8 I/O
2 IO_L30N_2 AB15 I/O
2 IO_L10P_2 U8 I/O
2 IO_L30P_2 AA15 I/O
2 IO_L11N_2 AB8 I/O

R
Pinout Descriptions
XC3S1600E FG484 XC3S1600E FG484
2 IO_L32N_2 W15 I/O 2 IP_L37N_2 AA19 INPUT
2 IO_L32P_2 Y15 I/O 2 IP_L37P_2 AB19 INPUT
2 IO_L33N_2 U16 I/O 2 VCCO_2 T12 VCCO
2 IO_L33P_2 V16 I/O 2 VCCO_2 U9 VCCO
2 IO_L35N_2/A22 AB17 DUAL 2 VCCO_2 V15 VCCO
2 IO_L35P_2/A23 AA17 DUAL 2 VCCO_2 AA5 VCCO
2 IO_L36N_2 W17 I/O 2 VCCO_2 AA9 VCCO
2 IO_L36P_2 Y17 I/O 2 VCCO_2 AA13 VCCO
2 IO_L38N_2/A20 Y18 DUAL 2 VCCO_2 AA18 VCCO
2 IO_L38P_2/A21 W18 DUAL 3 IO_L01N_3 C1 I/O

2 IO_L39N_2/VS1/A18 AA20 DUAL 3 IO_L01P_3 C2 I/O
2 IO_L39P_2/VS2/A19 AB20 DUAL 3 IO_L02N_3/VREF_3 D2 VREF
2 IO_L40N_2/CCLK W19 DUAL 3 IO_L02P_3 D3 I/O
2 IO_L40P_2/VS0/A17 Y19 DUAL 3 IO_L03N_3 E3 I/O
2 IP V17 INPUT 3 IO_L03P_3 E4 I/O
2 IP AB2 INPUT 3 IO_L04N_3 E1 I/O
2 IP_L02N_2 AA4 INPUT 3 IO_L04P_3 D1 I/O
2 IP_L02P_2 Y4 INPUT 3 IO_L05N_3 F4 I/O
2 IP_L05N_2 Y6 INPUT 3 IO_L05P_3 F3 I/O
2 IP_L05P_2 AA6 INPUT 3 IO_L06N_3 G5 I/O
2 IP_L08N_2 AB7 INPUT 3 IO_L06P_3 G4 I/O
2 IP_L08P_2 AB6 INPUT 3 IO_L07N_3 F1 I/O
2 IP_L15N_2 Y10 INPUT 3 IO_L07P_3 G1 I/O
2 IP_L15P_2 W10 INPUT 3 IO_L08N_3/VREF_3 G6 VREF
2 IP_L18N_2/VREF_2 AA11 VREF 3 IO_L08P_3 G7 I/O
2 IP_L18P_2 Y11 INPUT 3 IO_L09N_3 H4 I/O
2 IP_L21N_2/M2/GCLK1 P12 DUAL/ 3 IO_L09P_3 H5 I/O

GCLK
3 IO_L10N_3 H2 I/O
2 IP_L21P_2/RDWR_B/ R12 DUAL/
GCLK0 GCLK 3 IO_L10P_3 H3 I/O
2 IP_L24N_2 R13 INPUT 3 IO_L11N_3 H1 I/O
2 IP_L24P_2 T13 INPUT 3 IO_L11P_3 J1 I/O
2 IP_L31N_2/VREF_2 T15 VREF 3 IO_L12N_3 J6 I/O
2 IP_L31P_2 U15 INPUT 3 IO_L12P_3 J5 I/O
2 IP_L34N_2 Y16 INPUT 3 IO_L13N_3/VREF_3 J3 VREF
2 IP_L34P_2 W16 INPUT 3 IO_L13P_3 K3 I/O

R
Pinout Descriptions
XC3S1600E FG484 XC3S1600E FG484
3 IO_L14N_3 J8 I/O 3 IO_L31P_3 U1 I/O
3 IO_L14P_3 K8 I/O 3 IO_L32N_3 T4 I/O
3 IO_L15N_3 K4 I/O 3 IO_L32P_3 T5 I/O
3 IO_L15P_3 K5 I/O 3 IO_L33N_3 W1 I/O
3 IO_L16N_3 K1 I/O 3 IO_L33P_3 V1 I/O
3 IO_L16P_3 L1 I/O 3 IO_L34N_3 U4 I/O
3 IO_L17N_3 L7 I/O 3 IO_L34P_3 U3 I/O
3 IO_L17P_3 K7 I/O 3 IO_L35N_3 V4 I/O
3 IO_L18N_3/LHCLK1 L5 LHCLK 3 IO_L35P_3 V3 I/O
3 IO_L18P_3/LHCLK0 M5 LHCLK 3 IO_L36N_3/VREF_3 W3 VREF

3 IO_L19N_3/LHCLK3/IRDY2 M8 LHCLK 3 IO_L36P_3 W2 I/O
3 IO_L19P_3/LHCLK2 L8 LHCLK 3 IO_L37N_3 Y2 I/O
3 IO_L20N_3/LHCLK5 N1 LHCLK 3 IO_L37P_3 Y1 I/O
3 IO_L20P_3/LHCLK4/TRDY2 M1 LHCLK 3 IO_L38N_3 AA1 I/O
3 IO_L21N_3/LHCLK7 M4 LHCLK 3 IO_L38P_3 AA2 I/O
3 IO_L21P_3/LHCLK6 M3 LHCLK 3 IP F2 INPUT
3 IO_L22N_3 N6 I/O 3 IP F5 INPUT
3 IO_L22P_3 N7 I/O 3 IP G3 INPUT
3 IO_L23N_3 P8 I/O 3 IP H7 INPUT
3 IO_L23P_3 N8 I/O 3 IP J7 INPUT
3 IO_L24N_3/VREF_3 N4 VREF 3 IP K2 INPUT
3 IO_L24P_3 N5 I/O 3 IP K6 INPUT
3 IO_L25N_3 P2 I/O 3 IP M2 INPUT
3 IO_L25P_3 P1 I/O 3 IP M6 INPUT
3 IO_L26N_3 R7 I/O 3 IP N3 INPUT
3 IO_L27N_3 P6 I/O 3 IP R8 INPUT
3 IO_L27P_3 P5 I/O 3 IP T1 INPUT
3 IO_L28N_3 R2 I/O 3 IP T7 INPUT
3 IO_L28P_3 R1 I/O 3 IP U5 INPUT
3 IO_L29N_3 R3 I/O 3 IP W4 INPUT

3 IO_L29P_3 R4 I/O 3 IP/VREF_3 L3 VREF
3 IO_L30N_3 T6 I/O 3 IP/VREF_3 T3 VREF
3 IO_L30P_3 R6 I/O 3 VCCO_3 E2 VCCO
3 IO_L31N_3 U2 I/O 3 VCCO_3 H6 VCCO

R
Pinout Descriptions
XC3S1600E FG484 XC3S1600E FG484
3 VCCO_3 J2 VCCO GND GND P4 GND
3 VCCO_3 M7 VCCO GND GND P9 GND
3 VCCO_3 N2 VCCO GND GND P11 GND
3 VCCO_3 R5 VCCO GND GND P14 GND
3 VCCO_3 V2 VCCO GND GND P19 GND
GND GND A1 GND GND GND T2 GND
GND GND A11 GND GND GND T21 GND
GND GND A22 GND GND GND U6 GND
GND GND B7 GND GND GND U17 GND
GND GND B16 GND GND GND V10 GND

GND GND C3 GND GND GND V13 GND
GND GND E10 GND GND GND Y20 GND
GND GND E13 GND GND GND AA7 GND
GND GND F6 GND GND GND AA16 GND
GND GND F17 GND GND GND AB1 GND
GND GND G2 GND GND GND AB12 GND
GND GND G21 GND GND GND AB22 GND
GND GND J4 GND VCCAUX DONE AA21 CONFIG
GND GND J9 GND VCCAUX PROG_B B1 CONFIG
GND GND J12 GND VCCAUX TCK E17 JTAG
GND GND J14 GND VCCAUX TDI B2 JTAG
GND GND J19 GND VCCAUX TDO B20 JTAG
GND GND K10 GND VCCAUX TMS D19 JTAG
GND GND K12 GND VCCAUX VCCAUX D12 VCCAUX
GND GND L2 GND VCCAUX VCCAUX E5 VCCAUX
GND GND L6 GND VCCAUX VCCAUX E18 VCCAUX
GND GND L9 GND VCCAUX VCCAUX K14 VCCAUX
GND GND L13 GND VCCAUX VCCAUX L4 VCCAUX
GND GND M10 GND VCCAUX VCCAUX M19 VCCAUX
GND GND M14 GND VCCAUX VCCAUX N9 VCCAUX

GND GND M17 GND VCCAUX VCCAUX V5 VCCAUX
GND GND M21 GND VCCAUX VCCAUX V18 VCCAUX
GND GND N11 GND VCCAUX VCCAUX W11 VCCAUX
GND GND N13 GND VCCINT VCCINT J10 VCCINT

R
Pinout Descriptions
XC3S1600E FG484 XC3S1600E FG484
VCCINT VCCINT K9 VCCINT VCCINT VCCINT M13 VCCINT
VCCINT VCCINT L10 VCCINT VCCINT VCCINT N14 VCCINT
VCCINT VCCINT L11 VCCINT VCCINT VCCINT P13 VCCINT

User I/Os by Bank
VCCINT VCCINT M9 VCCINT distributed between the four I/O banks on the FG484 pack-
VCCINT VCCINT M11 VCCINT age.
VCCINT VCCINT M12 VCCINT
Table 32: User I/Os Per Bank for the XC3S1600E in the FG484 Package
Package Maximum
Top 0 94 56 22 1 7 8
Right 1 94 50 16 21 7 0
Bottom 2 94 45 18 24 7 0
Left 3 94 63 16 0 7 8
TOTAL 376 214 72 46 28 16
Footprint Migration Differences

The XC3S1600E FPGA is the only Spartan-3E device
offered in the FG484 package.

R
Pinout Descriptions
FG484 Footprint Bank 0

1 2 3 4 5 6 7 8 9 10 11
Left Half of Package
INPUT INPUT I/O I/O I/O I/O I/O I/O I/O
(top view) A GND
L37P_0 L37N_0 L35N_0 L35P_0 L33N_0 L33P_0 L30P_0 L24N_0 L24P_0
GND
I/O
I/O I/O I/O I/O
B PROG_B TDI
L39P_0 L39N_0
VCCO_0 I/O GND
L30N_0 L28P_0
VCCO_0 L21N_0
GCLK11
I/O: Unrestricted,
214 general-purpose user I/O I/O I/O I/O INPUT INPUT INPUT I/O I/O
I/O
C L01N_3 L01P_3
GND
L40P_0
I/O
L34P_0 L34N_0 L31N_0 L28N_0 L25P_0
L21P_0
GCLK10
INPUT: User I/O or I/O I/O I/O I/O
I/O I/O I/O I/O INPUT I/O I/O
72 reference resistor input for D L04P_3
L02N_3
L02P_3
L40N_0
L38P_0
L38N_0
L36P_0 L31P_0 L29P_0
L25N_0
L22N_0
VREF_3 HSWAP VREF_0 VREF_0
bank
DUAL: Configuration pin, E L04N_3
VCCO_3
L03N_3 L03P_3
VCCAUX INPUT
L36N_0
VCCO_0
L29N_0
GND
L22P_0
46 then possible user I/O
I/O
I/O I/O I/O I/O INPUT INPUT
F L07N_3
INPUT
L05P_3 L05N_3
INPUT GND L32N_0
L32P_0
I/O
L23N_0 L23P_0
VREF: User I/O or input VREF_0
I/O
I/O I/O I/O I/O INPUT INPUT
G L07P_3
GND INPUT
L06P_3 L06N_3
L08N_3
L08P_3
I/O
L26N_0 L26P_0
VCCO_0
GCLK: User I/O, input, or VREF_3
16 clock buffer input INPUT
H L11N_3 L10N_3 L10P_3 L09N_3 L09P_3
VCCO_3 INPUT
L27N_0 L27P_0
I/O L20N_0
GCLK9
CONFIG: Dedicated
2 configuration pins I/O
I/O I/O I/O I/O
J L11P_3
VCCO_3 L13N_3 GND
L12P_3 L12N_3
INPUT
L14N_3
GND VCCINT I/O
VREF_3
JTAG: Dedicated JTAG
4 port pins I/O I/O I/O I/O I/O I/O
K L16N_3
INPUT
L13P_3 L15N_3 L15P_3
INPUT
L17P_3 L14P_3
VCCINT GND VCCINT
GND: Ground I/O I/O

48 L
I/O INPUT I/O
Bank 3
GND VCCAUX L18N_3 GND L19P_3 GND VCCINT VCCINT

L16P_3 VREF_3 L17N_3
LHCLK1 LHCLK2
VCCO: Output voltage I/O I/O I/O I/O I/O

28 supply for bank M L20P_3 INPUT L21P_3 L21N_3 L18P_3 INPUT VCCO_3 L19N_3 VCCINT GND VCCINT
LHCLK4 LHCLK3
TRDY2 LHCLK6 LHCLK7 LHCLK0 IRDY2
VCCINT: Internal core I/O I/O

I/O I/O I/O I/O
16 supply voltage (+1.2V)
N L20N_3 VCCO_3 INPUT L24N_3
L24P_3 L22N_3 L22P_3 L23P_3
VCCAUX VCCINT GND
LHCLK5 VREF_3
VCCAUX: Auxiliary supply I/O I/O I/O I/O I/O I/O I/O
10 P L25P_3 L25N_3
INPUT GND
L27P_3 L27N_3 L26P_3 L23N_3
GND
L17P_2
GND
voltage (+2.5V)
I/O I/O
I/O I/O I/O I/O I/O I/O I/O L20P_2
N.C.: Not connected R L28P_3 L28N_3 L29N_3 L29P_3
VCCO_3
L30P_3 L26N_3
INPUT L13N_2
L17N_2 D4
0 VREF_2 GCLK14
I/O
INPUT I/O I/O I/O I/O I/O I/O L20N_2
T INPUT GND
VREF_3 L32N_3 L32P_3 L30N_3
INPUT
L10N_2 L13P_2 L16P_2 D3
GCLK15
I/O
I/O I/O I/O I/O I/O I/O I/O L19N_2
U L31P_3 L31N_3 L34P_3 L34N_3
INPUT GND
L07N_2 L10P_2
VCCO_2
L16N_2 D6
GCLK13
I/O I/O
I/O I/O I/O I/O I/O I/O L19P_2
V L33P_3
VCCO_3
L35P_3 L35N_3
VCCAUX
L04P_2 L07P_2
L09N_2
L12P_2
GND
D7
VREF_2 GCLK12
I/O I/O
I/O I/O L03P_2 I/O I/O I/O I/O INPUT
W L33N_3 L36P_3
L36N_3 INPUT
DOUT L04N_2 L06N_2 L09P_2 L12N_2 L15P_2
VCCAUX
VREF_3 BUSY
I/O
I/O I/O INPUT L03N_2 INPUT I/O INPUT INPUT
Y L37P_3 L37N_3
GND
L02P_2 MOSI L05N_2 L06P_2
I/O I/O
L15N_2 L18P_2
CSI_B
A I/O INPUT
I/O I/O INPUT INPUT I/O
L01P_2 VCCO_2 GND VCCO_2 I/O L18N_2
A L38N_3 L38P_3 L02N_2 L05P_2 L11P_2
CSO_B VREF_2
A I/O
I/O INPUT INPUT I/O I/O I/O I/O
GND INPUT L01N_2 I/O
B INIT_B
VREF_2 L08P_2 L08N_2 L11N_2 L14N_2 L14P_2 D5
Bank 2 DS312_10_031105

R
Pinout Descriptions
Bank 0
12 13 14 15 16 17 18 19 20 21 22
Right Half of Package
I/O I/O
INPUT
L17N_0
INPUT
L17P_0
L12N_0
I/O
L12P_0
I/O
L07N_0
I/O
L07P_0
I/O
L04P_0
I/O
L04N_0
L03N_0
I/O
L03P_0
GND A (top view)
VREF_0 VREF_0
I/O I/O I/O I/O

INPUT
L19P_0 I/O VCCO_0 L09N_0 GND
L05P_0
VCCO_0 INPUT TDO L38N_1 L38P_1 B
GCLK6 VREF_0 LDC2 LDC1
I/O I/O I/O

INPUT I/O I/O INPUT I/O I/O
L19N_0
L14P_0
I/O
L09P_0 L06N_0 L05N_0 L01N_0 L01P_0
GND L37N_1 L37P_1 C
GCLK7 LDC0 HDC
INPUT I/O INPUT I/O INPUT INPUT INPUT I/O

VCCAUX
L14N_0 L11N_0 L08P_0 L06P_0 L02N_0 L02P_0
TMS INPUT
VREF_1 L34N_1
D
I/O
L18N_0 GND
L11P_0 L08N_0
I/O TCK VCCAUX
L36P_1 L36N_1
VCCO_1
L34P_1
E
GCLK5
I/O
L18P_0
L15P_0
VCCO_0
L10P_0
I/O GND
L35P_1 L35N_1 L32N_1
INPUT
L31N_1
F
GCLK4
I/O I/O I/O I/O I/O I/O I/O I/O I/O

VREF_0 L15N_0 L13P_0 L10N_0
INPUT
L30P_1 L33N_1 L33P_1 L32P_1
GND
L31P_1
G
INPUT I/O
L20P_0
L16P_0 L13N_0
I/O INPUT
L30N_1
VCCO_1
L29P_1 L29N_1
L28N_1
L28P_1
H
GCLK8 VREF_1

GND
L16N_0
GND
L25P_1
INPUT
L27N_1 L27P_1
GND
L26N_1 L26P_1
INPUT J
I/O I/O
I/O I/O I/O I/O
GND VCCINT VCCAUX
L25N_1 L23P_1
L23N_1
L24P_1 L24N_1
INPUT VCCO_1 L22N_1 K
A0 A1
I/O I/O I/O I/O I/O

INPUT L20P_1
VCCINT GND VCCINT INPUT VCCO_1 L21P_1 L21N_1 A6 L20N_1 L22P_1 L Bank 1
VREF_1 A4 A3 RHCLK4 A5
RHCLK6 RHCLK7 RHCLK5 A2
IRDY1
I/O I/O I/O I/O
L19N_1
VCCINT VCCINT GND L19P_1 A7 GND INPUT VCCAUX L17N_1 GND L18N_1 M
A8 RHCLK3 A9
RHCLK2 TRDY1 VREF_1 RHCLK1
I/O I/O I/O

I/O I/O I/O L18P_1
VCCINT GND VCCINT INPUT L16N_1 L16P_1
L15N_1 L15P_1 L17P_1
INPUT
A10
N
A11 A12 RHCLK0
INPUT I/O
L21N_2 I/O I/O I/O I/O
M2
VCCINT GND
L14N_1 L14P_1 L12P_1
L12N_1 GND INPUT VCCO_1
L13N_1
P
GCLK1 VREF_1
INPUT
L21P_2 INPUT I/O I/O I/O I/O I/O I/O I/O
RDWR_B L24N_2 L27P_2
INPUT
L10N_1
VCCO_1
L09P_1 L09N_1 L11P_1 L11N_1 L13P_1
R
GCLK0
INPUT
VCCO_2
L24P_2 L27N_2
L31N_2
L10P_1
INPUT
L06P_1 L06N_1
INPUT GND
L08N_1
T
VREF_2
I/O I/O I/O

L23N_2 I/O INPUT I/O I/O I/O I/O
DIN L26P_2
L26N_2
L31P_2 L33N_2
GND INPUT
L04N_1
L07N_1
L07P_1 L08P_1
U
D0 VREF_2 VREF_1
I/O
I/O I/O I/O I/O I/O
L23P_2 GND
L29P_2
VCCO_2
L33P_2
INPUT VCCAUX
L04P_1 L03P_1
VCCO_1
L05N_1
V
M0
I/O I/O I/O I/O I/O

L22N_2 I/O I/O I/O INPUT I/O I/O
D1 L25P_2 L29N_2 L32N_2 L34P_2 L36N_2
L38P_2 L40N_2 L03N_1 L02N_1
L05P_1
W
GCLK3 A21 CCLK VREF_1 A13
I/O I/O I/O I/O I/O

L22P_2 I/O I/O I/O INPUT I/O L40P_2
D2 L25N_2 L28N_2 L32P_2 L34N_2 L36P_2
L38N_2
VS0
GND L02P_1 L01N_1 Y
GCLK2 A20 A17 A14 A15
I/O I/O I/O

I/O I/O I/O INPUT L39N_2
A
VCCO_2 GND L35P_2 VCCO_2 DONE L01P_1
M1 L28P_2 L30P_2 L37N_2 VS1 A
A23 A18 A16
I/O I/O
I/O INPUT L39P_2 I/O A
GND I/O I/O I/O L35N_2 I/O GND
L30N_2
A22
L37P_2 VS2
A19
VREF_2 B
Bank 2 DS312_11_031105

R
Pinout Descriptions
Revision History

03/21/05 1.1 Added XC3S250E in the CP132 package to Table 6. Corrected number of differential I/O
pairs on CP132. Added pinout and footprint information for the CP132, FG400, and FG484
packages. Removed IRDY and TRDY pins from the VQ100, TQ144, and PQ208 packages.



Spartan-3E FPGA Family: Complete Data Sheet: Introduction and Ordering Information DC and Switching Characteristics

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Spartan-3E FPGA Family: Complete Data Sheet: Introduction and Ordering Information DC and Switching Characteristics

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R Spartan-3E FPGA Family:

DS312-2 (v1.1) March 21, 2005

DS312 March 21, 2005 www.xilinx.com 1

DS312-1 (v1.1) March 21, 2005 www.xilinx.com 1

Introduction and Ordering Information

Figure 1: Spartan-3E Family Architecture

2 www.xilinx.com DS312-1 (v1.1) March 21, 2005

Introduction and Ordering Information

Configuration I/O Capabilities

Table 2: Available User I/Os and Differential (Diff) I/O Pairs

XC3S250E 66 30 92 41 108 40 158 65 172 68 - - - - - -

XC3S500E - - 92 41 - - 158 65 190 77 232 92 - - - -

XC3S1200E - - - - - - - - 190 77 250 99 304 124 - -

XC3S1600E - - - - - - - - - - 250 99 304 124 376 156

DS312-1 (v1.1) March 21, 2005 www.xilinx.com 3

Introduction and Ordering Information

Mask Revision Code

SPARTAN Process Technology

Figure 2: Spartan-3E QFP Example Package Marking

Mask Revision Code

Figure 3: Spartan-3E BGA Example Package Marking

Ball A1 3S250E Device Type

Lot Code F1234567-0525 Date Code

Figure 4: Spartan-3E CP132 and CPG132 Example Package Marking

4 www.xilinx.com DS312-1 (v1.1) March 21, 2005

Introduction and Ordering Information

Example: XC3S250E -4 FT 256 C

Package Type Number of Pins DS312_03_011405

Example: XC3S250E -4 FT G 256 C

DS312-1 (v1.1) March 21, 2005 www.xilinx.com 5

Introduction and Ordering Information

Date Version Revision

The Spartan-3E Family Data Sheet

6 www.xilinx.com DS312-1 (v1.1) March 21, 2005

R Spartan-3E FPGA Family:

Introduction the delay element, there are alternate routes through a

DS312-2 (v1.1) March 21, 2005 www.xilinx.com 1

Figure 1: Simplified IOB Diagram

2 www.xilinx.com DS312-2 (v1.1) March 21, 2005

Synchronous input (IQ1)

Synchronous input (IQ2)

Asynchronous input (I) DS312-2_18_022205

Figure 2: Input Delay Elements

DS312-2 (v1.1) March 21, 2005 www.xilinx.com 3

Storage Element Functions This is accomplished by taking data synchronized to the

Table 1: Storage Element Signal Description

Table 2: Storage Element Options

4 www.xilinx.com DS312-2 (v1.1) March 21, 2005

Table 2: Storage Element Options

Double-Data-Rate Transmission The storage-element pair on the Three-State path (TFF1

DDR MUX Q DDR MUX Q

Figure 3: Two Methods for Clocking the DDR Register

DS312-2 (v1.1) March 21, 2005 www.xilinx.com 5

Register Cascade Feature

PAD d d+1 d+2 d+3 d+4 d+5 d+6 d+7 d+8

Figure 4: Input DDR (without Cascade Feature)

6 www.xilinx.com DS312-2 (v1.1) March 21, 2005

D1 d d+2 d+4 d+6 d+8 d+10 D1 d d+2 d+4 d+6 d+8