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    Es MCQ - DMA

    Uploaded by

    Uma
    The document discusses Direct Memory Access (DMA) controllers and how they differ from interrupt-based I/O. DMA controllers allow I/O devices to access main memory directly without intervention from the CPU. DMA controllers contain registers that provide signals, addresses and control to initiate data transfers between I/O devices and memory. During a DMA transfer, the CPU is notified via an interrupt signal and may be temporarily suspended to allow the transfer to occur.

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    Es MCQ - DMA

    Uploaded by

    Uma
    491 views4 pages
    The document discusses Direct Memory Access (DMA) controllers and how they differ from interrupt-based I/O. DMA controllers allow I/O devices to access main memory directly without intervention from the CPU. DMA controllers contain registers that provide signals, addresses and control to initiate data transfers between I/O devices and memory. During a DMA transfer, the CPU is notified via an interrupt signal and may be temporarily suspended to allow the transfer to occur.

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    es mcq -DMA

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    The document discusses Direct Memory Access (DMA) controllers and how they differ from interrupt-based I/O. DMA controllers allow I/O devices to access main memory directly without intervention from the CPU. DMA controllers contain registers that provide signals, addresses and control to initiate data transfers between I/O devices and memory. During a DMA transfer, the CPU is notified via an interrupt signal and may be temporarily suspended to allow the transfer to occur.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    491 views4 pages

    Es MCQ - DMA

    Uploaded by

    Uma
    The document discusses Direct Memory Access (DMA) controllers and how they differ from interrupt-based I/O. DMA controllers allow I/O devices to access main memory directly without intervention from the CPU. DMA controllers contain registers that provide signals, addresses and control to initiate data transfers between I/O devices and memory. During a DMA transfer, the CPU is notified via an interrupt signal and may be temporarily suspended to allow the transfer to occur.

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    1.

    The DMA differs from the interrupt mode by


    a) The involvement of the processor for the operation
    b) The method accessing the I/O devices
    c) The amount of data transfer possible
    d) Both a and c

    Answer: Both a and c

    2. The DMA transfers are performed by a control circuit


    called as
    a) Device interface
    b) DMA controller
    c) Data controller
    d) Overlooker
    Answer: DMA controller

    3. In DMA transfers, the required signals and addresses are


    given by the
    a) Processor
    b) Device drivers
    c) DMA controllers
    d) The program itself

    Answer: DMA controllers


    4. After the complition of the DMA transfer the processor is
    notified by
    a) Acknowledge signal
    b) Interrupt signal
    c) WMFC signal
    d) None of the above

    Answer: Interrupt signal


    5. The DMA controller has _______ registers
    a) 4
    b) 2
    c) 3
    d) 1

    Answer:3
    6. When the R/W bit of the status register of the DMA
    controller is set to 1,
    a) Read operation is performed
    b) Write operation is performed

    Answer: Read operation is performed


    7. The controller is connected to the ____
    a) Processor BUS
    b) System BUS
    c) External BUS
    d) None of the above
    Answer: System BUS

    8. Can a single DMA controller perform operations on two


    different disks simulteneously…??
    a) True
    b) False
    Answer: True

    9. The techinique whereby the DMA controller steals the


    access cycles of the processor to operate is called
    a) Fast conning
    b) Memory Con
    c) Cycle stealing
    d) Memory stealing
    Answer: Cycle stealing

    10. The technique where the controller is given complete


    access to main memory is
    a) Cycle stealing
    b) Memory stealing
    c) Memory Con
    d) Burst mode

    Answer: Burst mode

    11. The controller uses _____ to help with the transfers when
    handling network interfaces.
    a) Input Buffer storage
    b) Signal echancers
    c) Bridge circuits
    d) All of the above

    Answer: Input Buffer storage


    12. To overcome the conflict over the possession of the BUS
    we use ______
    a) Optimizers
    b) BUS arbitrators
    c) Multiple BUS structure
    d) None of the above

    Answer: BUS arbitrators


    13. The registers of the controller are ______
    a) 64 bits
    b) 24 bits
    c) 32 bits
    d) 16 bits
    Answer: 32 bits

    14. When process requests for a DMA transfer ,


    a) Then the process is temporarily suspended
    b) The process continues execution
    c) Another process gets executed
    d) Both a and c

    Answer: Both a and c


    15. The DMA transfer is initiated by _____
    a) Processor
    b) The process being executed
    c) I/O devices
    d) OS
    Answer: I/O devices

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