Chunghwa Picture Tubes, Ltd.

Technical Specification
To : WTE
Date : 2011/04/08

CPT TFT-LCD
CLAB 215FA01

ACCEPTED BY

APPROVED BY CHECKED BY PREPARED BY

TFT-LCD Plant
Product Planning
Kevin Chen Tristan Wang
Management
Division.

Prepared by: Design General Division

CHUNGHWA PICTUER TUBES, LTD.
No. 1, Huaying Rd., Sanho Tsun, Lungtan Shiang, Taoyuan, Taiwan, 325, R.O.C.
TEL: +886-3-4805678 FAX: +886-3-4800589

Doc. No: CLAB215FA01–WTE–SPEC-Ver2 Issue Date: 2011/04/08

CPT CHUNGHWA PICTURES TUBES, LTD.,

Table of Content

NO Table of Content Note

1 OVERVIEW P.3
2 ABSOLUTE MAXIMUM RATINGS P.4
3 ELECTRICAL CHARACTERISTICS P.5
4 INTERFACE PIN CONNECTION P.7
5 INTERFACE TIMING P.8
6 BLOCK DIAGRAM P.11
7 MECHANICAL SPECIFICATION P.12

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1. OVERVIEW
CLAB215FA01 is 21.5” color TFT-LCD (Thin Film Transistor Liquid Crystal Display) module composed
of LCD panel, driver ICs, control circuit. By applying 6 bit digital data, 1920×1080, 16.7M-color images
are displayed on the 21.5” diagonal screen. Input power voltage is 5.0V for LCD driving. General
specification is summarized in the following table:

ITEM SPECIFICATION
Display Area(mm) 476.64 (H) × 268.11 (V) (21.53-inch diagonal)
Number of Pixels 1920 (H) × 1080(V)
Pixel Pitch(mm) 0.24825 (H) × 0.24825 (V)
Color Pixel Arrangement RGB vertical stripe
Display Mode Normally white, TN
Number of Colors 16.7M(6bits+Hi-FRC)
Brightness(cd/m^2) 300 cd/m2 (Typ.)(center, 7.5mA)
Viewing Angle(H/V) 170/160 (Typ.)
Surface Treatment Anti-glare, 3H
Power consumption(W) 5W (Typ)

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2. ABSOLUTE MAXIMUM RATINGS

ITEM SYMBOL MIN. MAX. UNIT REMARK
Power Supply Voltage for LCD VCC 0 6 V
Operation Temperature Top -30 85 1). 2). 3). 4)
Storage Temperature Tstg -40 100 1). 2). 3). 4)

[Note]
1)The relative temperature and humidity range are as below sketch, 90%RHMax.(Ta 40 ).
2).The maximum wet bulb temperature 39 (Ta＞40 ) and without dewing.
3).If you use the product in an environment which over the definition of temperature and humidity too
long to effect the result of eye-etching.
4) Test Condition: IEC 1000-4-2 VESDt: Contact discharge to input connector; VESDC: Contact
discharge to module
5). If you operate the product in normal temperature range, the center surface of panel should be under
60 .

Relative humidity(%RH)

90 Operating Range
80
Storage Range
60

40

20
5

0 20 40 50 60
-20 Temperature (°C)

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3. ELECTRICAL CHARACTERISTICS
(1).TFT-LCD Ta=25
ITEM SYMBOL MIN TYP MAX UNIT REMARK
Power Supply Voltage for LCD VCC 4.5 5.0 5.5 V *1)
Power Supply Current for LCD ICC -- 1000 1500 mA *2)
Permissive Ripple Voltage for Logic VRP -- -- 100 mVp-p VCC=5.0V
Differential Resistance Zm 90 100 110 Ω
The same motion input Voltage VCM 1.125 1.25 1.375 V

Differential input Voltage ｜VID｜ 250 350 450 mV

LVDS:
IN+，IN- High electric potential threshold *3)
VTH - - 100 mV
voltage
Low electric potential threshold
VTL -100 - - mV
voltage
LCD Irush Current Irush - - 4 A *4)

Power consumption P - 5 7.5 W *2)

[Note]
*1)Power、data sequence
0.50ms≦t1≦10ms t4≧1 sec
0.01ms＜t2≦50ms t5≧200ms
0.01ms＜t3≦50ms t6≧200ms

Vin=5.0V
4.5V 4.5V
data
LCD Power Supply
Logic Signal
0.5V 0.5V 0.5V

t1 t2 t3 t4
VL

Backlight Power Supply

t5 t6
Data: RGB DATA, DCLK, DENA

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VCC-dip conditions:
(1) When 3.6V Vcc(min)<4.5V: td 10 ms
(2) When Vcc <3.6 V, VCC-dip conditions should also follow the VCC-turn-on conditions.

2). Typical value is measured when displaying horizontal gray scale line pattern:
64 gray level, 1920 line mode
VCC=5.0 V，fH= 67.8 kHz，fV=60 Hz，fCLK=72 MHz

*3) LVDS Signal definition

｜VID｜ VTH
VTL

VIN+：Positive differential DATA & CLK Input

VIN-： Negative differential DATA ＆ CLK Input

*4).Irush Measurement Condition

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4. INTERFACE PIN CONNECTION

(1) CN1
Outlet connector: GS2330-0312R-7F (FOXCONN) (or equivalent)

PIN NO. REMARK FUNCTION

1 RXO0- minus signal of odd channel 0(LVDS)
2 RXO0+ plus signal of odd channel 0(LVDS)
3 RXO1- minus signal of odd channel 1(LVDS)
4 RXO1+ plus signal of odd channel 1(LVDS)
5 RXO2- minus signal of odd channel 2(LVDS)
6 RXO2+ plus signal of odd channel 2(LVDS)
7 GND GND
8 RXOC- minus signal of odd clock channel (LVDS)
9 RXOC+ plus signal of odd clock channel (LVDS)
10 RXO3- minus signal of odd channel 3(LVDS)
11 RXO3+ plus signal of odd channel 3(LVDS)
12 RXE0- minus signal of even channel 0(LVDS)
13 RXE0+ plus signal of even channel 0(LVDS)
14 GND GND
15 RXE1- minus signal of even channel 1(LVDS)
16 RXE1+ plus signal of even channel 1(LVDS)
17 GND GND
18 RXE2- minus signal of even channel 2(LVDS)
19 RXE2+ plus signal of even channel 2(LVDS)
20 RXEC- minus signal of even clock channel (LVDS)
21 RXEC+ plus signal of even clock channel (LVDS)
22 RXE3- minus signal of even channel 3(LVDS)
23 RXE3+ plus signal of even channel 3(LVDS)
24 GND GND
25 NC NC
26 NC Test pin (Can’t connect to GND)
27 NC NC
28 VCC Power supply input voltage(5.0 V)
29 VCC Power supply input voltage(5.0 V)
30 VCC Power supply input voltage(5.0 V)
1) Keep the NC Pin and don’t connect it to GND or other signals.
2) GND Pin must connect to the ground, don’t let it be a vacant pin.

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5. INTERFACE TIMING
(1) Timing Characteristic
ITEM SYMBOL MIN. TYP. MAX. UNIT
Freq. fCLK 55 72 90 MHz
DCLK
Cycle tCLK 18.18 13.89 11.11 ns
Horizontal effective time tHA 960 960 960 tCLK
Horizontal Horizontal blank time tHB 40 100 160 tCLK
LCD
Horizontal total time tH 992 1060 1075 tCLK
Timing
DENA Vertical frame Rate Fr 50 60 75 Hz
Vertical total time tV 1084 1130 1170 tH
Vertical
Vertical effective time tVA 1080 1080 1080 tH
Vertical blank time tVB 10 50 150 tH
[Note]
*1) DENA (data enable) usually is positive
*2) DCLK still inputs during blanking
*3) LVDS transmitter IC: HX8861-C06 (HIMAX)
*4) DE mode only
*5) It maybe cause flicker at 50Hz.
(2).Timing Chart
a. Horizontal Signal

DCLK
First Data Last Data

ODD DATA Invalid Data 5 Invalid Data

1 3 1917 1919
(R,G,B)

EVEN DATA Invalid Data 1918 1920 Invalid Data

2 4 6
(R,G,B)

tHB tHA

DENA

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b. Vertical Signal

LINE DATA Invalid Data 1 3 3 1079 1080 Invalid Data

tVB tVA

DENA

(3).LVDS Data

For 6Bit+Hi-FRC

1CLK

RXOC

RXO4 - OB[7] OB[6] OG[7] OG[6] OR[7] OR[6]

DE VS HS OB[5] OB[4] OB[3] OB[2]

RXO3

RXO2 OB[1] OB[0] OG[5] OG[4] OG[3] OG[2] OG[1]

OG[0] OR[5] OR[4] OR[3] OR[2] OR[1] OR[0]

RXO1

PREVIOUS DATA for current CLK cycle NEXT

1CLK

RXEC

RXE4 EB[7] EB[6] EG[7] EG[6] ER[7] ER[6]

-

RXE3 EB[5] EB[4] EB[3] EB[2]

- - -

RXE2 EB[1] EB[0] EG[5] EG[4] EG[3] EG[2] EG[1]

EG[0] ER[5] ER[4] ER[3] ER[2] ER[1] ER[0]

RXE1

PREVIOUS DATA for current CLK cycle NEXT

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Color Data Assignment

R DATA G DATA B DATA
COLOR INPUT DATA R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0
MSB LSB MSB LSB MSB LSB
BLACK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RED(255) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GREEN(255) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
BASIC BLUE(255) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
COLOR CYAN 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
MAGENTA 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
YELLOW 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
WHITE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
RED(0) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RED(1) 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RED(2) 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RED

RED(254) 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RED(255) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GREEN(0) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GREEN(1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
GREEN(2) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
GREEN

GREEN(254) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0
GREEN(255) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
BLUE(0) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BLUE(1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
BLUE(2) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
BLUE

BLUE(254) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0
BLUE(255) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
[Note] 1) Definition of gray scale: Color (n): n indicates gray scale level; higher n means brighter level.
2) Data: 1-High, 0-Low.
3)For odd & even data also.
(4).Color Data Distribution
D(1,1) D(2,1) .. D(X,1) .. D(1919,1) D(1920,1)
D(1,2) D(2,2) .. D(X,2) .. D(1919,2) D(1920,2)
.. .. + .. + .. ..
D(1,Y) D(2,Y) .. D(X,Y) .. D(1919,Y) D(1920,Y)
.. .. + .. + .. ..
D(1,1079) D(2, 1079) .. D(X, 1079) .. D(1919, 1079) D(1920, 1079)
D(1, 1080) D(2, 1080) .. D(X, 1080) .. D(1919, 1080) D(1920,1080)

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6. BLOCK DIAGRAM

TFT-LCD Module

Mini-LVDS
receiver 2ch
Timing Source Driver
CN1 I/F Connector

Controller

Gate Driver
LCD Panel

Power Supply 1920 X 3 X 1080

Circuit

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7. MECHANICAL SPECIFICATION
(1) OLB Drawing (Tolerance is ± 0.5mm unless noted) [Unit:mm]

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