Verilog: - A IEEE Standard Hardware Descriptive Language

Verilog
• A IEEE standard Hardware Descriptive Language

Types of Verilog Modeling
Verilog Modeling
Behavioral Modeling Structural Modeling

Behavioral Modeling
• Only the functionality of the circuit is mapped no concern for
structure
Model maps Input to

Input Output
Output
Structural Modeling
• Only the functionality of the circuit is mapped with specific structural
elements structure
Input Output
RTL Synthesis
RTL Synthesis Vs Simulation
Synthesize and Simulate model on

compile code to run test benches and
on a target board export the outputs
Verilog components
Comments and formatting
module module_name (port_list*);
Port declarations* Others components
Data type declarations Sub model Instantiation Format
Circuit functionality Defining Port Connections
Timing specifications
endmodule
Different syntax and operators in Verilog
Syntax Operators
Parameter Arithmetic: + - * / % ** Miscellaneous: ?: {,} {{}}
Numbers Bitwise: ~ & | ^ ^~ ~^ Operator Precedence
Continuous Assignments: assign Reduction: & ~& | ~| ^ ^~ ~^

#time
Procedural Assignments: Relational: > < >= <=

initial always = <=
Behavioral statements: Equality: == != === !==

if case
Loops: forever repeat for Logical: ! && || Structural Modeling

while Behavioral Modeling
Shift: << >> <<< >>>

Functions and Tasks
module and(out,ina,inb); module and (out , ina , inb);
Comments and formatting

• Case-sensitive (e.g.: A ≠ a) Sample X space
• Keywords are lower case (e.g.: module, endmodule)
• X and Y direction white space are ignored module and ( out,
ina,
inb);
• SEMICOLON (;) is statement terminator
• //: single line comment
• /* */: Multi-line comment
Y space
All are same
Port list and Port declarations
• Ports are the list of all inputs and outputs
• Port Types: input, output, inout
• Declaration: <port_type> <port_name>
module mult_acc (out, ina, ind, clk, acclr); module mult_acc
(
input [7:0] ina, inb; input [7:0] ina, inb,
input clk, aclr;
output [15:0] out;
OR input clk, aclr,
output [15:0] out,
);
endmodule endmodule
Data type declarations wire, tri, supply0 & supply1
Net Data Types

(physical
connection)
Data Types
Variable Data
Types (temporary
storage)
reg, integer, real, time, realtime

Net Data Types
• wire: Represents a node or connection
• tri: Represents a tri-state node
• supply0: Hard codes logic 0
• supply1: Hard coded logic 1
Bus Declarations:
<data_type> [MSB:LSB] <signal name>;
<data_type> [LSB:MSB] <signal name>;
Examples:
wire [7:0] out;
tri enable;
Variable Data Types
• reg: unsigned variable of a particular size
• integer: signed 32 bit variable
• real, time, realtime: no synthesis support
Bus Declarations:
reg [MSB:LSB] <signal name>;
reg [LSB:MSB] <signal name>;
Examples:
reg [7:0] out;
integer count;
Initiation Format
<component_name> #<delay> <instance_name> (port_list);
The module name of lower level component

Delay through a component (optional)
Unique name of instance
Input and output ports of the of the sub component
Defining Port Connections
Here you know the
• By ordered list order of inputs
e.g.:
half_adder u1(c1,s1,a,b);
• By name
half_adder u1(.a(s1),.b(cin),.sum(fsum),.co(co2));
a<-s1
b<-cin
sum<-fsum
co<-co2
Parameter
• Value assigned to a symbolic name
• Must resolve to constant at compile time
• Can be overwritten at compile time
• localparam – same as parameter but cannot be overwritten
e.g.:
Numbers
<size>’<base format><number>
E.g.: 3-bit wide number=3’b010
32-bit wide number=32’b010 or 2 (as 32 is default size)
Format Base/Meaning Example Number of Bits wide
D’ or d’ Decimal 16’d255 16
H’ or h’ Hexadecimal 8’h9a 8
B’ or b’ Binary ’b1010 32
O’ or o’ Octal ’o21 32
S’ or s’ Signed (2’s complement) 16’shFA 16
- Negative (stored as 2’s complement) -8’d3 8
_ ignored 32’h21_65_bc_fe 32
X or x unknown 12’h12x 12 (LSB are unknown)
Z or z High Impedance 1’bz 1

Arithmetic Operators
Bitwise Operators
Reduction Operators
Relational Operators
Equality Operators
Logical Operators
Shift Operators
Miscellaneous Operators
Operator Precedence
Continuous Assignments
Assignment takes
• LHS is net data type place after 5 time
units of delay
• RHS is net, register or function calls
wire[15:0]adder_out=muly_out+out assign #5 adder_out=mult_out+out

Is equivalent to
wire[15:0]adder_out
assign adder_out=mult_out+out
Procedural Assignments
initial and always = and <=
Behavioral statements
If-else statements Case statements
x and z should match

to be true
In casez, z is treated
as don’t cares
“?” denotes don’t cate terms
In casex, x and z are

treated as don’t
cares, instead of
logical values
Loops
Functions and Tasks
Functions Task
Reference
• Verilog HDL Basics – YouTube
• Altera Tutorial - Verilog HDL Basic.pptx
• Introduction to Verilog Part 1 – YouTube
• IntroductionToVerilog Part2 – YouTube

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Verilog

• A IEEE standard Hardware Descriptive Language

Behavioral Modeling Structural Modeling

Model maps Input to

Synthesize and Simulate model on

module module_name (port_list*);

Port declarations* Others components

Data type declarations Sub model Instantiation Format

Circuit functionality Defining Port Connections

Parameter Arithmetic: + - * / % ** Miscellaneous: ?: {,} {{}}

Numbers Bitwise: ~ & | ^ ^~ ~^ Operator Precedence

Continuous Assignments: assign Reduction: & ~& | ~| ^ ^~ ~^

Procedural Assignments: Relational: > < >= <=

Behavioral statements: Equality: == != === !==

Loops: forever repeat for Logical: ! && || Structural Modeling

Shift: << >> <<< >>>

Comments and formatting

Net Data Types

reg, integer, real, time, realtime

The module name of lower level component

S’ or s’ Signed (2’s complement) 16’shFA 16

- Negative (stored as 2’s complement) -8’d3 8

X or x unknown 12’h12x 12 (LSB are unknown)

Z or z High Impedance 1’bz 1

wire[15:0]adder_out=muly_out+out assign #5 adder_out=mult_out+out

x and z should match

In casex, x and z are

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