a 3 V to 5 V Single Supply, 200 kSPS

8-Channel, 12-Bit Sampling ADC

AD7858/AD7858L*
FEATURES FUNCTIONAL BLOCK DIAGRAM
Specified for VDD of 3 V to 5.5 V
AD7858—200 kSPS; AD7858L—100 kSPS AVDD AGND
System and Self-Calibration with Autocalibration on
Power-Up AIN1
Eight Single-Ended or Four Pseudo-Differential Inputs I/P AD7858/
T/H AD7858L
MUX
Low Power AIN8 DVDD
AD7858: 12 mW (VDD = 3 V) 2.5V
AD7858L: 4.5 mW (V DD = 3 V) REFERENCE
Automatic Power-Down After Conversion (25 ␮W) COMP

Flexible Serial Interface: REFIN /REF OUT BUF DGND

8051/SPI™/QSPI™/␮P Compatible
24-Lead DIP, SOIC, and SSOP Packages CREF1

CHARGE
APPLICATIONS REDISTRIBUTION
DAC
Battery-Powered Systems (Personal Digital Assistants,
CLKIN
Medical Instruments, Mobile Communications) CREF2
SAR AND ADC CONVST
Pen Computers CONTROL
CALIBRATION BUSY
Instrumentation and Control Systems CAL MEMORY AND
CONTROLLER SLEEP
High-Speed Modems

GENERAL DESCRIPTION SERIAL INTERFACE/CONTROL REGISTER

The AD7858/AD7858L are high-speed, low-power, 12-bit
ADCs that operate from a single 3 V or 5 V power supply, the SYNC DIN DOUT SCLK
AD7858 being optimized for speed and the AD7858L for low
power. The ADC powers up with a set of default conditions at
which time it can be operated as a read-only ADC. The ADC
contains self-calibration and system calibration options to en- PRODUCT HIGHLIGHTS
sure accurate operation over time and temperature and have a 1. Specified for 3 V and 5 V supplies.
number of power-down options for low-power applications. 2. Automatic calibration on power-up.
The part powers up with a set of default conditions and can
3. Flexible power management options including automatic
operate as a read-only ADC.
power-down after conversion.
The AD7858 is capable of 200 kHz throughput rate while the
4. Operates with reference voltages from 1.2 V to VDD.
AD7858L is capable of 100 kHz throughput rate. The input
track-and-hold acquires a signal in 500 ns and features a 5. Analog input range from 0 V to VDD.
pseudo-differential sampling scheme. The AD7858/AD7858L 6. Eight single-ended or four pseudo-differential input channels.
voltage range is 0 to VREF with straight binary output coding.
7. System and self-calibration.
Input signal range is to the supply and the part is capable of con-
verting full power signals to 100 kHz. 8. Versatile serial I/O port (SPI/QSPI/8051/µP).
CMOS construction ensures low power dissipation of typically 9. Lower power version AD7858L.
4.5 mW for normal operation and 1.15 mW in power-down
mode with a throughput rate of 10 kSPS (VDD = 3 V). The part
is available in 24-lead, 0.3 inch-wide dual-in-line package
(DIP), 24-lead small outline (SOIC), and 24-lead small shrink
outline (SSOP) packages.

*Patent pending.
See page 31 for data sheet index.
SPI and QSPI are trademarks of Motorola, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000
 1, 2
AD7858/AD7858L–SPECIFICATIONS
Reference unless otherwise noted, f
(AV = DV = +3.0 V to +5.5 V, REF /REF = 2.5 V External
DD DD IN OUT
= 4 MHz (1.8 MHz B Grade (0ⴗC to +70ⴗC), 1 MHz A and B Grades (–40ⴗC to +85ⴗC) for L Version); f =
CLKIN SAMPLE
200 kHz (AD7858), 100 kHz (AD7858L); SLEEP = Logic High; TA = TMIN to TMAX, unless otherwise noted.) Specifications in ( ) apply to the AD7858L.
Parameter A Version1 B Version1 Units Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal to Noise + Distortion Ratio3 70 71 dB min Typically SNR is 72 dB
(SNR) VIN = 10 kHz Sine Wave, fSAMPLE = 200 kHz (100 kHz)
Total Harmonic Distortion (THD) –78 –78 dB max VIN = 10 kHz Sine Wave, fSAMPLE = 200 kHz (100 kHz)
Peak Harmonic or Spurious Noise –78 –78 dB max VIN = 10 kHz Sine Wave, fSAMPLE = 200 kHz (100 kHz)
Intermodulation Distortion (IMD)
Second Order Terms –78 –80 dB typ fa = 9.983 kHz, fb = 10.05 kHz, fSAMPLE = 200 kHz (100 kHz)
Third Order Terms –78 –80 dB typ fa = 9.983 kHz, fb = 10.05 kHz, fSAMPLE = 200 kHz (100 kHz)
Channel-to-Channel Isolation –90 –90 dB typ VIN = 25 kHz
DC ACCURACY Any Channel
Resolution 12 12 Bits
Integral Nonlinearity ±1 ±1 LSB max 2.5 V External Reference VDD = 3 V, VDD = 5 V (B Grade Only)
±1 ± 0.5 LSB max 5 V External Reference VDD = 5 V
(± 1) LSB max (L Version, 5 V External Reference, VDD = 5 V)
(± 1) LSB max (L Version)
Differential Nonlinearity ±1 ±1 LSB max Guaranteed No Missed Codes to 12 Bits. 2.5 V External
Reference VDD = 3 V, 5 V External Reference, VDD = 5 V
Total Unadjusted Error ±1 ±1 LSB typ
Unipolar Offset Error ±5 ±5 LSB max Typically ± 2 LSBs
± 2.5 ± 2.5 LSB max 5 V External Reference, VDD = 5 V
(± 3) (± 3) LSB max (L Version)
(± 1.5) (± 1.5) LSB max (L Version, 5 V External Reference, VDD = 5 V)
Unipolar Offset Error Match 1.5 1.5 LSB max
Positive Full-Scale Error ±4 ±4 LSB max
± 1.5 ± 1.5 LSB max 5 V External Reference, VDD = 5 V
Positive Full-Scale Error Match 1 1 LSB max
ANALOG INPUT
Input Voltage Ranges 0 to VREF 0 to VREF Volts i.e., AIN(+) – AIN(–) = 0 to VREF, AIN(–) can be biased
up but AIN(+) cannot go below AIN(–)
Leakage Current ±1 ±1 µA max
Input Capacitance 20 20 pF typ
REFERENCE INPUT/OUTPUT
REFIN Input Voltage Range 2.3/VDD 2.3/VDD V min/max Functional from 1.2 V
Input Impedance 150 150 kΩ typ
REFOUT Output Voltage 2.3/2.7 2.3/2.7 V min/max
REFOUT Tempco 20 20 ppm/°C typ
LOGIC INPUTS
Input High Voltage, VINH 2.4 2.4 V min AVDD = DVDD = 4.5 V to 5.5 V
2.1 2.1 V min AVDD = DVDD = 3.0 V to 3.6 V
Input Low Voltage, VINL 0.8 0.8 V max AVDD = DVDD = 4.5 V to 5.5 V
0.6 0.6 V max AVDD = DVDD = 3.0 V to 3.6 V
Input Current, IIN ± 10 ± 10 µA max Typically 10 nA, VIN = 0 V or VDD
Input Capacitance, CIN4 10 10 pF max
LOGIC OUTPUTS
Output High Voltage, VOH ISOURCE = 200 µA
4 4 V min AVDD = DVDD = 4.5 V to 5.5 V
2.4 2.4 V min AVDD = DVDD = 3.0 V to 3.6 V
Output Low Voltage, VOL 0.4 0.4 V max ISINK = 0.8 mA
Floating-State Leakage Current ± 10 ± 10 µA max
Floating-State Output Capacitance4 10 10 pF max
Output Coding Straight (Natural) Binary
CONVERSION RATE
Conversion Time 4.6 (18) 4.6 µs max (L Versions Only, –40°C to +85°C, 1 MHz CLKIN)
(10) µs max (L Versions Only, 0°C to +70°C, 1.8 MHz CLKIN)
Track/Hold Acquisition Time 0.4 (1) 0.4 (1) µs min (L Versions Only)

–2– REV. B
 AD7858/AD7858L
Parameter A Version1 B Version1 Units Test Conditions/Comments
DYNAMIC PERFORMANCE
AVDD, DVDD +3.0/+5.5 +3.0/+5.5 V min/max
IDD
Normal Mode5 6 (1.9) 6 (1.9) mA max AVDD = DVDD = 4.5 V to 5.5 V. Typically 4.5 mA (1.5)
5.5 (1.9) 5.5 (1.9) mA max AVDD = DVDD = 3.0 V to 3.6 V. Typically 4.0 mA (1.5 mA)
Sleep Mode6
With External Clock On 10 10 µA typ Full Power-Down. Power Management Bits in Control
Register Set as PMGT1 = 1, PMGT0 = 0
400 400 µA typ Partial Power-Down. Power Management Bits in
Control Register Set as PMGT1 = 1, PMGT0 = 1
With External Clock Off 5 5 µA max Typically 1 µA. Full Power-Down. Power Management Bits
in Control
Register Set as PMGT1 = 1, PMGT0 = 0
200 200 µA typ Partial Power-Down. Power Management Bits in Control
Register Set as PMGT1 = 1, PMGT0 = 1
Normal-Mode Power Dissipation 33 (10.5) 33 (10.5) mW max VDD = 5.5 V. Typically 25 mW (8); SLEEP = VDD
20 (6.85) 20 (6.85) mW max VDD = 3.6 V. Typically 15 mW (5.4); SLEEP = VDD
Sleep Mode Power Dissipation
With External Clock On 55 55 µW typ VDD = 5.5 V. SLEEP = 0 V
36 36 µW typ VDD = 3.6 V. SLEEP = 0 V
With External Clock Off 27.5 27.5 µW max VDD = 5.5 V. Typically 5.5 µW; SLEEP = 0 V
18 18 µW max VDD = 3.6 V. Typically 3.6 µW; SLEEP = 0 V
SYSTEM CALIBRATION
Offset Calibration Span7 +0.05 × VREF/–0.05 × VREF V max/min Allowable Offset Voltage Span for Calibration
Gain Calibration Span7 +1.025 × VREF/–0.975 × VREF V max/min Allowable Full-Scale Voltage Span for Calibration
NOTES
1
Temperature ranges as follows: A, B Versions: –40°C to +85°C. For L Versions, A and B Versions f CLKIN = 1 MHz over –40°C to +85°C temperature range,
B Version f CLKIN = 1.8 MHz over 0°C to +70°C temperature range.
2
Specifications apply after calibration.
3
SNR calculation includes distortion and noise components.
4
Sample tested @ +25°C to ensure compliance.
5
All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DVDD. No load on the digital outputs. Analog inputs @ AGND.
6
CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DVDD. No load on the digital
outputs. Analog inputs @ AGND.
7
The Offset and Gain Calibration Spans are defined as the range of offset and gain errors that the AD7858/AD7858L can calibrate. Note also that these are voltage
spans and are not absolute voltages ( i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–)
± 0.05 × VREF, and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be
VREF ± 0.025 × VREF). This is explained in more detail in the Calibration section of the data sheet.
Specifications subject to change without notice.

REV. B –3–
AD7858/AD7858L
(AVDD = DVDD = +3.0 V to +5.5 V; fCLKIN = 4 MHz for AD7858 and 1.8/1 MHz for AD7858L;
TIMING SPECIFICATIONS1 T = T A MIN to TMAX , unless otherwise noted)

Limit at TMIN, TMAX

(A, B Versions)
Parameter 5V 3V Units Description
2
fCLKIN 500 500 kHz min Master Clock Frequency
4 4 MHz max
1.8 1.8 MHz max L Version, 0°C to +70°C, B Grade Only
1 1 MHz max L Version, –40°C to +85°C
fSCLK 4 4 MHz max
t1 3 100 100 ns min CONVST Pulsewidth
t2 50 90 ns max CONVST↓ to BUSY↑ Propagation Delay
tCONVERT 4.6 4.6 µs max Conversion Time = 18 tCLKIN
10 (18) 10 (18) µs max L Version 1.8 (1) MHz CLKIN. Conversion Time = 18 tCLKIN
t3 –0.4 tSCLK –0.4 tSCLK ns min SYNC↓ to SCLK↓ Setup Time (Noncontinuous SCLK Input)
⫿0.4 tSCLK ⫿0.4 tSCLK ns min/max SYNC↓ to SCLK↓ Setup Time (Continuous SCLK Input)
t4 4 50 90 ns max Delay from SYNC↓ Until DOUT Three-State Disabled
t5 4 50 90 ns max Delay from SYNC↓ Until DIN Three-State Disabled
t6 4 75 115 ns max Data Access Time After SCLK↓
t7 40 60 ns min Data Setup Time Prior to SCLK↑
t8 20 30 ns min Data Valid to SCLK Hold Time
t9 0.4 tSCLK 0.4 tSCLK ns min SCLK High Pulsewidth
t10 0.4 tSCLK 0.4 tSCLK ns min SCLK Low Pulsewidth
t11 30 50 ns min SCLK↑ to SYNC↑ Hold Time (Noncontinuous SCLK)
30/0.4 tSCLK 50/0.4 tSCLK ns min/max (Continuous SCLK)
t125 50 50 ns max Delay from SYNC↑ Until DOUT Three-State Enabled
t13 90 130 ns max Delay from SCLK↑ to DIN Being Configured as Output
t146 50 90 ns max Delay from SCLK↑ to DIN Being Configured as Input
t15 2.5 tCLKIN 2.5 tCLKIN ns max CAL↑ to BUSY↑ Delay
t16 2.5 tCLKIN 2.5 tCLKIN ns max CONVST↓ to BUSY↑ Delay in Calibration Sequence
tCAL7 31.25 31.25 ms typ Full Self-Calibration Time, Master Clock Dependent
(125013 tCLKIN)
tCAL17 27.78 27.78 ms typ Internal DAC Plus System Full-Scale Calibration Time, Master
Clock Dependent (111114 tCLKIN)
tCAL27 3.47 3.47 ms typ System Offset Calibration Time, Master Clock Dependent
(13899 tCLKIN)
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V.
See Table XI and timing diagrams for different interface modes and Calibration.
2
Mark/Space ratio for the master clock input is 40/60 to 60/40.
3
The CONVST pulsewidth will apply here only for normal operation. When the part is in power-down mode, a different CONVST pulsewidth will apply
(see Power-Down section).
4
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
5
t12 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t 12, quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.
6
t14 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is the
true delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line
knowing that a bus conflict will not occur.
7
The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to
the 1.8/1 MHz master clock.
Specifications subject to change without notice.

–4– REV. B
 AD7858/AD7858L
TYPICAL TIMING DIAGRAMS
Figures 2 and 3 show typical read and write timing diagrams for 1.6mA IOL

serial Interface Mode 2. The reading and writing occurs after

conversion in Figure 2, and during conversion in Figure 3. To TO
+2.1V
OUTPUT
attain the maximum sample rate of 100 kHz (AD7858L) or PIN CL
200 kHz (AD7858), reading and writing must be performed 100pF

during conversion as in Figure 3. At least 400 ns acquisition 200␮A IOH

time must be allowed (the time from the falling edge of BUSY
to the next rising edge of CONVST) before the next conversion Figure 1. Load Circuit for Digital Output Timing
begins to ensure that the part is settled to the 12-bit level. If the Specifications
user does not want to provide the CONVST signal, the conver-
sion can be initiated in software by writing to the control register.

tCONVERT = 4.6␮s MAX, 10␮s MAX FOR L VERSION

t1 = 100ns MIN, t4 = 50/90ns MAX 5V/3V, t7 = 40/60ns MIN 5V/3V
t1
CONVST (I/P)
tCONVERT
t2
BUSY (O/P)

SYNC (I/P)

t3 t9 t11
SCLK (I/P) 1 5 6 16
t4 t10 t12
t6 t6
THREE-STATE THREE-
DOUT (O/P) DB15 DB11 DB0
STATE
t8
t7
DIN (I/P) DB15 DB11 DB0

Figure 2. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing After Conversion)

tCONVERT = 4.6␮s MAX, 10␮s MAX FOR L VERSION

t1 = 100ns MIN, t4 = 50/90ns MAX 5V/3V, t7 = 40/60ns MIN 5V/3V
t1
CONVST (I/P)
tCONVERT
t2
BUSY (O/P)

SYNC (I/P)

t3 t9 t11
SCLK (I/P) 1 5 6 16
t4 t10 t12
t6 t6
THREE-STATE THREE-
DOUT (O/P) DB15 DB11 DB0
STATE
t8
t7
DIN (I/P) DB15 DB11 DB0

Figure 3. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing During Conversion)

REV. B –5–
AD7858/AD7858L
ABSOLUTE MAXIMUM RATINGS 1 SOIC, SSOP Package, Power Dissipation . . . . . . . . . . 450 mW
(TA = +25°C unless otherwise noted) θJA Thermal Impedance . . . 75°C/W (SOIC) 115°C/W (SSOP)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V θJC Thermal Impedance . . . . 25°C/W (SOIC) 35°C/W (SSOP)
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Lead Temperature, Soldering
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Analog Input Voltage to AGND . . . . –0.3 V to AVDD + 0.3 V Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V NOTES
1
Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
REFIN/REFOUT to AGND . . . . . . . . . –0.3 V to AVDD + 0.3 V device at these or any other conditions above those listed in the operational
Input Current to Any Pin Except Supplies2 . . . . . . . ± 10 mA sections of this specification is not implied. Exposure to absolute maximum rating
Operating Temperature Range conditions for extended periods may affect device reliability.
2
Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C Transient currents of up to 100 mA will not cause SCR latch-up.
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . 34.7°C/W
Lead Temperature, (Soldering, 10 sec) . . . . . . . . . . +260°C

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although WARNING!
the AD7858/AD7858L features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
ESD SENSITIVE DEVICE
are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE PIN CONFIGURATIONS

DIP, SOIC, AND SSOP
Linearity Power
Error Dissipation Package
Model (LSB)1 (mW) Options2 CONVST 1 24 SYNC

AD7858AN ±1 20 N-24 BUSY 2 23 SCLK

SLEEP 3
AD7858BN ± 1/2 20 N-24 22 CLKIN
REFIN /REFOUT 4
AD7858LAN3 ±1 6.85 N-24 AD7858/
21 DIN
AVDD 5
AD7858LBN3 ±1 6.85 N-24 AD7858L 20 DOUT
AGND 6
AD7858AR ±1 20 R-24 TOP VIEW 19 DGND
CREF1 7 (Not to Scale) 18 DVDD
AD7858BR ± 1/2 20 R-24
17 CAL
AD7858LAR3 ±1 6.85 R-24 CREF2 8
AIN1 9 16 AIN8
AD7858LBR3 ±1 6.85 R-24
AIN2 10
AD7858LARS3 ±1 6.85 RS-24 15 AIN7
AIN3 11 14 AIN6
EVAL-AD7858CB4
AIN4 12 13 AIN5
EVAL-CONTROL BOARD5
NOTES
1
Linearity error here refers to integral linearity error.
2
N = Plastic DIP; R = SOIC; RS = SSOP.
3
L signifies the low-power version.
4
This can be used as a stand-alone evaluation board or in conjunction with the EVAL-
CONTROL BOARD for evaluation/demonstration purposes.
5
This board is a complete unit allowing a PC to control and communicate with all
Analog Devices evaluation boards ending in the CB designators.

–6– REV. B
 AD7858/AD7858L
PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Description

1 CONVST Convert Start. Logic Input. A low to high transition on this input puts the track/hold into its hold mode
and starts conversion. When this input is not used, it should be tied to DVDD.
2 BUSY Busy Output. The busy output is triggered high by the falling edge of CONVST or rising edge of CAL,
and remains high until conversion is completed. BUSY is also used to indicate when the AD7858/
AD7858L has completed its on-chip calibration sequence.
3 SLEEP Sleep Input/Low-Power Mode. A Logic 0 initiates a sleep, and all circuitry is powered down including the
internal voltage reference provided there is no conversion or calibration being performed. Calibration
data is retained. A Logic 1 results in normal operation. See Power-Down section for more details.
4 REFIN/REFOUT Reference Input/Output. This pin is connected to the internal reference through a series resistor and is
the reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V and this
appears at the pin. This pin can be overdriven by an external reference or can be taken as high as AVDD.
When this pin is tied to AVDD, or when an externally applied reference approaches AVDD, the CREF1 pin
should also be tied to AVDD.
5 AVDD Analog Positive Supply Voltage, +3.0 V to +5.5 V.
6 AGND Analog Ground. Ground reference for track/hold, reference, and DAC.
7 CREF1 Reference Capacitor (0.1 µF Multilayer Ceramic). This external capacitor is used as a charge source for
the internal DAC. The capacitor should be tied between the pin and AGND.
8 CREF2 Reference Capacitor (0.01 µF Ceramic Disc). This external capacitor is used in conjunction with the on-
chip reference. The capacitor should be tied between the pin and AGND.
9–16 AIN1–AIN8 Analog Inputs. Eight analog inputs that can be used as eight single-ended inputs (referenced to AGND)
or four pseudo-differential inputs. Channel configuration is selected by writing to the control register.
Both the positive and negative inputs cannot go below AGND or above AVDD at any time. Also the posi-
tive input cannot go below the negative input. See Table III for channel selection.
17 CAL Calibration Input. This pin has an internal pull-up current source of 0.15 µA. A Logic 0 on this pin resets
all calibration control logic and initiates a calibration on its rising edge. There is the option of connecting
a 10 nF capacitor from this pin to DGND to allow for an automatic self-calibration on power-up. This
input overrides all other internal operations. If the autocalibration is not required, this pin should be tied
to a logic high.
18 DVDD Digital Supply Voltage, +3.0 V to +5.5 V.
19 DGND Digital Ground. Ground reference point for digital circuitry.
20 DOUT Serial Data Output. The data output is supplied to this pin as a 16-bit serial word.
21 DIN Serial Data Input. The data to be written is applied to this pin in serial form (16-bit word). This pin can
act as an input pin or as a I/O pin depending on the serial interface mode the part is in (see Table X).
22 CLKIN Master clock signal for the device (4 MHz AD7858, 1.8 MHz AD7858L). Sets the conversion and cali-
bration times.
23 SCLK Serial Port Clock. Logic Input. The user must provide a serial clock on this input.
24 SYNC Frame Sync. Logic Input. This pin is level triggered active low and frames the serial clock for the read
and write operations (see Table IX).

REV. B –7–
AD7858/AD7858L
TERMINOLOGY1 Total Harmonic Distortion
Integral Nonlinearity Total harmonic distortion (THD) is the ratio of the rms sum of
This is the maximum deviation from a straight line passing harmonics to the fundamental. For the AD7858/AD7858L, it is
through the endpoints of the ADC transfer function. The end- defined as:
points of the transfer function are zero scale, a point 1/2 LSB
2 2 2 2 2
below the first code transition, and full scale, a point 1/2 LSB (V2 + V3 + V4 + V5 + V6 )
above the last code transition. THD ( dB ) = 20 log
V1
Differential Nonlinearity where V1 is the rms amplitude of the fundamental and V2, V3,
This is the difference between the measured and the ideal 1 LSB V4, V5, and V6 are the rms amplitudes of the second through the
change between any two adjacent codes in the ADC. sixth harmonics.
Total Unadjusted Error Peak Harmonic or Spurious Noise
This is the deviation of the actual code from the ideal code tak- Peak harmonic or spurious noise is defined as the ratio of the
ing all errors into account (Gain, Offset, Integral Nonlinearity, and rms value of the next largest component in the ADC output
other errors) at any point along the transfer function. spectrum (up to fS/2 and excluding dc) to the rms value of the
Unipolar Offset Error fundamental. Normally, the value of this specification is deter-
This is the deviation of the first code transition (00 . . . 000 to mined by the largest harmonic in the spectrum, but for parts
00 . . . 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB). where the harmonics are buried in the noise floor, it will be a
Positive Full-Scale Error noise peak.
This is the deviation of the last code transition from the ideal Intermodulation Distortion
AIN(+) voltage (AIN(–) + Full Scale – 1.5 LSB) after the offset With inputs consisting of sine waves at two frequencies, fa and
error has been adjusted out. fb, any active device with nonlinearities will create distortion
Channel-to-Channel Isolation products at sum and difference frequencies of mfa ± nfb where
Channel-to-channel isolation is a measure of crosstalk between m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
the channels. It is measured by applying a full-scale 25 kHz those for which neither m nor n are equal to zero. For example,
signal to the other seven channels and determining how much the second order terms include (fa + fb) and (fa – fb), while the
that signal is attenuated in the channel of interest. The figure third order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and
given is the worst case for all channels. (fa – 2fb).

Track/Hold Acquisition Time Testing is performed using the CCIF standard where two input
The track/hold amplifier returns into track mode and the end of frequencies near the top end of the input bandwidth are used. In
conversion. Track/hold acquisition time is the time required for this case, the second order terms are usually distanced in fre-
the output of the track/hold amplifier to reach its final value, quency from the original sine waves, while the third order terms
within ± 1/2 LSB, after the end of conversion. are usually at a frequency close to the input frequencies. As a
result, the second and third order terms are specified separately.
Signal to (Noise + Distortion) Ratio The calculation of the intermodulation distortion is as per the
This is the measured ratio of signal to (noise + distortion) at the THD specification where it is the ratio of the rms sum of the
output of the A/D converter. The signal is the rms amplitude of individual distortion products to the rms amplitude of the sum
the fundamental. Noise is the sum of all nonfundamental signals of the fundamentals expressed in dBs.
up to half the sampling frequency (fS/2), excluding dc. The ratio
is dependent on the number of quantization levels in the digitiza-
tion process; the more levels, the smaller the quantization noise.
The theoretical signal to (noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02 N +1.76) dB
Thus for a 12-bit converter, this is 74 dB.
1
AIN(+) refers to the positive input of the pseudo differential pair, and AIN(–)
refers to the negative analog input of the pseudo differential pair or to AGND
depending on the channel configuration.

–8– REV. B
 AD7858/AD7858L
ON-CHIP REGISTERS
The AD7858/AD7858L powers up with a set of default conditions. The only writing required is to select the channel configuration.
Without performing any other write operations the AD7858/AD7858L still retains the flexibility for performing a full power-down
and a full self-calibration.
Extra features and flexibility, such as performing different power-down options, different types of calibrations including system
calibration, and software conversion start, can be selected by further writing to the part.
The AD7858/AD7858L contains a Control Register, ADC Output Data Register, Status Register, Test Register, and
10 Calibration Registers. The control register is write-only, the ADC output data register and the status register are read-only, and
the test and calibration registers are both read/write registers. The Test Register is used for testing the part and should not be written to.
Addressing the On-Chip Registers
Writing
A write operation to the AD7858/AD7858L consists of 16 bits. The two MSBs, ADDR0 and ADDR1, are decoded to determine
which register is addressed, and the subsequent 14 bits of data are written to the addressed register. It is not until all 16 bits are
written that the data is latched into the addressed registers. Table I shows the decoding of the address bits while Figure 4 shows the
overall write register hierarchy.

Table I. Write Register Addressing

ADDR1 ADDR0 Comment

0 0 This combination does not address any register so the subsequent 14 data bits are ignored.
0 1 This combination addresses the TEST REGISTER. The subsequent 14 data bits are written to the test
register.
1 0 This combination addresses the CALIBRATION REGISTERS. The subsequent 14 data bits are written
to the selected calibration register.
1 1 This combination addresses the CONTROL REGISTER. The subsequent 14 data bits are written to the
control register.

Reading
To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These
bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address
bits while Figure 5 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be
from the ADC output data register.
Once the read selection bits are set in the Control Register, all subsequent read operations that follow will be from the selected regis-
ter until the read selection bits are changed in the Control Register.

Table II. Read Register Addressing

RDSLT1 RDSLT0 Comment

0 0 All successive read operations will be from ADC OUTPUT DATA REGISTER. This is the power-up
default setting. There will always be 4 leading zeros when reading from the ADC Output Data Register.
0 1 All successive read operations will be from TEST REGISTER.
1 0 All successive read operations will be from CALIBRATION REGISTERS.
1 1 All successive read operations will be from STATUS REGISTER.

ADDR1, ADDR0 RDSLT1, RDSLT0

DECODE DECODE

01 10 11 00 01 10 11
TEST CALIBRATION CONTROL ADC OUTPUT TEST CALIBRATION STATUS
REGISTER REGISTERS REGISTER DATA REGISTER REGISTER REGISTERS REGISTER

GAIN(1) GAIN(1)
GAIN(1) OFFSET(1) GAIN(1)
OFFSET(1) OFFSET(1) GAIN(1) OFFSET(1) OFFSET(1) GAIN(1)
DAC(8) OFFSET(1) DAC(8)
00 01 10 11 CALSLT1, CALSLT0 00 01 10 11
CALSLT1, CALSLT0
DECODE DECODE

Figure 4. Write Register Hierarchy/Address Decoding Figure 5. Read Register Hierarchy/Address Decoding

REV. B –9–
AD7858/AD7858L
CONTROL REGISTER
The arrangement of the Control Register is shown below. The control register is a write only register and contains 14 bits of data.
The control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register are de-
scribed below. The power-up status of all bits is 0.
MSB
SGL/DIFF CH2 CH1 CH0 PMGT1 PMGT0 RDSLT1

RDSLT0 2/3 MODE CONVST CALMD CALSLT1 CALSLT0 STCAL

LSB

CONTROL REGISTER BIT FUNCTION DESCRIPTION

Bit Mnemonic Comment

13 SGL/DIFF A 0 in this bit position configures the input channels in pseudo-differential mode. A 1 in this bit position
configures the input channels in single-ended mode (see Table III).
12 CH2 These three bits are used to select the channel on which the conversion is performed. The channels can
11 CH1 be configured as eight single-ended channels or four pseudo-differential channels. The default selection
10 CH0 is AIN1 for the positive input and AIN2 for the negative input (see Table III for channel selection).
9 PMGT1 Power Management Bits. These two bits are used with the SLEEP pin for putting the part into various
8 PMGT0 Power-Down Modes (see Power-Down section for more details).
7 RDSLT1 Theses two bits determine which register is addressed for the read operations (see Table II).
6 RDSLT0
5 2/3 MODE Interface Mode Select Bit. With this bit set to 0, Interface Mode 2 is enabled. With this bit set to 1,
Interface Mode 1 is enabled where DIN is used as an output as well as an input. This bit is set to 0 by
default after every read cycle; thus when using the Two-Wire Interface Mode, this bit needs to be set to
1 in every write cycle.
4 CONVST Conversion Start Bit. A logic one in this bit position starts a single conversion, and this bit is automati-
cally reset to 0 at the end of conversion. This bit may also be used in conjunction with system calibration
(see Calibration section.)
3 CALMD Calibration Mode Bit. A 0 here selects self-calibration, and a 1 selects a system calibration (see Table IV).
2 CALSLT1 Calibration Selection Bits and Start Calibration Bit. These bits have two functions.
1 CALSLT0 With the STCAL bit set to 1 the CALSLT1 and CALSLT0 bits determine the type of calibration per
0 STCAL formed by the part (see Table IV). The STCAL bit is automatically reset to 0 at the end of calibration.
With the STCAL bit set to 0 the CALSLT1 and CALSLT0 bits are decoded to address the calibration
register for read/write of calibration coefficients (see section on the Calibration Registers for more details).

–10– REV. B
 AD7858/AD7858L
Table III. Channel Selection

SGL/DIFF CH2 CH1 CH0 AIN(+)* AIN(–)*

0 0 0 0 AIN1 AIN2
0 0 0 1 AIN3 AIN4
0 0 1 0 AIN5 AIN6
0 0 1 1 AIN7 AIN8
0 1 0 0 AIN2 AIN1
0 1 0 1 AIN4 AIN3
0 1 1 0 AIN6 AIN5
0 1 1 1 AIN8 AIN7
1 0 0 0 AIN1 AGND
1 0 0 1 AIN3 AGND
1 0 1 0 AIN5 AGND
1 0 1 1 AIN7 AGND
1 1 0 0 AIN2 AGND
1 1 0 1 AIN4 AGND
1 1 1 0 AIN6 AGND
1 1 1 1 AIN8 AGND
*AIN(+) refers to the positive input seen by the AD7858/AD7858L sample and hold circuit,
*AIN(–) refers to the negative input seen by the AD7858/AD7858L sample and hold circuit.

Table IV. Calibration Selection

CALMD CALSLT1 CALSLT0 Calibration Type

0 0 0 A Full Internal Calibration is initiated where the Internal DAC is calibrated
followed by the Internal Gain Error, and finally the Internal Offset Error is
calibrated out. This is the default setting.
0 0 1 Here the Internal Gain Error is calibrated out followed by the Internal Offset
Error calibrated out.
0 1 0 This calibrates out the Internal Offset Error only.
0 1 1 This calibrates out the Internal Gain Error only.
1 0 0 A Full System Calibration is initiated here where first the Internal DAC is
calibrated followed by the System Gain Error, and finally the System Offset
Error is calibrated out.
1 0 1 Here the System Gain Error is calibrated out followed by the System Offset
Error.
1 1 0 This calibrates out the System Offset Error only.
1 1 1 This calibrates out the System Gain Error only.

REV. B –11–
AD7858/AD7858L
STATUS REGISTER
The arrangement of the Status Register is shown below. The status register is a read-only register and contains 16 bits of data. The
status register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the bits
in the status register are described below. The power-up status of all bits is 0.

START

WRITE TO CONTROL REGISTER

SETTING RDSLT0 = RDSLT1 = 1

READ STATUS REGISTER

Figure 6. Flowchart for Reading the Status Register

MSB
ZERO BUSY SGL/DIFF CH2 CH1 CH0 PMGT1 PMGT0

RDSLT1 RDSLT0 2/3 MODE X CALMD CALSLT1 CALSLT0 STCAL

LSB

STATUS REGISTER BIT FUNCTION DESCRIPTION

Bit Mnemonic Comment

15 ZERO This bit is always 0.
14 BUSY Conversion/Calibration Busy Bit. When this bit is 1, it indicates that there is a conversion
or calibration in progress. When this bit is 0, there is no conversion or calibration in progress.
13 SGL/DIFF These four bits indicate the channel selected for conversion (see Table III).
12 CH2
11 CH1
10 CH0
9 PMGT1 Power management bits. These bits along with the SLEEP pin will indicate if the part is in a
8 PMGT0 power-down mode or not. See Table VI for description.
7 RDSLT1 Both of these bits are always 1, indicating it is the status register being read (see Table II).
6 RDSLT0
5 2/3 MODE Interface Mode Select Bit. With this bit at 0, the device is in Interface Mode 2. With this bit at
1, the device is in Interface Mode 1. This bit is reset to 0 after every read cycle.
4 X Don’t care bit.
3 CALMD Calibration Mode Bit. A 0 in this bit indicates a self-calibration is selected, and a 1 in this bit
indicates a system calibration is selected (see Table IV).
2 CALSLT1 Calibration Selection Bits and Start Calibration Bit. The STCAL bit is read as a 1 if a
1 CALSLT0 calibration is in progress and as a 0 if there is no calibration in progress. The CALSLT1 and
0 STCAL CALSLT0 bits indicate which of the calibration registers are addressed for reading and writing
(see section on the Calibration Registers for more details).

–12– REV. B
 AD7858/AD7858L
CALIBRATION REGISTERS
The AD7858/AD7858L has 10 calibration registers in all, eight for the DAC, one for the offset, and one for gain. Data can be written
to or read from all 10 calibration registers. In self- and system calibration the part automatically modifies the calibration registers; only if the
user needs to modify the calibration registers should an attempt be made to read from and write to the calibration registers.
Addressing the Calibration Registers
The calibration selection bits in the control register CALSLT1 and CALSLT0 determine which of the calibration registers are ad-
dressed (see Table V). The addressing applies to both the read and write operations for the calibration registers. The user should not
attempt to read from and write to the calibration registers at the same time.

Table V. Calibration Register Addressing

CALSLT1 CALSLT0 Comment

0 0 This combination addresses the Gain (1), Offset (1) and DAC Registers (8). Ten registers in total.
0 1 This combination addresses the Gain (1) and Offset (1) Registers. Two registers in total.
1 0 This combination addresses the Offset Register. One register in total.
1 1 This combination addresses the Gain Register. One register in total.

Writing to/Reading from the Calibration Registers When reading from the calibration registers there will always be
For writing to the calibration registers a write to the control two leading zeros for each of the registers. When operating in
register is required to set the CALSLT0 and CALSLT1 bits. Serial Interface Mode 1 the read operations to the calibration
For reading from the calibration registers a write to the control registers cannot be aborted. The full number of read operations
register is required to set the CALSLT0 and CALSLT1 bits, must be completed (see section on Serial Interface Mode 1
but also to set the RDSLT1 and RDSLT0 bits to 10 (this ad- Timing for more detail).
dresses the calibration registers for reading). The calibration
register pointer is reset on writing to the control register setting
START
the CALSLT1 and CALSLT0 bits, or upon completion of all
the calibration register write/read operations. When reset it
points to the first calibration register in the selected write/read WRITE TO CONTROL REGISTER SETTING STCAL = 0
AND CALSLT1, CALSLT0 = 00, 01, 10, 11
sequence. The calibration register pointer will point to the gain
calibration register upon reset in all but one case, this case being
CAL REGISTER POINTER IS
where the offset calibration register is selected on its own AUTOMATICALLY RESET
(CALSLT1 = 1, CALSLT0 = 0). Where more than one calibra-
tion register is being accessed the calibration register pointer will
WRITE TO CAL REGISTER
be automatically incremented after each calibration register (ADDR1 = 1, ADDR0 = 0)
write/read operation. The order in which the 10 calibration
registers are arranged is shown in Figure 7. The user may abort
CAL REGISTER POINTER IS
at any time before all the calibration register write/read opera- AUTOMATICALLY INCREMENTED
tions are completed, and the next control register write opera-
tion will reset the calibration register pointer. The flow chart in
Figure 8 shows the sequence for writing to the calibration regis- LAST
REGISTER
ters and Figure 9 for reading. WRITE NO
OPERATION
OR
CALIBRATION REGISTERS ABORT
?
CAL REGISTER
ADDRESS POINTER GAIN REGISTER (1) YES
OFFSET REGISTER (2)

DAC 1ST MSB REGISTER (3) FINISHED

CALIBRATION REGISTER . . .
ADDRESS POINTER . . .
POSITION IS DETERMINED . . .
Figure 8. Flowchart for Writing to the Calibration Registers
BY THE NUMBER OF . . .
CALIBRATION REGISTERS . . .
ADDRESSED AND THE . . .
NUMBER OF READ/WRITE . . .
OPERATIONS
DAC 8TH MSB REGISTER (10)

Figure 7. Calibration Register Arrangements

REV. B –13–
AD7858/AD7858L
START
Q. If a +20 mV offset is present in the analog input signal and the
reference voltage is 2.5 V what code needs to be written to the
offset register to compensate for the offset?
WRITE TO CONTROL REGISTER SETTING STCAL = 0, RDSLT1 = 1,
RDSLT0 = 0, AND CALSLT1, CALSLT0 = 00, 01, 10, 11 A. 2.5 V reference implies that the resolution in the offset regis-
ter is 5% × 2.5 V/213 = 0.015 mV. +20 mV/0.015 mV =
CAL REGISTER POINTER IS
1310.72; rounding to the nearest number gives 1311. In
AUTOMATICALLY RESET binary terms this is 0101 0001 1111. Therefore, decrease the
offset register by 0101 0001 1111.
READ CAL REGISTER This method of compensating for offset in the analog input
signal allows for fine tuning the offset compensation. If the
offset on the analog input signal is known, there will be no need
CAL REGISTER POINTER IS
AUTOMATICALLY INCREMENTED to apply the offset voltage to the analog input pins and do a
system calibration. The offset compensation can take place in
software.
LAST Adjusting the Gain Calibration Register
REGISTER
READ NO The gain calibration register contains 16 bits, two leading 0s
OPERATION
OR and 14 data bits. The data bits are binary weighted as in the
ABORT
?
offset calibration register. The gain register value is effectively
multiplied by the analog input to scale the conversion result
YES
over the full range. Increasing the gain register compensates for
FINISHED a smaller analog input range and decreasing the gain register
compensates for a larger input range. The maximum analog
Figure 9. Flowchart for Reading from the Calibration input range that the gain register can compensate for is 1.025
Registers times the reference voltage, and the minimum input range is
0.975 times the reference voltage.
Adjusting the Offset Calibration Register
The offset calibration register contains 16 bits, two leading zeros,
and 14 data bits. By changing the contents of the offset register
different amounts of offset on the analog input signal can be
compensated for. Increasing the number in the offset calibration
register compensates for negative offset on the analog input
signal, and decreasing the number in the offset calibration regis-
ter compensates for positive offset on the analog input signal.
The default value of the offset calibration register is 0010 0000
0000 0000 approximately. This is not an exact value, but the
value in the offset register should be close to this value. Each of
the 14 data bits in the offset register is binary weighted; the
MSB has a weighting of 5% of the reference voltage, the MSB-1
has a weighting of 2.5%, the MSB-2 has a weighting of 1.25%,
and so on down to the LSB which has a weighting of 0.0006%.
This gives a resolution of ± 0.0006% of VREF approximately.
More accurately the resolution is ± (0.05 × VREF )/213 volts =
± 0.015 mV, with a 2.5 V reference. The maximum offset that
can be compensated for is ± 5% of the reference voltage, which
equates to ± 125 mV with a 2.5 V reference and ± 250 mV with
a 5 V reference.

–14– REV. B
 AD7858/AD7858L
CIRCUIT INFORMATION conversion will take 17.5 CLKIN periods. The maximum speci-
The AD7858/AD7858L is a fast, 12-bit single supply A/D con- fied conversion time is 4.6 µs for the AD7858 (18tCLKIN,
verter. The part requires an external 4 MHz/1.8 MHz master CLKIN = 4 MHz) and 10 µs for the AD7858L (18tCLKIN,
clock (CLKIN), two CREF capacitors, a CONVST signal to start CLKIN = 1.8 MHz). When a conversion is completed, the
conversion, and power supply decoupling capacitors. The part BUSY output goes low, and then the result of the conversion
provides the user with track/hold, on-chip reference, calibration can be read by accessing the data through the serial interface.
features, A/D converter, and serial interface logic functions on a To obtain optimum performance from the part, the read opera-
single chip. The A/D converter section of the AD7858/AD7858L tion should not occur during the conversion or 400 ns prior to
consists of a conventional successive-approximation converter the next CONVST rising edge. However, the maximum
based around a capacitor DAC. The AD7858/AD7858L accepts throughput rates are achieved by reading/writing during conver-
an analog input range of 0 to +VDD where the reference can be sion, and reading/writing during conversion is likely to degrade
tied to VDD. The reference input to the part is buffered on-chip. the Signal to (Noise + Distortion) by only 0.5 dBs. The AD7858
A major advantage of the AD7858/AD7858L is that a conversion can operate at throughput rates up to 200 kHz, 100 kHz for the
can be initiated in software as well as applying a signal to the AD7858L. For the AD7858 a conversion takes 18 CLKIN
CONVST pin. Another innovative feature of the AD7858/ periods; 2 CLKIN periods are needed for the acquisition time
AD7858L is self-calibration on power-up, which is initiated giving a full cycle time of 5 µs (= 200 kHz, CLKIN = 4 MHz).
having a capacitor from the CAL pin to AGND, to give superior For the AD7858L 100 kHz throughput can be obtained as
dc accuracy. See Automatic Calibration on Power-Up section. follows: the CLKIN and CONVST signals are arranged to give
The part is available in a 24-pin SSOP package and this offers a conversion time of 16.5 CLKIN periods as described above,
the user considerable space-saving advantages over alternative 1.5 CLKIN periods are allowed for the acquisition time. This
solutions. The AD7858L version typically consumes only gives a full cycle time of 10 µs (=100 kHz, CLKIN = 1.8 MHz).
5.5 mW making it ideal for battery-powered applications. When using the software conversion start for maximum through-
put the user must ensure the control register write operation
CONVERTER DETAILS extends beyond the falling edge of BUSY. The falling edge of
The master clock for the part must be applied to the CLKIN BUSY resets the CONVST bit to 0 and allows it to be repro-
pin. Conversion is initiated on the AD7858/AD7858L by pulsing grammed to 1 to start the next conversion.
the CONVST input or by writing to the control register and
setting the CONVST bit to 1. On the rising edge of CONVST TYPICAL CONNECTION DIAGRAM
(or at the end of the control register write operation), the on- Figure 10 shows a typical connection diagram for the AD7858/
chip track/hold goes from track to hold mode. The falling edge AD7858L. The AGND and the DGND pins are connected
of the CLKIN signal that follows the rising edge of the CONVST together at the device for good noise suppression. The CAL pin
signal initiates the conversion, provided the rising edge of has a 0.01 µF capacitor to enable an automatic self-calibration
CONVST occurs at least 10 ns typically before this CLKIN on power-up. The conversion result is output in a 16-bit word
edge. The conversion cycle will take 16.5 CLKIN periods from with four leading zeros followed by the MSB of the 12-bit result.
this CLKIN falling edge. If the 10 ns setup time is not met, the Note that after the AVDD and DVDD power-up the part will

4MHz/1.8MHz OSCILLATOR

200kHz/100kHz PULSE GENERATOR

MASTER CLOCK
ANALOG SUPPLY INPUT
+3V TO +5V 10␮F 0.1␮F 0.1␮F
CONVERSION
START INPUT
AVDD DVDD
CLKIN OSCILLOSCOPE
0V TO 2.5V AIN(+)
INPUT
AIN(–) SCLK CH1
SERIAL CLOCK
CREF1 INPUT
0.1␮F CONVST CH2
CREF2 AD7858/
0.01␮F SYNC CH3
AD7858L FRAME SYNC INPUT
DVDD SLEEP DIN CH4
CAL SERIAL DATA INPUT
0.01␮F DOUT CH5
AGND SERIAL DATA
OUTPUT
AUTO CAL ON DGND
POWER-UP
INTERNAL/ 4 LEADING
DATA GENERATOR ZEROS FOR
0.1␮F EXTERNAL
ADC DATA
REFERENCE

OPTIONAL
AD780/
EXTERNAL PULSE GENERATOR
REF-192
REFERENCE

Figure 10. Typical Circuit

REV. B –15–
AD7858/AD7858L
require approximately 150 ms for the internal reference to settle For ac applications, removing high frequency components from
and for the automatic calibration on power-up to be completed. the analog input signal is recommended by use of an RC low-
For applications where power consumption is a major concern pass filter on the AIN(+) pin as shown in Figure 13. In applica-
then the SLEEP pin can be connected to DGND. See Power- tions where harmonic distortion and signal to noise ratio are
Down section for more detail on low power applications. critical the analog input should be driven from a low impedance
source. Large source impedances will significantly affect the ac
ANALOG INPUT performance of the ADC. This may necessitate the use of an
The equivalent circuit of the analog input section is shown in input buffer amplifier. The choice of the op amp will be a func-
Figure 11. During the acquisition interval the switches are both tion of the particular application.
in the track position and the AIN(+) charges the 20 pF capacitor When no amplifier is used to drive the analog input the source
through the 125 Ω resistance. On the rising edge of CONVST impedance should be limited to low values. The maximum
switches SW1 and SW2 go into the hold position retaining source impedance will depend on the amount of total harmonic
charge on the 20 pF capacitor as a sample of the signal on distortion (THD) that can be tolerated. The THD will increase
AIN(+). The AIN(–) is connected to the 20 pF capacitor, and as the source impedance increases and performance will de-
this unbalances the voltage at node A at the input of the com- grade. Figure 12 shows a graph of the total harmonic distortion
parator. The capacitor DAC adjusts during the remainder of the versus analog input signal frequency for different source imped-
conversion cycle to restore the voltage at node A to the correct ances. With the setup as in Figure 13, the THD is at the –90 dB
value. This action transfers a charge, representing the analog level. With a source impedance of 1 kΩ and no capacitor on the
input signal, to the capacitor DAC which in turn forms a digital AIN(+) pin, the THD increases with frequency.
representation of the analog input signal. The voltage on the
AIN(–) pin directly influences the charge transferred to the –72
capacitor DAC at the hold instant. If this voltage changes dur- THD vs. FREQUENCY FOR DIFFERENT
SOURCE IMPEDANCES
ing the conversion period, the DAC representation of the analog
–76
input voltage will be altered. Therefore it is most important that
the voltage on the AIN(–) pin remains constant during the conver- RIN = 1k⍀
sion period. Furthermore it is recommended that the AIN(–) –80
THD – dB

pin is always connected to AGND or to a fixed dc voltage.

Acquisition Time –84
The track and hold amplifier enters its tracking mode on the RIN = 50⍀, 10nF
falling edge of the BUSY signal. The time required for the track AS IN FIGURE 13

and hold amplifier to acquire an input signal will depend on –88

how quickly the 20 pF input capacitance is charged. The acqui-
sition time is calculated using the formula:
–92
0 20 40 60 80 100
tACQ = 9 × (RIN + 125 Ω) × 20 pF INPUT FREQUENCY – kHz

where RIN is the source impedance of the input signal, and Figure 12. THD vs. Analog Input Frequency
125 Ω, 20 pF is the input R, C.
In a single supply application (both 3 V and 5 V), the V+ and
125⍀ TRACK
V– of the op amp can be taken directly from the supplies to the
AIN(+) AD7858/AD7858L which eliminates the need for extra external
AIN(–) SW1 power supplies. When operating with rail-to-rail inputs and
125⍀ HOLD
CAPACITOR outputs, at frequencies greater than 10 kHz care must be taken
20pF DAC
in selecting the particular op amp for the application. In particu-
NODE A lar for single supply applications the input amplifiers should be
connected in a gain of –1 arrangement to get the optimum per-
SW2 formance. Figure 13 shows the arrangement for a single supply
COMPARATOR
TRACK HOLD
application with a 50 Ω and 10 nF low-pass filter (cutoff fre-
CREF2 quency 320 kHz) on the AIN(+) pin. Note that the 10 nF is a
capacitor with good linearity to ensure good ac performance.
Figure 11. Analog Input Equivalent Circuit
Recommended single supply op amps are the AD820 and the
DC/AC Applications AD820-3 V.
For dc applications high source impedances are acceptable
provided there is enough acquisition time between conversions +3V TO +5V
10␮F 0.1␮F
to charge the 20 pF capacitor. The acquisition time can be 10k⍀

calculated from the above formula for different source imped- VIN 10k⍀
V+
ances. For example with RIN = 5 kΩ, the required acquisition (0 TO VREF) 50⍀ TO AIN(+) OF
10k⍀ AD7858/AD7858L
time will be 922 ns. VREF 10nF
V+ AD820 (NPO)
10k⍀ AD820-3V

Figure 13. Analog Input Buffering

–16– REV. B
 AD7858/AD7858L
Input Range REFERENCE SECTION
The analog input range for the AD7858/AD7858L is 0 V to For specified performance, it is recommended that when using
VREF. The AIN(–) pin on the AD7858/AD7858L can be biased an external reference this reference should be between 2.3 V
up above AGND, if required. The advantage of biasing the and the analog supply AVDD. The connections for the relevant
lower end of the analog input range away from AGND is that reference pins are shown in the typical connection diagrams. If
the user does not need to have the analog input swing all the the internal reference is being used, the REFIN/REFOUT pin
way down to AGND. This has the advantage in true single- should have a 100 nF capacitor connected to AGND very close
supply applications that the input amplifier does not need to to the REFIN/REFOUT pin. These connections are shown in
swing all the way down to AGND. The upper end of the analog Figure 16.
input range is shifted up by the same amount. Care must be If the internal reference is required for use external to the ADC,
taken so that the bias applied does not shift the upper end of the it should be buffered at the REFIN/REFOUT pin and a 100 nF
analog input above the AVDD supply. In the case where the connected from this pin to AGND. The typical noise performance
reference is the supply, AVDD, the AIN(–) must be tied to for the internal reference, with 5 V supplies, is 150 nV/√Hz @
AGND. 1 kHz and dc noise is 100 µV p-p.

TRACK AND HOLD ANALOG SUPPLY

AIN(+) AMPLIFIER +3V TO +5V
VIN = 0 TO VREF 10␮F 0.1␮F 0.1␮F
DOUT STRAIGHT
AIN(–) BINARY
FORMAT
AVDD DVDD
AD7858/ CREF1
0.1␮F
AD7858L
AD7858/
CREF2 AD7858L
Figure 14. 0 to VREF Input Configuration 0.01␮F
Transfer Function
For the AD7858/AD7858L input range the designed code tran- REFIN/REFOUT
0.1␮F
sitions occur midway between successive integer LSB values
(i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs . . . FS – 3/2 LSBs). The
output coding is straight binary with 1 LSB = FS/4096 = 3.3 V/
4096 = 0.8 mV when VREF = 3.3 V. The ideal input/output Figure 16. Relevant Connections When Using Internal
transfer characteristic is shown in Figure 15. Reference
The other option is that the REFIN/REFOUT pin be overdriven
OUTPUT
CODE by connecting it to an external reference. This is possible due to
111...111 the series resistance from the REFIN/REFOUT pin to the internal
111...110
reference. This external reference can have a range that includes
AVDD. When using AVDD as the reference source, the 100 nF
111...101
capacitor from the REFIN/REFOUT pin to AGND should be as
111...100
close as possible to the REFIN/REFOUT pin, and also the CREF1
pin should be connected to AVDD to keep this pin at the same
level as the reference. The connections for this arrangement are
shown in Figure 17. When using AVDD it may be necessary to
000...011
add a resistor in series with the AVDD supply. This will have the
1LSB = FS effect of filtering the noise associated with the AVDD supply.
000...010 4096

000...001 ANALOG SUPPLY

+3V TO +5V
000...000 10␮F 0.1␮F 0.1␮F
0V 1LSB +FS –1LSB
VIN = (AIN(+) – AIN(–)), INPUT VOLTAGE
AVDD DVDD
Figure 15. AD7858/AD7858L Transfer Characteristic CREF1
0.1␮F

AD7858/
CREF2 AD7858L
0.01␮F

REFIN/REFOUT
0.1␮F

Figure 17. Relevant Connections When Using AVDD as the

Reference

REV. B –17–
AD7858/AD7858L
PERFORMANCE CURVES –78
Figure 18 shows a typical FFT plot for the AD7858 at 200 kHz AVDD = DVDD = 3.3V/5.0V,
100mVp-p SINE WAVE ON AVDD
sample rate and 10 kHz input frequency. –80

0
–82
AVDD = DVDD = 3.3V

PSRR – dB
fSAMPLE = 200kHz
–20 3.3V
fIN = 10kHz
–84
SNR = 72.04dB
THD = –88.43dB
–40
–86
SNR – dB

5.0V
–60
–88

–80
–90
0 20 40 60 80 100
INPUT FREQUENCY – kHz
–100
Figure 20. PSRR vs. Frequency
–120
0 20 40 60 80 100
POWER-DOWN OPTIONS
FREQUENCY – kHz
The AD7858 provides flexible power management to allow the
Figure 18. FFT Plot user to achieve the best power performance for a given through-
Figure 19 shows the SNR vs. Frequency for different supplies put rate. The power management options are selected by
and different external references. programming the power management bits, PMGT1 and PMGT0,
in the control register and by use of the SLEEP pin. Table VI
74 summarizes the power-down options that are available and how
AVDD = DVDD WITH 2.5V REFERENCE
UNLESS STATED OTHERWISE
they can be selected by using either software, hardware, or a
combination of both. The AD7858 can be fully or partially
73
powered down. When fully powered down, all the on-chip cir-
5.0V SUPPLIES, WITH 5V REFERENCE cuitry is powered down and IDD is 1 µA typ. If a partial power-
S(N+D) RATIO – dB

72 5.0V SUPPLIES
down is selected, then all the on-chip circuitry except the reference
is powered down and IDD is 400 µA typ. The choice of full or par-
5.0V SUPPLIES, L VERSION tial power-down does not give any significant improvement in
71 throughput with a power-down between conversions. This is
discussed in the next section–Power-Up Times. However, a
3.3V SUPPLIES partial power-down does allow the on-chip reference to be used
70
externally even though the rest of the AD7858 circuitry is pow-
ered down. It also allows the AD7858 to be powered up faster
69 after a long power-down period when using the on-chip refer-
0 20 40 60 80 100 ence (See Power-Up Times–Using On-Chip Reference).
INPUT FREQUENCY – kHz
When using the SLEEP pin, the power management bits PMGT1
Figure 19. SNR vs. Frequency
and PMGT0 should be set to zero (default status on power-up).
Figure 20 shows the Power Supply Rejection Ratio vs. Fre- Bringing the SLEEP pin logic high ensures normal operation,
quency for the part. The Power Supply Rejection Ratio is de- and the part does not power down at any stage. This may be
fined as the ratio of the power in adc output at frequency f to necessary if the part is being used at high throughput rates when
the power of a full-scale sine wave. it is not possible to power down between conversions. If the user
PSRR (dB) = 10 log (Pf/Pfs) wishes to power down between conversions at lower throughput
rates (i.e. <100 kSPS for the AD7858) to achieve better power
Pf = Power at frequency f in adc output, Pfs = power of a performances, then the SLEEP pin should be tied logic low.
full-scale sine wave. Here a 100 mV peak-to-peak sine wave is
coupled onto the AVDD supply while the digital supply is left If the power-down options are to be selected in software only,
unaltered. Both the 3.3 V and 5.0 V supply performances are then the SLEEP pin should be tied logic high. By setting the
shown. power management bits PMGT1 and PMGT0 as shown in
Table VI, a Full Power-Down, Full Power-Up, Full Power-
Down Between Conversions, and a Partial Power-Down Be-
tween Conversions can be selected.

–18– REV. B
 AD7858/AD7858L
Table VI. Power Management Options a logic high. If the autocalibration is disabled, then the user must
take into account the time required by the AD7858 to power-up
PMGT1 PMGT0 SLEEP before a self-calibration is carried out. This power-up time is the
Bit Bit Pin Comment time taken for the AD7858 to power up when power is first
0 0 0 Full Power-Down if Not applied (300 µs) typ) or the time it takes the external reference
Calibrating or Converting to settle to the 12-bit level–whichever is the longer.
(Default Condition The AD7858 powers up from a full hardware or software
After Power-On) power-down in 5 µs typ. This limits the throughput which the
0 0 1 Normal Operation part is capable of to 104 kSPS for the AD7858 operating with a
0 1 X Normal Operation 4 MHz CLK and 66 kSPS for the AD7858L with a 1.8 MHz
(Independent of the SLEEP Pin) CLK when powering down between conversions. Figure 22
1 0 X Full Power-Down shows how power-down between conversions is implemented
1 1 X Partial Power-Down if Not using the CONVST pin. The user first selects the power-down
Converting between conversions option by using the SLEEP pin and the
power management bits, PMGT1 and PMGT0, in the control
A typical connection diagram for a low power application is register, (see last section). In this mode the AD7858 automati-
shown in Figure 21 (AD7858L is the low power version of the cally enters a full power-down at the end of a conversion, i.e.,
AD7858). when BUSY goes low. The falling edge of the next CONVST
pulse causes the part to power up. Assuming the external refer-
CURRENT,
I = 1.5mA
ence is left powered up, the AD7858 should be ready for normal
ANALOG
TYP 0.1␮F 1.8MHz
OSCILLATOR
operation 5 µs after this falling edge. The rising edge of CONVST
SUPPLY
+3V 10␮F 0.1␮F initiates a conversion so the CONVST pulse should be at least
5 µs wide. The part automatically powers down on completion
of the conversion.
MASTER
AVDD DVDD CLOCK 100kHz
0V TO 2.5V INPUT PULSE START CONVERSION ON RISING EDGE
AIN(+) CLKIN GENERATOR
INPUT POWER-UP ON FALLING EDGE
AIN(–)
AD7858/ 5␮s
CREF1
AD7858L
0.1␮F CONVERSION
START INPUT CONVST
CONVST
tCONVERT
CREF2 SERIAL CLOCK
0.01␮F INPUT
SCLK BUSY
AUTO POWER
DOWN AFTER
SLEEP SYNC POWER-UP NORMAL FULL POWER-UP
CONVERSION
TIME OPERATION POWER-DOWN TIME
LOW
CAL SERIAL DATA POWER
0.01␮F
OUTPUT ␮C/␮P Figure 22. Power-Up Timing When Using CONVST Pin
DOUT
AUTO CAL
ON AGND SERIAL DATA NOTE: Where the software CONVST is used or automatic full
POWER-UP INPUT
DGND DIN power-down, the part must be powered up in software with an
REFIN /REFOUT extra write setting PMGT1 = 0 and PMGT0 = 1 before a con-
version is initiated in the next write. Automatic partial power-
INTERNAL
REFERENCE down after a calibration is not possible; the part must be
0.1␮F powered down manually. If software calibrations are to be used
when operating in the partial power-down mode, then three
OPTIONAL
REF192 EXTERNAL
separate writes are required. The first initiates the type of cali-
REFERENCE bration required, the second write powers the part down into
partial power-down mode, while the third write powers the part
Figure 21. Typical Low Power Circuit
up again before the next calibration command is issued.
POWER-UP TIMES Using the Internal (On-Chip) Reference
Using an External Reference As in the case of an external reference, the AD7858 can power-
When the AD7858 is powered up, the part is powered up from up from one of two conditions, power-up after the supplies are
one of two conditions. First, when the power supplies are ini- connected or power-up from hardware/software power-down.
tially powered up and, secondly, when the part is powered up When using the on-chip reference and powering up when AVDD
from either a hardware or software power-down (see last section). and DVDD are first connected, it is recommended that the power-
up calibration mode be disabled as explained above. When using
When AVDD and DVDD are powered up, the AD7858 should be
the on-chip reference, the power-up time is effectively the time
left idle for approximately 32 ms (4 MHz CLK) to allow for the
it takes to charge up the external capacitor on the REFIN/REFOUT
autocalibration if a 10 nF cap is placed on the CAL pin, (see
pin. This time is given by the equation:
Calibration section). During power-up the functionality of the
SLEEP pin is disabled, i.e., the part will not power down until tUP = 9 × R × C
the end of the calibration if SLEEP is tied logic low. The auto- where R ≅ 150 kΩ and C = external capacitor.
calibration on power-up can be disabled if the CAL pin is tied to

REV. B –19–
AD7858/AD7858L
The recommended value of the external capacitor is 100 nF; 10
this gives a power-up time of approximately 135 ms before a
calibration is initiated and normal operation should commence. AD7858 (4MHz CLK)
When CREF is fully charged, the power-up time from a hardware
or software power-down reduces to 5 µs. This is because an 1

POWER – mW
internal switch opens to provide a high impedance discharge
path for the reference capacitor during power-down—see Figure
23. An added advantage of the low charge leakage from the
AD7858L (1.8MHz CLK)
reference capacitor during power-down is that even though the
0.1
reference is being powered down between conversions, the
reference capacitor holds the reference voltage to within
0.5 LSBs with throughput rates of 100 samples/second and
over with a full power-down between conversions. A high input
impedance op amp like the AD707 should be used to buffer this 0.01
0 5 10 15 20 25 30 35 40 45 50
reference capacitor if it is being used externally. Note, if the THROUGHPUT – kSPS
AD7858 is left in its power-down state for more than 100 ms,
Figure 24. Power vs. Throughput Rate
the charge on CREF will start to leak away and the power-up
time will increase. If this long power-up time is a problem, the
CALIBRATION SECTION
user can use a partial power-down for the last conversion so the
Calibration Overview
reference remains powered up.
The automatic calibration that is performed on power-up en-
sures that the calibration options covered in this section will not
be required in a significant amount of applications. The user
SWITCH OPENS
DURING POWER-DOWN AD7858 will not have to initiate a calibration unless the operating condi-
REFIN/REFOUT tions change (CLKIN frequency, analog input mode, reference
ON-CHIP
REFERENCE voltage, temperature, and supply voltages). The AD7858/
EXTERNAL
CAPACITOR AD7858L have a number of calibration features that may be
TO OTHER required in some applications and there are a number of advan-
BUF
CIRCUITRY tages in performing these different types of calibration. First,
the internal errors in the ADC can be reduced significantly to
give superior dc performance, and secondly, system offset and
Figure 23. On-Chip Reference During Power-Down gain errors can be removed. This allows the user to remove
reference errors (whether it be internal or external reference)
POWER VS. THROUGHPUT RATE and to make use of the full dynamic range of the AD7858/
The main advantage of a full power-down after a conversion is AD7858L by adjusting the analog input range of the part for a
that it significantly reduces the power consumption of the part specific system.
at lower throughput rates. When using this mode of operation,
There are two main calibration modes on the AD7858/AD7858L,
the AD7858 is only powered up for the duration of the conver-
self-calibration and system calibration. There are various op-
sion. If the power-up time of the AD7858 is taken to be 5 µs
tions in both self-calibration and system calibration as outlined
and it is assumed that the current during power-up is 4 mA typ,
previously in Table IV. All the calibration functions can be
then power consumption as a function of throughput can easily
initiated by pulsing the CAL pin or by writing to the control
be calculated. The AD7858 has a conversion time of 4.6 µs
register and setting the STCAL bit to one. The timing diagrams
with a 4 MHz external clock. This means the AD7858 con-
that follow involve using the CAL pin.
sumes 4 mA typ, (or 12 mW typ VDD = 3 V) for 9.6 µs in every
conversion cycle if the device is powered down at the end of a The duration of each of the different types of calibrations is
conversion. If the throughput rate is 1 kSPS, the cycle time is given in Table VIII for the AD7858 with a 4 MHz master clock.
1000 µs and the average power dissipated during each cycle is These calibration times are master clock dependent. Therefore,
(9.6/1000) × (12 mW) = 115 µW. The graph, Figure 24, shows the calibrating times for the AD7858L (CLKIN = 1.8 MHz)
the power consumption of the AD7858 as a function of through- will be longer than those quoted in Table VIII.
put. Table VII lists the power consumption for various through-
put rates. Table VIII. Calibration Times (AD7858 with 4 MHz CLKIN)

Table VII. Power Consumption vs. Throughput Type of Self- or

System Calibration Time
Throughput Rate Power Full 31.25 ms
1 kSPS 115 µW Offset + Gain 6.94 ms
10 kSPS 1.15 mW Offset 3.47 ms
Gain 3.47 ms

–20– REV. B
 AD7858/AD7858L
Automatic Calibration on Power-On For the self- (gain + offset), self-offset, and self-gain calibrations
The CAL pin has a 0.15 µA pull-up current source connected the BUSY line will be triggered high by the rising edge of the
to it internally to allow for an automatic full self-calibration on CAL signal (or the end of the write to the control register if
power-on. A full self-calibration will be initiated on power-on if calibration is initiated in software) and will stay high for the
a capacitor is connected from the CAL pin to DGND. The full duration of the self-calibration. The length of time that
internal current source connected to the CAL pin charges up the BUSY is high will depend on the type of self-calibration
the external capacitor and the time required to charge the exter- that is initiated. Typical figures are given in Table VIII. The
nal capacitor will depend on the size of the capacitor itself. This timing diagrams for the other self-calibration options will be
time should be large enough to ensure that the internal refer- similar to that outlined in Figure 25.
ence is settled before the calibration is performed. A 33 nF
capacitor is sufficient to ensure that the internal reference has t1 = 100ns MIN,
settled (see Power-Up Times) before a calibration is initiated t15 = 2.5 tCLKIN MAX,
taking into account trigger level and current source variations tCAL = 125013 tCLKIN
t1
on the CAL pin. However, if an external reference is being
used, this reference must have stabilized before the automatic CAL (I/P)
calibration is initiated (a larger capacitor on the CAL pin t15
should be used if the external reference has not settled when the
autocalibration is initiated). Once the capacitor on the CAL pin BUSY (O/P)
has charged, the calibration will be performed which will take
tCAL
32 ms (4 MHz CLKIN). Therefore the autocalibration should
be complete before operating the part. After calibration, the Figure 25. Timing Diagram for Full Self-Calibration
part is accurate to the 12-bit level and the specifications quoted
System Calibration Description
on the data sheet apply. There will be no need to perform
System calibration allows the user to take out system errors
another calibration unless the operating conditions change or
external to the AD7858/AD7858L as well as calibrate the errors
unless a system calibration is required.
of the AD7858/AD7858L itself. The maximum calibration
Self-Calibration Description range for the system offset errors is ± 5% of VREF and for the
There are four different calibration options within the self- system gain errors is ± 2.5% of VREF. This means that the maxi-
calibration mode. First, there is a full self-calibration where the mum allowable system offset voltage applied between the
DAC, internal gain, and internal offset errors are calibrated out. AIN(+) and AIN(–) pins for the calibration to adjust out this
Then, there is the (Gain + Offset) self-calibration which cali- error is ± 0.05 × VREF (i.e., the AIN(+) can be 0.05 × VREF above
brates out the internal gain error and then the internal offset AIN(–) or 0.05 × VREF below AIN(–)). For the System gain error
errors. The internal DAC is not calibrated here. Finally, there the maximum allowable system full-scale voltage that can be
are the self-offset and self-gain calibrations which calibrate out applied between AIN(+) and AIN(–) for the calibration to
the internal offset errors and the internal gain errors respectively. adjust out this error is VREF ± 0.025 × VREF ( i.e., the AIN(+)
The internal capacitor DAC is calibrated by trimming each of above AIN(–)). If the system offset or system gain errors are
the capacitors in the DAC. It is the ratio of these capacitors to outside the ranges mentioned the system calibration algorithm
each other that is critical, and so the calibration algorithm en- will reduce the errors as much as the trim range allows.
sures that this ratio is at a specific value by the end of the cali- Figures 26 through 28 illustrate why a specific type of system
bration routine. For the offset and gain there are two separate calibration might be used. Figure 26 shows a system offset
capacitors, one of which is trimmed when an offset or gain calibration (assuming a positive offset) where the analog input
calibration is performed. Again, it is the ratio of these capacitors range has been shifted upwards by the system offset after the
to the capacitors in the DAC that is critical and the calibration system offset calibration is completed. A negative offset may
algorithm ensures that this ratio is at a specified value for both also be accounted for by a system offset calibration.
the offset and gain calibrations.
The zero-scale error is adjusted for an offset calibration, and MAX SYSTEM FULL SCALE
IS ⴞ2.5% FROM VREF
the positive full-scale error is adjusted for a gain calibration.
VREF + SYS OFFSET
Self-Calibration Timing VREF –1LSB VREF – 1LSB

The diagram of Figure 25 shows the timing for a full self- ANALOG
SYSTEM OFFSET ANALOG
INPUT
calibration. Here the BUSY line stays high for the full length of INPUT
RANGE
RANGE
the self-calibration. A self-calibration is initiated by bringing the CALIBRATION

CAL pin low (which initiates an internal reset) and then high SYS OFFSET SYS OFFSET
AGND AGND
again or by writing to the control register and setting the STCAL
MAX SYSTEM OFFSET MAX SYSTEM OFFSET
bit to 1 (note that if the part is in a power-down mode the CAL pulse- IS ⴞ5% OF VREF IS ⴞ5% OF VREF
width must take account of the power-up time ). The BUSY line is
triggered high from the rising edge of CAL (or the end of the Figure 26. System Offset Calibration
write to the control register if calibration is initiated in soft-
ware), and BUSY will go low when the full self-calibration is
complete after a time tCAL as shown in Figure 25.

REV. B –21–
AD7858/AD7858L
Figure 27 shows a system gain calibration (assuming a system system (gain + offset) calibrations will be sufficient. If the sys-
full scale greater than the reference voltage) where the analog tem errors are large (close to the specified limits of the calibra-
input range has been increased after the system gain calibration tion range) three system (gain + offset) calibrations may be
is completed. A system full-scale voltage less than the reference required to reduced the offset and gain errors to at least the 12-
voltage may also be accounted for by a system gain calibration. bit level. There will never be any need to perform more than
three system (offset + gain) calibrations.
MAX SYSTEM FULL SCALE MAX SYSTEM FULL SCALE
IS ⴞ2.5% FROM VREF IS ⴞ2.5% FROM VREF The zero scale error is adjusted for an offset calibration and the
SYS F.S. SYS F.S.
positive full-scale error is adjusted for a gain calibration.
VREF – 1LSB VREF – 1LSB
System Calibration Timing
SYSTEM GAIN
ANALOG ANALOG The calibration timing diagram in Figure 29 is for a full system
INPUT INPUT
RANGE RANGE calibration where the falling edge of CAL initiates an internal
CALIBRATION
reset before starting a calibration (note that if the part is in power-
AGND AGND
down mode the CAL pulsewidth must take account of the power-up
Figure 27. System Gain Calibration time). If a full system calibration is to be performed in software
Finally in Figure 28 both the system offset and gain are ac- it is easier to perform separate gain and offset calibrations so
counted for by the a system offset followed by a system gain that the CONVST bit in the control register does not have to be
calibration. First the analog input range is shifted upwards by programmed in the middle of the system calibration sequence.
the positive system offset and then the analog input range is The rising edge of CAL starts calibration of the internal DAC
adjusted at the top end to account for the system full scale. and causes the BUSY line to go high. If the control register is
set for a full system calibration, the CONVST must be used
MAX SYSTEM FULL SCALE MAX SYSTEM FULL SCALE also. The full-scale system voltage should be applied to the
IS ⴞ2.5% FROM VREF IS ⴞ2.5% FROM VREF analog input pins from the start of calibration. The BUSY line
SYS F.S. VREF + SYS OFFSET will go low once the DAC and System Gain Calibration are
VREF –1LSB SYS F.S.
VREF – 1LSB complete. Next the system offset voltage is applied to the AIN
SYSTEM OFFSET
CALIBRATION pin for a minimum setup time (tSETUP) of 100 ns before the
ANALOG
INPUT
FOLLOWED BY ANALOG
INPUT rising edge of the CONVST and remain until the BUSY signal
RANGE RANGE goes low. The rising edge of the CONVST starts the system
SYSTEM GAIN offset calibration section of the full system calibration and also
CALIBRATION
SYS OFFSET SYS OFFSET
causes the BUSY signal to go high. The BUSY signal will go
AGND AGND
low after a time tCAL2 when the calibration sequence is com-
MAX SYSTEM OFFSET MAX SYSTEM OFFSET
IS ⴞ5% OF VREF IS ⴞ5% OF VREF plete. In some applications not all the input channels may be
used. In this case it may be useful to dedicate two input chan-
Figure 28. System (Gain + Offset) Calibration nels for the system calibration, one which has the system offset
System Gain and Offset Interaction voltage applied to it, and one which has the system full scale
The inherent architecture of the AD7858/AD7858L leads to an voltage applied to it. When a system offset or gain calibration is
interaction between the system offset and gain errors when a performed, the channel selected should correspond to the sys-
system calibration is performed. Therefore, it is recommended tem offset or system full-scale voltage channel.
to perform the cycle of a system offset calibration followed by a The timing for a system (gain + offset) calibration is very similar
system gain calibration twice. Separate system offset and system to that of Figure 29 the only difference being that the time tCAL1
gain calibrations reduce the offset and gain errors to at least the will be replaced by a shorter time of the order of tCAL2 as the
12-bit level. By performing a system offset CAL first and a internal DAC will not be calibrated. The BUSY signal will
system gain calibration second, priority is given to reducing the signify when the gain calibration is finished and when the part is
gain error to zero before reducing the offset error to zero. If the ready for the offset calibration.
system errors are small, a system offset calibration would be
performed, followed by a system gain calibration. If the system t1 = 100ns MIN, t14 = 50/90ns MIN 5V/3V,
errors are large (close to the specified limits of the calibration t15 = 2.5 tCLKIN MAX, tCAL1 = 111114 tCLKIN,
range), this cycle would be repeated twice to ensure that the tCAL2 = 13899 tCLKIN

offset and gain errors were reduced to at least the 12-bit level. t1
The advantage of doing separate system offset and system gain CAL (I/P)
calibrations is that the user has more control over when the t15
analog inputs need to be at the required levels, and the BUSY (O/P)
CONVST signal does not have to be used. tCAL1 tCAL2
Alternatively, a system (gain + offset) calibration can be t16
performed. It is recommended to perform three system (gain + CONVST (I/P)

offset) calibrations to reduce the offset and gain errors to the tSETUP
12-bit level. For the system (gain + offset) calibration priority is AIN (I/P) VSYSTEM FULL SCALE VOFFSET
given to reducing the offset error to zero before reducing the
gain error to zero. Thus if the system errors are small then two Figure 29. Timing Diagram for Full System Calibration

–22– REV. B
 AD7858/AD7858L
The timing diagram for a system offset or system gain calibra- Resetting the Serial Interface
tion is shown in Figure 30. Here again the CAL is pulsed and When writing to the part via the DIN line there is the possibility
the rising edge of the CAL initiates the calibration sequence (or of writing data into the incorrect registers, such as the test regis-
the calibration can be initiated in software by writing to the ter for instance, or writing the incorrect data and corrupting the
control register). The rising edge of the CAL causes the BUSY serial interface. The SYNC pin acts as a reset. Bringing the
line to go high and it will stay high until the calibration se- SYNC pin high resets the internal shift register. The first data
quence is finished. The analog input should be set at the correct bit after the next SYNC falling edge will now be the first bit of a
level for a minimum setup time (tSETUP) of 100 ns before the rising new 16-bit transfer. It is also possible that the test register con-
edge of CAL and stay at the correct level until the BUSY signal tents were altered when the interface was lost. Therefore, once
goes low. the serial interface is reset it may be necessary to write the 16-bit
word 0100 0000 0000 0010 to restore the test register to its
t1 default value. Now the part and serial interface are completely
CAL (I/P) reset. It is always useful to retain the ability to program the
SYNC line from a port of the µController/DSP to have the
t15
ability to reset the serial interface.
BUSY (O/P) Table X summarizes the interface modes provided by the
tCAL2 AD7858/AD7858L. It also outlines the various µP/µC to which
tSETUP
the particular interface is suited.
VSYSTEM FULL SCALE OR VSYSTEM OFFSET
AIN (I/P) Interface Mode 1 may only be set by programming the control
register (see section on Control Register).
Figure 30. Timing Diagram for System Gain or System
Offset Calibration Some of the more popular µProcessors, µControllers, and the
DSP machines that the AD7858/AD7858L will interface to
SERIAL INTERFACE SUMMARY directly are mentioned here. This does not cover all µCs, µPs,
Table IX details the two interface modes and the serial clock and DSPs. A more detailed timing description on each of the
edges from which the data is clocked out by the AD7858/ interface modes follows.
AD7858L (DOUT Edge) and that the data is latched in on
(DIN Edge). Table X. Interface Mode Description
In both interface Modes 1 and 2 the SYNC is gated with the Interface ␮Processor/
SCLK. Thus the SYNC↓ may clock out the MSB of data. Sub- Mode ␮Controller Comment
sequent bits will be clocked out by the Serial Clock, SCLK. The
condition for the SYNC↓ clocking out the MSB of data is as 1 8XC51 (2-Wire)
follows: 8XL51 (DIN Is an Input/
PIC17C42 Output Pin)
The falling edge of SYNC will clock out the MSB if the serial clock
is low when the SYNC goes low. 2 68HC11 (3-Wire, SPI)
68L11 (Default Mode)
If this condition is not the case, the SCLK will clock out the
68HC16
MSB. If a noncontinuous SCLK is used, it should idle high.
PIC16C64
ADSP21xx
Table IX. SCLK Active Edges
DSP56000
Interface Mode DSP56001
Edge DOUT Edge DIN DSP56002
DSP56L002
1, 2 SCLK↓ SCLK↑

REV. B –23–
AD7858/AD7858L
DETAILED TIMING SECTION automatically revert back to an input after a time, t14. Note that
Mode 1 (2-Wire 8051 Interface) a continuous SCLK shown by the dotted waveform in Figure 35
The read and writing takes place on the DIN line and the con- can be used provided that the SYNC is low for only 16 clock
version is initiated by pulsing the CONVST pin (note that in pulses in each of the read and write cycles.
every write cycle the 2/3 MODE bit must be set to 1). The In Figure 32 the SYNC line is tied low permanently and this
conversion may be started by setting the CONVST bit in the results in a different timing arrangement. With SYNC tied low
control register to 1 instead of using the CONVST pin. permanently the DIN pin will never be three-stated. The 16th
Below in Figure 31 and in Figure 32 are the timing diagrams for rising edge of SCLK configures the DIN pin as an input or an
Operating Mode 1 in Table X where we are in the 2-wire inter- output as shown in the diagram. Here no more than 16 SCLK
face mode. Here the DIN pin is used for both input and output pulses must occur for each of the read and write operations.
as shown. The SYNC input is level triggered active low and can If reading from and writing to the calibration registers in this
be pulsed (Figure 31) or can be constantly low (Figure 32). interface mode, all the selected calibration registers must be
In Figure 31 the part samples the input data on the rising edge read from or written to. The read and write operations cannot
of SCLK. After the 16th rising edge of SCLK the DIN is con- be aborted. When reading from the calibration registers, the
figured as an output. When the SYNC is taken high the DIN is DIN pin will remain as an output for the full duration of all the
three-stated. Taking SYNC low disables the three-state on the calibration register read operations. When writing to the calibra-
DIN pin and the first SCLK falling edge clocks out the first data tion registers, the DIN pin will remain as an input for the full
bit. Once the 16 clocks have been provided the DIN pin will duration of all the calibration register write operations.

t3 = –0.4tSCLK MIN (NONCONTINUOUS SCLK) ⴞ0.4tSCLK ns MIN/MAX (CONTINUOUS SCLK),

t6 = 75/115ns MAX (5V/3V), t7 = 40/60ns MIN (5V/3V), t8 = 20/30ns MIN (5V/3V)
POLARITY PIN LOGIC HIGH

SYNC (I/P)

t11 t3 t11
t3

SCLK (I/P) 1 16 1 16
t5 t14
t7
t12 t6 t6
t8
DIN (I/O) DB15 DB0 DB15 DB0
THREE-STATE
DATA WRITE DATA READ

DIN BECOMES AN OUTPUT DIN BECOMES AN INPUT

Figure 31. Timing Diagram for Read/Write Operation with DIN as an Input/Output
(i.e., Mode 1)

t6 = 75/115ns MAX (5V/3V), t7 = 40/60ns MIN (5V/3V), t8 = 20/30ns MIN (5V/3V),

t13 = 90/130ns MAX (5V/3V), t14 = 50/90ns MIN (5V/3V)
POLARITY PIN LOGIC HIGH

SCLK (I/P) 1 16 1 6 16

t7 t14
t13 t6 t6
t8
DIN (I/O) DB15 DB0 DB15 DB0

DATA WRITE DATA READ

DIN BECOMES AN INPUT

Figure 32. Timing Diagram for Read/Write Operation with DIN as an Input/Output
and SYNC Input Tied Low (i.e., Interface Mode 1)

–24– REV. B
 AD7858/AD7858L
Mode 2 (3-Wire SPI/QSPI Interface Mode) SYNC going low disables the three-state on the DOUT pin.
This is the DEFAULT INTERFACE MODE. The first falling edge of the SCLK after the SYNC going low
In Figure 33 below we have the timing diagram for interface clocks out the first leading zero on the DOUT pin. The DOUT
Mode 2 which is the SPI/QSPI interface mode. Here the SYNC pin is three-stated again a time t12 after the SYNC goes high.
input is active low and may be pulsed or tied permanently low. With the DIN pin the data input has to be set up a time t7 be-
If SYNC is permanently low, 16 clock pulses must be applied to fore the SCLK rising edge as the part samples the input data on
the SCLK pin for the part to operate correctly, otherwise with a the SCLK rising edge in this case. If resetting the interface is
pulsed SYNC input a continuous SCLK may be applied pro- required, the SYNC must be taken high and then low.
vided SYNC is low for only 16 SCLK cycles. In Figure 33 the

t3 = –0.4tSCLK MIN (NONCONTINUOUS SCLK) ⴞ0.4tSCLK ns MIN/MAX (CONTINUOUS SCLK),

t6 = 75/115ns MAX (5V/3V), t7 = 40/60ns MIN (5V/3V), t8 = 20/30ns MIN (5V/3V),
POLARITY PIN LOGIC HIGH t11 = 30/50ns MIN (NONCONTINUOUS SCLK) (5V/3V), (30/50)/0.4tSCLK ns MIN/MAX
(CONTINUOUS SCLK) (5V/3V)

SYNC (I/P)

t11
t3 t9
SCLK (I/P) 1 2 3 4 5 6 16

t5 t10 t12
t6 t6
THREE-STATE THREE-STATE
DOUT (O/P) DB15 DB14 DB13 DB12 DB11 DB10 DB0

t7 t8
t8
DIN (I/P) DB15 DB14 DB13 DB12 DB11 DB10 DB0

Figure 33. SPI/QSPI Mode 2 Timing Diagram for Read/Write Operation

with DIN Input, DOUT Output, and SYNC Input

REV. B –25–
AD7858/AD7858L
CONFIGURING THE AD7858/AD7858L than one conversion. The options of using a hardware (pulsing
The AD7858/AD7858L contains 14 on-chip registers which can the CONVST pin) or software (setting the CONVST bit to 1)
be accessed via the serial interface. In the majority of applications it conversion start, and reading/writing during or after conversion
will not be necessary to access all of these registers. Here the are shown in Figures 34 and 35. If the CONVST pin is never
CLKIN signal is applied directly after power-on; the CLKIN used then it should be tied to DVDD permanently. Where refer-
signal must be present to allow the part to perform a calibration. ence is made to the BUSY bit equal to a Logic 0, to indicate the
This automatic calibration will be completed approximately 32 ms end of conversion, the user in this case would poll the BUSY bit
after the AD7858 has powered up (4 MHz CLK). in the status register.
For accessing the on-chip registers it is necessary to write to the Interface Mode 1 Configuration
part. To change the channel from the default channel setting Figure 34 shows the flowchart for configuring the part in Inter-
the user will be required to write to the part. To enable Serial face Mode 1. This mode of operation can only be enabled by
Interface Mode 1 the user must also write to the part. Figure 34 writing to the control register and setting the 2/3 MODE bit.
and 35 outline flowcharts of how to configure the AD7858/ Reading and writing cannot take place simultaneously in this
AD7858L Serial Interface Modes 1 and 2 respectively. The mode as the DIN pin is used for both reading and writing.
continuous loops on all diagrams indicate the sequence for more

START

POWER-ON, APPLY CLKIN SIGNAL,

WAIT FOR AUTOMATIC CALIBRATION

SERIAL
INTERFACE
MODE
?

INITIATE
YES CONVERSION
IN
SOFTWARE
?

NO

APPLY SYNC (IF REQUIRED), SCLK, WRITE APPLY SYNC (IF REQUIRED), SCLK,
TO CONTROL REGISTER SETTING CHANNEL WRITE TO CONTROL REGISTER
TWO-WIRE MODE SETTING CHANNEL AND TWO-WIRE MODE

WRITE
TO CONTROL REGISTER SETTING CONVST PULSE CONVST PIN
BIT TO 1 (SEE NOTE)

READ
YES DATA
DURING
CONVERSION
?

WAIT APPROX. 200ns AFTER

CONVST RISING EDGE OR AFTER END NO
OF CONTROL REGISTER WRITE
WAIT FOR BUSY SIGNAL TO GO LOW
OR
WAIT FOR BUSY BIT = 0
APPLY SYNC (IF REQUIRED), SCLK, READ
PREVIOUS CONVERSION RESULT ON DIN PIN

APPLY SYNC (IF REQUIRED), SCLK, READ

CURRENT CONVERSION RESULT ON DIN PIN

NOTE:
TWO SEPARATE WRITES ARE REQUIRED TO SET A NEW CHANNEL ADDRESS AND INITIATE A
CONVERSION ON THAT NEW CHANNEL IN SOFTWARE AS THE ACQUISITION TIME (2 tCLKIN)
MUST ELAPSE BEFORE THE CONVERSION BEGINS. IF BOTH COMMANDS ARE ISSUED IN THE ONE
WRITE THE RESULT OF THIS CONVERSION SHOULD BE DISCARDED AND THE NEXT
CONVERSION ON THAT SAME CHANNEL WILL PROVIDE CORRECT RESULTS.

Figure 34. Flowchart for Setting Up, Reading, and Writing in Interface Mode 1

–26– REV. B
 AD7858/AD7858L
Interface Mode 2 Configuration that no valid data is written to any of the registers. When using
Figure 35 shows the flowchart for configuring the part in Inter- the software conversion start and transferring data during con-
face Mode 2. In this case the read and write operations take version Note 1 must be obeyed.
place simultaneously via the serial port. Writing all 0s ensures

START

POWER-ON, APPLY CLKIN SIGNAL,

WAIT FOR AUTOMATIC CALIBRATION

SERIAL
INTERFACE
MODE
?

INITIATE
CONVERSION YES
IN
SOFTWARE
?

NO TRANSFER YES
DATA DURING
CONVERSION
PULSE CONVST PIN ?
APPLY SYNC (IF REQUIRED), SCLK, WRITE
TO CONTROL REGISTER SETTING CHANNEL,
(SEE NOTE 1)
NO

WRITE TO CONTROL REGISTER

TRANSFER APPLY SYNC (IF REQUIRED), SCLK, WRITE SETTING CONVST BIT TO 1,
YES TO CONTROL REGISTER SETTING CHANNEL
DATA DURING READ PREVIOUS RESULT ON
CONVERSION DOUT PIN (SEE NOTES 1&2)
?
WRITE TO CONTROL REGISTER SETTING
CONVST BIT TO 1, READ
WAIT APPROX 200ns AFTER NO CURRENT CONVERSION RESULT
CONVST RISING EDGE ON DOUT PIN (SEE NOTE 2)
WAIT FOR BUSY SIGNAL TO GO LOW
OR
WAIT FOR BUSY BIT = 0 WAIT FOR BUSY SIGNAL TO GO LOW
APPLY SYNC (IF REQUIRED), SCLK, READ
PREVIOUS CONVERSION RESULT ON DOUT OR
PIN, AND WRITE CHANNEL SELECTION WAIT FOR BUSY BIT = 0
APPLY SYNC (IF REQUIRED), SCLK,
READ CURRENT CONVERSION RESULT
ON DOUT PIN, AND WRITE CHANNEL
SELECTION

NOTES
1WHEN USING THE SOFTWARE CONVERSION START AND TRANSFERRING DATA DURING CONVERSION THE USER MUST ENSURE THE CONTROL REGISTER

WRITE OPERATION EXTENDS BEYOND THE FALLING EDGE OF BUSY. THE FALLING EDGE OF BUSY RESETS THE CONVST BIT TO 0 AND ONLY AFTER THIS
TIME CAN IT BE REPROGRAMMED TO 1 TO START THE NEXT CONVERSION.
2TWO SEPARATE WRITES ARE REQUIRED TO SET A NEW CHANNEL ADDRESS AND INITIATE A CONVERSION ON THAT NEW CHANNEL IN SOFTWARE AS

THE ACQUISITION TIME (2 tCLKIN) MUST ELAPSE BEFORE THE CONVERSION BEGINS. IF BOTH COMMANDS ARE ISSUED IN THE ONE WRITE THE
RESULT OF THIS CONVERSION SHOULD BE DISCARDED AND THE NEXT CONVERSION ON THAT SAME CHANNEL WILL PROVIDE CORRECT RESULTS.

Figure 35. Flowchart for Setting Up, Reading, and Writing in Interface Mode 2

REV. B –27–
AD7858/AD7858L
MICROPROCESSOR INTERFACING OPTIONAL
In many applications, the user may not require the facility of AD7858/AD7858L
4MHz/1.8MHz
CONVST
writing to most of the on-chip registers. The only writing neces- 8XC51/L51

sary is to set the input channel configuration. After this the MASTER CLKIN
CONVST is applied, a conversion is performed, and the result P3.1 SCLK SLAVE
may be read using the SCLK to clock out the data from the
P3.0 DIN
output register on to the DOUT pin. At the same time a write
operation occurs and this may consist of all 0s where no data is (INT0/P3.2)
OPTIONAL
BUSY

written to the part or may set a different input channel configu- SYNC
ration for the next conversion. The SCLK may be connected to
the CLKIN pin if the user does not want to have to provide
separate serial and master clocks. With this arrangement the Figure 37. 8XC51/PIC16C42 Interface
SYNC signal must be low for 16 SCLK cycles for the read and AD7858/AD7858L to 68HC11/16/L11/PIC16C42 Interface
write operations. Figure 38 shows the AD7858/AD7858L SPI/QSPI interface to
the 68HC11/16/L11/PIC16C42. The 68L11 is for interfacing to
the AD7858/AD7858L when the supply is 3 V. The AD7858/
CONVST CONVERSION START
AD7858L is in Interface Mode 2. The SYNC line is not used
4MHz/1.8MHz
CLKIN
MASTER CLOCK and is tied to DGND. The µController is configured as the mas-
SCLK
ter, by setting the MSTR bit in the SPCR to 1, and provides the
SYNC SIGNAL TO
AD7858/ GATE THE SCLK serial clock on the SCK pin. For all the µControllers the CPOL
SYNC
AD7858L bit is set to 1 and for the 68HC11/16/L11 the CPHA bit is set to
DIN SERIAL DATA INPUT
SERIAL DATA
1. The CLKIN and CONVST signals can be supplied from the
DOUT
OUTPUT µController or from separate sources. The BUSY signal can be
used as an interrupt to tell the µController when the conversion
Figure 36. Simplified Interface Diagram is finished, then the reading and writing can take place. If re-
quired the reading and writing can take place during conversion
AD7858/AD7858L to 8XC51 Interface and there will be no need for the BUSY signal in this case.
Figure 37 shows the AD7858/AD7858L interface to the
8XC51. The 8XL51 is for interfacing to the AD7858/AD7858L OPTIONAL
when the supply is at 3 V. The 8XC51 only runs at 5 V. The AD7858/AD7858L
4MHz/1.8MHz
8XC51 is in Mode 0 operation. This is a two-wire interface CONVST
DVDD
consisting of the SCLK and the DIN which acts as a bidirec- 68HC11/L11/16 CLKIN
SPI
tional line. The SYNC is tied low. The BUSY line can be used SS SYNC
to give an interrupt driven system but this would not normally HC16, QSPI SLAVE
SCK SCLK
be the case with the 8XC51. For the 8XC51 12 MHz version MASTER
MISO DOUT
the serial clock will run at a maximum of 1 MHz so the serial OPTIONAL
IRQ BUSY
interface of the AD7858/AD7858L will only be running at
1 MHz. The CLKIN signal must be provided separately to the MOSI DIN

AD7858/AD7858L from a port line on the 8XC51 or from a

source other than the 8XC51. Here the SCLK cannot be tied to Figure 38. 68HC11 and 68HC16 Interface
the CLKIN as the SYNC is tied low permanently. The CONVST
For the 68HC16 the word length should be set to 16 bits, and
signal can be provided from an external timer or conversion can
the SS line should be tied to the SYNC pin for the QSPI inter-
be started in software if required. The sequence of events would
face. The micro-sequencer and RAM associated with the
typically be to write to the control register via the DIN line setting
68HC16 QSPI port can be used to perform a number of read
a conversion start and the 2-wire interface mode (this would be
and write operations, and store the conversion results in
performed in two 8-bit writes), wait for the conversion to be
memory, independent of the CPU. This is especially useful when
finished (4.6 µs with 4 MHz CLKIN), read the conversion result
reading the conversion results from all eight channels consecu-
data on the DIN line (this would be performed in two 8-bits
tively. The command section of the QSPI port RAM would be
reads), and repeat the sequence. The maximum serial frequency
programmed to perform a conversion on one channel, read the
will be determined by the data access and hold times of the
conversion result, perform a conversion on the next channel,
8XC51 and the AD7858/AD7858L.
read the conversion result, and so on until all eight conversion
results are stored into the QSPI RAM.

–28– REV. B
 AD7858/AD7858L
A typical sequence of events would be to write to the control AD7858/AD7858L to DSP56000/1/2/L002 Interface
register via the DIN line setting a conversion start and at the Figure 40 shows the AD7858/AD7858L to DSP56000/1/2/
same time reading data from the previous conversion on the L002 interface. Here the DSP5600x is the master and the
DOUT line (both the read and write operations would each be AD7858 is the slave. The AD7858/AD7858L is in Interface
two 8-bit operations, one 16-bit operation for the 68HC16), Mode 2. The DSP56L002 is used when the AD7858/AD7858L
wait for the conversion to be finished (= 4.6 µs for AD7858 is being operated at 3 V. The setting of the bits in the registers
with 4 MHz CLKIN), and then repeat the sequence. The maxi- of the DSP5600x would be for synchronous operation (SYN =
mum serial frequency will be determined by the data access and 1), internal frame sync (SCD2 = 1), gated internal clock (GCK
hold times of the µControllers and the AD7858/AD7858L. = 1, SCKD = 1), 16-bit word length (WL1 = 1, WL0 = 0). Since
a gated clock is used here the SCLK cannot be tied to the CLKIN
AD7858/AD7858L to ADSP-21xx Interface
of the AD7858/AD7858L. The SCLK from the DSP5600x
Figure 39 shows the AD7858/AD7858L interface to the ADSP-
must be inverted before it is applied to the AD7858/AD7858L.
21xx. The ADSP-21xx is the master and the AD7858/AD7858L
Again the data access and hold times of the DSP5600x and
is the slave. The AD7858/AD7858L is in Interface Mode 2.
the AD7858/AD7858L allows for a SCLK of 4 MHz/1.8 MHz.
For the ADSP-21xx the bits in the serial port control register
should be set up as TFSR = RFSR = 1 (need a frame sync for OPTIONAL
every transfer), SLEN = 15 (16-bit word length), TFSW = AD7858/AD7858L
4MHz/1.8MHz
RFSW = 1 (alternate framing mode for transmit and receive CONVST
operations), INVRFS = INVTFS = 1 (active low RFS and DSP56000/1/2/L002
CLKIN
TFS), IRFS = 0, ITFS = 1 (External RFS and internal TFS),
SCK SCLK
and ISCLK = 1 (internal serial clock). The CLKIN and SLAVE
CONVST signals can be supplied from the ADSP-21xx or MASTER
SRD DOUT

from an external source. The serial clock from the ADSP-21xx SC2 SYNC
OPTIONAL
must be inverted before the SCLK pin of the AD7858/AD7858L. IRQ BUSY
This SCLK could also be used to drive the CLKIN input of the STD DIN
AD7858/AD7858L. The BUSY signal indicates when the con-
version is finished and may not be required. The data access Figure 40. DSP56000/1/2 Interface
and hold times of the ADSP-21xx and the AD7858/AD7858L
allow for a serial clock of 4 MHz/1.8 MHz at 5 V and 3.3 MHz/
1.8 MHz at 3 V supplies.

OPTIONAL
AD7858/AD7858L
CONVST
ADSP-21xx 4MHz/1.8MHz CLKIN
SCK SCLK

DR DOUT

RFS SYNC
MASTER
TFS SLAVE
OPTIONAL
IRQ BUSY
DT DIN

Figure 39. ADSP-21xx Interface

REV. B –29–
AD7858/AD7858L
APPLICATION HINTS Good decoupling is also important. All analog supplies should
Grounding and Layout be decoupled with 10 µF tantalum in parallel with 0.1 µF ca-
The analog and digital supplies to the AD7858/AD7858L are pacitors to AGND. All digital supplies should have a 0.1 µF
independent and separately pinned out to minimize coupling disc ceramic capacitor to AGND. To achieve the best from
between the analog and digital sections of the device. The part these decoupling components, they must be placed as close as
has very good immunity to noise on the power supplies as can possible to the device, ideally right up against the device. In
be seen by the PSRR vs. Frequency graph. However, care systems where a common supply voltage is used to drive both
should still be taken with regard to grounding and layout. the AVDD and DVDD of the AD7858/AD7858L, it is recom-
The printed circuit board that houses the AD7858/AD7858L mended that the system’s AVDD supply be used. In this case
should be designed such that the analog and digital sections are there should be a 10 Ω resistor between the AVDD pin and
separated and confined to certain areas of the board. This facili- DVDD pin. This supply should have the recommended analog
tates the use of ground planes that can be separated easily. A supply decoupling capacitors between the AVDD pin of the
minimum etch technique is generally best for ground planes as AD7858/AD7858L and AGND and the recommended digital
it gives the best shielding. Digital and analog ground planes supply decoupling capacitor between the DVDD pin of the
should only be joined in one place. If the AD7858/AD7858L is AD7858/AD7858L and DGND.
the only device requiring an AGND to DGND connection, Evaluating the AD7858/AD7858L Performance
then the ground planes should be connected at the AGND and The recommended layout for the AD7858/AD7858L is out-
DGND pins of the AD7858/AD7858L. If the AD7858/ lined in the evaluation board for the AD7858/AD7858L. The
AD7858L is in a system where multiple devices require AGND evaluation board package includes a fully assembled and tested
to DGND connections, the connection should still be made at evaluation board, documentation, and software for controlling
one point only, a star ground point which should be established the board from the PC via the EVAL-CONTROL BOARD.
as close as possible to the AD7858/AD7858L. The EVAL-CONTROL BOARD can be used in conjunction
Avoid running digital lines under the device as these will couple with the AD7858/AD7858L Evaluation board, as well as many
noise onto the die. The analog ground plane should be allowed other Analog Devices evaluation boards ending in the CB desig-
to run under the AD7858/AD7858L to avoid noise coupling. nator, to demonstrate/evaluate the ac and dc performance of the
The power supply lines to the AD7858/AD7858L should use as AD7858/AD7858L.
large a trace as possible to provide low impedance paths and The software allows the user to perform ac (fast Fourier trans-
reduce the effects of glitches on the power supply line. Fast form) and dc (histogram of codes) tests on the AD7858/
switching signals like clocks should be shielded with digital AD7858L. It also gives full access to all the AD7858/AD7858L
ground to avoid radiating noise to other sections of the board, on-chip registers allowing for various calibration and power-
and clock signals should never be run near the analog inputs. down options to be programmed.
Avoid crossover of digital and analog signals. Traces on oppo- AD785x Family
site sides of the board should run at right angles to each other. All parts are 12 bits, 200 kSPS, 3.0 V to 5.5 V.
This will reduce the effects of feedthrough through the board. A
microstrip technique is by far the best but is not always possible AD7853 – Single Channel Serial
with a double-sided board. In this technique, the component AD7854 – Single Channel Parallel
side of the board is dedicated to ground planes while signals are
AD7858 – Eight Channel Serial
placed on the solder side.
AD7859 – Eight Channel Parallel

–30– REV. B
 AD7858/AD7858L
PAGE INDEX
Topic Page No.
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Self-Calibration Description . . . . . . . . . . . . . . . . . . . . . . . 21
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 Self-Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . 1 System Calibration Description . . . . . . . . . . . . . . . . . . . . 21
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 System Gain and Offset Interaction . . . . . . . . . . . . . . . . . 22
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 4 System Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . 22
TYPICAL TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . 5 SERIAL INTERFACE SUMMARY . . . . . . . . . . . . . . . . . . 23
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6 Resetting The Serial Interface . . . . . . . . . . . . . . . . . . . . . 23
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DETAILED TIMING SECTION
PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Mode 1 (2-Wire 8051 Interface) . . . . . . . . . . . . . . . . . . . 24
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 7 Mode 2 (3-Wire SPI/QSPI Interface) . . . . . . . . . . . . . . . . 25
TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 CONFIGURING THE AD7858/AD7858L . . . . . . . . . . . . 26
ON-CHIP REGISTERS Interface Mode 1 Configuration . . . . . . . . . . . . . . . . . . . . 26
Addressing the On-Chip Registers . . . . . . . . . . . . . . . . . . . 9 Interface Mode 2 Configuration . . . . . . . . . . . . . . . . . . . . 27
CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 MICROPROCESSOR INTERFACING . . . . . . . . . . . . . . . 28
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AD7858/AD7858L–8XC51 Interface . . . . . . . . . . . . . . . 28
CALIBRATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . 13 AD7858/AD7858L–68HC11/16/L11/PIC16C42
Addressing the Calibration Registers . . . . . . . . . . . . . . . . 13 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Writing to/Reading from the Calibration Registers . . . . . . 13 AD7858/AD7858L–ADSP-21xx Interface . . . . . . . . . . . . 29
Adjusting the Offset Calibration Registers . . . . . . . . . . . . 14 AD7858/AD7858L–DSP56000/1/2/L002 Interface . . . . . 29
Adjusting the Gain Calibration Register . . . . . . . . . . . . . . 14 APPLICATION HINTS
CIRCUIT INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . 15 Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
CONVERTER DETAILS . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Evaluating the AD7858/AD7858L Performance . . . . . . . 30
TYPICAL CONNECTION DIAGRAM . . . . . . . . . . . . . . 15 INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
ANALOG INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 32
Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TABLE INDEX
DC/AC Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
# Title Page No.
Input Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table I. Write Register Addressing . . . . . . . . . . . . . . . . . 9
Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table II. Read Register Addressing . . . . . . . . . . . . . . . . . 9
REFERENCE SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table III. Channel Selection . . . . . . . . . . . . . . . . . . . . . . 11
PERFORMANCE CURVES . . . . . . . . . . . . . . . . . . . . . . . . 18
Table IV. Calibration Selection . . . . . . . . . . . . . . . . . . . . 11
POWER-DOWN OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . 18
Table V. Calibration Register Addressing . . . . . . . . . . . 13
POWER-UP TIMES
Table VI. Power Management Options . . . . . . . . . . . . . . 19
Using an External Reference . . . . . . . . . . . . . . . . . . . . . . 19
Table VII. Power Consumption vs. Throughput . . . . . . . 20
Using the Internal (On-Chip) Reference . . . . . . . . . . . . . 19
Table VIII. Calibration Times (AD7858 with 4 MHz
POWER VS. THROUGHPUT RATE . . . . . . . . . . . . . . . . 20
CLKIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
CALIBRATION SECTION
Table IX. SCLK Active Edges . . . . . . . . . . . . . . . . . . . . . 23
Calibration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table X. Interface Mode Description . . . . . . . . . . . . . . . 23
Automatic Calibration on Power-On . . . . . . . . . . . . . . . . 21

REV. B –31–
AD7858/AD7858L
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

24-Lead Plastic DIP (N-24)

1.228 (31.19)
1.226 (31.14)

24 13

C01337–0–6/00
0.260 ⴞ0.001
(6.61 ⴞ0.03)
1 12 0.32 (8.128)
0.30 (7.62)
PIN 1
0.130 (3.30)
0.128 (3.25)

15ⴗ
0.011 (0.28)
0.02 (0.5) 0.11 (2.79) 0.07 (1.78) SEATING 0
0.009 (0.23)
0.016 (0.41) 0.09 (2.28) 0.05 (1.27) PLANE

NOTES
1. LEAD NO. 1 IDENTIFIED BY A DOT OR NOTCH.
2. PLASTIC LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED
IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.

24-Lead Small Outline Package (R-24)

0.608 (15.45)
0.596 (15.13)

24 13
0.414 (10.52)
0.398 (10.10)
0.291 (7.39)
0.299 (7.6)

1 12

PIN 1 0.096 (2.44) 0.03 (0.76)

0.089 (2.26) 0.02 (0.51)

6ⴗ 0.042 (1.067)
0.01 (0.254) 0.05 0.019 (0.49) 0ⴗ 0.018 (0.447)
(1.27) SEATING
0.006 (0.15) 0.014 (0.35) PLANE 0.013 (0.32)
BSC
0.009 (0.23)
NOTES
1. LEAD NO. 1 IDENTIFIED BY A DOT.
2. SOIC LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED
IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.

24-Lead Shrink Small Outline Package (RS-24)

0.328 (8.33)
0.318 (8.08)

24 13
0.205 (5.207)
0.212 (5.38)
0.301 (7.64)
0.311 (7.9)

PRINTED IN U.S.A.
1 12

PIN 1 0.07 (1.78)

0.066 (1.67)

8ⴗ 0.037 (0.94)
0.008 (0.203) 0.0256 0.015 (0.38) 0ⴗ
SEATING 0.022 (0.559)
(0.65) 0.010 (0.25) PLANE 0.009 (0.229)
0.002 (0.050) BSC 0.005 (0.127)

NOTES
1. LEAD NO. 1 IDENTIFIED BY A DOT.
2. LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED
IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.

–32– REV. B