Lecture 1

Design and Technology Trends

R. Saleh
Dept. of ECE
University of British Columbia
res@ece.ubc.ca

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 Recently Designed Chips

• Itanium chip (Intel), 2B tx, 700mm2 , 8 layer 65nm

CMOS (4 processors)
• TILE64 Processor, 64-Core SoC with Mesh NoC
Interconnect, 90nm CMOS
• 153Mb-SRAM (Intel), 45nm, high-k metal-gate CMOS
• FPGAs recently fabricated in 45nm

• What are the major technology and design issues

that are driving the IC industry?
Let’s start from the simple rules of MOS scaling…

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 MOS Transistor Scaling
(1974 to present)

Scaling factor s=0.7 per node (0.5x per 2 nodes)

Metal pitch Technology Node

set by 1/2 pitch
(interconnect)

Poly width
Gate length
(transistor)

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 Ideal Technology Scaling (constant field)

Quantity Before Scaling After Scaling

Channel Length L L’ = L * s

Channel Width W W’ = W * s

Gate Oxide thickness tox t’ox = tox * s

Junction depth xj x’j = xj * s

Power Supply Vdd Vdd’ = Vdd * s

Threshold Voltage Vth V’th = Vth * s

Doping Density, p NA NA’ = NA / s

n+ ND ND’ = ND / s

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 Technology Nodes 1999-2019

1999 2001 2004 2007 2010 2013 2016 2019

0.7x 0.7x

180nm 130nm 90nm 65nm 45nm 32nm 22nm 16nm

0.5x
N-1 N N+1

Two year cycle between nodes until 2001, then 3 year cycle begins.

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 Forecast Technology Parameters

Year Technology Physical tox Dielec- Vdd Vth Na Nd xj

Node(nm) Gate(nm) (nm) tric K (V) (V) (/cm3) (/cm3) (nm)
2001 130 90 3.0 3.7 1.2 0.34 1.0e16 1.0e19 67.5
2004 90 53 2.4 3.0 1.1 0.32 1.4e16 1.4e19 46.7
2007 65 32 1.7 2.5 0.9 0.29 2.0e16 2.0e19 33.8
2010 45 22 1.5 2.0 0.8 0.29 2.9e16 2.9e19 23.4
2013 32 16 1.4 1.9 0.7 0.25 4.0e16 4.0e19 16.6
2016 22 11 1.3 1.7 0.6 0.22 5.9e16 5.9e19 11.4

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 Where are we now?

• 130nm and 90nm CMOS volume production

• Early production of 65nm, Leading-edge use of 45nm

• Scaling of gate is leading scaling of wire

• Scaling is driven by DIGITAL design needs

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 Making Photolithograph Work

• Extensive use of OPC and PSM in 90nm and below:

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 Deep Submicron Technology Generations

Table 1: Time overlap of semiconductor generations

95 96 97 98 99 00 01 02 03 04 05 06 07 08 09 10 11 12
350 1 2 3 4 5
nm
-2 -1 250 1 2 3 4 5
nm
-4 -3 -2 -1 180 1 2 3 4 5 6 7 8
nm
-6 -5 -4 -3 -2 -1 130 1 2 3 4 5 6
nm
-9 -8 -7 -6 -5 -4 -3 -2 -1 90 1 2 3 4 5
nm
-11 1-Univerisity
0 -9 -8 research
-7 -6 -5 Industry -2 -1 65
-4 -3 development 1 2 3
Production4 5
nm
-11 10
- -9 -8 -7 -6 -5 -4 -3 -2 -1 45 1 2
nm
11
- 10
- -9 -8 -7 -6 -5 -4 -3 -2 -1
-11 -10 -9 -8 -7 -6 -5 -4

Each generation spans ~17 years…we are unlikely to be totally suprised

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 MPU Trends - Moore’s Law

10,000 Transistors Double

Every Two Years
1000

100
100

Transistors 10
(MT) P6
Pentium® proc
1 486
386
0.1 286
2X Growth
8085 8086
0.01
in 2 Years!
8080
8008
0.001
4004

’70 ’80 ’90 ’00 ’10

Source: Intel

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 More MPU Trends

100 ~40mm Die in 2010?

40
36
28 32

Pentium® Pro proc

Die size
486 Pentium® proc
(mm) 10
386
286
8080 8086
8085
8008
4004
~7% growth per year

~2X growth in 10 years

1

’70 ’80 ’90 ’00 ’10

Source: Intel

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 Delay Metric - FO4 Concept

Use FO4 delay

1X 4X 16X
CIN Cload
as optimal delay

Delay vs Fanout

5 where γ is ratio of
4 γ=0.0
γ=0.5
Delay

3 Parasitic output
γ=1.0
2 γ=2.0
Capacitance to gate
1

0 capacitance
0 2 4 6 8
Fanout

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 FO4 INV Delay Scaling

For scaling purposes, the alpha-power model is very useful:

Idsat = K W Leff-0.5Tox-0.8 (Vgs -Vth)1.25
If L,Tox V all scale (note V scaling will be limited by Vth scaling),
Current should remains constant per micron of width (approx. 600 to 800uA/µm)
∆t’ = CV/i = s∆t since C, V, i all scale down by s
Fanout =4 inverter delay at TT, 90% Vdd, 125 oC
700
FO4 delay ≈ 425ps * Ldrawn
600
FO4 Gate delay ( pS)

500
400
300
200
100
0
1.2 1 0.8 0.6 0.4 0.2
Technology Ldrawn (um)
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 MPU Clock Frequency Trend

1000 Intel: Borkar/Parkhurst

100

80386
80486
Pentium
Pentium II

10
Dec-83 Dec-86 Dec-89 Dec-92 Dec-95 Dec-98

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 MPU Clock Frequency Trend

10000
Forward projection
may be too optimistic
P4
1000

100

80386
80486
Pentium
Pentium II

Expon.
10
Dec-83 Dec-86 Dec-89 Dec-92 Dec-95 Dec-98 Dec-99 Dec-00 Dec-01 Dec-02

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Intel: Borkar/Parkhurst
 MPU Clock Cycle Trend (FO4 Delays)

100.00 Intel: Borkar/Parkhurst

80386
80486
Pentium
Pentium II

10.00
Dec-83 Dec-86 Dec-89 Dec-92 Dec-95 Dec-98

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 MPU Clock Cycle Trend (FO4 Delays)

100.00

Forward projection
does not make sense

80386
80486
Pentium
Pentium II

Expon.
10.00
Dec-83 Dec-86 Dec-89 Dec-92 Dec-95 Dec-98 Dec-99 Dec-00 Dec-01 Dec-02

Intel: Borkar/Parkhurst Curve actually

flattens at 14-16 FO4
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 Power Trend - Ever Increasing

1000
ye ars
/3
x 1 .4
Power per chip [W]

100
rs
a
10 ye Processors
/3
x4 published
1
in ISSCC
0.1
MPU
DSP
0.01
1980 1985 1990 1995 2000 Year
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 Dynamic vs. Leakage Power

Dynamic Power
Leakage Power
Power (watts)

250nm 180nm 130nm 90nm 65nm

Technology Node
Krishnamurthy, et al., CICC 2002

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 Leakage Current Contributions

130nm 90nm 65nm

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 MPU Diminishing Returns

• Power knob running out

– Speed == Power
– 10W/cm2 limit for convection cooling, 50W/cm2 limit for forced-air cooling
– Large currents, large power surges on wakeup
– Cf. 125A supply current, 150W total power at 1.2V Vdd for EV8 (Compaq)
– die size will not continue to increase unless more memory is used to occupy
the additional area
– additional power dissipation coming from subthreshold leakage

• Speed knob running out

– Historically, 2x clock frequency every process generation
• 1.4x from device scaling
• 1.4x from pipelining, hence fewer logic stages (from 40-100 down to around 16 FO4
INV delays)
– Clocks cannot be generated with period < 6-8 FO4 INV delays
– Around 14-16 FO4 INV delays is limit for clock period
Unrealistic to continue 2x frequency trend!
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 Low-Power Design Techniques

• Supply Voltage Scaling

• Frequency Scaling
• Multiple Supply Voltages (Voltage Islands)
• Clock Gating
• Power Gating
• Multiple Threshold Voltages: LVT, SVT, HVT
• Substrate Biasing
• Power Shut Off
• HW/SW Power Management

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 Low-Power Application: PDA

0.18um / 400MHz / 470mW (typical)

MM Application
MP3 PWR CPG
PWM RTC Processor
JPEG
Simple Moving Picture FICP SSP CPU Area
Sound I2C GPIO I-cache D-cache 6.5MTrs.
Max 400MHz
USB USB OST 32KB 32KB
MMC MMC I2S DMA controller
Available Time MEM LCD
6-10Hr KEY UART AC97
Cnt. Cnt.
Data Transfer
Area
Peripheral Area SDRAM Flash LCD 100MHz
4 – 48MHz 64MB 32MB
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 Trends in Low-Power Design Content

• Today, such designs contain embedded processing engines

such as CPU and DSP, and memory blocks such as SRAM and
embedded DRAM
• As we scale technology and keep power constant how does the
amount of logic vs. memory change?
• Consider the following assumptions to develop trends for on-
chip logic/memory percentages
• Die size is 100mm2
• Clock frequency starts at 150MHz increases by about 40% per
technology node
• Average power dissipation in limited to 100mW at 100oC
• Initial condition at Year 2001: area percentage 75% logic, 25%
memory

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 Logic/Memory Content Trend

100%

Logic Area Contribution (%) LSTP

90%
Total Memory Area (%) LSTP

80%

70%
Percentage of Area (%)

60%

50%

40%

30%

20%

10%
Die Size = 1cm2

0%
2001 2004 2007 2010 2013 2016
Year

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 ASIC Logic/Memory Content Trends

• Source: Dataquest (2001)

ASIC Core Composition Breakout

60
Percentgae of Die Area

50
(I/Os Excluded)

Random Logic
40
Memory
30 Analog
20 Cores
10

0
1999 2000 2001

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 Design Trend: Productivity Gap

Year Technology Chip Complexity ASIC Frequency

1997 250 nm 50M Tr. 100MHz
1999 180 nm 150M Tr. 200MHz
2002 130 nm 250M Tr. 400MHz
2004 90 nm 500M Tr. 600MHz

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 Designing a 50M Transistor IC

• Gates Required ~12.5M

• Gates/Day (Verified) 1K (including memory)
• Total Eng. Days 12,500
• Total Eng. Years 35
• Cost/Eng./Year $200K
• Total People Cost $7M
• Other costs (masks, tools, etc.) $8M

Actual Cost is $10-15M to get actual prototypes after fabrication.

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 Productivity Gap

• Deep submicron (DSM) technology allows hundreds of millions

of transistors to be integrated on a single chip
• Number of transistors that a designer can design per day
(~1000 gates/day) is not going up significantly
• New design methodologies are needed to address the
integration/productivity issues
⇒ “System on a chip” Design with reusable IP
– new design methodology, IP development
– new HW/SW design and verification issues
– new test issues

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 SoC Design Hierarchy

SOC consists of new logic blocks and existing IP

New Logic blocks

Existing IP including memory

Each logic block can be implemented

by newly designed portion and a re-use
portion based on IPs
Newly designed portion

Re-use portion including memory

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 SoC Platform Design Concept
Pre-Qualified/Verified Foundation Block + Reference Design
Foundation-IP* Scaleable
bus, test, power, IO,
MEM clock, timing architectures

Application
Hardware IP Processor(s), RTOS(es)
Space CPU
FPGA and SW architecture
SW IP
Methodology / Flows:
Programmable IP System-level performance
evaluation environment
HW/SW Co-synthesis
SoC IC Design Flows
*IP can be hardware (digital SoC Verification Flow
or analog) or software. Foundry-Specific System-Level Performance
IP can be hard, soft or Pre-Qualification Evaluation
‘firm’ (HW), source or Rapid Prototype for
object (SW) End-Customer Evaluation
SoC Derivative Design
Methodologies
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 Purpose of this Course

• This course addresses SoC/IP design in DSM technologies

• It is a very broad subject, one that industry is grappling with on a
daily basis – one course cannot address all the issue properly
• The goal is to present an overview of the various issues from
“Systems to Silicon” to provide a perspective on what is
happening in technology and design.
• We will begin with the Systems Level and work our way down to
the Silicon Level
• The projects, presentations, and assignments will provide in-
depth analysis of the subjects that are of interest to you

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