Digital Systems: I. Number Representation and Arithmetic Circuits

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DIGITAL SYSTEMS

EXERCISE 2
I. Number Representation and Arithmetic Circuits
1. Represent each of the following signed decimal numbers in the 2’s-complement system. Use a total
eight bits, including the sign bit.
a. +35
b. -24
c. 128
d. -126

2. Each of the following numbers represents a signed decimal number in the 2’s-complement system.
Determine the decima value in each case.
a. 01101
b. 10011001
c. 11111111
d. 01100011

3. Add or subtract the following in binary.


a. 10111 + 110
b. 11.101 + 10.01
c. 011001 – 111010
d. 100110 – 100111

4. Add the following decimal numbers after converting each to its BCD code:
a. 34BCD + 24BCD
b. 25BCD + 35BCD
c. 762BCD + 348BCD
d. 599BCD + 984BCD

5. A certain data file is scattered at two places in the disk at addresses 104D 224F through 105F 1000 and
76EF 1122 through 76F0 FF23. If the data file is to be kept at continuous locations starting from F00F
0000, what should be the address of the end location?

6. Two 2’s-complement numbers having sign bits x and y are added, and the sign bit of the result is z.
Determine the Boolean function which indiciated the occurence of overflow.

7. Convert the Full Adder circuit to all NAND gates.

8. What is the difference between Carry-Look Ahead Adder and Ripple Carry Adder.

II. Register and Counter


9. A binary counter is being pulsed by a 8.192 MHz clock signal. The output frequency from the last FF is
4 KHz
a. Determine the MOD number
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b. Determine the counting range

10. Design a MOD-12 Asynchronous UP Counter using T Flip-Flops (PGT)

11. Design an asynchronous couter for the following count sequence using J-K Flip-Flops:
6543216…
12. Given the asynchronous counter as follows.

a. Determine modulus (MOD) of the counter


b. Determine output signals which have glitches
c. Determine the duty cycle of A,B,C,D

13. Design a 4-bit BCD synchronous counter using J-K Flip-flops

14. Design a synchronous counter for the following sequence using D Flip-Flops. Assume that 110, 010 are
the intial states.

III. MSI Logic Circuits


15. Derive the Boolean expression for output Q of the following MUX

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16. Derive the Boolean expression for input F of the following DEMUX

17. Given that X and Y are inputs, B and D are outputs, D is the difference of X – Y, and B is the borrow
bit. Design a Half-Subtractor circuit using 2-to-1 Multiplexers.

18. Given Y (A,B,C,D), D = MSB implemented by a IC 74151 as the following circuit. Determine the
Boolean function of Y

19. How many inputs will a decimal-to-BCD encoder have?

20. What is the number of inputs and outputs of a decoder that accept 128 different input combinations?

21. Design an octal-to-binary encoder

22. Show how to use IC 74138s to form a 1-of-16 decoder.

23. The following figure shows how a decoder can be used in the generation of control signals. Assume that
a RESET pulse has occurred at timt t0 and determine the CONTROL waveform for 10 clock pulses.

24. Design an 8-bit magnitude comparator using IC 74HC85s


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